// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1 (win64) Build 5076996 Wed May 22 18:37:14 MDT 2024
// Date        : Wed Oct 16 12:59:49 2024
// Host        : DESKTOP-1TRD5RL running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim c:/VNA_XDMA_REPO/src/ip/xdma_0/xdma_0_sim_netlist.v
// Design      : xdma_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a100tfgg484-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "xdma_0,xdma_0_core_top,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "xdma_0_core_top,Vivado 2024.1" *) 
(* NotValidForBitStream *)
module xdma_0
   (sys_clk,
    sys_rst_n,
    user_lnk_up,
    pci_exp_txp,
    pci_exp_txn,
    pci_exp_rxp,
    pci_exp_rxn,
    axi_aclk,
    axi_aresetn,
    usr_irq_req,
    usr_irq_ack,
    msi_enable,
    msi_vector_width,
    m_axi_awready,
    m_axi_wready,
    m_axi_bid,
    m_axi_bresp,
    m_axi_bvalid,
    m_axi_arready,
    m_axi_rid,
    m_axi_rdata,
    m_axi_rresp,
    m_axi_rlast,
    m_axi_rvalid,
    m_axi_awid,
    m_axi_awaddr,
    m_axi_awlen,
    m_axi_awsize,
    m_axi_awburst,
    m_axi_awprot,
    m_axi_awvalid,
    m_axi_awlock,
    m_axi_awcache,
    m_axi_wdata,
    m_axi_wstrb,
    m_axi_wlast,
    m_axi_wvalid,
    m_axi_bready,
    m_axi_arid,
    m_axi_araddr,
    m_axi_arlen,
    m_axi_arsize,
    m_axi_arburst,
    m_axi_arprot,
    m_axi_arvalid,
    m_axi_arlock,
    m_axi_arcache,
    m_axi_rready,
    cfg_mgmt_addr,
    cfg_mgmt_write,
    cfg_mgmt_write_data,
    cfg_mgmt_byte_enable,
    cfg_mgmt_read,
    cfg_mgmt_read_data,
    cfg_mgmt_read_write_done,
    cfg_mgmt_type1_cfg_reg_access,
    m_axib_awid,
    m_axib_awaddr,
    m_axib_awlen,
    m_axib_awsize,
    m_axib_awburst,
    m_axib_awprot,
    m_axib_awvalid,
    m_axib_awready,
    m_axib_awlock,
    m_axib_awcache,
    m_axib_wdata,
    m_axib_wstrb,
    m_axib_wlast,
    m_axib_wvalid,
    m_axib_wready,
    m_axib_bid,
    m_axib_bresp,
    m_axib_bvalid,
    cfg_aer_interrupt_msgnum_i,
    cfg_dsn_i,
    cfg_err_aer_headerlog_i,
    cfg_err_tlp_cpl_header_i,
    cfg_interrupt_di_i,
    cfg_mgmt_di_i,
    cfg_mgmt_dwaddr_i,
    cfg_pciecap_interrupt_msgnum_i,
    cfg_pm_force_state_i,
    cfg_turnoff_ok_i,
    fc_sel_i,
    m_axis_rx_tready_i,
    pl_directed_link_auton_i,
    pl_directed_link_change_i,
    pl_directed_link_speed_i,
    pl_directed_link_width_i,
    pl_upstream_prefer_deemph_i,
    rx_np_ok_i,
    rx_np_req_i,
    s_axis_tx_tdata_i,
    s_axis_tx_tkeep_i,
    s_axis_tx_tlast_i,
    s_axis_tx_tuser_i,
    s_axis_tx_tvalid_i,
    tx_cfg_gnt_i,
    cfg_bus_number_o,
    cfg_device_number_o,
    cfg_function_number_o,
    cfg_to_turnoff_o,
    m_axis_rx_tdata_o,
    m_axis_rx_tkeep_o,
    m_axis_rx_tlast_o,
    m_axis_rx_tuser_o,
    m_axis_rx_tvalid_o,
    Integrated_bloc_reset_o,
    s_axis_tx_tready_o,
    m_axib_bready,
    m_axib_arid,
    m_axib_araddr,
    m_axib_arlen,
    m_axib_arsize,
    m_axib_arburst,
    m_axib_arprot,
    m_axib_arvalid,
    m_axib_arready,
    m_axib_arlock,
    m_axib_arcache,
    m_axib_rid,
    m_axib_rdata,
    m_axib_rresp,
    m_axib_rlast,
    m_axib_rvalid,
    m_axib_rready);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SYS_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SYS_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input sys_clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.sys_rst_n RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.sys_rst_n, BOARD.ASSOCIATED_PARAM SYS_RST_N_BOARD_INTERFACE, TYPE PCIE_PERST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input sys_rst_n;
  output user_lnk_up;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt txp" *) output [1:0]pci_exp_txp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt txn" *) output [1:0]pci_exp_txn;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt rxp" *) input [1:0]pci_exp_rxp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt rxn" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME pcie_mgt, BOARD.ASSOCIATED_PARAM PCIE_BOARD_INTERFACE" *) input [1:0]pci_exp_rxn;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.axi_aclk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.axi_aclk, ASSOCIATED_BUSIF M_AXI:S_AXI_B:M_AXI_LITE:S_AXI_LITE:M_AXI_BYPASS:M_AXI_B:S_AXIS_C2H_0:S_AXIS_C2H_1:S_AXIS_C2H_2:S_AXIS_C2H_3:M_AXIS_H2C_0:M_AXIS_H2C_1:M_AXIS_H2C_2:M_AXIS_H2C_3:sc0_ats_m_axis_cq:sc0_ats_m_axis_rc:sc0_ats_s_axis_cc:sc0_ats_s_axis_rq:sc1_ats_m_axis_cq:sc1_ats_m_axis_rc:sc1_ats_s_axis_cc:sc1_ats_s_axis_rq:cxs_tx:cxs_rx:atspri_s_axis_rq:atspri_m_axis_cq, ASSOCIATED_RESET axi_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) output axi_aclk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.axi_aresetn RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output axi_aresetn;
  input [0:0]usr_irq_req;
  output [0:0]usr_irq_ack;
  output msi_enable;
  output [2:0]msi_vector_width;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input [3:0]m_axi_bid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input [3:0]m_axi_rid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [63:0]m_axi_rdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output [3:0]m_axi_awid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [63:0]m_axi_awaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [7:0]m_axi_awlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]m_axi_awburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output m_axi_awlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]m_axi_awcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [63:0]m_axi_wdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [7:0]m_axi_wstrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output m_axi_wlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output [3:0]m_axi_arid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [63:0]m_axi_araddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [7:0]m_axi_arlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]m_axi_arburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output m_axi_arlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]m_axi_arcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, SUPPORTS_NARROW_BURST 0, HAS_BURST 0, HAS_BURST.VALUE_SRC CONSTANT, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 4, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 256, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt ADDR" *) input [18:0]cfg_mgmt_addr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_EN" *) input cfg_mgmt_write;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_DATA" *) input [31:0]cfg_mgmt_write_data;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt BYTE_EN" *) input [3:0]cfg_mgmt_byte_enable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_EN" *) input cfg_mgmt_read;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_DATA" *) output [31:0]cfg_mgmt_read_data;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_WRITE_DONE" *) output cfg_mgmt_read_write_done;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt TYPE1_CFG_REG_ACCESS" *) input cfg_mgmt_type1_cfg_reg_access;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWID" *) output [3:0]m_axib_awid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWADDR" *) output [63:0]m_axib_awaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWLEN" *) output [7:0]m_axib_awlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWSIZE" *) output [2:0]m_axib_awsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWBURST" *) output [1:0]m_axib_awburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWPROT" *) output [2:0]m_axib_awprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWVALID" *) output m_axib_awvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWREADY" *) input m_axib_awready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWLOCK" *) output m_axib_awlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS AWCACHE" *) output [3:0]m_axib_awcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS WDATA" *) output [63:0]m_axib_wdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS WSTRB" *) output [7:0]m_axib_wstrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS WLAST" *) output m_axib_wlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS WVALID" *) output m_axib_wvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS WREADY" *) input m_axib_wready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS BID" *) input [3:0]m_axib_bid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS BRESP" *) input [1:0]m_axib_bresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS BVALID" *) input m_axib_bvalid;
  input [4:0]cfg_aer_interrupt_msgnum_i;
  input [63:0]cfg_dsn_i;
  input [127:0]cfg_err_aer_headerlog_i;
  input [47:0]cfg_err_tlp_cpl_header_i;
  input [7:0]cfg_interrupt_di_i;
  input [31:0]cfg_mgmt_di_i;
  input [9:0]cfg_mgmt_dwaddr_i;
  input [4:0]cfg_pciecap_interrupt_msgnum_i;
  input [1:0]cfg_pm_force_state_i;
  input cfg_turnoff_ok_i;
  input [2:0]fc_sel_i;
  input m_axis_rx_tready_i;
  input pl_directed_link_auton_i;
  input [1:0]pl_directed_link_change_i;
  input pl_directed_link_speed_i;
  input [1:0]pl_directed_link_width_i;
  input pl_upstream_prefer_deemph_i;
  input rx_np_ok_i;
  input rx_np_req_i;
  input [63:0]s_axis_tx_tdata_i;
  input [7:0]s_axis_tx_tkeep_i;
  input s_axis_tx_tlast_i;
  input [3:0]s_axis_tx_tuser_i;
  input s_axis_tx_tvalid_i;
  input tx_cfg_gnt_i;
  output [7:0]cfg_bus_number_o;
  output [4:0]cfg_device_number_o;
  output [2:0]cfg_function_number_o;
  output cfg_to_turnoff_o;
  output [63:0]m_axis_rx_tdata_o;
  output [7:0]m_axis_rx_tkeep_o;
  output m_axis_rx_tlast_o;
  output [21:0]m_axis_rx_tuser_o;
  output m_axis_rx_tvalid_o;
  output Integrated_bloc_reset_o;
  output s_axis_tx_tready_o;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS BREADY" *) output m_axib_bready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARID" *) output [3:0]m_axib_arid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARADDR" *) output [63:0]m_axib_araddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARLEN" *) output [7:0]m_axib_arlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARSIZE" *) output [2:0]m_axib_arsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARBURST" *) output [1:0]m_axib_arburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARPROT" *) output [2:0]m_axib_arprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARVALID" *) output m_axib_arvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARREADY" *) input m_axib_arready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARLOCK" *) output m_axib_arlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS ARCACHE" *) output [3:0]m_axib_arcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RID" *) input [3:0]m_axib_rid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RDATA" *) input [63:0]m_axib_rdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RRESP" *) input [1:0]m_axib_rresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RLAST" *) input m_axib_rlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RVALID" *) input m_axib_rvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_BYPASS RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_BYPASS, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, HAS_BURST 0, SUPPORTS_NARROW_BURST 0, NUM_READ_THREADS 2, NUM_WRITE_THREADS 2, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 4, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 256, PHASE 0.0, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axib_rready;

  wire \<const0> ;
  wire \<const1> ;
  wire axi_aclk;
  wire axi_aresetn;
  wire [4:0]cfg_aer_interrupt_msgnum_i;
  wire [7:0]cfg_bus_number_o;
  wire [4:0]cfg_device_number_o;
  wire [63:0]cfg_dsn_i;
  wire [127:0]cfg_err_aer_headerlog_i;
  wire [47:0]cfg_err_tlp_cpl_header_i;
  wire [2:0]cfg_function_number_o;
  wire [7:0]cfg_interrupt_di_i;
  wire [18:0]cfg_mgmt_addr;
  wire [3:0]cfg_mgmt_byte_enable;
  wire [31:0]cfg_mgmt_di_i;
  wire [9:0]cfg_mgmt_dwaddr_i;
  wire cfg_mgmt_read;
  wire [31:0]cfg_mgmt_read_data;
  wire cfg_mgmt_read_write_done;
  wire cfg_mgmt_type1_cfg_reg_access;
  wire cfg_mgmt_write;
  wire [31:0]cfg_mgmt_write_data;
  wire [4:0]cfg_pciecap_interrupt_msgnum_i;
  wire [1:0]cfg_pm_force_state_i;
  wire cfg_to_turnoff_o;
  wire cfg_turnoff_ok_i;
  wire [2:0]fc_sel_i;
  wire [63:0]m_axi_araddr;
  wire [1:0]m_axi_arburst;
  wire [3:0]m_axi_arcache;
  wire [3:0]m_axi_arid;
  wire [7:0]m_axi_arlen;
  wire m_axi_arlock;
  wire [2:0]m_axi_arprot;
  wire m_axi_arready;
  wire [2:0]m_axi_arsize;
  wire m_axi_arvalid;
  wire [63:0]m_axi_awaddr;
  wire [1:0]m_axi_awburst;
  wire [3:0]m_axi_awcache;
  wire [3:0]m_axi_awid;
  wire [7:0]m_axi_awlen;
  wire m_axi_awlock;
  wire [2:0]m_axi_awprot;
  wire m_axi_awready;
  wire [2:0]m_axi_awsize;
  wire m_axi_awvalid;
  wire [3:0]m_axi_bid;
  wire m_axi_bready;
  wire [1:0]m_axi_bresp;
  wire m_axi_bvalid;
  wire [63:0]m_axi_rdata;
  wire [3:0]m_axi_rid;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire [1:0]m_axi_rresp;
  wire m_axi_rvalid;
  wire [63:0]m_axi_wdata;
  wire m_axi_wlast;
  wire m_axi_wready;
  wire [7:0]m_axi_wstrb;
  wire m_axi_wvalid;
  wire [63:0]m_axib_araddr;
  wire [1:0]m_axib_arburst;
  wire [3:0]m_axib_arcache;
  wire [3:0]m_axib_arid;
  wire [7:0]m_axib_arlen;
  wire [2:0]m_axib_arprot;
  wire m_axib_arready;
  wire [2:0]m_axib_arsize;
  wire m_axib_arvalid;
  wire [63:0]m_axib_awaddr;
  wire [1:0]m_axib_awburst;
  wire [3:0]m_axib_awcache;
  wire [3:0]m_axib_awid;
  wire [7:0]m_axib_awlen;
  wire [2:0]m_axib_awprot;
  wire m_axib_awready;
  wire [2:0]m_axib_awsize;
  wire m_axib_awvalid;
  wire [3:0]m_axib_bid;
  wire m_axib_bready;
  wire [1:0]m_axib_bresp;
  wire m_axib_bvalid;
  wire [63:0]m_axib_rdata;
  wire [3:0]m_axib_rid;
  wire m_axib_rlast;
  wire m_axib_rready;
  wire [1:0]m_axib_rresp;
  wire m_axib_rvalid;
  wire [63:0]m_axib_wdata;
  wire m_axib_wlast;
  wire m_axib_wready;
  wire [7:0]m_axib_wstrb;
  wire m_axib_wvalid;
  wire [63:0]m_axis_rx_tdata_o;
  wire [7:4]\^m_axis_rx_tkeep_o ;
  wire m_axis_rx_tlast_o;
  wire m_axis_rx_tready_i;
  wire [21:0]\^m_axis_rx_tuser_o ;
  wire m_axis_rx_tvalid_o;
  wire msi_enable;
  wire [2:0]msi_vector_width;
  wire [1:0]pci_exp_rxn;
  wire [1:0]pci_exp_rxp;
  wire [1:0]pci_exp_txn;
  wire [1:0]pci_exp_txp;
  wire pl_directed_link_auton_i;
  wire [1:0]pl_directed_link_change_i;
  wire pl_directed_link_speed_i;
  wire [1:0]pl_directed_link_width_i;
  wire pl_upstream_prefer_deemph_i;
  wire rx_np_ok_i;
  wire rx_np_req_i;
  wire [63:0]s_axis_tx_tdata_i;
  wire [7:0]s_axis_tx_tkeep_i;
  wire s_axis_tx_tlast_i;
  wire s_axis_tx_tready_o;
  wire [3:0]s_axis_tx_tuser_i;
  wire s_axis_tx_tvalid_i;
  wire sys_clk;
  wire sys_rst_n;
  wire tx_cfg_gnt_i;
  wire user_lnk_up;
  wire [0:0]usr_irq_ack;
  wire [0:0]usr_irq_req;
  wire NLW_inst_Integrated_bloc_reset_o_UNCONNECTED;
  wire NLW_inst_ats_pri_en_UNCONNECTED;
  wire NLW_inst_atspri_m_axis_cq_tlast_UNCONNECTED;
  wire NLW_inst_atspri_m_axis_cq_tvalid_UNCONNECTED;
  wire NLW_inst_atspri_s_axis_rq_tready_UNCONNECTED;
  wire NLW_inst_axi_ctl_aresetn_UNCONNECTED;
  wire NLW_inst_c2h_dsc_byp_ready_0_UNCONNECTED;
  wire NLW_inst_c2h_dsc_byp_ready_1_UNCONNECTED;
  wire NLW_inst_c2h_dsc_byp_ready_2_UNCONNECTED;
  wire NLW_inst_c2h_dsc_byp_ready_3_UNCONNECTED;
  wire NLW_inst_cap_req_UNCONNECTED;
  wire NLW_inst_cfg_config_space_enable_sd_UNCONNECTED;
  wire NLW_inst_cfg_err_cor_in_sd_UNCONNECTED;
  wire NLW_inst_cfg_err_cor_o_UNCONNECTED;
  wire NLW_inst_cfg_err_fatal_o_UNCONNECTED;
  wire NLW_inst_cfg_err_nonfatal_o_UNCONNECTED;
  wire NLW_inst_cfg_err_uncor_in_sd_UNCONNECTED;
  wire NLW_inst_cfg_ext_read_received_UNCONNECTED;
  wire NLW_inst_cfg_ext_write_received_UNCONNECTED;
  wire NLW_inst_cfg_interrupt_msi_fail_UNCONNECTED;
  wire NLW_inst_cfg_interrupt_msi_pending_status_data_enable_sd_UNCONNECTED;
  wire NLW_inst_cfg_interrupt_msi_sent_UNCONNECTED;
  wire NLW_inst_cfg_interrupt_msi_tph_present_sd_UNCONNECTED;
  wire NLW_inst_cfg_interrupt_msix_fail_UNCONNECTED;
  wire NLW_inst_cfg_interrupt_msix_int_sd_UNCONNECTED;
  wire NLW_inst_cfg_interrupt_msix_sent_UNCONNECTED;
  wire NLW_inst_cfg_link_training_enable_sd_UNCONNECTED;
  wire NLW_inst_cfg_local_error_valid_o_UNCONNECTED;
  wire NLW_inst_cfg_mgmt_read_sd_UNCONNECTED;
  wire NLW_inst_cfg_mgmt_type1_cfg_reg_access_sd_UNCONNECTED;
  wire NLW_inst_cfg_mgmt_write_sd_UNCONNECTED;
  wire NLW_inst_cfg_msg_transmit_sd_UNCONNECTED;
  wire NLW_inst_cfg_status_ats_en_UNCONNECTED;
  wire NLW_inst_cfg_status_pr_en_UNCONNECTED;
  wire NLW_inst_cfg_status_pr_rf_UNCONNECTED;
  wire NLW_inst_cfg_status_pr_rst_UNCONNECTED;
  wire NLW_inst_cfg_status_pr_uprgi_UNCONNECTED;
  wire NLW_inst_core_clk_UNCONNECTED;
  wire NLW_inst_cxs0_active_ack_tx_UNCONNECTED;
  wire NLW_inst_cxs0_active_req_rx_UNCONNECTED;
  wire NLW_inst_cxs0_cntl_chk_rx_UNCONNECTED;
  wire NLW_inst_cxs0_crdgnt_chk_tx_UNCONNECTED;
  wire NLW_inst_cxs0_crdgnt_tx_UNCONNECTED;
  wire NLW_inst_cxs0_crdrtn_chk_rx_UNCONNECTED;
  wire NLW_inst_cxs0_crdrtn_rx_UNCONNECTED;
  wire NLW_inst_cxs0_deact_hint_tx_UNCONNECTED;
  wire NLW_inst_cxs0_valid_chk_rx_UNCONNECTED;
  wire NLW_inst_cxs0_valid_rx_UNCONNECTED;
  wire NLW_inst_drp_rdy_UNCONNECTED;
  wire NLW_inst_drpclk_usp_in_UNCONNECTED;
  wire NLW_inst_ext_ch_gt_drpclk_UNCONNECTED;
  wire NLW_inst_ext_phy_clk_bufg_gt_ce_UNCONNECTED;
  wire NLW_inst_ext_phy_clk_bufg_gt_reset_UNCONNECTED;
  wire NLW_inst_ext_phy_clk_bufgtcemask_UNCONNECTED;
  wire NLW_inst_ext_phy_clk_gt_bufgtrstmask_UNCONNECTED;
  wire NLW_inst_ext_phy_clk_rst_idle_UNCONNECTED;
  wire NLW_inst_ext_phy_clk_txoutclk_UNCONNECTED;
  wire NLW_inst_ext_usp_qpllxrcalenb_UNCONNECTED;
  wire NLW_inst_gt_drp_clk_UNCONNECTED;
  wire NLW_inst_gtwiz_reset_rx_done_us_in_UNCONNECTED;
  wire NLW_inst_gtwiz_reset_rx_done_usp_in_UNCONNECTED;
  wire NLW_inst_gtwiz_reset_tx_done_us_in_UNCONNECTED;
  wire NLW_inst_gtwiz_reset_tx_done_usp_in_UNCONNECTED;
  wire NLW_inst_gtwiz_userclk_rx_active_us_in_UNCONNECTED;
  wire NLW_inst_gtwiz_userclk_rx_active_usp_in_UNCONNECTED;
  wire NLW_inst_gtwiz_userclk_tx_active_us_in_UNCONNECTED;
  wire NLW_inst_gtwiz_userclk_tx_active_usp_in_UNCONNECTED;
  wire NLW_inst_gtwiz_userclk_tx_reset_us_in_UNCONNECTED;
  wire NLW_inst_h2c_dsc_byp_ready_0_UNCONNECTED;
  wire NLW_inst_h2c_dsc_byp_ready_1_UNCONNECTED;
  wire NLW_inst_h2c_dsc_byp_ready_2_UNCONNECTED;
  wire NLW_inst_h2c_dsc_byp_ready_3_UNCONNECTED;
  wire NLW_inst_int_dclk_out_UNCONNECTED;
  wire NLW_inst_int_oobclk_out_UNCONNECTED;
  wire NLW_inst_int_pclk_out_slave_UNCONNECTED;
  wire NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED;
  wire NLW_inst_int_userclk1_out_UNCONNECTED;
  wire NLW_inst_int_userclk2_out_UNCONNECTED;
  wire NLW_inst_interrupt_out_UNCONNECTED;
  wire NLW_inst_interrupt_out_msi_vec0to31_UNCONNECTED;
  wire NLW_inst_interrupt_out_msi_vec32to63_UNCONNECTED;
  wire NLW_inst_interrupt_out_msix_0_UNCONNECTED;
  wire NLW_inst_interrupt_out_msix_1_UNCONNECTED;
  wire NLW_inst_interrupt_out_msix_2_UNCONNECTED;
  wire NLW_inst_interrupt_out_msix_3_UNCONNECTED;
  wire NLW_inst_m_axib_arlock_UNCONNECTED;
  wire NLW_inst_m_axib_awlock_UNCONNECTED;
  wire NLW_inst_m_axil_arvalid_UNCONNECTED;
  wire NLW_inst_m_axil_awvalid_UNCONNECTED;
  wire NLW_inst_m_axil_bready_UNCONNECTED;
  wire NLW_inst_m_axil_rready_UNCONNECTED;
  wire NLW_inst_m_axil_wvalid_UNCONNECTED;
  wire NLW_inst_m_axis_cc_tlast_out_UNCONNECTED;
  wire NLW_inst_m_axis_cc_tvalid_out_UNCONNECTED;
  wire NLW_inst_m_axis_cq_tready_sd_UNCONNECTED;
  wire NLW_inst_m_axis_h2c_tlast_0_UNCONNECTED;
  wire NLW_inst_m_axis_h2c_tlast_1_UNCONNECTED;
  wire NLW_inst_m_axis_h2c_tlast_2_UNCONNECTED;
  wire NLW_inst_m_axis_h2c_tlast_3_UNCONNECTED;
  wire NLW_inst_m_axis_h2c_tvalid_0_UNCONNECTED;
  wire NLW_inst_m_axis_h2c_tvalid_1_UNCONNECTED;
  wire NLW_inst_m_axis_h2c_tvalid_2_UNCONNECTED;
  wire NLW_inst_m_axis_h2c_tvalid_3_UNCONNECTED;
  wire NLW_inst_m_axis_rc_tready_sd_UNCONNECTED;
  wire NLW_inst_m_axis_rq_tlast_out_UNCONNECTED;
  wire NLW_inst_m_axis_rq_tvalid_out_UNCONNECTED;
  wire NLW_inst_mcap_design_switch_UNCONNECTED;
  wire NLW_inst_msix_enable_UNCONNECTED;
  wire NLW_inst_pcie4_cxs0_active_ack_rx_sd_UNCONNECTED;
  wire NLW_inst_pcie4_cxs0_active_req_tx_sd_UNCONNECTED;
  wire NLW_inst_pcie4_cxs0_cntl_chk_tx_sd_UNCONNECTED;
  wire NLW_inst_pcie4_cxs0_crdgnt_chk_rx_sd_UNCONNECTED;
  wire NLW_inst_pcie4_cxs0_crdgnt_rx_sd_UNCONNECTED;
  wire NLW_inst_pcie4_cxs0_crdrtn_chk_tx_sd_UNCONNECTED;
  wire NLW_inst_pcie4_cxs0_crdrtn_tx_sd_UNCONNECTED;
  wire NLW_inst_pcie4_cxs0_deact_hint_rx_sd_UNCONNECTED;
  wire NLW_inst_pcie4_cxs0_valid_chk_tx_sd_UNCONNECTED;
  wire NLW_inst_pcie4_cxs0_valid_tx_sd_UNCONNECTED;
  wire NLW_inst_phy_prst_n_UNCONNECTED;
  wire NLW_inst_phy_rrst_n_UNCONNECTED;
  wire NLW_inst_phy_rst_idle_UNCONNECTED;
  wire NLW_inst_pipe_clk_UNCONNECTED;
  wire NLW_inst_pipe_gen3_out_UNCONNECTED;
  wire NLW_inst_pipe_qrst_idle_UNCONNECTED;
  wire NLW_inst_pipe_rate_idle_UNCONNECTED;
  wire NLW_inst_pipe_rst_idle_UNCONNECTED;
  wire NLW_inst_pipe_tx0_rcvr_det_UNCONNECTED;
  wire NLW_inst_pipe_txoutclk_out_UNCONNECTED;
  wire NLW_inst_qpll_drp_clk_UNCONNECTED;
  wire NLW_inst_qpll_drp_gen3_UNCONNECTED;
  wire NLW_inst_qpll_drp_ovrd_UNCONNECTED;
  wire NLW_inst_qpll_drp_rst_n_UNCONNECTED;
  wire NLW_inst_qpll_drp_start_UNCONNECTED;
  wire NLW_inst_qpll_qplld_UNCONNECTED;
  wire NLW_inst_rd_interrupt_UNCONNECTED;
  wire NLW_inst_s_axi_arready_UNCONNECTED;
  wire NLW_inst_s_axi_awready_UNCONNECTED;
  wire NLW_inst_s_axi_bvalid_UNCONNECTED;
  wire NLW_inst_s_axi_rlast_UNCONNECTED;
  wire NLW_inst_s_axi_rvalid_UNCONNECTED;
  wire NLW_inst_s_axi_wready_UNCONNECTED;
  wire NLW_inst_s_axib_arready_UNCONNECTED;
  wire NLW_inst_s_axib_awready_UNCONNECTED;
  wire NLW_inst_s_axib_bvalid_UNCONNECTED;
  wire NLW_inst_s_axib_rlast_UNCONNECTED;
  wire NLW_inst_s_axib_rvalid_UNCONNECTED;
  wire NLW_inst_s_axib_wready_UNCONNECTED;
  wire NLW_inst_s_axil_arready_UNCONNECTED;
  wire NLW_inst_s_axil_awready_UNCONNECTED;
  wire NLW_inst_s_axil_bvalid_UNCONNECTED;
  wire NLW_inst_s_axil_rvalid_UNCONNECTED;
  wire NLW_inst_s_axil_wready_UNCONNECTED;
  wire NLW_inst_s_axis_c2h_tready_0_UNCONNECTED;
  wire NLW_inst_s_axis_c2h_tready_1_UNCONNECTED;
  wire NLW_inst_s_axis_c2h_tready_2_UNCONNECTED;
  wire NLW_inst_s_axis_c2h_tready_3_UNCONNECTED;
  wire NLW_inst_s_axis_cc_tlast_sd_UNCONNECTED;
  wire NLW_inst_s_axis_cc_tvalid_sd_UNCONNECTED;
  wire NLW_inst_s_axis_cq_tlast_out_UNCONNECTED;
  wire NLW_inst_s_axis_cq_tready_out_UNCONNECTED;
  wire NLW_inst_s_axis_cq_tvalid_out_UNCONNECTED;
  wire NLW_inst_s_axis_rc_tlast_out_UNCONNECTED;
  wire NLW_inst_s_axis_rc_tready_out_UNCONNECTED;
  wire NLW_inst_s_axis_rc_tvalid_out_UNCONNECTED;
  wire NLW_inst_s_axis_rq_tlast_sd_UNCONNECTED;
  wire NLW_inst_s_axis_rq_tvalid_sd_UNCONNECTED;
  wire NLW_inst_sc0_ats_m_axis_cq_tlast_UNCONNECTED;
  wire NLW_inst_sc0_ats_m_axis_cq_tvalid_UNCONNECTED;
  wire NLW_inst_sc0_ats_m_axis_rc_tlast_UNCONNECTED;
  wire NLW_inst_sc0_ats_m_axis_rc_tvalid_UNCONNECTED;
  wire NLW_inst_sc0_ats_s_axis_cc_tready_UNCONNECTED;
  wire NLW_inst_sc0_ats_s_axis_rq_tready_UNCONNECTED;
  wire NLW_inst_sc1_ats_m_axis_cq_tlast_UNCONNECTED;
  wire NLW_inst_sc1_ats_m_axis_cq_tvalid_UNCONNECTED;
  wire NLW_inst_sc1_ats_m_axis_rc_tlast_UNCONNECTED;
  wire NLW_inst_sc1_ats_m_axis_rc_tvalid_UNCONNECTED;
  wire NLW_inst_sc1_ats_s_axis_cc_tready_UNCONNECTED;
  wire NLW_inst_sc1_ats_s_axis_rq_tready_UNCONNECTED;
  wire NLW_inst_startup_cfgclk_UNCONNECTED;
  wire NLW_inst_startup_cfgmclk_UNCONNECTED;
  wire NLW_inst_startup_eos_UNCONNECTED;
  wire NLW_inst_startup_preq_UNCONNECTED;
  wire NLW_inst_sys_clk_bufg_UNCONNECTED;
  wire NLW_inst_sys_clk_ce_out_UNCONNECTED;
  wire NLW_inst_usr_flr_clr_UNCONNECTED;
  wire NLW_inst_usr_flr_set_UNCONNECTED;
  wire NLW_inst_wr_interrupt_UNCONNECTED;
  wire [63:0]NLW_inst_atspri_m_axis_cq_tdata_UNCONNECTED;
  wire [1:0]NLW_inst_atspri_m_axis_cq_tkeep_UNCONNECTED;
  wire [84:0]NLW_inst_atspri_m_axis_cq_tuser_UNCONNECTED;
  wire [7:0]NLW_inst_c2h_sts_0_UNCONNECTED;
  wire [7:0]NLW_inst_c2h_sts_1_UNCONNECTED;
  wire [7:0]NLW_inst_c2h_sts_2_UNCONNECTED;
  wire [7:0]NLW_inst_c2h_sts_3_UNCONNECTED;
  wire [2:0]NLW_inst_cfg_current_speed_o_UNCONNECTED;
  wire [7:0]NLW_inst_cfg_ds_bus_number_sd_UNCONNECTED;
  wire [4:0]NLW_inst_cfg_ds_device_number_sd_UNCONNECTED;
  wire [2:0]NLW_inst_cfg_ds_function_number_sd_UNCONNECTED;
  wire [7:0]NLW_inst_cfg_ds_port_number_sd_UNCONNECTED;
  wire [63:0]NLW_inst_cfg_dsn_sd_UNCONNECTED;
  wire [7:0]NLW_inst_cfg_ext_function_number_UNCONNECTED;
  wire [9:0]NLW_inst_cfg_ext_register_number_UNCONNECTED;
  wire [3:0]NLW_inst_cfg_ext_write_byte_enable_UNCONNECTED;
  wire [31:0]NLW_inst_cfg_ext_write_data_UNCONNECTED;
  wire [2:0]NLW_inst_cfg_fc_sel_sd_UNCONNECTED;
  wire [3:0]NLW_inst_cfg_flr_done_sd_UNCONNECTED;
  wire [3:0]NLW_inst_cfg_flr_in_process_UNCONNECTED;
  wire [7:0]NLW_inst_cfg_function_status_UNCONNECTED;
  wire [3:0]NLW_inst_cfg_interrupt_int_sd_UNCONNECTED;
  wire [2:0]NLW_inst_cfg_interrupt_msi_attr_sd_UNCONNECTED;
  wire [3:0]NLW_inst_cfg_interrupt_msi_enable_UNCONNECTED;
  wire [7:0]NLW_inst_cfg_interrupt_msi_function_number_sd_UNCONNECTED;
  wire [31:0]NLW_inst_cfg_interrupt_msi_int_sd_UNCONNECTED;
  wire [3:0]NLW_inst_cfg_interrupt_msi_pending_status_function_num_sd_UNCONNECTED;
  wire [31:0]NLW_inst_cfg_interrupt_msi_pending_status_sd_UNCONNECTED;
  wire [8:0]NLW_inst_cfg_interrupt_msi_tph_st_tag_sd_UNCONNECTED;
  wire [1:0]NLW_inst_cfg_interrupt_msi_tph_type_sd_UNCONNECTED;
  wire [63:0]NLW_inst_cfg_interrupt_msix_address_sd_UNCONNECTED;
  wire [31:0]NLW_inst_cfg_interrupt_msix_data_sd_UNCONNECTED;
  wire [1:0]NLW_inst_cfg_interrupt_msix_enable_UNCONNECTED;
  wire [1:0]NLW_inst_cfg_interrupt_msix_mask_UNCONNECTED;
  wire [1:0]NLW_inst_cfg_interrupt_msix_vec_pending_sd_UNCONNECTED;
  wire [3:0]NLW_inst_cfg_interrupt_pending_sd_UNCONNECTED;
  wire [4:0]NLW_inst_cfg_local_error_o_UNCONNECTED;
  wire [5:0]NLW_inst_cfg_ltssm_state_UNCONNECTED;
  wire [5:0]NLW_inst_cfg_ltssm_state_o_UNCONNECTED;
  wire [2:0]NLW_inst_cfg_max_payload_UNCONNECTED;
  wire [2:0]NLW_inst_cfg_max_read_req_UNCONNECTED;
  wire [9:0]NLW_inst_cfg_mgmt_addr_sd_UNCONNECTED;
  wire [3:0]NLW_inst_cfg_mgmt_byte_enable_sd_UNCONNECTED;
  wire [7:0]NLW_inst_cfg_mgmt_function_number_sd_UNCONNECTED;
  wire [31:0]NLW_inst_cfg_mgmt_write_data_sd_UNCONNECTED;
  wire [31:0]NLW_inst_cfg_msg_transmit_data_sd_UNCONNECTED;
  wire [2:0]NLW_inst_cfg_msg_transmit_type_sd_UNCONNECTED;
  wire [3:0]NLW_inst_cfg_negotiated_width_o_UNCONNECTED;
  wire [4:0]NLW_inst_cfg_status_ats_stu_UNCONNECTED;
  wire [31:0]NLW_inst_cfg_status_ost_pr_alloc_UNCONNECTED;
  wire [251:0]NLW_inst_cfg_vf_flr_in_process_UNCONNECTED;
  wire [25:0]NLW_inst_common_commands_out_UNCONNECTED;
  wire [1:0]NLW_inst_cpllfreqlock_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_cpllpd_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_cpllpd_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_cpllreset_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_cpllreset_usp_in_UNCONNECTED;
  wire [13:0]NLW_inst_cxs0_cntl_rx_UNCONNECTED;
  wire [31:0]NLW_inst_cxs0_data_chk_rx_UNCONNECTED;
  wire [255:0]NLW_inst_cxs0_data_rx_UNCONNECTED;
  wire [1:0]NLW_inst_dmonfiforeset_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_dmonfiforeset_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_dmonitorclk_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_dmonitorclk_usp_in_UNCONNECTED;
  wire [15:0]NLW_inst_drp_do_UNCONNECTED;
  wire [17:0]NLW_inst_drpaddr_us_in_UNCONNECTED;
  wire [19:0]NLW_inst_drpaddr_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_drpclk_us_in_UNCONNECTED;
  wire [31:0]NLW_inst_drpdi_us_in_UNCONNECTED;
  wire [31:0]NLW_inst_drpdi_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_drpen_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_drpen_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_drprst_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_drpwe_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_drpwe_usp_in_UNCONNECTED;
  wire [31:0]NLW_inst_ext_ch_gt_drpdo_UNCONNECTED;
  wire [1:0]NLW_inst_ext_ch_gt_drprdy_UNCONNECTED;
  wire [8:0]NLW_inst_ext_phy_clk_bufgtdiv_UNCONNECTED;
  wire [0:0]NLW_inst_ext_qpll1pd_UNCONNECTED;
  wire [2:0]NLW_inst_ext_qpll1rate_UNCONNECTED;
  wire [0:0]NLW_inst_ext_qpll1refclk_UNCONNECTED;
  wire [0:0]NLW_inst_ext_qpll1reset_UNCONNECTED;
  wire [0:0]NLW_inst_ext_usp_qpll0pd_UNCONNECTED;
  wire [0:0]NLW_inst_ext_usp_qpll0reset_UNCONNECTED;
  wire [0:0]NLW_inst_ext_usp_qpll1pd_UNCONNECTED;
  wire [0:0]NLW_inst_ext_usp_qpll1reset_UNCONNECTED;
  wire [2:0]NLW_inst_ext_usp_qpllxrate_UNCONNECTED;
  wire [0:0]NLW_inst_ext_usp_qpllxrefclk_UNCONNECTED;
  wire [1:0]NLW_inst_eyescanreset_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_eyescanreset_usp_in_UNCONNECTED;
  wire [8:0]NLW_inst_gt_bufgtdiv_UNCONNECTED;
  wire [1:0]NLW_inst_gt_ch_drp_rdy_UNCONNECTED;
  wire [1:0]NLW_inst_gt_cplllock_UNCONNECTED;
  wire [33:0]NLW_inst_gt_dmonitorout_UNCONNECTED;
  wire [1:0]NLW_inst_gt_eyescandataerror_UNCONNECTED;
  wire [1:0]NLW_inst_gt_gen34_eios_det_UNCONNECTED;
  wire [1:0]NLW_inst_gt_gtpowergood_UNCONNECTED;
  wire [1:0]NLW_inst_gt_pcierateidle_UNCONNECTED;
  wire [1:0]NLW_inst_gt_pcieuserratestart_UNCONNECTED;
  wire [1:0]NLW_inst_gt_phystatus_UNCONNECTED;
  wire [0:0]NLW_inst_gt_qpll0lock_UNCONNECTED;
  wire [0:0]NLW_inst_gt_qpll1lock_UNCONNECTED;
  wire [5:0]NLW_inst_gt_rxbufstatus_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxcdrlock_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxcommadet_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxdlysresetdone_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxoutclk_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxoutclkfabric_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxoutclkpcs_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxphaligndone_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxpmaresetdone_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxprbserr_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxprbslocked_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxrecclkout_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxresetdone_UNCONNECTED;
  wire [5:0]NLW_inst_gt_rxstatus_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxsyncdone_UNCONNECTED;
  wire [1:0]NLW_inst_gt_rxvalid_UNCONNECTED;
  wire [1:0]NLW_inst_gt_txdlysresetdone_UNCONNECTED;
  wire [1:0]NLW_inst_gt_txelecidle_UNCONNECTED;
  wire [1:0]NLW_inst_gt_txoutclk_UNCONNECTED;
  wire [1:0]NLW_inst_gt_txoutclkfabric_UNCONNECTED;
  wire [1:0]NLW_inst_gt_txoutclkpcs_UNCONNECTED;
  wire [1:0]NLW_inst_gt_txphaligndone_UNCONNECTED;
  wire [1:0]NLW_inst_gt_txphinitdone_UNCONNECTED;
  wire [1:0]NLW_inst_gt_txpmaresetdone_UNCONNECTED;
  wire [1:0]NLW_inst_gt_txprogdivresetdone_UNCONNECTED;
  wire [1:0]NLW_inst_gt_txresetdone_UNCONNECTED;
  wire [1:0]NLW_inst_gt_txsyncdone_UNCONNECTED;
  wire [1:0]NLW_inst_gthrxn_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_gthrxp_us_in_UNCONNECTED;
  wire [0:0]NLW_inst_gtrefclk00_usp_in_UNCONNECTED;
  wire [0:0]NLW_inst_gtrefclk01_us_in_UNCONNECTED;
  wire [0:0]NLW_inst_gtrefclk01_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_gtrefclk0_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_gtrefclk0_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_gtrxreset_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_gtrxreset_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_gttxreset_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_gttxreset_usp_in_UNCONNECTED;
  wire [7:0]NLW_inst_h2c_sts_0_UNCONNECTED;
  wire [7:0]NLW_inst_h2c_sts_1_UNCONNECTED;
  wire [7:0]NLW_inst_h2c_sts_2_UNCONNECTED;
  wire [7:0]NLW_inst_h2c_sts_3_UNCONNECTED;
  wire [0:0]NLW_inst_int_qpll1lock_out_UNCONNECTED;
  wire [0:0]NLW_inst_int_qpll1outclk_out_UNCONNECTED;
  wire [0:0]NLW_inst_int_qpll1outrefclk_out_UNCONNECTED;
  wire [1:0]NLW_inst_int_qplllock_out_UNCONNECTED;
  wire [1:0]NLW_inst_int_qplloutclk_out_UNCONNECTED;
  wire [1:0]NLW_inst_int_qplloutrefclk_out_UNCONNECTED;
  wire [1:0]NLW_inst_int_rxoutclk_out_UNCONNECTED;
  wire [0:0]NLW_inst_int_usp_qpll0lock_out_UNCONNECTED;
  wire [0:0]NLW_inst_int_usp_qpll0outclk_out_UNCONNECTED;
  wire [0:0]NLW_inst_int_usp_qpll0outrefclk_out_UNCONNECTED;
  wire [0:0]NLW_inst_int_usp_qpll1lock_out_UNCONNECTED;
  wire [0:0]NLW_inst_int_usp_qpll1outclk_out_UNCONNECTED;
  wire [0:0]NLW_inst_int_usp_qpll1outrefclk_out_UNCONNECTED;
  wire [5:0]NLW_inst_loopback_us_in_UNCONNECTED;
  wire [5:0]NLW_inst_loopback_usp_in_UNCONNECTED;
  wire [7:0]NLW_inst_m_axi_wuser_UNCONNECTED;
  wire [7:0]NLW_inst_m_axib_aruser_UNCONNECTED;
  wire [7:0]NLW_inst_m_axib_awuser_UNCONNECTED;
  wire [7:0]NLW_inst_m_axib_wuser_UNCONNECTED;
  wire [31:0]NLW_inst_m_axil_araddr_UNCONNECTED;
  wire [2:0]NLW_inst_m_axil_arprot_UNCONNECTED;
  wire [10:0]NLW_inst_m_axil_aruser_UNCONNECTED;
  wire [31:0]NLW_inst_m_axil_awaddr_UNCONNECTED;
  wire [2:0]NLW_inst_m_axil_awprot_UNCONNECTED;
  wire [10:0]NLW_inst_m_axil_awuser_UNCONNECTED;
  wire [31:0]NLW_inst_m_axil_wdata_UNCONNECTED;
  wire [3:0]NLW_inst_m_axil_wstrb_UNCONNECTED;
  wire [63:0]NLW_inst_m_axis_cc_tdata_out_UNCONNECTED;
  wire [1:0]NLW_inst_m_axis_cc_tkeep_out_UNCONNECTED;
  wire [3:0]NLW_inst_m_axis_cc_tready_out_UNCONNECTED;
  wire [32:0]NLW_inst_m_axis_cc_tuser_out_UNCONNECTED;
  wire [63:0]NLW_inst_m_axis_h2c_tdata_0_UNCONNECTED;
  wire [63:0]NLW_inst_m_axis_h2c_tdata_1_UNCONNECTED;
  wire [63:0]NLW_inst_m_axis_h2c_tdata_2_UNCONNECTED;
  wire [63:0]NLW_inst_m_axis_h2c_tdata_3_UNCONNECTED;
  wire [7:0]NLW_inst_m_axis_h2c_tkeep_0_UNCONNECTED;
  wire [7:0]NLW_inst_m_axis_h2c_tkeep_1_UNCONNECTED;
  wire [7:0]NLW_inst_m_axis_h2c_tkeep_2_UNCONNECTED;
  wire [7:0]NLW_inst_m_axis_h2c_tkeep_3_UNCONNECTED;
  wire [7:0]NLW_inst_m_axis_h2c_tuser_0_UNCONNECTED;
  wire [7:0]NLW_inst_m_axis_h2c_tuser_1_UNCONNECTED;
  wire [7:0]NLW_inst_m_axis_h2c_tuser_2_UNCONNECTED;
  wire [7:0]NLW_inst_m_axis_h2c_tuser_3_UNCONNECTED;
  wire [63:0]NLW_inst_m_axis_rq_tdata_out_UNCONNECTED;
  wire [1:0]NLW_inst_m_axis_rq_tkeep_out_UNCONNECTED;
  wire [3:0]NLW_inst_m_axis_rq_tready_out_UNCONNECTED;
  wire [59:0]NLW_inst_m_axis_rq_tuser_out_UNCONNECTED;
  wire [3:0]NLW_inst_m_axis_rx_tkeep_o_UNCONNECTED;
  wire [20:9]NLW_inst_m_axis_rx_tuser_o_UNCONNECTED;
  wire [13:0]NLW_inst_pcie4_cxs0_cntl_tx_sd_UNCONNECTED;
  wire [31:0]NLW_inst_pcie4_cxs0_data_chk_tx_sd_UNCONNECTED;
  wire [255:0]NLW_inst_pcie4_cxs0_data_tx_sd_UNCONNECTED;
  wire [1:0]NLW_inst_pcie_cq_np_req_sd_UNCONNECTED;
  wire [1:0]NLW_inst_pcieeqrxeqadaptdone_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_pcieeqrxeqadaptdone_usp_in_UNCONNECTED;
  wire [2:0]NLW_inst_pcierateqpll0_usp_in_UNCONNECTED;
  wire [2:0]NLW_inst_pcierateqpll1_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_pcierstidle_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_pcierstidle_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_pciersttxsyncstart_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_pciersttxsyncstart_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_pcieuserratedone_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_pcieuserratedone_usp_in_UNCONNECTED;
  wire [31:0]NLW_inst_pcsrsvdin_us_in_UNCONNECTED;
  wire [3:0]NLW_inst_phy_rst_fsm_UNCONNECTED;
  wire [5:0]NLW_inst_phy_rxeq_fsm_UNCONNECTED;
  wire [3:0]NLW_inst_phy_txeq_ctrl_UNCONNECTED;
  wire [5:0]NLW_inst_phy_txeq_fsm_UNCONNECTED;
  wire [7:0]NLW_inst_phy_txeq_preset_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_cpll_lock_UNCONNECTED;
  wire [31:0]NLW_inst_pipe_debug_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_0_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_1_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_2_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_3_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_4_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_5_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_6_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_7_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_8_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_9_UNCONNECTED;
  wire [127:0]NLW_inst_pipe_debug_debug_out_128_0_UNCONNECTED;
  wire [127:0]NLW_inst_pipe_debug_debug_out_128_1_UNCONNECTED;
  wire [127:0]NLW_inst_pipe_debug_debug_out_128_2_UNCONNECTED;
  wire [127:0]NLW_inst_pipe_debug_debug_out_128_3_UNCONNECTED;
  wire [15:0]NLW_inst_pipe_debug_debug_out_ext_16_0_UNCONNECTED;
  wire [15:0]NLW_inst_pipe_debug_debug_out_ext_16_1_UNCONNECTED;
  wire [15:0]NLW_inst_pipe_debug_debug_out_ext_16_2_UNCONNECTED;
  wire [15:0]NLW_inst_pipe_debug_debug_out_ext_16_3_UNCONNECTED;
  wire [7:0]NLW_inst_pipe_debug_inject_rx_status_UNCONNECTED;
  wire [7:0]NLW_inst_pipe_debug_inject_tx_status_UNCONNECTED;
  wire [29:0]NLW_inst_pipe_dmonitorout_UNCONNECTED;
  wire [13:0]NLW_inst_pipe_drp_fsm_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_eyescandataerror_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_pclk_sel_out_UNCONNECTED;
  wire [0:0]NLW_inst_pipe_qpll_lock_UNCONNECTED;
  wire [11:0]NLW_inst_pipe_qrst_fsm_UNCONNECTED;
  wire [9:0]NLW_inst_pipe_rate_fsm_UNCONNECTED;
  wire [4:0]NLW_inst_pipe_rst_fsm_UNCONNECTED;
  wire [5:0]NLW_inst_pipe_rxbufstatus_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxcommadet_UNCONNECTED;
  wire [15:0]NLW_inst_pipe_rxdisperr_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxdlysresetdone_UNCONNECTED;
  wire [15:0]NLW_inst_pipe_rxnotintable_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxoutclk_out_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxphaligndone_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxpmaresetdone_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxprbserr_UNCONNECTED;
  wire [5:0]NLW_inst_pipe_rxstatus_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxsyncdone_UNCONNECTED;
  wire [13:0]NLW_inst_pipe_sync_fsm_rx_UNCONNECTED;
  wire [11:0]NLW_inst_pipe_sync_fsm_tx_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_tx0_powerdown_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_0_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_10_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_11_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_12_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_13_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_14_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_15_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_1_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_2_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_3_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_4_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_5_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_6_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_7_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_8_sigs_UNCONNECTED;
  wire [83:0]NLW_inst_pipe_tx_9_sigs_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_txdlysresetdone_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_txphaligndone_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_txphinitdone_UNCONNECTED;
  wire [1:0]NLW_inst_qpll0clk_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_qpll0freqlock_usp_in_UNCONNECTED;
  wire [0:0]NLW_inst_qpll0pd_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_qpll0refclk_us_in_UNCONNECTED;
  wire [0:0]NLW_inst_qpll0reset_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_qpll1clk_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_qpll1freqlock_usp_in_UNCONNECTED;
  wire [0:0]NLW_inst_qpll1pd_us_in_UNCONNECTED;
  wire [0:0]NLW_inst_qpll1pd_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_qpll1refclk_us_in_UNCONNECTED;
  wire [0:0]NLW_inst_qpll1reset_us_in_UNCONNECTED;
  wire [0:0]NLW_inst_qpll1reset_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_qpll_qpllreset_UNCONNECTED;
  wire [4:0]NLW_inst_qpllrsvd2_us_in_UNCONNECTED;
  wire [4:0]NLW_inst_qpllrsvd3_us_in_UNCONNECTED;
  wire [0:0]NLW_inst_rcalenb_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_resetovrd_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rx8b10ben_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rx8b10ben_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxbufreset_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxbufreset_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxcdrfreqreset_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxcdrhold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxcdrhold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxcdrreset_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxcommadeten_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxcommadeten_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfeagchold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfeagchold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfecfokhold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfecfokhold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfekhhold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfekhhold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfelfhold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfelfhold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfelpmreset_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap10hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap10hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap11hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap11hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap12hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap12hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap13hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap13hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap14hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap14hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap15hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap15hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap2hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap2hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap3hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap3hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap4hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap4hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap5hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap5hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap6hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap6hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap7hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap7hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap8hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap8hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap9hold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfetap9hold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfeuthold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfeuthold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfevphold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxdfevphold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxlpmen_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxlpmen_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxlpmgchold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxlpmgchold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxlpmhfhold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxlpmhfhold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxlpmlfhold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxlpmlfhold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxlpmoshold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxlpmoshold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxmcommaalignen_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxmcommaalignen_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxoshold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxoshold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxpcommaalignen_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxpcommaalignen_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxpcsreset_usp_in_UNCONNECTED;
  wire [3:0]NLW_inst_rxpd_us_in_UNCONNECTED;
  wire [3:0]NLW_inst_rxpd_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxpmareset_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxpolarity_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxpolarity_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxprbscntreset_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxprbscntreset_usp_in_UNCONNECTED;
  wire [7:0]NLW_inst_rxprbssel_us_in_UNCONNECTED;
  wire [7:0]NLW_inst_rxprbssel_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxprogdivreset_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxprogdivreset_usp_in_UNCONNECTED;
  wire [5:0]NLW_inst_rxrate_us_in_UNCONNECTED;
  wire [5:0]NLW_inst_rxrate_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxratemode_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxratemode_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxslide_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxslide_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxtermination_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxuserrdy_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxuserrdy_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxusrclk2_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxusrclk2_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxusrclk_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_rxusrclk_usp_in_UNCONNECTED;
  wire [15:0]NLW_inst_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_inst_s_axi_bresp_UNCONNECTED;
  wire [31:0]NLW_inst_s_axi_rdata_UNCONNECTED;
  wire [15:0]NLW_inst_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_inst_s_axi_rresp_UNCONNECTED;
  wire [3:0]NLW_inst_s_axib_bid_UNCONNECTED;
  wire [1:0]NLW_inst_s_axib_bresp_UNCONNECTED;
  wire [63:0]NLW_inst_s_axib_rdata_UNCONNECTED;
  wire [3:0]NLW_inst_s_axib_rid_UNCONNECTED;
  wire [1:0]NLW_inst_s_axib_rresp_UNCONNECTED;
  wire [7:0]NLW_inst_s_axib_ruser_UNCONNECTED;
  wire [1:0]NLW_inst_s_axil_bresp_UNCONNECTED;
  wire [31:0]NLW_inst_s_axil_rdata_UNCONNECTED;
  wire [1:0]NLW_inst_s_axil_rresp_UNCONNECTED;
  wire [63:0]NLW_inst_s_axis_cc_tdata_sd_UNCONNECTED;
  wire [1:0]NLW_inst_s_axis_cc_tkeep_sd_UNCONNECTED;
  wire [32:0]NLW_inst_s_axis_cc_tuser_sd_UNCONNECTED;
  wire [63:0]NLW_inst_s_axis_cq_tdata_out_UNCONNECTED;
  wire [1:0]NLW_inst_s_axis_cq_tkeep_out_UNCONNECTED;
  wire [84:0]NLW_inst_s_axis_cq_tuser_out_UNCONNECTED;
  wire [63:0]NLW_inst_s_axis_rc_tdata_out_UNCONNECTED;
  wire [1:0]NLW_inst_s_axis_rc_tkeep_out_UNCONNECTED;
  wire [74:0]NLW_inst_s_axis_rc_tuser_out_UNCONNECTED;
  wire [63:0]NLW_inst_s_axis_rq_tdata_sd_UNCONNECTED;
  wire [1:0]NLW_inst_s_axis_rq_tkeep_sd_UNCONNECTED;
  wire [59:0]NLW_inst_s_axis_rq_tuser_sd_UNCONNECTED;
  wire [63:0]NLW_inst_sc0_ats_m_axis_cq_tdata_UNCONNECTED;
  wire [7:0]NLW_inst_sc0_ats_m_axis_cq_tkeep_UNCONNECTED;
  wire [84:0]NLW_inst_sc0_ats_m_axis_cq_tuser_UNCONNECTED;
  wire [63:0]NLW_inst_sc0_ats_m_axis_rc_tdata_UNCONNECTED;
  wire [7:0]NLW_inst_sc0_ats_m_axis_rc_tkeep_UNCONNECTED;
  wire [74:0]NLW_inst_sc0_ats_m_axis_rc_tuser_UNCONNECTED;
  wire [63:0]NLW_inst_sc1_ats_m_axis_cq_tdata_UNCONNECTED;
  wire [7:0]NLW_inst_sc1_ats_m_axis_cq_tkeep_UNCONNECTED;
  wire [84:0]NLW_inst_sc1_ats_m_axis_cq_tuser_UNCONNECTED;
  wire [63:0]NLW_inst_sc1_ats_m_axis_rc_tdata_UNCONNECTED;
  wire [7:0]NLW_inst_sc1_ats_m_axis_rc_tkeep_UNCONNECTED;
  wire [74:0]NLW_inst_sc1_ats_m_axis_rc_tuser_UNCONNECTED;
  wire [3:0]NLW_inst_startup_di_UNCONNECTED;
  wire [1:0]NLW_inst_tx8b10ben_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_tx8b10ben_usp_in_UNCONNECTED;
  wire [31:0]NLW_inst_txctrl0_us_in_UNCONNECTED;
  wire [31:0]NLW_inst_txctrl0_usp_in_UNCONNECTED;
  wire [31:0]NLW_inst_txctrl1_us_in_UNCONNECTED;
  wire [31:0]NLW_inst_txctrl1_usp_in_UNCONNECTED;
  wire [15:0]NLW_inst_txctrl2_us_in_UNCONNECTED;
  wire [15:0]NLW_inst_txctrl2_usp_in_UNCONNECTED;
  wire [255:0]NLW_inst_txdata_us_in_UNCONNECTED;
  wire [255:0]NLW_inst_txdata_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdeemph_us_in_UNCONNECTED;
  wire [3:0]NLW_inst_txdeemph_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdetectrx_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdetectrx_usp_in_UNCONNECTED;
  wire [7:0]NLW_inst_txdiffctrl_us_in_UNCONNECTED;
  wire [9:0]NLW_inst_txdiffctrl_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlybypass_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlybypass_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlyen_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlyen_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlyhold_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlyhold_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlyovrden_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlyovrden_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlysreset_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlysreset_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlyupdown_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txdlyupdown_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txelecidle_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txelecidle_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txinhibit_us_in_UNCONNECTED;
  wire [13:0]NLW_inst_txmaincursor_us_in_UNCONNECTED;
  wire [13:0]NLW_inst_txmaincursor_usp_in_UNCONNECTED;
  wire [5:0]NLW_inst_txmargin_us_in_UNCONNECTED;
  wire [5:0]NLW_inst_txmargin_usp_in_UNCONNECTED;
  wire [5:0]NLW_inst_txoutclksel_us_in_UNCONNECTED;
  wire [5:0]NLW_inst_txoutclksel_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txpcsreset_usp_in_UNCONNECTED;
  wire [3:0]NLW_inst_txpd_us_in_UNCONNECTED;
  wire [3:0]NLW_inst_txpd_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txpdelecidlemode_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphalign_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphalign_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphalignen_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphalignen_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphdlypd_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphdlypd_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphdlyreset_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphdlyreset_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphdlytstclk_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphdlytstclk_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphinit_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphinit_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphovrden_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txphovrden_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txpisopd_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txpmareset_usp_in_UNCONNECTED;
  wire [9:0]NLW_inst_txpostcursor_us_in_UNCONNECTED;
  wire [9:0]NLW_inst_txpostcursor_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txprbsforceerr_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txprbsforceerr_usp_in_UNCONNECTED;
  wire [7:0]NLW_inst_txprbssel_us_in_UNCONNECTED;
  wire [7:0]NLW_inst_txprbssel_usp_in_UNCONNECTED;
  wire [9:0]NLW_inst_txprecursor_us_in_UNCONNECTED;
  wire [9:0]NLW_inst_txprecursor_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txprogdivreset_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txprogdivreset_usp_in_UNCONNECTED;
  wire [5:0]NLW_inst_txrate_us_in_UNCONNECTED;
  wire [5:0]NLW_inst_txrate_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txswing_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txswing_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txsyncallin_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txsyncallin_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txsyncin_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txsyncin_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txsyncmode_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txsyncmode_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txuserrdy_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txuserrdy_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txusrclk2_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txusrclk2_usp_in_UNCONNECTED;
  wire [1:0]NLW_inst_txusrclk_us_in_UNCONNECTED;
  wire [1:0]NLW_inst_txusrclk_usp_in_UNCONNECTED;
  wire [7:0]NLW_inst_usr_flr_fnc_UNCONNECTED;

  assign Integrated_bloc_reset_o = \<const0> ;
  assign m_axib_arlock = \<const0> ;
  assign m_axib_awlock = \<const0> ;
  assign m_axis_rx_tkeep_o[7:4] = \^m_axis_rx_tkeep_o [7:4];
  assign m_axis_rx_tkeep_o[3] = \<const1> ;
  assign m_axis_rx_tkeep_o[2] = \<const1> ;
  assign m_axis_rx_tkeep_o[1] = \<const1> ;
  assign m_axis_rx_tkeep_o[0] = \<const1> ;
  assign m_axis_rx_tuser_o[21] = \^m_axis_rx_tuser_o [21];
  assign m_axis_rx_tuser_o[20] = \<const0> ;
  assign m_axis_rx_tuser_o[19:17] = \^m_axis_rx_tuser_o [19:17];
  assign m_axis_rx_tuser_o[16] = \<const0> ;
  assign m_axis_rx_tuser_o[15] = \<const0> ;
  assign m_axis_rx_tuser_o[14] = \^m_axis_rx_tuser_o [14];
  assign m_axis_rx_tuser_o[13] = \<const0> ;
  assign m_axis_rx_tuser_o[12] = \<const0> ;
  assign m_axis_rx_tuser_o[11] = \<const0> ;
  assign m_axis_rx_tuser_o[10] = \<const0> ;
  assign m_axis_rx_tuser_o[9] = \<const0> ;
  assign m_axis_rx_tuser_o[8:0] = \^m_axis_rx_tuser_o [8:0];
  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  (* ACS_EXT_CAP_ENABLE = "FALSE" *) 
  (* AXI4MM_ULTRA = "0" *) 
  (* AXILITE_MASTER_APERTURE_SIZE = "8'b00001101" *) 
  (* AXILITE_MASTER_CONTROL = "3'b000" *) 
  (* AXISTEN_IF_ENABLE_MSG_ROUTE = "18'b000000000000000000" *) 
  (* AXIST_BYPASS_APERTURE_SIZE = "8'b00001101" *) 
  (* AXIST_BYPASS_CONTROL = "3'b100" *) 
  (* AXIS_CCIX_RX_TDATA_WIDTH = "256" *) 
  (* AXIS_CCIX_RX_TUSER_WIDTH = "47" *) 
  (* AXIS_CCIX_TX_TDATA_WIDTH = "256" *) 
  (* AXIS_CCIX_TX_TUSER_WIDTH = "47" *) 
  (* AXIS_PIPE_LINE_STAGE = "0" *) 
  (* AXI_ACLK_LOOPBACK = "FALSE" *) 
  (* AXI_ADDR_WIDTH = "64" *) 
  (* AXI_DATA_WIDTH = "64" *) 
  (* AXI_VIP_IN_EXDES = "FALSE" *) 
  (* AXSIZE_BYTE_ACCESS_EN = "FALSE" *) 
  (* BACKPRESSURE = "0" *) 
  (* BARLITE0 = "7" *) 
  (* BARLITE1 = "0" *) 
  (* BARLITE2 = "7" *) 
  (* BARLITE_EXT_PF0 = "6'b000000" *) 
  (* BARLITE_EXT_PF1 = "6'b000000" *) 
  (* BARLITE_EXT_PF2 = "6'b000000" *) 
  (* BARLITE_EXT_PF3 = "6'b000000" *) 
  (* BARLITE_INT_PF0 = "6'b000001" *) 
  (* BARLITE_INT_PF1 = "6'b000000" *) 
  (* BARLITE_INT_PF2 = "6'b000000" *) 
  (* BARLITE_INT_PF3 = "6'b000000" *) 
  (* BRIDGE_BURST = "FALSE" *) 
  (* C2H_XDMA_CHNL = "8'b00001111" *) 
  (* CCIX_DVSEC = "FALSE" *) 
  (* CCIX_ENABLE = "FALSE" *) 
  (* CDC_WB_EN = "1" *) 
  (* CFG_EXT_IF = "FALSE" *) 
  (* CFG_MGMT_IF = "TRUE" *) 
  (* CFG_SPACE_ENABLE = "FALSE" *) 
  (* COMPONENT_NAME = "xdma_0" *) 
  (* CORE_CLK_FREQ = "2" *) 
  (* C_ADDR_ALGN = "1" *) 
  (* C_ADDR_BITS = "64" *) 
  (* C_ATS_CAP_NEXTPTR = "12'b000000000000" *) 
  (* C_ATS_CC_TUSER_WIDTH = "33" *) 
  (* C_ATS_CQ_TUSER_WIDTH = "85" *) 
  (* C_ATS_DATA_WIDTH = "64" *) 
  (* C_ATS_ENABLE = "FALSE" *) 
  (* C_ATS_OFFSET = "30'b000000000000000000000100100000" *) 
  (* C_ATS_RC_TUSER_WIDTH = "75" *) 
  (* C_ATS_RQ_TUSER_WIDTH = "60" *) 
  (* C_ATS_SWITCH_UNIQUE_BDF = "1" *) 
  (* C_AXIBAR2PCIEATTR_0 = "3'b000" *) 
  (* C_AXIBAR2PCIEATTR_1 = "3'b000" *) 
  (* C_AXIBAR2PCIEATTR_2 = "3'b000" *) 
  (* C_AXIBAR2PCIEATTR_3 = "3'b000" *) 
  (* C_AXIBAR2PCIEATTR_4 = "3'b000" *) 
  (* C_AXIBAR2PCIEATTR_5 = "3'b000" *) 
  (* C_AXIBAR2PCIEBAR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR2PCIEBAR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR2PCIEBAR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR2PCIEBAR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR2PCIEBAR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR2PCIEBAR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_AS_0 = "1" *) 
  (* C_AXIBAR_AS_1 = "1" *) 
  (* C_AXIBAR_AS_2 = "1" *) 
  (* C_AXIBAR_AS_3 = "1" *) 
  (* C_AXIBAR_AS_4 = "1" *) 
  (* C_AXIBAR_AS_5 = "1" *) 
  (* C_AXIBAR_HIGHADDR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_HIGHADDR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_HIGHADDR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_HIGHADDR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_HIGHADDR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_HIGHADDR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_NOXLATE = "0" *) 
  (* C_AXIBAR_NUM = "1" *) 
  (* C_AXIBAR_REGIONEN = "0" *) 
  (* C_BASEADDR = "4096" *) 
  (* C_C2H_NUM_CHNL = "1" *) 
  (* C_C2H_NUM_RIDS = "16" *) 
  (* C_C2H_TUSER_WIDTH = "64" *) 
  (* C_COMP_TIMEOUT = "1" *) 
  (* C_DEVICE_NUMBER = "0" *) 
  (* C_DSC_MAGIC_EN = "1" *) 
  (* C_ECC_ENABLE = "0" *) 
  (* C_ENABLE_RESOURCE_REDUCTION = "FALSE" *) 
  (* C_ERRC_DEC_EN = "0" *) 
  (* C_FAMILY = "artix7" *) 
  (* C_FF_ON_INT_IF = "FALSE" *) 
  (* C_GEN2_DEVICES = "1'b1" *) 
  (* C_H2C_NUM_CHNL = "1" *) 
  (* C_H2C_NUM_RIDS = "32" *) 
  (* C_H2C_TUSER_WIDTH = "48" *) 
  (* C_HIGHADDR = "8191" *) 
  (* C_IGNORE_SIZE_AXI_SLAVE = "1" *) 
  (* C_INCLUDE_BAROFFSET_REG = "1" *) 
  (* C_INCLUDE_RC = "0" *) 
  (* C_INTX_RX_PIN_EN = "1" *) 
  (* C_INV_QUEUE_DEPTH = "5'b00000" *) 
  (* C_KEEP_WIDTH = "8" *) 
  (* C_LAST_CORE_CAP_ADDR = "12'b000100000000" *) 
  (* C_LEGACY_INT_EN = "TRUE" *) 
  (* C_METERING_ON = "1" *) 
  (* C_MSIX_INT_TABLE_EN = "0" *) 
  (* C_MSIX_RX_PIN_EN = "1" *) 
  (* C_MSI_ENABLED = "TRUE" *) 
  (* C_MSI_RX_PIN_EN = "0" *) 
  (* C_M_AXIL_ARUSER_WIDTH = "11" *) 
  (* C_M_AXIL_AWUSER_WIDTH = "11" *) 
  (* C_M_AXIS_DATA_WIDTH = "64" *) 
  (* C_M_AXIS_RC_USER_WIDTH = "75" *) 
  (* C_M_AXIS_RQ_USER_WIDTH = "60" *) 
  (* C_M_AXIS_USER_WIDTH = "64" *) 
  (* C_M_AXI_ADDR_WIDTH = "64" *) 
  (* C_M_AXI_ARUSER_WIDTH = "8" *) 
  (* C_M_AXI_AWUSER_WIDTH = "8" *) 
  (* C_M_AXI_BUSER_WIDTH = "1" *) 
  (* C_M_AXI_DATA_WIDTH = "64" *) 
  (* C_M_AXI_ID_WIDTH = "4" *) 
  (* C_M_AXI_NUM_READ = "8" *) 
  (* C_M_AXI_NUM_READQ = "2" *) 
  (* C_M_AXI_NUM_WRITE = "4" *) 
  (* C_M_AXI_NUM_WRITE_SCALE = "1" *) 
  (* C_M_AXI_RUSER_WIDTH = "8" *) 
  (* C_M_AXI_WUSER_WIDTH = "8" *) 
  (* C_M_KEEP_WIDTH = "2" *) 
  (* C_NUMQ_PER_CHNL = "256" *) 
  (* C_NUM_AXI_DSC_CPL_DID = "64" *) 
  (* C_NUM_DSC_PCIE_RID = "32" *) 
  (* C_NUM_MSIX_VECTORS = "32" *) 
  (* C_NUM_OF_SC = "1" *) 
  (* C_NUM_PCIE_DSC_CPL_DID = "256" *) 
  (* C_NUM_USER_INTR = "9" *) 
  (* C_NUM_USER_NEW_INTR = "6" *) 
  (* C_NUM_USR_IRQ = "1" *) 
  (* C_OLD_BRIDGE_TIMEOUT = "0" *) 
  (* C_OST_PR_CAP = "0" *) 
  (* C_PARITY_CHECK = "0" *) 
  (* C_PARITY_GEN = "0" *) 
  (* C_PARITY_PROP = "0" *) 
  (* C_PCIEBAR2AXIBAR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_0_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_1_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_2_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_3_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_4_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_5_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_6 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_6_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR_AS = "1" *) 
  (* C_PCIEBAR_LEN_0 = "16" *) 
  (* C_PCIEBAR_LEN_1 = "20" *) 
  (* C_PCIEBAR_LEN_2 = "64" *) 
  (* C_PCIEBAR_LEN_3 = "64" *) 
  (* C_PCIEBAR_LEN_4 = "64" *) 
  (* C_PCIEBAR_LEN_5 = "64" *) 
  (* C_PCIEBAR_LEN_6 = "7" *) 
  (* C_PCIEBAR_NUM = "6" *) 
  (* C_PCIE_PFS_SUPPORTED = "0" *) 
  (* C_PRI_ENABLE = "FALSE" *) 
  (* C_PR_CAP_NEXTPTR = "12'b000000000000" *) 
  (* C_PR_OFFSET = "30'b000000000000000000000100100100" *) 
  (* C_RD_BUFFER_ADDR_SIZE = "9" *) 
  (* C_RD_BUFFER_SIZE_BITS = "5" *) 
  (* C_SLAVE_READ_64OS_EN = "0" *) 
  (* C_SMMU_EN = "0" *) 
  (* C_SRIOV_EN = "0" *) 
  (* C_S_AXIS_CC_USER_WIDTH = "33" *) 
  (* C_S_AXIS_CQP_USER_WIDTH = "85" *) 
  (* C_S_AXIS_CQ_USER_WIDTH = "85" *) 
  (* C_S_AXIS_DATA_WIDTH = "64" *) 
  (* C_S_AXIS_USER_WIDTH = "64" *) 
  (* C_S_AXI_ADDR_WIDTH = "64" *) 
  (* C_S_AXI_DATA_WIDTH = "64" *) 
  (* C_S_AXI_ID_WIDTH = "4" *) 
  (* C_S_AXI_NUM_READ = "8" *) 
  (* C_S_AXI_NUM_WRITE = "8" *) 
  (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *) 
  (* C_S_KEEP_WIDTH = "2" *) 
  (* C_TIMEOUT0_SEL = "4'b1110" *) 
  (* C_TIMEOUT1_SEL = "4'b1111" *) 
  (* C_TIMEOUT_MULT = "3'b011" *) 
  (* C_USER_PTR = "16'b0000000011011000" *) 
  (* C_VSEC_CAP_ADDR = "12'b000100101000" *) 
  (* C_VSEC_CAP_LAST = "FALSE" *) 
  (* C_VSEC_ID = "16'b0000000000000000" *) 
  (* DAT_WIDTH = "64" *) 
  (* DEDICATE_PERST = "true" *) 
  (* DEV_PORT_TYPE = "0" *) 
  (* DIFF_AXI_ADDR_WIDTH = "0" *) 
  (* DISABLE_BRAM_PIPELINE = "FALSE" *) 
  (* DISABLE_EQ_SYNCHRONIZER = "FALSE" *) 
  (* DMA_2RP = "FALSE" *) 
  (* DMA_EN = "1" *) 
  (* DMA_MM = "1" *) 
  (* DMA_RESET_SOURCE_SEL = "0" *) 
  (* DMA_SP = "0" *) 
  (* DMA_ST = "0" *) 
  (* DRP_CLK_SEL = "0" *) 
  (* DSC_BYPASS_RD = "0" *) 
  (* DSC_BYPASS_WR = "0" *) 
  (* EGW_IS_PARENT_IP = "1" *) 
  (* ENABLE_ATS_SWITCH = "FALSE" *) 
  (* ENABLE_ERROR_INJECTION = "FALSE" *) 
  (* ENABLE_IBERT = "FALSE" *) 
  (* ENABLE_JTAG_DBG = "FALSE" *) 
  (* ENABLE_LTSSM_DBG = "FALSE" *) 
  (* ENABLE_MORE = "FALSE" *) 
  (* EN_AXI_MASTER_IF = "TRUE" *) 
  (* EN_AXI_SLAVE_IF = "TRUE" *) 
  (* EN_DEBUG_PORTS = "FALSE" *) 
  (* EN_GT_SELECTION = "FALSE" *) 
  (* EN_PCIE_DEBUG_PORTS = "FALSE" *) 
  (* EN_RCHNL_0 = "TRUE" *) 
  (* EN_RCHNL_1 = "FALSE" *) 
  (* EN_RCHNL_2 = "FALSE" *) 
  (* EN_RCHNL_3 = "FALSE" *) 
  (* EN_RCHNL_4 = "FALSE" *) 
  (* EN_RCHNL_5 = "FALSE" *) 
  (* EN_RCHNL_6 = "FALSE" *) 
  (* EN_RCHNL_7 = "FALSE" *) 
  (* EN_TRANSCEIVER_STATUS_PORTS = "FALSE" *) 
  (* EN_WCHNL_0 = "TRUE" *) 
  (* EN_WCHNL_1 = "FALSE" *) 
  (* EN_WCHNL_2 = "FALSE" *) 
  (* EN_WCHNL_3 = "FALSE" *) 
  (* EN_WCHNL_4 = "FALSE" *) 
  (* EN_WCHNL_5 = "FALSE" *) 
  (* EN_WCHNL_6 = "FALSE" *) 
  (* EN_WCHNL_7 = "FALSE" *) 
  (* ERRC_DEC_EN = "FALSE" *) 
  (* EXT_CH_GT_DRP = "false" *) 
  (* EXT_STARTUP_PRIMITIVE = "false" *) 
  (* EXT_SYS_CLK_BUFG = "FALSE" *) 
  (* EXT_XVC_VSEC_ENABLE = "FALSE" *) 
  (* FIRSTVF_OFFSET_PF0 = "0" *) 
  (* FIRSTVF_OFFSET_PF1 = "0" *) 
  (* FIRSTVF_OFFSET_PF2 = "0" *) 
  (* FIRSTVF_OFFSET_PF3 = "0" *) 
  (* FLR_ENABLE = "FALSE" *) 
  (* FREE_RUN_FREQ = "0" *) 
  (* FUNC_MODE = "1" *) 
  (* GEN4_EIEOS_0S7 = "TRUE" *) 
  (* GTCOM_IN_CORE = "2" *) 
  (* GTWIZ_IN_CORE = "1" *) 
  (* H2C_XDMA_CHNL = "8'b00001111" *) 
  (* IMPL_TARGET = "SOFT" *) 
  (* INS_LOSS_PROFILE = "Add-in_Card" *) 
  (* INTERRUPT_OUT_WIDTH = "1" *) 
  (* IS_BOARD_PROJECT = "0" *) 
  (* LEGACY_CFG_EXT_IF = "FALSE" *) 
  (* MCAP_ENABLEMENT = "NONE" *) 
  (* MCAP_FPGA_BITSTREAM_VERSION = "0" *) 
  (* MM_SLAVE_EN = "0" *) 
  (* MSIX_ENABLED = "FALSE" *) 
  (* MSIX_IMPL_EXT = "FALSE" *) 
  (* MSIX_PCIE_INTERNAL = "0" *) 
  (* MSIX_RX_DECODE_EN = "FALSE" *) 
  (* MSIX_VEC_NUM = "1024" *) 
  (* MSI_ENABLED = "TRUE" *) 
  (* MULTQ_CHNL = "8'b00000000" *) 
  (* MULTQ_EN = "0" *) 
  (* MULT_PF_DES = "FALSE" *) 
  (* MULT_PF_DESIGN = "0" *) 
  (* NUM_PFS = "1" *) 
  (* NUM_VFS_PF0 = "0" *) 
  (* NUM_VFS_PF1 = "0" *) 
  (* NUM_VFS_PF2 = "0" *) 
  (* NUM_VFS_PF3 = "0" *) 
  (* PCIE3_DRP = "false" *) 
  (* PCIEBAR_NUM = "6" *) 
  (* PCIE_BLK_LOCN = "0" *) 
  (* PCIE_BLK_TYPE = "0" *) 
  (* PCIE_ID_IF = "FALSE" *) 
  (* PF0_BAR0_APERTURE_SIZE = "8'b00001010" *) 
  (* PF0_BAR0_CONTROL = "3'b100" *) 
  (* PF0_BAR1_APERTURE_SIZE = "8'b00000101" *) 
  (* PF0_BAR1_CONTROL = "3'b000" *) 
  (* PF0_BAR2_APERTURE_SIZE = "8'b00000101" *) 
  (* PF0_BAR2_CONTROL = "3'b000" *) 
  (* PF0_BAR3_APERTURE_SIZE = "8'b00000101" *) 
  (* PF0_BAR3_CONTROL = "3'b000" *) 
  (* PF0_BAR4_APERTURE_SIZE = "8'b00000101" *) 
  (* PF0_BAR4_CONTROL = "3'b000" *) 
  (* PF0_BAR5_APERTURE_SIZE = "8'b00000101" *) 
  (* PF0_BAR5_CONTROL = "3'b000" *) 
  (* PF0_CLASS_CODE = "24'b000001110000000000000001" *) 
  (* PF0_DEVICE_ID = "16'b0111000000100010" *) 
  (* PF0_EXPANSION_ROM_APERTURE_SIZE = "5'b00000" *) 
  (* PF0_EXPANSION_ROM_ENABLE = "FALSE" *) 
  (* PF0_INTERRUPT_PIN = "3'b001" *) 
  (* PF0_MSIX_TAR_ID = "6'b001000" *) 
  (* PF0_MSI_CAP_MULTIMSGCAP = "0" *) 
  (* PF0_REVISION_ID = "8'b00000000" *) 
  (* PF0_SUBSYSTEM_ID = "16'b0000000000000111" *) 
  (* PF0_SUBSYSTEM_VENDOR_ID = "16'b0001000011101110" *) 
  (* PF0_VENDOR_ID = "16'b0001000011101110" *) 
  (* PF1_BAR0_APERTURE_SIZE = "8'b00010010" *) 
  (* PF1_BAR0_CONTROL = "3'b100" *) 
  (* PF1_BAR1_APERTURE_SIZE = "8'b00001010" *) 
  (* PF1_BAR1_CONTROL = "3'b100" *) 
  (* PF1_BAR2_APERTURE_SIZE = "8'b00001010" *) 
  (* PF1_BAR2_CONTROL = "3'b110" *) 
  (* PF1_BAR3_APERTURE_SIZE = "8'b00001010" *) 
  (* PF1_BAR3_CONTROL = "3'b000" *) 
  (* PF1_BAR4_APERTURE_SIZE = "8'b00001010" *) 
  (* PF1_BAR4_CONTROL = "3'b110" *) 
  (* PF1_BAR5_APERTURE_SIZE = "8'b00001010" *) 
  (* PF1_BAR5_CONTROL = "3'b000" *) 
  (* PF1_CLASS_CODE = "24'b000001110000000000000001" *) 
  (* PF1_DEVICE_ID = "16'b0001000001000001" *) 
  (* PF1_ENABLED = "0" *) 
  (* PF1_EXPANSION_ROM_APERTURE_SIZE = "5'b00000" *) 
  (* PF1_EXPANSION_ROM_ENABLE = "FALSE" *) 
  (* PF1_MSIX_TAR_ID = "6'b001001" *) 
  (* PF1_PCIEBAR2AXIBAR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* PF1_PCIEBAR2AXIBAR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* PF1_PCIEBAR2AXIBAR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* PF1_PCIEBAR2AXIBAR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* PF1_PCIEBAR2AXIBAR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* PF1_PCIEBAR2AXIBAR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* PF1_PCIEBAR2AXIBAR_6 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* PF1_REVISION_ID = "8'b00000000" *) 
  (* PF1_SUBSYSTEM_ID = "16'b0000000000000111" *) 
  (* PF1_SUBSYSTEM_VENDOR_ID = "16'b0001000011101110" *) 
  (* PF1_VENDOR_ID = "16'b0001000011101110" *) 
  (* PF2_DEVICE_ID = "16'b0001000001000000" *) 
  (* PF2_ENABLED = "0" *) 
  (* PF2_REVISION_ID = "8'b00000000" *) 
  (* PF2_SUBSYSTEM_ID = "16'b0000000000000111" *) 
  (* PF3_DEVICE_ID = "16'b0001000000111001" *) 
  (* PF3_ENABLED = "0" *) 
  (* PF3_REVISION_ID = "8'b00000000" *) 
  (* PF3_SUBSYSTEM_ID = "16'b0000000000000111" *) 
  (* PF_SWAP = "FALSE" *) 
  (* PIPE_DEBUG_EN = "FALSE" *) 
  (* PIPE_LINE_STAGE = "2" *) 
  (* PIPE_SIM = "FALSE" *) 
  (* PLL_TYPE = "2" *) 
  (* PL_DISABLE_UPCONFIG_CAPABLE = "FALSE" *) 
  (* PL_LINK_CAP_MAX_LINK_SPEED = "2" *) 
  (* PL_LINK_CAP_MAX_LINK_WIDTH = "2" *) 
  (* PL_UPSTREAM_FACING = "true" *) 
  (* PMON_EN = "1" *) 
  (* PROG_USR_IRQ_VEC_MAP = "0" *) 
  (* RBAR_ENABLE = "FALSE" *) 
  (* RD_CH0_ENABLED = "FALSE" *) 
  (* RD_CH1_ENABLED = "FALSE" *) 
  (* RD_CH2_ENABLED = "FALSE" *) 
  (* RD_CH3_ENABLED = "FALSE" *) 
  (* REF_CLK_FREQ = "0" *) 
  (* RQ_SEQ_NUM_IGNORE = "0" *) 
  (* RUNBIT_FIX = "FALSE" *) 
  (* RUN_BIT_FIX = "0" *) 
  (* RX_DETECT = "0" *) 
  (* SELECT_QUAD = "GTH_Quad_128" *) 
  (* SHARED_LOGIC = "0" *) 
  (* SHARED_LOGIC_BOTH = "false" *) 
  (* SHARED_LOGIC_BOTH_7XG2 = "false" *) 
  (* SHARED_LOGIC_CLK = "false" *) 
  (* SHARED_LOGIC_CLK_7XG2 = "false" *) 
  (* SHARED_LOGIC_GTC = "false" *) 
  (* SHARED_LOGIC_GTC_7XG2 = "false" *) 
  (* SHELL_BRIDGE = "0" *) 
  (* SILICON_REV = "Pre-Production" *) 
  (* SOFT_RESET_EN = "FALSE" *) 
  (* SPLIT_DMA = "FALSE" *) 
  (* SPLIT_DMA_SINGLE_PF = "FALSE" *) 
  (* SRIOV_ACTIVE_VFS = "252" *) 
  (* SRIOV_EN = "0" *) 
  (* STS_WIDTH = "8" *) 
  (* SYS_RESET_POLARITY = "0" *) 
  (* TANDEM_RFSOC = "FALSE" *) 
  (* TCQ = "1" *) 
  (* TL_LEGACY_MODE_ENABLE = "false" *) 
  (* TL_PF_ENABLE_REG = "2'b00" *) 
  (* ULTRASCALE = "FALSE" *) 
  (* ULTRASCALE_PLUS = "FALSE" *) 
  (* USER_CLK_FREQ = "1" *) 
  (* USE_ATTR = "0" *) 
  (* USE_STANDARD_INTERFACES = "FALSE" *) 
  (* USRINT_EXPN = "FALSE" *) 
  (* USR_INT_EXPN = "0" *) 
  (* USR_IRQ_EXDES = "FALSE" *) 
  (* USR_MPL_SIZE = "4096" *) 
  (* USR_MRS_SIZE = "4096" *) 
  (* V7_GEN3 = "FALSE" *) 
  (* VCU118_BOARD = "FALSE" *) 
  (* VCU1262 = "FALSE" *) 
  (* VDM_EN = "FALSE" *) 
  (* VERSAL = "FALSE" *) 
  (* VERSAL_PART_TYPE = "SXX" *) 
  (* VERSION = "6" *) 
  (* VF_BARLITE_EXT_PF0 = "6'b000000" *) 
  (* VF_BARLITE_EXT_PF1 = "6'b000000" *) 
  (* VF_BARLITE_EXT_PF2 = "6'b000000" *) 
  (* VF_BARLITE_EXT_PF3 = "6'b000000" *) 
  (* VF_BARLITE_INT_PF0 = "6'b000001" *) 
  (* VF_BARLITE_INT_PF1 = "6'b000001" *) 
  (* VF_BARLITE_INT_PF2 = "6'b000001" *) 
  (* VF_BARLITE_INT_PF3 = "6'b000001" *) 
  (* VU9P_BOARD = "FALSE" *) 
  (* VU9P_TUL_EX = "FALSE" *) 
  (* WR_CH0_ENABLED = "FALSE" *) 
  (* WR_CH1_ENABLED = "FALSE" *) 
  (* WR_CH2_ENABLED = "FALSE" *) 
  (* WR_CH3_ENABLED = "FALSE" *) 
  (* XDMA_APERTURE_SIZE = "8'b00001001" *) 
  (* XDMA_AXILITE_MASTER = "FALSE" *) 
  (* XDMA_AXILITE_SLAVE = "FALSE" *) 
  (* XDMA_AXIST_BYPASS = "TRUE" *) 
  (* XDMA_AXI_INTF_MM = "1" *) 
  (* XDMA_CONTROL = "3'b100" *) 
  (* XDMA_DSC_BYPASS = "FALSE" *) 
  (* XDMA_DSC_ENG = "1" *) 
  (* XDMA_NON_INCREMENTAL_EXDES = "FALSE" *) 
  (* XDMA_NUM_PCIE_TAG = "64" *) 
  (* XDMA_NUM_USR_IRQ = "1" *) 
  (* XDMA_PCIE_64BIT_EN = "xdma_pcie_64bit_en" *) 
  (* XDMA_RNUM_CHNL = "1" *) 
  (* XDMA_RNUM_RIDS = "32" *) 
  (* XDMA_STS_PORTS = "FALSE" *) 
  (* XDMA_ST_INFINITE_DESC_EXDES = "FALSE" *) 
  (* XDMA_WNUM_CHNL = "1" *) 
  (* XDMA_WNUM_RIDS = "16" *) 
  (* xlnx_ref_board = "None" *) 
  xdma_0_core_top inst
       (.Integrated_bloc_reset_o(NLW_inst_Integrated_bloc_reset_o_UNCONNECTED),
        .ats_pri_en(NLW_inst_ats_pri_en_UNCONNECTED),
        .atspri_m_axis_cq_tdata(NLW_inst_atspri_m_axis_cq_tdata_UNCONNECTED[63:0]),
        .atspri_m_axis_cq_tkeep(NLW_inst_atspri_m_axis_cq_tkeep_UNCONNECTED[1:0]),
        .atspri_m_axis_cq_tlast(NLW_inst_atspri_m_axis_cq_tlast_UNCONNECTED),
        .atspri_m_axis_cq_tready(1'b0),
        .atspri_m_axis_cq_tuser(NLW_inst_atspri_m_axis_cq_tuser_UNCONNECTED[84:0]),
        .atspri_m_axis_cq_tvalid(NLW_inst_atspri_m_axis_cq_tvalid_UNCONNECTED),
        .atspri_s_axis_rq_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .atspri_s_axis_rq_tkeep({1'b0,1'b0}),
        .atspri_s_axis_rq_tlast(1'b0),
        .atspri_s_axis_rq_tready(NLW_inst_atspri_s_axis_rq_tready_UNCONNECTED),
        .atspri_s_axis_rq_tuser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .atspri_s_axis_rq_tvalid(1'b0),
        .axi_aclk(axi_aclk),
        .axi_aresetn(axi_aresetn),
        .axi_ctl_aclk(1'b0),
        .axi_ctl_aresetn(NLW_inst_axi_ctl_aresetn_UNCONNECTED),
        .bufgtce_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .bufgtce_usp_out({1'b0,1'b0}),
        .bufgtcemask_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .bufgtcemask_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .bufgtdiv_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .bufgtdiv_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .bufgtreset_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .bufgtreset_usp_out({1'b0,1'b0}),
        .bufgtrstmask_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .bufgtrstmask_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_ctl_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_ctl_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_ctl_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_ctl_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_dst_addr_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_dst_addr_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_dst_addr_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_dst_addr_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_len_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_len_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_len_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_len_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_load_0(1'b0),
        .c2h_dsc_byp_load_1(1'b0),
        .c2h_dsc_byp_load_2(1'b0),
        .c2h_dsc_byp_load_3(1'b0),
        .c2h_dsc_byp_ready_0(NLW_inst_c2h_dsc_byp_ready_0_UNCONNECTED),
        .c2h_dsc_byp_ready_1(NLW_inst_c2h_dsc_byp_ready_1_UNCONNECTED),
        .c2h_dsc_byp_ready_2(NLW_inst_c2h_dsc_byp_ready_2_UNCONNECTED),
        .c2h_dsc_byp_ready_3(NLW_inst_c2h_dsc_byp_ready_3_UNCONNECTED),
        .c2h_dsc_byp_src_addr_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_src_addr_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_src_addr_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_src_addr_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_sts_0(NLW_inst_c2h_sts_0_UNCONNECTED[7:0]),
        .c2h_sts_1(NLW_inst_c2h_sts_1_UNCONNECTED[7:0]),
        .c2h_sts_2(NLW_inst_c2h_sts_2_UNCONNECTED[7:0]),
        .c2h_sts_3(NLW_inst_c2h_sts_3_UNCONNECTED[7:0]),
        .cap_gnt(1'b1),
        .cap_rel(1'b0),
        .cap_req(NLW_inst_cap_req_UNCONNECTED),
        .ccix_optimized_tlp_tx_and_rx_enable_in(1'b0),
        .cfg_aer_interrupt_msgnum_i(cfg_aer_interrupt_msgnum_i),
        .cfg_bus_number_o(cfg_bus_number_o),
        .cfg_config_space_enable_sd(NLW_inst_cfg_config_space_enable_sd_UNCONNECTED),
        .cfg_current_speed_o(NLW_inst_cfg_current_speed_o_UNCONNECTED[2:0]),
        .cfg_current_speed_sd({1'b0,1'b0}),
        .cfg_dev_id_pf0({1'b0,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b1,1'b0}),
        .cfg_dev_id_pf1({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
        .cfg_dev_id_pf2({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_dev_id_pf3({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b0,1'b1}),
        .cfg_device_number_o(cfg_device_number_o),
        .cfg_ds_bus_number_sd(NLW_inst_cfg_ds_bus_number_sd_UNCONNECTED[7:0]),
        .cfg_ds_device_number_sd(NLW_inst_cfg_ds_device_number_sd_UNCONNECTED[4:0]),
        .cfg_ds_function_number_sd(NLW_inst_cfg_ds_function_number_sd_UNCONNECTED[2:0]),
        .cfg_ds_port_number_sd(NLW_inst_cfg_ds_port_number_sd_UNCONNECTED[7:0]),
        .cfg_dsn_i(cfg_dsn_i),
        .cfg_dsn_sd(NLW_inst_cfg_dsn_sd_UNCONNECTED[63:0]),
        .cfg_err_aer_headerlog_i(cfg_err_aer_headerlog_i),
        .cfg_err_cor_in_sd(NLW_inst_cfg_err_cor_in_sd_UNCONNECTED),
        .cfg_err_cor_o(NLW_inst_cfg_err_cor_o_UNCONNECTED),
        .cfg_err_cor_out_sd(1'b0),
        .cfg_err_fatal_o(NLW_inst_cfg_err_fatal_o_UNCONNECTED),
        .cfg_err_fatal_out_sd(1'b0),
        .cfg_err_nonfatal_o(NLW_inst_cfg_err_nonfatal_o_UNCONNECTED),
        .cfg_err_nonfatal_out_sd(1'b0),
        .cfg_err_tlp_cpl_header_i(cfg_err_tlp_cpl_header_i),
        .cfg_err_uncor_in_sd(NLW_inst_cfg_err_uncor_in_sd_UNCONNECTED),
        .cfg_ext_function_number(NLW_inst_cfg_ext_function_number_UNCONNECTED[7:0]),
        .cfg_ext_read_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_ext_read_data_valid(1'b0),
        .cfg_ext_read_received(NLW_inst_cfg_ext_read_received_UNCONNECTED),
        .cfg_ext_register_number(NLW_inst_cfg_ext_register_number_UNCONNECTED[9:0]),
        .cfg_ext_write_byte_enable(NLW_inst_cfg_ext_write_byte_enable_UNCONNECTED[3:0]),
        .cfg_ext_write_data(NLW_inst_cfg_ext_write_data_UNCONNECTED[31:0]),
        .cfg_ext_write_received(NLW_inst_cfg_ext_write_received_UNCONNECTED),
        .cfg_fc_nph_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_fc_sel_sd(NLW_inst_cfg_fc_sel_sd_UNCONNECTED[2:0]),
        .cfg_fc_vc_sel(1'b0),
        .cfg_flr_done({1'b0,1'b0,1'b0,1'b0}),
        .cfg_flr_done_sd(NLW_inst_cfg_flr_done_sd_UNCONNECTED[3:0]),
        .cfg_flr_in_process(NLW_inst_cfg_flr_in_process_UNCONNECTED[3:0]),
        .cfg_flr_in_process_sd({1'b0,1'b0,1'b0,1'b0}),
        .cfg_function_number_o(cfg_function_number_o),
        .cfg_function_status(NLW_inst_cfg_function_status_UNCONNECTED[7:0]),
        .cfg_function_status_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_hot_reset_out_sd(1'b0),
        .cfg_interrupt_di_i(cfg_interrupt_di_i),
        .cfg_interrupt_int_sd(NLW_inst_cfg_interrupt_int_sd_UNCONNECTED[3:0]),
        .cfg_interrupt_msi_attr_sd(NLW_inst_cfg_interrupt_msi_attr_sd_UNCONNECTED[2:0]),
        .cfg_interrupt_msi_data_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_interrupt_msi_enable(NLW_inst_cfg_interrupt_msi_enable_UNCONNECTED[3:0]),
        .cfg_interrupt_msi_enable_sd({1'b0,1'b0,1'b0,1'b0}),
        .cfg_interrupt_msi_fail(NLW_inst_cfg_interrupt_msi_fail_UNCONNECTED),
        .cfg_interrupt_msi_fail_sd(1'b0),
        .cfg_interrupt_msi_function_number_sd(NLW_inst_cfg_interrupt_msi_function_number_sd_UNCONNECTED[7:0]),
        .cfg_interrupt_msi_int_sd(NLW_inst_cfg_interrupt_msi_int_sd_UNCONNECTED[31:0]),
        .cfg_interrupt_msi_mask_update_sd(1'b0),
        .cfg_interrupt_msi_pending_status_data_enable_sd(NLW_inst_cfg_interrupt_msi_pending_status_data_enable_sd_UNCONNECTED),
        .cfg_interrupt_msi_pending_status_function_num_sd(NLW_inst_cfg_interrupt_msi_pending_status_function_num_sd_UNCONNECTED[3:0]),
        .cfg_interrupt_msi_pending_status_sd(NLW_inst_cfg_interrupt_msi_pending_status_sd_UNCONNECTED[31:0]),
        .cfg_interrupt_msi_sent(NLW_inst_cfg_interrupt_msi_sent_UNCONNECTED),
        .cfg_interrupt_msi_sent_sd(1'b0),
        .cfg_interrupt_msi_tph_present_sd(NLW_inst_cfg_interrupt_msi_tph_present_sd_UNCONNECTED),
        .cfg_interrupt_msi_tph_st_tag_sd(NLW_inst_cfg_interrupt_msi_tph_st_tag_sd_UNCONNECTED[8:0]),
        .cfg_interrupt_msi_tph_type_sd(NLW_inst_cfg_interrupt_msi_tph_type_sd_UNCONNECTED[1:0]),
        .cfg_interrupt_msix_address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_interrupt_msix_address_sd(NLW_inst_cfg_interrupt_msix_address_sd_UNCONNECTED[63:0]),
        .cfg_interrupt_msix_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_interrupt_msix_data_sd(NLW_inst_cfg_interrupt_msix_data_sd_UNCONNECTED[31:0]),
        .cfg_interrupt_msix_enable(NLW_inst_cfg_interrupt_msix_enable_UNCONNECTED[1:0]),
        .cfg_interrupt_msix_enable_sd({1'b0,1'b0,1'b0,1'b0}),
        .cfg_interrupt_msix_fail(NLW_inst_cfg_interrupt_msix_fail_UNCONNECTED),
        .cfg_interrupt_msix_int(1'b0),
        .cfg_interrupt_msix_int_sd(NLW_inst_cfg_interrupt_msix_int_sd_UNCONNECTED),
        .cfg_interrupt_msix_mask(NLW_inst_cfg_interrupt_msix_mask_UNCONNECTED[1:0]),
        .cfg_interrupt_msix_mask_sd({1'b0,1'b0,1'b0,1'b0}),
        .cfg_interrupt_msix_sent(NLW_inst_cfg_interrupt_msix_sent_UNCONNECTED),
        .cfg_interrupt_msix_vec_pending_sd(NLW_inst_cfg_interrupt_msix_vec_pending_sd_UNCONNECTED[1:0]),
        .cfg_interrupt_msix_vec_pending_status_sd(1'b0),
        .cfg_interrupt_msix_vf_enable_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_interrupt_msix_vf_mask_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_interrupt_pending_sd(NLW_inst_cfg_interrupt_pending_sd_UNCONNECTED[3:0]),
        .cfg_interrupt_sent_sd(1'b0),
        .cfg_link_training_enable_sd(NLW_inst_cfg_link_training_enable_sd_UNCONNECTED),
        .cfg_local_error_o(NLW_inst_cfg_local_error_o_UNCONNECTED[4:0]),
        .cfg_local_error_out_sd({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_local_error_valid_o(NLW_inst_cfg_local_error_valid_o_UNCONNECTED),
        .cfg_ltssm_state(NLW_inst_cfg_ltssm_state_UNCONNECTED[5:0]),
        .cfg_ltssm_state_o(NLW_inst_cfg_ltssm_state_o_UNCONNECTED[5:0]),
        .cfg_ltssm_state_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_max_payload(NLW_inst_cfg_max_payload_UNCONNECTED[2:0]),
        .cfg_max_payload_sd({1'b0,1'b0}),
        .cfg_max_read_req(NLW_inst_cfg_max_read_req_UNCONNECTED[2:0]),
        .cfg_max_read_req_sd({1'b0,1'b0,1'b0}),
        .cfg_mgmt_addr(cfg_mgmt_addr),
        .cfg_mgmt_addr_sd(NLW_inst_cfg_mgmt_addr_sd_UNCONNECTED[9:0]),
        .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
        .cfg_mgmt_byte_enable_sd(NLW_inst_cfg_mgmt_byte_enable_sd_UNCONNECTED[3:0]),
        .cfg_mgmt_di_i(cfg_mgmt_di_i),
        .cfg_mgmt_dwaddr_i(cfg_mgmt_dwaddr_i),
        .cfg_mgmt_function_number_sd(NLW_inst_cfg_mgmt_function_number_sd_UNCONNECTED[7:0]),
        .cfg_mgmt_read(cfg_mgmt_read),
        .cfg_mgmt_read_data(cfg_mgmt_read_data),
        .cfg_mgmt_read_data_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_mgmt_read_sd(NLW_inst_cfg_mgmt_read_sd_UNCONNECTED),
        .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
        .cfg_mgmt_read_write_done_sd(1'b0),
        .cfg_mgmt_type1_cfg_reg_access(cfg_mgmt_type1_cfg_reg_access),
        .cfg_mgmt_type1_cfg_reg_access_sd(NLW_inst_cfg_mgmt_type1_cfg_reg_access_sd_UNCONNECTED),
        .cfg_mgmt_write(cfg_mgmt_write),
        .cfg_mgmt_write_data(cfg_mgmt_write_data),
        .cfg_mgmt_write_data_sd(NLW_inst_cfg_mgmt_write_data_sd_UNCONNECTED[31:0]),
        .cfg_mgmt_write_sd(NLW_inst_cfg_mgmt_write_sd_UNCONNECTED),
        .cfg_msg_received_data_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_msg_received_sd(1'b0),
        .cfg_msg_received_type_sd({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_msg_transmit_data_sd(NLW_inst_cfg_msg_transmit_data_sd_UNCONNECTED[31:0]),
        .cfg_msg_transmit_done_sd(1'b0),
        .cfg_msg_transmit_sd(NLW_inst_cfg_msg_transmit_sd_UNCONNECTED),
        .cfg_msg_transmit_type_sd(NLW_inst_cfg_msg_transmit_type_sd_UNCONNECTED[2:0]),
        .cfg_negotiated_width_o(NLW_inst_cfg_negotiated_width_o_UNCONNECTED[3:0]),
        .cfg_negotiated_width_sd({1'b0,1'b0,1'b0}),
        .cfg_pciecap_interrupt_msgnum_i(cfg_pciecap_interrupt_msgnum_i),
        .cfg_phy_link_down_sd(1'b0),
        .cfg_phy_link_status_sd({1'b0,1'b0}),
        .cfg_pl_status_change_sd(1'b0),
        .cfg_pm_force_state_i(cfg_pm_force_state_i),
        .cfg_rev_id_pf0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_rev_id_pf1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_rev_id_pf2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_rev_id_pf3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_status_ats_en(NLW_inst_cfg_status_ats_en_UNCONNECTED),
        .cfg_status_ats_stu(NLW_inst_cfg_status_ats_stu_UNCONNECTED[4:0]),
        .cfg_status_clr_s(1'b0),
        .cfg_status_ost_pr_alloc(NLW_inst_cfg_status_ost_pr_alloc_UNCONNECTED[31:0]),
        .cfg_status_pr_en(NLW_inst_cfg_status_pr_en_UNCONNECTED),
        .cfg_status_pr_rf(NLW_inst_cfg_status_pr_rf_UNCONNECTED),
        .cfg_status_pr_rst(NLW_inst_cfg_status_pr_rst_UNCONNECTED),
        .cfg_status_pr_uprgi(NLW_inst_cfg_status_pr_uprgi_UNCONNECTED),
        .cfg_status_set_rf(1'b0),
        .cfg_status_set_s(1'b0),
        .cfg_status_set_uprgi(1'b0),
        .cfg_subsys_id_pf0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}),
        .cfg_subsys_id_pf1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}),
        .cfg_subsys_id_pf2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}),
        .cfg_subsys_id_pf3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}),
        .cfg_subsys_vend_id({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b1,1'b1,1'b1,1'b0}),
        .cfg_to_turnoff_o(cfg_to_turnoff_o),
        .cfg_turnoff_ok_i(cfg_turnoff_ok_i),
        .cfg_vend_id({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b1,1'b1,1'b1,1'b0}),
        .cfg_vf_flr_done(1'b0),
        .cfg_vf_flr_func_num({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_vf_flr_in_process(NLW_inst_cfg_vf_flr_in_process_UNCONNECTED[251:0]),
        .cfg_vf_flr_in_process_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .common_commands_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .common_commands_out(NLW_inst_common_commands_out_UNCONNECTED[25:0]),
        .config_space_enable(1'b1),
        .core_clk(NLW_inst_core_clk_UNCONNECTED),
        .cpllfreqlock_usp_in(NLW_inst_cpllfreqlock_usp_in_UNCONNECTED[1:0]),
        .cplllock_us_out({1'b0,1'b0}),
        .cplllock_usp_out({1'b0,1'b0}),
        .cpllpd_us_in(NLW_inst_cpllpd_us_in_UNCONNECTED[1:0]),
        .cpllpd_usp_in(NLW_inst_cpllpd_usp_in_UNCONNECTED[1:0]),
        .cpllreset_us_in(NLW_inst_cpllreset_us_in_UNCONNECTED[1:0]),
        .cpllreset_usp_in(NLW_inst_cpllreset_usp_in_UNCONNECTED[1:0]),
        .cxs0_active_ack_rx(1'b0),
        .cxs0_active_ack_tx(NLW_inst_cxs0_active_ack_tx_UNCONNECTED),
        .cxs0_active_req_rx(NLW_inst_cxs0_active_req_rx_UNCONNECTED),
        .cxs0_active_req_tx(1'b0),
        .cxs0_cntl_chk_rx(NLW_inst_cxs0_cntl_chk_rx_UNCONNECTED),
        .cxs0_cntl_chk_tx(1'b0),
        .cxs0_cntl_rx(NLW_inst_cxs0_cntl_rx_UNCONNECTED[13:0]),
        .cxs0_cntl_tx({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cxs0_crdgnt_chk_rx(1'b0),
        .cxs0_crdgnt_chk_tx(NLW_inst_cxs0_crdgnt_chk_tx_UNCONNECTED),
        .cxs0_crdgnt_rx(1'b0),
        .cxs0_crdgnt_tx(NLW_inst_cxs0_crdgnt_tx_UNCONNECTED),
        .cxs0_crdrtn_chk_rx(NLW_inst_cxs0_crdrtn_chk_rx_UNCONNECTED),
        .cxs0_crdrtn_chk_tx(1'b0),
        .cxs0_crdrtn_rx(NLW_inst_cxs0_crdrtn_rx_UNCONNECTED),
        .cxs0_crdrtn_tx(1'b0),
        .cxs0_data_chk_rx(NLW_inst_cxs0_data_chk_rx_UNCONNECTED[31:0]),
        .cxs0_data_chk_tx({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cxs0_data_rx(NLW_inst_cxs0_data_rx_UNCONNECTED[255:0]),
        .cxs0_data_tx({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cxs0_deact_hint_rx(1'b0),
        .cxs0_deact_hint_tx(NLW_inst_cxs0_deact_hint_tx_UNCONNECTED),
        .cxs0_valid_chk_rx(NLW_inst_cxs0_valid_chk_rx_UNCONNECTED),
        .cxs0_valid_chk_tx(1'b0),
        .cxs0_valid_rx(NLW_inst_cxs0_valid_rx_UNCONNECTED),
        .cxs0_valid_tx(1'b0),
        .dma_bridge_resetn(1'b1),
        .dmonfiforeset_us_in(NLW_inst_dmonfiforeset_us_in_UNCONNECTED[1:0]),
        .dmonfiforeset_usp_in(NLW_inst_dmonfiforeset_usp_in_UNCONNECTED[1:0]),
        .dmonitorclk_us_in(NLW_inst_dmonitorclk_us_in_UNCONNECTED[1:0]),
        .dmonitorclk_usp_in(NLW_inst_dmonitorclk_usp_in_UNCONNECTED[1:0]),
        .dmonitorout_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .dmonitorout_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .drp_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .drp_clk(1'b0),
        .drp_di({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .drp_do(NLW_inst_drp_do_UNCONNECTED[15:0]),
        .drp_en(1'b0),
        .drp_rdy(NLW_inst_drp_rdy_UNCONNECTED),
        .drp_we(1'b0),
        .drpaddr_us_in(NLW_inst_drpaddr_us_in_UNCONNECTED[17:0]),
        .drpaddr_usp_in(NLW_inst_drpaddr_usp_in_UNCONNECTED[19:0]),
        .drpclk_us_in(NLW_inst_drpclk_us_in_UNCONNECTED[1:0]),
        .drpclk_usp_in(NLW_inst_drpclk_usp_in_UNCONNECTED),
        .drpdi_us_in(NLW_inst_drpdi_us_in_UNCONNECTED[31:0]),
        .drpdi_usp_in(NLW_inst_drpdi_usp_in_UNCONNECTED[31:0]),
        .drpdo_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .drpdo_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .drpen_us_in(NLW_inst_drpen_us_in_UNCONNECTED[1:0]),
        .drpen_usp_in(NLW_inst_drpen_usp_in_UNCONNECTED[1:0]),
        .drprdy_us_out({1'b0,1'b0}),
        .drprdy_usp_out({1'b0,1'b0}),
        .drprst_usp_in(NLW_inst_drprst_usp_in_UNCONNECTED[1:0]),
        .drpwe_us_in(NLW_inst_drpwe_us_in_UNCONNECTED[1:0]),
        .drpwe_usp_in(NLW_inst_drpwe_usp_in_UNCONNECTED[1:0]),
        .ext_ch_gt_drpaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ext_ch_gt_drpclk(NLW_inst_ext_ch_gt_drpclk_UNCONNECTED),
        .ext_ch_gt_drpdi({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ext_ch_gt_drpdo(NLW_inst_ext_ch_gt_drpdo_UNCONNECTED[31:0]),
        .ext_ch_gt_drpen({1'b0,1'b0}),
        .ext_ch_gt_drprdy(NLW_inst_ext_ch_gt_drprdy_UNCONNECTED[1:0]),
        .ext_ch_gt_drpwe({1'b0,1'b0}),
        .ext_phy_clk_bufg_gt_ce(NLW_inst_ext_phy_clk_bufg_gt_ce_UNCONNECTED),
        .ext_phy_clk_bufg_gt_reset(NLW_inst_ext_phy_clk_bufg_gt_reset_UNCONNECTED),
        .ext_phy_clk_bufgtcemask(NLW_inst_ext_phy_clk_bufgtcemask_UNCONNECTED),
        .ext_phy_clk_bufgtdiv(NLW_inst_ext_phy_clk_bufgtdiv_UNCONNECTED[8:0]),
        .ext_phy_clk_gt_bufgtrstmask(NLW_inst_ext_phy_clk_gt_bufgtrstmask_UNCONNECTED),
        .ext_phy_clk_int_clock(1'b0),
        .ext_phy_clk_pclk(1'b0),
        .ext_phy_clk_pclk2_gt(1'b0),
        .ext_phy_clk_phy_coreclk(1'b0),
        .ext_phy_clk_phy_mcapclk(1'b0),
        .ext_phy_clk_phy_pclk2(1'b0),
        .ext_phy_clk_phy_userclk(1'b0),
        .ext_phy_clk_rst_idle(NLW_inst_ext_phy_clk_rst_idle_UNCONNECTED),
        .ext_phy_clk_txoutclk(NLW_inst_ext_phy_clk_txoutclk_UNCONNECTED),
        .ext_qpll1lock_out(1'b0),
        .ext_qpll1outclk_out(1'b0),
        .ext_qpll1outrefclk_out(1'b0),
        .ext_qpll1pd(NLW_inst_ext_qpll1pd_UNCONNECTED[0]),
        .ext_qpll1rate(NLW_inst_ext_qpll1rate_UNCONNECTED[2:0]),
        .ext_qpll1refclk(NLW_inst_ext_qpll1refclk_UNCONNECTED[0]),
        .ext_qpll1reset(NLW_inst_ext_qpll1reset_UNCONNECTED[0]),
        .ext_usp_qpll0lock_out(1'b0),
        .ext_usp_qpll0outclk_out(1'b0),
        .ext_usp_qpll0outrefclk_out(1'b0),
        .ext_usp_qpll0pd(NLW_inst_ext_usp_qpll0pd_UNCONNECTED[0]),
        .ext_usp_qpll0reset(NLW_inst_ext_usp_qpll0reset_UNCONNECTED[0]),
        .ext_usp_qpll1lock_out(1'b0),
        .ext_usp_qpll1outclk_out(1'b0),
        .ext_usp_qpll1outrefclk_out(1'b0),
        .ext_usp_qpll1pd(NLW_inst_ext_usp_qpll1pd_UNCONNECTED[0]),
        .ext_usp_qpll1reset(NLW_inst_ext_usp_qpll1reset_UNCONNECTED[0]),
        .ext_usp_qpllxrate(NLW_inst_ext_usp_qpllxrate_UNCONNECTED[2:0]),
        .ext_usp_qpllxrcalenb(NLW_inst_ext_usp_qpllxrcalenb_UNCONNECTED),
        .ext_usp_qpllxrefclk(NLW_inst_ext_usp_qpllxrefclk_UNCONNECTED[0]),
        .eyescandataerror_us_out({1'b0,1'b0}),
        .eyescanreset_us_in(NLW_inst_eyescanreset_us_in_UNCONNECTED[1:0]),
        .eyescanreset_usp_in(NLW_inst_eyescanreset_usp_in_UNCONNECTED[1:0]),
        .fc_sel_i(fc_sel_i),
        .free_run_clock(1'b0),
        .gt_bufgtdiv(NLW_inst_gt_bufgtdiv_UNCONNECTED[8:0]),
        .gt_ch_drp_rdy(NLW_inst_gt_ch_drp_rdy_UNCONNECTED[1:0]),
        .gt_cplllock(NLW_inst_gt_cplllock_UNCONNECTED[1:0]),
        .gt_dmonfiforeset({1'b0,1'b0}),
        .gt_dmonitorclk({1'b0,1'b0}),
        .gt_dmonitorout(NLW_inst_gt_dmonitorout_UNCONNECTED[33:0]),
        .gt_drp_clk(NLW_inst_gt_drp_clk_UNCONNECTED),
        .gt_eyescandataerror(NLW_inst_gt_eyescandataerror_UNCONNECTED[1:0]),
        .gt_gen34_eios_det(NLW_inst_gt_gen34_eios_det_UNCONNECTED[1:0]),
        .gt_gtpowergood(NLW_inst_gt_gtpowergood_UNCONNECTED[1:0]),
        .gt_loopback({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .gt_pcierateidle(NLW_inst_gt_pcierateidle_UNCONNECTED[1:0]),
        .gt_pcieuserratedone({1'b0,1'b0}),
        .gt_pcieuserratestart(NLW_inst_gt_pcieuserratestart_UNCONNECTED[1:0]),
        .gt_phystatus(NLW_inst_gt_phystatus_UNCONNECTED[1:0]),
        .gt_qpll0lock(NLW_inst_gt_qpll0lock_UNCONNECTED[0]),
        .gt_qpll1lock(NLW_inst_gt_qpll1lock_UNCONNECTED[0]),
        .gt_rxbufreset({1'b0,1'b0}),
        .gt_rxbufstatus(NLW_inst_gt_rxbufstatus_UNCONNECTED[5:0]),
        .gt_rxcdrlock(NLW_inst_gt_rxcdrlock_UNCONNECTED[1:0]),
        .gt_rxcdrreset({1'b0,1'b0}),
        .gt_rxcommadet(NLW_inst_gt_rxcommadet_UNCONNECTED[1:0]),
        .gt_rxdfelpmreset({1'b0,1'b0}),
        .gt_rxdlysresetdone(NLW_inst_gt_rxdlysresetdone_UNCONNECTED[1:0]),
        .gt_rxoutclk(NLW_inst_gt_rxoutclk_UNCONNECTED[1:0]),
        .gt_rxoutclkfabric(NLW_inst_gt_rxoutclkfabric_UNCONNECTED[1:0]),
        .gt_rxoutclkpcs(NLW_inst_gt_rxoutclkpcs_UNCONNECTED[1:0]),
        .gt_rxpcsreset({1'b0,1'b0}),
        .gt_rxphaligndone(NLW_inst_gt_rxphaligndone_UNCONNECTED[1:0]),
        .gt_rxpmareset({1'b0,1'b0}),
        .gt_rxpmaresetdone(NLW_inst_gt_rxpmaresetdone_UNCONNECTED[1:0]),
        .gt_rxprbscntreset({1'b0,1'b0}),
        .gt_rxprbserr(NLW_inst_gt_rxprbserr_UNCONNECTED[1:0]),
        .gt_rxprbslocked(NLW_inst_gt_rxprbslocked_UNCONNECTED[1:0]),
        .gt_rxprbssel({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .gt_rxrecclkout(NLW_inst_gt_rxrecclkout_UNCONNECTED[1:0]),
        .gt_rxresetdone(NLW_inst_gt_rxresetdone_UNCONNECTED[1:0]),
        .gt_rxstatus(NLW_inst_gt_rxstatus_UNCONNECTED[5:0]),
        .gt_rxsyncdone(NLW_inst_gt_rxsyncdone_UNCONNECTED[1:0]),
        .gt_rxvalid(NLW_inst_gt_rxvalid_UNCONNECTED[1:0]),
        .gt_txdlysresetdone(NLW_inst_gt_txdlysresetdone_UNCONNECTED[1:0]),
        .gt_txelecidle(NLW_inst_gt_txelecidle_UNCONNECTED[1:0]),
        .gt_txinhibit({1'b0,1'b0}),
        .gt_txoutclk(NLW_inst_gt_txoutclk_UNCONNECTED[1:0]),
        .gt_txoutclkfabric(NLW_inst_gt_txoutclkfabric_UNCONNECTED[1:0]),
        .gt_txoutclkpcs(NLW_inst_gt_txoutclkpcs_UNCONNECTED[1:0]),
        .gt_txpcsreset({1'b0,1'b0}),
        .gt_txphaligndone(NLW_inst_gt_txphaligndone_UNCONNECTED[1:0]),
        .gt_txphinitdone(NLW_inst_gt_txphinitdone_UNCONNECTED[1:0]),
        .gt_txpmareset({1'b0,1'b0}),
        .gt_txpmaresetdone(NLW_inst_gt_txpmaresetdone_UNCONNECTED[1:0]),
        .gt_txprbsforceerr({1'b0,1'b0}),
        .gt_txprbssel({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .gt_txprogdivresetdone(NLW_inst_gt_txprogdivresetdone_UNCONNECTED[1:0]),
        .gt_txresetdone(NLW_inst_gt_txresetdone_UNCONNECTED[1:0]),
        .gt_txsyncdone(NLW_inst_gt_txsyncdone_UNCONNECTED[1:0]),
        .gthrxn_us_in(NLW_inst_gthrxn_us_in_UNCONNECTED[1:0]),
        .gthrxp_us_in(NLW_inst_gthrxp_us_in_UNCONNECTED[1:0]),
        .gthtxn_us_out({1'b0,1'b0}),
        .gthtxp_us_out({1'b0,1'b0}),
        .gtpowergood_us_out({1'b0,1'b0}),
        .gtpowergood_usp_out({1'b0,1'b0}),
        .gtrefclk00_usp_in(NLW_inst_gtrefclk00_usp_in_UNCONNECTED[0]),
        .gtrefclk01_us_in(NLW_inst_gtrefclk01_us_in_UNCONNECTED[0]),
        .gtrefclk01_usp_in(NLW_inst_gtrefclk01_usp_in_UNCONNECTED[0]),
        .gtrefclk0_us_in(NLW_inst_gtrefclk0_us_in_UNCONNECTED[1:0]),
        .gtrefclk0_usp_in(NLW_inst_gtrefclk0_usp_in_UNCONNECTED[1:0]),
        .gtrxreset_us_in(NLW_inst_gtrxreset_us_in_UNCONNECTED[1:0]),
        .gtrxreset_usp_in(NLW_inst_gtrxreset_usp_in_UNCONNECTED[1:0]),
        .gttxreset_us_in(NLW_inst_gttxreset_us_in_UNCONNECTED[1:0]),
        .gttxreset_usp_in(NLW_inst_gttxreset_usp_in_UNCONNECTED[1:0]),
        .gtwiz_reset_rx_done_us_in(NLW_inst_gtwiz_reset_rx_done_us_in_UNCONNECTED),
        .gtwiz_reset_rx_done_usp_in(NLW_inst_gtwiz_reset_rx_done_usp_in_UNCONNECTED),
        .gtwiz_reset_tx_done_us_in(NLW_inst_gtwiz_reset_tx_done_us_in_UNCONNECTED),
        .gtwiz_reset_tx_done_usp_in(NLW_inst_gtwiz_reset_tx_done_usp_in_UNCONNECTED),
        .gtwiz_userclk_rx_active_us_in(NLW_inst_gtwiz_userclk_rx_active_us_in_UNCONNECTED),
        .gtwiz_userclk_rx_active_usp_in(NLW_inst_gtwiz_userclk_rx_active_usp_in_UNCONNECTED),
        .gtwiz_userclk_tx_active_us_in(NLW_inst_gtwiz_userclk_tx_active_us_in_UNCONNECTED),
        .gtwiz_userclk_tx_active_usp_in(NLW_inst_gtwiz_userclk_tx_active_usp_in_UNCONNECTED),
        .gtwiz_userclk_tx_reset_us_in(NLW_inst_gtwiz_userclk_tx_reset_us_in_UNCONNECTED),
        .h2c_dsc_byp_ctl_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_ctl_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_ctl_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_ctl_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_dst_addr_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_dst_addr_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_dst_addr_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_dst_addr_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_len_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_len_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_len_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_len_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_load_0(1'b0),
        .h2c_dsc_byp_load_1(1'b0),
        .h2c_dsc_byp_load_2(1'b0),
        .h2c_dsc_byp_load_3(1'b0),
        .h2c_dsc_byp_ready_0(NLW_inst_h2c_dsc_byp_ready_0_UNCONNECTED),
        .h2c_dsc_byp_ready_1(NLW_inst_h2c_dsc_byp_ready_1_UNCONNECTED),
        .h2c_dsc_byp_ready_2(NLW_inst_h2c_dsc_byp_ready_2_UNCONNECTED),
        .h2c_dsc_byp_ready_3(NLW_inst_h2c_dsc_byp_ready_3_UNCONNECTED),
        .h2c_dsc_byp_src_addr_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_src_addr_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_src_addr_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_src_addr_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_sts_0(NLW_inst_h2c_sts_0_UNCONNECTED[7:0]),
        .h2c_sts_1(NLW_inst_h2c_sts_1_UNCONNECTED[7:0]),
        .h2c_sts_2(NLW_inst_h2c_sts_2_UNCONNECTED[7:0]),
        .h2c_sts_3(NLW_inst_h2c_sts_3_UNCONNECTED[7:0]),
        .int_dclk_out(NLW_inst_int_dclk_out_UNCONNECTED),
        .int_oobclk_out(NLW_inst_int_oobclk_out_UNCONNECTED),
        .int_pclk_out_slave(NLW_inst_int_pclk_out_slave_UNCONNECTED),
        .int_pclk_sel_slave({1'b0,1'b0}),
        .int_pipe_rxusrclk_out(NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED),
        .int_qpll1lock_out(NLW_inst_int_qpll1lock_out_UNCONNECTED[0]),
        .int_qpll1outclk_out(NLW_inst_int_qpll1outclk_out_UNCONNECTED[0]),
        .int_qpll1outrefclk_out(NLW_inst_int_qpll1outrefclk_out_UNCONNECTED[0]),
        .int_qplllock_out(NLW_inst_int_qplllock_out_UNCONNECTED[1:0]),
        .int_qplloutclk_out(NLW_inst_int_qplloutclk_out_UNCONNECTED[1:0]),
        .int_qplloutrefclk_out(NLW_inst_int_qplloutrefclk_out_UNCONNECTED[1:0]),
        .int_rxoutclk_out(NLW_inst_int_rxoutclk_out_UNCONNECTED[1:0]),
        .int_userclk1_out(NLW_inst_int_userclk1_out_UNCONNECTED),
        .int_userclk2_out(NLW_inst_int_userclk2_out_UNCONNECTED),
        .int_usp_qpll0lock_out(NLW_inst_int_usp_qpll0lock_out_UNCONNECTED[0]),
        .int_usp_qpll0outclk_out(NLW_inst_int_usp_qpll0outclk_out_UNCONNECTED[0]),
        .int_usp_qpll0outrefclk_out(NLW_inst_int_usp_qpll0outrefclk_out_UNCONNECTED[0]),
        .int_usp_qpll1lock_out(NLW_inst_int_usp_qpll1lock_out_UNCONNECTED[0]),
        .int_usp_qpll1outclk_out(NLW_inst_int_usp_qpll1outclk_out_UNCONNECTED[0]),
        .int_usp_qpll1outrefclk_out(NLW_inst_int_usp_qpll1outrefclk_out_UNCONNECTED[0]),
        .interrupt_out(NLW_inst_interrupt_out_UNCONNECTED),
        .interrupt_out_msi_vec0to31(NLW_inst_interrupt_out_msi_vec0to31_UNCONNECTED),
        .interrupt_out_msi_vec32to63(NLW_inst_interrupt_out_msi_vec32to63_UNCONNECTED),
        .interrupt_out_msix_0(NLW_inst_interrupt_out_msix_0_UNCONNECTED),
        .interrupt_out_msix_1(NLW_inst_interrupt_out_msix_1_UNCONNECTED),
        .interrupt_out_msix_2(NLW_inst_interrupt_out_msix_2_UNCONNECTED),
        .interrupt_out_msix_3(NLW_inst_interrupt_out_msix_3_UNCONNECTED),
        .loopback_us_in(NLW_inst_loopback_us_in_UNCONNECTED[5:0]),
        .loopback_usp_in(NLW_inst_loopback_usp_in_UNCONNECTED[5:0]),
        .m_axi_araddr(m_axi_araddr),
        .m_axi_arburst(m_axi_arburst),
        .m_axi_arcache(m_axi_arcache),
        .m_axi_arid(m_axi_arid),
        .m_axi_arlen(m_axi_arlen),
        .m_axi_arlock(m_axi_arlock),
        .m_axi_arprot(m_axi_arprot),
        .m_axi_arready(m_axi_arready),
        .m_axi_arsize(m_axi_arsize),
        .m_axi_arvalid(m_axi_arvalid),
        .m_axi_awaddr(m_axi_awaddr),
        .m_axi_awburst(m_axi_awburst),
        .m_axi_awcache(m_axi_awcache),
        .m_axi_awid(m_axi_awid),
        .m_axi_awlen(m_axi_awlen),
        .m_axi_awlock(m_axi_awlock),
        .m_axi_awprot(m_axi_awprot),
        .m_axi_awready(m_axi_awready),
        .m_axi_awsize(m_axi_awsize),
        .m_axi_awvalid(m_axi_awvalid),
        .m_axi_bid(m_axi_bid),
        .m_axi_bready(m_axi_bready),
        .m_axi_bresp(m_axi_bresp),
        .m_axi_bvalid(m_axi_bvalid),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rid(m_axi_rid),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rresp(m_axi_rresp),
        .m_axi_ruser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_wdata(m_axi_wdata),
        .m_axi_wlast(m_axi_wlast),
        .m_axi_wready(m_axi_wready),
        .m_axi_wstrb(m_axi_wstrb),
        .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[7:0]),
        .m_axi_wvalid(m_axi_wvalid),
        .m_axib_araddr(m_axib_araddr),
        .m_axib_arburst(m_axib_arburst),
        .m_axib_arcache(m_axib_arcache),
        .m_axib_arid(m_axib_arid),
        .m_axib_arlen(m_axib_arlen),
        .m_axib_arlock(NLW_inst_m_axib_arlock_UNCONNECTED),
        .m_axib_arprot(m_axib_arprot),
        .m_axib_arready(m_axib_arready),
        .m_axib_arsize(m_axib_arsize),
        .m_axib_aruser(NLW_inst_m_axib_aruser_UNCONNECTED[7:0]),
        .m_axib_arvalid(m_axib_arvalid),
        .m_axib_awaddr(m_axib_awaddr),
        .m_axib_awburst(m_axib_awburst),
        .m_axib_awcache(m_axib_awcache),
        .m_axib_awid(m_axib_awid),
        .m_axib_awlen(m_axib_awlen),
        .m_axib_awlock(NLW_inst_m_axib_awlock_UNCONNECTED),
        .m_axib_awprot(m_axib_awprot),
        .m_axib_awready(m_axib_awready),
        .m_axib_awsize(m_axib_awsize),
        .m_axib_awuser(NLW_inst_m_axib_awuser_UNCONNECTED[7:0]),
        .m_axib_awvalid(m_axib_awvalid),
        .m_axib_bid(m_axib_bid),
        .m_axib_bready(m_axib_bready),
        .m_axib_bresp(m_axib_bresp),
        .m_axib_bvalid(m_axib_bvalid),
        .m_axib_rdata(m_axib_rdata),
        .m_axib_rid(m_axib_rid),
        .m_axib_rlast(m_axib_rlast),
        .m_axib_rready(m_axib_rready),
        .m_axib_rresp(m_axib_rresp),
        .m_axib_ruser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axib_rvalid(m_axib_rvalid),
        .m_axib_wdata(m_axib_wdata),
        .m_axib_wlast(m_axib_wlast),
        .m_axib_wready(m_axib_wready),
        .m_axib_wstrb(m_axib_wstrb),
        .m_axib_wuser(NLW_inst_m_axib_wuser_UNCONNECTED[7:0]),
        .m_axib_wvalid(m_axib_wvalid),
        .m_axil_araddr(NLW_inst_m_axil_araddr_UNCONNECTED[31:0]),
        .m_axil_arprot(NLW_inst_m_axil_arprot_UNCONNECTED[2:0]),
        .m_axil_arready(1'b0),
        .m_axil_aruser(NLW_inst_m_axil_aruser_UNCONNECTED[10:0]),
        .m_axil_arvalid(NLW_inst_m_axil_arvalid_UNCONNECTED),
        .m_axil_awaddr(NLW_inst_m_axil_awaddr_UNCONNECTED[31:0]),
        .m_axil_awprot(NLW_inst_m_axil_awprot_UNCONNECTED[2:0]),
        .m_axil_awready(1'b0),
        .m_axil_awuser(NLW_inst_m_axil_awuser_UNCONNECTED[10:0]),
        .m_axil_awvalid(NLW_inst_m_axil_awvalid_UNCONNECTED),
        .m_axil_bready(NLW_inst_m_axil_bready_UNCONNECTED),
        .m_axil_bresp({1'b0,1'b0}),
        .m_axil_bvalid(1'b0),
        .m_axil_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axil_rready(NLW_inst_m_axil_rready_UNCONNECTED),
        .m_axil_rresp({1'b0,1'b0}),
        .m_axil_rvalid(1'b0),
        .m_axil_wdata(NLW_inst_m_axil_wdata_UNCONNECTED[31:0]),
        .m_axil_wready(1'b0),
        .m_axil_wstrb(NLW_inst_m_axil_wstrb_UNCONNECTED[3:0]),
        .m_axil_wvalid(NLW_inst_m_axil_wvalid_UNCONNECTED),
        .m_axis_cc_tdata_out(NLW_inst_m_axis_cc_tdata_out_UNCONNECTED[63:0]),
        .m_axis_cc_tkeep_out(NLW_inst_m_axis_cc_tkeep_out_UNCONNECTED[1:0]),
        .m_axis_cc_tlast_out(NLW_inst_m_axis_cc_tlast_out_UNCONNECTED),
        .m_axis_cc_tready_out(NLW_inst_m_axis_cc_tready_out_UNCONNECTED[3:0]),
        .m_axis_cc_tuser_out(NLW_inst_m_axis_cc_tuser_out_UNCONNECTED[32:0]),
        .m_axis_cc_tvalid_out(NLW_inst_m_axis_cc_tvalid_out_UNCONNECTED),
        .m_axis_cq_tdata_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axis_cq_tkeep_sd({1'b0,1'b0}),
        .m_axis_cq_tlast_sd(1'b0),
        .m_axis_cq_tready_sd(NLW_inst_m_axis_cq_tready_sd_UNCONNECTED),
        .m_axis_cq_tuser_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axis_cq_tvalid_sd(1'b0),
        .m_axis_h2c_tdata_0(NLW_inst_m_axis_h2c_tdata_0_UNCONNECTED[63:0]),
        .m_axis_h2c_tdata_1(NLW_inst_m_axis_h2c_tdata_1_UNCONNECTED[63:0]),
        .m_axis_h2c_tdata_2(NLW_inst_m_axis_h2c_tdata_2_UNCONNECTED[63:0]),
        .m_axis_h2c_tdata_3(NLW_inst_m_axis_h2c_tdata_3_UNCONNECTED[63:0]),
        .m_axis_h2c_tkeep_0(NLW_inst_m_axis_h2c_tkeep_0_UNCONNECTED[7:0]),
        .m_axis_h2c_tkeep_1(NLW_inst_m_axis_h2c_tkeep_1_UNCONNECTED[7:0]),
        .m_axis_h2c_tkeep_2(NLW_inst_m_axis_h2c_tkeep_2_UNCONNECTED[7:0]),
        .m_axis_h2c_tkeep_3(NLW_inst_m_axis_h2c_tkeep_3_UNCONNECTED[7:0]),
        .m_axis_h2c_tlast_0(NLW_inst_m_axis_h2c_tlast_0_UNCONNECTED),
        .m_axis_h2c_tlast_1(NLW_inst_m_axis_h2c_tlast_1_UNCONNECTED),
        .m_axis_h2c_tlast_2(NLW_inst_m_axis_h2c_tlast_2_UNCONNECTED),
        .m_axis_h2c_tlast_3(NLW_inst_m_axis_h2c_tlast_3_UNCONNECTED),
        .m_axis_h2c_tready_0(1'b0),
        .m_axis_h2c_tready_1(1'b0),
        .m_axis_h2c_tready_2(1'b0),
        .m_axis_h2c_tready_3(1'b0),
        .m_axis_h2c_tuser_0(NLW_inst_m_axis_h2c_tuser_0_UNCONNECTED[7:0]),
        .m_axis_h2c_tuser_1(NLW_inst_m_axis_h2c_tuser_1_UNCONNECTED[7:0]),
        .m_axis_h2c_tuser_2(NLW_inst_m_axis_h2c_tuser_2_UNCONNECTED[7:0]),
        .m_axis_h2c_tuser_3(NLW_inst_m_axis_h2c_tuser_3_UNCONNECTED[7:0]),
        .m_axis_h2c_tvalid_0(NLW_inst_m_axis_h2c_tvalid_0_UNCONNECTED),
        .m_axis_h2c_tvalid_1(NLW_inst_m_axis_h2c_tvalid_1_UNCONNECTED),
        .m_axis_h2c_tvalid_2(NLW_inst_m_axis_h2c_tvalid_2_UNCONNECTED),
        .m_axis_h2c_tvalid_3(NLW_inst_m_axis_h2c_tvalid_3_UNCONNECTED),
        .m_axis_rc_tdata_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axis_rc_tkeep_sd({1'b0,1'b0}),
        .m_axis_rc_tlast_sd(1'b0),
        .m_axis_rc_tready_sd(NLW_inst_m_axis_rc_tready_sd_UNCONNECTED),
        .m_axis_rc_tuser_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axis_rc_tvalid_sd(1'b0),
        .m_axis_rq_tdata_out(NLW_inst_m_axis_rq_tdata_out_UNCONNECTED[63:0]),
        .m_axis_rq_tkeep_out(NLW_inst_m_axis_rq_tkeep_out_UNCONNECTED[1:0]),
        .m_axis_rq_tlast_out(NLW_inst_m_axis_rq_tlast_out_UNCONNECTED),
        .m_axis_rq_tready_out(NLW_inst_m_axis_rq_tready_out_UNCONNECTED[3:0]),
        .m_axis_rq_tuser_out(NLW_inst_m_axis_rq_tuser_out_UNCONNECTED[59:0]),
        .m_axis_rq_tvalid_out(NLW_inst_m_axis_rq_tvalid_out_UNCONNECTED),
        .m_axis_rx_tdata_o(m_axis_rx_tdata_o),
        .m_axis_rx_tkeep_o({\^m_axis_rx_tkeep_o ,NLW_inst_m_axis_rx_tkeep_o_UNCONNECTED[3:0]}),
        .m_axis_rx_tlast_o(m_axis_rx_tlast_o),
        .m_axis_rx_tready_i(m_axis_rx_tready_i),
        .m_axis_rx_tuser_o(\^m_axis_rx_tuser_o ),
        .m_axis_rx_tvalid_o(m_axis_rx_tvalid_o),
        .mcap_design_switch(NLW_inst_mcap_design_switch_UNCONNECTED),
        .mcap_eos_in(1'b0),
        .msi_enable(msi_enable),
        .msi_vector_width(msi_vector_width),
        .msix_enable(NLW_inst_msix_enable_UNCONNECTED),
        .pci_exp_rxn(pci_exp_rxn),
        .pci_exp_rxp(pci_exp_rxp),
        .pci_exp_txn(pci_exp_txn),
        .pci_exp_txp(pci_exp_txp),
        .pcie4_cxs0_active_ack_rx_sd(NLW_inst_pcie4_cxs0_active_ack_rx_sd_UNCONNECTED),
        .pcie4_cxs0_active_ack_tx_sd(1'b0),
        .pcie4_cxs0_active_req_rx_sd(1'b0),
        .pcie4_cxs0_active_req_tx_sd(NLW_inst_pcie4_cxs0_active_req_tx_sd_UNCONNECTED),
        .pcie4_cxs0_cntl_chk_rx_sd(1'b0),
        .pcie4_cxs0_cntl_chk_tx_sd(NLW_inst_pcie4_cxs0_cntl_chk_tx_sd_UNCONNECTED),
        .pcie4_cxs0_cntl_rx_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pcie4_cxs0_cntl_tx_sd(NLW_inst_pcie4_cxs0_cntl_tx_sd_UNCONNECTED[13:0]),
        .pcie4_cxs0_crdgnt_chk_rx_sd(NLW_inst_pcie4_cxs0_crdgnt_chk_rx_sd_UNCONNECTED),
        .pcie4_cxs0_crdgnt_chk_tx_sd(1'b0),
        .pcie4_cxs0_crdgnt_rx_sd(NLW_inst_pcie4_cxs0_crdgnt_rx_sd_UNCONNECTED),
        .pcie4_cxs0_crdgnt_tx_sd(1'b0),
        .pcie4_cxs0_crdrtn_chk_rx_sd(1'b0),
        .pcie4_cxs0_crdrtn_chk_tx_sd(NLW_inst_pcie4_cxs0_crdrtn_chk_tx_sd_UNCONNECTED),
        .pcie4_cxs0_crdrtn_rx_sd(1'b0),
        .pcie4_cxs0_crdrtn_tx_sd(NLW_inst_pcie4_cxs0_crdrtn_tx_sd_UNCONNECTED),
        .pcie4_cxs0_data_chk_rx_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pcie4_cxs0_data_chk_tx_sd(NLW_inst_pcie4_cxs0_data_chk_tx_sd_UNCONNECTED[31:0]),
        .pcie4_cxs0_data_rx_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pcie4_cxs0_data_tx_sd(NLW_inst_pcie4_cxs0_data_tx_sd_UNCONNECTED[255:0]),
        .pcie4_cxs0_deact_hint_rx_sd(NLW_inst_pcie4_cxs0_deact_hint_rx_sd_UNCONNECTED),
        .pcie4_cxs0_deact_hint_tx_sd(1'b0),
        .pcie4_cxs0_valid_chk_rx_sd(1'b0),
        .pcie4_cxs0_valid_chk_tx_sd(NLW_inst_pcie4_cxs0_valid_chk_tx_sd_UNCONNECTED),
        .pcie4_cxs0_valid_rx_sd(1'b0),
        .pcie4_cxs0_valid_tx_sd(NLW_inst_pcie4_cxs0_valid_tx_sd_UNCONNECTED),
        .pcie_cq_np_req_count_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pcie_cq_np_req_sd(NLW_inst_pcie_cq_np_req_sd_UNCONNECTED[1:0]),
        .pcie_rq_seq_num0_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pcie_rq_seq_num1_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pcie_rq_seq_num_vld0_sd(1'b0),
        .pcie_rq_seq_num_vld1_sd(1'b0),
        .pcie_tfc_npd_av_sd({1'b0,1'b0,1'b0,1'b0}),
        .pcie_tfc_nph_av_sd({1'b0,1'b0,1'b0,1'b0}),
        .pcieeqrxeqadaptdone_us_in(NLW_inst_pcieeqrxeqadaptdone_us_in_UNCONNECTED[1:0]),
        .pcieeqrxeqadaptdone_usp_in(NLW_inst_pcieeqrxeqadaptdone_usp_in_UNCONNECTED[1:0]),
        .pcierategen3_us_out({1'b0,1'b0}),
        .pcierategen3_usp_out({1'b0,1'b0}),
        .pcierateidle_us_out({1'b0,1'b0}),
        .pcierateidle_usp_out({1'b0,1'b0}),
        .pcierateqpll0_usp_in(NLW_inst_pcierateqpll0_usp_in_UNCONNECTED[2:0]),
        .pcierateqpll1_usp_in(NLW_inst_pcierateqpll1_usp_in_UNCONNECTED[2:0]),
        .pcierateqpllpd_us_out({1'b0,1'b0,1'b0,1'b0}),
        .pcierateqpllpd_usp_out({1'b0,1'b0,1'b0,1'b0}),
        .pcierateqpllreset_us_out({1'b0,1'b0,1'b0,1'b0}),
        .pcierateqpllreset_usp_out({1'b0,1'b0,1'b0,1'b0}),
        .pcierstidle_us_in(NLW_inst_pcierstidle_us_in_UNCONNECTED[1:0]),
        .pcierstidle_usp_in(NLW_inst_pcierstidle_usp_in_UNCONNECTED[1:0]),
        .pciersttxsyncstart_us_in(NLW_inst_pciersttxsyncstart_us_in_UNCONNECTED[1:0]),
        .pciersttxsyncstart_usp_in(NLW_inst_pciersttxsyncstart_usp_in_UNCONNECTED[1:0]),
        .pciesynctxsyncdone_us_out({1'b0,1'b0}),
        .pciesynctxsyncdone_usp_out({1'b0,1'b0}),
        .pcieusergen3rdy_us_out({1'b0,1'b0}),
        .pcieusergen3rdy_usp_out({1'b0,1'b0}),
        .pcieuserphystatusrst_us_out({1'b0,1'b0}),
        .pcieuserphystatusrst_usp_out({1'b0,1'b0}),
        .pcieuserratedone_us_in(NLW_inst_pcieuserratedone_us_in_UNCONNECTED[1:0]),
        .pcieuserratedone_usp_in(NLW_inst_pcieuserratedone_usp_in_UNCONNECTED[1:0]),
        .pcieuserratestart_us_out({1'b0,1'b0}),
        .pcieuserratestart_usp_out({1'b0,1'b0}),
        .pcsrsvdin_us_in(NLW_inst_pcsrsvdin_us_in_UNCONNECTED[31:0]),
        .pcsrsvdout_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .phy_prst_n(NLW_inst_phy_prst_n_UNCONNECTED),
        .phy_rdy_out_sd(1'b0),
        .phy_rrst_n(NLW_inst_phy_rrst_n_UNCONNECTED),
        .phy_rst_fsm(NLW_inst_phy_rst_fsm_UNCONNECTED[3:0]),
        .phy_rst_idle(NLW_inst_phy_rst_idle_UNCONNECTED),
        .phy_rxeq_fsm(NLW_inst_phy_rxeq_fsm_UNCONNECTED[5:0]),
        .phy_txeq_ctrl(NLW_inst_phy_txeq_ctrl_UNCONNECTED[3:0]),
        .phy_txeq_fsm(NLW_inst_phy_txeq_fsm_UNCONNECTED[5:0]),
        .phy_txeq_preset(NLW_inst_phy_txeq_preset_UNCONNECTED[7:0]),
        .phystatus_us_out({1'b0,1'b0}),
        .phystatus_usp_out({1'b0,1'b0}),
        .pipe_clk(NLW_inst_pipe_clk_UNCONNECTED),
        .pipe_cpll_lock(NLW_inst_pipe_cpll_lock_UNCONNECTED[1:0]),
        .pipe_dclk_in(1'b0),
        .pipe_debug(NLW_inst_pipe_debug_UNCONNECTED[31:0]),
        .pipe_debug_0(NLW_inst_pipe_debug_0_UNCONNECTED[1:0]),
        .pipe_debug_1(NLW_inst_pipe_debug_1_UNCONNECTED[1:0]),
        .pipe_debug_2(NLW_inst_pipe_debug_2_UNCONNECTED[1:0]),
        .pipe_debug_3(NLW_inst_pipe_debug_3_UNCONNECTED[1:0]),
        .pipe_debug_4(NLW_inst_pipe_debug_4_UNCONNECTED[1:0]),
        .pipe_debug_5(NLW_inst_pipe_debug_5_UNCONNECTED[1:0]),
        .pipe_debug_6(NLW_inst_pipe_debug_6_UNCONNECTED[1:0]),
        .pipe_debug_7(NLW_inst_pipe_debug_7_UNCONNECTED[1:0]),
        .pipe_debug_8(NLW_inst_pipe_debug_8_UNCONNECTED[1:0]),
        .pipe_debug_9(NLW_inst_pipe_debug_9_UNCONNECTED[1:0]),
        .pipe_debug_ctl_in_rx0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_debug_ctl_in_rx1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_debug_ctl_in_tx0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_debug_ctl_in_tx1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_debug_ctl_vec4({1'b0,1'b0,1'b0,1'b0}),
        .pipe_debug_debug_out_128_0(NLW_inst_pipe_debug_debug_out_128_0_UNCONNECTED[127:0]),
        .pipe_debug_debug_out_128_1(NLW_inst_pipe_debug_debug_out_128_1_UNCONNECTED[127:0]),
        .pipe_debug_debug_out_128_2(NLW_inst_pipe_debug_debug_out_128_2_UNCONNECTED[127:0]),
        .pipe_debug_debug_out_128_3(NLW_inst_pipe_debug_debug_out_128_3_UNCONNECTED[127:0]),
        .pipe_debug_debug_out_ext_16_0(NLW_inst_pipe_debug_debug_out_ext_16_0_UNCONNECTED[15:0]),
        .pipe_debug_debug_out_ext_16_1(NLW_inst_pipe_debug_debug_out_ext_16_1_UNCONNECTED[15:0]),
        .pipe_debug_debug_out_ext_16_2(NLW_inst_pipe_debug_debug_out_ext_16_2_UNCONNECTED[15:0]),
        .pipe_debug_debug_out_ext_16_3(NLW_inst_pipe_debug_debug_out_ext_16_3_UNCONNECTED[15:0]),
        .pipe_debug_inject_rx_status(NLW_inst_pipe_debug_inject_rx_status_UNCONNECTED[7:0]),
        .pipe_debug_inject_tx_status(NLW_inst_pipe_debug_inject_tx_status_UNCONNECTED[7:0]),
        .pipe_debug_ltssm_pol_act(1'b0),
        .pipe_debug_ltssm_rec_spd_1(1'b0),
        .pipe_debug_mux_ctl({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_dmonitorout(NLW_inst_pipe_dmonitorout_UNCONNECTED[29:0]),
        .pipe_drp_fsm(NLW_inst_pipe_drp_fsm_UNCONNECTED[13:0]),
        .pipe_eyescandataerror(NLW_inst_pipe_eyescandataerror_UNCONNECTED[1:0]),
        .pipe_gen3_out(NLW_inst_pipe_gen3_out_UNCONNECTED),
        .pipe_loopback({1'b0,1'b0,1'b0}),
        .pipe_mmcm_lock_in(1'b1),
        .pipe_mmcm_rst_n(1'b1),
        .pipe_oobclk_in(1'b0),
        .pipe_pclk_in(1'b0),
        .pipe_pclk_sel_out(NLW_inst_pipe_pclk_sel_out_UNCONNECTED[1:0]),
        .pipe_qpll_lock(NLW_inst_pipe_qpll_lock_UNCONNECTED[0]),
        .pipe_qrst_fsm(NLW_inst_pipe_qrst_fsm_UNCONNECTED[11:0]),
        .pipe_qrst_idle(NLW_inst_pipe_qrst_idle_UNCONNECTED),
        .pipe_rate_fsm(NLW_inst_pipe_rate_fsm_UNCONNECTED[9:0]),
        .pipe_rate_idle(NLW_inst_pipe_rate_idle_UNCONNECTED),
        .pipe_rst_fsm(NLW_inst_pipe_rst_fsm_UNCONNECTED[4:0]),
        .pipe_rst_idle(NLW_inst_pipe_rst_idle_UNCONNECTED),
        .pipe_rx_0_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_10_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_11_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_12_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_13_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_14_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_15_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_1_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_2_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_3_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_4_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_5_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_6_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_7_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_8_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_9_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rxbufstatus(NLW_inst_pipe_rxbufstatus_UNCONNECTED[5:0]),
        .pipe_rxcommadet(NLW_inst_pipe_rxcommadet_UNCONNECTED[1:0]),
        .pipe_rxdisperr(NLW_inst_pipe_rxdisperr_UNCONNECTED[15:0]),
        .pipe_rxdlysresetdone(NLW_inst_pipe_rxdlysresetdone_UNCONNECTED[1:0]),
        .pipe_rxnotintable(NLW_inst_pipe_rxnotintable_UNCONNECTED[15:0]),
        .pipe_rxoutclk_in({1'b0,1'b0}),
        .pipe_rxoutclk_out(NLW_inst_pipe_rxoutclk_out_UNCONNECTED[1:0]),
        .pipe_rxphaligndone(NLW_inst_pipe_rxphaligndone_UNCONNECTED[1:0]),
        .pipe_rxpmaresetdone(NLW_inst_pipe_rxpmaresetdone_UNCONNECTED[1:0]),
        .pipe_rxprbscntreset(1'b0),
        .pipe_rxprbserr(NLW_inst_pipe_rxprbserr_UNCONNECTED[1:0]),
        .pipe_rxprbssel({1'b0,1'b0,1'b0}),
        .pipe_rxstatus(NLW_inst_pipe_rxstatus_UNCONNECTED[5:0]),
        .pipe_rxsyncdone(NLW_inst_pipe_rxsyncdone_UNCONNECTED[1:0]),
        .pipe_rxusrclk_in(1'b0),
        .pipe_sync_fsm_rx(NLW_inst_pipe_sync_fsm_rx_UNCONNECTED[13:0]),
        .pipe_sync_fsm_tx(NLW_inst_pipe_sync_fsm_tx_UNCONNECTED[11:0]),
        .pipe_tx0_powerdown(NLW_inst_pipe_tx0_powerdown_UNCONNECTED[1:0]),
        .pipe_tx0_rcvr_det(NLW_inst_pipe_tx0_rcvr_det_UNCONNECTED),
        .pipe_tx_0_sigs(NLW_inst_pipe_tx_0_sigs_UNCONNECTED[83:0]),
        .pipe_tx_10_sigs(NLW_inst_pipe_tx_10_sigs_UNCONNECTED[83:0]),
        .pipe_tx_11_sigs(NLW_inst_pipe_tx_11_sigs_UNCONNECTED[83:0]),
        .pipe_tx_12_sigs(NLW_inst_pipe_tx_12_sigs_UNCONNECTED[83:0]),
        .pipe_tx_13_sigs(NLW_inst_pipe_tx_13_sigs_UNCONNECTED[83:0]),
        .pipe_tx_14_sigs(NLW_inst_pipe_tx_14_sigs_UNCONNECTED[83:0]),
        .pipe_tx_15_sigs(NLW_inst_pipe_tx_15_sigs_UNCONNECTED[83:0]),
        .pipe_tx_1_sigs(NLW_inst_pipe_tx_1_sigs_UNCONNECTED[83:0]),
        .pipe_tx_2_sigs(NLW_inst_pipe_tx_2_sigs_UNCONNECTED[83:0]),
        .pipe_tx_3_sigs(NLW_inst_pipe_tx_3_sigs_UNCONNECTED[83:0]),
        .pipe_tx_4_sigs(NLW_inst_pipe_tx_4_sigs_UNCONNECTED[83:0]),
        .pipe_tx_5_sigs(NLW_inst_pipe_tx_5_sigs_UNCONNECTED[83:0]),
        .pipe_tx_6_sigs(NLW_inst_pipe_tx_6_sigs_UNCONNECTED[83:0]),
        .pipe_tx_7_sigs(NLW_inst_pipe_tx_7_sigs_UNCONNECTED[83:0]),
        .pipe_tx_8_sigs(NLW_inst_pipe_tx_8_sigs_UNCONNECTED[83:0]),
        .pipe_tx_9_sigs(NLW_inst_pipe_tx_9_sigs_UNCONNECTED[83:0]),
        .pipe_txdlysresetdone(NLW_inst_pipe_txdlysresetdone_UNCONNECTED[1:0]),
        .pipe_txinhibit({1'b0,1'b0}),
        .pipe_txoutclk_out(NLW_inst_pipe_txoutclk_out_UNCONNECTED),
        .pipe_txphaligndone(NLW_inst_pipe_txphaligndone_UNCONNECTED[1:0]),
        .pipe_txphinitdone(NLW_inst_pipe_txphinitdone_UNCONNECTED[1:0]),
        .pipe_txprbsforceerr(1'b0),
        .pipe_txprbssel({1'b0,1'b0,1'b0}),
        .pipe_userclk1_in(1'b0),
        .pipe_userclk2_in(1'b0),
        .pl_directed_link_auton_i(pl_directed_link_auton_i),
        .pl_directed_link_change_i(pl_directed_link_change_i),
        .pl_directed_link_speed_i(pl_directed_link_speed_i),
        .pl_directed_link_width_i(pl_directed_link_width_i),
        .pl_upstream_prefer_deemph_i(pl_upstream_prefer_deemph_i),
        .qpll0clk_us_in(NLW_inst_qpll0clk_us_in_UNCONNECTED[1:0]),
        .qpll0freqlock_usp_in(NLW_inst_qpll0freqlock_usp_in_UNCONNECTED[1:0]),
        .qpll0lock_usp_out(1'b0),
        .qpll0outclk_usp_out(1'b0),
        .qpll0outrefclk_usp_out(1'b0),
        .qpll0pd_usp_in(NLW_inst_qpll0pd_usp_in_UNCONNECTED[0]),
        .qpll0refclk_us_in(NLW_inst_qpll0refclk_us_in_UNCONNECTED[1:0]),
        .qpll0reset_usp_in(NLW_inst_qpll0reset_usp_in_UNCONNECTED[0]),
        .qpll1clk_us_in(NLW_inst_qpll1clk_us_in_UNCONNECTED[1:0]),
        .qpll1freqlock_usp_in(NLW_inst_qpll1freqlock_usp_in_UNCONNECTED[1:0]),
        .qpll1lock_us_out(1'b0),
        .qpll1lock_usp_out(1'b0),
        .qpll1outclk_us_out(1'b0),
        .qpll1outclk_usp_out(1'b0),
        .qpll1outrefclk_us_out(1'b0),
        .qpll1outrefclk_usp_out(1'b0),
        .qpll1pd_us_in(NLW_inst_qpll1pd_us_in_UNCONNECTED[0]),
        .qpll1pd_usp_in(NLW_inst_qpll1pd_usp_in_UNCONNECTED[0]),
        .qpll1refclk_us_in(NLW_inst_qpll1refclk_us_in_UNCONNECTED[1:0]),
        .qpll1reset_us_in(NLW_inst_qpll1reset_us_in_UNCONNECTED[0]),
        .qpll1reset_usp_in(NLW_inst_qpll1reset_usp_in_UNCONNECTED[0]),
        .qpll_drp_clk(NLW_inst_qpll_drp_clk_UNCONNECTED),
        .qpll_drp_crscode({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .qpll_drp_done({1'b0,1'b0}),
        .qpll_drp_fsm({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .qpll_drp_gen3(NLW_inst_qpll_drp_gen3_UNCONNECTED),
        .qpll_drp_ovrd(NLW_inst_qpll_drp_ovrd_UNCONNECTED),
        .qpll_drp_reset({1'b0,1'b0}),
        .qpll_drp_rst_n(NLW_inst_qpll_drp_rst_n_UNCONNECTED),
        .qpll_drp_start(NLW_inst_qpll_drp_start_UNCONNECTED),
        .qpll_qplld(NLW_inst_qpll_qplld_UNCONNECTED),
        .qpll_qplllock({1'b0,1'b0}),
        .qpll_qplloutclk({1'b0,1'b0}),
        .qpll_qplloutrefclk({1'b0,1'b0}),
        .qpll_qpllreset(NLW_inst_qpll_qpllreset_UNCONNECTED[1:0]),
        .qpllrsvd2_us_in(NLW_inst_qpllrsvd2_us_in_UNCONNECTED[4:0]),
        .qpllrsvd3_us_in(NLW_inst_qpllrsvd3_us_in_UNCONNECTED[4:0]),
        .rbar_bar_size_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rbar_function_number_sd({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rbar_write_enable_bar0_sd(1'b0),
        .rbar_write_enable_bar1_sd(1'b0),
        .rbar_write_enable_bar2_sd(1'b0),
        .rbar_write_enable_bar3_sd(1'b0),
        .rbar_write_enable_bar4_sd(1'b0),
        .rbar_write_enable_bar5_sd(1'b0),
        .rcalenb_usp_in(NLW_inst_rcalenb_usp_in_UNCONNECTED[0]),
        .rd_interrupt(NLW_inst_rd_interrupt_UNCONNECTED),
        .resetovrd_usp_in(NLW_inst_resetovrd_usp_in_UNCONNECTED[1:0]),
        .rx8b10ben_us_in(NLW_inst_rx8b10ben_us_in_UNCONNECTED[1:0]),
        .rx8b10ben_usp_in(NLW_inst_rx8b10ben_usp_in_UNCONNECTED[1:0]),
        .rx_np_ok_i(rx_np_ok_i),
        .rx_np_req_i(rx_np_req_i),
        .rxbufreset_us_in(NLW_inst_rxbufreset_us_in_UNCONNECTED[1:0]),
        .rxbufreset_usp_in(NLW_inst_rxbufreset_usp_in_UNCONNECTED[1:0]),
        .rxbufstatus_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxbufstatus_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxbyteisaligned_us_out({1'b0,1'b0}),
        .rxbyteisaligned_usp_out({1'b0,1'b0}),
        .rxbyterealign_us_out({1'b0,1'b0}),
        .rxbyterealign_usp_out({1'b0,1'b0}),
        .rxcdrfreqreset_usp_in(NLW_inst_rxcdrfreqreset_usp_in_UNCONNECTED[1:0]),
        .rxcdrhold_us_in(NLW_inst_rxcdrhold_us_in_UNCONNECTED[1:0]),
        .rxcdrhold_usp_in(NLW_inst_rxcdrhold_usp_in_UNCONNECTED[1:0]),
        .rxcdrlock_us_out({1'b0,1'b0}),
        .rxcdrlock_usp_out({1'b0,1'b0}),
        .rxcdrreset_usp_in(NLW_inst_rxcdrreset_usp_in_UNCONNECTED[1:0]),
        .rxclkcorcnt_us_out({1'b0,1'b0,1'b0,1'b0}),
        .rxclkcorcnt_usp_out({1'b0,1'b0,1'b0,1'b0}),
        .rxcommadet_us_out({1'b0,1'b0}),
        .rxcommadet_usp_out({1'b0,1'b0}),
        .rxcommadeten_us_in(NLW_inst_rxcommadeten_us_in_UNCONNECTED[1:0]),
        .rxcommadeten_usp_in(NLW_inst_rxcommadeten_usp_in_UNCONNECTED[1:0]),
        .rxctrl0_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxctrl0_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxctrl1_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxctrl1_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxctrl2_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxctrl2_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxctrl3_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxctrl3_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxdata_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxdata_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxdfeagchold_us_in(NLW_inst_rxdfeagchold_us_in_UNCONNECTED[1:0]),
        .rxdfeagchold_usp_in(NLW_inst_rxdfeagchold_usp_in_UNCONNECTED[1:0]),
        .rxdfecfokhold_us_in(NLW_inst_rxdfecfokhold_us_in_UNCONNECTED[1:0]),
        .rxdfecfokhold_usp_in(NLW_inst_rxdfecfokhold_usp_in_UNCONNECTED[1:0]),
        .rxdfekhhold_us_in(NLW_inst_rxdfekhhold_us_in_UNCONNECTED[1:0]),
        .rxdfekhhold_usp_in(NLW_inst_rxdfekhhold_usp_in_UNCONNECTED[1:0]),
        .rxdfelfhold_us_in(NLW_inst_rxdfelfhold_us_in_UNCONNECTED[1:0]),
        .rxdfelfhold_usp_in(NLW_inst_rxdfelfhold_usp_in_UNCONNECTED[1:0]),
        .rxdfelpmreset_usp_in(NLW_inst_rxdfelpmreset_usp_in_UNCONNECTED[1:0]),
        .rxdfetap10hold_us_in(NLW_inst_rxdfetap10hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap10hold_usp_in(NLW_inst_rxdfetap10hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap11hold_us_in(NLW_inst_rxdfetap11hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap11hold_usp_in(NLW_inst_rxdfetap11hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap12hold_us_in(NLW_inst_rxdfetap12hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap12hold_usp_in(NLW_inst_rxdfetap12hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap13hold_us_in(NLW_inst_rxdfetap13hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap13hold_usp_in(NLW_inst_rxdfetap13hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap14hold_us_in(NLW_inst_rxdfetap14hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap14hold_usp_in(NLW_inst_rxdfetap14hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap15hold_us_in(NLW_inst_rxdfetap15hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap15hold_usp_in(NLW_inst_rxdfetap15hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap2hold_us_in(NLW_inst_rxdfetap2hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap2hold_usp_in(NLW_inst_rxdfetap2hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap3hold_us_in(NLW_inst_rxdfetap3hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap3hold_usp_in(NLW_inst_rxdfetap3hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap4hold_us_in(NLW_inst_rxdfetap4hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap4hold_usp_in(NLW_inst_rxdfetap4hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap5hold_us_in(NLW_inst_rxdfetap5hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap5hold_usp_in(NLW_inst_rxdfetap5hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap6hold_us_in(NLW_inst_rxdfetap6hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap6hold_usp_in(NLW_inst_rxdfetap6hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap7hold_us_in(NLW_inst_rxdfetap7hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap7hold_usp_in(NLW_inst_rxdfetap7hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap8hold_us_in(NLW_inst_rxdfetap8hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap8hold_usp_in(NLW_inst_rxdfetap8hold_usp_in_UNCONNECTED[1:0]),
        .rxdfetap9hold_us_in(NLW_inst_rxdfetap9hold_us_in_UNCONNECTED[1:0]),
        .rxdfetap9hold_usp_in(NLW_inst_rxdfetap9hold_usp_in_UNCONNECTED[1:0]),
        .rxdfeuthold_us_in(NLW_inst_rxdfeuthold_us_in_UNCONNECTED[1:0]),
        .rxdfeuthold_usp_in(NLW_inst_rxdfeuthold_usp_in_UNCONNECTED[1:0]),
        .rxdfevphold_us_in(NLW_inst_rxdfevphold_us_in_UNCONNECTED[1:0]),
        .rxdfevphold_usp_in(NLW_inst_rxdfevphold_usp_in_UNCONNECTED[1:0]),
        .rxdlysresetdone_us_out({1'b0,1'b0}),
        .rxdlysresetdone_usp_out({1'b0,1'b0}),
        .rxelecidle_us_out({1'b0,1'b0}),
        .rxelecidle_usp_out({1'b0,1'b0}),
        .rxlpmen_us_in(NLW_inst_rxlpmen_us_in_UNCONNECTED[1:0]),
        .rxlpmen_usp_in(NLW_inst_rxlpmen_usp_in_UNCONNECTED[1:0]),
        .rxlpmgchold_us_in(NLW_inst_rxlpmgchold_us_in_UNCONNECTED[1:0]),
        .rxlpmgchold_usp_in(NLW_inst_rxlpmgchold_usp_in_UNCONNECTED[1:0]),
        .rxlpmhfhold_us_in(NLW_inst_rxlpmhfhold_us_in_UNCONNECTED[1:0]),
        .rxlpmhfhold_usp_in(NLW_inst_rxlpmhfhold_usp_in_UNCONNECTED[1:0]),
        .rxlpmlfhold_us_in(NLW_inst_rxlpmlfhold_us_in_UNCONNECTED[1:0]),
        .rxlpmlfhold_usp_in(NLW_inst_rxlpmlfhold_usp_in_UNCONNECTED[1:0]),
        .rxlpmoshold_us_in(NLW_inst_rxlpmoshold_us_in_UNCONNECTED[1:0]),
        .rxlpmoshold_usp_in(NLW_inst_rxlpmoshold_usp_in_UNCONNECTED[1:0]),
        .rxmcommaalignen_us_in(NLW_inst_rxmcommaalignen_us_in_UNCONNECTED[1:0]),
        .rxmcommaalignen_usp_in(NLW_inst_rxmcommaalignen_usp_in_UNCONNECTED[1:0]),
        .rxoshold_us_in(NLW_inst_rxoshold_us_in_UNCONNECTED[1:0]),
        .rxoshold_usp_in(NLW_inst_rxoshold_usp_in_UNCONNECTED[1:0]),
        .rxoutclk_us_out({1'b0,1'b0}),
        .rxoutclk_usp_out({1'b0,1'b0}),
        .rxoutclkfabric_usp_out({1'b0,1'b0}),
        .rxoutclkpcs_usp_out({1'b0,1'b0}),
        .rxpcommaalignen_us_in(NLW_inst_rxpcommaalignen_us_in_UNCONNECTED[1:0]),
        .rxpcommaalignen_usp_in(NLW_inst_rxpcommaalignen_usp_in_UNCONNECTED[1:0]),
        .rxpcsreset_usp_in(NLW_inst_rxpcsreset_usp_in_UNCONNECTED[1:0]),
        .rxpd_us_in(NLW_inst_rxpd_us_in_UNCONNECTED[3:0]),
        .rxpd_usp_in(NLW_inst_rxpd_usp_in_UNCONNECTED[3:0]),
        .rxphaligndone_us_out({1'b0,1'b0}),
        .rxphaligndone_usp_out({1'b0,1'b0}),
        .rxpmareset_usp_in(NLW_inst_rxpmareset_usp_in_UNCONNECTED[1:0]),
        .rxpmaresetdone_us_out({1'b0,1'b0}),
        .rxpmaresetdone_usp_out({1'b0,1'b0}),
        .rxpolarity_us_in(NLW_inst_rxpolarity_us_in_UNCONNECTED[1:0]),
        .rxpolarity_usp_in(NLW_inst_rxpolarity_usp_in_UNCONNECTED[1:0]),
        .rxprbscntreset_us_in(NLW_inst_rxprbscntreset_us_in_UNCONNECTED[1:0]),
        .rxprbscntreset_usp_in(NLW_inst_rxprbscntreset_usp_in_UNCONNECTED[1:0]),
        .rxprbserr_us_out({1'b0,1'b0}),
        .rxprbserr_usp_out({1'b0,1'b0}),
        .rxprbslocked_us_out({1'b0,1'b0}),
        .rxprbslocked_usp_out({1'b0,1'b0}),
        .rxprbssel_us_in(NLW_inst_rxprbssel_us_in_UNCONNECTED[7:0]),
        .rxprbssel_usp_in(NLW_inst_rxprbssel_usp_in_UNCONNECTED[7:0]),
        .rxprgdivresetdone_us_out({1'b0,1'b0}),
        .rxprogdivreset_us_in(NLW_inst_rxprogdivreset_us_in_UNCONNECTED[1:0]),
        .rxprogdivreset_usp_in(NLW_inst_rxprogdivreset_usp_in_UNCONNECTED[1:0]),
        .rxrate_us_in(NLW_inst_rxrate_us_in_UNCONNECTED[5:0]),
        .rxrate_usp_in(NLW_inst_rxrate_usp_in_UNCONNECTED[5:0]),
        .rxratedone_us_out({1'b0,1'b0}),
        .rxratedone_usp_out({1'b0,1'b0}),
        .rxratemode_us_in(NLW_inst_rxratemode_us_in_UNCONNECTED[1:0]),
        .rxratemode_usp_in(NLW_inst_rxratemode_usp_in_UNCONNECTED[1:0]),
        .rxrecclkout_usp_out({1'b0,1'b0}),
        .rxresetdone_us_out({1'b0,1'b0}),
        .rxresetdone_usp_out({1'b0,1'b0}),
        .rxslide_us_in(NLW_inst_rxslide_us_in_UNCONNECTED[1:0]),
        .rxslide_usp_in(NLW_inst_rxslide_usp_in_UNCONNECTED[1:0]),
        .rxstatus_us_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxstatus_usp_out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rxsyncdone_us_out({1'b0,1'b0}),
        .rxsyncdone_usp_out({1'b0,1'b0}),
        .rxtermination_usp_in(NLW_inst_rxtermination_usp_in_UNCONNECTED[1:0]),
        .rxuserrdy_us_in(NLW_inst_rxuserrdy_us_in_UNCONNECTED[1:0]),
        .rxuserrdy_usp_in(NLW_inst_rxuserrdy_usp_in_UNCONNECTED[1:0]),
        .rxusrclk2_us_in(NLW_inst_rxusrclk2_us_in_UNCONNECTED[1:0]),
        .rxusrclk2_usp_in(NLW_inst_rxusrclk2_usp_in_UNCONNECTED[1:0]),
        .rxusrclk_us_in(NLW_inst_rxusrclk_us_in_UNCONNECTED[1:0]),
        .rxusrclk_usp_in(NLW_inst_rxusrclk_usp_in_UNCONNECTED[1:0]),
        .rxvalid_us_out({1'b0,1'b0}),
        .rxvalid_usp_out({1'b0,1'b0}),
        .s_aclk(1'b0),
        .s_aresetn(1'b0),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlock(1'b0),
        .s_axi_arprot({1'b0,1'b0,1'b0}),
        .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_inst_s_axi_arready_UNCONNECTED),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_aruser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlock(1'b0),
        .s_axi_awprot({1'b0,1'b0,1'b0}),
        .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_inst_s_axi_awready_UNCONNECTED),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awuser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[15:0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_inst_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_bvalid(NLW_inst_s_axi_bvalid_UNCONNECTED),
        .s_axi_rdata(NLW_inst_s_axi_rdata_UNCONNECTED[31:0]),
        .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[15:0]),
        .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_inst_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_rvalid(NLW_inst_s_axi_rvalid_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_inst_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wvalid(1'b0),
        .s_axib_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axib_arburst({1'b0,1'b0}),
        .s_axib_arid({1'b0,1'b0,1'b0,1'b0}),
        .s_axib_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axib_arready(NLW_inst_s_axib_arready_UNCONNECTED),
        .s_axib_arregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axib_arsize({1'b0,1'b0,1'b0}),
        .s_axib_arvalid(1'b0),
        .s_axib_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axib_awburst({1'b0,1'b0}),
        .s_axib_awid({1'b0,1'b0,1'b0,1'b0}),
        .s_axib_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axib_awready(NLW_inst_s_axib_awready_UNCONNECTED),
        .s_axib_awregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axib_awsize({1'b0,1'b0,1'b0}),
        .s_axib_awvalid(1'b0),
        .s_axib_bid(NLW_inst_s_axib_bid_UNCONNECTED[3:0]),
        .s_axib_bready(1'b0),
        .s_axib_bresp(NLW_inst_s_axib_bresp_UNCONNECTED[1:0]),
        .s_axib_bvalid(NLW_inst_s_axib_bvalid_UNCONNECTED),
        .s_axib_rdata(NLW_inst_s_axib_rdata_UNCONNECTED[63:0]),
        .s_axib_rid(NLW_inst_s_axib_rid_UNCONNECTED[3:0]),
        .s_axib_rlast(NLW_inst_s_axib_rlast_UNCONNECTED),
        .s_axib_rready(1'b0),
        .s_axib_rresp(NLW_inst_s_axib_rresp_UNCONNECTED[1:0]),
        .s_axib_ruser(NLW_inst_s_axib_ruser_UNCONNECTED[7:0]),
        .s_axib_rvalid(NLW_inst_s_axib_rvalid_UNCONNECTED),
        .s_axib_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axib_wlast(1'b0),
        .s_axib_wready(NLW_inst_s_axib_wready_UNCONNECTED),
        .s_axib_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axib_wuser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axib_wvalid(1'b0),
        .s_axil_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axil_arprot({1'b0,1'b0,1'b0}),
        .s_axil_arready(NLW_inst_s_axil_arready_UNCONNECTED),
        .s_axil_arvalid(1'b0),
        .s_axil_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axil_awprot({1'b0,1'b0,1'b0}),
        .s_axil_awready(NLW_inst_s_axil_awready_UNCONNECTED),
        .s_axil_awvalid(1'b0),
        .s_axil_bready(1'b0),
        .s_axil_bresp(NLW_inst_s_axil_bresp_UNCONNECTED[1:0]),
        .s_axil_bvalid(NLW_inst_s_axil_bvalid_UNCONNECTED),
        .s_axil_rdata(NLW_inst_s_axil_rdata_UNCONNECTED[31:0]),
        .s_axil_rready(1'b0),
        .s_axil_rresp(NLW_inst_s_axil_rresp_UNCONNECTED[1:0]),
        .s_axil_rvalid(NLW_inst_s_axil_rvalid_UNCONNECTED),
        .s_axil_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axil_wready(NLW_inst_s_axil_wready_UNCONNECTED),
        .s_axil_wstrb({1'b0,1'b0,1'b0,1'b0}),
        .s_axil_wvalid(1'b0),
        .s_axis_c2h_tdata_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tdata_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tdata_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tdata_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tkeep_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tkeep_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tkeep_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tkeep_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tlast_0(1'b0),
        .s_axis_c2h_tlast_1(1'b0),
        .s_axis_c2h_tlast_2(1'b0),
        .s_axis_c2h_tlast_3(1'b0),
        .s_axis_c2h_tready_0(NLW_inst_s_axis_c2h_tready_0_UNCONNECTED),
        .s_axis_c2h_tready_1(NLW_inst_s_axis_c2h_tready_1_UNCONNECTED),
        .s_axis_c2h_tready_2(NLW_inst_s_axis_c2h_tready_2_UNCONNECTED),
        .s_axis_c2h_tready_3(NLW_inst_s_axis_c2h_tready_3_UNCONNECTED),
        .s_axis_c2h_tuser_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tuser_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tuser_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tuser_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tvalid_0(1'b0),
        .s_axis_c2h_tvalid_1(1'b0),
        .s_axis_c2h_tvalid_2(1'b0),
        .s_axis_c2h_tvalid_3(1'b0),
        .s_axis_cc_tdata_sd(NLW_inst_s_axis_cc_tdata_sd_UNCONNECTED[63:0]),
        .s_axis_cc_tkeep_sd(NLW_inst_s_axis_cc_tkeep_sd_UNCONNECTED[1:0]),
        .s_axis_cc_tlast_sd(NLW_inst_s_axis_cc_tlast_sd_UNCONNECTED),
        .s_axis_cc_tready_sd({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_cc_tuser_sd(NLW_inst_s_axis_cc_tuser_sd_UNCONNECTED[32:0]),
        .s_axis_cc_tvalid_sd(NLW_inst_s_axis_cc_tvalid_sd_UNCONNECTED),
        .s_axis_cq_tdata_out(NLW_inst_s_axis_cq_tdata_out_UNCONNECTED[63:0]),
        .s_axis_cq_tkeep_out(NLW_inst_s_axis_cq_tkeep_out_UNCONNECTED[1:0]),
        .s_axis_cq_tlast_out(NLW_inst_s_axis_cq_tlast_out_UNCONNECTED),
        .s_axis_cq_tready_out(NLW_inst_s_axis_cq_tready_out_UNCONNECTED),
        .s_axis_cq_tuser_out(NLW_inst_s_axis_cq_tuser_out_UNCONNECTED[84:0]),
        .s_axis_cq_tvalid_out(NLW_inst_s_axis_cq_tvalid_out_UNCONNECTED),
        .s_axis_rc_tdata_out(NLW_inst_s_axis_rc_tdata_out_UNCONNECTED[63:0]),
        .s_axis_rc_tkeep_out(NLW_inst_s_axis_rc_tkeep_out_UNCONNECTED[1:0]),
        .s_axis_rc_tlast_out(NLW_inst_s_axis_rc_tlast_out_UNCONNECTED),
        .s_axis_rc_tready_out(NLW_inst_s_axis_rc_tready_out_UNCONNECTED),
        .s_axis_rc_tuser_out(NLW_inst_s_axis_rc_tuser_out_UNCONNECTED[74:0]),
        .s_axis_rc_tvalid_out(NLW_inst_s_axis_rc_tvalid_out_UNCONNECTED),
        .s_axis_rq_tdata_sd(NLW_inst_s_axis_rq_tdata_sd_UNCONNECTED[63:0]),
        .s_axis_rq_tkeep_sd(NLW_inst_s_axis_rq_tkeep_sd_UNCONNECTED[1:0]),
        .s_axis_rq_tlast_sd(NLW_inst_s_axis_rq_tlast_sd_UNCONNECTED),
        .s_axis_rq_tready_sd({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_rq_tuser_sd(NLW_inst_s_axis_rq_tuser_sd_UNCONNECTED[59:0]),
        .s_axis_rq_tvalid_sd(NLW_inst_s_axis_rq_tvalid_sd_UNCONNECTED),
        .s_axis_tx_tdata_i(s_axis_tx_tdata_i),
        .s_axis_tx_tkeep_i({s_axis_tx_tkeep_i[7],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tx_tlast_i(s_axis_tx_tlast_i),
        .s_axis_tx_tready_o(s_axis_tx_tready_o),
        .s_axis_tx_tuser_i(s_axis_tx_tuser_i),
        .s_axis_tx_tvalid_i(s_axis_tx_tvalid_i),
        .sc0_ats_m_axis_cq_tdata(NLW_inst_sc0_ats_m_axis_cq_tdata_UNCONNECTED[63:0]),
        .sc0_ats_m_axis_cq_tkeep(NLW_inst_sc0_ats_m_axis_cq_tkeep_UNCONNECTED[7:0]),
        .sc0_ats_m_axis_cq_tlast(NLW_inst_sc0_ats_m_axis_cq_tlast_UNCONNECTED),
        .sc0_ats_m_axis_cq_tready(1'b0),
        .sc0_ats_m_axis_cq_tuser(NLW_inst_sc0_ats_m_axis_cq_tuser_UNCONNECTED[84:0]),
        .sc0_ats_m_axis_cq_tvalid(NLW_inst_sc0_ats_m_axis_cq_tvalid_UNCONNECTED),
        .sc0_ats_m_axis_rc_tdata(NLW_inst_sc0_ats_m_axis_rc_tdata_UNCONNECTED[63:0]),
        .sc0_ats_m_axis_rc_tkeep(NLW_inst_sc0_ats_m_axis_rc_tkeep_UNCONNECTED[7:0]),
        .sc0_ats_m_axis_rc_tlast(NLW_inst_sc0_ats_m_axis_rc_tlast_UNCONNECTED),
        .sc0_ats_m_axis_rc_tready(1'b0),
        .sc0_ats_m_axis_rc_tuser(NLW_inst_sc0_ats_m_axis_rc_tuser_UNCONNECTED[74:0]),
        .sc0_ats_m_axis_rc_tvalid(NLW_inst_sc0_ats_m_axis_rc_tvalid_UNCONNECTED),
        .sc0_ats_s_axis_cc_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc0_ats_s_axis_cc_tkeep({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc0_ats_s_axis_cc_tlast(1'b0),
        .sc0_ats_s_axis_cc_tready(NLW_inst_sc0_ats_s_axis_cc_tready_UNCONNECTED),
        .sc0_ats_s_axis_cc_tuser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc0_ats_s_axis_cc_tvalid(1'b0),
        .sc0_ats_s_axis_rq_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc0_ats_s_axis_rq_tkeep({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc0_ats_s_axis_rq_tlast(1'b0),
        .sc0_ats_s_axis_rq_tready(NLW_inst_sc0_ats_s_axis_rq_tready_UNCONNECTED),
        .sc0_ats_s_axis_rq_tuser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc0_ats_s_axis_rq_tvalid(1'b0),
        .sc1_ats_m_axis_cq_tdata(NLW_inst_sc1_ats_m_axis_cq_tdata_UNCONNECTED[63:0]),
        .sc1_ats_m_axis_cq_tkeep(NLW_inst_sc1_ats_m_axis_cq_tkeep_UNCONNECTED[7:0]),
        .sc1_ats_m_axis_cq_tlast(NLW_inst_sc1_ats_m_axis_cq_tlast_UNCONNECTED),
        .sc1_ats_m_axis_cq_tready(1'b0),
        .sc1_ats_m_axis_cq_tuser(NLW_inst_sc1_ats_m_axis_cq_tuser_UNCONNECTED[84:0]),
        .sc1_ats_m_axis_cq_tvalid(NLW_inst_sc1_ats_m_axis_cq_tvalid_UNCONNECTED),
        .sc1_ats_m_axis_rc_tdata(NLW_inst_sc1_ats_m_axis_rc_tdata_UNCONNECTED[63:0]),
        .sc1_ats_m_axis_rc_tkeep(NLW_inst_sc1_ats_m_axis_rc_tkeep_UNCONNECTED[7:0]),
        .sc1_ats_m_axis_rc_tlast(NLW_inst_sc1_ats_m_axis_rc_tlast_UNCONNECTED),
        .sc1_ats_m_axis_rc_tready(1'b0),
        .sc1_ats_m_axis_rc_tuser(NLW_inst_sc1_ats_m_axis_rc_tuser_UNCONNECTED[74:0]),
        .sc1_ats_m_axis_rc_tvalid(NLW_inst_sc1_ats_m_axis_rc_tvalid_UNCONNECTED),
        .sc1_ats_s_axis_cc_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc1_ats_s_axis_cc_tkeep({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc1_ats_s_axis_cc_tlast(1'b0),
        .sc1_ats_s_axis_cc_tready(NLW_inst_sc1_ats_s_axis_cc_tready_UNCONNECTED),
        .sc1_ats_s_axis_cc_tuser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc1_ats_s_axis_cc_tvalid(1'b0),
        .sc1_ats_s_axis_rq_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc1_ats_s_axis_rq_tkeep({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc1_ats_s_axis_rq_tlast(1'b0),
        .sc1_ats_s_axis_rq_tready(NLW_inst_sc1_ats_s_axis_rq_tready_UNCONNECTED),
        .sc1_ats_s_axis_rq_tuser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sc1_ats_s_axis_rq_tvalid(1'b0),
        .startup_cfgclk(NLW_inst_startup_cfgclk_UNCONNECTED),
        .startup_cfgmclk(NLW_inst_startup_cfgmclk_UNCONNECTED),
        .startup_di(NLW_inst_startup_di_UNCONNECTED[3:0]),
        .startup_do({1'b0,1'b0,1'b0,1'b0}),
        .startup_dts({1'b0,1'b0,1'b0,1'b0}),
        .startup_eos(NLW_inst_startup_eos_UNCONNECTED),
        .startup_fcsbo(1'b0),
        .startup_fcsbts(1'b0),
        .startup_gsr(1'b0),
        .startup_gts(1'b0),
        .startup_keyclearb(1'b1),
        .startup_pack(1'b0),
        .startup_preq(NLW_inst_startup_preq_UNCONNECTED),
        .startup_usrcclko(1'b0),
        .startup_usrcclkts(1'b1),
        .startup_usrdoneo(1'b0),
        .startup_usrdonets(1'b1),
        .sys_clk(sys_clk),
        .sys_clk_bufg(NLW_inst_sys_clk_bufg_UNCONNECTED),
        .sys_clk_ce_out(NLW_inst_sys_clk_ce_out_UNCONNECTED),
        .sys_clk_gt(1'b0),
        .sys_rst_n(sys_rst_n),
        .tx8b10ben_us_in(NLW_inst_tx8b10ben_us_in_UNCONNECTED[1:0]),
        .tx8b10ben_usp_in(NLW_inst_tx8b10ben_usp_in_UNCONNECTED[1:0]),
        .tx_cfg_gnt_i(tx_cfg_gnt_i),
        .txctrl0_us_in(NLW_inst_txctrl0_us_in_UNCONNECTED[31:0]),
        .txctrl0_usp_in(NLW_inst_txctrl0_usp_in_UNCONNECTED[31:0]),
        .txctrl1_us_in(NLW_inst_txctrl1_us_in_UNCONNECTED[31:0]),
        .txctrl1_usp_in(NLW_inst_txctrl1_usp_in_UNCONNECTED[31:0]),
        .txctrl2_us_in(NLW_inst_txctrl2_us_in_UNCONNECTED[15:0]),
        .txctrl2_usp_in(NLW_inst_txctrl2_usp_in_UNCONNECTED[15:0]),
        .txdata_us_in(NLW_inst_txdata_us_in_UNCONNECTED[255:0]),
        .txdata_usp_in(NLW_inst_txdata_usp_in_UNCONNECTED[255:0]),
        .txdeemph_us_in(NLW_inst_txdeemph_us_in_UNCONNECTED[1:0]),
        .txdeemph_usp_in(NLW_inst_txdeemph_usp_in_UNCONNECTED[3:0]),
        .txdetectrx_us_in(NLW_inst_txdetectrx_us_in_UNCONNECTED[1:0]),
        .txdetectrx_usp_in(NLW_inst_txdetectrx_usp_in_UNCONNECTED[1:0]),
        .txdiffctrl_us_in(NLW_inst_txdiffctrl_us_in_UNCONNECTED[7:0]),
        .txdiffctrl_usp_in(NLW_inst_txdiffctrl_usp_in_UNCONNECTED[9:0]),
        .txdlybypass_us_in(NLW_inst_txdlybypass_us_in_UNCONNECTED[1:0]),
        .txdlybypass_usp_in(NLW_inst_txdlybypass_usp_in_UNCONNECTED[1:0]),
        .txdlyen_us_in(NLW_inst_txdlyen_us_in_UNCONNECTED[1:0]),
        .txdlyen_usp_in(NLW_inst_txdlyen_usp_in_UNCONNECTED[1:0]),
        .txdlyhold_us_in(NLW_inst_txdlyhold_us_in_UNCONNECTED[1:0]),
        .txdlyhold_usp_in(NLW_inst_txdlyhold_usp_in_UNCONNECTED[1:0]),
        .txdlyovrden_us_in(NLW_inst_txdlyovrden_us_in_UNCONNECTED[1:0]),
        .txdlyovrden_usp_in(NLW_inst_txdlyovrden_usp_in_UNCONNECTED[1:0]),
        .txdlysreset_us_in(NLW_inst_txdlysreset_us_in_UNCONNECTED[1:0]),
        .txdlysreset_usp_in(NLW_inst_txdlysreset_usp_in_UNCONNECTED[1:0]),
        .txdlysresetdone_us_out({1'b0,1'b0}),
        .txdlysresetdone_usp_out({1'b0,1'b0}),
        .txdlyupdown_us_in(NLW_inst_txdlyupdown_us_in_UNCONNECTED[1:0]),
        .txdlyupdown_usp_in(NLW_inst_txdlyupdown_usp_in_UNCONNECTED[1:0]),
        .txelecidle_us_in(NLW_inst_txelecidle_us_in_UNCONNECTED[1:0]),
        .txelecidle_usp_in(NLW_inst_txelecidle_usp_in_UNCONNECTED[1:0]),
        .txinhibit_us_in(NLW_inst_txinhibit_us_in_UNCONNECTED[1:0]),
        .txmaincursor_us_in(NLW_inst_txmaincursor_us_in_UNCONNECTED[13:0]),
        .txmaincursor_usp_in(NLW_inst_txmaincursor_usp_in_UNCONNECTED[13:0]),
        .txmargin_us_in(NLW_inst_txmargin_us_in_UNCONNECTED[5:0]),
        .txmargin_usp_in(NLW_inst_txmargin_usp_in_UNCONNECTED[5:0]),
        .txoutclk_us_out({1'b0,1'b0}),
        .txoutclk_usp_out({1'b0,1'b0}),
        .txoutclkfabric_usp_out({1'b0,1'b0}),
        .txoutclkpcs_usp_out({1'b0,1'b0}),
        .txoutclksel_us_in(NLW_inst_txoutclksel_us_in_UNCONNECTED[5:0]),
        .txoutclksel_usp_in(NLW_inst_txoutclksel_usp_in_UNCONNECTED[5:0]),
        .txpcsreset_usp_in(NLW_inst_txpcsreset_usp_in_UNCONNECTED[1:0]),
        .txpd_us_in(NLW_inst_txpd_us_in_UNCONNECTED[3:0]),
        .txpd_usp_in(NLW_inst_txpd_usp_in_UNCONNECTED[3:0]),
        .txpdelecidlemode_usp_in(NLW_inst_txpdelecidlemode_usp_in_UNCONNECTED[1:0]),
        .txphalign_us_in(NLW_inst_txphalign_us_in_UNCONNECTED[1:0]),
        .txphalign_usp_in(NLW_inst_txphalign_usp_in_UNCONNECTED[1:0]),
        .txphaligndone_us_out({1'b0,1'b0}),
        .txphaligndone_usp_out({1'b0,1'b0}),
        .txphalignen_us_in(NLW_inst_txphalignen_us_in_UNCONNECTED[1:0]),
        .txphalignen_usp_in(NLW_inst_txphalignen_usp_in_UNCONNECTED[1:0]),
        .txphdlypd_us_in(NLW_inst_txphdlypd_us_in_UNCONNECTED[1:0]),
        .txphdlypd_usp_in(NLW_inst_txphdlypd_usp_in_UNCONNECTED[1:0]),
        .txphdlyreset_us_in(NLW_inst_txphdlyreset_us_in_UNCONNECTED[1:0]),
        .txphdlyreset_usp_in(NLW_inst_txphdlyreset_usp_in_UNCONNECTED[1:0]),
        .txphdlytstclk_us_in(NLW_inst_txphdlytstclk_us_in_UNCONNECTED[1:0]),
        .txphdlytstclk_usp_in(NLW_inst_txphdlytstclk_usp_in_UNCONNECTED[1:0]),
        .txphinit_us_in(NLW_inst_txphinit_us_in_UNCONNECTED[1:0]),
        .txphinit_usp_in(NLW_inst_txphinit_usp_in_UNCONNECTED[1:0]),
        .txphinitdone_us_out({1'b0,1'b0}),
        .txphinitdone_usp_out({1'b0,1'b0}),
        .txphovrden_us_in(NLW_inst_txphovrden_us_in_UNCONNECTED[1:0]),
        .txphovrden_usp_in(NLW_inst_txphovrden_usp_in_UNCONNECTED[1:0]),
        .txpisopd_usp_in(NLW_inst_txpisopd_usp_in_UNCONNECTED[1:0]),
        .txpmareset_usp_in(NLW_inst_txpmareset_usp_in_UNCONNECTED[1:0]),
        .txpmaresetdone_us_out({1'b0,1'b0}),
        .txpmaresetdone_usp_out({1'b0,1'b0}),
        .txpostcursor_us_in(NLW_inst_txpostcursor_us_in_UNCONNECTED[9:0]),
        .txpostcursor_usp_in(NLW_inst_txpostcursor_usp_in_UNCONNECTED[9:0]),
        .txprbsforceerr_us_in(NLW_inst_txprbsforceerr_us_in_UNCONNECTED[1:0]),
        .txprbsforceerr_usp_in(NLW_inst_txprbsforceerr_usp_in_UNCONNECTED[1:0]),
        .txprbssel_us_in(NLW_inst_txprbssel_us_in_UNCONNECTED[7:0]),
        .txprbssel_usp_in(NLW_inst_txprbssel_usp_in_UNCONNECTED[7:0]),
        .txprecursor_us_in(NLW_inst_txprecursor_us_in_UNCONNECTED[9:0]),
        .txprecursor_usp_in(NLW_inst_txprecursor_usp_in_UNCONNECTED[9:0]),
        .txprgdivresetdone_us_out({1'b0,1'b0}),
        .txprgdivresetdone_usp_out({1'b0,1'b0}),
        .txprogdivreset_us_in(NLW_inst_txprogdivreset_us_in_UNCONNECTED[1:0]),
        .txprogdivreset_usp_in(NLW_inst_txprogdivreset_usp_in_UNCONNECTED[1:0]),
        .txrate_us_in(NLW_inst_txrate_us_in_UNCONNECTED[5:0]),
        .txrate_usp_in(NLW_inst_txrate_usp_in_UNCONNECTED[5:0]),
        .txresetdone_us_out({1'b0,1'b0}),
        .txresetdone_usp_out({1'b0,1'b0}),
        .txswing_us_in(NLW_inst_txswing_us_in_UNCONNECTED[1:0]),
        .txswing_usp_in(NLW_inst_txswing_usp_in_UNCONNECTED[1:0]),
        .txsyncallin_us_in(NLW_inst_txsyncallin_us_in_UNCONNECTED[1:0]),
        .txsyncallin_usp_in(NLW_inst_txsyncallin_usp_in_UNCONNECTED[1:0]),
        .txsyncdone_us_out({1'b0,1'b0}),
        .txsyncdone_usp_out({1'b0,1'b0}),
        .txsyncin_us_in(NLW_inst_txsyncin_us_in_UNCONNECTED[1:0]),
        .txsyncin_usp_in(NLW_inst_txsyncin_usp_in_UNCONNECTED[1:0]),
        .txsyncmode_us_in(NLW_inst_txsyncmode_us_in_UNCONNECTED[1:0]),
        .txsyncmode_usp_in(NLW_inst_txsyncmode_usp_in_UNCONNECTED[1:0]),
        .txsyncout_us_out({1'b0,1'b0}),
        .txsyncout_usp_out({1'b0,1'b0}),
        .txuserrdy_us_in(NLW_inst_txuserrdy_us_in_UNCONNECTED[1:0]),
        .txuserrdy_usp_in(NLW_inst_txuserrdy_usp_in_UNCONNECTED[1:0]),
        .txusrclk2_us_in(NLW_inst_txusrclk2_us_in_UNCONNECTED[1:0]),
        .txusrclk2_usp_in(NLW_inst_txusrclk2_usp_in_UNCONNECTED[1:0]),
        .txusrclk_us_in(NLW_inst_txusrclk_us_in_UNCONNECTED[1:0]),
        .txusrclk_usp_in(NLW_inst_txusrclk_usp_in_UNCONNECTED[1:0]),
        .user_clk_sd(1'b0),
        .user_lnk_up(user_lnk_up),
        .user_lnk_up_sd(1'b0),
        .user_reset_sd(1'b0),
        .usr_flr_clr(NLW_inst_usr_flr_clr_UNCONNECTED),
        .usr_flr_done_fnc({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .usr_flr_done_vld(1'b0),
        .usr_flr_fnc(NLW_inst_usr_flr_fnc_UNCONNECTED[7:0]),
        .usr_flr_set(NLW_inst_usr_flr_set_UNCONNECTED),
        .usr_irq_ack(usr_irq_ack),
        .usr_irq_function_number({1'b0,1'b0}),
        .usr_irq_req(usr_irq_req),
        .wr_interrupt(NLW_inst_wr_interrupt_UNCONNECTED));
endmodule

module xdma_0_axi_stream_intf
   (\pcie_dma_in\.pcie_rq_seq_num0 ,
    m_axis_rx_tready,
    s_axis_tx_tlast_reg,
    s_axis_tx_tvalid_reg,
    \s_axis_tx_tdata_reg[63] ,
    \s_axis_tx_tkeep_reg[7] ,
    \s_axis_cq\.tdata ,
    \s_axis_cq\.tuser ,
    \s_axis_cq\.tvalid ,
    \s_axis_cq\.tlast ,
    \m_axis_rq\.tready ,
    \pcie_dma_in\.pcie_rq_seq_num_vld0 ,
    \m_axis_cc\.tready ,
    \s_axis_rc\.tkeep ,
    \s_axis_rc\.tuser ,
    \s_axis_rc\.tlast ,
    \s_axis_rc\.tdata ,
    user_clk_out,
    E,
    m_axis_rx_tkeep_o,
    m_axis_rx_tlast,
    user_reset_out,
    s_axis_tx_tready,
    \m_axis_cc\.tlast ,
    dmaFlag,
    m_axis_rx_tready_i,
    s_axis_tx_tlast_i,
    s_axis_tx_tvalid_i,
    s_axis_tx_tdata_i,
    s_axis_tx_tkeep_i,
    D,
    m_axis_rx_tvalid,
    m_axis_rx_tuser_o,
    \s_axis_cq\.tready ,
    \tx_64.req_addr_reg[63] ,
    s_axis_rq_tuser,
    \m_axis_rq\.tlast ,
    \m_axis_rq\.tvalid ,
    cfg_function_number_o,
    cfg_device_number_o,
    cfg_bus_number_o,
    \m_axis_cc\.tvalid ,
    \m_axis_cc\.tdata ,
    \s_axis_rc\.tready );
  output [3:0]\pcie_dma_in\.pcie_rq_seq_num0 ;
  output m_axis_rx_tready;
  output s_axis_tx_tlast_reg;
  output s_axis_tx_tvalid_reg;
  output [63:0]\s_axis_tx_tdata_reg[63] ;
  output [0:0]\s_axis_tx_tkeep_reg[7] ;
  output [63:0]\s_axis_cq\.tdata ;
  output [4:0]\s_axis_cq\.tuser ;
  output \s_axis_cq\.tvalid ;
  output \s_axis_cq\.tlast ;
  output \m_axis_rq\.tready ;
  output \pcie_dma_in\.pcie_rq_seq_num_vld0 ;
  output \m_axis_cc\.tready ;
  output [1:0]\s_axis_rc\.tkeep ;
  output [3:0]\s_axis_rc\.tuser ;
  output \s_axis_rc\.tlast ;
  output [63:0]\s_axis_rc\.tdata ;
  input user_clk_out;
  input [0:0]E;
  input [3:0]m_axis_rx_tkeep_o;
  input m_axis_rx_tlast;
  input user_reset_out;
  input s_axis_tx_tready;
  input \m_axis_cc\.tlast ;
  input dmaFlag;
  input m_axis_rx_tready_i;
  input s_axis_tx_tlast_i;
  input s_axis_tx_tvalid_i;
  input [63:0]s_axis_tx_tdata_i;
  input [0:0]s_axis_tx_tkeep_i;
  input [63:0]D;
  input m_axis_rx_tvalid;
  input [13:0]m_axis_rx_tuser_o;
  input [0:0]\s_axis_cq\.tready ;
  input [63:0]\tx_64.req_addr_reg[63] ;
  input [11:0]s_axis_rq_tuser;
  input \m_axis_rq\.tlast ;
  input \m_axis_rq\.tvalid ;
  input [2:0]cfg_function_number_o;
  input [4:0]cfg_device_number_o;
  input [7:0]cfg_bus_number_o;
  input \m_axis_cc\.tvalid ;
  input [63:0]\m_axis_cc\.tdata ;
  input [0:0]\s_axis_rc\.tready ;

  wire [9:0]A;
  wire [63:0]D;
  wire [0:0]E;
  wire [7:0]cfg_bus_number_o;
  wire [4:0]cfg_device_number_o;
  wire [2:0]cfg_function_number_o;
  wire dmaFlag;
  wire in_packet_q;
  wire in_packet_q_0;
  wire [63:0]\m_axis_cc\.tdata ;
  wire \m_axis_cc\.tlast ;
  wire \m_axis_cc\.tready ;
  wire \m_axis_cc\.tvalid ;
  wire \m_axis_rq\.tlast ;
  wire \m_axis_rq\.tready ;
  wire \m_axis_rq\.tvalid ;
  wire [63:0]m_axis_rx_cpl_tdata;
  wire m_axis_rx_cpl_tvalid;
  wire [63:0]m_axis_rx_tgt_tdata;
  wire m_axis_rx_tgt_tlast;
  wire m_axis_rx_tgt_tready;
  wire m_axis_rx_tgt_tvalid;
  wire [3:0]m_axis_rx_tkeep_o;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire m_axis_rx_tready_i;
  wire [13:0]m_axis_rx_tuser_o;
  wire m_axis_rx_tvalid;
  wire [3:0]\pcie_dma_in\.pcie_rq_seq_num0 ;
  wire \pcie_dma_in\.pcie_rq_seq_num_vld0 ;
  wire req_ATS;
  wire req_LTR;
  wire req_OBFF;
  wire req_VDM;
  wire [2:0]req_bar_id;
  wire [3:0]req_fbe;
  wire req_mesg;
  wire [7:0]req_msg_code;
  wire [63:0]\s_axis_cq\.tdata ;
  wire \s_axis_cq\.tlast ;
  wire [0:0]\s_axis_cq\.tready ;
  wire [4:0]\s_axis_cq\.tuser ;
  wire \s_axis_cq\.tvalid ;
  wire [63:0]\s_axis_rc\.tdata ;
  wire [1:0]\s_axis_rc\.tkeep ;
  wire \s_axis_rc\.tlast ;
  wire [0:0]\s_axis_rc\.tready ;
  wire [3:0]\s_axis_rc\.tuser ;
  wire [11:0]s_axis_rq_tuser;
  wire [63:2]s_axis_tx_req_tdata;
  wire s_axis_tx_req_tlast;
  wire s_axis_tx_req_tready;
  wire s_axis_tx_req_tvalid;
  wire [63:0]s_axis_tx_tdata_i;
  wire [63:0]\s_axis_tx_tdata_reg[63] ;
  wire [63:0]s_axis_tx_tgt_tdata;
  wire [7:7]s_axis_tx_tgt_tkeep;
  wire s_axis_tx_tgt_tready;
  wire s_axis_tx_tgt_tvalid;
  wire [0:0]s_axis_tx_tkeep_i;
  wire [0:0]\s_axis_tx_tkeep_reg[7] ;
  wire s_axis_tx_tlast_i;
  wire s_axis_tx_tlast_reg;
  wire s_axis_tx_tready;
  wire s_axis_tx_tvalid_i;
  wire s_axis_tx_tvalid_reg;
  wire [1:1]state;
  wire [1:0]transfer_SM;
  wire [63:0]\tx_64.req_addr_reg[63] ;
  wire user_clk_out;
  wire user_reset_out;
  wire [2:0]wr_attr;
  wire [11:0]wr_byte;
  wire [15:0]wr_cid;
  wire [2:0]wr_tc;
  wire xdma_0_dma_cpl_i_n_1;
  wire xdma_0_dma_cpl_i_n_2;
  wire xdma_0_dma_req_i_n_10;
  wire xdma_0_dma_req_i_n_11;
  wire xdma_0_dma_req_i_n_12;
  wire xdma_0_dma_req_i_n_13;
  wire xdma_0_dma_req_i_n_14;
  wire xdma_0_dma_req_i_n_15;
  wire xdma_0_dma_req_i_n_16;
  wire xdma_0_dma_req_i_n_17;
  wire xdma_0_dma_req_i_n_18;
  wire xdma_0_dma_req_i_n_19;
  wire xdma_0_dma_req_i_n_20;
  wire xdma_0_dma_req_i_n_21;
  wire xdma_0_dma_req_i_n_22;
  wire xdma_0_dma_req_i_n_23;
  wire xdma_0_dma_req_i_n_24;
  wire xdma_0_dma_req_i_n_25;
  wire xdma_0_dma_req_i_n_26;
  wire xdma_0_dma_req_i_n_27;
  wire xdma_0_dma_req_i_n_28;
  wire xdma_0_dma_req_i_n_29;
  wire xdma_0_dma_req_i_n_30;
  wire xdma_0_dma_req_i_n_31;
  wire xdma_0_dma_req_i_n_32;
  wire xdma_0_dma_req_i_n_33;
  wire xdma_0_dma_req_i_n_34;
  wire xdma_0_dma_req_i_n_35;
  wire xdma_0_dma_req_i_n_36;
  wire xdma_0_dma_req_i_n_37;
  wire xdma_0_dma_req_i_n_5;
  wire xdma_0_dma_req_i_n_7;
  wire xdma_0_dma_req_i_n_8;
  wire xdma_0_dma_req_i_n_9;
  wire xdma_0_rx_demux_i_n_150;
  wire xdma_0_rx_demux_i_n_195;
  wire xdma_0_rx_demux_i_n_196;
  wire xdma_0_rx_demux_i_n_197;
  wire xdma_0_rx_demux_i_n_198;
  wire xdma_0_rx_demux_i_n_199;
  wire xdma_0_rx_demux_i_n_200;
  wire xdma_0_rx_demux_i_n_201;
  wire xdma_0_rx_demux_i_n_202;
  wire xdma_0_rx_demux_i_n_203;
  wire xdma_0_rx_demux_i_n_204;
  wire xdma_0_rx_demux_i_n_205;
  wire xdma_0_rx_demux_i_n_206;
  wire xdma_0_rx_demux_i_n_207;
  wire xdma_0_rx_demux_i_n_208;
  wire xdma_0_rx_demux_i_n_209;
  wire xdma_0_rx_demux_i_n_210;
  wire xdma_0_rx_demux_i_n_211;
  wire xdma_0_rx_demux_i_n_212;
  wire xdma_0_rx_demux_i_n_213;
  wire xdma_0_rx_demux_i_n_214;
  wire xdma_0_rx_demux_i_n_215;
  wire xdma_0_rx_demux_i_n_216;
  wire xdma_0_rx_demux_i_n_217;
  wire xdma_0_rx_demux_i_n_218;
  wire xdma_0_rx_demux_i_n_219;
  wire xdma_0_rx_demux_i_n_220;
  wire xdma_0_rx_demux_i_n_221;
  wire xdma_0_rx_demux_i_n_222;
  wire xdma_0_rx_demux_i_n_223;
  wire xdma_0_rx_demux_i_n_224;
  wire xdma_0_rx_demux_i_n_225;
  wire xdma_0_rx_demux_i_n_226;
  wire xdma_0_rx_demux_i_n_227;
  wire xdma_0_rx_demux_i_n_228;
  wire xdma_0_rx_demux_i_n_229;
  wire xdma_0_rx_demux_i_n_230;
  wire xdma_0_tgt_cpl_i_n_0;
  wire xdma_0_tgt_cpl_i_n_1;
  wire xdma_0_tgt_req_i_n_3;

  xdma_0_dma_cpl xdma_0_dma_cpl_i
       (.D(A),
        .Q({xdma_0_dma_cpl_i_n_1,xdma_0_dma_cpl_i_n_2}),
        .in_packet_q(in_packet_q),
        .in_packet_q_reg_0(xdma_0_rx_demux_i_n_198),
        .m_axis_tdata({m_axis_rx_cpl_tdata[63:8],m_axis_rx_cpl_tdata[6:0]}),
        .m_axis_tvalid(m_axis_rx_cpl_tvalid),
        .\rc_64.wr_attr_reg[2]_0 (wr_attr),
        .\rc_64.wr_byte_reg[11]_0 (wr_byte),
        .\rc_64.wr_cid_reg[15]_0 (wr_cid),
        .\rc_64.wr_compl_status_reg[2]_0 ({xdma_0_rx_demux_i_n_195,xdma_0_rx_demux_i_n_196,xdma_0_rx_demux_i_n_197}),
        .\rc_64.wr_data_reg[31]_0 ({xdma_0_rx_demux_i_n_199,xdma_0_rx_demux_i_n_200,xdma_0_rx_demux_i_n_201,xdma_0_rx_demux_i_n_202,xdma_0_rx_demux_i_n_203,xdma_0_rx_demux_i_n_204,xdma_0_rx_demux_i_n_205,xdma_0_rx_demux_i_n_206,xdma_0_rx_demux_i_n_207,xdma_0_rx_demux_i_n_208,xdma_0_rx_demux_i_n_209,xdma_0_rx_demux_i_n_210,xdma_0_rx_demux_i_n_211,xdma_0_rx_demux_i_n_212,xdma_0_rx_demux_i_n_213,xdma_0_rx_demux_i_n_214,xdma_0_rx_demux_i_n_215,xdma_0_rx_demux_i_n_216,xdma_0_rx_demux_i_n_217,xdma_0_rx_demux_i_n_218,xdma_0_rx_demux_i_n_219,xdma_0_rx_demux_i_n_220,xdma_0_rx_demux_i_n_221,xdma_0_rx_demux_i_n_222,xdma_0_rx_demux_i_n_223,xdma_0_rx_demux_i_n_224,xdma_0_rx_demux_i_n_225,xdma_0_rx_demux_i_n_226,xdma_0_rx_demux_i_n_227,xdma_0_rx_demux_i_n_228,xdma_0_rx_demux_i_n_229,xdma_0_rx_demux_i_n_230}),
        .\rc_64.wr_tc_reg[2]_0 (wr_tc),
        .\s_axis_rc\.tdata (\s_axis_rc\.tdata ),
        .\s_axis_rc\.tkeep (\s_axis_rc\.tkeep ),
        .\s_axis_rc\.tlast (\s_axis_rc\.tlast ),
        .\s_axis_rc\.tready (\s_axis_rc\.tready ),
        .\s_axis_rc\.tuser (\s_axis_rc\.tuser ),
        .user_clk_out(user_clk_out),
        .user_reset_out(user_reset_out));
  xdma_0_dma_req xdma_0_dma_req_i
       (.\FSM_sequential_transfer_SM_reg[1] (xdma_0_dma_req_i_n_36),
        .\FSM_sequential_transfer_SM_reg[1]_0 (xdma_0_dma_req_i_n_37),
        .\FSM_sequential_tx_64.state_reg[1]_0 (xdma_0_dma_req_i_n_5),
        .\Head_reg[16] (xdma_0_dma_req_i_n_15),
        .\Head_reg[17] (xdma_0_dma_req_i_n_14),
        .\Head_reg[18] (xdma_0_dma_req_i_n_13),
        .\Head_reg[19] (xdma_0_dma_req_i_n_12),
        .\Head_reg[20] (xdma_0_dma_req_i_n_11),
        .\Head_reg[21] (xdma_0_dma_req_i_n_10),
        .\Head_reg[22] (xdma_0_dma_req_i_n_9),
        .\Head_reg[23] (xdma_0_dma_req_i_n_8),
        .\Head_reg[26] (xdma_0_dma_req_i_n_21),
        .\Head_reg[27] (xdma_0_dma_req_i_n_20),
        .\Head_reg[28] (xdma_0_dma_req_i_n_19),
        .\Head_reg[29] (xdma_0_dma_req_i_n_18),
        .\Head_reg[30] (xdma_0_dma_req_i_n_17),
        .\Head_reg[31] (xdma_0_dma_req_i_n_16),
        .cfg_bus_number_o(cfg_bus_number_o),
        .cfg_device_number_o(cfg_device_number_o),
        .cfg_function_number_o(cfg_function_number_o),
        .\m_axis_cc\.tlast (\m_axis_cc\.tlast ),
        .\m_axis_rq\.tlast (\m_axis_rq\.tlast ),
        .\m_axis_rq\.tready (\m_axis_rq\.tready ),
        .\m_axis_rq\.tvalid (\m_axis_rq\.tvalid ),
        .\pcie_dma_in\.pcie_rq_seq_num0 (\pcie_dma_in\.pcie_rq_seq_num0 ),
        .s_axis_rq_tuser(s_axis_rq_tuser),
        .s_axis_tx_req_tdata({s_axis_tx_req_tdata[63:48],s_axis_tx_req_tdata[33:32],s_axis_tx_req_tdata[30:29],s_axis_tx_req_tdata[22:20],s_axis_tx_req_tdata[18],s_axis_tx_req_tdata[14],s_axis_tx_req_tdata[12:2]}),
        .s_axis_tx_req_tlast(s_axis_tx_req_tlast),
        .s_axis_tx_req_tready(s_axis_tx_req_tready),
        .s_axis_tx_req_tvalid(s_axis_tx_req_tvalid),
        .s_axis_tx_tgt_tdata({s_axis_tx_tgt_tdata[47:34],s_axis_tx_tgt_tdata[31],s_axis_tx_tgt_tdata[28:23],s_axis_tx_tgt_tdata[19],s_axis_tx_tgt_tdata[17:15],s_axis_tx_tgt_tdata[13],s_axis_tx_tgt_tdata[1:0]}),
        .s_axis_tx_tgt_tkeep(s_axis_tx_tgt_tkeep),
        .s_axis_tx_tgt_tvalid(s_axis_tx_tgt_tvalid),
        .s_axis_tx_tlast_reg(xdma_0_tgt_cpl_i_n_1),
        .s_axis_tx_tready(s_axis_tx_tready),
        .transfer_SM(transfer_SM),
        .tready_thrtl_reg(xdma_0_dma_req_i_n_7),
        .\tx_64.req_addr_reg[63]_0 (\tx_64.req_addr_reg[63] ),
        .\tx_64.wr_data_reg[0]_0 (xdma_0_dma_req_i_n_27),
        .\tx_64.wr_data_reg[11]_0 (xdma_0_dma_req_i_n_29),
        .\tx_64.wr_data_reg[15]_0 (xdma_0_dma_req_i_n_28),
        .\tx_64.wr_data_reg[1]_0 (xdma_0_dma_req_i_n_26),
        .\tx_64.wr_data_reg[21]_0 (xdma_0_dma_req_i_n_33),
        .\tx_64.wr_data_reg[23]_0 (xdma_0_dma_req_i_n_32),
        .\tx_64.wr_data_reg[24]_0 (xdma_0_dma_req_i_n_35),
        .\tx_64.wr_data_reg[25]_0 (xdma_0_dma_req_i_n_34),
        .\tx_64.wr_data_reg[2]_0 (xdma_0_dma_req_i_n_25),
        .\tx_64.wr_data_reg[3]_0 (xdma_0_dma_req_i_n_24),
        .\tx_64.wr_data_reg[4]_0 (xdma_0_dma_req_i_n_23),
        .\tx_64.wr_data_reg[7]_0 (xdma_0_dma_req_i_n_22),
        .\tx_64.wr_data_reg[8]_0 (xdma_0_dma_req_i_n_31),
        .\tx_64.wr_data_reg[9]_0 (xdma_0_dma_req_i_n_30),
        .user_clk_out(user_clk_out),
        .user_reset_out(user_reset_out));
  xdma_0_rx_demux xdma_0_rx_demux_i
       (.D(D),
        .E(E),
        .Q({xdma_0_dma_cpl_i_n_1,xdma_0_dma_cpl_i_n_2}),
        .dmaFlag(dmaFlag),
        .empty_fwft_i_reg(m_axis_rx_tgt_tvalid),
        .\goreg_bm.dout_i_reg[38] ({xdma_0_rx_demux_i_n_199,xdma_0_rx_demux_i_n_200,xdma_0_rx_demux_i_n_201,xdma_0_rx_demux_i_n_202,xdma_0_rx_demux_i_n_203,xdma_0_rx_demux_i_n_204,xdma_0_rx_demux_i_n_205,xdma_0_rx_demux_i_n_206,xdma_0_rx_demux_i_n_207,xdma_0_rx_demux_i_n_208,xdma_0_rx_demux_i_n_209,xdma_0_rx_demux_i_n_210,xdma_0_rx_demux_i_n_211,xdma_0_rx_demux_i_n_212,xdma_0_rx_demux_i_n_213,xdma_0_rx_demux_i_n_214,xdma_0_rx_demux_i_n_215,xdma_0_rx_demux_i_n_216,xdma_0_rx_demux_i_n_217,xdma_0_rx_demux_i_n_218,xdma_0_rx_demux_i_n_219,xdma_0_rx_demux_i_n_220,xdma_0_rx_demux_i_n_221,xdma_0_rx_demux_i_n_222,xdma_0_rx_demux_i_n_223,xdma_0_rx_demux_i_n_224,xdma_0_rx_demux_i_n_225,xdma_0_rx_demux_i_n_226,xdma_0_rx_demux_i_n_227,xdma_0_rx_demux_i_n_228,xdma_0_rx_demux_i_n_229,xdma_0_rx_demux_i_n_230}),
        .\goreg_dm.dout_i_reg[4] (req_bar_id),
        .\goreg_dm.dout_i_reg[59] (req_fbe),
        .\goreg_dm.dout_i_reg[59]_0 (req_msg_code),
        .\goreg_dm.dout_i_reg[94] (m_axis_rx_tgt_tdata),
        .in_packet_q(in_packet_q_0),
        .in_packet_q_0(in_packet_q),
        .in_packet_q_reg(xdma_0_rx_demux_i_n_150),
        .in_packet_q_reg_0(wr_cid),
        .in_packet_q_reg_1(wr_byte),
        .in_packet_q_reg_2(A),
        .in_packet_q_reg_3(wr_attr),
        .in_packet_q_reg_4(wr_tc),
        .in_packet_q_reg_5({xdma_0_rx_demux_i_n_195,xdma_0_rx_demux_i_n_196,xdma_0_rx_demux_i_n_197}),
        .m_axis_rx_tkeep_o(m_axis_rx_tkeep_o),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tready_i(m_axis_rx_tready_i),
        .m_axis_rx_tuser_o(m_axis_rx_tuser_o),
        .m_axis_rx_tvalid(m_axis_rx_tvalid),
        .m_axis_tdata({m_axis_rx_cpl_tdata[63:8],m_axis_rx_cpl_tdata[6:0]}),
        .m_axis_tlast(m_axis_rx_tgt_tlast),
        .m_axis_tready(m_axis_rx_tgt_tready),
        .m_axis_tvalid(m_axis_rx_cpl_tvalid),
        .req_ATS(req_ATS),
        .req_LTR(req_LTR),
        .req_OBFF(req_OBFF),
        .req_VDM(req_VDM),
        .req_mesg(req_mesg),
        .\s_axis_rc\.tready (\s_axis_rc\.tready ),
        .state(state),
        .\tx_64.req_bar_id_reg[0] (xdma_0_tgt_req_i_n_3),
        .user_clk_out(user_clk_out),
        .user_reset_out(user_reset_out),
        .user_reset_out_reg(xdma_0_rx_demux_i_n_198));
  xdma_0_tgt_cpl xdma_0_tgt_cpl_i
       (.\FSM_sequential_transfer_SM_reg[1] (xdma_0_dma_req_i_n_5),
        .\FSM_sequential_tx_64.state_reg[1]_0 (xdma_0_tgt_cpl_i_n_1),
        .cfg_bus_number_o(cfg_bus_number_o),
        .cfg_device_number_o(cfg_device_number_o),
        .cfg_function_number_o(cfg_function_number_o),
        .\m_axis_cc\.tdata (\m_axis_cc\.tdata ),
        .\m_axis_cc\.tlast (\m_axis_cc\.tlast ),
        .\m_axis_cc\.tready (\m_axis_cc\.tready ),
        .\m_axis_cc\.tvalid (\m_axis_cc\.tvalid ),
        .s_axis_tx_req_tvalid(s_axis_tx_req_tvalid),
        .s_axis_tx_tgt_tdata(s_axis_tx_tgt_tdata),
        .s_axis_tx_tgt_tkeep(s_axis_tx_tgt_tkeep),
        .s_axis_tx_tgt_tready(s_axis_tx_tgt_tready),
        .s_axis_tx_tgt_tvalid(s_axis_tx_tgt_tvalid),
        .s_axis_tx_tready(s_axis_tx_tready),
        .transfer_SM(transfer_SM),
        .tready_thrtl_reg(xdma_0_tgt_cpl_i_n_0),
        .user_clk_out(user_clk_out),
        .user_reset_out(user_reset_out));
  xdma_0_tgt_req xdma_0_tgt_req_i
       (.D(req_fbe),
        .\FSM_sequential_tx_64.state_reg[1]_0 (state),
        .in_packet_q(in_packet_q_0),
        .in_packet_q_reg_0(xdma_0_tgt_req_i_n_3),
        .m_axis_tlast(m_axis_rx_tgt_tlast),
        .m_axis_tready(m_axis_rx_tgt_tready),
        .req_ATS(req_ATS),
        .req_LTR(req_LTR),
        .req_OBFF(req_OBFF),
        .req_VDM(req_VDM),
        .req_mesg(req_mesg),
        .\s_axis_cq\.tdata (\s_axis_cq\.tdata ),
        .\s_axis_cq\.tlast (\s_axis_cq\.tlast ),
        .\s_axis_cq\.tready (\s_axis_cq\.tready ),
        .\s_axis_cq\.tuser (\s_axis_cq\.tuser ),
        .\s_axis_cq\.tvalid (\s_axis_cq\.tvalid ),
        .\tx_64.req_VDM_reg_0 (xdma_0_rx_demux_i_n_150),
        .\tx_64.req_bar_id_reg[2]_0 (req_bar_id),
        .\tx_64.req_msg_code_reg[7]_0 (req_msg_code),
        .\tx_64.req_rid_reg[15]_0 (m_axis_rx_tgt_tdata),
        .\tx_64.req_tag_reg[0]_0 (m_axis_rx_tgt_tvalid),
        .user_clk_out(user_clk_out),
        .user_reset_out(user_reset_out));
  xdma_0_tx_mux xdma_0_tx_mux_i
       (.\FSM_sequential_transfer_SM_reg[0]_0 (xdma_0_dma_req_i_n_7),
        .\FSM_sequential_transfer_SM_reg[1]_0 (xdma_0_tgt_cpl_i_n_0),
        .dmaFlag(dmaFlag),
        .\pcie_dma_in\.pcie_rq_seq_num_vld0 (\pcie_dma_in\.pcie_rq_seq_num_vld0 ),
        .s_axis_tx_req_tdata({s_axis_tx_req_tdata[63:48],s_axis_tx_req_tdata[33:32],s_axis_tx_req_tdata[30:29],s_axis_tx_req_tdata[22:20],s_axis_tx_req_tdata[18],s_axis_tx_req_tdata[14],s_axis_tx_req_tdata[12:2]}),
        .s_axis_tx_req_tlast(s_axis_tx_req_tlast),
        .s_axis_tx_req_tready(s_axis_tx_req_tready),
        .s_axis_tx_req_tvalid(s_axis_tx_req_tvalid),
        .s_axis_tx_tdata_i(s_axis_tx_tdata_i),
        .\s_axis_tx_tdata_reg[0]_0 (xdma_0_dma_req_i_n_35),
        .\s_axis_tx_tdata_reg[13]_0 (xdma_0_dma_req_i_n_33),
        .\s_axis_tx_tdata_reg[15]_0 (xdma_0_dma_req_i_n_32),
        .\s_axis_tx_tdata_reg[16]_0 (xdma_0_dma_req_i_n_31),
        .\s_axis_tx_tdata_reg[17]_0 (xdma_0_dma_req_i_n_30),
        .\s_axis_tx_tdata_reg[19]_0 (xdma_0_dma_req_i_n_29),
        .\s_axis_tx_tdata_reg[1]_0 (xdma_0_dma_req_i_n_34),
        .\s_axis_tx_tdata_reg[23]_0 (xdma_0_dma_req_i_n_28),
        .\s_axis_tx_tdata_reg[24]_0 (xdma_0_dma_req_i_n_27),
        .\s_axis_tx_tdata_reg[25]_0 (xdma_0_dma_req_i_n_26),
        .\s_axis_tx_tdata_reg[26]_0 (xdma_0_dma_req_i_n_25),
        .\s_axis_tx_tdata_reg[27]_0 (xdma_0_dma_req_i_n_24),
        .\s_axis_tx_tdata_reg[28]_0 (xdma_0_dma_req_i_n_23),
        .\s_axis_tx_tdata_reg[31]_0 (xdma_0_dma_req_i_n_22),
        .\s_axis_tx_tdata_reg[34]_0 (xdma_0_dma_req_i_n_21),
        .\s_axis_tx_tdata_reg[35]_0 (xdma_0_dma_req_i_n_20),
        .\s_axis_tx_tdata_reg[36]_0 (xdma_0_dma_req_i_n_19),
        .\s_axis_tx_tdata_reg[37]_0 (xdma_0_dma_req_i_n_18),
        .\s_axis_tx_tdata_reg[38]_0 (xdma_0_dma_req_i_n_17),
        .\s_axis_tx_tdata_reg[39]_0 (xdma_0_dma_req_i_n_16),
        .\s_axis_tx_tdata_reg[40]_0 (xdma_0_dma_req_i_n_15),
        .\s_axis_tx_tdata_reg[41]_0 (xdma_0_dma_req_i_n_14),
        .\s_axis_tx_tdata_reg[42]_0 (xdma_0_dma_req_i_n_13),
        .\s_axis_tx_tdata_reg[43]_0 (xdma_0_dma_req_i_n_12),
        .\s_axis_tx_tdata_reg[44]_0 (xdma_0_dma_req_i_n_11),
        .\s_axis_tx_tdata_reg[45]_0 (xdma_0_dma_req_i_n_10),
        .\s_axis_tx_tdata_reg[46]_0 (xdma_0_dma_req_i_n_9),
        .\s_axis_tx_tdata_reg[47]_0 (xdma_0_dma_req_i_n_8),
        .\s_axis_tx_tdata_reg[63]_0 (\s_axis_tx_tdata_reg[63] ),
        .s_axis_tx_tgt_tdata({s_axis_tx_tgt_tdata[63:48],s_axis_tx_tgt_tdata[33:32],s_axis_tx_tgt_tdata[30:29],s_axis_tx_tgt_tdata[22:20],s_axis_tx_tgt_tdata[18],s_axis_tx_tgt_tdata[14],s_axis_tx_tgt_tdata[12:2]}),
        .s_axis_tx_tgt_tready(s_axis_tx_tgt_tready),
        .s_axis_tx_tgt_tvalid(s_axis_tx_tgt_tvalid),
        .s_axis_tx_tkeep_i(s_axis_tx_tkeep_i),
        .\s_axis_tx_tkeep_reg[7]_0 (\s_axis_tx_tkeep_reg[7] ),
        .\s_axis_tx_tkeep_reg[7]_1 (xdma_0_dma_req_i_n_36),
        .s_axis_tx_tlast_i(s_axis_tx_tlast_i),
        .s_axis_tx_tlast_reg_0(s_axis_tx_tlast_reg),
        .s_axis_tx_tlast_reg_1(xdma_0_dma_req_i_n_37),
        .s_axis_tx_tready(s_axis_tx_tready),
        .s_axis_tx_tvalid_i(s_axis_tx_tvalid_i),
        .s_axis_tx_tvalid_reg_0(s_axis_tx_tvalid_reg),
        .transfer_SM(transfer_SM),
        .user_clk_out(user_clk_out),
        .user_reset_out(user_reset_out));
endmodule

module xdma_0_cfg_sideband
   (cfg_interrupt,
    cfg_interrupt_assert,
    \pcie_dma_in\.cfg_interrupt_sent ,
    \pcie_dma_in\.cfg_interrupt_msi_sent ,
    cfg_interrupt_di,
    E,
    user_reset_out,
    user_clk_out,
    cfg_interrupt_rdy,
    \pcie_dma_out\.cfg_interrupt_int ,
    cfg_interrupt_msienable,
    \pcie_dma_out\.cfg_interrupt_msi_int ,
    cfg_command,
    cfg_interrupt_mmenable,
    dmaFlag,
    cfg_interrupt_di_i);
  output cfg_interrupt;
  output cfg_interrupt_assert;
  output \pcie_dma_in\.cfg_interrupt_sent ;
  output \pcie_dma_in\.cfg_interrupt_msi_sent ;
  output [4:0]cfg_interrupt_di;
  output [0:0]E;
  input user_reset_out;
  input user_clk_out;
  input cfg_interrupt_rdy;
  input [0:0]\pcie_dma_out\.cfg_interrupt_int ;
  input cfg_interrupt_msienable;
  input [31:0]\pcie_dma_out\.cfg_interrupt_msi_int ;
  input [0:0]cfg_command;
  input [2:0]cfg_interrupt_mmenable;
  input dmaFlag;
  input [4:0]cfg_interrupt_di_i;

  wire [0:0]E;
  wire \Legacy_MSI_Interrupt.cfg_interrupt_reg_i_1_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_assert_i_1_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_10_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_11_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_2_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_3_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_4_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_5_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_6_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_7_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_8_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_9_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_1_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_2_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_3_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_4_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_5_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_6_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_7_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_8_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_9_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_2_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_3_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_4_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_5_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_6_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_2_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_3_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_4_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_5_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_6_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_7_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_5_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[0] ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[1] ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[2] ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[3] ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[4] ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_1_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_2_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_3_n_0 ;
  wire \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_4_n_0 ;
  wire \Legacy_MSI_Interrupt.interrupt_req_sent_i_1_n_0 ;
  wire \Legacy_MSI_Interrupt.interrupt_req_sent_i_2_n_0 ;
  wire \Legacy_MSI_Interrupt.interrupt_req_sent_i_3_n_0 ;
  wire [0:0]cfg_command;
  wire cfg_interrupt;
  wire cfg_interrupt_assert;
  wire [4:0]cfg_interrupt_di;
  wire [4:0]cfg_interrupt_di_i;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire cfg_interrupt_rdy;
  wire cfg_interrupt_reg;
  wire dmaFlag;
  wire [4:0]g2ip_cfg_interrupt_di;
  wire i__carry_i_1_n_0;
  wire i__carry_i_2_n_0;
  wire i__carry_i_3_n_0;
  wire i__carry_i_4_n_0;
  wire i__carry_i_5_n_0;
  wire i__carry_i_6_n_0;
  wire i__carry_i_7_n_0;
  wire i__carry_i_8_n_0;
  wire interrupt_req_sent;
  wire interrupt_req_sent0;
  wire \interrupt_req_sent0_inferred__0/i__carry_n_1 ;
  wire \interrupt_req_sent0_inferred__0/i__carry_n_2 ;
  wire \interrupt_req_sent0_inferred__0/i__carry_n_3 ;
  wire \pcie_dma_in\.cfg_interrupt_msi_sent ;
  wire \pcie_dma_in\.cfg_interrupt_sent ;
  wire [0:0]\pcie_dma_out\.cfg_interrupt_int ;
  wire [31:0]\pcie_dma_out\.cfg_interrupt_msi_int ;
  wire user_clk_out;
  wire user_reset_out;
  wire [3:0]\NLW_interrupt_req_sent0_inferred__0/i__carry_O_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair2098" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Legacy_MSI_Interrupt.cfg_interrupt_reg_i_1 
       (.I0(cfg_interrupt),
        .I1(cfg_interrupt_msienable),
        .I2(\pcie_dma_out\.cfg_interrupt_int ),
        .O(\Legacy_MSI_Interrupt.cfg_interrupt_reg_i_1_n_0 ));
  FDRE \Legacy_MSI_Interrupt.cfg_interrupt_reg_reg 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\Legacy_MSI_Interrupt.cfg_interrupt_reg_i_1_n_0 ),
        .Q(cfg_interrupt_reg),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2092" *) 
  LUT4 #(
    .INIT(16'hFD04)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_assert_i_1 
       (.I0(cfg_interrupt_reg),
        .I1(\pcie_dma_out\.cfg_interrupt_int ),
        .I2(cfg_interrupt_msienable),
        .I3(cfg_interrupt_assert),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_assert_i_1_n_0 ));
  FDRE \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_assert_reg 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_assert_i_1_n_0 ),
        .Q(cfg_interrupt_assert),
        .R(user_reset_out));
  LUT6 #(
    .INIT(64'hFFFFFFFF5454FF54)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_1 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_2_n_0 ),
        .I1(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_3_n_0 ),
        .I2(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_4_n_0 ),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [3]),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [2]),
        .I5(\pcie_dma_out\.cfg_interrupt_msi_int [1]),
        .O(g2ip_cfg_interrupt_di[0]));
  (* SOFT_HLUTNM = "soft_lutpair2088" *) 
  LUT5 #(
    .INIT(32'h000000F2)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_10 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [31]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [30]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [29]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [26]),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [28]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFF4)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_11 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [15]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [16]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [12]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [10]),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [14]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF00F4)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_2 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [7]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [8]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [6]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [5]),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [4]),
        .I5(\pcie_dma_out\.cfg_interrupt_msi_int [2]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAAB)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_3 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_5_n_0 ),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [24]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [22]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [20]),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_6_n_0 ),
        .I5(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_7_n_0 ),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF4544)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_4 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [10]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [11]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [12]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [13]),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_8_n_0 ),
        .I5(\pcie_dma_out\.cfg_interrupt_msi_int [9]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF4544)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_5 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [20]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [21]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [22]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [23]),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_9_n_0 ),
        .I5(\pcie_dma_out\.cfg_interrupt_msi_int [19]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2093" *) 
  LUT4 #(
    .INIT(16'h0045)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_6 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [25]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [26]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [27]),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_10_n_0 ),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2094" *) 
  LUT4 #(
    .INIT(16'hFF10)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_7 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [17]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [15]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [18]),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_11_n_0 ),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_8 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [7]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [5]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2094" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_9 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [17]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [15]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555550054)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_1 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [1]),
        .I1(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_2_n_0 ),
        .I2(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_3_n_0 ),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_4_n_0 ),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [3]),
        .I5(\pcie_dma_out\.cfg_interrupt_msi_int [2]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF54)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_2 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_5_n_0 ),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [15]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [14]),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_7_n_0 ),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [11]),
        .I5(\pcie_dma_out\.cfg_interrupt_msi_int [10]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2222222222220002)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_3 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_6_n_0 ),
        .I1(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_7_n_0 ),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [20]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [21]),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [18]),
        .I5(\pcie_dma_out\.cfg_interrupt_msi_int [19]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hEEEFEEEFEEEFEEEE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_4 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [4]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [5]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [7]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [6]),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [9]),
        .I5(\pcie_dma_out\.cfg_interrupt_msi_int [8]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2095" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_5 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [13]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [12]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFEFEFEFEFEFEFEFF)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_6 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_8_n_0 ),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [23]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [22]),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_9_n_0 ),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [25]),
        .I5(\pcie_dma_out\.cfg_interrupt_msi_int [24]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2095" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_7 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [12]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [13]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [16]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [17]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2091" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_8 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [19]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [18]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h1110111011101111)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_9 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [26]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [27]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [29]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [28]),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [31]),
        .I5(\pcie_dma_out\.cfg_interrupt_msi_int [30]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h01010100)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_1 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [3]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [2]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [1]),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_2_n_0 ),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_3_n_0 ),
        .O(g2ip_cfg_interrupt_di[2]));
  LUT6 #(
    .INIT(64'h0040444455555555)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_2 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_5_n_0 ),
        .I1(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_6_n_0 ),
        .I2(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_4_n_0 ),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6_n_0 ),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_5_n_0 ),
        .I5(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_6_n_0 ),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2096" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_3 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [6]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [7]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [4]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [5]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2088" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_4 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [30]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [31]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [28]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [29]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2087" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_5 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [22]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [23]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [20]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [21]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2089" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_6 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [14]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [15]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [12]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [13]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[2]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h005D)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_1 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_2_n_0 ),
        .I1(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_3_n_0 ),
        .I2(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_4_n_0 ),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_5_n_0 ),
        .O(g2ip_cfg_interrupt_di[3]));
  (* SOFT_HLUTNM = "soft_lutpair2089" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_2 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [13]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [12]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [15]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [14]),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_5_n_0 ),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_3 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [29]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [28]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [31]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [30]),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6_n_0 ),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2087" *) 
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_4 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [21]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [20]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [23]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [22]),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_6_n_0 ),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_5 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [5]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [4]),
        .I2(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_7_n_0 ),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [3]),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [2]),
        .I5(\pcie_dma_out\.cfg_interrupt_msi_int [1]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2091" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_6 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [18]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [19]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [16]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [17]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2096" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_7 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [7]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [6]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1 
       (.I0(cfg_interrupt_msienable),
        .I1(user_reset_out),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2090" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_2 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3_n_0 ),
        .I1(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4_n_0 ),
        .O(g2ip_cfg_interrupt_di[4]));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_5_n_0 ),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [14]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [15]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [12]),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [13]),
        .I5(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_5_n_0 ),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6_n_0 ),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [30]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [31]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [28]),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [29]),
        .I5(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[3]_i_4_n_0 ),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_5 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [10]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [11]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [8]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [9]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2093" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6 
       (.I0(\pcie_dma_out\.cfg_interrupt_msi_int [24]),
        .I1(\pcie_dma_out\.cfg_interrupt_msi_int [25]),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [26]),
        .I3(\pcie_dma_out\.cfg_interrupt_msi_int [27]),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_6_n_0 ));
  FDRE \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg[0] 
       (.C(user_clk_out),
        .CE(E),
        .D(g2ip_cfg_interrupt_di[0]),
        .Q(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[0] ),
        .R(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0 ));
  FDRE \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg[1] 
       (.C(user_clk_out),
        .CE(E),
        .D(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[1]_i_1_n_0 ),
        .Q(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[1] ),
        .R(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0 ));
  FDRE \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg[2] 
       (.C(user_clk_out),
        .CE(E),
        .D(g2ip_cfg_interrupt_di[2]),
        .Q(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[2] ),
        .R(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0 ));
  FDRE \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg[3] 
       (.C(user_clk_out),
        .CE(E),
        .D(g2ip_cfg_interrupt_di[3]),
        .Q(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[3] ),
        .R(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0 ));
  FDRE \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg[4] 
       (.C(user_clk_out),
        .CE(E),
        .D(g2ip_cfg_interrupt_di[4]),
        .Q(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[4] ),
        .R(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0B0A)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_1 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_2_n_0 ),
        .I1(cfg_interrupt_rdy),
        .I2(user_reset_out),
        .I3(cfg_interrupt),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hABABABABABABAAAB)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_2 
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_3_n_0 ),
        .I1(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_4_n_0 ),
        .I2(cfg_interrupt_reg),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3_n_0 ),
        .I4(\pcie_dma_out\.cfg_interrupt_msi_int [0]),
        .I5(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4_n_0 ),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2092" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_3 
       (.I0(cfg_interrupt_reg),
        .I1(\pcie_dma_out\.cfg_interrupt_int ),
        .I2(cfg_interrupt_msienable),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2086" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_4 
       (.I0(cfg_interrupt_msienable),
        .I1(cfg_command),
        .O(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_4_n_0 ));
  FDRE \Legacy_MSI_Interrupt.g2ip_cfg_interrupt_reg 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_i_1_n_0 ),
        .Q(cfg_interrupt),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2086" *) 
  LUT5 #(
    .INIT(32'h0000FD00)) 
    \Legacy_MSI_Interrupt.interrupt_req_sent_i_1 
       (.I0(cfg_interrupt_msienable),
        .I1(cfg_command),
        .I2(\Legacy_MSI_Interrupt.interrupt_req_sent_i_2_n_0 ),
        .I3(\Legacy_MSI_Interrupt.interrupt_req_sent_i_3_n_0 ),
        .I4(user_reset_out),
        .O(\Legacy_MSI_Interrupt.interrupt_req_sent_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2090" *) 
  LUT4 #(
    .INIT(16'hAAAE)) 
    \Legacy_MSI_Interrupt.interrupt_req_sent_i_2 
       (.I0(cfg_interrupt_reg),
        .I1(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_3_n_0 ),
        .I2(\pcie_dma_out\.cfg_interrupt_msi_int [0]),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di[4]_i_4_n_0 ),
        .O(\Legacy_MSI_Interrupt.interrupt_req_sent_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF090000F0090000)) 
    \Legacy_MSI_Interrupt.interrupt_req_sent_i_3 
       (.I0(cfg_interrupt_reg),
        .I1(\pcie_dma_out\.cfg_interrupt_int ),
        .I2(interrupt_req_sent),
        .I3(cfg_interrupt_msienable),
        .I4(cfg_interrupt_rdy),
        .I5(interrupt_req_sent0),
        .O(\Legacy_MSI_Interrupt.interrupt_req_sent_i_3_n_0 ));
  FDRE \Legacy_MSI_Interrupt.interrupt_req_sent_reg 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\Legacy_MSI_Interrupt.interrupt_req_sent_i_1_n_0 ),
        .Q(interrupt_req_sent),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    dma_cpl_fifo_inst_i_1
       (.I0(user_reset_out),
        .O(E));
  LUT2 #(
    .INIT(4'h8)) 
    i__carry_i_1
       (.I0(cfg_interrupt_mmenable[1]),
        .I1(cfg_interrupt_mmenable[2]),
        .O(i__carry_i_1_n_0));
  LUT4 #(
    .INIT(16'h4044)) 
    i__carry_i_2
       (.I0(cfg_interrupt_mmenable[1]),
        .I1(cfg_interrupt_mmenable[2]),
        .I2(cfg_interrupt_mmenable[0]),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[4] ),
        .O(i__carry_i_2_n_0));
  LUT5 #(
    .INIT(32'h10001100)) 
    i__carry_i_3
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[3] ),
        .I1(cfg_interrupt_mmenable[2]),
        .I2(cfg_interrupt_mmenable[0]),
        .I3(cfg_interrupt_mmenable[1]),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[2] ),
        .O(i__carry_i_3_n_0));
  LUT5 #(
    .INIT(32'h00100011)) 
    i__carry_i_4
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[1] ),
        .I1(cfg_interrupt_mmenable[2]),
        .I2(cfg_interrupt_mmenable[0]),
        .I3(cfg_interrupt_mmenable[1]),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[0] ),
        .O(i__carry_i_4_n_0));
  LUT2 #(
    .INIT(4'h7)) 
    i__carry_i_5
       (.I0(cfg_interrupt_mmenable[2]),
        .I1(cfg_interrupt_mmenable[1]),
        .O(i__carry_i_5_n_0));
  LUT4 #(
    .INIT(16'h04F3)) 
    i__carry_i_6
       (.I0(cfg_interrupt_mmenable[0]),
        .I1(cfg_interrupt_mmenable[2]),
        .I2(cfg_interrupt_mmenable[1]),
        .I3(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[4] ),
        .O(i__carry_i_6_n_0));
  LUT5 #(
    .INIT(32'h00045951)) 
    i__carry_i_7
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[3] ),
        .I1(cfg_interrupt_mmenable[1]),
        .I2(cfg_interrupt_mmenable[2]),
        .I3(cfg_interrupt_mmenable[0]),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[2] ),
        .O(i__carry_i_7_n_0));
  LUT5 #(
    .INIT(32'h00015654)) 
    i__carry_i_8
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[1] ),
        .I1(cfg_interrupt_mmenable[1]),
        .I2(cfg_interrupt_mmenable[2]),
        .I3(cfg_interrupt_mmenable[0]),
        .I4(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[0] ),
        .O(i__carry_i_8_n_0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 \interrupt_req_sent0_inferred__0/i__carry 
       (.CI(1'b0),
        .CO({interrupt_req_sent0,\interrupt_req_sent0_inferred__0/i__carry_n_1 ,\interrupt_req_sent0_inferred__0/i__carry_n_2 ,\interrupt_req_sent0_inferred__0/i__carry_n_3 }),
        .CYINIT(1'b0),
        .DI({i__carry_i_1_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4_n_0}),
        .O(\NLW_interrupt_req_sent0_inferred__0/i__carry_O_UNCONNECTED [3:0]),
        .S({i__carry_i_5_n_0,i__carry_i_6_n_0,i__carry_i_7_n_0,i__carry_i_8_n_0}));
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_238
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[4] ),
        .I1(dmaFlag),
        .I2(cfg_interrupt_di_i[4]),
        .O(cfg_interrupt_di[4]));
  (* SOFT_HLUTNM = "soft_lutpair2099" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_239
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[3] ),
        .I1(dmaFlag),
        .I2(cfg_interrupt_di_i[3]),
        .O(cfg_interrupt_di[3]));
  (* SOFT_HLUTNM = "soft_lutpair2099" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_240
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[2] ),
        .I1(dmaFlag),
        .I2(cfg_interrupt_di_i[2]),
        .O(cfg_interrupt_di[2]));
  (* SOFT_HLUTNM = "soft_lutpair2097" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_241
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[1] ),
        .I1(dmaFlag),
        .I2(cfg_interrupt_di_i[1]),
        .O(cfg_interrupt_di[1]));
  (* SOFT_HLUTNM = "soft_lutpair2097" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_242
       (.I0(\Legacy_MSI_Interrupt.g2ip_cfg_interrupt_di_reg_n_0_[0] ),
        .I1(dmaFlag),
        .I2(cfg_interrupt_di_i[0]),
        .O(cfg_interrupt_di[0]));
  LUT2 #(
    .INIT(4'h8)) 
    udma_wrapper_i_145
       (.I0(cfg_interrupt_msienable),
        .I1(interrupt_req_sent),
        .O(\pcie_dma_in\.cfg_interrupt_msi_sent ));
  (* SOFT_HLUTNM = "soft_lutpair2098" *) 
  LUT2 #(
    .INIT(4'h2)) 
    udma_wrapper_i_146
       (.I0(interrupt_req_sent),
        .I1(cfg_interrupt_msienable),
        .O(\pcie_dma_in\.cfg_interrupt_sent ));
endmodule

(* ACS_EXT_CAP_ENABLE = "FALSE" *) (* AXI4MM_ULTRA = "0" *) (* AXILITE_MASTER_APERTURE_SIZE = "8'b00001101" *) 
(* AXILITE_MASTER_CONTROL = "3'b000" *) (* AXISTEN_IF_ENABLE_MSG_ROUTE = "18'b000000000000000000" *) (* AXIST_BYPASS_APERTURE_SIZE = "8'b00001101" *) 
(* AXIST_BYPASS_CONTROL = "3'b100" *) (* AXIS_CCIX_RX_TDATA_WIDTH = "256" *) (* AXIS_CCIX_RX_TUSER_WIDTH = "47" *) 
(* AXIS_CCIX_TX_TDATA_WIDTH = "256" *) (* AXIS_CCIX_TX_TUSER_WIDTH = "47" *) (* AXIS_PIPE_LINE_STAGE = "0" *) 
(* AXI_ACLK_LOOPBACK = "FALSE" *) (* AXI_ADDR_WIDTH = "64" *) (* AXI_DATA_WIDTH = "64" *) 
(* AXI_VIP_IN_EXDES = "FALSE" *) (* AXSIZE_BYTE_ACCESS_EN = "FALSE" *) (* BACKPRESSURE = "0" *) 
(* BARLITE0 = "7" *) (* BARLITE1 = "0" *) (* BARLITE2 = "7" *) 
(* BARLITE_EXT_PF0 = "6'b000000" *) (* BARLITE_EXT_PF1 = "6'b000000" *) (* BARLITE_EXT_PF2 = "6'b000000" *) 
(* BARLITE_EXT_PF3 = "6'b000000" *) (* BARLITE_INT_PF0 = "6'b000001" *) (* BARLITE_INT_PF1 = "6'b000000" *) 
(* BARLITE_INT_PF2 = "6'b000000" *) (* BARLITE_INT_PF3 = "6'b000000" *) (* BRIDGE_BURST = "FALSE" *) 
(* C2H_XDMA_CHNL = "8'b00001111" *) (* CCIX_DVSEC = "FALSE" *) (* CCIX_ENABLE = "FALSE" *) 
(* CDC_WB_EN = "1" *) (* CFG_EXT_IF = "FALSE" *) (* CFG_MGMT_IF = "TRUE" *) 
(* CFG_SPACE_ENABLE = "FALSE" *) (* COMPONENT_NAME = "xdma_0" *) (* CORE_CLK_FREQ = "2" *) 
(* C_ADDR_ALGN = "1" *) (* C_ADDR_BITS = "64" *) (* C_ATS_CAP_NEXTPTR = "12'b000000000000" *) 
(* C_ATS_CC_TUSER_WIDTH = "33" *) (* C_ATS_CQ_TUSER_WIDTH = "85" *) (* C_ATS_DATA_WIDTH = "64" *) 
(* C_ATS_ENABLE = "FALSE" *) (* C_ATS_OFFSET = "30'b000000000000000000000100100000" *) (* C_ATS_RC_TUSER_WIDTH = "75" *) 
(* C_ATS_RQ_TUSER_WIDTH = "60" *) (* C_ATS_SWITCH_UNIQUE_BDF = "1" *) (* C_AXIBAR2PCIEATTR_0 = "3'b000" *) 
(* C_AXIBAR2PCIEATTR_1 = "3'b000" *) (* C_AXIBAR2PCIEATTR_2 = "3'b000" *) (* C_AXIBAR2PCIEATTR_3 = "3'b000" *) 
(* C_AXIBAR2PCIEATTR_4 = "3'b000" *) (* C_AXIBAR2PCIEATTR_5 = "3'b000" *) (* C_AXIBAR2PCIEBAR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_AXIBAR2PCIEBAR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR2PCIEBAR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR2PCIEBAR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_AXIBAR2PCIEBAR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR2PCIEBAR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_AXIBAR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_AXIBAR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR_AS_0 = "1" *) 
(* C_AXIBAR_AS_1 = "1" *) (* C_AXIBAR_AS_2 = "1" *) (* C_AXIBAR_AS_3 = "1" *) 
(* C_AXIBAR_AS_4 = "1" *) (* C_AXIBAR_AS_5 = "1" *) (* C_AXIBAR_HIGHADDR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_AXIBAR_HIGHADDR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR_HIGHADDR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR_HIGHADDR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_AXIBAR_HIGHADDR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR_HIGHADDR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_AXIBAR_NOXLATE = "0" *) 
(* C_AXIBAR_NUM = "1" *) (* C_AXIBAR_REGIONEN = "0" *) (* C_BASEADDR = "4096" *) 
(* C_C2H_NUM_CHNL = "1" *) (* C_C2H_NUM_RIDS = "16" *) (* C_C2H_TUSER_WIDTH = "64" *) 
(* C_COMP_TIMEOUT = "1" *) (* C_DEVICE_NUMBER = "0" *) (* C_DSC_MAGIC_EN = "1" *) 
(* C_ECC_ENABLE = "0" *) (* C_ENABLE_RESOURCE_REDUCTION = "FALSE" *) (* C_ERRC_DEC_EN = "0" *) 
(* C_FAMILY = "artix7" *) (* C_FF_ON_INT_IF = "FALSE" *) (* C_GEN2_DEVICES = "1'b1" *) 
(* C_H2C_NUM_CHNL = "1" *) (* C_H2C_NUM_RIDS = "32" *) (* C_H2C_TUSER_WIDTH = "48" *) 
(* C_HIGHADDR = "8191" *) (* C_IGNORE_SIZE_AXI_SLAVE = "1" *) (* C_INCLUDE_BAROFFSET_REG = "1" *) 
(* C_INCLUDE_RC = "0" *) (* C_INTX_RX_PIN_EN = "1" *) (* C_INV_QUEUE_DEPTH = "5'b00000" *) 
(* C_KEEP_WIDTH = "8" *) (* C_LAST_CORE_CAP_ADDR = "12'b000100000000" *) (* C_LEGACY_INT_EN = "TRUE" *) 
(* C_METERING_ON = "1" *) (* C_MSIX_INT_TABLE_EN = "0" *) (* C_MSIX_RX_PIN_EN = "1" *) 
(* C_MSI_ENABLED = "TRUE" *) (* C_MSI_RX_PIN_EN = "0" *) (* C_M_AXIL_ARUSER_WIDTH = "11" *) 
(* C_M_AXIL_AWUSER_WIDTH = "11" *) (* C_M_AXIS_DATA_WIDTH = "64" *) (* C_M_AXIS_RC_USER_WIDTH = "75" *) 
(* C_M_AXIS_RQ_USER_WIDTH = "60" *) (* C_M_AXIS_USER_WIDTH = "64" *) (* C_M_AXI_ADDR_WIDTH = "64" *) 
(* C_M_AXI_ARUSER_WIDTH = "8" *) (* C_M_AXI_AWUSER_WIDTH = "8" *) (* C_M_AXI_BUSER_WIDTH = "1" *) 
(* C_M_AXI_DATA_WIDTH = "64" *) (* C_M_AXI_ID_WIDTH = "4" *) (* C_M_AXI_NUM_READ = "8" *) 
(* C_M_AXI_NUM_READQ = "2" *) (* C_M_AXI_NUM_WRITE = "4" *) (* C_M_AXI_NUM_WRITE_SCALE = "1" *) 
(* C_M_AXI_RUSER_WIDTH = "8" *) (* C_M_AXI_WUSER_WIDTH = "8" *) (* C_M_KEEP_WIDTH = "2" *) 
(* C_NUMQ_PER_CHNL = "256" *) (* C_NUM_AXI_DSC_CPL_DID = "64" *) (* C_NUM_DSC_PCIE_RID = "32" *) 
(* C_NUM_MSIX_VECTORS = "32" *) (* C_NUM_OF_SC = "1" *) (* C_NUM_PCIE_DSC_CPL_DID = "256" *) 
(* C_NUM_USER_INTR = "9" *) (* C_NUM_USER_NEW_INTR = "6" *) (* C_NUM_USR_IRQ = "1" *) 
(* C_OLD_BRIDGE_TIMEOUT = "0" *) (* C_OST_PR_CAP = "0" *) (* C_PARITY_CHECK = "0" *) 
(* C_PARITY_GEN = "0" *) (* C_PARITY_PROP = "0" *) (* C_PCIEBAR2AXIBAR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_PCIEBAR2AXIBAR_0_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_PCIEBAR2AXIBAR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_PCIEBAR2AXIBAR_1_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_PCIEBAR2AXIBAR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_PCIEBAR2AXIBAR_2_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_PCIEBAR2AXIBAR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_PCIEBAR2AXIBAR_3_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_PCIEBAR2AXIBAR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_PCIEBAR2AXIBAR_4_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_PCIEBAR2AXIBAR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_PCIEBAR2AXIBAR_5_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_PCIEBAR2AXIBAR_6 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_PCIEBAR2AXIBAR_6_TMP = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_PCIEBAR_AS = "1" *) (* C_PCIEBAR_LEN_0 = "16" *) 
(* C_PCIEBAR_LEN_1 = "20" *) (* C_PCIEBAR_LEN_2 = "64" *) (* C_PCIEBAR_LEN_3 = "64" *) 
(* C_PCIEBAR_LEN_4 = "64" *) (* C_PCIEBAR_LEN_5 = "64" *) (* C_PCIEBAR_LEN_6 = "7" *) 
(* C_PCIEBAR_NUM = "6" *) (* C_PCIE_PFS_SUPPORTED = "0" *) (* C_PRI_ENABLE = "FALSE" *) 
(* C_PR_CAP_NEXTPTR = "12'b000000000000" *) (* C_PR_OFFSET = "30'b000000000000000000000100100100" *) (* C_RD_BUFFER_ADDR_SIZE = "9" *) 
(* C_RD_BUFFER_SIZE_BITS = "5" *) (* C_SLAVE_READ_64OS_EN = "0" *) (* C_SMMU_EN = "0" *) 
(* C_SRIOV_EN = "0" *) (* C_S_AXIS_CC_USER_WIDTH = "33" *) (* C_S_AXIS_CQP_USER_WIDTH = "85" *) 
(* C_S_AXIS_CQ_USER_WIDTH = "85" *) (* C_S_AXIS_DATA_WIDTH = "64" *) (* C_S_AXIS_USER_WIDTH = "64" *) 
(* C_S_AXI_ADDR_WIDTH = "64" *) (* C_S_AXI_DATA_WIDTH = "64" *) (* C_S_AXI_ID_WIDTH = "4" *) 
(* C_S_AXI_NUM_READ = "8" *) (* C_S_AXI_NUM_WRITE = "8" *) (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *) 
(* C_S_KEEP_WIDTH = "2" *) (* C_TIMEOUT0_SEL = "4'b1110" *) (* C_TIMEOUT1_SEL = "4'b1111" *) 
(* C_TIMEOUT_MULT = "3'b011" *) (* C_USER_PTR = "16'b0000000011011000" *) (* C_VSEC_CAP_ADDR = "12'b000100101000" *) 
(* C_VSEC_CAP_LAST = "FALSE" *) (* C_VSEC_ID = "16'b0000000000000000" *) (* DAT_WIDTH = "64" *) 
(* DEDICATE_PERST = "true" *) (* DEV_PORT_TYPE = "0" *) (* DIFF_AXI_ADDR_WIDTH = "0" *) 
(* DISABLE_BRAM_PIPELINE = "FALSE" *) (* DISABLE_EQ_SYNCHRONIZER = "FALSE" *) (* DMA_2RP = "FALSE" *) 
(* DMA_EN = "1" *) (* DMA_MM = "1" *) (* DMA_RESET_SOURCE_SEL = "0" *) 
(* DMA_SP = "0" *) (* DMA_ST = "0" *) (* DRP_CLK_SEL = "0" *) 
(* DSC_BYPASS_RD = "0" *) (* DSC_BYPASS_WR = "0" *) (* EGW_IS_PARENT_IP = "1" *) 
(* ENABLE_ATS_SWITCH = "FALSE" *) (* ENABLE_ERROR_INJECTION = "FALSE" *) (* ENABLE_IBERT = "FALSE" *) 
(* ENABLE_JTAG_DBG = "FALSE" *) (* ENABLE_LTSSM_DBG = "FALSE" *) (* ENABLE_MORE = "FALSE" *) 
(* EN_AXI_MASTER_IF = "TRUE" *) (* EN_AXI_SLAVE_IF = "TRUE" *) (* EN_DEBUG_PORTS = "FALSE" *) 
(* EN_GT_SELECTION = "FALSE" *) (* EN_PCIE_DEBUG_PORTS = "FALSE" *) (* EN_RCHNL_0 = "TRUE" *) 
(* EN_RCHNL_1 = "FALSE" *) (* EN_RCHNL_2 = "FALSE" *) (* EN_RCHNL_3 = "FALSE" *) 
(* EN_RCHNL_4 = "FALSE" *) (* EN_RCHNL_5 = "FALSE" *) (* EN_RCHNL_6 = "FALSE" *) 
(* EN_RCHNL_7 = "FALSE" *) (* EN_TRANSCEIVER_STATUS_PORTS = "FALSE" *) (* EN_WCHNL_0 = "TRUE" *) 
(* EN_WCHNL_1 = "FALSE" *) (* EN_WCHNL_2 = "FALSE" *) (* EN_WCHNL_3 = "FALSE" *) 
(* EN_WCHNL_4 = "FALSE" *) (* EN_WCHNL_5 = "FALSE" *) (* EN_WCHNL_6 = "FALSE" *) 
(* EN_WCHNL_7 = "FALSE" *) (* ERRC_DEC_EN = "FALSE" *) (* EXT_CH_GT_DRP = "false" *) 
(* EXT_STARTUP_PRIMITIVE = "false" *) (* EXT_SYS_CLK_BUFG = "FALSE" *) (* EXT_XVC_VSEC_ENABLE = "FALSE" *) 
(* FIRSTVF_OFFSET_PF0 = "0" *) (* FIRSTVF_OFFSET_PF1 = "0" *) (* FIRSTVF_OFFSET_PF2 = "0" *) 
(* FIRSTVF_OFFSET_PF3 = "0" *) (* FLR_ENABLE = "FALSE" *) (* FREE_RUN_FREQ = "0" *) 
(* FUNC_MODE = "1" *) (* GEN4_EIEOS_0S7 = "TRUE" *) (* GTCOM_IN_CORE = "2" *) 
(* GTWIZ_IN_CORE = "1" *) (* H2C_XDMA_CHNL = "8'b00001111" *) (* IMPL_TARGET = "SOFT" *) 
(* INS_LOSS_PROFILE = "Add-in_Card" *) (* INTERRUPT_OUT_WIDTH = "1" *) (* IS_BOARD_PROJECT = "0" *) 
(* LEGACY_CFG_EXT_IF = "FALSE" *) (* MCAP_ENABLEMENT = "NONE" *) (* MCAP_FPGA_BITSTREAM_VERSION = "0" *) 
(* MM_SLAVE_EN = "0" *) (* MSIX_ENABLED = "FALSE" *) (* MSIX_IMPL_EXT = "FALSE" *) 
(* MSIX_PCIE_INTERNAL = "0" *) (* MSIX_RX_DECODE_EN = "FALSE" *) (* MSIX_VEC_NUM = "1024" *) 
(* MSI_ENABLED = "TRUE" *) (* MULTQ_CHNL = "8'b00000000" *) (* MULTQ_EN = "0" *) 
(* MULT_PF_DES = "FALSE" *) (* MULT_PF_DESIGN = "0" *) (* NUM_PFS = "1" *) 
(* NUM_VFS_PF0 = "0" *) (* NUM_VFS_PF1 = "0" *) (* NUM_VFS_PF2 = "0" *) 
(* NUM_VFS_PF3 = "0" *) (* PCIE3_DRP = "false" *) (* PCIEBAR_NUM = "6" *) 
(* PCIE_BLK_LOCN = "0" *) (* PCIE_BLK_TYPE = "0" *) (* PCIE_ID_IF = "FALSE" *) 
(* PF0_BAR0_APERTURE_SIZE = "8'b00001010" *) (* PF0_BAR0_CONTROL = "3'b100" *) (* PF0_BAR1_APERTURE_SIZE = "8'b00000101" *) 
(* PF0_BAR1_CONTROL = "3'b000" *) (* PF0_BAR2_APERTURE_SIZE = "8'b00000101" *) (* PF0_BAR2_CONTROL = "3'b000" *) 
(* PF0_BAR3_APERTURE_SIZE = "8'b00000101" *) (* PF0_BAR3_CONTROL = "3'b000" *) (* PF0_BAR4_APERTURE_SIZE = "8'b00000101" *) 
(* PF0_BAR4_CONTROL = "3'b000" *) (* PF0_BAR5_APERTURE_SIZE = "8'b00000101" *) (* PF0_BAR5_CONTROL = "3'b000" *) 
(* PF0_CLASS_CODE = "24'b000001110000000000000001" *) (* PF0_DEVICE_ID = "16'b0111000000100010" *) (* PF0_EXPANSION_ROM_APERTURE_SIZE = "5'b00000" *) 
(* PF0_EXPANSION_ROM_ENABLE = "FALSE" *) (* PF0_INTERRUPT_PIN = "3'b001" *) (* PF0_MSIX_TAR_ID = "6'b001000" *) 
(* PF0_MSI_CAP_MULTIMSGCAP = "0" *) (* PF0_REVISION_ID = "8'b00000000" *) (* PF0_SUBSYSTEM_ID = "16'b0000000000000111" *) 
(* PF0_SUBSYSTEM_VENDOR_ID = "16'b0001000011101110" *) (* PF0_VENDOR_ID = "16'b0001000011101110" *) (* PF1_BAR0_APERTURE_SIZE = "8'b00010010" *) 
(* PF1_BAR0_CONTROL = "3'b100" *) (* PF1_BAR1_APERTURE_SIZE = "8'b00001010" *) (* PF1_BAR1_CONTROL = "3'b100" *) 
(* PF1_BAR2_APERTURE_SIZE = "8'b00001010" *) (* PF1_BAR2_CONTROL = "3'b110" *) (* PF1_BAR3_APERTURE_SIZE = "8'b00001010" *) 
(* PF1_BAR3_CONTROL = "3'b000" *) (* PF1_BAR4_APERTURE_SIZE = "8'b00001010" *) (* PF1_BAR4_CONTROL = "3'b110" *) 
(* PF1_BAR5_APERTURE_SIZE = "8'b00001010" *) (* PF1_BAR5_CONTROL = "3'b000" *) (* PF1_CLASS_CODE = "24'b000001110000000000000001" *) 
(* PF1_DEVICE_ID = "16'b0001000001000001" *) (* PF1_ENABLED = "0" *) (* PF1_EXPANSION_ROM_APERTURE_SIZE = "5'b00000" *) 
(* PF1_EXPANSION_ROM_ENABLE = "FALSE" *) (* PF1_MSIX_TAR_ID = "6'b001001" *) (* PF1_PCIEBAR2AXIBAR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* PF1_PCIEBAR2AXIBAR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* PF1_PCIEBAR2AXIBAR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* PF1_PCIEBAR2AXIBAR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* PF1_PCIEBAR2AXIBAR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* PF1_PCIEBAR2AXIBAR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* PF1_PCIEBAR2AXIBAR_6 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* PF1_REVISION_ID = "8'b00000000" *) (* PF1_SUBSYSTEM_ID = "16'b0000000000000111" *) (* PF1_SUBSYSTEM_VENDOR_ID = "16'b0001000011101110" *) 
(* PF1_VENDOR_ID = "16'b0001000011101110" *) (* PF2_DEVICE_ID = "16'b0001000001000000" *) (* PF2_ENABLED = "0" *) 
(* PF2_REVISION_ID = "8'b00000000" *) (* PF2_SUBSYSTEM_ID = "16'b0000000000000111" *) (* PF3_DEVICE_ID = "16'b0001000000111001" *) 
(* PF3_ENABLED = "0" *) (* PF3_REVISION_ID = "8'b00000000" *) (* PF3_SUBSYSTEM_ID = "16'b0000000000000111" *) 
(* PF_SWAP = "FALSE" *) (* PIPE_DEBUG_EN = "FALSE" *) (* PIPE_LINE_STAGE = "2" *) 
(* PIPE_SIM = "FALSE" *) (* PLL_TYPE = "2" *) (* PL_DISABLE_UPCONFIG_CAPABLE = "FALSE" *) 
(* PL_LINK_CAP_MAX_LINK_SPEED = "2" *) (* PL_LINK_CAP_MAX_LINK_WIDTH = "2" *) (* PL_UPSTREAM_FACING = "true" *) 
(* PMON_EN = "1" *) (* PROG_USR_IRQ_VEC_MAP = "0" *) (* RBAR_ENABLE = "FALSE" *) 
(* RD_CH0_ENABLED = "FALSE" *) (* RD_CH1_ENABLED = "FALSE" *) (* RD_CH2_ENABLED = "FALSE" *) 
(* RD_CH3_ENABLED = "FALSE" *) (* REF_CLK_FREQ = "0" *) (* RQ_SEQ_NUM_IGNORE = "0" *) 
(* RUNBIT_FIX = "FALSE" *) (* RUN_BIT_FIX = "0" *) (* RX_DETECT = "0" *) 
(* SELECT_QUAD = "GTH_Quad_128" *) (* SHARED_LOGIC = "0" *) (* SHARED_LOGIC_BOTH = "false" *) 
(* SHARED_LOGIC_BOTH_7XG2 = "false" *) (* SHARED_LOGIC_CLK = "false" *) (* SHARED_LOGIC_CLK_7XG2 = "false" *) 
(* SHARED_LOGIC_GTC = "false" *) (* SHARED_LOGIC_GTC_7XG2 = "false" *) (* SHELL_BRIDGE = "0" *) 
(* SILICON_REV = "Pre-Production" *) (* SOFT_RESET_EN = "FALSE" *) (* SPLIT_DMA = "FALSE" *) 
(* SPLIT_DMA_SINGLE_PF = "FALSE" *) (* SRIOV_ACTIVE_VFS = "252" *) (* SRIOV_EN = "0" *) 
(* STS_WIDTH = "8" *) (* SYS_RESET_POLARITY = "0" *) (* TANDEM_RFSOC = "FALSE" *) 
(* TCQ = "1" *) (* TL_LEGACY_MODE_ENABLE = "false" *) (* TL_PF_ENABLE_REG = "2'b00" *) 
(* ULTRASCALE = "FALSE" *) (* ULTRASCALE_PLUS = "FALSE" *) (* USER_CLK_FREQ = "1" *) 
(* USE_ATTR = "0" *) (* USE_STANDARD_INTERFACES = "FALSE" *) (* USRINT_EXPN = "FALSE" *) 
(* USR_INT_EXPN = "0" *) (* USR_IRQ_EXDES = "FALSE" *) (* USR_MPL_SIZE = "4096" *) 
(* USR_MRS_SIZE = "4096" *) (* V7_GEN3 = "FALSE" *) (* VCU118_BOARD = "FALSE" *) 
(* VCU1262 = "FALSE" *) (* VDM_EN = "FALSE" *) (* VERSAL = "FALSE" *) 
(* VERSAL_PART_TYPE = "SXX" *) (* VERSION = "6" *) (* VF_BARLITE_EXT_PF0 = "6'b000000" *) 
(* VF_BARLITE_EXT_PF1 = "6'b000000" *) (* VF_BARLITE_EXT_PF2 = "6'b000000" *) (* VF_BARLITE_EXT_PF3 = "6'b000000" *) 
(* VF_BARLITE_INT_PF0 = "6'b000001" *) (* VF_BARLITE_INT_PF1 = "6'b000001" *) (* VF_BARLITE_INT_PF2 = "6'b000001" *) 
(* VF_BARLITE_INT_PF3 = "6'b000001" *) (* VU9P_BOARD = "FALSE" *) (* VU9P_TUL_EX = "FALSE" *) 
(* WR_CH0_ENABLED = "FALSE" *) (* WR_CH1_ENABLED = "FALSE" *) (* WR_CH2_ENABLED = "FALSE" *) 
(* WR_CH3_ENABLED = "FALSE" *) (* XDMA_APERTURE_SIZE = "8'b00001001" *) (* XDMA_AXILITE_MASTER = "FALSE" *) 
(* XDMA_AXILITE_SLAVE = "FALSE" *) (* XDMA_AXIST_BYPASS = "TRUE" *) (* XDMA_AXI_INTF_MM = "1" *) 
(* XDMA_CONTROL = "3'b100" *) (* XDMA_DSC_BYPASS = "FALSE" *) (* XDMA_DSC_ENG = "1" *) 
(* XDMA_NON_INCREMENTAL_EXDES = "FALSE" *) (* XDMA_NUM_PCIE_TAG = "64" *) (* XDMA_NUM_USR_IRQ = "1" *) 
(* XDMA_PCIE_64BIT_EN = "xdma_pcie_64bit_en" *) (* XDMA_RNUM_CHNL = "1" *) (* XDMA_RNUM_RIDS = "32" *) 
(* XDMA_STS_PORTS = "FALSE" *) (* XDMA_ST_INFINITE_DESC_EXDES = "FALSE" *) (* XDMA_WNUM_CHNL = "1" *) 
(* XDMA_WNUM_RIDS = "16" *) (* xlnx_ref_board = "None" *) 
module xdma_0_core_top
   (sys_clk,
    sys_clk_ce_out,
    sys_clk_gt,
    sys_rst_n,
    dma_bridge_resetn,
    user_lnk_up,
    cfg_ltssm_state,
    config_space_enable,
    pci_exp_txp,
    pci_exp_txn,
    pci_exp_rxp,
    pci_exp_rxn,
    free_run_clock,
    gt_drp_clk,
    axi_aclk,
    axi_aresetn,
    axi_ctl_aclk,
    axi_ctl_aresetn,
    usr_irq_req,
    usr_irq_ack,
    usr_irq_function_number,
    msi_enable,
    msix_enable,
    msi_vector_width,
    m_axi_awid,
    m_axi_awaddr,
    m_axi_awlen,
    m_axi_awsize,
    m_axi_awburst,
    m_axi_awprot,
    m_axi_awvalid,
    m_axi_awready,
    m_axi_awlock,
    m_axi_awcache,
    m_axi_wdata,
    m_axi_wuser,
    m_axi_wstrb,
    m_axi_wlast,
    m_axi_wvalid,
    m_axi_wready,
    m_axi_bid,
    m_axi_bresp,
    m_axi_bvalid,
    m_axi_bready,
    m_axi_arid,
    m_axi_araddr,
    m_axi_arlen,
    m_axi_arsize,
    m_axi_arburst,
    m_axi_arprot,
    m_axi_arvalid,
    m_axi_arready,
    m_axi_arlock,
    m_axi_arcache,
    m_axi_rid,
    m_axi_rdata,
    m_axi_ruser,
    m_axi_rresp,
    m_axi_rlast,
    m_axi_rvalid,
    m_axi_rready,
    m_axib_awid,
    m_axib_awaddr,
    m_axib_awuser,
    m_axib_awlen,
    m_axib_awsize,
    m_axib_awburst,
    m_axib_awprot,
    m_axib_awvalid,
    m_axib_awready,
    m_axib_awlock,
    m_axib_awcache,
    m_axib_wdata,
    m_axib_wuser,
    m_axib_wstrb,
    m_axib_wlast,
    m_axib_wvalid,
    m_axib_wready,
    m_axib_bid,
    m_axib_bresp,
    m_axib_bvalid,
    m_axib_bready,
    m_axib_arid,
    m_axib_araddr,
    m_axib_aruser,
    m_axib_arlen,
    m_axib_arsize,
    m_axib_arburst,
    m_axib_arprot,
    m_axib_arvalid,
    m_axib_arready,
    m_axib_arlock,
    m_axib_arcache,
    m_axib_rid,
    m_axib_rdata,
    m_axib_ruser,
    m_axib_rresp,
    m_axib_rlast,
    m_axib_rvalid,
    m_axib_rready,
    s_axib_awid,
    s_axib_awaddr,
    s_axib_awregion,
    s_axib_awlen,
    s_axib_awsize,
    s_axib_awburst,
    s_axib_awvalid,
    s_axib_awready,
    s_axib_wdata,
    s_axib_wstrb,
    s_axib_wlast,
    s_axib_wvalid,
    s_axib_wready,
    s_axib_bid,
    s_axib_bresp,
    s_axib_bvalid,
    s_axib_bready,
    s_axib_arid,
    s_axib_araddr,
    s_axib_arregion,
    s_axib_arlen,
    s_axib_arsize,
    s_axib_arburst,
    s_axib_arvalid,
    s_axib_arready,
    s_axib_rid,
    s_axib_rresp,
    s_axib_rlast,
    s_axib_rvalid,
    s_axib_rdata,
    s_axib_wuser,
    s_axib_ruser,
    s_axib_rready,
    interrupt_out,
    interrupt_out_msi_vec0to31,
    interrupt_out_msi_vec32to63,
    interrupt_out_msix_0,
    interrupt_out_msix_1,
    interrupt_out_msix_2,
    interrupt_out_msix_3,
    s_axis_c2h_tdata_0,
    s_axis_c2h_tlast_0,
    s_axis_c2h_tuser_0,
    s_axis_c2h_tkeep_0,
    s_axis_c2h_tvalid_0,
    s_axis_c2h_tready_0,
    m_axis_h2c_tdata_0,
    m_axis_h2c_tlast_0,
    m_axis_h2c_tuser_0,
    m_axis_h2c_tkeep_0,
    m_axis_h2c_tvalid_0,
    m_axis_h2c_tready_0,
    s_axis_c2h_tdata_1,
    s_axis_c2h_tlast_1,
    s_axis_c2h_tuser_1,
    s_axis_c2h_tkeep_1,
    s_axis_c2h_tvalid_1,
    s_axis_c2h_tready_1,
    m_axis_h2c_tdata_1,
    m_axis_h2c_tlast_1,
    m_axis_h2c_tuser_1,
    m_axis_h2c_tkeep_1,
    m_axis_h2c_tvalid_1,
    m_axis_h2c_tready_1,
    s_axis_c2h_tdata_2,
    s_axis_c2h_tlast_2,
    s_axis_c2h_tuser_2,
    s_axis_c2h_tkeep_2,
    s_axis_c2h_tvalid_2,
    s_axis_c2h_tready_2,
    m_axis_h2c_tdata_2,
    m_axis_h2c_tlast_2,
    m_axis_h2c_tuser_2,
    m_axis_h2c_tkeep_2,
    m_axis_h2c_tvalid_2,
    m_axis_h2c_tready_2,
    s_axis_c2h_tdata_3,
    s_axis_c2h_tlast_3,
    s_axis_c2h_tuser_3,
    s_axis_c2h_tkeep_3,
    s_axis_c2h_tvalid_3,
    s_axis_c2h_tready_3,
    m_axis_h2c_tdata_3,
    m_axis_h2c_tlast_3,
    m_axis_h2c_tuser_3,
    m_axis_h2c_tkeep_3,
    m_axis_h2c_tvalid_3,
    m_axis_h2c_tready_3,
    m_axil_awaddr,
    m_axil_awuser,
    m_axil_awprot,
    m_axil_awvalid,
    m_axil_awready,
    m_axil_wdata,
    m_axil_wstrb,
    m_axil_wvalid,
    m_axil_wready,
    m_axil_bvalid,
    m_axil_bresp,
    m_axil_bready,
    m_axil_araddr,
    m_axil_aruser,
    m_axil_arprot,
    m_axil_arvalid,
    m_axil_arready,
    m_axil_rdata,
    m_axil_rresp,
    m_axil_rvalid,
    m_axil_rready,
    s_axil_awaddr,
    s_axil_awprot,
    s_axil_awvalid,
    s_axil_awready,
    s_axil_wdata,
    s_axil_wstrb,
    s_axil_wvalid,
    s_axil_wready,
    s_axil_bvalid,
    s_axil_bresp,
    s_axil_bready,
    s_axil_araddr,
    s_axil_arprot,
    s_axil_arvalid,
    s_axil_arready,
    s_axil_rdata,
    s_axil_rresp,
    s_axil_rvalid,
    s_axil_rready,
    c2h_dsc_byp_ready_0,
    c2h_dsc_byp_src_addr_0,
    c2h_dsc_byp_dst_addr_0,
    c2h_dsc_byp_len_0,
    c2h_dsc_byp_ctl_0,
    c2h_dsc_byp_load_0,
    c2h_dsc_byp_ready_1,
    c2h_dsc_byp_src_addr_1,
    c2h_dsc_byp_dst_addr_1,
    c2h_dsc_byp_len_1,
    c2h_dsc_byp_ctl_1,
    c2h_dsc_byp_load_1,
    c2h_dsc_byp_ready_2,
    c2h_dsc_byp_src_addr_2,
    c2h_dsc_byp_dst_addr_2,
    c2h_dsc_byp_len_2,
    c2h_dsc_byp_ctl_2,
    c2h_dsc_byp_load_2,
    c2h_dsc_byp_ready_3,
    c2h_dsc_byp_src_addr_3,
    c2h_dsc_byp_dst_addr_3,
    c2h_dsc_byp_len_3,
    c2h_dsc_byp_ctl_3,
    c2h_dsc_byp_load_3,
    h2c_dsc_byp_ready_0,
    h2c_dsc_byp_src_addr_0,
    h2c_dsc_byp_dst_addr_0,
    h2c_dsc_byp_len_0,
    h2c_dsc_byp_ctl_0,
    h2c_dsc_byp_load_0,
    h2c_dsc_byp_ready_1,
    h2c_dsc_byp_src_addr_1,
    h2c_dsc_byp_dst_addr_1,
    h2c_dsc_byp_len_1,
    h2c_dsc_byp_ctl_1,
    h2c_dsc_byp_load_1,
    h2c_dsc_byp_ready_2,
    h2c_dsc_byp_src_addr_2,
    h2c_dsc_byp_dst_addr_2,
    h2c_dsc_byp_len_2,
    h2c_dsc_byp_ctl_2,
    h2c_dsc_byp_load_2,
    h2c_dsc_byp_ready_3,
    h2c_dsc_byp_src_addr_3,
    h2c_dsc_byp_dst_addr_3,
    h2c_dsc_byp_len_3,
    h2c_dsc_byp_ctl_3,
    h2c_dsc_byp_load_3,
    c2h_sts_0,
    h2c_sts_0,
    c2h_sts_1,
    h2c_sts_1,
    c2h_sts_2,
    h2c_sts_2,
    c2h_sts_3,
    h2c_sts_3,
    pipe_debug_ctl_in_tx0,
    pipe_debug_ctl_in_tx1,
    pipe_debug_ctl_in_rx0,
    pipe_debug_ctl_in_rx1,
    pipe_debug_ltssm_rec_spd_1,
    pipe_debug_ltssm_pol_act,
    pipe_debug_ctl_vec4,
    pipe_debug_mux_ctl,
    pipe_debug_debug_out_128_0,
    pipe_debug_debug_out_ext_16_0,
    pipe_debug_debug_out_128_1,
    pipe_debug_debug_out_ext_16_1,
    pipe_debug_debug_out_128_2,
    pipe_debug_debug_out_ext_16_2,
    pipe_debug_debug_out_128_3,
    pipe_debug_debug_out_ext_16_3,
    pipe_debug_inject_tx_status,
    pipe_debug_inject_rx_status,
    cfg_vend_id,
    cfg_subsys_vend_id,
    cfg_dev_id_pf0,
    cfg_rev_id_pf0,
    cfg_subsys_id_pf0,
    cfg_dev_id_pf1,
    cfg_rev_id_pf1,
    cfg_subsys_id_pf1,
    cfg_dev_id_pf2,
    cfg_rev_id_pf2,
    cfg_subsys_id_pf2,
    cfg_dev_id_pf3,
    cfg_rev_id_pf3,
    cfg_subsys_id_pf3,
    common_commands_in,
    pipe_rx_0_sigs,
    pipe_rx_1_sigs,
    pipe_rx_2_sigs,
    pipe_rx_3_sigs,
    pipe_rx_4_sigs,
    pipe_rx_5_sigs,
    pipe_rx_6_sigs,
    pipe_rx_7_sigs,
    pipe_rx_8_sigs,
    pipe_rx_9_sigs,
    pipe_rx_10_sigs,
    pipe_rx_11_sigs,
    pipe_rx_12_sigs,
    pipe_rx_13_sigs,
    pipe_rx_14_sigs,
    pipe_rx_15_sigs,
    common_commands_out,
    pipe_tx_0_sigs,
    pipe_tx_1_sigs,
    pipe_tx_2_sigs,
    pipe_tx_3_sigs,
    pipe_tx_4_sigs,
    pipe_tx_5_sigs,
    pipe_tx_6_sigs,
    pipe_tx_7_sigs,
    pipe_tx_8_sigs,
    pipe_tx_9_sigs,
    pipe_tx_10_sigs,
    pipe_tx_11_sigs,
    pipe_tx_12_sigs,
    pipe_tx_13_sigs,
    pipe_tx_14_sigs,
    pipe_tx_15_sigs,
    cfg_mgmt_addr,
    cfg_mgmt_write,
    cfg_mgmt_write_data,
    cfg_mgmt_byte_enable,
    cfg_mgmt_read,
    cfg_mgmt_read_data,
    cfg_mgmt_read_write_done,
    cfg_mgmt_type1_cfg_reg_access,
    pipe_txprbssel,
    pipe_rxprbssel,
    pipe_txprbsforceerr,
    pipe_rxprbscntreset,
    pipe_loopback,
    pipe_rxprbserr,
    pipe_txinhibit,
    pipe_rst_fsm,
    pipe_qrst_fsm,
    pipe_rate_fsm,
    pipe_sync_fsm_tx,
    pipe_sync_fsm_rx,
    pipe_drp_fsm,
    pipe_rst_idle,
    pipe_qrst_idle,
    pipe_rate_idle,
    pipe_eyescandataerror,
    pipe_rxstatus,
    pipe_dmonitorout,
    pipe_cpll_lock,
    pipe_qpll_lock,
    pipe_rxpmaresetdone,
    pipe_rxbufstatus,
    pipe_txphaligndone,
    pipe_txphinitdone,
    pipe_txdlysresetdone,
    pipe_rxphaligndone,
    pipe_rxdlysresetdone,
    pipe_rxsyncdone,
    pipe_rxdisperr,
    pipe_rxnotintable,
    pipe_rxcommadet,
    gt_ch_drp_rdy,
    pipe_debug_0,
    pipe_debug_1,
    pipe_debug_2,
    pipe_debug_3,
    pipe_debug_4,
    pipe_debug_5,
    pipe_debug_6,
    pipe_debug_7,
    pipe_debug_8,
    pipe_debug_9,
    pipe_debug,
    gt_pcieuserratedone,
    gt_loopback,
    gt_txprbsforceerr,
    gt_txinhibit,
    gt_txprbssel,
    gt_rxprbssel,
    gt_rxprbscntreset,
    gt_dmonitorclk,
    gt_dmonfiforeset,
    gt_txelecidle,
    gt_txresetdone,
    gt_rxresetdone,
    gt_rxpmaresetdone,
    gt_txphaligndone,
    gt_txphinitdone,
    gt_txdlysresetdone,
    gt_rxphaligndone,
    gt_rxdlysresetdone,
    gt_rxsyncdone,
    gt_eyescandataerror,
    gt_rxprbserr,
    gt_dmonitorout,
    gt_rxcommadet,
    gt_phystatus,
    gt_rxvalid,
    gt_rxcdrlock,
    gt_pcierateidle,
    gt_pcieuserratestart,
    gt_gtpowergood,
    gt_cplllock,
    gt_rxoutclk,
    gt_rxrecclkout,
    gt_qpll1lock,
    gt_rxstatus,
    gt_rxbufstatus,
    gt_bufgtdiv,
    phy_txeq_ctrl,
    phy_txeq_preset,
    phy_rst_fsm,
    phy_txeq_fsm,
    phy_rxeq_fsm,
    phy_rst_idle,
    phy_rrst_n,
    phy_prst_n,
    ext_ch_gt_drpclk,
    ext_ch_gt_drpaddr,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi,
    ext_ch_gt_drprdy,
    ext_ch_gt_drpdo,
    mcap_design_switch,
    cap_req,
    cap_gnt,
    cap_rel,
    mcap_eos_in,
    startup_cfgclk,
    startup_cfgmclk,
    startup_di,
    startup_eos,
    startup_preq,
    startup_do,
    startup_dts,
    startup_fcsbo,
    startup_fcsbts,
    startup_gsr,
    startup_gts,
    startup_keyclearb,
    startup_pack,
    startup_usrcclko,
    startup_usrcclkts,
    startup_usrdoneo,
    startup_usrdonets,
    drp_rdy,
    drp_do,
    drp_clk,
    drp_en,
    drp_we,
    drp_addr,
    drp_di,
    cfg_ext_read_received,
    cfg_ext_write_received,
    cfg_ext_register_number,
    cfg_ext_function_number,
    cfg_ext_write_data,
    cfg_ext_write_byte_enable,
    cfg_ext_read_data,
    cfg_ext_read_data_valid,
    int_pclk_out_slave,
    int_pipe_rxusrclk_out,
    int_rxoutclk_out,
    int_dclk_out,
    int_userclk1_out,
    int_userclk2_out,
    int_oobclk_out,
    int_qplllock_out,
    int_qplloutclk_out,
    int_qplloutrefclk_out,
    int_pclk_sel_slave,
    pipe_pclk_in,
    pipe_rxusrclk_in,
    pipe_rxoutclk_in,
    pipe_dclk_in,
    pipe_userclk1_in,
    pipe_userclk2_in,
    pipe_oobclk_in,
    pipe_mmcm_rst_n,
    pipe_mmcm_lock_in,
    pipe_txoutclk_out,
    pipe_rxoutclk_out,
    pipe_pclk_sel_out,
    pipe_gen3_out,
    qpll_drp_crscode,
    qpll_drp_fsm,
    qpll_drp_done,
    qpll_drp_reset,
    qpll_qplllock,
    qpll_qplloutclk,
    qpll_qplloutrefclk,
    qpll_qplld,
    qpll_qpllreset,
    qpll_drp_clk,
    qpll_drp_rst_n,
    qpll_drp_ovrd,
    qpll_drp_gen3,
    qpll_drp_start,
    int_qpll1lock_out,
    int_qpll1outclk_out,
    int_qpll1outrefclk_out,
    ext_qpll1refclk,
    ext_qpll1pd,
    ext_qpll1rate,
    ext_qpll1reset,
    ext_qpll1lock_out,
    ext_qpll1outclk_out,
    ext_qpll1outrefclk_out,
    m_axis_rq_tdata_out,
    m_axis_rq_tlast_out,
    m_axis_rq_tuser_out,
    m_axis_rq_tkeep_out,
    m_axis_rq_tready_out,
    m_axis_rq_tvalid_out,
    s_axis_rc_tdata_out,
    s_axis_rc_tuser_out,
    s_axis_rc_tlast_out,
    s_axis_rc_tkeep_out,
    s_axis_rc_tvalid_out,
    s_axis_rc_tready_out,
    s_axis_cq_tdata_out,
    s_axis_cq_tuser_out,
    s_axis_cq_tlast_out,
    s_axis_cq_tkeep_out,
    s_axis_cq_tvalid_out,
    s_axis_cq_tready_out,
    m_axis_cc_tdata_out,
    m_axis_cc_tuser_out,
    m_axis_cc_tlast_out,
    m_axis_cc_tkeep_out,
    m_axis_cc_tvalid_out,
    m_axis_cc_tready_out,
    gt_qpll0lock,
    gt_gen34_eios_det,
    gt_txoutclk,
    gt_txoutclkfabric,
    gt_rxoutclkfabric,
    gt_txoutclkpcs,
    gt_rxoutclkpcs,
    gt_txpmareset,
    gt_rxpmareset,
    gt_txpcsreset,
    gt_rxpcsreset,
    gt_rxbufreset,
    gt_rxcdrreset,
    gt_rxdfelpmreset,
    gt_txprogdivresetdone,
    gt_txpmaresetdone,
    gt_txsyncdone,
    gt_rxprbslocked,
    bufgtce_us_out,
    bufgtcemask_us_out,
    bufgtdiv_us_out,
    bufgtreset_us_out,
    bufgtrstmask_us_out,
    cplllock_us_out,
    dmonitorout_us_out,
    drpdo_us_out,
    drprdy_us_out,
    eyescandataerror_us_out,
    gthtxn_us_out,
    gthtxp_us_out,
    gtpowergood_us_out,
    pcierategen3_us_out,
    pcierateidle_us_out,
    pcierateqpllpd_us_out,
    pcierateqpllreset_us_out,
    pciesynctxsyncdone_us_out,
    pcieusergen3rdy_us_out,
    pcieuserphystatusrst_us_out,
    pcieuserratestart_us_out,
    pcsrsvdout_us_out,
    phystatus_us_out,
    rxbufstatus_us_out,
    rxbyteisaligned_us_out,
    rxbyterealign_us_out,
    rxcdrlock_us_out,
    rxclkcorcnt_us_out,
    rxcommadet_us_out,
    rxctrl0_us_out,
    rxctrl1_us_out,
    rxctrl2_us_out,
    rxctrl3_us_out,
    rxdata_us_out,
    rxdlysresetdone_us_out,
    rxelecidle_us_out,
    rxoutclk_us_out,
    rxphaligndone_us_out,
    rxpmaresetdone_us_out,
    rxprbserr_us_out,
    rxprbslocked_us_out,
    rxprgdivresetdone_us_out,
    rxratedone_us_out,
    rxresetdone_us_out,
    rxstatus_us_out,
    rxsyncdone_us_out,
    rxvalid_us_out,
    txdlysresetdone_us_out,
    txoutclk_us_out,
    txphaligndone_us_out,
    txphinitdone_us_out,
    txpmaresetdone_us_out,
    txprgdivresetdone_us_out,
    txresetdone_us_out,
    txsyncout_us_out,
    txsyncdone_us_out,
    cpllpd_us_in,
    rxdfeagchold_us_in,
    rxdfecfokhold_us_in,
    rxdfelfhold_us_in,
    rxdfekhhold_us_in,
    rxdfetap2hold_us_in,
    rxdfetap3hold_us_in,
    rxdfetap4hold_us_in,
    rxdfetap5hold_us_in,
    rxdfetap6hold_us_in,
    rxdfetap7hold_us_in,
    rxdfetap8hold_us_in,
    rxdfetap9hold_us_in,
    rxdfetap10hold_us_in,
    rxdfetap11hold_us_in,
    rxdfetap12hold_us_in,
    rxdfetap13hold_us_in,
    rxdfetap14hold_us_in,
    rxdfetap15hold_us_in,
    rxdfeuthold_us_in,
    rxdfevphold_us_in,
    rxoshold_us_in,
    rxlpmgchold_us_in,
    rxlpmhfhold_us_in,
    rxlpmlfhold_us_in,
    rxlpmoshold_us_in,
    cpllreset_us_in,
    dmonfiforeset_us_in,
    dmonitorclk_us_in,
    drpclk_us_in,
    drpaddr_us_in,
    drpdi_us_in,
    drpen_us_in,
    drpwe_us_in,
    eyescanreset_us_in,
    gthrxn_us_in,
    gthrxp_us_in,
    gtrefclk0_us_in,
    gtrxreset_us_in,
    gttxreset_us_in,
    gtwiz_reset_rx_done_us_in,
    gtwiz_reset_tx_done_us_in,
    gtwiz_userclk_rx_active_us_in,
    gtwiz_userclk_tx_active_us_in,
    gtwiz_userclk_tx_reset_us_in,
    loopback_us_in,
    pcieeqrxeqadaptdone_us_in,
    pcierstidle_us_in,
    pciersttxsyncstart_us_in,
    pcieuserratedone_us_in,
    pcsrsvdin_us_in,
    rx8b10ben_us_in,
    rxbufreset_us_in,
    rxcdrhold_us_in,
    rxcommadeten_us_in,
    rxlpmen_us_in,
    rxmcommaalignen_us_in,
    rxpcommaalignen_us_in,
    rxpd_us_in,
    rxpolarity_us_in,
    rxprbscntreset_us_in,
    rxprbssel_us_in,
    rxprogdivreset_us_in,
    rxrate_us_in,
    rxratemode_us_in,
    rxslide_us_in,
    rxuserrdy_us_in,
    rxusrclk2_us_in,
    rxusrclk_us_in,
    tx8b10ben_us_in,
    txctrl0_us_in,
    txctrl1_us_in,
    txctrl2_us_in,
    txdata_us_in,
    txdeemph_us_in,
    txdetectrx_us_in,
    txdiffctrl_us_in,
    txdlybypass_us_in,
    txdlyen_us_in,
    txdlyhold_us_in,
    txdlyovrden_us_in,
    txdlysreset_us_in,
    txdlyupdown_us_in,
    txelecidle_us_in,
    txinhibit_us_in,
    txmaincursor_us_in,
    txmargin_us_in,
    txoutclksel_us_in,
    txpd_us_in,
    txphalign_us_in,
    txphalignen_us_in,
    txphdlypd_us_in,
    txphdlyreset_us_in,
    txphdlytstclk_us_in,
    txphinit_us_in,
    txphovrden_us_in,
    txpostcursor_us_in,
    txprbsforceerr_us_in,
    txprbssel_us_in,
    txprecursor_us_in,
    txprogdivreset_us_in,
    txrate_us_in,
    txswing_us_in,
    txsyncallin_us_in,
    txsyncin_us_in,
    txsyncmode_us_in,
    txuserrdy_us_in,
    txusrclk2_us_in,
    txusrclk_us_in,
    qpll0clk_us_in,
    qpll0refclk_us_in,
    qpll1clk_us_in,
    qpll1refclk_us_in,
    gtrefclk01_us_in,
    qpll1pd_us_in,
    qpll1reset_us_in,
    qpllrsvd2_us_in,
    qpllrsvd3_us_in,
    qpll1lock_us_out,
    qpll1outclk_us_out,
    qpll1outrefclk_us_out,
    cfg_bus_number_o,
    cfg_device_number_o,
    cfg_function_number_o,
    cfg_to_turnoff_o,
    m_axis_rx_tdata_o,
    m_axis_rx_tkeep_o,
    m_axis_rx_tlast_o,
    m_axis_rx_tuser_o,
    m_axis_rx_tvalid_o,
    s_axis_tx_tready_o,
    Integrated_bloc_reset_o,
    cfg_aer_interrupt_msgnum_i,
    cfg_dsn_i,
    cfg_err_aer_headerlog_i,
    cfg_err_tlp_cpl_header_i,
    cfg_interrupt_di_i,
    cfg_mgmt_di_i,
    cfg_mgmt_dwaddr_i,
    cfg_pciecap_interrupt_msgnum_i,
    cfg_pm_force_state_i,
    cfg_turnoff_ok_i,
    fc_sel_i,
    m_axis_rx_tready_i,
    pl_directed_link_auton_i,
    pl_directed_link_change_i,
    pl_directed_link_speed_i,
    pl_directed_link_width_i,
    pl_upstream_prefer_deemph_i,
    rx_np_ok_i,
    rx_np_req_i,
    s_axis_tx_tdata_i,
    s_axis_tx_tkeep_i,
    s_axis_tx_tlast_i,
    s_axis_tx_tuser_i,
    s_axis_tx_tvalid_i,
    tx_cfg_gnt_i,
    gtrefclk01_usp_in,
    gtrefclk00_usp_in,
    pcierateqpll0_usp_in,
    pcierateqpll1_usp_in,
    qpll0pd_usp_in,
    qpll0reset_usp_in,
    qpll1pd_usp_in,
    qpll1reset_usp_in,
    qpll0lock_usp_out,
    qpll0outclk_usp_out,
    qpll0outrefclk_usp_out,
    qpll1lock_usp_out,
    qpll1outclk_usp_out,
    qpll1outrefclk_usp_out,
    qpll0freqlock_usp_in,
    qpll1freqlock_usp_in,
    pcierateqpllpd_usp_out,
    pcierateqpllreset_usp_out,
    rcalenb_usp_in,
    txpisopd_usp_in,
    bufgtce_usp_out,
    bufgtcemask_usp_out,
    bufgtdiv_usp_out,
    bufgtreset_usp_out,
    bufgtrstmask_usp_out,
    cpllfreqlock_usp_in,
    cplllock_usp_out,
    cpllpd_usp_in,
    cpllreset_usp_in,
    dmonfiforeset_usp_in,
    dmonitorclk_usp_in,
    dmonitorout_usp_out,
    eyescanreset_usp_in,
    gtpowergood_usp_out,
    gtrefclk0_usp_in,
    gtrxreset_usp_in,
    gttxreset_usp_in,
    gtwiz_reset_rx_done_usp_in,
    gtwiz_reset_tx_done_usp_in,
    gtwiz_userclk_rx_active_usp_in,
    gtwiz_userclk_tx_active_usp_in,
    loopback_usp_in,
    pcieeqrxeqadaptdone_usp_in,
    pcierategen3_usp_out,
    pcierateidle_usp_out,
    pcierstidle_usp_in,
    pciersttxsyncstart_usp_in,
    pciesynctxsyncdone_usp_out,
    pcieusergen3rdy_usp_out,
    pcieuserphystatusrst_usp_out,
    pcieuserratedone_usp_in,
    pcieuserratestart_usp_out,
    phystatus_usp_out,
    resetovrd_usp_in,
    rx8b10ben_usp_in,
    rxbufreset_usp_in,
    rxbufstatus_usp_out,
    rxbyteisaligned_usp_out,
    rxbyterealign_usp_out,
    rxcdrfreqreset_usp_in,
    rxcdrhold_usp_in,
    rxcdrlock_usp_out,
    rxcdrreset_usp_in,
    rxclkcorcnt_usp_out,
    rxcommadet_usp_out,
    rxcommadeten_usp_in,
    rxctrl0_usp_out,
    rxctrl1_usp_out,
    rxctrl2_usp_out,
    rxctrl3_usp_out,
    rxdata_usp_out,
    rxdfeagchold_usp_in,
    rxdfecfokhold_usp_in,
    rxdfekhhold_usp_in,
    rxdfelfhold_usp_in,
    rxdfelpmreset_usp_in,
    rxdfetap10hold_usp_in,
    rxdfetap11hold_usp_in,
    rxdfetap12hold_usp_in,
    rxdfetap13hold_usp_in,
    rxdfetap14hold_usp_in,
    rxdfetap15hold_usp_in,
    rxdfetap2hold_usp_in,
    rxdfetap3hold_usp_in,
    rxdfetap4hold_usp_in,
    rxdfetap5hold_usp_in,
    rxdfetap6hold_usp_in,
    rxdfetap7hold_usp_in,
    rxdfetap8hold_usp_in,
    rxdfetap9hold_usp_in,
    rxdfeuthold_usp_in,
    rxdfevphold_usp_in,
    rxdlysresetdone_usp_out,
    rxelecidle_usp_out,
    rxlpmen_usp_in,
    rxlpmgchold_usp_in,
    rxlpmhfhold_usp_in,
    rxlpmlfhold_usp_in,
    rxlpmoshold_usp_in,
    rxmcommaalignen_usp_in,
    rxoshold_usp_in,
    rxoutclk_usp_out,
    rxoutclkfabric_usp_out,
    rxoutclkpcs_usp_out,
    rxpcommaalignen_usp_in,
    rxpcsreset_usp_in,
    rxpd_usp_in,
    rxphaligndone_usp_out,
    rxpmareset_usp_in,
    rxpmaresetdone_usp_out,
    rxpolarity_usp_in,
    rxprbscntreset_usp_in,
    rxprbserr_usp_out,
    rxprbslocked_usp_out,
    rxprbssel_usp_in,
    rxprogdivreset_usp_in,
    rxrate_usp_in,
    rxratedone_usp_out,
    rxrecclkout_usp_out,
    rxresetdone_usp_out,
    rxslide_usp_in,
    rxstatus_usp_out,
    rxsyncdone_usp_out,
    rxtermination_usp_in,
    rxuserrdy_usp_in,
    rxusrclk2_usp_in,
    rxusrclk_usp_in,
    rxvalid_usp_out,
    tx8b10ben_usp_in,
    txctrl0_usp_in,
    txctrl1_usp_in,
    txctrl2_usp_in,
    txdata_usp_in,
    txdeemph_usp_in,
    txdetectrx_usp_in,
    txdiffctrl_usp_in,
    txdlybypass_usp_in,
    txdlyen_usp_in,
    txdlyhold_usp_in,
    txdlyovrden_usp_in,
    txdlysreset_usp_in,
    txdlysresetdone_usp_out,
    txdlyupdown_usp_in,
    txelecidle_usp_in,
    txmaincursor_usp_in,
    txmargin_usp_in,
    txoutclk_usp_out,
    txoutclkfabric_usp_out,
    txoutclkpcs_usp_out,
    txoutclksel_usp_in,
    txpcsreset_usp_in,
    txpd_usp_in,
    txphalign_usp_in,
    txphaligndone_usp_out,
    txphalignen_usp_in,
    txphdlypd_usp_in,
    txphdlyreset_usp_in,
    txphdlytstclk_usp_in,
    txphinit_usp_in,
    txphinitdone_usp_out,
    txphovrden_usp_in,
    rxratemode_usp_in,
    txpmareset_usp_in,
    txpmaresetdone_usp_out,
    txpostcursor_usp_in,
    txprbsforceerr_usp_in,
    txprbssel_usp_in,
    txprecursor_usp_in,
    txprgdivresetdone_usp_out,
    txprogdivreset_usp_in,
    txpdelecidlemode_usp_in,
    txrate_usp_in,
    txresetdone_usp_out,
    txswing_usp_in,
    txsyncallin_usp_in,
    txsyncdone_usp_out,
    txsyncin_usp_in,
    txsyncmode_usp_in,
    txsyncout_usp_out,
    txuserrdy_usp_in,
    txusrclk2_usp_in,
    txusrclk_usp_in,
    drpclk_usp_in,
    drpaddr_usp_in,
    drpen_usp_in,
    drprst_usp_in,
    drpwe_usp_in,
    drpdi_usp_in,
    drprdy_usp_out,
    drpdo_usp_out,
    ext_phy_clk_pclk2_gt,
    ext_phy_clk_int_clock,
    ext_phy_clk_pclk,
    ext_phy_clk_phy_pclk2,
    ext_phy_clk_phy_coreclk,
    ext_phy_clk_phy_userclk,
    ext_phy_clk_phy_mcapclk,
    ext_phy_clk_bufg_gt_ce,
    ext_phy_clk_bufg_gt_reset,
    ext_phy_clk_rst_idle,
    ext_phy_clk_txoutclk,
    ext_phy_clk_bufgtcemask,
    ext_phy_clk_gt_bufgtrstmask,
    ext_phy_clk_bufgtdiv,
    int_usp_qpll0lock_out,
    int_usp_qpll0outrefclk_out,
    int_usp_qpll0outclk_out,
    int_usp_qpll1lock_out,
    int_usp_qpll1outrefclk_out,
    int_usp_qpll1outclk_out,
    ext_usp_qpllxrefclk,
    ext_usp_qpllxrate,
    ext_usp_qpllxrcalenb,
    ext_usp_qpll0pd,
    ext_usp_qpll0reset,
    ext_usp_qpll0lock_out,
    ext_usp_qpll0outclk_out,
    ext_usp_qpll0outrefclk_out,
    ext_usp_qpll1pd,
    ext_usp_qpll1reset,
    ext_usp_qpll1lock_out,
    ext_usp_qpll1outclk_out,
    ext_usp_qpll1outrefclk_out,
    cfg_negotiated_width_o,
    cfg_current_speed_o,
    cfg_ltssm_state_o,
    cfg_err_cor_o,
    cfg_err_fatal_o,
    cfg_err_nonfatal_o,
    cfg_local_error_o,
    cfg_local_error_valid_o,
    pipe_tx0_rcvr_det,
    pipe_clk,
    sys_clk_bufg,
    pipe_tx0_powerdown,
    cfg_function_status,
    cfg_max_read_req,
    cfg_max_payload,
    cfg_flr_done,
    cfg_flr_in_process,
    cfg_vf_flr_in_process,
    cfg_vf_flr_func_num,
    cfg_vf_flr_done,
    cfg_interrupt_msi_enable,
    cfg_interrupt_msix_enable,
    cfg_interrupt_msix_mask,
    cfg_interrupt_msix_data,
    cfg_interrupt_msix_address,
    cfg_interrupt_msix_int,
    cfg_interrupt_msi_sent,
    cfg_interrupt_msi_fail,
    cfg_interrupt_msix_sent,
    cfg_interrupt_msix_fail,
    phy_rdy_out_sd,
    cfg_err_cor_in_sd,
    cfg_link_training_enable_sd,
    cfg_config_space_enable_sd,
    cfg_ltssm_state_sd,
    user_lnk_up_sd,
    s_axis_rq_tdata_sd,
    s_axis_rq_tlast_sd,
    s_axis_rq_tuser_sd,
    s_axis_rq_tkeep_sd,
    s_axis_rq_tvalid_sd,
    s_axis_rq_tready_sd,
    m_axis_rc_tdata_sd,
    m_axis_rc_tuser_sd,
    m_axis_rc_tlast_sd,
    m_axis_rc_tkeep_sd,
    m_axis_rc_tvalid_sd,
    m_axis_rc_tready_sd,
    m_axis_cq_tdata_sd,
    m_axis_cq_tuser_sd,
    m_axis_cq_tlast_sd,
    m_axis_cq_tkeep_sd,
    m_axis_cq_tvalid_sd,
    m_axis_cq_tready_sd,
    s_axis_cc_tdata_sd,
    s_axis_cc_tuser_sd,
    s_axis_cc_tlast_sd,
    s_axis_cc_tkeep_sd,
    s_axis_cc_tvalid_sd,
    s_axis_cc_tready_sd,
    rbar_bar_size_sd,
    rbar_function_number_sd,
    rbar_write_enable_bar0_sd,
    rbar_write_enable_bar1_sd,
    rbar_write_enable_bar2_sd,
    rbar_write_enable_bar3_sd,
    rbar_write_enable_bar4_sd,
    rbar_write_enable_bar5_sd,
    user_clk_sd,
    user_reset_sd,
    pcie_cq_np_req_sd,
    pcie_cq_np_req_count_sd,
    pcie_tfc_nph_av_sd,
    pcie_tfc_npd_av_sd,
    pcie_rq_seq_num_vld0_sd,
    pcie_rq_seq_num0_sd,
    pcie_rq_seq_num_vld1_sd,
    pcie_rq_seq_num1_sd,
    cfg_fc_nph_sd,
    cfg_fc_sel_sd,
    cfg_phy_link_down_sd,
    cfg_phy_link_status_sd,
    cfg_negotiated_width_sd,
    cfg_current_speed_sd,
    cfg_pl_status_change_sd,
    cfg_hot_reset_out_sd,
    cfg_ds_port_number_sd,
    cfg_ds_bus_number_sd,
    cfg_ds_device_number_sd,
    cfg_ds_function_number_sd,
    cfg_dsn_sd,
    cfg_function_status_sd,
    cfg_max_read_req_sd,
    cfg_max_payload_sd,
    cfg_err_uncor_in_sd,
    cfg_flr_done_sd,
    cfg_flr_in_process_sd,
    cfg_vf_flr_in_process_sd,
    usr_flr_fnc,
    usr_flr_set,
    usr_flr_clr,
    usr_flr_done_fnc,
    usr_flr_done_vld,
    cfg_err_cor_out_sd,
    cfg_err_nonfatal_out_sd,
    cfg_err_fatal_out_sd,
    cfg_local_error_out_sd,
    cfg_msg_received_sd,
    cfg_msg_received_data_sd,
    cfg_msg_received_type_sd,
    cfg_msg_transmit_sd,
    cfg_msg_transmit_type_sd,
    cfg_msg_transmit_data_sd,
    cfg_msg_transmit_done_sd,
    cfg_mgmt_addr_sd,
    cfg_mgmt_write_sd,
    cfg_mgmt_write_data_sd,
    cfg_mgmt_byte_enable_sd,
    cfg_mgmt_read_sd,
    cfg_mgmt_type1_cfg_reg_access_sd,
    cfg_mgmt_read_data_sd,
    cfg_mgmt_read_write_done_sd,
    cfg_mgmt_function_number_sd,
    cfg_interrupt_int_sd,
    cfg_interrupt_sent_sd,
    cfg_interrupt_pending_sd,
    cfg_interrupt_msi_enable_sd,
    cfg_interrupt_msi_mask_update_sd,
    cfg_interrupt_msi_data_sd,
    cfg_interrupt_msi_int_sd,
    cfg_interrupt_msi_pending_status_sd,
    cfg_interrupt_msi_pending_status_data_enable_sd,
    cfg_interrupt_msi_pending_status_function_num_sd,
    cfg_interrupt_msi_attr_sd,
    cfg_interrupt_msi_tph_present_sd,
    cfg_interrupt_msi_tph_type_sd,
    cfg_interrupt_msi_tph_st_tag_sd,
    cfg_interrupt_msi_function_number_sd,
    cfg_interrupt_msi_sent_sd,
    cfg_interrupt_msi_fail_sd,
    cfg_interrupt_msix_enable_sd,
    cfg_interrupt_msix_mask_sd,
    cfg_interrupt_msix_data_sd,
    cfg_interrupt_msix_address_sd,
    cfg_interrupt_msix_int_sd,
    cfg_interrupt_msix_vf_enable_sd,
    cfg_interrupt_msix_vf_mask_sd,
    cfg_interrupt_msix_vec_pending_sd,
    cfg_interrupt_msix_vec_pending_status_sd,
    rd_interrupt,
    wr_interrupt,
    ats_pri_en,
    cfg_fc_vc_sel,
    core_clk,
    cxs0_active_req_tx,
    cxs0_active_ack_tx,
    cxs0_deact_hint_tx,
    cxs0_valid_tx,
    cxs0_crdgnt_tx,
    cxs0_crdrtn_tx,
    cxs0_cntl_tx,
    cxs0_data_tx,
    cxs0_valid_chk_tx,
    cxs0_crdgnt_chk_tx,
    cxs0_crdrtn_chk_tx,
    cxs0_cntl_chk_tx,
    cxs0_data_chk_tx,
    cxs0_active_req_rx,
    cxs0_active_ack_rx,
    cxs0_deact_hint_rx,
    cxs0_valid_rx,
    cxs0_crdgnt_rx,
    cxs0_crdrtn_rx,
    cxs0_cntl_rx,
    cxs0_data_rx,
    cxs0_valid_chk_rx,
    cxs0_crdgnt_chk_rx,
    cxs0_crdrtn_chk_rx,
    cxs0_cntl_chk_rx,
    cxs0_data_chk_rx,
    pcie4_cxs0_active_req_tx_sd,
    pcie4_cxs0_active_ack_tx_sd,
    pcie4_cxs0_deact_hint_tx_sd,
    pcie4_cxs0_valid_tx_sd,
    pcie4_cxs0_crdgnt_tx_sd,
    pcie4_cxs0_crdrtn_tx_sd,
    pcie4_cxs0_cntl_tx_sd,
    pcie4_cxs0_data_tx_sd,
    pcie4_cxs0_valid_chk_tx_sd,
    pcie4_cxs0_crdgnt_chk_tx_sd,
    pcie4_cxs0_crdrtn_chk_tx_sd,
    pcie4_cxs0_cntl_chk_tx_sd,
    pcie4_cxs0_data_chk_tx_sd,
    pcie4_cxs0_active_req_rx_sd,
    pcie4_cxs0_active_ack_rx_sd,
    pcie4_cxs0_deact_hint_rx_sd,
    pcie4_cxs0_valid_rx_sd,
    pcie4_cxs0_crdgnt_rx_sd,
    pcie4_cxs0_crdrtn_rx_sd,
    pcie4_cxs0_cntl_rx_sd,
    pcie4_cxs0_data_rx_sd,
    pcie4_cxs0_valid_chk_rx_sd,
    pcie4_cxs0_crdgnt_chk_rx_sd,
    pcie4_cxs0_crdrtn_chk_rx_sd,
    pcie4_cxs0_cntl_chk_rx_sd,
    pcie4_cxs0_data_chk_rx_sd,
    ccix_optimized_tlp_tx_and_rx_enable_in,
    sc0_ats_s_axis_rq_tvalid,
    sc0_ats_s_axis_rq_tready,
    sc0_ats_s_axis_rq_tdata,
    sc0_ats_s_axis_rq_tkeep,
    sc0_ats_s_axis_rq_tlast,
    sc0_ats_s_axis_rq_tuser,
    sc0_ats_m_axis_rc_tvalid,
    sc0_ats_m_axis_rc_tready,
    sc0_ats_m_axis_rc_tdata,
    sc0_ats_m_axis_rc_tkeep,
    sc0_ats_m_axis_rc_tlast,
    sc0_ats_m_axis_rc_tuser,
    sc0_ats_s_axis_cc_tvalid,
    sc0_ats_s_axis_cc_tready,
    sc0_ats_s_axis_cc_tdata,
    sc0_ats_s_axis_cc_tkeep,
    sc0_ats_s_axis_cc_tlast,
    sc0_ats_s_axis_cc_tuser,
    sc0_ats_m_axis_cq_tvalid,
    sc0_ats_m_axis_cq_tready,
    sc0_ats_m_axis_cq_tdata,
    sc0_ats_m_axis_cq_tkeep,
    sc0_ats_m_axis_cq_tlast,
    sc0_ats_m_axis_cq_tuser,
    sc1_ats_s_axis_rq_tvalid,
    sc1_ats_s_axis_rq_tready,
    sc1_ats_s_axis_rq_tdata,
    sc1_ats_s_axis_rq_tkeep,
    sc1_ats_s_axis_rq_tlast,
    sc1_ats_s_axis_rq_tuser,
    sc1_ats_m_axis_rc_tvalid,
    sc1_ats_m_axis_rc_tready,
    sc1_ats_m_axis_rc_tdata,
    sc1_ats_m_axis_rc_tkeep,
    sc1_ats_m_axis_rc_tlast,
    sc1_ats_m_axis_rc_tuser,
    sc1_ats_s_axis_cc_tvalid,
    sc1_ats_s_axis_cc_tready,
    sc1_ats_s_axis_cc_tdata,
    sc1_ats_s_axis_cc_tkeep,
    sc1_ats_s_axis_cc_tlast,
    sc1_ats_s_axis_cc_tuser,
    sc1_ats_m_axis_cq_tvalid,
    sc1_ats_m_axis_cq_tready,
    sc1_ats_m_axis_cq_tdata,
    sc1_ats_m_axis_cq_tkeep,
    sc1_ats_m_axis_cq_tlast,
    sc1_ats_m_axis_cq_tuser,
    s_aclk,
    s_aresetn,
    s_axi_araddr,
    s_axi_arburst,
    s_axi_arcache,
    s_axi_arid,
    s_axi_arlen,
    s_axi_arlock,
    s_axi_arprot,
    s_axi_arqos,
    s_axi_arready,
    s_axi_arsize,
    s_axi_aruser,
    s_axi_arvalid,
    s_axi_awaddr,
    s_axi_awburst,
    s_axi_awcache,
    s_axi_awid,
    s_axi_awlen,
    s_axi_awlock,
    s_axi_awprot,
    s_axi_awqos,
    s_axi_awready,
    s_axi_awsize,
    s_axi_awuser,
    s_axi_awvalid,
    s_axi_bid,
    s_axi_bready,
    s_axi_bresp,
    s_axi_bvalid,
    s_axi_rdata,
    s_axi_rid,
    s_axi_rlast,
    s_axi_rready,
    s_axi_rresp,
    s_axi_rvalid,
    s_axi_wdata,
    s_axi_wlast,
    s_axi_wready,
    s_axi_wstrb,
    s_axi_wvalid,
    atspri_m_axis_cq_tdata,
    atspri_m_axis_cq_tuser,
    atspri_m_axis_cq_tlast,
    atspri_m_axis_cq_tkeep,
    atspri_m_axis_cq_tvalid,
    atspri_m_axis_cq_tready,
    atspri_s_axis_rq_tdata,
    atspri_s_axis_rq_tuser,
    atspri_s_axis_rq_tlast,
    atspri_s_axis_rq_tkeep,
    atspri_s_axis_rq_tvalid,
    atspri_s_axis_rq_tready,
    cfg_status_ats_stu,
    cfg_status_ats_en,
    cfg_status_pr_en,
    cfg_status_pr_rst,
    cfg_status_pr_uprgi,
    cfg_status_set_uprgi,
    cfg_status_pr_rf,
    cfg_status_set_rf,
    cfg_status_set_s,
    cfg_status_clr_s,
    cfg_status_ost_pr_alloc);
  (* keep = "true" *) input sys_clk;
  (* keep = "true" *) output sys_clk_ce_out;
  (* keep = "true" *) input sys_clk_gt;
  (* keep = "true" *) input sys_rst_n;
  input dma_bridge_resetn;
  (* keep = "true" *) output user_lnk_up;
  output [5:0]cfg_ltssm_state;
  input config_space_enable;
  (* keep = "true" *) output [1:0]pci_exp_txp;
  (* keep = "true" *) output [1:0]pci_exp_txn;
  (* keep = "true" *) input [1:0]pci_exp_rxp;
  (* keep = "true" *) input [1:0]pci_exp_rxn;
  input free_run_clock;
  output gt_drp_clk;
  (* keep = "true" *) output axi_aclk;
  (* keep = "true" *) output axi_aresetn;
  (* keep = "true" *) input axi_ctl_aclk;
  (* keep = "true" *) output axi_ctl_aresetn;
  (* keep = "true" *) input [0:0]usr_irq_req;
  (* keep = "true" *) output [0:0]usr_irq_ack;
  (* keep = "true" *) input [1:0]usr_irq_function_number;
  (* keep = "true" *) output msi_enable;
  (* keep = "true" *) output msix_enable;
  (* keep = "true" *) output [2:0]msi_vector_width;
  (* keep = "true" *) output [3:0]m_axi_awid;
  (* keep = "true" *) output [63:0]m_axi_awaddr;
  (* keep = "true" *) output [7:0]m_axi_awlen;
  (* keep = "true" *) output [2:0]m_axi_awsize;
  (* keep = "true" *) output [1:0]m_axi_awburst;
  (* keep = "true" *) output [2:0]m_axi_awprot;
  (* keep = "true" *) output m_axi_awvalid;
  (* keep = "true" *) input m_axi_awready;
  (* keep = "true" *) output m_axi_awlock;
  (* keep = "true" *) output [3:0]m_axi_awcache;
  (* keep = "true" *) output [63:0]m_axi_wdata;
  (* keep = "true" *) output [7:0]m_axi_wuser;
  (* keep = "true" *) output [7:0]m_axi_wstrb;
  (* keep = "true" *) output m_axi_wlast;
  (* keep = "true" *) output m_axi_wvalid;
  (* keep = "true" *) input m_axi_wready;
  (* keep = "true" *) input [3:0]m_axi_bid;
  (* keep = "true" *) input [1:0]m_axi_bresp;
  (* keep = "true" *) input m_axi_bvalid;
  (* keep = "true" *) output m_axi_bready;
  (* keep = "true" *) output [3:0]m_axi_arid;
  (* keep = "true" *) output [63:0]m_axi_araddr;
  (* keep = "true" *) output [7:0]m_axi_arlen;
  (* keep = "true" *) output [2:0]m_axi_arsize;
  (* keep = "true" *) output [1:0]m_axi_arburst;
  (* keep = "true" *) output [2:0]m_axi_arprot;
  (* keep = "true" *) output m_axi_arvalid;
  (* keep = "true" *) input m_axi_arready;
  (* keep = "true" *) output m_axi_arlock;
  (* keep = "true" *) output [3:0]m_axi_arcache;
  (* keep = "true" *) input [3:0]m_axi_rid;
  (* keep = "true" *) input [63:0]m_axi_rdata;
  (* keep = "true" *) input [7:0]m_axi_ruser;
  (* keep = "true" *) input [1:0]m_axi_rresp;
  (* keep = "true" *) input m_axi_rlast;
  (* keep = "true" *) input m_axi_rvalid;
  (* keep = "true" *) output m_axi_rready;
  (* keep = "true" *) output [3:0]m_axib_awid;
  (* keep = "true" *) output [63:0]m_axib_awaddr;
  (* keep = "true" *) output [7:0]m_axib_awuser;
  (* keep = "true" *) output [7:0]m_axib_awlen;
  (* keep = "true" *) output [2:0]m_axib_awsize;
  (* keep = "true" *) output [1:0]m_axib_awburst;
  (* keep = "true" *) output [2:0]m_axib_awprot;
  (* keep = "true" *) output m_axib_awvalid;
  (* keep = "true" *) input m_axib_awready;
  output m_axib_awlock;
  (* keep = "true" *) output [3:0]m_axib_awcache;
  (* keep = "true" *) output [63:0]m_axib_wdata;
  (* keep = "true" *) output [7:0]m_axib_wuser;
  (* keep = "true" *) output [7:0]m_axib_wstrb;
  (* keep = "true" *) output m_axib_wlast;
  (* keep = "true" *) output m_axib_wvalid;
  (* keep = "true" *) input m_axib_wready;
  (* keep = "true" *) input [3:0]m_axib_bid;
  (* keep = "true" *) input [1:0]m_axib_bresp;
  (* keep = "true" *) input m_axib_bvalid;
  (* keep = "true" *) output m_axib_bready;
  (* keep = "true" *) output [3:0]m_axib_arid;
  (* keep = "true" *) output [63:0]m_axib_araddr;
  (* keep = "true" *) output [7:0]m_axib_aruser;
  (* keep = "true" *) output [7:0]m_axib_arlen;
  (* keep = "true" *) output [2:0]m_axib_arsize;
  (* keep = "true" *) output [1:0]m_axib_arburst;
  (* keep = "true" *) output [2:0]m_axib_arprot;
  (* keep = "true" *) output m_axib_arvalid;
  (* keep = "true" *) input m_axib_arready;
  output m_axib_arlock;
  (* keep = "true" *) output [3:0]m_axib_arcache;
  (* keep = "true" *) input [3:0]m_axib_rid;
  (* keep = "true" *) input [63:0]m_axib_rdata;
  (* keep = "true" *) input [7:0]m_axib_ruser;
  (* keep = "true" *) input [1:0]m_axib_rresp;
  (* keep = "true" *) input m_axib_rlast;
  (* keep = "true" *) input m_axib_rvalid;
  (* keep = "true" *) output m_axib_rready;
  input [3:0]s_axib_awid;
  input [63:0]s_axib_awaddr;
  input [3:0]s_axib_awregion;
  input [7:0]s_axib_awlen;
  input [2:0]s_axib_awsize;
  input [1:0]s_axib_awburst;
  input s_axib_awvalid;
  output s_axib_awready;
  input [63:0]s_axib_wdata;
  input [7:0]s_axib_wstrb;
  input s_axib_wlast;
  input s_axib_wvalid;
  output s_axib_wready;
  output [3:0]s_axib_bid;
  output [1:0]s_axib_bresp;
  output s_axib_bvalid;
  input s_axib_bready;
  input [3:0]s_axib_arid;
  input [63:0]s_axib_araddr;
  input [3:0]s_axib_arregion;
  input [7:0]s_axib_arlen;
  input [2:0]s_axib_arsize;
  input [1:0]s_axib_arburst;
  input s_axib_arvalid;
  output s_axib_arready;
  output [3:0]s_axib_rid;
  output [1:0]s_axib_rresp;
  output s_axib_rlast;
  output s_axib_rvalid;
  output [63:0]s_axib_rdata;
  input [7:0]s_axib_wuser;
  output [7:0]s_axib_ruser;
  input s_axib_rready;
  output interrupt_out;
  output interrupt_out_msi_vec0to31;
  output interrupt_out_msi_vec32to63;
  output interrupt_out_msix_0;
  output interrupt_out_msix_1;
  output interrupt_out_msix_2;
  output interrupt_out_msix_3;
  input [63:0]s_axis_c2h_tdata_0;
  input s_axis_c2h_tlast_0;
  input [7:0]s_axis_c2h_tuser_0;
  input [7:0]s_axis_c2h_tkeep_0;
  input s_axis_c2h_tvalid_0;
  output s_axis_c2h_tready_0;
  output [63:0]m_axis_h2c_tdata_0;
  output m_axis_h2c_tlast_0;
  output [7:0]m_axis_h2c_tuser_0;
  output [7:0]m_axis_h2c_tkeep_0;
  output m_axis_h2c_tvalid_0;
  input m_axis_h2c_tready_0;
  input [63:0]s_axis_c2h_tdata_1;
  input s_axis_c2h_tlast_1;
  input [7:0]s_axis_c2h_tuser_1;
  input [7:0]s_axis_c2h_tkeep_1;
  input s_axis_c2h_tvalid_1;
  output s_axis_c2h_tready_1;
  output [63:0]m_axis_h2c_tdata_1;
  output m_axis_h2c_tlast_1;
  output [7:0]m_axis_h2c_tuser_1;
  output [7:0]m_axis_h2c_tkeep_1;
  output m_axis_h2c_tvalid_1;
  input m_axis_h2c_tready_1;
  input [63:0]s_axis_c2h_tdata_2;
  input s_axis_c2h_tlast_2;
  input [7:0]s_axis_c2h_tuser_2;
  input [7:0]s_axis_c2h_tkeep_2;
  input s_axis_c2h_tvalid_2;
  output s_axis_c2h_tready_2;
  output [63:0]m_axis_h2c_tdata_2;
  output m_axis_h2c_tlast_2;
  output [7:0]m_axis_h2c_tuser_2;
  output [7:0]m_axis_h2c_tkeep_2;
  output m_axis_h2c_tvalid_2;
  input m_axis_h2c_tready_2;
  input [63:0]s_axis_c2h_tdata_3;
  input s_axis_c2h_tlast_3;
  input [7:0]s_axis_c2h_tuser_3;
  input [7:0]s_axis_c2h_tkeep_3;
  input s_axis_c2h_tvalid_3;
  output s_axis_c2h_tready_3;
  output [63:0]m_axis_h2c_tdata_3;
  output m_axis_h2c_tlast_3;
  output [7:0]m_axis_h2c_tuser_3;
  output [7:0]m_axis_h2c_tkeep_3;
  output m_axis_h2c_tvalid_3;
  input m_axis_h2c_tready_3;
  (* keep = "true" *) output [31:0]m_axil_awaddr;
  (* keep = "true" *) output [10:0]m_axil_awuser;
  output [2:0]m_axil_awprot;
  (* keep = "true" *) output m_axil_awvalid;
  (* keep = "true" *) input m_axil_awready;
  (* keep = "true" *) output [31:0]m_axil_wdata;
  (* keep = "true" *) output [3:0]m_axil_wstrb;
  (* keep = "true" *) output m_axil_wvalid;
  (* keep = "true" *) input m_axil_wready;
  (* keep = "true" *) input m_axil_bvalid;
  (* keep = "true" *) input [1:0]m_axil_bresp;
  (* keep = "true" *) output m_axil_bready;
  (* keep = "true" *) output [31:0]m_axil_araddr;
  (* keep = "true" *) output [10:0]m_axil_aruser;
  output [2:0]m_axil_arprot;
  (* keep = "true" *) output m_axil_arvalid;
  (* keep = "true" *) input m_axil_arready;
  (* keep = "true" *) input [31:0]m_axil_rdata;
  (* keep = "true" *) input [1:0]m_axil_rresp;
  (* keep = "true" *) input m_axil_rvalid;
  (* keep = "true" *) output m_axil_rready;
  (* keep = "true" *) input [31:0]s_axil_awaddr;
  input [2:0]s_axil_awprot;
  (* keep = "true" *) input s_axil_awvalid;
  (* keep = "true" *) output s_axil_awready;
  (* keep = "true" *) input [31:0]s_axil_wdata;
  (* keep = "true" *) input [3:0]s_axil_wstrb;
  (* keep = "true" *) input s_axil_wvalid;
  (* keep = "true" *) output s_axil_wready;
  (* keep = "true" *) output s_axil_bvalid;
  (* keep = "true" *) output [1:0]s_axil_bresp;
  (* keep = "true" *) input s_axil_bready;
  (* keep = "true" *) input [31:0]s_axil_araddr;
  input [2:0]s_axil_arprot;
  (* keep = "true" *) input s_axil_arvalid;
  (* keep = "true" *) output s_axil_arready;
  (* keep = "true" *) output [31:0]s_axil_rdata;
  (* keep = "true" *) output [1:0]s_axil_rresp;
  (* keep = "true" *) output s_axil_rvalid;
  (* keep = "true" *) input s_axil_rready;
  output c2h_dsc_byp_ready_0;
  input [63:0]c2h_dsc_byp_src_addr_0;
  input [63:0]c2h_dsc_byp_dst_addr_0;
  input [27:0]c2h_dsc_byp_len_0;
  input [15:0]c2h_dsc_byp_ctl_0;
  input c2h_dsc_byp_load_0;
  output c2h_dsc_byp_ready_1;
  input [63:0]c2h_dsc_byp_src_addr_1;
  input [63:0]c2h_dsc_byp_dst_addr_1;
  input [27:0]c2h_dsc_byp_len_1;
  input [15:0]c2h_dsc_byp_ctl_1;
  input c2h_dsc_byp_load_1;
  output c2h_dsc_byp_ready_2;
  input [63:0]c2h_dsc_byp_src_addr_2;
  input [63:0]c2h_dsc_byp_dst_addr_2;
  input [27:0]c2h_dsc_byp_len_2;
  input [15:0]c2h_dsc_byp_ctl_2;
  input c2h_dsc_byp_load_2;
  output c2h_dsc_byp_ready_3;
  input [63:0]c2h_dsc_byp_src_addr_3;
  input [63:0]c2h_dsc_byp_dst_addr_3;
  input [27:0]c2h_dsc_byp_len_3;
  input [15:0]c2h_dsc_byp_ctl_3;
  input c2h_dsc_byp_load_3;
  output h2c_dsc_byp_ready_0;
  input [63:0]h2c_dsc_byp_src_addr_0;
  input [63:0]h2c_dsc_byp_dst_addr_0;
  input [27:0]h2c_dsc_byp_len_0;
  input [15:0]h2c_dsc_byp_ctl_0;
  input h2c_dsc_byp_load_0;
  output h2c_dsc_byp_ready_1;
  input [63:0]h2c_dsc_byp_src_addr_1;
  input [63:0]h2c_dsc_byp_dst_addr_1;
  input [27:0]h2c_dsc_byp_len_1;
  input [15:0]h2c_dsc_byp_ctl_1;
  input h2c_dsc_byp_load_1;
  output h2c_dsc_byp_ready_2;
  input [63:0]h2c_dsc_byp_src_addr_2;
  input [63:0]h2c_dsc_byp_dst_addr_2;
  input [27:0]h2c_dsc_byp_len_2;
  input [15:0]h2c_dsc_byp_ctl_2;
  input h2c_dsc_byp_load_2;
  output h2c_dsc_byp_ready_3;
  input [63:0]h2c_dsc_byp_src_addr_3;
  input [63:0]h2c_dsc_byp_dst_addr_3;
  input [27:0]h2c_dsc_byp_len_3;
  input [15:0]h2c_dsc_byp_ctl_3;
  input h2c_dsc_byp_load_3;
  output [7:0]c2h_sts_0;
  output [7:0]h2c_sts_0;
  output [7:0]c2h_sts_1;
  output [7:0]h2c_sts_1;
  output [7:0]c2h_sts_2;
  output [7:0]h2c_sts_2;
  output [7:0]c2h_sts_3;
  output [7:0]h2c_sts_3;
  input [31:0]pipe_debug_ctl_in_tx0;
  input [31:0]pipe_debug_ctl_in_tx1;
  input [31:0]pipe_debug_ctl_in_rx0;
  input [31:0]pipe_debug_ctl_in_rx1;
  input pipe_debug_ltssm_rec_spd_1;
  input pipe_debug_ltssm_pol_act;
  input [3:0]pipe_debug_ctl_vec4;
  input [31:0]pipe_debug_mux_ctl;
  output [127:0]pipe_debug_debug_out_128_0;
  output [15:0]pipe_debug_debug_out_ext_16_0;
  output [127:0]pipe_debug_debug_out_128_1;
  output [15:0]pipe_debug_debug_out_ext_16_1;
  output [127:0]pipe_debug_debug_out_128_2;
  output [15:0]pipe_debug_debug_out_ext_16_2;
  output [127:0]pipe_debug_debug_out_128_3;
  output [15:0]pipe_debug_debug_out_ext_16_3;
  output [7:0]pipe_debug_inject_tx_status;
  output [7:0]pipe_debug_inject_rx_status;
  input [15:0]cfg_vend_id;
  input [15:0]cfg_subsys_vend_id;
  input [15:0]cfg_dev_id_pf0;
  input [7:0]cfg_rev_id_pf0;
  input [15:0]cfg_subsys_id_pf0;
  input [15:0]cfg_dev_id_pf1;
  input [7:0]cfg_rev_id_pf1;
  input [15:0]cfg_subsys_id_pf1;
  input [15:0]cfg_dev_id_pf2;
  input [7:0]cfg_rev_id_pf2;
  input [15:0]cfg_subsys_id_pf2;
  input [15:0]cfg_dev_id_pf3;
  input [7:0]cfg_rev_id_pf3;
  input [15:0]cfg_subsys_id_pf3;
  input [25:0]common_commands_in;
  input [83:0]pipe_rx_0_sigs;
  input [83:0]pipe_rx_1_sigs;
  input [83:0]pipe_rx_2_sigs;
  input [83:0]pipe_rx_3_sigs;
  input [83:0]pipe_rx_4_sigs;
  input [83:0]pipe_rx_5_sigs;
  input [83:0]pipe_rx_6_sigs;
  input [83:0]pipe_rx_7_sigs;
  input [83:0]pipe_rx_8_sigs;
  input [83:0]pipe_rx_9_sigs;
  input [83:0]pipe_rx_10_sigs;
  input [83:0]pipe_rx_11_sigs;
  input [83:0]pipe_rx_12_sigs;
  input [83:0]pipe_rx_13_sigs;
  input [83:0]pipe_rx_14_sigs;
  input [83:0]pipe_rx_15_sigs;
  output [25:0]common_commands_out;
  output [83:0]pipe_tx_0_sigs;
  output [83:0]pipe_tx_1_sigs;
  output [83:0]pipe_tx_2_sigs;
  output [83:0]pipe_tx_3_sigs;
  output [83:0]pipe_tx_4_sigs;
  output [83:0]pipe_tx_5_sigs;
  output [83:0]pipe_tx_6_sigs;
  output [83:0]pipe_tx_7_sigs;
  output [83:0]pipe_tx_8_sigs;
  output [83:0]pipe_tx_9_sigs;
  output [83:0]pipe_tx_10_sigs;
  output [83:0]pipe_tx_11_sigs;
  output [83:0]pipe_tx_12_sigs;
  output [83:0]pipe_tx_13_sigs;
  output [83:0]pipe_tx_14_sigs;
  output [83:0]pipe_tx_15_sigs;
  (* keep = "true" *) input [18:0]cfg_mgmt_addr;
  (* keep = "true" *) input cfg_mgmt_write;
  (* keep = "true" *) input [31:0]cfg_mgmt_write_data;
  (* keep = "true" *) input [3:0]cfg_mgmt_byte_enable;
  (* keep = "true" *) input cfg_mgmt_read;
  (* keep = "true" *) output [31:0]cfg_mgmt_read_data;
  (* keep = "true" *) output cfg_mgmt_read_write_done;
  (* keep = "true" *) input cfg_mgmt_type1_cfg_reg_access;
  input [2:0]pipe_txprbssel;
  input [2:0]pipe_rxprbssel;
  input pipe_txprbsforceerr;
  input pipe_rxprbscntreset;
  input [2:0]pipe_loopback;
  output [1:0]pipe_rxprbserr;
  input [1:0]pipe_txinhibit;
  output [4:0]pipe_rst_fsm;
  output [11:0]pipe_qrst_fsm;
  output [9:0]pipe_rate_fsm;
  output [11:0]pipe_sync_fsm_tx;
  output [13:0]pipe_sync_fsm_rx;
  output [13:0]pipe_drp_fsm;
  output pipe_rst_idle;
  output pipe_qrst_idle;
  output pipe_rate_idle;
  output [1:0]pipe_eyescandataerror;
  output [5:0]pipe_rxstatus;
  output [29:0]pipe_dmonitorout;
  output [1:0]pipe_cpll_lock;
  output [0:0]pipe_qpll_lock;
  output [1:0]pipe_rxpmaresetdone;
  output [5:0]pipe_rxbufstatus;
  output [1:0]pipe_txphaligndone;
  output [1:0]pipe_txphinitdone;
  output [1:0]pipe_txdlysresetdone;
  output [1:0]pipe_rxphaligndone;
  output [1:0]pipe_rxdlysresetdone;
  output [1:0]pipe_rxsyncdone;
  output [15:0]pipe_rxdisperr;
  output [15:0]pipe_rxnotintable;
  output [1:0]pipe_rxcommadet;
  output [1:0]gt_ch_drp_rdy;
  output [1:0]pipe_debug_0;
  output [1:0]pipe_debug_1;
  output [1:0]pipe_debug_2;
  output [1:0]pipe_debug_3;
  output [1:0]pipe_debug_4;
  output [1:0]pipe_debug_5;
  output [1:0]pipe_debug_6;
  output [1:0]pipe_debug_7;
  output [1:0]pipe_debug_8;
  output [1:0]pipe_debug_9;
  output [31:0]pipe_debug;
  input [1:0]gt_pcieuserratedone;
  input [5:0]gt_loopback;
  input [1:0]gt_txprbsforceerr;
  input [1:0]gt_txinhibit;
  input [7:0]gt_txprbssel;
  input [7:0]gt_rxprbssel;
  input [1:0]gt_rxprbscntreset;
  input [1:0]gt_dmonitorclk;
  input [1:0]gt_dmonfiforeset;
  output [1:0]gt_txelecidle;
  output [1:0]gt_txresetdone;
  output [1:0]gt_rxresetdone;
  output [1:0]gt_rxpmaresetdone;
  output [1:0]gt_txphaligndone;
  output [1:0]gt_txphinitdone;
  output [1:0]gt_txdlysresetdone;
  output [1:0]gt_rxphaligndone;
  output [1:0]gt_rxdlysresetdone;
  output [1:0]gt_rxsyncdone;
  output [1:0]gt_eyescandataerror;
  output [1:0]gt_rxprbserr;
  output [33:0]gt_dmonitorout;
  output [1:0]gt_rxcommadet;
  output [1:0]gt_phystatus;
  output [1:0]gt_rxvalid;
  output [1:0]gt_rxcdrlock;
  output [1:0]gt_pcierateidle;
  output [1:0]gt_pcieuserratestart;
  output [1:0]gt_gtpowergood;
  output [1:0]gt_cplllock;
  output [1:0]gt_rxoutclk;
  output [1:0]gt_rxrecclkout;
  output [0:0]gt_qpll1lock;
  output [5:0]gt_rxstatus;
  output [5:0]gt_rxbufstatus;
  output [8:0]gt_bufgtdiv;
  output [3:0]phy_txeq_ctrl;
  output [7:0]phy_txeq_preset;
  output [3:0]phy_rst_fsm;
  output [5:0]phy_txeq_fsm;
  output [5:0]phy_rxeq_fsm;
  output phy_rst_idle;
  output phy_rrst_n;
  output phy_prst_n;
  (* keep = "true" *) output ext_ch_gt_drpclk;
  (* keep = "true" *) input [17:0]ext_ch_gt_drpaddr;
  (* keep = "true" *) input [1:0]ext_ch_gt_drpen;
  (* keep = "true" *) input [1:0]ext_ch_gt_drpwe;
  (* keep = "true" *) input [31:0]ext_ch_gt_drpdi;
  (* keep = "true" *) output [1:0]ext_ch_gt_drprdy;
  (* keep = "true" *) output [31:0]ext_ch_gt_drpdo;
  output mcap_design_switch;
  output cap_req;
  input cap_gnt;
  input cap_rel;
  input mcap_eos_in;
  output startup_cfgclk;
  output startup_cfgmclk;
  output [3:0]startup_di;
  output startup_eos;
  output startup_preq;
  input [3:0]startup_do;
  input [3:0]startup_dts;
  input startup_fcsbo;
  input startup_fcsbts;
  input startup_gsr;
  input startup_gts;
  input startup_keyclearb;
  input startup_pack;
  input startup_usrcclko;
  input startup_usrcclkts;
  input startup_usrdoneo;
  input startup_usrdonets;
  output drp_rdy;
  output [15:0]drp_do;
  (* keep = "true" *) input drp_clk;
  (* keep = "true" *) input drp_en;
  (* keep = "true" *) input drp_we;
  (* keep = "true" *) input [10:0]drp_addr;
  (* keep = "true" *) input [15:0]drp_di;
  output cfg_ext_read_received;
  output cfg_ext_write_received;
  output [9:0]cfg_ext_register_number;
  output [7:0]cfg_ext_function_number;
  output [31:0]cfg_ext_write_data;
  output [3:0]cfg_ext_write_byte_enable;
  input [31:0]cfg_ext_read_data;
  input cfg_ext_read_data_valid;
  output int_pclk_out_slave;
  output int_pipe_rxusrclk_out;
  output [1:0]int_rxoutclk_out;
  output int_dclk_out;
  output int_userclk1_out;
  output int_userclk2_out;
  output int_oobclk_out;
  output [1:0]int_qplllock_out;
  output [1:0]int_qplloutclk_out;
  output [1:0]int_qplloutrefclk_out;
  input [1:0]int_pclk_sel_slave;
  input pipe_pclk_in;
  input pipe_rxusrclk_in;
  input [1:0]pipe_rxoutclk_in;
  input pipe_dclk_in;
  input pipe_userclk1_in;
  input pipe_userclk2_in;
  input pipe_oobclk_in;
  input pipe_mmcm_rst_n;
  input pipe_mmcm_lock_in;
  output pipe_txoutclk_out;
  output [1:0]pipe_rxoutclk_out;
  output [1:0]pipe_pclk_sel_out;
  output pipe_gen3_out;
  input [11:0]qpll_drp_crscode;
  input [17:0]qpll_drp_fsm;
  input [1:0]qpll_drp_done;
  input [1:0]qpll_drp_reset;
  input [1:0]qpll_qplllock;
  input [1:0]qpll_qplloutclk;
  input [1:0]qpll_qplloutrefclk;
  output qpll_qplld;
  output [1:0]qpll_qpllreset;
  output qpll_drp_clk;
  output qpll_drp_rst_n;
  output qpll_drp_ovrd;
  output qpll_drp_gen3;
  output qpll_drp_start;
  output [0:0]int_qpll1lock_out;
  output [0:0]int_qpll1outclk_out;
  output [0:0]int_qpll1outrefclk_out;
  output [0:0]ext_qpll1refclk;
  output [0:0]ext_qpll1pd;
  output [2:0]ext_qpll1rate;
  output [0:0]ext_qpll1reset;
  input [0:0]ext_qpll1lock_out;
  input [0:0]ext_qpll1outclk_out;
  input [0:0]ext_qpll1outrefclk_out;
  output [63:0]m_axis_rq_tdata_out;
  output m_axis_rq_tlast_out;
  output [59:0]m_axis_rq_tuser_out;
  output [1:0]m_axis_rq_tkeep_out;
  output [3:0]m_axis_rq_tready_out;
  output m_axis_rq_tvalid_out;
  output [63:0]s_axis_rc_tdata_out;
  output [74:0]s_axis_rc_tuser_out;
  output s_axis_rc_tlast_out;
  output [1:0]s_axis_rc_tkeep_out;
  output s_axis_rc_tvalid_out;
  output s_axis_rc_tready_out;
  output [63:0]s_axis_cq_tdata_out;
  output [84:0]s_axis_cq_tuser_out;
  output s_axis_cq_tlast_out;
  output [1:0]s_axis_cq_tkeep_out;
  output s_axis_cq_tvalid_out;
  output s_axis_cq_tready_out;
  output [63:0]m_axis_cc_tdata_out;
  output [32:0]m_axis_cc_tuser_out;
  output m_axis_cc_tlast_out;
  output [1:0]m_axis_cc_tkeep_out;
  output m_axis_cc_tvalid_out;
  output [3:0]m_axis_cc_tready_out;
  output [0:0]gt_qpll0lock;
  output [1:0]gt_gen34_eios_det;
  output [1:0]gt_txoutclk;
  output [1:0]gt_txoutclkfabric;
  output [1:0]gt_rxoutclkfabric;
  output [1:0]gt_txoutclkpcs;
  output [1:0]gt_rxoutclkpcs;
  input [1:0]gt_txpmareset;
  input [1:0]gt_rxpmareset;
  input [1:0]gt_txpcsreset;
  input [1:0]gt_rxpcsreset;
  input [1:0]gt_rxbufreset;
  input [1:0]gt_rxcdrreset;
  input [1:0]gt_rxdfelpmreset;
  output [1:0]gt_txprogdivresetdone;
  output [1:0]gt_txpmaresetdone;
  output [1:0]gt_txsyncdone;
  output [1:0]gt_rxprbslocked;
  input [5:0]bufgtce_us_out;
  input [5:0]bufgtcemask_us_out;
  input [17:0]bufgtdiv_us_out;
  input [5:0]bufgtreset_us_out;
  input [5:0]bufgtrstmask_us_out;
  input [1:0]cplllock_us_out;
  input [33:0]dmonitorout_us_out;
  input [31:0]drpdo_us_out;
  input [1:0]drprdy_us_out;
  input [1:0]eyescandataerror_us_out;
  input [1:0]gthtxn_us_out;
  input [1:0]gthtxp_us_out;
  input [1:0]gtpowergood_us_out;
  input [1:0]pcierategen3_us_out;
  input [1:0]pcierateidle_us_out;
  input [3:0]pcierateqpllpd_us_out;
  input [3:0]pcierateqpllreset_us_out;
  input [1:0]pciesynctxsyncdone_us_out;
  input [1:0]pcieusergen3rdy_us_out;
  input [1:0]pcieuserphystatusrst_us_out;
  input [1:0]pcieuserratestart_us_out;
  input [23:0]pcsrsvdout_us_out;
  input [1:0]phystatus_us_out;
  input [5:0]rxbufstatus_us_out;
  input [1:0]rxbyteisaligned_us_out;
  input [1:0]rxbyterealign_us_out;
  input [1:0]rxcdrlock_us_out;
  input [3:0]rxclkcorcnt_us_out;
  input [1:0]rxcommadet_us_out;
  input [31:0]rxctrl0_us_out;
  input [31:0]rxctrl1_us_out;
  input [15:0]rxctrl2_us_out;
  input [15:0]rxctrl3_us_out;
  input [255:0]rxdata_us_out;
  input [1:0]rxdlysresetdone_us_out;
  input [1:0]rxelecidle_us_out;
  input [1:0]rxoutclk_us_out;
  input [1:0]rxphaligndone_us_out;
  input [1:0]rxpmaresetdone_us_out;
  input [1:0]rxprbserr_us_out;
  input [1:0]rxprbslocked_us_out;
  input [1:0]rxprgdivresetdone_us_out;
  input [1:0]rxratedone_us_out;
  input [1:0]rxresetdone_us_out;
  input [5:0]rxstatus_us_out;
  input [1:0]rxsyncdone_us_out;
  input [1:0]rxvalid_us_out;
  input [1:0]txdlysresetdone_us_out;
  input [1:0]txoutclk_us_out;
  input [1:0]txphaligndone_us_out;
  input [1:0]txphinitdone_us_out;
  input [1:0]txpmaresetdone_us_out;
  input [1:0]txprgdivresetdone_us_out;
  input [1:0]txresetdone_us_out;
  input [1:0]txsyncout_us_out;
  input [1:0]txsyncdone_us_out;
  output [1:0]cpllpd_us_in;
  output [1:0]rxdfeagchold_us_in;
  output [1:0]rxdfecfokhold_us_in;
  output [1:0]rxdfelfhold_us_in;
  output [1:0]rxdfekhhold_us_in;
  output [1:0]rxdfetap2hold_us_in;
  output [1:0]rxdfetap3hold_us_in;
  output [1:0]rxdfetap4hold_us_in;
  output [1:0]rxdfetap5hold_us_in;
  output [1:0]rxdfetap6hold_us_in;
  output [1:0]rxdfetap7hold_us_in;
  output [1:0]rxdfetap8hold_us_in;
  output [1:0]rxdfetap9hold_us_in;
  output [1:0]rxdfetap10hold_us_in;
  output [1:0]rxdfetap11hold_us_in;
  output [1:0]rxdfetap12hold_us_in;
  output [1:0]rxdfetap13hold_us_in;
  output [1:0]rxdfetap14hold_us_in;
  output [1:0]rxdfetap15hold_us_in;
  output [1:0]rxdfeuthold_us_in;
  output [1:0]rxdfevphold_us_in;
  output [1:0]rxoshold_us_in;
  output [1:0]rxlpmgchold_us_in;
  output [1:0]rxlpmhfhold_us_in;
  output [1:0]rxlpmlfhold_us_in;
  output [1:0]rxlpmoshold_us_in;
  output [1:0]cpllreset_us_in;
  output [1:0]dmonfiforeset_us_in;
  output [1:0]dmonitorclk_us_in;
  output [1:0]drpclk_us_in;
  output [17:0]drpaddr_us_in;
  output [31:0]drpdi_us_in;
  output [1:0]drpen_us_in;
  output [1:0]drpwe_us_in;
  output [1:0]eyescanreset_us_in;
  output [1:0]gthrxn_us_in;
  output [1:0]gthrxp_us_in;
  output [1:0]gtrefclk0_us_in;
  output [1:0]gtrxreset_us_in;
  output [1:0]gttxreset_us_in;
  output gtwiz_reset_rx_done_us_in;
  output gtwiz_reset_tx_done_us_in;
  output gtwiz_userclk_rx_active_us_in;
  output gtwiz_userclk_tx_active_us_in;
  output gtwiz_userclk_tx_reset_us_in;
  output [5:0]loopback_us_in;
  output [1:0]pcieeqrxeqadaptdone_us_in;
  output [1:0]pcierstidle_us_in;
  output [1:0]pciersttxsyncstart_us_in;
  output [1:0]pcieuserratedone_us_in;
  output [31:0]pcsrsvdin_us_in;
  output [1:0]rx8b10ben_us_in;
  output [1:0]rxbufreset_us_in;
  output [1:0]rxcdrhold_us_in;
  output [1:0]rxcommadeten_us_in;
  output [1:0]rxlpmen_us_in;
  output [1:0]rxmcommaalignen_us_in;
  output [1:0]rxpcommaalignen_us_in;
  output [3:0]rxpd_us_in;
  output [1:0]rxpolarity_us_in;
  output [1:0]rxprbscntreset_us_in;
  output [7:0]rxprbssel_us_in;
  output [1:0]rxprogdivreset_us_in;
  output [5:0]rxrate_us_in;
  output [1:0]rxratemode_us_in;
  output [1:0]rxslide_us_in;
  output [1:0]rxuserrdy_us_in;
  output [1:0]rxusrclk2_us_in;
  output [1:0]rxusrclk_us_in;
  output [1:0]tx8b10ben_us_in;
  output [31:0]txctrl0_us_in;
  output [31:0]txctrl1_us_in;
  output [15:0]txctrl2_us_in;
  output [255:0]txdata_us_in;
  output [1:0]txdeemph_us_in;
  output [1:0]txdetectrx_us_in;
  output [7:0]txdiffctrl_us_in;
  output [1:0]txdlybypass_us_in;
  output [1:0]txdlyen_us_in;
  output [1:0]txdlyhold_us_in;
  output [1:0]txdlyovrden_us_in;
  output [1:0]txdlysreset_us_in;
  output [1:0]txdlyupdown_us_in;
  output [1:0]txelecidle_us_in;
  output [1:0]txinhibit_us_in;
  output [13:0]txmaincursor_us_in;
  output [5:0]txmargin_us_in;
  output [5:0]txoutclksel_us_in;
  output [3:0]txpd_us_in;
  output [1:0]txphalign_us_in;
  output [1:0]txphalignen_us_in;
  output [1:0]txphdlypd_us_in;
  output [1:0]txphdlyreset_us_in;
  output [1:0]txphdlytstclk_us_in;
  output [1:0]txphinit_us_in;
  output [1:0]txphovrden_us_in;
  output [9:0]txpostcursor_us_in;
  output [1:0]txprbsforceerr_us_in;
  output [7:0]txprbssel_us_in;
  output [9:0]txprecursor_us_in;
  output [1:0]txprogdivreset_us_in;
  output [5:0]txrate_us_in;
  output [1:0]txswing_us_in;
  output [1:0]txsyncallin_us_in;
  output [1:0]txsyncin_us_in;
  output [1:0]txsyncmode_us_in;
  output [1:0]txuserrdy_us_in;
  output [1:0]txusrclk2_us_in;
  output [1:0]txusrclk_us_in;
  output [1:0]qpll0clk_us_in;
  output [1:0]qpll0refclk_us_in;
  output [1:0]qpll1clk_us_in;
  output [1:0]qpll1refclk_us_in;
  output [0:0]gtrefclk01_us_in;
  output [0:0]qpll1pd_us_in;
  output [0:0]qpll1reset_us_in;
  output [4:0]qpllrsvd2_us_in;
  output [4:0]qpllrsvd3_us_in;
  input [0:0]qpll1lock_us_out;
  input [0:0]qpll1outclk_us_out;
  input [0:0]qpll1outrefclk_us_out;
  output [7:0]cfg_bus_number_o;
  output [4:0]cfg_device_number_o;
  output [2:0]cfg_function_number_o;
  output cfg_to_turnoff_o;
  output [63:0]m_axis_rx_tdata_o;
  output [7:0]m_axis_rx_tkeep_o;
  output m_axis_rx_tlast_o;
  output [21:0]m_axis_rx_tuser_o;
  output m_axis_rx_tvalid_o;
  output s_axis_tx_tready_o;
  output Integrated_bloc_reset_o;
  input [4:0]cfg_aer_interrupt_msgnum_i;
  input [63:0]cfg_dsn_i;
  input [127:0]cfg_err_aer_headerlog_i;
  input [47:0]cfg_err_tlp_cpl_header_i;
  input [7:0]cfg_interrupt_di_i;
  input [31:0]cfg_mgmt_di_i;
  input [9:0]cfg_mgmt_dwaddr_i;
  input [4:0]cfg_pciecap_interrupt_msgnum_i;
  input [1:0]cfg_pm_force_state_i;
  input cfg_turnoff_ok_i;
  input [2:0]fc_sel_i;
  input m_axis_rx_tready_i;
  input pl_directed_link_auton_i;
  input [1:0]pl_directed_link_change_i;
  input pl_directed_link_speed_i;
  input [1:0]pl_directed_link_width_i;
  input pl_upstream_prefer_deemph_i;
  input rx_np_ok_i;
  input rx_np_req_i;
  input [63:0]s_axis_tx_tdata_i;
  input [7:0]s_axis_tx_tkeep_i;
  input s_axis_tx_tlast_i;
  input [3:0]s_axis_tx_tuser_i;
  input s_axis_tx_tvalid_i;
  input tx_cfg_gnt_i;
  output [0:0]gtrefclk01_usp_in;
  output [0:0]gtrefclk00_usp_in;
  output [2:0]pcierateqpll0_usp_in;
  output [2:0]pcierateqpll1_usp_in;
  output [0:0]qpll0pd_usp_in;
  output [0:0]qpll0reset_usp_in;
  output [0:0]qpll1pd_usp_in;
  output [0:0]qpll1reset_usp_in;
  input [0:0]qpll0lock_usp_out;
  input [0:0]qpll0outclk_usp_out;
  input [0:0]qpll0outrefclk_usp_out;
  input [0:0]qpll1lock_usp_out;
  input [0:0]qpll1outclk_usp_out;
  input [0:0]qpll1outrefclk_usp_out;
  output [1:0]qpll0freqlock_usp_in;
  output [1:0]qpll1freqlock_usp_in;
  input [3:0]pcierateqpllpd_usp_out;
  input [3:0]pcierateqpllreset_usp_out;
  output [0:0]rcalenb_usp_in;
  output [1:0]txpisopd_usp_in;
  input [1:0]bufgtce_usp_out;
  input [5:0]bufgtcemask_usp_out;
  input [17:0]bufgtdiv_usp_out;
  input [1:0]bufgtreset_usp_out;
  input [5:0]bufgtrstmask_usp_out;
  output [1:0]cpllfreqlock_usp_in;
  input [1:0]cplllock_usp_out;
  output [1:0]cpllpd_usp_in;
  output [1:0]cpllreset_usp_in;
  output [1:0]dmonfiforeset_usp_in;
  output [1:0]dmonitorclk_usp_in;
  input [31:0]dmonitorout_usp_out;
  output [1:0]eyescanreset_usp_in;
  input [1:0]gtpowergood_usp_out;
  output [1:0]gtrefclk0_usp_in;
  output [1:0]gtrxreset_usp_in;
  output [1:0]gttxreset_usp_in;
  output gtwiz_reset_rx_done_usp_in;
  output gtwiz_reset_tx_done_usp_in;
  output gtwiz_userclk_rx_active_usp_in;
  output gtwiz_userclk_tx_active_usp_in;
  output [5:0]loopback_usp_in;
  output [1:0]pcieeqrxeqadaptdone_usp_in;
  input [1:0]pcierategen3_usp_out;
  input [1:0]pcierateidle_usp_out;
  output [1:0]pcierstidle_usp_in;
  output [1:0]pciersttxsyncstart_usp_in;
  input [1:0]pciesynctxsyncdone_usp_out;
  input [1:0]pcieusergen3rdy_usp_out;
  input [1:0]pcieuserphystatusrst_usp_out;
  output [1:0]pcieuserratedone_usp_in;
  input [1:0]pcieuserratestart_usp_out;
  input [1:0]phystatus_usp_out;
  output [1:0]resetovrd_usp_in;
  output [1:0]rx8b10ben_usp_in;
  output [1:0]rxbufreset_usp_in;
  input [5:0]rxbufstatus_usp_out;
  input [1:0]rxbyteisaligned_usp_out;
  input [1:0]rxbyterealign_usp_out;
  output [1:0]rxcdrfreqreset_usp_in;
  output [1:0]rxcdrhold_usp_in;
  input [1:0]rxcdrlock_usp_out;
  output [1:0]rxcdrreset_usp_in;
  input [3:0]rxclkcorcnt_usp_out;
  input [1:0]rxcommadet_usp_out;
  output [1:0]rxcommadeten_usp_in;
  input [31:0]rxctrl0_usp_out;
  input [31:0]rxctrl1_usp_out;
  input [15:0]rxctrl2_usp_out;
  input [15:0]rxctrl3_usp_out;
  input [255:0]rxdata_usp_out;
  output [1:0]rxdfeagchold_usp_in;
  output [1:0]rxdfecfokhold_usp_in;
  output [1:0]rxdfekhhold_usp_in;
  output [1:0]rxdfelfhold_usp_in;
  output [1:0]rxdfelpmreset_usp_in;
  output [1:0]rxdfetap10hold_usp_in;
  output [1:0]rxdfetap11hold_usp_in;
  output [1:0]rxdfetap12hold_usp_in;
  output [1:0]rxdfetap13hold_usp_in;
  output [1:0]rxdfetap14hold_usp_in;
  output [1:0]rxdfetap15hold_usp_in;
  output [1:0]rxdfetap2hold_usp_in;
  output [1:0]rxdfetap3hold_usp_in;
  output [1:0]rxdfetap4hold_usp_in;
  output [1:0]rxdfetap5hold_usp_in;
  output [1:0]rxdfetap6hold_usp_in;
  output [1:0]rxdfetap7hold_usp_in;
  output [1:0]rxdfetap8hold_usp_in;
  output [1:0]rxdfetap9hold_usp_in;
  output [1:0]rxdfeuthold_usp_in;
  output [1:0]rxdfevphold_usp_in;
  input [1:0]rxdlysresetdone_usp_out;
  input [1:0]rxelecidle_usp_out;
  output [1:0]rxlpmen_usp_in;
  output [1:0]rxlpmgchold_usp_in;
  output [1:0]rxlpmhfhold_usp_in;
  output [1:0]rxlpmlfhold_usp_in;
  output [1:0]rxlpmoshold_usp_in;
  output [1:0]rxmcommaalignen_usp_in;
  output [1:0]rxoshold_usp_in;
  input [1:0]rxoutclk_usp_out;
  input [1:0]rxoutclkfabric_usp_out;
  input [1:0]rxoutclkpcs_usp_out;
  output [1:0]rxpcommaalignen_usp_in;
  output [1:0]rxpcsreset_usp_in;
  output [3:0]rxpd_usp_in;
  input [1:0]rxphaligndone_usp_out;
  output [1:0]rxpmareset_usp_in;
  input [1:0]rxpmaresetdone_usp_out;
  output [1:0]rxpolarity_usp_in;
  output [1:0]rxprbscntreset_usp_in;
  input [1:0]rxprbserr_usp_out;
  input [1:0]rxprbslocked_usp_out;
  output [7:0]rxprbssel_usp_in;
  output [1:0]rxprogdivreset_usp_in;
  output [5:0]rxrate_usp_in;
  input [1:0]rxratedone_usp_out;
  input [1:0]rxrecclkout_usp_out;
  input [1:0]rxresetdone_usp_out;
  output [1:0]rxslide_usp_in;
  input [5:0]rxstatus_usp_out;
  input [1:0]rxsyncdone_usp_out;
  output [1:0]rxtermination_usp_in;
  output [1:0]rxuserrdy_usp_in;
  output [1:0]rxusrclk2_usp_in;
  output [1:0]rxusrclk_usp_in;
  input [1:0]rxvalid_usp_out;
  output [1:0]tx8b10ben_usp_in;
  output [31:0]txctrl0_usp_in;
  output [31:0]txctrl1_usp_in;
  output [15:0]txctrl2_usp_in;
  output [255:0]txdata_usp_in;
  output [3:0]txdeemph_usp_in;
  output [1:0]txdetectrx_usp_in;
  output [9:0]txdiffctrl_usp_in;
  output [1:0]txdlybypass_usp_in;
  output [1:0]txdlyen_usp_in;
  output [1:0]txdlyhold_usp_in;
  output [1:0]txdlyovrden_usp_in;
  output [1:0]txdlysreset_usp_in;
  input [1:0]txdlysresetdone_usp_out;
  output [1:0]txdlyupdown_usp_in;
  output [1:0]txelecidle_usp_in;
  output [13:0]txmaincursor_usp_in;
  output [5:0]txmargin_usp_in;
  input [1:0]txoutclk_usp_out;
  input [1:0]txoutclkfabric_usp_out;
  input [1:0]txoutclkpcs_usp_out;
  output [5:0]txoutclksel_usp_in;
  output [1:0]txpcsreset_usp_in;
  output [3:0]txpd_usp_in;
  output [1:0]txphalign_usp_in;
  input [1:0]txphaligndone_usp_out;
  output [1:0]txphalignen_usp_in;
  output [1:0]txphdlypd_usp_in;
  output [1:0]txphdlyreset_usp_in;
  output [1:0]txphdlytstclk_usp_in;
  output [1:0]txphinit_usp_in;
  input [1:0]txphinitdone_usp_out;
  output [1:0]txphovrden_usp_in;
  output [1:0]rxratemode_usp_in;
  output [1:0]txpmareset_usp_in;
  input [1:0]txpmaresetdone_usp_out;
  output [9:0]txpostcursor_usp_in;
  output [1:0]txprbsforceerr_usp_in;
  output [7:0]txprbssel_usp_in;
  output [9:0]txprecursor_usp_in;
  input [1:0]txprgdivresetdone_usp_out;
  output [1:0]txprogdivreset_usp_in;
  output [1:0]txpdelecidlemode_usp_in;
  output [5:0]txrate_usp_in;
  input [1:0]txresetdone_usp_out;
  output [1:0]txswing_usp_in;
  output [1:0]txsyncallin_usp_in;
  input [1:0]txsyncdone_usp_out;
  output [1:0]txsyncin_usp_in;
  output [1:0]txsyncmode_usp_in;
  input [1:0]txsyncout_usp_out;
  output [1:0]txuserrdy_usp_in;
  output [1:0]txusrclk2_usp_in;
  output [1:0]txusrclk_usp_in;
  output drpclk_usp_in;
  output [19:0]drpaddr_usp_in;
  output [1:0]drpen_usp_in;
  output [1:0]drprst_usp_in;
  output [1:0]drpwe_usp_in;
  output [31:0]drpdi_usp_in;
  input [1:0]drprdy_usp_out;
  input [31:0]drpdo_usp_out;
  input ext_phy_clk_pclk2_gt;
  input ext_phy_clk_int_clock;
  input ext_phy_clk_pclk;
  input ext_phy_clk_phy_pclk2;
  input ext_phy_clk_phy_coreclk;
  input ext_phy_clk_phy_userclk;
  input ext_phy_clk_phy_mcapclk;
  output ext_phy_clk_bufg_gt_ce;
  output ext_phy_clk_bufg_gt_reset;
  output ext_phy_clk_rst_idle;
  output ext_phy_clk_txoutclk;
  output ext_phy_clk_bufgtcemask;
  output ext_phy_clk_gt_bufgtrstmask;
  output [8:0]ext_phy_clk_bufgtdiv;
  output [0:0]int_usp_qpll0lock_out;
  output [0:0]int_usp_qpll0outrefclk_out;
  output [0:0]int_usp_qpll0outclk_out;
  output [0:0]int_usp_qpll1lock_out;
  output [0:0]int_usp_qpll1outrefclk_out;
  output [0:0]int_usp_qpll1outclk_out;
  output [0:0]ext_usp_qpllxrefclk;
  output [2:0]ext_usp_qpllxrate;
  output ext_usp_qpllxrcalenb;
  output [0:0]ext_usp_qpll0pd;
  output [0:0]ext_usp_qpll0reset;
  input [0:0]ext_usp_qpll0lock_out;
  input [0:0]ext_usp_qpll0outclk_out;
  input [0:0]ext_usp_qpll0outrefclk_out;
  output [0:0]ext_usp_qpll1pd;
  output [0:0]ext_usp_qpll1reset;
  input [0:0]ext_usp_qpll1lock_out;
  input [0:0]ext_usp_qpll1outclk_out;
  input [0:0]ext_usp_qpll1outrefclk_out;
  output [3:0]cfg_negotiated_width_o;
  output [2:0]cfg_current_speed_o;
  output [5:0]cfg_ltssm_state_o;
  output cfg_err_cor_o;
  output cfg_err_fatal_o;
  output cfg_err_nonfatal_o;
  output [4:0]cfg_local_error_o;
  output cfg_local_error_valid_o;
  output pipe_tx0_rcvr_det;
  output pipe_clk;
  output sys_clk_bufg;
  output [1:0]pipe_tx0_powerdown;
  output [7:0]cfg_function_status;
  output [2:0]cfg_max_read_req;
  output [2:0]cfg_max_payload;
  input [3:0]cfg_flr_done;
  output [3:0]cfg_flr_in_process;
  output [251:0]cfg_vf_flr_in_process;
  input [7:0]cfg_vf_flr_func_num;
  input cfg_vf_flr_done;
  output [3:0]cfg_interrupt_msi_enable;
  output [1:0]cfg_interrupt_msix_enable;
  output [1:0]cfg_interrupt_msix_mask;
  input [31:0]cfg_interrupt_msix_data;
  input [63:0]cfg_interrupt_msix_address;
  input cfg_interrupt_msix_int;
  output cfg_interrupt_msi_sent;
  output cfg_interrupt_msi_fail;
  output cfg_interrupt_msix_sent;
  output cfg_interrupt_msix_fail;
  input phy_rdy_out_sd;
  output cfg_err_cor_in_sd;
  output cfg_link_training_enable_sd;
  output cfg_config_space_enable_sd;
  input [5:0]cfg_ltssm_state_sd;
  input user_lnk_up_sd;
  output [63:0]s_axis_rq_tdata_sd;
  output s_axis_rq_tlast_sd;
  output [59:0]s_axis_rq_tuser_sd;
  output [1:0]s_axis_rq_tkeep_sd;
  output s_axis_rq_tvalid_sd;
  input [3:0]s_axis_rq_tready_sd;
  input [63:0]m_axis_rc_tdata_sd;
  input [74:0]m_axis_rc_tuser_sd;
  input m_axis_rc_tlast_sd;
  input [1:0]m_axis_rc_tkeep_sd;
  input m_axis_rc_tvalid_sd;
  output m_axis_rc_tready_sd;
  input [63:0]m_axis_cq_tdata_sd;
  input [84:0]m_axis_cq_tuser_sd;
  input m_axis_cq_tlast_sd;
  input [1:0]m_axis_cq_tkeep_sd;
  input m_axis_cq_tvalid_sd;
  output m_axis_cq_tready_sd;
  output [63:0]s_axis_cc_tdata_sd;
  output [32:0]s_axis_cc_tuser_sd;
  output s_axis_cc_tlast_sd;
  output [1:0]s_axis_cc_tkeep_sd;
  output s_axis_cc_tvalid_sd;
  input [3:0]s_axis_cc_tready_sd;
  input [5:0]rbar_bar_size_sd;
  input [7:0]rbar_function_number_sd;
  input rbar_write_enable_bar0_sd;
  input rbar_write_enable_bar1_sd;
  input rbar_write_enable_bar2_sd;
  input rbar_write_enable_bar3_sd;
  input rbar_write_enable_bar4_sd;
  input rbar_write_enable_bar5_sd;
  input user_clk_sd;
  input user_reset_sd;
  output [1:0]pcie_cq_np_req_sd;
  input [5:0]pcie_cq_np_req_count_sd;
  input [3:0]pcie_tfc_nph_av_sd;
  input [3:0]pcie_tfc_npd_av_sd;
  input pcie_rq_seq_num_vld0_sd;
  input [5:0]pcie_rq_seq_num0_sd;
  input pcie_rq_seq_num_vld1_sd;
  input [5:0]pcie_rq_seq_num1_sd;
  input [7:0]cfg_fc_nph_sd;
  output [2:0]cfg_fc_sel_sd;
  input cfg_phy_link_down_sd;
  input [1:0]cfg_phy_link_status_sd;
  input [2:0]cfg_negotiated_width_sd;
  input [1:0]cfg_current_speed_sd;
  input cfg_pl_status_change_sd;
  input cfg_hot_reset_out_sd;
  output [7:0]cfg_ds_port_number_sd;
  output [7:0]cfg_ds_bus_number_sd;
  output [4:0]cfg_ds_device_number_sd;
  output [2:0]cfg_ds_function_number_sd;
  output [63:0]cfg_dsn_sd;
  input [15:0]cfg_function_status_sd;
  input [2:0]cfg_max_read_req_sd;
  input [1:0]cfg_max_payload_sd;
  output cfg_err_uncor_in_sd;
  output [3:0]cfg_flr_done_sd;
  input [3:0]cfg_flr_in_process_sd;
  input [251:0]cfg_vf_flr_in_process_sd;
  output [7:0]usr_flr_fnc;
  output usr_flr_set;
  output usr_flr_clr;
  input [7:0]usr_flr_done_fnc;
  input usr_flr_done_vld;
  input cfg_err_cor_out_sd;
  input cfg_err_nonfatal_out_sd;
  input cfg_err_fatal_out_sd;
  input [4:0]cfg_local_error_out_sd;
  input cfg_msg_received_sd;
  input [7:0]cfg_msg_received_data_sd;
  input [4:0]cfg_msg_received_type_sd;
  output cfg_msg_transmit_sd;
  output [2:0]cfg_msg_transmit_type_sd;
  output [31:0]cfg_msg_transmit_data_sd;
  input cfg_msg_transmit_done_sd;
  output [9:0]cfg_mgmt_addr_sd;
  output cfg_mgmt_write_sd;
  output [31:0]cfg_mgmt_write_data_sd;
  output [3:0]cfg_mgmt_byte_enable_sd;
  output cfg_mgmt_read_sd;
  output cfg_mgmt_type1_cfg_reg_access_sd;
  input [31:0]cfg_mgmt_read_data_sd;
  input cfg_mgmt_read_write_done_sd;
  output [7:0]cfg_mgmt_function_number_sd;
  output [3:0]cfg_interrupt_int_sd;
  input cfg_interrupt_sent_sd;
  output [3:0]cfg_interrupt_pending_sd;
  input [3:0]cfg_interrupt_msi_enable_sd;
  input cfg_interrupt_msi_mask_update_sd;
  input [31:0]cfg_interrupt_msi_data_sd;
  output [31:0]cfg_interrupt_msi_int_sd;
  output [31:0]cfg_interrupt_msi_pending_status_sd;
  output cfg_interrupt_msi_pending_status_data_enable_sd;
  output [3:0]cfg_interrupt_msi_pending_status_function_num_sd;
  output [2:0]cfg_interrupt_msi_attr_sd;
  output cfg_interrupt_msi_tph_present_sd;
  output [1:0]cfg_interrupt_msi_tph_type_sd;
  output [8:0]cfg_interrupt_msi_tph_st_tag_sd;
  output [7:0]cfg_interrupt_msi_function_number_sd;
  input cfg_interrupt_msi_sent_sd;
  input cfg_interrupt_msi_fail_sd;
  input [3:0]cfg_interrupt_msix_enable_sd;
  input [3:0]cfg_interrupt_msix_mask_sd;
  output [31:0]cfg_interrupt_msix_data_sd;
  output [63:0]cfg_interrupt_msix_address_sd;
  output cfg_interrupt_msix_int_sd;
  input [251:0]cfg_interrupt_msix_vf_enable_sd;
  input [251:0]cfg_interrupt_msix_vf_mask_sd;
  output [1:0]cfg_interrupt_msix_vec_pending_sd;
  input cfg_interrupt_msix_vec_pending_status_sd;
  output rd_interrupt;
  output wr_interrupt;
  output ats_pri_en;
  input cfg_fc_vc_sel;
  output core_clk;
  input cxs0_active_req_tx;
  output cxs0_active_ack_tx;
  output cxs0_deact_hint_tx;
  input cxs0_valid_tx;
  output cxs0_crdgnt_tx;
  input cxs0_crdrtn_tx;
  input [13:0]cxs0_cntl_tx;
  input [255:0]cxs0_data_tx;
  input cxs0_valid_chk_tx;
  output cxs0_crdgnt_chk_tx;
  input cxs0_crdrtn_chk_tx;
  input cxs0_cntl_chk_tx;
  input [31:0]cxs0_data_chk_tx;
  output cxs0_active_req_rx;
  input cxs0_active_ack_rx;
  input cxs0_deact_hint_rx;
  output cxs0_valid_rx;
  input cxs0_crdgnt_rx;
  output cxs0_crdrtn_rx;
  output [13:0]cxs0_cntl_rx;
  output [255:0]cxs0_data_rx;
  output cxs0_valid_chk_rx;
  input cxs0_crdgnt_chk_rx;
  output cxs0_crdrtn_chk_rx;
  output cxs0_cntl_chk_rx;
  output [31:0]cxs0_data_chk_rx;
  output pcie4_cxs0_active_req_tx_sd;
  input pcie4_cxs0_active_ack_tx_sd;
  input pcie4_cxs0_deact_hint_tx_sd;
  output pcie4_cxs0_valid_tx_sd;
  input pcie4_cxs0_crdgnt_tx_sd;
  output pcie4_cxs0_crdrtn_tx_sd;
  output [13:0]pcie4_cxs0_cntl_tx_sd;
  output [255:0]pcie4_cxs0_data_tx_sd;
  output pcie4_cxs0_valid_chk_tx_sd;
  input pcie4_cxs0_crdgnt_chk_tx_sd;
  output pcie4_cxs0_crdrtn_chk_tx_sd;
  output pcie4_cxs0_cntl_chk_tx_sd;
  output [31:0]pcie4_cxs0_data_chk_tx_sd;
  input pcie4_cxs0_active_req_rx_sd;
  output pcie4_cxs0_active_ack_rx_sd;
  output pcie4_cxs0_deact_hint_rx_sd;
  input pcie4_cxs0_valid_rx_sd;
  output pcie4_cxs0_crdgnt_rx_sd;
  input pcie4_cxs0_crdrtn_rx_sd;
  input [13:0]pcie4_cxs0_cntl_rx_sd;
  input [255:0]pcie4_cxs0_data_rx_sd;
  input pcie4_cxs0_valid_chk_rx_sd;
  output pcie4_cxs0_crdgnt_chk_rx_sd;
  input pcie4_cxs0_crdrtn_chk_rx_sd;
  input pcie4_cxs0_cntl_chk_rx_sd;
  input [31:0]pcie4_cxs0_data_chk_rx_sd;
  input ccix_optimized_tlp_tx_and_rx_enable_in;
  input sc0_ats_s_axis_rq_tvalid;
  output sc0_ats_s_axis_rq_tready;
  input [63:0]sc0_ats_s_axis_rq_tdata;
  input [7:0]sc0_ats_s_axis_rq_tkeep;
  input sc0_ats_s_axis_rq_tlast;
  input [59:0]sc0_ats_s_axis_rq_tuser;
  output sc0_ats_m_axis_rc_tvalid;
  input sc0_ats_m_axis_rc_tready;
  output [63:0]sc0_ats_m_axis_rc_tdata;
  output [7:0]sc0_ats_m_axis_rc_tkeep;
  output sc0_ats_m_axis_rc_tlast;
  output [74:0]sc0_ats_m_axis_rc_tuser;
  input sc0_ats_s_axis_cc_tvalid;
  output sc0_ats_s_axis_cc_tready;
  input [63:0]sc0_ats_s_axis_cc_tdata;
  input [7:0]sc0_ats_s_axis_cc_tkeep;
  input sc0_ats_s_axis_cc_tlast;
  input [32:0]sc0_ats_s_axis_cc_tuser;
  output sc0_ats_m_axis_cq_tvalid;
  input sc0_ats_m_axis_cq_tready;
  output [63:0]sc0_ats_m_axis_cq_tdata;
  output [7:0]sc0_ats_m_axis_cq_tkeep;
  output sc0_ats_m_axis_cq_tlast;
  output [84:0]sc0_ats_m_axis_cq_tuser;
  input sc1_ats_s_axis_rq_tvalid;
  output sc1_ats_s_axis_rq_tready;
  input [63:0]sc1_ats_s_axis_rq_tdata;
  input [7:0]sc1_ats_s_axis_rq_tkeep;
  input sc1_ats_s_axis_rq_tlast;
  input [59:0]sc1_ats_s_axis_rq_tuser;
  output sc1_ats_m_axis_rc_tvalid;
  input sc1_ats_m_axis_rc_tready;
  output [63:0]sc1_ats_m_axis_rc_tdata;
  output [7:0]sc1_ats_m_axis_rc_tkeep;
  output sc1_ats_m_axis_rc_tlast;
  output [74:0]sc1_ats_m_axis_rc_tuser;
  input sc1_ats_s_axis_cc_tvalid;
  output sc1_ats_s_axis_cc_tready;
  input [63:0]sc1_ats_s_axis_cc_tdata;
  input [7:0]sc1_ats_s_axis_cc_tkeep;
  input sc1_ats_s_axis_cc_tlast;
  input [32:0]sc1_ats_s_axis_cc_tuser;
  output sc1_ats_m_axis_cq_tvalid;
  input sc1_ats_m_axis_cq_tready;
  output [63:0]sc1_ats_m_axis_cq_tdata;
  output [7:0]sc1_ats_m_axis_cq_tkeep;
  output sc1_ats_m_axis_cq_tlast;
  output [84:0]sc1_ats_m_axis_cq_tuser;
  input s_aclk;
  input s_aresetn;
  input [13:0]s_axi_araddr;
  input [1:0]s_axi_arburst;
  input [3:0]s_axi_arcache;
  input [15:0]s_axi_arid;
  input [7:0]s_axi_arlen;
  input [0:0]s_axi_arlock;
  input [2:0]s_axi_arprot;
  input [3:0]s_axi_arqos;
  output s_axi_arready;
  input [2:0]s_axi_arsize;
  input [15:0]s_axi_aruser;
  input s_axi_arvalid;
  input [13:0]s_axi_awaddr;
  input [1:0]s_axi_awburst;
  input [3:0]s_axi_awcache;
  input [15:0]s_axi_awid;
  input [7:0]s_axi_awlen;
  input [0:0]s_axi_awlock;
  input [2:0]s_axi_awprot;
  input [3:0]s_axi_awqos;
  output s_axi_awready;
  input [2:0]s_axi_awsize;
  input [15:0]s_axi_awuser;
  input s_axi_awvalid;
  output [15:0]s_axi_bid;
  input s_axi_bready;
  output [1:0]s_axi_bresp;
  output s_axi_bvalid;
  output [31:0]s_axi_rdata;
  output [15:0]s_axi_rid;
  output s_axi_rlast;
  input s_axi_rready;
  output [1:0]s_axi_rresp;
  output s_axi_rvalid;
  input [31:0]s_axi_wdata;
  input s_axi_wlast;
  output s_axi_wready;
  input [3:0]s_axi_wstrb;
  input s_axi_wvalid;
  output [63:0]atspri_m_axis_cq_tdata;
  output [84:0]atspri_m_axis_cq_tuser;
  output atspri_m_axis_cq_tlast;
  output [1:0]atspri_m_axis_cq_tkeep;
  output atspri_m_axis_cq_tvalid;
  input atspri_m_axis_cq_tready;
  input [63:0]atspri_s_axis_rq_tdata;
  input [59:0]atspri_s_axis_rq_tuser;
  input atspri_s_axis_rq_tlast;
  input [1:0]atspri_s_axis_rq_tkeep;
  input atspri_s_axis_rq_tvalid;
  output atspri_s_axis_rq_tready;
  output [4:0]cfg_status_ats_stu;
  output cfg_status_ats_en;
  output cfg_status_pr_en;
  output cfg_status_pr_rst;
  output cfg_status_pr_uprgi;
  input cfg_status_set_uprgi;
  output cfg_status_pr_rf;
  input cfg_status_set_rf;
  input cfg_status_set_s;
  input cfg_status_clr_s;
  output [31:0]cfg_status_ost_pr_alloc;

  wire \<const0> ;
  wire \<const1> ;
  (* RTL_KEEP = "true" *) wire axi_aclk;
  wire \axis_rc\.tready ;
  (* RTL_KEEP = "true" *) wire [7:0]blk_cfg_ext_function_number;
  (* RTL_KEEP = "true" *) wire [31:0]blk_cfg_ext_read_data;
  (* RTL_KEEP = "true" *) wire blk_cfg_ext_read_data_valid;
  (* RTL_KEEP = "true" *) wire blk_cfg_ext_read_received;
  (* RTL_KEEP = "true" *) wire [9:0]blk_cfg_ext_register_number;
  (* RTL_KEEP = "true" *) wire [3:0]blk_cfg_ext_write_byte_enable;
  (* RTL_KEEP = "true" *) wire [31:0]blk_cfg_ext_write_data;
  (* RTL_KEEP = "true" *) wire blk_cfg_ext_write_received;
  wire [4:0]cfg_aer_interrupt_msgnum_i;
  wire [7:0]cfg_bus_number_o;
  wire [4:0]cfg_device_number_o;
  wire [63:0]cfg_dsn_i;
  wire [127:0]cfg_err_aer_headerlog_i;
  wire [47:0]cfg_err_tlp_cpl_header_i;
  wire [0:0]cfg_fc_sel;
  wire [2:0]cfg_function_number_o;
  wire [7:0]cfg_interrupt_di_i;
  wire [0:0]cfg_interrupt_int;
  wire [31:0]cfg_interrupt_msi_int;
  (* RTL_KEEP = "true" *) wire [18:0]cfg_mgmt_addr;
  (* RTL_KEEP = "true" *) wire [3:0]cfg_mgmt_byte_enable;
  wire [31:0]cfg_mgmt_di_i;
  wire [9:0]cfg_mgmt_dwaddr_i;
  (* RTL_KEEP = "true" *) wire cfg_mgmt_read;
  (* RTL_KEEP = "true" *) wire [31:0]cfg_mgmt_read_data;
  (* RTL_KEEP = "true" *) wire cfg_mgmt_read_write_done;
  (* RTL_KEEP = "true" *) wire cfg_mgmt_type1_cfg_reg_access;
  (* RTL_KEEP = "true" *) wire cfg_mgmt_write;
  (* RTL_KEEP = "true" *) wire [31:0]cfg_mgmt_write_data;
  wire [4:0]cfg_pciecap_interrupt_msgnum_i;
  wire [1:0]cfg_pm_force_state_i;
  wire cfg_to_turnoff_o;
  wire cfg_turnoff_ok_i;
  wire dma_soft_reset;
  wire [2:0]fc_sel_i;
  (* RTL_KEEP = "true" *) wire [63:0]m_axi_araddr_temp;
  (* RTL_KEEP = "true" *) wire [1:0]\^m_axi_arburst ;
  (* RTL_KEEP = "true" *) wire [7:0]m_axi_arlen;
  (* RTL_KEEP = "true" *) wire m_axi_arready;
  (* RTL_KEEP = "true" *) wire [2:0]\^m_axi_arsize ;
  (* RTL_KEEP = "true" *) wire m_axi_arvalid;
  (* RTL_KEEP = "true" *) wire [63:0]m_axi_awaddr_temp;
  (* RTL_KEEP = "true" *) wire [1:0]\^m_axi_awburst ;
  (* RTL_KEEP = "true" *) wire [7:0]m_axi_awlen;
  (* RTL_KEEP = "true" *) wire m_axi_awready;
  (* RTL_KEEP = "true" *) wire [2:0]\^m_axi_awsize ;
  (* RTL_KEEP = "true" *) wire m_axi_awvalid;
  (* RTL_KEEP = "true" *) wire [3:0]m_axi_bid;
  (* RTL_KEEP = "true" *) wire m_axi_bready;
  (* RTL_KEEP = "true" *) wire [1:0]m_axi_bresp;
  (* RTL_KEEP = "true" *) wire m_axi_bvalid;
  (* RTL_KEEP = "true" *) wire [63:0]m_axi_rdata;
  (* RTL_KEEP = "true" *) wire [3:0]m_axi_rid;
  (* RTL_KEEP = "true" *) wire m_axi_rlast;
  (* RTL_KEEP = "true" *) wire m_axi_rready;
  (* RTL_KEEP = "true" *) wire [1:0]m_axi_rresp;
  (* RTL_KEEP = "true" *) wire m_axi_rvalid;
  (* RTL_KEEP = "true" *) wire [63:0]m_axi_wdata;
  (* RTL_KEEP = "true" *) wire m_axi_wlast;
  (* RTL_KEEP = "true" *) wire m_axi_wready;
  (* RTL_KEEP = "true" *) wire [7:0]m_axi_wstrb;
  (* RTL_KEEP = "true" *) wire m_axi_wvalid;
  (* RTL_KEEP = "true" *) wire [63:0]m_axib_araddr_temp;
  (* RTL_KEEP = "true" *) wire [7:0]m_axib_arlen;
  (* RTL_KEEP = "true" *) wire [2:0]\^m_axib_arprot ;
  (* RTL_KEEP = "true" *) wire m_axib_arready;
  (* RTL_KEEP = "true" *) wire [2:0]\^m_axib_arsize ;
  (* RTL_KEEP = "true" *) wire m_axib_arvalid;
  (* RTL_KEEP = "true" *) wire [63:0]m_axib_awaddr_temp;
  (* RTL_KEEP = "true" *) wire [7:0]m_axib_awlen;
  (* RTL_KEEP = "true" *) wire [2:0]\^m_axib_awprot ;
  (* RTL_KEEP = "true" *) wire m_axib_awready;
  (* RTL_KEEP = "true" *) wire [2:0]\^m_axib_awsize ;
  (* RTL_KEEP = "true" *) wire m_axib_awvalid;
  (* RTL_KEEP = "true" *) wire [3:0]m_axib_bid;
  (* RTL_KEEP = "true" *) wire m_axib_bready;
  (* RTL_KEEP = "true" *) wire [1:0]m_axib_bresp;
  (* RTL_KEEP = "true" *) wire m_axib_bvalid;
  (* RTL_KEEP = "true" *) wire [63:0]m_axib_rdata;
  (* RTL_KEEP = "true" *) wire [3:0]m_axib_rid;
  (* RTL_KEEP = "true" *) wire m_axib_rlast;
  (* RTL_KEEP = "true" *) wire m_axib_rready;
  (* RTL_KEEP = "true" *) wire [1:0]m_axib_rresp;
  (* RTL_KEEP = "true" *) wire m_axib_rvalid;
  (* RTL_KEEP = "true" *) wire [63:0]m_axib_wdata;
  (* RTL_KEEP = "true" *) wire m_axib_wlast;
  (* RTL_KEEP = "true" *) wire m_axib_wready;
  (* RTL_KEEP = "true" *) wire [7:0]m_axib_wstrb;
  (* RTL_KEEP = "true" *) wire m_axib_wvalid;
  wire [63:0]m_axis_rx_tdata_o;
  wire [7:4]\^m_axis_rx_tkeep_o ;
  wire m_axis_rx_tlast_o;
  wire m_axis_rx_tready_i;
  wire [21:0]\^m_axis_rx_tuser_o ;
  wire m_axis_rx_tvalid_o;
  wire [8:0]\mi_c2h0_dat\.radr ;
  wire [63:0]\mi_c2h0_dat\.rdat ;
  wire [8:0]\mi_c2h0_dat\.wadr ;
  wire [63:0]\mi_c2h0_dat\.wdat ;
  wire [1:0]\mi_c2h0_dat\.wen ;
  wire [8:0]\mi_c2h_pcie_dsc_cpld\.radr ;
  wire [63:0]\mi_c2h_pcie_dsc_cpld\.rdat ;
  wire [8:0]\mi_c2h_pcie_dsc_cpld\.wadr ;
  wire [63:0]\mi_c2h_pcie_dsc_cpld\.wdat ;
  wire [0:0]\mi_c2h_pcie_dsc_cpld\.wen ;
  wire [8:0]\mi_h2c0_dat\.radr ;
  wire [63:0]\mi_h2c0_dat\.rdat ;
  wire [8:0]\mi_h2c0_dat\.wadr ;
  wire [63:0]\mi_h2c0_dat\.wdat ;
  wire [1:0]\mi_h2c0_dat\.wen ;
  wire [7:0]\mi_h2c0_dat\.wpar ;
  wire [8:0]\mi_h2c_rd_brg_dat\.radr ;
  wire [63:0]\mi_h2c_rd_brg_dat\.rdat ;
  wire [8:0]\mi_h2c_rd_brg_dat\.wadr ;
  wire [63:0]\mi_h2c_rd_brg_dat\.wdat ;
  wire [0:0]\mi_h2c_rd_brg_dat\.wen ;
  wire [8:0]\mi_h2c_wr_brg_dat\.radr ;
  wire [63:0]\mi_h2c_wr_brg_dat\.rdat ;
  wire [7:0]\mi_h2c_wr_brg_dat\.rpar ;
  wire [8:0]\mi_h2c_wr_brg_dat\.wadr ;
  wire [63:0]\mi_h2c_wr_brg_dat\.wdat ;
  wire [0:0]\mi_h2c_wr_brg_dat\.wen ;
  (* RTL_KEEP = "true" *) wire msi_enable;
  (* RTL_KEEP = "true" *) wire [2:0]msi_vector_width;
  (* RTL_KEEP = "true" *) wire n_0_0;
  (* RTL_KEEP = "true" *) wire n_0_1;
  (* RTL_KEEP = "true" *) wire n_0_100;
  (* RTL_KEEP = "true" *) wire n_0_101;
  (* RTL_KEEP = "true" *) wire n_0_102;
  (* RTL_KEEP = "true" *) wire n_0_103;
  (* RTL_KEEP = "true" *) wire n_0_104;
  (* RTL_KEEP = "true" *) wire n_0_105;
  (* RTL_KEEP = "true" *) wire n_0_106;
  (* RTL_KEEP = "true" *) wire n_0_107;
  (* RTL_KEEP = "true" *) wire n_0_108;
  (* RTL_KEEP = "true" *) wire n_0_109;
  (* RTL_KEEP = "true" *) wire n_0_110;
  (* RTL_KEEP = "true" *) wire n_0_111;
  (* RTL_KEEP = "true" *) wire n_0_112;
  (* RTL_KEEP = "true" *) wire n_0_113;
  (* RTL_KEEP = "true" *) wire n_0_114;
  (* RTL_KEEP = "true" *) wire n_0_115;
  (* RTL_KEEP = "true" *) wire n_0_116;
  (* RTL_KEEP = "true" *) wire n_0_117;
  (* RTL_KEEP = "true" *) wire n_0_118;
  (* RTL_KEEP = "true" *) wire n_0_119;
  (* RTL_KEEP = "true" *) wire n_0_120;
  (* RTL_KEEP = "true" *) wire n_0_121;
  (* RTL_KEEP = "true" *) wire n_0_122;
  (* RTL_KEEP = "true" *) wire n_0_123;
  (* RTL_KEEP = "true" *) wire n_0_124;
  (* RTL_KEEP = "true" *) wire n_0_125;
  (* RTL_KEEP = "true" *) wire n_0_126;
  (* RTL_KEEP = "true" *) wire n_0_127;
  (* RTL_KEEP = "true" *) wire n_0_128;
  (* RTL_KEEP = "true" *) wire n_0_129;
  (* RTL_KEEP = "true" *) wire n_0_130;
  (* RTL_KEEP = "true" *) wire n_0_131;
  (* RTL_KEEP = "true" *) wire n_0_132;
  (* RTL_KEEP = "true" *) wire n_0_133;
  (* RTL_KEEP = "true" *) wire n_0_134;
  (* RTL_KEEP = "true" *) wire n_0_135;
  (* RTL_KEEP = "true" *) wire n_0_136;
  (* RTL_KEEP = "true" *) wire n_0_137;
  (* RTL_KEEP = "true" *) wire n_0_138;
  (* RTL_KEEP = "true" *) wire n_0_139;
  (* RTL_KEEP = "true" *) wire n_0_140;
  (* RTL_KEEP = "true" *) wire n_0_141;
  (* RTL_KEEP = "true" *) wire n_0_142;
  (* RTL_KEEP = "true" *) wire n_0_143;
  (* RTL_KEEP = "true" *) wire n_0_16;
  (* RTL_KEEP = "true" *) wire n_0_17;
  (* RTL_KEEP = "true" *) wire n_0_177;
  (* RTL_KEEP = "true" *) wire n_0_178;
  (* RTL_KEEP = "true" *) wire n_0_179;
  (* RTL_KEEP = "true" *) wire n_0_18;
  (* RTL_KEEP = "true" *) wire n_0_180;
  (* RTL_KEEP = "true" *) wire n_0_181;
  (* RTL_KEEP = "true" *) wire n_0_182;
  (* RTL_KEEP = "true" *) wire n_0_183;
  (* RTL_KEEP = "true" *) wire n_0_184;
  (* RTL_KEEP = "true" *) wire n_0_185;
  (* RTL_KEEP = "true" *) wire n_0_186;
  (* RTL_KEEP = "true" *) wire n_0_187;
  (* RTL_KEEP = "true" *) wire n_0_188;
  (* RTL_KEEP = "true" *) wire n_0_189;
  (* RTL_KEEP = "true" *) wire n_0_19;
  (* RTL_KEEP = "true" *) wire n_0_190;
  (* RTL_KEEP = "true" *) wire n_0_191;
  (* RTL_KEEP = "true" *) wire n_0_192;
  (* RTL_KEEP = "true" *) wire n_0_193;
  (* RTL_KEEP = "true" *) wire n_0_194;
  (* RTL_KEEP = "true" *) wire n_0_195;
  (* RTL_KEEP = "true" *) wire n_0_196;
  (* RTL_KEEP = "true" *) wire n_0_197;
  (* RTL_KEEP = "true" *) wire n_0_198;
  (* RTL_KEEP = "true" *) wire n_0_199;
  (* RTL_KEEP = "true" *) wire n_0_20;
  (* RTL_KEEP = "true" *) wire n_0_200;
  (* RTL_KEEP = "true" *) wire n_0_201;
  (* RTL_KEEP = "true" *) wire n_0_202;
  (* RTL_KEEP = "true" *) wire n_0_203;
  (* RTL_KEEP = "true" *) wire n_0_204;
  (* RTL_KEEP = "true" *) wire n_0_205;
  (* RTL_KEEP = "true" *) wire n_0_206;
  (* RTL_KEEP = "true" *) wire n_0_207;
  (* RTL_KEEP = "true" *) wire n_0_208;
  (* RTL_KEEP = "true" *) wire n_0_209;
  (* RTL_KEEP = "true" *) wire n_0_21;
  (* RTL_KEEP = "true" *) wire n_0_210;
  (* RTL_KEEP = "true" *) wire n_0_211;
  (* RTL_KEEP = "true" *) wire n_0_212;
  (* RTL_KEEP = "true" *) wire n_0_213;
  (* RTL_KEEP = "true" *) wire n_0_214;
  (* RTL_KEEP = "true" *) wire n_0_215;
  (* RTL_KEEP = "true" *) wire n_0_216;
  (* RTL_KEEP = "true" *) wire n_0_217;
  (* RTL_KEEP = "true" *) wire n_0_218;
  (* RTL_KEEP = "true" *) wire n_0_219;
  (* RTL_KEEP = "true" *) wire n_0_22;
  (* RTL_KEEP = "true" *) wire n_0_220;
  (* RTL_KEEP = "true" *) wire n_0_221;
  (* RTL_KEEP = "true" *) wire n_0_222;
  (* RTL_KEEP = "true" *) wire n_0_223;
  (* RTL_KEEP = "true" *) wire n_0_224;
  (* RTL_KEEP = "true" *) wire n_0_225;
  (* RTL_KEEP = "true" *) wire n_0_226;
  (* RTL_KEEP = "true" *) wire n_0_227;
  (* RTL_KEEP = "true" *) wire n_0_228;
  (* RTL_KEEP = "true" *) wire n_0_229;
  (* RTL_KEEP = "true" *) wire n_0_23;
  (* RTL_KEEP = "true" *) wire n_0_230;
  (* RTL_KEEP = "true" *) wire n_0_231;
  (* RTL_KEEP = "true" *) wire n_0_232;
  (* RTL_KEEP = "true" *) wire n_0_233;
  (* RTL_KEEP = "true" *) wire n_0_234;
  (* RTL_KEEP = "true" *) wire n_0_235;
  (* RTL_KEEP = "true" *) wire n_0_236;
  (* RTL_KEEP = "true" *) wire n_0_237;
  (* RTL_KEEP = "true" *) wire n_0_238;
  (* RTL_KEEP = "true" *) wire n_0_239;
  (* RTL_KEEP = "true" *) wire n_0_240;
  (* RTL_KEEP = "true" *) wire n_0_241;
  (* RTL_KEEP = "true" *) wire n_0_242;
  (* RTL_KEEP = "true" *) wire n_0_243;
  (* RTL_KEEP = "true" *) wire n_0_244;
  (* RTL_KEEP = "true" *) wire n_0_245;
  (* RTL_KEEP = "true" *) wire n_0_246;
  (* RTL_KEEP = "true" *) wire n_0_247;
  (* RTL_KEEP = "true" *) wire n_0_248;
  (* RTL_KEEP = "true" *) wire n_0_249;
  (* RTL_KEEP = "true" *) wire n_0_250;
  (* RTL_KEEP = "true" *) wire n_0_251;
  (* RTL_KEEP = "true" *) wire n_0_252;
  (* RTL_KEEP = "true" *) wire n_0_253;
  (* RTL_KEEP = "true" *) wire n_0_254;
  (* RTL_KEEP = "true" *) wire n_0_255;
  (* RTL_KEEP = "true" *) wire n_0_256;
  (* RTL_KEEP = "true" *) wire n_0_257;
  (* RTL_KEEP = "true" *) wire n_0_258;
  (* RTL_KEEP = "true" *) wire n_0_259;
  (* RTL_KEEP = "true" *) wire n_0_260;
  (* RTL_KEEP = "true" *) wire n_0_261;
  (* RTL_KEEP = "true" *) wire n_0_262;
  (* RTL_KEEP = "true" *) wire n_0_263;
  (* RTL_KEEP = "true" *) wire n_0_264;
  (* RTL_KEEP = "true" *) wire n_0_265;
  (* RTL_KEEP = "true" *) wire n_0_266;
  (* RTL_KEEP = "true" *) wire n_0_267;
  (* RTL_KEEP = "true" *) wire n_0_268;
  (* RTL_KEEP = "true" *) wire n_0_269;
  (* RTL_KEEP = "true" *) wire n_0_270;
  (* RTL_KEEP = "true" *) wire n_0_271;
  (* RTL_KEEP = "true" *) wire n_0_272;
  (* RTL_KEEP = "true" *) wire n_0_273;
  (* RTL_KEEP = "true" *) wire n_0_274;
  (* RTL_KEEP = "true" *) wire n_0_275;
  (* RTL_KEEP = "true" *) wire n_0_276;
  (* RTL_KEEP = "true" *) wire n_0_277;
  (* RTL_KEEP = "true" *) wire n_0_278;
  (* RTL_KEEP = "true" *) wire n_0_279;
  (* RTL_KEEP = "true" *) wire n_0_280;
  (* RTL_KEEP = "true" *) wire n_0_281;
  (* RTL_KEEP = "true" *) wire n_0_282;
  (* RTL_KEEP = "true" *) wire n_0_283;
  (* RTL_KEEP = "true" *) wire n_0_284;
  (* RTL_KEEP = "true" *) wire n_0_285;
  (* RTL_KEEP = "true" *) wire n_0_286;
  (* RTL_KEEP = "true" *) wire n_0_287;
  (* RTL_KEEP = "true" *) wire n_0_288;
  (* RTL_KEEP = "true" *) wire n_0_289;
  (* RTL_KEEP = "true" *) wire n_0_290;
  (* RTL_KEEP = "true" *) wire n_0_291;
  (* RTL_KEEP = "true" *) wire n_0_292;
  (* RTL_KEEP = "true" *) wire n_0_293;
  (* RTL_KEEP = "true" *) wire n_0_294;
  (* RTL_KEEP = "true" *) wire n_0_295;
  (* RTL_KEEP = "true" *) wire n_0_296;
  (* RTL_KEEP = "true" *) wire n_0_297;
  (* RTL_KEEP = "true" *) wire n_0_298;
  (* RTL_KEEP = "true" *) wire n_0_299;
  (* RTL_KEEP = "true" *) wire n_0_300;
  (* RTL_KEEP = "true" *) wire n_0_301;
  (* RTL_KEEP = "true" *) wire n_0_302;
  (* RTL_KEEP = "true" *) wire n_0_303;
  (* RTL_KEEP = "true" *) wire n_0_304;
  (* RTL_KEEP = "true" *) wire n_0_305;
  (* RTL_KEEP = "true" *) wire n_0_306;
  (* RTL_KEEP = "true" *) wire n_0_307;
  (* RTL_KEEP = "true" *) wire n_0_308;
  (* RTL_KEEP = "true" *) wire n_0_309;
  (* RTL_KEEP = "true" *) wire n_0_310;
  (* RTL_KEEP = "true" *) wire n_0_311;
  (* RTL_KEEP = "true" *) wire n_0_312;
  (* RTL_KEEP = "true" *) wire n_0_313;
  (* RTL_KEEP = "true" *) wire n_0_314;
  (* RTL_KEEP = "true" *) wire n_0_315;
  (* RTL_KEEP = "true" *) wire n_0_316;
  (* RTL_KEEP = "true" *) wire n_0_317;
  (* RTL_KEEP = "true" *) wire n_0_318;
  (* RTL_KEEP = "true" *) wire n_0_319;
  (* RTL_KEEP = "true" *) wire n_0_320;
  (* RTL_KEEP = "true" *) wire n_0_321;
  (* RTL_KEEP = "true" *) wire n_0_322;
  (* RTL_KEEP = "true" *) wire n_0_323;
  (* RTL_KEEP = "true" *) wire n_0_324;
  (* RTL_KEEP = "true" *) wire n_0_325;
  (* RTL_KEEP = "true" *) wire n_0_326;
  (* RTL_KEEP = "true" *) wire n_0_327;
  (* RTL_KEEP = "true" *) wire n_0_328;
  (* RTL_KEEP = "true" *) wire n_0_329;
  (* RTL_KEEP = "true" *) wire n_0_330;
  (* RTL_KEEP = "true" *) wire n_0_331;
  (* RTL_KEEP = "true" *) wire n_0_332;
  (* RTL_KEEP = "true" *) wire n_0_333;
  (* RTL_KEEP = "true" *) wire n_0_334;
  (* RTL_KEEP = "true" *) wire n_0_335;
  (* RTL_KEEP = "true" *) wire n_0_336;
  (* RTL_KEEP = "true" *) wire n_0_337;
  (* RTL_KEEP = "true" *) wire n_0_338;
  (* RTL_KEEP = "true" *) wire n_0_339;
  (* RTL_KEEP = "true" *) wire n_0_340;
  (* RTL_KEEP = "true" *) wire n_0_397;
  (* RTL_KEEP = "true" *) wire n_0_398;
  (* RTL_KEEP = "true" *) wire n_0_399;
  (* RTL_KEEP = "true" *) wire n_0_400;
  (* RTL_KEEP = "true" *) wire n_0_401;
  (* RTL_KEEP = "true" *) wire n_0_402;
  (* RTL_KEEP = "true" *) wire n_0_403;
  (* RTL_KEEP = "true" *) wire n_0_404;
  (* RTL_KEEP = "true" *) wire n_0_405;
  (* RTL_KEEP = "true" *) wire n_0_406;
  (* RTL_KEEP = "true" *) wire n_0_407;
  (* RTL_KEEP = "true" *) wire n_0_408;
  (* RTL_KEEP = "true" *) wire n_0_409;
  (* RTL_KEEP = "true" *) wire n_0_410;
  (* RTL_KEEP = "true" *) wire n_0_411;
  (* RTL_KEEP = "true" *) wire n_0_412;
  (* RTL_KEEP = "true" *) wire n_0_413;
  (* RTL_KEEP = "true" *) wire n_0_414;
  (* RTL_KEEP = "true" *) wire n_0_415;
  (* RTL_KEEP = "true" *) wire n_0_416;
  (* RTL_KEEP = "true" *) wire n_0_417;
  (* RTL_KEEP = "true" *) wire n_0_418;
  (* RTL_KEEP = "true" *) wire n_0_419;
  (* RTL_KEEP = "true" *) wire n_0_42;
  (* RTL_KEEP = "true" *) wire n_0_420;
  (* RTL_KEEP = "true" *) wire n_0_421;
  (* RTL_KEEP = "true" *) wire n_0_422;
  (* RTL_KEEP = "true" *) wire n_0_423;
  (* RTL_KEEP = "true" *) wire n_0_424;
  (* RTL_KEEP = "true" *) wire n_0_425;
  (* RTL_KEEP = "true" *) wire n_0_426;
  (* RTL_KEEP = "true" *) wire n_0_427;
  (* RTL_KEEP = "true" *) wire n_0_428;
  (* RTL_KEEP = "true" *) wire n_0_429;
  (* RTL_KEEP = "true" *) wire n_0_43;
  (* RTL_KEEP = "true" *) wire n_0_430;
  (* RTL_KEEP = "true" *) wire n_0_431;
  (* RTL_KEEP = "true" *) wire n_0_432;
  (* RTL_KEEP = "true" *) wire n_0_433;
  (* RTL_KEEP = "true" *) wire n_0_434;
  (* RTL_KEEP = "true" *) wire n_0_435;
  (* RTL_KEEP = "true" *) wire n_0_436;
  (* RTL_KEEP = "true" *) wire n_0_437;
  (* RTL_KEEP = "true" *) wire n_0_438;
  (* RTL_KEEP = "true" *) wire n_0_439;
  (* RTL_KEEP = "true" *) wire n_0_44;
  (* RTL_KEEP = "true" *) wire n_0_440;
  (* RTL_KEEP = "true" *) wire n_0_441;
  (* RTL_KEEP = "true" *) wire n_0_442;
  (* RTL_KEEP = "true" *) wire n_0_443;
  (* RTL_KEEP = "true" *) wire n_0_444;
  (* RTL_KEEP = "true" *) wire n_0_445;
  (* RTL_KEEP = "true" *) wire n_0_446;
  (* RTL_KEEP = "true" *) wire n_0_447;
  (* RTL_KEEP = "true" *) wire n_0_448;
  (* RTL_KEEP = "true" *) wire n_0_449;
  (* RTL_KEEP = "true" *) wire n_0_45;
  (* RTL_KEEP = "true" *) wire n_0_450;
  (* RTL_KEEP = "true" *) wire n_0_451;
  (* RTL_KEEP = "true" *) wire n_0_452;
  (* RTL_KEEP = "true" *) wire n_0_453;
  (* RTL_KEEP = "true" *) wire n_0_454;
  (* RTL_KEEP = "true" *) wire n_0_455;
  (* RTL_KEEP = "true" *) wire n_0_456;
  (* RTL_KEEP = "true" *) wire n_0_457;
  (* RTL_KEEP = "true" *) wire n_0_458;
  (* RTL_KEEP = "true" *) wire n_0_459;
  (* RTL_KEEP = "true" *) wire n_0_46;
  (* RTL_KEEP = "true" *) wire n_0_460;
  (* RTL_KEEP = "true" *) wire n_0_461;
  (* RTL_KEEP = "true" *) wire n_0_462;
  (* RTL_KEEP = "true" *) wire n_0_463;
  (* RTL_KEEP = "true" *) wire n_0_464;
  (* RTL_KEEP = "true" *) wire n_0_465;
  (* RTL_KEEP = "true" *) wire n_0_466;
  (* RTL_KEEP = "true" *) wire n_0_467;
  (* RTL_KEEP = "true" *) wire n_0_468;
  (* RTL_KEEP = "true" *) wire n_0_469;
  (* RTL_KEEP = "true" *) wire n_0_47;
  (* RTL_KEEP = "true" *) wire n_0_470;
  (* RTL_KEEP = "true" *) wire n_0_471;
  (* RTL_KEEP = "true" *) wire n_0_472;
  (* RTL_KEEP = "true" *) wire n_0_473;
  (* RTL_KEEP = "true" *) wire n_0_474;
  (* RTL_KEEP = "true" *) wire n_0_475;
  (* RTL_KEEP = "true" *) wire n_0_476;
  (* RTL_KEEP = "true" *) wire n_0_477;
  (* RTL_KEEP = "true" *) wire n_0_478;
  (* RTL_KEEP = "true" *) wire n_0_479;
  (* RTL_KEEP = "true" *) wire n_0_48;
  (* RTL_KEEP = "true" *) wire n_0_480;
  (* RTL_KEEP = "true" *) wire n_0_481;
  (* RTL_KEEP = "true" *) wire n_0_482;
  (* RTL_KEEP = "true" *) wire n_0_49;
  (* RTL_KEEP = "true" *) wire n_0_62;
  (* RTL_KEEP = "true" *) wire n_0_63;
  (* RTL_KEEP = "true" *) wire n_0_64;
  (* RTL_KEEP = "true" *) wire n_0_65;
  (* RTL_KEEP = "true" *) wire n_0_66;
  (* RTL_KEEP = "true" *) wire n_0_67;
  (* RTL_KEEP = "true" *) wire n_0_68;
  (* RTL_KEEP = "true" *) wire n_0_69;
  (* RTL_KEEP = "true" *) wire n_0_78;
  (* RTL_KEEP = "true" *) wire n_0_79;
  (* RTL_KEEP = "true" *) wire n_0_80;
  (* RTL_KEEP = "true" *) wire n_0_81;
  (* RTL_KEEP = "true" *) wire n_0_82;
  (* RTL_KEEP = "true" *) wire n_0_83;
  (* RTL_KEEP = "true" *) wire n_0_84;
  (* RTL_KEEP = "true" *) wire n_0_85;
  (* RTL_KEEP = "true" *) wire n_0_86;
  (* RTL_KEEP = "true" *) wire n_0_87;
  (* RTL_KEEP = "true" *) wire n_0_88;
  (* RTL_KEEP = "true" *) wire n_0_89;
  (* RTL_KEEP = "true" *) wire n_0_90;
  (* RTL_KEEP = "true" *) wire n_0_91;
  (* RTL_KEEP = "true" *) wire n_0_92;
  (* RTL_KEEP = "true" *) wire n_0_93;
  (* RTL_KEEP = "true" *) wire n_0_94;
  (* RTL_KEEP = "true" *) wire n_0_95;
  (* RTL_KEEP = "true" *) wire n_0_96;
  (* RTL_KEEP = "true" *) wire n_0_97;
  (* RTL_KEEP = "true" *) wire n_0_98;
  (* RTL_KEEP = "true" *) wire n_0_99;
  (* RTL_KEEP = "true" *) wire [1:0]pci_exp_rxn;
  (* RTL_KEEP = "true" *) wire [1:0]pci_exp_rxp;
  (* RTL_KEEP = "true" *) wire [1:0]pci_exp_txn;
  (* RTL_KEEP = "true" *) wire [1:0]pci_exp_txp;
  wire [7:0]\pcie_dma_in\.cfg_fc_nph ;
  wire \pcie_dma_in\.cfg_interrupt_sent ;
  wire \pcie_dma_in\.cfg_phy_link_down ;
  wire [3:0]\pcie_dma_in\.pcie_rq_seq_num0 ;
  wire \pcie_dma_in\.pcie_rq_seq_num_vld0 ;
  wire \pcie_dma_out\.pcie_cq_np_req ;
  wire pl_directed_link_auton_i;
  wire [1:0]pl_directed_link_change_i;
  wire pl_directed_link_speed_i;
  wire [1:0]pl_directed_link_width_i;
  wire pl_upstream_prefer_deemph_i;
  wire rx_np_ok_i;
  wire rx_np_req_i;
  wire [63:0]s_axis_tx_tdata_i;
  wire [7:0]s_axis_tx_tkeep_i;
  wire s_axis_tx_tlast_i;
  wire s_axis_tx_tready_o;
  wire [3:0]s_axis_tx_tuser_i;
  wire s_axis_tx_tvalid_i;
  (* RTL_KEEP = "true" *) wire sys_clk;
  (* RTL_KEEP = "true" *) wire sys_rst_n;
  (* async_reg = "true" *) wire sys_rst_n_reg;
  (* async_reg = "true" *) wire sys_rst_n_reg2;
  wire sys_rst_n_reg_i_1_n_0;
  wire tx_cfg_gnt_i;
  wire udma_wrapper_n_10730;
  wire udma_wrapper_n_10731;
  wire udma_wrapper_n_10732;
  wire udma_wrapper_n_10733;
  wire udma_wrapper_n_10734;
  wire udma_wrapper_n_10735;
  wire udma_wrapper_n_10736;
  wire udma_wrapper_n_10737;
  wire udma_wrapper_n_10738;
  wire udma_wrapper_n_10739;
  wire udma_wrapper_n_10740;
  wire udma_wrapper_n_10741;
  wire udma_wrapper_n_10742;
  wire udma_wrapper_n_10743;
  wire udma_wrapper_n_10744;
  wire udma_wrapper_n_10745;
  wire udma_wrapper_n_10746;
  wire udma_wrapper_n_10747;
  wire udma_wrapper_n_10748;
  wire udma_wrapper_n_10749;
  wire udma_wrapper_n_10750;
  wire udma_wrapper_n_10751;
  wire udma_wrapper_n_10752;
  wire udma_wrapper_n_10753;
  wire udma_wrapper_n_10754;
  wire udma_wrapper_n_10755;
  wire udma_wrapper_n_10756;
  wire udma_wrapper_n_10757;
  wire udma_wrapper_n_10758;
  wire udma_wrapper_n_10759;
  wire udma_wrapper_n_10760;
  wire udma_wrapper_n_10761;
  wire udma_wrapper_n_10762;
  wire udma_wrapper_n_10763;
  wire udma_wrapper_n_10764;
  wire udma_wrapper_n_10765;
  wire udma_wrapper_n_10766;
  wire udma_wrapper_n_10767;
  wire udma_wrapper_n_10768;
  wire udma_wrapper_n_10769;
  wire udma_wrapper_n_10770;
  wire udma_wrapper_n_10771;
  wire udma_wrapper_n_10772;
  wire udma_wrapper_n_10773;
  wire udma_wrapper_n_10774;
  wire udma_wrapper_n_10775;
  wire udma_wrapper_n_10776;
  wire udma_wrapper_n_10777;
  wire udma_wrapper_n_10778;
  wire udma_wrapper_n_10779;
  wire udma_wrapper_n_10780;
  wire udma_wrapper_n_10781;
  wire udma_wrapper_n_10782;
  wire udma_wrapper_n_10783;
  wire udma_wrapper_n_10784;
  wire udma_wrapper_n_10785;
  wire udma_wrapper_n_10786;
  wire udma_wrapper_n_10787;
  wire udma_wrapper_n_10788;
  wire udma_wrapper_n_10789;
  wire udma_wrapper_n_10790;
  wire udma_wrapper_n_10791;
  wire udma_wrapper_n_10792;
  wire udma_wrapper_n_10793;
  wire udma_wrapper_n_10794;
  wire udma_wrapper_n_10827;
  wire udma_wrapper_n_10828;
  wire udma_wrapper_n_10829;
  wire udma_wrapper_n_10830;
  wire udma_wrapper_n_10847;
  wire udma_wrapper_n_10848;
  wire udma_wrapper_n_10849;
  wire udma_wrapper_n_10850;
  wire udma_wrapper_n_10851;
  wire udma_wrapper_n_10852;
  wire udma_wrapper_n_10853;
  wire udma_wrapper_n_10854;
  wire udma_wrapper_n_10857;
  wire udma_wrapper_n_10858;
  wire udma_wrapper_n_10859;
  wire udma_wrapper_n_10860;
  wire udma_wrapper_n_10861;
  wire udma_wrapper_n_10862;
  wire udma_wrapper_n_10863;
  wire udma_wrapper_n_10864;
  wire udma_wrapper_n_10865;
  wire udma_wrapper_n_10866;
  wire udma_wrapper_n_10867;
  wire udma_wrapper_n_10868;
  wire udma_wrapper_n_10869;
  wire udma_wrapper_n_10870;
  wire udma_wrapper_n_10871;
  wire udma_wrapper_n_10872;
  wire udma_wrapper_n_10873;
  wire udma_wrapper_n_10874;
  wire udma_wrapper_n_10875;
  wire udma_wrapper_n_10876;
  wire udma_wrapper_n_10877;
  wire udma_wrapper_n_10878;
  wire udma_wrapper_n_10879;
  wire udma_wrapper_n_10880;
  wire udma_wrapper_n_10881;
  wire udma_wrapper_n_10882;
  wire udma_wrapper_n_10883;
  wire udma_wrapper_n_10884;
  wire udma_wrapper_n_10885;
  wire udma_wrapper_n_10886;
  wire udma_wrapper_n_10887;
  wire udma_wrapper_n_10888;
  wire udma_wrapper_n_10889;
  wire udma_wrapper_n_10890;
  wire udma_wrapper_n_10891;
  wire udma_wrapper_n_10892;
  wire udma_wrapper_n_10893;
  wire udma_wrapper_n_10894;
  wire udma_wrapper_n_10895;
  wire udma_wrapper_n_10896;
  wire udma_wrapper_n_10897;
  wire udma_wrapper_n_10898;
  wire udma_wrapper_n_10899;
  wire udma_wrapper_n_10900;
  wire udma_wrapper_n_10901;
  wire udma_wrapper_n_10902;
  wire udma_wrapper_n_10903;
  wire udma_wrapper_n_10904;
  wire udma_wrapper_n_10905;
  wire udma_wrapper_n_10906;
  wire udma_wrapper_n_10907;
  wire udma_wrapper_n_10908;
  wire udma_wrapper_n_10909;
  wire udma_wrapper_n_10910;
  wire udma_wrapper_n_10911;
  wire udma_wrapper_n_10912;
  wire udma_wrapper_n_10913;
  wire udma_wrapper_n_10914;
  wire udma_wrapper_n_10915;
  wire udma_wrapper_n_10916;
  wire udma_wrapper_n_10917;
  wire udma_wrapper_n_10918;
  wire udma_wrapper_n_10919;
  wire udma_wrapper_n_10920;
  wire udma_wrapper_n_10921;
  wire udma_wrapper_n_10955;
  wire udma_wrapper_n_10958;
  wire udma_wrapper_n_11002;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12224;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12225;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12226;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12227;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12228;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12229;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12230;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12231;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12591;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12592;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12593;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12594;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12595;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12596;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12597;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12598;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12599;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12600;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12601;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12602;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12603;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12604;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12605;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12606;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12607;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12608;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12609;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12610;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12611;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12612;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12613;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12614;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12615;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12616;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12617;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12618;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12619;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12620;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12621;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12622;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12635;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12636;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12637;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12638;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12639;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12640;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12641;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12642;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12643;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12644;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12645;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12646;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12647;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12648;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12649;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12650;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12651;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12652;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12653;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12654;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12655;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12656;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12657;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12658;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12659;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12660;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12661;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12662;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12663;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12664;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12665;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12666;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12667;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12668;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12669;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12670;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12673;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12674;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12675;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12676;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12677;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12678;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12679;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12680;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12681;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12682;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12683;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12684;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12685;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12686;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12687;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12688;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12689;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12690;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12691;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12692;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12693;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12694;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12695;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12696;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12697;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12698;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12699;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12700;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12701;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12702;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12703;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12704;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12718;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12719;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12720;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12723;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12724;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12725;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12726;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12727;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12728;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12729;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12730;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12731;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12732;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12733;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12734;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12735;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12736;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12737;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12738;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12739;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12740;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12741;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12742;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12743;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12744;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12745;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12746;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12747;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12748;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12749;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12750;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12751;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12752;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12753;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12754;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12755;
  (* RTL_KEEP = "true" *) wire udma_wrapper_n_12758;
  (* RTL_KEEP = "true" *) wire user_lnk_up;
  (* RTL_KEEP = "true" *) wire [0:0]usr_irq_ack;
  (* RTL_KEEP = "true" *) wire [0:0]usr_irq_req;
  (* RTL_KEEP = "true" *) wire \xdma_0_cfg_sideband_i/p_9_in ;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_133;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_134;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_135;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_136;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_137;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_138;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_167;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_168;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_170;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_171;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_172;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_173;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_174;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_175;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_176;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_177;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_178;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_179;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_180;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_181;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_182;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_183;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_184;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_185;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_186;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_187;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_188;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_189;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_190;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_191;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_192;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_193;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_194;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_195;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_196;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_197;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_198;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_199;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_200;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_201;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_202;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_203;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_204;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_205;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_206;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_207;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_208;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_209;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_210;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_211;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_212;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_213;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_214;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_215;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_216;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_217;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_218;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_219;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_220;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_221;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_222;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_223;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_224;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_225;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_226;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_227;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_228;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_229;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_230;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_231;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_232;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_233;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_234;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_235;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_236;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_237;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_238;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_239;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_240;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_241;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_242;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_243;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_244;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_245;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_246;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_247;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_248;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_249;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_250;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_251;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_252;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_253;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_254;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_255;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_256;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_257;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_258;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_259;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_260;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_261;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_262;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_263;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_264;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_265;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_266;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_267;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_268;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_269;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_270;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_271;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_272;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_273;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_274;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_275;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_276;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_277;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_278;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_279;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_280;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_281;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_282;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_283;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_284;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_285;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_286;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_287;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_288;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_289;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_290;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_291;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_292;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_293;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_294;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_295;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_296;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_297;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_298;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_299;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_300;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_301;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_302;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_303;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_304;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_305;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_306;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_307;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_308;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_309;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_310;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_311;
  wire xdma_0_pcie2_to_pcie3_wrapper_i_n_312;
  wire \NLW_ram_top_mi_c2h0_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h0_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h1_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h1_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h2_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h2_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h3_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h3_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_axi_dsc_cpld\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_axi_dsc_cpld\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_axi_dsc_cpli\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_axi_dsc_cpli\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_pcie_dsc_cpld\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_pcie_dsc_cpld\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_pcie_dsc_cpli\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_pcie_dsc_cpli\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_rd_brg_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_rd_brg_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_wr_brg_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_c2h_wr_brg_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_dsc_crd_rcv\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_dsc_crd_rcv\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c0_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c0_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c1_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c1_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c2_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c2_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c3_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c3_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_axi_dsc_cpld\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_axi_dsc_cpld\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_axi_dsc_cpli\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_axi_dsc_cpli\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_pcie_dsc_cpld\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_pcie_dsc_cpld\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_pcie_dsc_cpli\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_pcie_dsc_cpli\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_rd_brg_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_rd_brg_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_wr_brg_dat\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_h2c_wr_brg_dat\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_hw_ctxt\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_hw_ctxt\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_sw_ctxt\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_sw_ctxt\.rsbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_wb_base_ctxt\.rdbe_UNCONNECTED ;
  wire \NLW_ram_top_mi_wb_base_ctxt\.rsbe_UNCONNECTED ;
  wire [511:64]\NLW_ram_top_mi_c2h0_dat\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_c2h0_dat\.rpar_UNCONNECTED ;
  wire [511:0]\NLW_ram_top_mi_c2h1_dat\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_c2h1_dat\.rpar_UNCONNECTED ;
  wire [511:0]\NLW_ram_top_mi_c2h2_dat\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_c2h2_dat\.rpar_UNCONNECTED ;
  wire [511:0]\NLW_ram_top_mi_c2h3_dat\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_c2h3_dat\.rpar_UNCONNECTED ;
  wire [511:0]\NLW_ram_top_mi_c2h_axi_dsc_cpld\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_c2h_axi_dsc_cpld\.rpar_UNCONNECTED ;
  wire [79:0]\NLW_ram_top_mi_c2h_axi_dsc_cpli\.rdat_UNCONNECTED ;
  wire [3:0]\NLW_ram_top_mi_c2h_axi_dsc_cpli\.rpar_UNCONNECTED ;
  wire [511:64]\NLW_ram_top_mi_c2h_pcie_dsc_cpld\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_c2h_pcie_dsc_cpld\.rpar_UNCONNECTED ;
  wire [79:0]\NLW_ram_top_mi_c2h_pcie_dsc_cpli\.rdat_UNCONNECTED ;
  wire [3:0]\NLW_ram_top_mi_c2h_pcie_dsc_cpli\.rpar_UNCONNECTED ;
  wire [511:0]\NLW_ram_top_mi_c2h_rd_brg_dat\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_c2h_rd_brg_dat\.rpar_UNCONNECTED ;
  wire [511:0]\NLW_ram_top_mi_c2h_wr_brg_dat\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_c2h_wr_brg_dat\.rpar_UNCONNECTED ;
  wire [15:0]\NLW_ram_top_mi_dsc_crd_rcv\.rdat_UNCONNECTED ;
  wire [1:0]\NLW_ram_top_mi_dsc_crd_rcv\.rpar_UNCONNECTED ;
  wire [511:64]\NLW_ram_top_mi_h2c0_dat\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_h2c0_dat\.rpar_UNCONNECTED ;
  wire [511:0]\NLW_ram_top_mi_h2c1_dat\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_h2c1_dat\.rpar_UNCONNECTED ;
  wire [511:0]\NLW_ram_top_mi_h2c2_dat\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_h2c2_dat\.rpar_UNCONNECTED ;
  wire [511:0]\NLW_ram_top_mi_h2c3_dat\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_h2c3_dat\.rpar_UNCONNECTED ;
  wire [511:0]\NLW_ram_top_mi_h2c_axi_dsc_cpld\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_h2c_axi_dsc_cpld\.rpar_UNCONNECTED ;
  wire [79:0]\NLW_ram_top_mi_h2c_axi_dsc_cpli\.rdat_UNCONNECTED ;
  wire [3:0]\NLW_ram_top_mi_h2c_axi_dsc_cpli\.rpar_UNCONNECTED ;
  wire [511:0]\NLW_ram_top_mi_h2c_pcie_dsc_cpld\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_h2c_pcie_dsc_cpld\.rpar_UNCONNECTED ;
  wire [79:0]\NLW_ram_top_mi_h2c_pcie_dsc_cpli\.rdat_UNCONNECTED ;
  wire [3:0]\NLW_ram_top_mi_h2c_pcie_dsc_cpli\.rpar_UNCONNECTED ;
  wire [511:64]\NLW_ram_top_mi_h2c_rd_brg_dat\.rdat_UNCONNECTED ;
  wire [63:0]\NLW_ram_top_mi_h2c_rd_brg_dat\.rpar_UNCONNECTED ;
  wire [511:64]\NLW_ram_top_mi_h2c_wr_brg_dat\.rdat_UNCONNECTED ;
  wire [63:8]\NLW_ram_top_mi_h2c_wr_brg_dat\.rpar_UNCONNECTED ;
  wire [31:0]\NLW_ram_top_mi_hw_ctxt\.rdat_UNCONNECTED ;
  wire [7:0]\NLW_ram_top_mi_hw_ctxt\.rpar_UNCONNECTED ;
  wire [127:0]\NLW_ram_top_mi_sw_ctxt\.rdat_UNCONNECTED ;
  wire [7:0]\NLW_ram_top_mi_sw_ctxt\.rpar_UNCONNECTED ;
  wire [127:0]\NLW_ram_top_mi_wb_base_ctxt\.rdat_UNCONNECTED ;
  wire [7:0]\NLW_ram_top_mi_wb_base_ctxt\.rpar_UNCONNECTED ;
  wire NLW_udma_wrapper_axi_aresetn_UNCONNECTED;
  wire NLW_udma_wrapper_blk_cfg_ext_read_data_valid_o_UNCONNECTED;
  wire NLW_udma_wrapper_cfg_status_ats_en_UNCONNECTED;
  wire NLW_udma_wrapper_cfg_status_pr_en_UNCONNECTED;
  wire NLW_udma_wrapper_cfg_status_pr_rf_UNCONNECTED;
  wire NLW_udma_wrapper_cfg_status_pr_rst_UNCONNECTED;
  wire NLW_udma_wrapper_cfg_status_pr_uprgi_UNCONNECTED;
  wire \NLW_udma_wrapper_dsc_in\.crd[vld]_UNCONNECTED ;
  wire \NLW_udma_wrapper_dsc_out\.dsc[dir]_UNCONNECTED ;
  wire \NLW_udma_wrapper_dsc_out\.dsc[wbi]_UNCONNECTED ;
  wire \NLW_udma_wrapper_dsc_out\.dsc[wbi_chk]_UNCONNECTED ;
  wire \NLW_udma_wrapper_fabric_out\.c2h_dsc_avail_inc_vld_UNCONNECTED ;
  wire \NLW_udma_wrapper_fabric_out\.flr_clr_UNCONNECTED ;
  wire \NLW_udma_wrapper_fabric_out\.flr_set_UNCONNECTED ;
  wire \NLW_udma_wrapper_fabric_out\.s_axis_c2h_tstat_vld_UNCONNECTED ;
  wire \NLW_udma_wrapper_fabric_out\.usr_irq_fail_UNCONNECTED ;
  wire \NLW_udma_wrapper_fabric_out\.usr_irq_sent_UNCONNECTED ;
  wire NLW_udma_wrapper_h2c_desc_cmd_in_rdy_UNCONNECTED;
  wire NLW_udma_wrapper_h2c_desc_cmd_out_vld_UNCONNECTED;
  wire NLW_udma_wrapper_m_axi_arlock_UNCONNECTED;
  wire NLW_udma_wrapper_m_axi_awlock_UNCONNECTED;
  wire NLW_udma_wrapper_m_axib_arlock_UNCONNECTED;
  wire NLW_udma_wrapper_m_axib_awlock_UNCONNECTED;
  wire NLW_udma_wrapper_m_axil_arvalid_UNCONNECTED;
  wire NLW_udma_wrapper_m_axil_awvalid_UNCONNECTED;
  wire NLW_udma_wrapper_m_axil_bready_UNCONNECTED;
  wire NLW_udma_wrapper_m_axil_rready_UNCONNECTED;
  wire NLW_udma_wrapper_m_axil_wvalid_UNCONNECTED;
  wire NLW_udma_wrapper_m_axis_cq_tlast_UNCONNECTED;
  wire NLW_udma_wrapper_m_axis_cq_tvalid_UNCONNECTED;
  wire \NLW_udma_wrapper_mi_c2h0_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_c2h1_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_c2h2_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_c2h3_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_c2h_rd_brg_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_c2h_wr_brg_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_dsc_crd_rcv\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_dsc_crd_rcv\.wen_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_h2c0_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_h2c1_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_h2c2_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_h2c3_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_h2c_rd_brg_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_h2c_wr_brg_dat\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_hw_ctxt\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_hw_ctxt\.wen_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_sw_ctxt\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_mi_wb_base_ctxt\.ren_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_config_space_enable_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_err_cor_in_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_err_uncor_in_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_ext_read_data_valid_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_hot_reset_in_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_pending_status_data_enable_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_tph_present_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msix_int_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_link_training_enable_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_read_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_type1_cfg_reg_access_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_write_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_msg_transmit_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_per_function_logic_request_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_per_function_output_request_UNCONNECTED ;
  wire \NLW_udma_wrapper_pcie_dma_out\.cfg_vf_flr_done_UNCONNECTED ;
  wire NLW_udma_wrapper_s_axi_arready_UNCONNECTED;
  wire NLW_udma_wrapper_s_axi_awready_UNCONNECTED;
  wire NLW_udma_wrapper_s_axi_bvalid_UNCONNECTED;
  wire NLW_udma_wrapper_s_axi_rlast_UNCONNECTED;
  wire NLW_udma_wrapper_s_axi_rvalid_UNCONNECTED;
  wire NLW_udma_wrapper_s_axi_wready_UNCONNECTED;
  wire NLW_udma_wrapper_s_axis_rq_tready_UNCONNECTED;
  wire NLW_udma_wrapper_user_cfg_ext_read_received_o_UNCONNECTED;
  wire NLW_udma_wrapper_user_cfg_ext_write_received_o_UNCONNECTED;
  wire NLW_udma_wrapper_usr_flr_clr_UNCONNECTED;
  wire NLW_udma_wrapper_usr_flr_set_UNCONNECTED;
  wire NLW_udma_wrapper_usr_irq_fail_UNCONNECTED;
  wire [31:0]NLW_udma_wrapper_blk_cfg_ext_read_data_o_UNCONNECTED;
  wire [12:0]\NLW_udma_wrapper_c2h_desc_avail_inc_num[0]_UNCONNECTED ;
  wire [4:0]\NLW_udma_wrapper_c2h_desc_avail_inc_qid[0]_UNCONNECTED ;
  wire [0:0]NLW_udma_wrapper_c2h_desc_avail_inc_vld_UNCONNECTED;
  wire [0:0]NLW_udma_wrapper_c2h_dsc_byp_ready_UNCONNECTED;
  wire [0:0]NLW_udma_wrapper_c2h_pktin_accept_UNCONNECTED;
  wire [7:0]\NLW_udma_wrapper_c2h_pktin_drop[0]_UNCONNECTED ;
  wire [7:0]NLW_udma_wrapper_c2h_sts_UNCONNECTED;
  wire [4:0]NLW_udma_wrapper_cfg_status_ats_stu_UNCONNECTED;
  wire [31:0]NLW_udma_wrapper_cfg_status_ost_pr_alloc_UNCONNECTED;
  wire [8:0]\NLW_udma_wrapper_dsc_in\.crd[num]_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_dsc_in\.crd[qid]_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_dsc_out\.dsc[chn]_UNCONNECTED ;
  wire [15:0]\NLW_udma_wrapper_dsc_out\.dsc[cidx]_UNCONNECTED ;
  wire [255:0]\NLW_udma_wrapper_dsc_out\.dsc[dsc]_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_dsc_out\.dsc[qid]_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_dsc_out\.dsc[qst]_UNCONNECTED ;
  wire [2:0]\NLW_udma_wrapper_dsc_out\.dsc[siz]_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_dsc_out\.dsc[vld]_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_fabric_out\.c2h_dsc_avail_inc_chn_UNCONNECTED ;
  wire [15:0]\NLW_udma_wrapper_fabric_out\.c2h_dsc_avail_inc_num_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.c2h_dsc_avail_inc_qid_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_fabric_out\.c2h_dsc_avail_inc_state_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.c2h_sts[0]_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.c2h_sts[1]_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.c2h_sts[2]_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.c2h_sts[3]_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.flr_fnc_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.h2c_sts[0]_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.h2c_sts[1]_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.h2c_sts[2]_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.h2c_sts[3]_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.s_axis_c2h_tstat_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_fabric_out\.s_axis_c2h_tstat_chn_UNCONNECTED ;
  wire [4:0]\NLW_udma_wrapper_fabric_out\.s_axis_c2h_tstat_qid_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_fabric_out\.usr_irq_rfnc_UNCONNECTED ;
  wire [4:0]\NLW_udma_wrapper_fabric_out\.usr_irq_rvec_UNCONNECTED ;
  wire [127:0]NLW_udma_wrapper_h2c_desc_cmd_out_data_UNCONNECTED;
  wire [4:0]NLW_udma_wrapper_h2c_desc_cmd_out_qid_UNCONNECTED;
  wire [0:0]NLW_udma_wrapper_h2c_dsc_byp_ready_UNCONNECTED;
  wire [7:0]NLW_udma_wrapper_h2c_sts_UNCONNECTED;
  wire [1:1]NLW_udma_wrapper_m_axi_arburst_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_m_axi_arcache_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_m_axi_arid_UNCONNECTED;
  wire [2:0]NLW_udma_wrapper_m_axi_arprot_UNCONNECTED;
  wire [2:2]NLW_udma_wrapper_m_axi_arsize_UNCONNECTED;
  wire [1:1]NLW_udma_wrapper_m_axi_awburst_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_m_axi_awcache_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_m_axi_awid_UNCONNECTED;
  wire [2:0]NLW_udma_wrapper_m_axi_awprot_UNCONNECTED;
  wire [2:2]NLW_udma_wrapper_m_axi_awsize_UNCONNECTED;
  wire [7:0]NLW_udma_wrapper_m_axi_wdataeccparity_UNCONNECTED;
  wire [1:0]NLW_udma_wrapper_m_axib_arburst_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_m_axib_arcache_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_m_axib_arid_UNCONNECTED;
  wire [2:2]NLW_udma_wrapper_m_axib_arprot_UNCONNECTED;
  wire [2:2]NLW_udma_wrapper_m_axib_arsize_UNCONNECTED;
  wire [7:0]NLW_udma_wrapper_m_axib_aruser_UNCONNECTED;
  wire [1:0]NLW_udma_wrapper_m_axib_awburst_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_m_axib_awcache_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_m_axib_awid_UNCONNECTED;
  wire [2:2]NLW_udma_wrapper_m_axib_awprot_UNCONNECTED;
  wire [2:2]NLW_udma_wrapper_m_axib_awsize_UNCONNECTED;
  wire [7:0]NLW_udma_wrapper_m_axib_awuser_UNCONNECTED;
  wire [2:0]NLW_udma_wrapper_m_axil_arprot_UNCONNECTED;
  wire [7:0]NLW_udma_wrapper_m_axil_aruser_UNCONNECTED;
  wire [2:0]NLW_udma_wrapper_m_axil_awprot_UNCONNECTED;
  wire [7:0]NLW_udma_wrapper_m_axil_awuser_UNCONNECTED;
  wire [1:0]\NLW_udma_wrapper_m_axis_cc\.tkeep_UNCONNECTED ;
  wire [32:0]\NLW_udma_wrapper_m_axis_cc\.tuser_UNCONNECTED ;
  wire [63:0]NLW_udma_wrapper_m_axis_cq_tdata_UNCONNECTED;
  wire [1:0]NLW_udma_wrapper_m_axis_cq_tkeep_UNCONNECTED;
  wire [84:0]NLW_udma_wrapper_m_axis_cq_tuser_UNCONNECTED;
  wire [63:0]NLW_udma_wrapper_m_axis_h2c_tdata_UNCONNECTED;
  wire [7:0]NLW_udma_wrapper_m_axis_h2c_tkeep_UNCONNECTED;
  wire [0:0]NLW_udma_wrapper_m_axis_h2c_tlast_UNCONNECTED;
  wire [7:0]NLW_udma_wrapper_m_axis_h2c_tparity_UNCONNECTED;
  wire [47:0]NLW_udma_wrapper_m_axis_h2c_tuser_UNCONNECTED;
  wire [0:0]NLW_udma_wrapper_m_axis_h2c_tvalid_UNCONNECTED;
  wire [1:0]\NLW_udma_wrapper_m_axis_rq\.tkeep_UNCONNECTED ;
  wire [59:8]\NLW_udma_wrapper_m_axis_rq\.tuser_UNCONNECTED ;
  wire [511:64]\NLW_udma_wrapper_mi_c2h0_dat\.wdat_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_c2h0_dat\.wpar_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_c2h1_dat\.radr_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_c2h1_dat\.wadr_UNCONNECTED ;
  wire [511:0]\NLW_udma_wrapper_mi_c2h1_dat\.wdat_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_mi_c2h1_dat\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_c2h1_dat\.wpar_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_c2h2_dat\.radr_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_c2h2_dat\.wadr_UNCONNECTED ;
  wire [511:0]\NLW_udma_wrapper_mi_c2h2_dat\.wdat_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_mi_c2h2_dat\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_c2h2_dat\.wpar_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_c2h3_dat\.radr_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_c2h3_dat\.wadr_UNCONNECTED ;
  wire [511:0]\NLW_udma_wrapper_mi_c2h3_dat\.wdat_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_mi_c2h3_dat\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_c2h3_dat\.wpar_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.radr_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.wadr_UNCONNECTED ;
  wire [511:0]\NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.wdat_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.wpar_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.radr_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.wadr_UNCONNECTED ;
  wire [79:0]\NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.wdat_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.wen_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.wpar_UNCONNECTED ;
  wire [9:9]\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.radr_UNCONNECTED ;
  wire [9:9]\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.wadr_UNCONNECTED ;
  wire [511:64]\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.wdat_UNCONNECTED ;
  wire [7:1]\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.wpar_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.radr_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.wadr_UNCONNECTED ;
  wire [79:0]\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.wdat_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.wen_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.wpar_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_c2h_rd_brg_dat\.radr_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_c2h_rd_brg_dat\.wadr_UNCONNECTED ;
  wire [511:0]\NLW_udma_wrapper_mi_c2h_rd_brg_dat\.wdat_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_mi_c2h_rd_brg_dat\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_c2h_rd_brg_dat\.wpar_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_c2h_wr_brg_dat\.radr_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_c2h_wr_brg_dat\.wadr_UNCONNECTED ;
  wire [511:0]\NLW_udma_wrapper_mi_c2h_wr_brg_dat\.wdat_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_mi_c2h_wr_brg_dat\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_c2h_wr_brg_dat\.wpar_UNCONNECTED ;
  wire [11:0]\NLW_udma_wrapper_mi_dsc_crd_rcv\.radr_UNCONNECTED ;
  wire [11:0]\NLW_udma_wrapper_mi_dsc_crd_rcv\.wadr_UNCONNECTED ;
  wire [15:0]\NLW_udma_wrapper_mi_dsc_crd_rcv\.wdat_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_mi_dsc_crd_rcv\.wpar_UNCONNECTED ;
  wire [511:64]\NLW_udma_wrapper_mi_h2c0_dat\.wdat_UNCONNECTED ;
  wire [63:8]\NLW_udma_wrapper_mi_h2c0_dat\.wpar_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_h2c1_dat\.radr_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_h2c1_dat\.wadr_UNCONNECTED ;
  wire [511:0]\NLW_udma_wrapper_mi_h2c1_dat\.wdat_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_mi_h2c1_dat\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_h2c1_dat\.wpar_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_h2c2_dat\.radr_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_h2c2_dat\.wadr_UNCONNECTED ;
  wire [511:0]\NLW_udma_wrapper_mi_h2c2_dat\.wdat_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_mi_h2c2_dat\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_h2c2_dat\.wpar_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_h2c3_dat\.radr_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_mi_h2c3_dat\.wadr_UNCONNECTED ;
  wire [511:0]\NLW_udma_wrapper_mi_h2c3_dat\.wdat_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_mi_h2c3_dat\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_h2c3_dat\.wpar_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.radr_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.wadr_UNCONNECTED ;
  wire [511:0]\NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.wdat_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.wpar_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.radr_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.wadr_UNCONNECTED ;
  wire [79:0]\NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.wdat_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.wen_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.wpar_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.radr_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.wadr_UNCONNECTED ;
  wire [511:0]\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.wdat_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.wpar_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.radr_UNCONNECTED ;
  wire [9:0]\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.wadr_UNCONNECTED ;
  wire [79:0]\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.wdat_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.wen_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.wpar_UNCONNECTED ;
  wire [511:64]\NLW_udma_wrapper_mi_h2c_rd_brg_dat\.wdat_UNCONNECTED ;
  wire [1:1]\NLW_udma_wrapper_mi_h2c_rd_brg_dat\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_h2c_rd_brg_dat\.wpar_UNCONNECTED ;
  wire [10:9]\NLW_udma_wrapper_mi_h2c_wr_brg_dat\.radr_UNCONNECTED ;
  wire [10:9]\NLW_udma_wrapper_mi_h2c_wr_brg_dat\.wadr_UNCONNECTED ;
  wire [511:64]\NLW_udma_wrapper_mi_h2c_wr_brg_dat\.wdat_UNCONNECTED ;
  wire [1:1]\NLW_udma_wrapper_mi_h2c_wr_brg_dat\.wen_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_h2c_wr_brg_dat\.wpar_UNCONNECTED ;
  wire [11:0]\NLW_udma_wrapper_mi_hw_ctxt\.radr_UNCONNECTED ;
  wire [11:0]\NLW_udma_wrapper_mi_hw_ctxt\.wadr_UNCONNECTED ;
  wire [31:0]\NLW_udma_wrapper_mi_hw_ctxt\.wdat_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_mi_hw_ctxt\.wpar_UNCONNECTED ;
  wire [11:0]\NLW_udma_wrapper_mi_sw_ctxt\.radr_UNCONNECTED ;
  wire [11:0]\NLW_udma_wrapper_mi_sw_ctxt\.wadr_UNCONNECTED ;
  wire [127:0]\NLW_udma_wrapper_mi_sw_ctxt\.wdat_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_mi_sw_ctxt\.wen_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_mi_sw_ctxt\.wpar_UNCONNECTED ;
  wire [11:0]\NLW_udma_wrapper_mi_wb_base_ctxt\.radr_UNCONNECTED ;
  wire [11:0]\NLW_udma_wrapper_mi_wb_base_ctxt\.wadr_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_mi_wb_base_ctxt\.wdat_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_mi_wb_base_ctxt\.wen_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_mi_wb_base_ctxt\.wpar_UNCONNECTED ;
  wire [6:0]\NLW_udma_wrapper_pcie_dma_gic\.interrupt_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_ds_bus_number_UNCONNECTED ;
  wire [4:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_ds_device_number_UNCONNECTED ;
  wire [2:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_ds_function_number_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_ds_port_number_UNCONNECTED ;
  wire [63:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_dsn_UNCONNECTED ;
  wire [31:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_ext_read_data_UNCONNECTED ;
  wire [2:1]\NLW_udma_wrapper_pcie_dma_out\.cfg_fc_sel_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_flr_done_UNCONNECTED ;
  wire [3:1]\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_int_UNCONNECTED ;
  wire [2:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_attr_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_function_number_UNCONNECTED ;
  wire [31:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_pending_status_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_pending_status_function_num_UNCONNECTED ;
  wire [8:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_tph_st_tag_UNCONNECTED ;
  wire [1:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_tph_type_UNCONNECTED ;
  wire [255:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msix_address_UNCONNECTED ;
  wire [31:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msix_data_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_pending_UNCONNECTED ;
  wire [18:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_addr_UNCONNECTED ;
  wire [3:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_byte_enable_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_function_number_UNCONNECTED ;
  wire [31:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_write_data_UNCONNECTED ;
  wire [31:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_msg_transmit_data_UNCONNECTED ;
  wire [2:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_msg_transmit_type_UNCONNECTED ;
  wire [2:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_per_func_status_control_UNCONNECTED ;
  wire [6:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_per_function_number_UNCONNECTED ;
  wire [7:0]\NLW_udma_wrapper_pcie_dma_out\.cfg_vf_flr_func_num_UNCONNECTED ;
  wire [1:1]\NLW_udma_wrapper_pcie_dma_out\.pcie_cq_np_req_UNCONNECTED ;
  wire [3:0]NLW_udma_wrapper_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_udma_wrapper_s_axi_bresp_UNCONNECTED;
  wire [63:0]NLW_udma_wrapper_s_axi_rdata_UNCONNECTED;
  wire [7:0]NLW_udma_wrapper_s_axi_rdataeccparity_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_udma_wrapper_s_axi_rresp_UNCONNECTED;
  wire [1:0]NLW_udma_wrapper_s_axil_bresp_UNCONNECTED;
  wire [1:0]NLW_udma_wrapper_s_axil_rresp_UNCONNECTED;
  wire [0:0]NLW_udma_wrapper_s_axis_c2h_tready_UNCONNECTED;
  wire [21:1]\NLW_udma_wrapper_s_axis_cq\.tready_UNCONNECTED ;
  wire [21:1]\NLW_udma_wrapper_s_axis_rc\.tready_UNCONNECTED ;
  wire [7:0]NLW_udma_wrapper_user_cfg_ext_function_number_o_UNCONNECTED;
  wire [9:0]NLW_udma_wrapper_user_cfg_ext_register_number_o_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_user_cfg_ext_write_byte_enable_o_UNCONNECTED;
  wire [31:0]NLW_udma_wrapper_user_cfg_ext_write_data_o_UNCONNECTED;
  wire [7:0]NLW_udma_wrapper_usr_flr_fnc_UNCONNECTED;

  assign Integrated_bloc_reset_o = \<const0> ;
  assign ats_pri_en = \<const0> ;
  assign atspri_m_axis_cq_tdata[63] = \<const0> ;
  assign atspri_m_axis_cq_tdata[62] = \<const0> ;
  assign atspri_m_axis_cq_tdata[61] = \<const0> ;
  assign atspri_m_axis_cq_tdata[60] = \<const0> ;
  assign atspri_m_axis_cq_tdata[59] = \<const0> ;
  assign atspri_m_axis_cq_tdata[58] = \<const0> ;
  assign atspri_m_axis_cq_tdata[57] = \<const0> ;
  assign atspri_m_axis_cq_tdata[56] = \<const0> ;
  assign atspri_m_axis_cq_tdata[55] = \<const0> ;
  assign atspri_m_axis_cq_tdata[54] = \<const0> ;
  assign atspri_m_axis_cq_tdata[53] = \<const0> ;
  assign atspri_m_axis_cq_tdata[52] = \<const0> ;
  assign atspri_m_axis_cq_tdata[51] = \<const0> ;
  assign atspri_m_axis_cq_tdata[50] = \<const0> ;
  assign atspri_m_axis_cq_tdata[49] = \<const0> ;
  assign atspri_m_axis_cq_tdata[48] = \<const0> ;
  assign atspri_m_axis_cq_tdata[47] = \<const0> ;
  assign atspri_m_axis_cq_tdata[46] = \<const0> ;
  assign atspri_m_axis_cq_tdata[45] = \<const0> ;
  assign atspri_m_axis_cq_tdata[44] = \<const0> ;
  assign atspri_m_axis_cq_tdata[43] = \<const0> ;
  assign atspri_m_axis_cq_tdata[42] = \<const0> ;
  assign atspri_m_axis_cq_tdata[41] = \<const0> ;
  assign atspri_m_axis_cq_tdata[40] = \<const0> ;
  assign atspri_m_axis_cq_tdata[39] = \<const0> ;
  assign atspri_m_axis_cq_tdata[38] = \<const0> ;
  assign atspri_m_axis_cq_tdata[37] = \<const0> ;
  assign atspri_m_axis_cq_tdata[36] = \<const0> ;
  assign atspri_m_axis_cq_tdata[35] = \<const0> ;
  assign atspri_m_axis_cq_tdata[34] = \<const0> ;
  assign atspri_m_axis_cq_tdata[33] = \<const0> ;
  assign atspri_m_axis_cq_tdata[32] = \<const0> ;
  assign atspri_m_axis_cq_tdata[31] = \<const0> ;
  assign atspri_m_axis_cq_tdata[30] = \<const0> ;
  assign atspri_m_axis_cq_tdata[29] = \<const0> ;
  assign atspri_m_axis_cq_tdata[28] = \<const0> ;
  assign atspri_m_axis_cq_tdata[27] = \<const0> ;
  assign atspri_m_axis_cq_tdata[26] = \<const0> ;
  assign atspri_m_axis_cq_tdata[25] = \<const0> ;
  assign atspri_m_axis_cq_tdata[24] = \<const0> ;
  assign atspri_m_axis_cq_tdata[23] = \<const0> ;
  assign atspri_m_axis_cq_tdata[22] = \<const0> ;
  assign atspri_m_axis_cq_tdata[21] = \<const0> ;
  assign atspri_m_axis_cq_tdata[20] = \<const0> ;
  assign atspri_m_axis_cq_tdata[19] = \<const0> ;
  assign atspri_m_axis_cq_tdata[18] = \<const0> ;
  assign atspri_m_axis_cq_tdata[17] = \<const0> ;
  assign atspri_m_axis_cq_tdata[16] = \<const0> ;
  assign atspri_m_axis_cq_tdata[15] = \<const0> ;
  assign atspri_m_axis_cq_tdata[14] = \<const0> ;
  assign atspri_m_axis_cq_tdata[13] = \<const0> ;
  assign atspri_m_axis_cq_tdata[12] = \<const0> ;
  assign atspri_m_axis_cq_tdata[11] = \<const0> ;
  assign atspri_m_axis_cq_tdata[10] = \<const0> ;
  assign atspri_m_axis_cq_tdata[9] = \<const0> ;
  assign atspri_m_axis_cq_tdata[8] = \<const0> ;
  assign atspri_m_axis_cq_tdata[7] = \<const0> ;
  assign atspri_m_axis_cq_tdata[6] = \<const0> ;
  assign atspri_m_axis_cq_tdata[5] = \<const0> ;
  assign atspri_m_axis_cq_tdata[4] = \<const0> ;
  assign atspri_m_axis_cq_tdata[3] = \<const0> ;
  assign atspri_m_axis_cq_tdata[2] = \<const0> ;
  assign atspri_m_axis_cq_tdata[1] = \<const0> ;
  assign atspri_m_axis_cq_tdata[0] = \<const0> ;
  assign atspri_m_axis_cq_tkeep[1] = \<const0> ;
  assign atspri_m_axis_cq_tkeep[0] = \<const0> ;
  assign atspri_m_axis_cq_tlast = \<const0> ;
  assign atspri_m_axis_cq_tuser[84] = \<const0> ;
  assign atspri_m_axis_cq_tuser[83] = \<const0> ;
  assign atspri_m_axis_cq_tuser[82] = \<const0> ;
  assign atspri_m_axis_cq_tuser[81] = \<const0> ;
  assign atspri_m_axis_cq_tuser[80] = \<const0> ;
  assign atspri_m_axis_cq_tuser[79] = \<const0> ;
  assign atspri_m_axis_cq_tuser[78] = \<const0> ;
  assign atspri_m_axis_cq_tuser[77] = \<const0> ;
  assign atspri_m_axis_cq_tuser[76] = \<const0> ;
  assign atspri_m_axis_cq_tuser[75] = \<const0> ;
  assign atspri_m_axis_cq_tuser[74] = \<const0> ;
  assign atspri_m_axis_cq_tuser[73] = \<const0> ;
  assign atspri_m_axis_cq_tuser[72] = \<const0> ;
  assign atspri_m_axis_cq_tuser[71] = \<const0> ;
  assign atspri_m_axis_cq_tuser[70] = \<const0> ;
  assign atspri_m_axis_cq_tuser[69] = \<const0> ;
  assign atspri_m_axis_cq_tuser[68] = \<const0> ;
  assign atspri_m_axis_cq_tuser[67] = \<const0> ;
  assign atspri_m_axis_cq_tuser[66] = \<const0> ;
  assign atspri_m_axis_cq_tuser[65] = \<const0> ;
  assign atspri_m_axis_cq_tuser[64] = \<const0> ;
  assign atspri_m_axis_cq_tuser[63] = \<const0> ;
  assign atspri_m_axis_cq_tuser[62] = \<const0> ;
  assign atspri_m_axis_cq_tuser[61] = \<const0> ;
  assign atspri_m_axis_cq_tuser[60] = \<const0> ;
  assign atspri_m_axis_cq_tuser[59] = \<const0> ;
  assign atspri_m_axis_cq_tuser[58] = \<const0> ;
  assign atspri_m_axis_cq_tuser[57] = \<const0> ;
  assign atspri_m_axis_cq_tuser[56] = \<const0> ;
  assign atspri_m_axis_cq_tuser[55] = \<const0> ;
  assign atspri_m_axis_cq_tuser[54] = \<const0> ;
  assign atspri_m_axis_cq_tuser[53] = \<const0> ;
  assign atspri_m_axis_cq_tuser[52] = \<const0> ;
  assign atspri_m_axis_cq_tuser[51] = \<const0> ;
  assign atspri_m_axis_cq_tuser[50] = \<const0> ;
  assign atspri_m_axis_cq_tuser[49] = \<const0> ;
  assign atspri_m_axis_cq_tuser[48] = \<const0> ;
  assign atspri_m_axis_cq_tuser[47] = \<const0> ;
  assign atspri_m_axis_cq_tuser[46] = \<const0> ;
  assign atspri_m_axis_cq_tuser[45] = \<const0> ;
  assign atspri_m_axis_cq_tuser[44] = \<const0> ;
  assign atspri_m_axis_cq_tuser[43] = \<const0> ;
  assign atspri_m_axis_cq_tuser[42] = \<const0> ;
  assign atspri_m_axis_cq_tuser[41] = \<const0> ;
  assign atspri_m_axis_cq_tuser[40] = \<const0> ;
  assign atspri_m_axis_cq_tuser[39] = \<const0> ;
  assign atspri_m_axis_cq_tuser[38] = \<const0> ;
  assign atspri_m_axis_cq_tuser[37] = \<const0> ;
  assign atspri_m_axis_cq_tuser[36] = \<const0> ;
  assign atspri_m_axis_cq_tuser[35] = \<const0> ;
  assign atspri_m_axis_cq_tuser[34] = \<const0> ;
  assign atspri_m_axis_cq_tuser[33] = \<const0> ;
  assign atspri_m_axis_cq_tuser[32] = \<const0> ;
  assign atspri_m_axis_cq_tuser[31] = \<const0> ;
  assign atspri_m_axis_cq_tuser[30] = \<const0> ;
  assign atspri_m_axis_cq_tuser[29] = \<const0> ;
  assign atspri_m_axis_cq_tuser[28] = \<const0> ;
  assign atspri_m_axis_cq_tuser[27] = \<const0> ;
  assign atspri_m_axis_cq_tuser[26] = \<const0> ;
  assign atspri_m_axis_cq_tuser[25] = \<const0> ;
  assign atspri_m_axis_cq_tuser[24] = \<const0> ;
  assign atspri_m_axis_cq_tuser[23] = \<const0> ;
  assign atspri_m_axis_cq_tuser[22] = \<const0> ;
  assign atspri_m_axis_cq_tuser[21] = \<const0> ;
  assign atspri_m_axis_cq_tuser[20] = \<const0> ;
  assign atspri_m_axis_cq_tuser[19] = \<const0> ;
  assign atspri_m_axis_cq_tuser[18] = \<const0> ;
  assign atspri_m_axis_cq_tuser[17] = \<const0> ;
  assign atspri_m_axis_cq_tuser[16] = \<const0> ;
  assign atspri_m_axis_cq_tuser[15] = \<const0> ;
  assign atspri_m_axis_cq_tuser[14] = \<const0> ;
  assign atspri_m_axis_cq_tuser[13] = \<const0> ;
  assign atspri_m_axis_cq_tuser[12] = \<const0> ;
  assign atspri_m_axis_cq_tuser[11] = \<const0> ;
  assign atspri_m_axis_cq_tuser[10] = \<const0> ;
  assign atspri_m_axis_cq_tuser[9] = \<const0> ;
  assign atspri_m_axis_cq_tuser[8] = \<const0> ;
  assign atspri_m_axis_cq_tuser[7] = \<const0> ;
  assign atspri_m_axis_cq_tuser[6] = \<const0> ;
  assign atspri_m_axis_cq_tuser[5] = \<const0> ;
  assign atspri_m_axis_cq_tuser[4] = \<const0> ;
  assign atspri_m_axis_cq_tuser[3] = \<const0> ;
  assign atspri_m_axis_cq_tuser[2] = \<const0> ;
  assign atspri_m_axis_cq_tuser[1] = \<const0> ;
  assign atspri_m_axis_cq_tuser[0] = \<const0> ;
  assign atspri_m_axis_cq_tvalid = \<const0> ;
  assign atspri_s_axis_rq_tready = \<const0> ;
  assign axi_aresetn = \xdma_0_cfg_sideband_i/p_9_in ;
  assign axi_ctl_aresetn = \<const0> ;
  assign c2h_dsc_byp_ready_0 = \<const0> ;
  assign c2h_dsc_byp_ready_1 = \<const0> ;
  assign c2h_dsc_byp_ready_2 = \<const0> ;
  assign c2h_dsc_byp_ready_3 = \<const0> ;
  assign c2h_sts_0[7] = \<const0> ;
  assign c2h_sts_0[6] = \<const0> ;
  assign c2h_sts_0[5] = \<const0> ;
  assign c2h_sts_0[4] = \<const0> ;
  assign c2h_sts_0[3] = \<const0> ;
  assign c2h_sts_0[2] = \<const0> ;
  assign c2h_sts_0[1] = \<const0> ;
  assign c2h_sts_0[0] = \<const0> ;
  assign c2h_sts_1[7] = \<const0> ;
  assign c2h_sts_1[6] = \<const0> ;
  assign c2h_sts_1[5] = \<const0> ;
  assign c2h_sts_1[4] = \<const0> ;
  assign c2h_sts_1[3] = \<const0> ;
  assign c2h_sts_1[2] = \<const0> ;
  assign c2h_sts_1[1] = \<const0> ;
  assign c2h_sts_1[0] = \<const0> ;
  assign c2h_sts_2[7] = \<const0> ;
  assign c2h_sts_2[6] = \<const0> ;
  assign c2h_sts_2[5] = \<const0> ;
  assign c2h_sts_2[4] = \<const0> ;
  assign c2h_sts_2[3] = \<const0> ;
  assign c2h_sts_2[2] = \<const0> ;
  assign c2h_sts_2[1] = \<const0> ;
  assign c2h_sts_2[0] = \<const0> ;
  assign c2h_sts_3[7] = \<const0> ;
  assign c2h_sts_3[6] = \<const0> ;
  assign c2h_sts_3[5] = \<const0> ;
  assign c2h_sts_3[4] = \<const0> ;
  assign c2h_sts_3[3] = \<const0> ;
  assign c2h_sts_3[2] = \<const0> ;
  assign c2h_sts_3[1] = \<const0> ;
  assign c2h_sts_3[0] = \<const0> ;
  assign cap_req = \<const0> ;
  assign cfg_config_space_enable_sd = \<const0> ;
  assign cfg_current_speed_o[2] = \<const0> ;
  assign cfg_current_speed_o[1] = \<const0> ;
  assign cfg_current_speed_o[0] = \<const0> ;
  assign cfg_ds_bus_number_sd[7] = \<const0> ;
  assign cfg_ds_bus_number_sd[6] = \<const0> ;
  assign cfg_ds_bus_number_sd[5] = \<const0> ;
  assign cfg_ds_bus_number_sd[4] = \<const0> ;
  assign cfg_ds_bus_number_sd[3] = \<const0> ;
  assign cfg_ds_bus_number_sd[2] = \<const0> ;
  assign cfg_ds_bus_number_sd[1] = \<const0> ;
  assign cfg_ds_bus_number_sd[0] = \<const0> ;
  assign cfg_ds_device_number_sd[4] = \<const0> ;
  assign cfg_ds_device_number_sd[3] = \<const0> ;
  assign cfg_ds_device_number_sd[2] = \<const0> ;
  assign cfg_ds_device_number_sd[1] = \<const0> ;
  assign cfg_ds_device_number_sd[0] = \<const0> ;
  assign cfg_ds_function_number_sd[2] = \<const0> ;
  assign cfg_ds_function_number_sd[1] = \<const0> ;
  assign cfg_ds_function_number_sd[0] = \<const0> ;
  assign cfg_ds_port_number_sd[7] = \<const0> ;
  assign cfg_ds_port_number_sd[6] = \<const0> ;
  assign cfg_ds_port_number_sd[5] = \<const0> ;
  assign cfg_ds_port_number_sd[4] = \<const0> ;
  assign cfg_ds_port_number_sd[3] = \<const0> ;
  assign cfg_ds_port_number_sd[2] = \<const0> ;
  assign cfg_ds_port_number_sd[1] = \<const0> ;
  assign cfg_ds_port_number_sd[0] = \<const0> ;
  assign cfg_dsn_sd[63] = \<const0> ;
  assign cfg_dsn_sd[62] = \<const0> ;
  assign cfg_dsn_sd[61] = \<const0> ;
  assign cfg_dsn_sd[60] = \<const0> ;
  assign cfg_dsn_sd[59] = \<const0> ;
  assign cfg_dsn_sd[58] = \<const0> ;
  assign cfg_dsn_sd[57] = \<const0> ;
  assign cfg_dsn_sd[56] = \<const0> ;
  assign cfg_dsn_sd[55] = \<const0> ;
  assign cfg_dsn_sd[54] = \<const0> ;
  assign cfg_dsn_sd[53] = \<const0> ;
  assign cfg_dsn_sd[52] = \<const0> ;
  assign cfg_dsn_sd[51] = \<const0> ;
  assign cfg_dsn_sd[50] = \<const0> ;
  assign cfg_dsn_sd[49] = \<const0> ;
  assign cfg_dsn_sd[48] = \<const0> ;
  assign cfg_dsn_sd[47] = \<const0> ;
  assign cfg_dsn_sd[46] = \<const0> ;
  assign cfg_dsn_sd[45] = \<const0> ;
  assign cfg_dsn_sd[44] = \<const0> ;
  assign cfg_dsn_sd[43] = \<const0> ;
  assign cfg_dsn_sd[42] = \<const0> ;
  assign cfg_dsn_sd[41] = \<const0> ;
  assign cfg_dsn_sd[40] = \<const0> ;
  assign cfg_dsn_sd[39] = \<const0> ;
  assign cfg_dsn_sd[38] = \<const0> ;
  assign cfg_dsn_sd[37] = \<const0> ;
  assign cfg_dsn_sd[36] = \<const0> ;
  assign cfg_dsn_sd[35] = \<const0> ;
  assign cfg_dsn_sd[34] = \<const0> ;
  assign cfg_dsn_sd[33] = \<const0> ;
  assign cfg_dsn_sd[32] = \<const0> ;
  assign cfg_dsn_sd[31] = \<const0> ;
  assign cfg_dsn_sd[30] = \<const0> ;
  assign cfg_dsn_sd[29] = \<const0> ;
  assign cfg_dsn_sd[28] = \<const0> ;
  assign cfg_dsn_sd[27] = \<const0> ;
  assign cfg_dsn_sd[26] = \<const0> ;
  assign cfg_dsn_sd[25] = \<const0> ;
  assign cfg_dsn_sd[24] = \<const0> ;
  assign cfg_dsn_sd[23] = \<const0> ;
  assign cfg_dsn_sd[22] = \<const0> ;
  assign cfg_dsn_sd[21] = \<const0> ;
  assign cfg_dsn_sd[20] = \<const0> ;
  assign cfg_dsn_sd[19] = \<const0> ;
  assign cfg_dsn_sd[18] = \<const0> ;
  assign cfg_dsn_sd[17] = \<const0> ;
  assign cfg_dsn_sd[16] = \<const0> ;
  assign cfg_dsn_sd[15] = \<const0> ;
  assign cfg_dsn_sd[14] = \<const0> ;
  assign cfg_dsn_sd[13] = \<const0> ;
  assign cfg_dsn_sd[12] = \<const0> ;
  assign cfg_dsn_sd[11] = \<const0> ;
  assign cfg_dsn_sd[10] = \<const0> ;
  assign cfg_dsn_sd[9] = \<const0> ;
  assign cfg_dsn_sd[8] = \<const0> ;
  assign cfg_dsn_sd[7] = \<const0> ;
  assign cfg_dsn_sd[6] = \<const0> ;
  assign cfg_dsn_sd[5] = \<const0> ;
  assign cfg_dsn_sd[4] = \<const0> ;
  assign cfg_dsn_sd[3] = \<const0> ;
  assign cfg_dsn_sd[2] = \<const0> ;
  assign cfg_dsn_sd[1] = \<const0> ;
  assign cfg_dsn_sd[0] = \<const0> ;
  assign cfg_err_cor_in_sd = \<const0> ;
  assign cfg_err_cor_o = \<const0> ;
  assign cfg_err_fatal_o = \<const0> ;
  assign cfg_err_nonfatal_o = \<const0> ;
  assign cfg_err_uncor_in_sd = \<const0> ;
  assign cfg_ext_function_number[7] = \<const0> ;
  assign cfg_ext_function_number[6] = \<const0> ;
  assign cfg_ext_function_number[5] = \<const0> ;
  assign cfg_ext_function_number[4] = \<const0> ;
  assign cfg_ext_function_number[3] = \<const0> ;
  assign cfg_ext_function_number[2] = \<const0> ;
  assign cfg_ext_function_number[1] = \<const0> ;
  assign cfg_ext_function_number[0] = \<const0> ;
  assign cfg_ext_read_received = \<const0> ;
  assign cfg_ext_register_number[9] = \<const0> ;
  assign cfg_ext_register_number[8] = \<const0> ;
  assign cfg_ext_register_number[7] = \<const0> ;
  assign cfg_ext_register_number[6] = \<const0> ;
  assign cfg_ext_register_number[5] = \<const0> ;
  assign cfg_ext_register_number[4] = \<const0> ;
  assign cfg_ext_register_number[3] = \<const0> ;
  assign cfg_ext_register_number[2] = \<const0> ;
  assign cfg_ext_register_number[1] = \<const0> ;
  assign cfg_ext_register_number[0] = \<const0> ;
  assign cfg_ext_write_byte_enable[3] = \<const0> ;
  assign cfg_ext_write_byte_enable[2] = \<const0> ;
  assign cfg_ext_write_byte_enable[1] = \<const0> ;
  assign cfg_ext_write_byte_enable[0] = \<const0> ;
  assign cfg_ext_write_data[31] = \<const0> ;
  assign cfg_ext_write_data[30] = \<const0> ;
  assign cfg_ext_write_data[29] = \<const0> ;
  assign cfg_ext_write_data[28] = \<const0> ;
  assign cfg_ext_write_data[27] = \<const0> ;
  assign cfg_ext_write_data[26] = \<const0> ;
  assign cfg_ext_write_data[25] = \<const0> ;
  assign cfg_ext_write_data[24] = \<const0> ;
  assign cfg_ext_write_data[23] = \<const0> ;
  assign cfg_ext_write_data[22] = \<const0> ;
  assign cfg_ext_write_data[21] = \<const0> ;
  assign cfg_ext_write_data[20] = \<const0> ;
  assign cfg_ext_write_data[19] = \<const0> ;
  assign cfg_ext_write_data[18] = \<const0> ;
  assign cfg_ext_write_data[17] = \<const0> ;
  assign cfg_ext_write_data[16] = \<const0> ;
  assign cfg_ext_write_data[15] = \<const0> ;
  assign cfg_ext_write_data[14] = \<const0> ;
  assign cfg_ext_write_data[13] = \<const0> ;
  assign cfg_ext_write_data[12] = \<const0> ;
  assign cfg_ext_write_data[11] = \<const0> ;
  assign cfg_ext_write_data[10] = \<const0> ;
  assign cfg_ext_write_data[9] = \<const0> ;
  assign cfg_ext_write_data[8] = \<const0> ;
  assign cfg_ext_write_data[7] = \<const0> ;
  assign cfg_ext_write_data[6] = \<const0> ;
  assign cfg_ext_write_data[5] = \<const0> ;
  assign cfg_ext_write_data[4] = \<const0> ;
  assign cfg_ext_write_data[3] = \<const0> ;
  assign cfg_ext_write_data[2] = \<const0> ;
  assign cfg_ext_write_data[1] = \<const0> ;
  assign cfg_ext_write_data[0] = \<const0> ;
  assign cfg_ext_write_received = \<const0> ;
  assign cfg_fc_sel_sd[2] = \<const0> ;
  assign cfg_fc_sel_sd[1] = \<const0> ;
  assign cfg_fc_sel_sd[0] = \<const0> ;
  assign cfg_flr_done_sd[3] = \<const0> ;
  assign cfg_flr_done_sd[2] = \<const0> ;
  assign cfg_flr_done_sd[1] = \<const0> ;
  assign cfg_flr_done_sd[0] = \<const0> ;
  assign cfg_flr_in_process[3] = \<const0> ;
  assign cfg_flr_in_process[2] = \<const0> ;
  assign cfg_flr_in_process[1] = \<const0> ;
  assign cfg_flr_in_process[0] = \<const0> ;
  assign cfg_function_status[7] = \<const0> ;
  assign cfg_function_status[6] = \<const0> ;
  assign cfg_function_status[5] = \<const0> ;
  assign cfg_function_status[4] = \<const0> ;
  assign cfg_function_status[3] = \<const0> ;
  assign cfg_function_status[2] = \<const0> ;
  assign cfg_function_status[1] = \<const0> ;
  assign cfg_function_status[0] = \<const0> ;
  assign cfg_interrupt_int_sd[3] = \<const0> ;
  assign cfg_interrupt_int_sd[2] = \<const0> ;
  assign cfg_interrupt_int_sd[1] = \<const0> ;
  assign cfg_interrupt_int_sd[0] = \<const0> ;
  assign cfg_interrupt_msi_attr_sd[2] = \<const0> ;
  assign cfg_interrupt_msi_attr_sd[1] = \<const0> ;
  assign cfg_interrupt_msi_attr_sd[0] = \<const0> ;
  assign cfg_interrupt_msi_enable[3] = \<const0> ;
  assign cfg_interrupt_msi_enable[2] = \<const0> ;
  assign cfg_interrupt_msi_enable[1] = \<const0> ;
  assign cfg_interrupt_msi_enable[0] = \<const0> ;
  assign cfg_interrupt_msi_fail = \<const0> ;
  assign cfg_interrupt_msi_function_number_sd[7] = \<const0> ;
  assign cfg_interrupt_msi_function_number_sd[6] = \<const0> ;
  assign cfg_interrupt_msi_function_number_sd[5] = \<const0> ;
  assign cfg_interrupt_msi_function_number_sd[4] = \<const0> ;
  assign cfg_interrupt_msi_function_number_sd[3] = \<const0> ;
  assign cfg_interrupt_msi_function_number_sd[2] = \<const0> ;
  assign cfg_interrupt_msi_function_number_sd[1] = \<const0> ;
  assign cfg_interrupt_msi_function_number_sd[0] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[31] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[30] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[29] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[28] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[27] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[26] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[25] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[24] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[23] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[22] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[21] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[20] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[19] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[18] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[17] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[16] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[15] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[14] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[13] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[12] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[11] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[10] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[9] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[8] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[7] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[6] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[5] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[4] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[3] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[2] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[1] = \<const0> ;
  assign cfg_interrupt_msi_int_sd[0] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_data_enable_sd = \<const0> ;
  assign cfg_interrupt_msi_pending_status_function_num_sd[3] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_function_num_sd[2] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_function_num_sd[1] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_function_num_sd[0] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[31] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[30] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[29] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[28] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[27] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[26] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[25] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[24] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[23] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[22] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[21] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[20] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[19] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[18] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[17] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[16] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[15] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[14] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[13] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[12] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[11] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[10] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[9] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[8] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[7] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[6] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[5] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[4] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[3] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[2] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[1] = \<const0> ;
  assign cfg_interrupt_msi_pending_status_sd[0] = \<const0> ;
  assign cfg_interrupt_msi_sent = \<const0> ;
  assign cfg_interrupt_msi_tph_present_sd = \<const0> ;
  assign cfg_interrupt_msi_tph_st_tag_sd[8] = \<const0> ;
  assign cfg_interrupt_msi_tph_st_tag_sd[7] = \<const0> ;
  assign cfg_interrupt_msi_tph_st_tag_sd[6] = \<const0> ;
  assign cfg_interrupt_msi_tph_st_tag_sd[5] = \<const0> ;
  assign cfg_interrupt_msi_tph_st_tag_sd[4] = \<const0> ;
  assign cfg_interrupt_msi_tph_st_tag_sd[3] = \<const0> ;
  assign cfg_interrupt_msi_tph_st_tag_sd[2] = \<const0> ;
  assign cfg_interrupt_msi_tph_st_tag_sd[1] = \<const0> ;
  assign cfg_interrupt_msi_tph_st_tag_sd[0] = \<const0> ;
  assign cfg_interrupt_msi_tph_type_sd[1] = \<const0> ;
  assign cfg_interrupt_msi_tph_type_sd[0] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[63] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[62] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[61] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[60] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[59] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[58] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[57] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[56] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[55] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[54] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[53] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[52] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[51] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[50] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[49] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[48] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[47] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[46] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[45] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[44] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[43] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[42] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[41] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[40] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[39] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[38] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[37] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[36] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[35] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[34] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[33] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[32] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[31] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[30] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[29] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[28] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[27] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[26] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[25] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[24] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[23] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[22] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[21] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[20] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[19] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[18] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[17] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[16] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[15] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[14] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[13] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[12] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[11] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[10] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[9] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[8] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[7] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[6] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[5] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[4] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[3] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[2] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[1] = \<const0> ;
  assign cfg_interrupt_msix_address_sd[0] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[31] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[30] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[29] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[28] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[27] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[26] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[25] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[24] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[23] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[22] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[21] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[20] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[19] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[18] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[17] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[16] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[15] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[14] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[13] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[12] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[11] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[10] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[9] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[8] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[7] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[6] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[5] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[4] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[3] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[2] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[1] = \<const0> ;
  assign cfg_interrupt_msix_data_sd[0] = \<const0> ;
  assign cfg_interrupt_msix_enable[1] = \<const0> ;
  assign cfg_interrupt_msix_enable[0] = \<const0> ;
  assign cfg_interrupt_msix_fail = \<const0> ;
  assign cfg_interrupt_msix_int_sd = \<const0> ;
  assign cfg_interrupt_msix_mask[1] = \<const0> ;
  assign cfg_interrupt_msix_mask[0] = \<const0> ;
  assign cfg_interrupt_msix_sent = \<const0> ;
  assign cfg_interrupt_msix_vec_pending_sd[1] = \<const0> ;
  assign cfg_interrupt_msix_vec_pending_sd[0] = \<const0> ;
  assign cfg_interrupt_pending_sd[3] = \<const0> ;
  assign cfg_interrupt_pending_sd[2] = \<const0> ;
  assign cfg_interrupt_pending_sd[1] = \<const0> ;
  assign cfg_interrupt_pending_sd[0] = \<const0> ;
  assign cfg_link_training_enable_sd = \<const0> ;
  assign cfg_local_error_o[4] = \<const0> ;
  assign cfg_local_error_o[3] = \<const0> ;
  assign cfg_local_error_o[2] = \<const0> ;
  assign cfg_local_error_o[1] = \<const0> ;
  assign cfg_local_error_o[0] = \<const0> ;
  assign cfg_local_error_valid_o = \<const0> ;
  assign cfg_ltssm_state[5] = \<const0> ;
  assign cfg_ltssm_state[4] = \<const0> ;
  assign cfg_ltssm_state[3] = \<const0> ;
  assign cfg_ltssm_state[2] = \<const0> ;
  assign cfg_ltssm_state[1] = \<const0> ;
  assign cfg_ltssm_state[0] = \<const0> ;
  assign cfg_ltssm_state_o[5] = \<const0> ;
  assign cfg_ltssm_state_o[4] = \<const0> ;
  assign cfg_ltssm_state_o[3] = \<const0> ;
  assign cfg_ltssm_state_o[2] = \<const0> ;
  assign cfg_ltssm_state_o[1] = \<const0> ;
  assign cfg_ltssm_state_o[0] = \<const0> ;
  assign cfg_max_payload[2] = \<const0> ;
  assign cfg_max_payload[1] = \<const0> ;
  assign cfg_max_payload[0] = \<const0> ;
  assign cfg_max_read_req[2] = \<const0> ;
  assign cfg_max_read_req[1] = \<const0> ;
  assign cfg_max_read_req[0] = \<const0> ;
  assign cfg_mgmt_addr_sd[9] = \<const0> ;
  assign cfg_mgmt_addr_sd[8] = \<const0> ;
  assign cfg_mgmt_addr_sd[7] = \<const0> ;
  assign cfg_mgmt_addr_sd[6] = \<const0> ;
  assign cfg_mgmt_addr_sd[5] = \<const0> ;
  assign cfg_mgmt_addr_sd[4] = \<const0> ;
  assign cfg_mgmt_addr_sd[3] = \<const0> ;
  assign cfg_mgmt_addr_sd[2] = \<const0> ;
  assign cfg_mgmt_addr_sd[1] = \<const0> ;
  assign cfg_mgmt_addr_sd[0] = \<const0> ;
  assign cfg_mgmt_byte_enable_sd[3] = \<const0> ;
  assign cfg_mgmt_byte_enable_sd[2] = \<const0> ;
  assign cfg_mgmt_byte_enable_sd[1] = \<const0> ;
  assign cfg_mgmt_byte_enable_sd[0] = \<const0> ;
  assign cfg_mgmt_function_number_sd[7] = \<const0> ;
  assign cfg_mgmt_function_number_sd[6] = \<const0> ;
  assign cfg_mgmt_function_number_sd[5] = \<const0> ;
  assign cfg_mgmt_function_number_sd[4] = \<const0> ;
  assign cfg_mgmt_function_number_sd[3] = \<const0> ;
  assign cfg_mgmt_function_number_sd[2] = \<const0> ;
  assign cfg_mgmt_function_number_sd[1] = \<const0> ;
  assign cfg_mgmt_function_number_sd[0] = \<const0> ;
  assign cfg_mgmt_read_sd = \<const0> ;
  assign cfg_mgmt_type1_cfg_reg_access_sd = \<const0> ;
  assign cfg_mgmt_write_data_sd[31] = \<const0> ;
  assign cfg_mgmt_write_data_sd[30] = \<const0> ;
  assign cfg_mgmt_write_data_sd[29] = \<const0> ;
  assign cfg_mgmt_write_data_sd[28] = \<const0> ;
  assign cfg_mgmt_write_data_sd[27] = \<const0> ;
  assign cfg_mgmt_write_data_sd[26] = \<const0> ;
  assign cfg_mgmt_write_data_sd[25] = \<const0> ;
  assign cfg_mgmt_write_data_sd[24] = \<const0> ;
  assign cfg_mgmt_write_data_sd[23] = \<const0> ;
  assign cfg_mgmt_write_data_sd[22] = \<const0> ;
  assign cfg_mgmt_write_data_sd[21] = \<const0> ;
  assign cfg_mgmt_write_data_sd[20] = \<const0> ;
  assign cfg_mgmt_write_data_sd[19] = \<const0> ;
  assign cfg_mgmt_write_data_sd[18] = \<const0> ;
  assign cfg_mgmt_write_data_sd[17] = \<const0> ;
  assign cfg_mgmt_write_data_sd[16] = \<const0> ;
  assign cfg_mgmt_write_data_sd[15] = \<const0> ;
  assign cfg_mgmt_write_data_sd[14] = \<const0> ;
  assign cfg_mgmt_write_data_sd[13] = \<const0> ;
  assign cfg_mgmt_write_data_sd[12] = \<const0> ;
  assign cfg_mgmt_write_data_sd[11] = \<const0> ;
  assign cfg_mgmt_write_data_sd[10] = \<const0> ;
  assign cfg_mgmt_write_data_sd[9] = \<const0> ;
  assign cfg_mgmt_write_data_sd[8] = \<const0> ;
  assign cfg_mgmt_write_data_sd[7] = \<const0> ;
  assign cfg_mgmt_write_data_sd[6] = \<const0> ;
  assign cfg_mgmt_write_data_sd[5] = \<const0> ;
  assign cfg_mgmt_write_data_sd[4] = \<const0> ;
  assign cfg_mgmt_write_data_sd[3] = \<const0> ;
  assign cfg_mgmt_write_data_sd[2] = \<const0> ;
  assign cfg_mgmt_write_data_sd[1] = \<const0> ;
  assign cfg_mgmt_write_data_sd[0] = \<const0> ;
  assign cfg_mgmt_write_sd = \<const0> ;
  assign cfg_msg_transmit_data_sd[31] = \<const0> ;
  assign cfg_msg_transmit_data_sd[30] = \<const0> ;
  assign cfg_msg_transmit_data_sd[29] = \<const0> ;
  assign cfg_msg_transmit_data_sd[28] = \<const0> ;
  assign cfg_msg_transmit_data_sd[27] = \<const0> ;
  assign cfg_msg_transmit_data_sd[26] = \<const0> ;
  assign cfg_msg_transmit_data_sd[25] = \<const0> ;
  assign cfg_msg_transmit_data_sd[24] = \<const0> ;
  assign cfg_msg_transmit_data_sd[23] = \<const0> ;
  assign cfg_msg_transmit_data_sd[22] = \<const0> ;
  assign cfg_msg_transmit_data_sd[21] = \<const0> ;
  assign cfg_msg_transmit_data_sd[20] = \<const0> ;
  assign cfg_msg_transmit_data_sd[19] = \<const0> ;
  assign cfg_msg_transmit_data_sd[18] = \<const0> ;
  assign cfg_msg_transmit_data_sd[17] = \<const0> ;
  assign cfg_msg_transmit_data_sd[16] = \<const0> ;
  assign cfg_msg_transmit_data_sd[15] = \<const0> ;
  assign cfg_msg_transmit_data_sd[14] = \<const0> ;
  assign cfg_msg_transmit_data_sd[13] = \<const0> ;
  assign cfg_msg_transmit_data_sd[12] = \<const0> ;
  assign cfg_msg_transmit_data_sd[11] = \<const0> ;
  assign cfg_msg_transmit_data_sd[10] = \<const0> ;
  assign cfg_msg_transmit_data_sd[9] = \<const0> ;
  assign cfg_msg_transmit_data_sd[8] = \<const0> ;
  assign cfg_msg_transmit_data_sd[7] = \<const0> ;
  assign cfg_msg_transmit_data_sd[6] = \<const0> ;
  assign cfg_msg_transmit_data_sd[5] = \<const0> ;
  assign cfg_msg_transmit_data_sd[4] = \<const0> ;
  assign cfg_msg_transmit_data_sd[3] = \<const0> ;
  assign cfg_msg_transmit_data_sd[2] = \<const0> ;
  assign cfg_msg_transmit_data_sd[1] = \<const0> ;
  assign cfg_msg_transmit_data_sd[0] = \<const0> ;
  assign cfg_msg_transmit_sd = \<const0> ;
  assign cfg_msg_transmit_type_sd[2] = \<const0> ;
  assign cfg_msg_transmit_type_sd[1] = \<const0> ;
  assign cfg_msg_transmit_type_sd[0] = \<const0> ;
  assign cfg_negotiated_width_o[3] = \<const0> ;
  assign cfg_negotiated_width_o[2] = \<const0> ;
  assign cfg_negotiated_width_o[1] = \<const0> ;
  assign cfg_negotiated_width_o[0] = \<const0> ;
  assign cfg_status_ats_en = \<const0> ;
  assign cfg_status_ats_stu[4] = \<const0> ;
  assign cfg_status_ats_stu[3] = \<const0> ;
  assign cfg_status_ats_stu[2] = \<const0> ;
  assign cfg_status_ats_stu[1] = \<const0> ;
  assign cfg_status_ats_stu[0] = \<const0> ;
  assign cfg_status_ost_pr_alloc[31] = \<const0> ;
  assign cfg_status_ost_pr_alloc[30] = \<const0> ;
  assign cfg_status_ost_pr_alloc[29] = \<const0> ;
  assign cfg_status_ost_pr_alloc[28] = \<const0> ;
  assign cfg_status_ost_pr_alloc[27] = \<const0> ;
  assign cfg_status_ost_pr_alloc[26] = \<const0> ;
  assign cfg_status_ost_pr_alloc[25] = \<const0> ;
  assign cfg_status_ost_pr_alloc[24] = \<const0> ;
  assign cfg_status_ost_pr_alloc[23] = \<const0> ;
  assign cfg_status_ost_pr_alloc[22] = \<const0> ;
  assign cfg_status_ost_pr_alloc[21] = \<const0> ;
  assign cfg_status_ost_pr_alloc[20] = \<const0> ;
  assign cfg_status_ost_pr_alloc[19] = \<const0> ;
  assign cfg_status_ost_pr_alloc[18] = \<const0> ;
  assign cfg_status_ost_pr_alloc[17] = \<const0> ;
  assign cfg_status_ost_pr_alloc[16] = \<const0> ;
  assign cfg_status_ost_pr_alloc[15] = \<const0> ;
  assign cfg_status_ost_pr_alloc[14] = \<const0> ;
  assign cfg_status_ost_pr_alloc[13] = \<const0> ;
  assign cfg_status_ost_pr_alloc[12] = \<const0> ;
  assign cfg_status_ost_pr_alloc[11] = \<const0> ;
  assign cfg_status_ost_pr_alloc[10] = \<const0> ;
  assign cfg_status_ost_pr_alloc[9] = \<const0> ;
  assign cfg_status_ost_pr_alloc[8] = \<const0> ;
  assign cfg_status_ost_pr_alloc[7] = \<const0> ;
  assign cfg_status_ost_pr_alloc[6] = \<const0> ;
  assign cfg_status_ost_pr_alloc[5] = \<const0> ;
  assign cfg_status_ost_pr_alloc[4] = \<const0> ;
  assign cfg_status_ost_pr_alloc[3] = \<const0> ;
  assign cfg_status_ost_pr_alloc[2] = \<const0> ;
  assign cfg_status_ost_pr_alloc[1] = \<const0> ;
  assign cfg_status_ost_pr_alloc[0] = \<const0> ;
  assign cfg_status_pr_en = \<const0> ;
  assign cfg_status_pr_rf = \<const0> ;
  assign cfg_status_pr_rst = \<const0> ;
  assign cfg_status_pr_uprgi = \<const0> ;
  assign cfg_vf_flr_in_process[251] = \<const0> ;
  assign cfg_vf_flr_in_process[250] = \<const0> ;
  assign cfg_vf_flr_in_process[249] = \<const0> ;
  assign cfg_vf_flr_in_process[248] = \<const0> ;
  assign cfg_vf_flr_in_process[247] = \<const0> ;
  assign cfg_vf_flr_in_process[246] = \<const0> ;
  assign cfg_vf_flr_in_process[245] = \<const0> ;
  assign cfg_vf_flr_in_process[244] = \<const0> ;
  assign cfg_vf_flr_in_process[243] = \<const0> ;
  assign cfg_vf_flr_in_process[242] = \<const0> ;
  assign cfg_vf_flr_in_process[241] = \<const0> ;
  assign cfg_vf_flr_in_process[240] = \<const0> ;
  assign cfg_vf_flr_in_process[239] = \<const0> ;
  assign cfg_vf_flr_in_process[238] = \<const0> ;
  assign cfg_vf_flr_in_process[237] = \<const0> ;
  assign cfg_vf_flr_in_process[236] = \<const0> ;
  assign cfg_vf_flr_in_process[235] = \<const0> ;
  assign cfg_vf_flr_in_process[234] = \<const0> ;
  assign cfg_vf_flr_in_process[233] = \<const0> ;
  assign cfg_vf_flr_in_process[232] = \<const0> ;
  assign cfg_vf_flr_in_process[231] = \<const0> ;
  assign cfg_vf_flr_in_process[230] = \<const0> ;
  assign cfg_vf_flr_in_process[229] = \<const0> ;
  assign cfg_vf_flr_in_process[228] = \<const0> ;
  assign cfg_vf_flr_in_process[227] = \<const0> ;
  assign cfg_vf_flr_in_process[226] = \<const0> ;
  assign cfg_vf_flr_in_process[225] = \<const0> ;
  assign cfg_vf_flr_in_process[224] = \<const0> ;
  assign cfg_vf_flr_in_process[223] = \<const0> ;
  assign cfg_vf_flr_in_process[222] = \<const0> ;
  assign cfg_vf_flr_in_process[221] = \<const0> ;
  assign cfg_vf_flr_in_process[220] = \<const0> ;
  assign cfg_vf_flr_in_process[219] = \<const0> ;
  assign cfg_vf_flr_in_process[218] = \<const0> ;
  assign cfg_vf_flr_in_process[217] = \<const0> ;
  assign cfg_vf_flr_in_process[216] = \<const0> ;
  assign cfg_vf_flr_in_process[215] = \<const0> ;
  assign cfg_vf_flr_in_process[214] = \<const0> ;
  assign cfg_vf_flr_in_process[213] = \<const0> ;
  assign cfg_vf_flr_in_process[212] = \<const0> ;
  assign cfg_vf_flr_in_process[211] = \<const0> ;
  assign cfg_vf_flr_in_process[210] = \<const0> ;
  assign cfg_vf_flr_in_process[209] = \<const0> ;
  assign cfg_vf_flr_in_process[208] = \<const0> ;
  assign cfg_vf_flr_in_process[207] = \<const0> ;
  assign cfg_vf_flr_in_process[206] = \<const0> ;
  assign cfg_vf_flr_in_process[205] = \<const0> ;
  assign cfg_vf_flr_in_process[204] = \<const0> ;
  assign cfg_vf_flr_in_process[203] = \<const0> ;
  assign cfg_vf_flr_in_process[202] = \<const0> ;
  assign cfg_vf_flr_in_process[201] = \<const0> ;
  assign cfg_vf_flr_in_process[200] = \<const0> ;
  assign cfg_vf_flr_in_process[199] = \<const0> ;
  assign cfg_vf_flr_in_process[198] = \<const0> ;
  assign cfg_vf_flr_in_process[197] = \<const0> ;
  assign cfg_vf_flr_in_process[196] = \<const0> ;
  assign cfg_vf_flr_in_process[195] = \<const0> ;
  assign cfg_vf_flr_in_process[194] = \<const0> ;
  assign cfg_vf_flr_in_process[193] = \<const0> ;
  assign cfg_vf_flr_in_process[192] = \<const0> ;
  assign cfg_vf_flr_in_process[191] = \<const0> ;
  assign cfg_vf_flr_in_process[190] = \<const0> ;
  assign cfg_vf_flr_in_process[189] = \<const0> ;
  assign cfg_vf_flr_in_process[188] = \<const0> ;
  assign cfg_vf_flr_in_process[187] = \<const0> ;
  assign cfg_vf_flr_in_process[186] = \<const0> ;
  assign cfg_vf_flr_in_process[185] = \<const0> ;
  assign cfg_vf_flr_in_process[184] = \<const0> ;
  assign cfg_vf_flr_in_process[183] = \<const0> ;
  assign cfg_vf_flr_in_process[182] = \<const0> ;
  assign cfg_vf_flr_in_process[181] = \<const0> ;
  assign cfg_vf_flr_in_process[180] = \<const0> ;
  assign cfg_vf_flr_in_process[179] = \<const0> ;
  assign cfg_vf_flr_in_process[178] = \<const0> ;
  assign cfg_vf_flr_in_process[177] = \<const0> ;
  assign cfg_vf_flr_in_process[176] = \<const0> ;
  assign cfg_vf_flr_in_process[175] = \<const0> ;
  assign cfg_vf_flr_in_process[174] = \<const0> ;
  assign cfg_vf_flr_in_process[173] = \<const0> ;
  assign cfg_vf_flr_in_process[172] = \<const0> ;
  assign cfg_vf_flr_in_process[171] = \<const0> ;
  assign cfg_vf_flr_in_process[170] = \<const0> ;
  assign cfg_vf_flr_in_process[169] = \<const0> ;
  assign cfg_vf_flr_in_process[168] = \<const0> ;
  assign cfg_vf_flr_in_process[167] = \<const0> ;
  assign cfg_vf_flr_in_process[166] = \<const0> ;
  assign cfg_vf_flr_in_process[165] = \<const0> ;
  assign cfg_vf_flr_in_process[164] = \<const0> ;
  assign cfg_vf_flr_in_process[163] = \<const0> ;
  assign cfg_vf_flr_in_process[162] = \<const0> ;
  assign cfg_vf_flr_in_process[161] = \<const0> ;
  assign cfg_vf_flr_in_process[160] = \<const0> ;
  assign cfg_vf_flr_in_process[159] = \<const0> ;
  assign cfg_vf_flr_in_process[158] = \<const0> ;
  assign cfg_vf_flr_in_process[157] = \<const0> ;
  assign cfg_vf_flr_in_process[156] = \<const0> ;
  assign cfg_vf_flr_in_process[155] = \<const0> ;
  assign cfg_vf_flr_in_process[154] = \<const0> ;
  assign cfg_vf_flr_in_process[153] = \<const0> ;
  assign cfg_vf_flr_in_process[152] = \<const0> ;
  assign cfg_vf_flr_in_process[151] = \<const0> ;
  assign cfg_vf_flr_in_process[150] = \<const0> ;
  assign cfg_vf_flr_in_process[149] = \<const0> ;
  assign cfg_vf_flr_in_process[148] = \<const0> ;
  assign cfg_vf_flr_in_process[147] = \<const0> ;
  assign cfg_vf_flr_in_process[146] = \<const0> ;
  assign cfg_vf_flr_in_process[145] = \<const0> ;
  assign cfg_vf_flr_in_process[144] = \<const0> ;
  assign cfg_vf_flr_in_process[143] = \<const0> ;
  assign cfg_vf_flr_in_process[142] = \<const0> ;
  assign cfg_vf_flr_in_process[141] = \<const0> ;
  assign cfg_vf_flr_in_process[140] = \<const0> ;
  assign cfg_vf_flr_in_process[139] = \<const0> ;
  assign cfg_vf_flr_in_process[138] = \<const0> ;
  assign cfg_vf_flr_in_process[137] = \<const0> ;
  assign cfg_vf_flr_in_process[136] = \<const0> ;
  assign cfg_vf_flr_in_process[135] = \<const0> ;
  assign cfg_vf_flr_in_process[134] = \<const0> ;
  assign cfg_vf_flr_in_process[133] = \<const0> ;
  assign cfg_vf_flr_in_process[132] = \<const0> ;
  assign cfg_vf_flr_in_process[131] = \<const0> ;
  assign cfg_vf_flr_in_process[130] = \<const0> ;
  assign cfg_vf_flr_in_process[129] = \<const0> ;
  assign cfg_vf_flr_in_process[128] = \<const0> ;
  assign cfg_vf_flr_in_process[127] = \<const0> ;
  assign cfg_vf_flr_in_process[126] = \<const0> ;
  assign cfg_vf_flr_in_process[125] = \<const0> ;
  assign cfg_vf_flr_in_process[124] = \<const0> ;
  assign cfg_vf_flr_in_process[123] = \<const0> ;
  assign cfg_vf_flr_in_process[122] = \<const0> ;
  assign cfg_vf_flr_in_process[121] = \<const0> ;
  assign cfg_vf_flr_in_process[120] = \<const0> ;
  assign cfg_vf_flr_in_process[119] = \<const0> ;
  assign cfg_vf_flr_in_process[118] = \<const0> ;
  assign cfg_vf_flr_in_process[117] = \<const0> ;
  assign cfg_vf_flr_in_process[116] = \<const0> ;
  assign cfg_vf_flr_in_process[115] = \<const0> ;
  assign cfg_vf_flr_in_process[114] = \<const0> ;
  assign cfg_vf_flr_in_process[113] = \<const0> ;
  assign cfg_vf_flr_in_process[112] = \<const0> ;
  assign cfg_vf_flr_in_process[111] = \<const0> ;
  assign cfg_vf_flr_in_process[110] = \<const0> ;
  assign cfg_vf_flr_in_process[109] = \<const0> ;
  assign cfg_vf_flr_in_process[108] = \<const0> ;
  assign cfg_vf_flr_in_process[107] = \<const0> ;
  assign cfg_vf_flr_in_process[106] = \<const0> ;
  assign cfg_vf_flr_in_process[105] = \<const0> ;
  assign cfg_vf_flr_in_process[104] = \<const0> ;
  assign cfg_vf_flr_in_process[103] = \<const0> ;
  assign cfg_vf_flr_in_process[102] = \<const0> ;
  assign cfg_vf_flr_in_process[101] = \<const0> ;
  assign cfg_vf_flr_in_process[100] = \<const0> ;
  assign cfg_vf_flr_in_process[99] = \<const0> ;
  assign cfg_vf_flr_in_process[98] = \<const0> ;
  assign cfg_vf_flr_in_process[97] = \<const0> ;
  assign cfg_vf_flr_in_process[96] = \<const0> ;
  assign cfg_vf_flr_in_process[95] = \<const0> ;
  assign cfg_vf_flr_in_process[94] = \<const0> ;
  assign cfg_vf_flr_in_process[93] = \<const0> ;
  assign cfg_vf_flr_in_process[92] = \<const0> ;
  assign cfg_vf_flr_in_process[91] = \<const0> ;
  assign cfg_vf_flr_in_process[90] = \<const0> ;
  assign cfg_vf_flr_in_process[89] = \<const0> ;
  assign cfg_vf_flr_in_process[88] = \<const0> ;
  assign cfg_vf_flr_in_process[87] = \<const0> ;
  assign cfg_vf_flr_in_process[86] = \<const0> ;
  assign cfg_vf_flr_in_process[85] = \<const0> ;
  assign cfg_vf_flr_in_process[84] = \<const0> ;
  assign cfg_vf_flr_in_process[83] = \<const0> ;
  assign cfg_vf_flr_in_process[82] = \<const0> ;
  assign cfg_vf_flr_in_process[81] = \<const0> ;
  assign cfg_vf_flr_in_process[80] = \<const0> ;
  assign cfg_vf_flr_in_process[79] = \<const0> ;
  assign cfg_vf_flr_in_process[78] = \<const0> ;
  assign cfg_vf_flr_in_process[77] = \<const0> ;
  assign cfg_vf_flr_in_process[76] = \<const0> ;
  assign cfg_vf_flr_in_process[75] = \<const0> ;
  assign cfg_vf_flr_in_process[74] = \<const0> ;
  assign cfg_vf_flr_in_process[73] = \<const0> ;
  assign cfg_vf_flr_in_process[72] = \<const0> ;
  assign cfg_vf_flr_in_process[71] = \<const0> ;
  assign cfg_vf_flr_in_process[70] = \<const0> ;
  assign cfg_vf_flr_in_process[69] = \<const0> ;
  assign cfg_vf_flr_in_process[68] = \<const0> ;
  assign cfg_vf_flr_in_process[67] = \<const0> ;
  assign cfg_vf_flr_in_process[66] = \<const0> ;
  assign cfg_vf_flr_in_process[65] = \<const0> ;
  assign cfg_vf_flr_in_process[64] = \<const0> ;
  assign cfg_vf_flr_in_process[63] = \<const0> ;
  assign cfg_vf_flr_in_process[62] = \<const0> ;
  assign cfg_vf_flr_in_process[61] = \<const0> ;
  assign cfg_vf_flr_in_process[60] = \<const0> ;
  assign cfg_vf_flr_in_process[59] = \<const0> ;
  assign cfg_vf_flr_in_process[58] = \<const0> ;
  assign cfg_vf_flr_in_process[57] = \<const0> ;
  assign cfg_vf_flr_in_process[56] = \<const0> ;
  assign cfg_vf_flr_in_process[55] = \<const0> ;
  assign cfg_vf_flr_in_process[54] = \<const0> ;
  assign cfg_vf_flr_in_process[53] = \<const0> ;
  assign cfg_vf_flr_in_process[52] = \<const0> ;
  assign cfg_vf_flr_in_process[51] = \<const0> ;
  assign cfg_vf_flr_in_process[50] = \<const0> ;
  assign cfg_vf_flr_in_process[49] = \<const0> ;
  assign cfg_vf_flr_in_process[48] = \<const0> ;
  assign cfg_vf_flr_in_process[47] = \<const0> ;
  assign cfg_vf_flr_in_process[46] = \<const0> ;
  assign cfg_vf_flr_in_process[45] = \<const0> ;
  assign cfg_vf_flr_in_process[44] = \<const0> ;
  assign cfg_vf_flr_in_process[43] = \<const0> ;
  assign cfg_vf_flr_in_process[42] = \<const0> ;
  assign cfg_vf_flr_in_process[41] = \<const0> ;
  assign cfg_vf_flr_in_process[40] = \<const0> ;
  assign cfg_vf_flr_in_process[39] = \<const0> ;
  assign cfg_vf_flr_in_process[38] = \<const0> ;
  assign cfg_vf_flr_in_process[37] = \<const0> ;
  assign cfg_vf_flr_in_process[36] = \<const0> ;
  assign cfg_vf_flr_in_process[35] = \<const0> ;
  assign cfg_vf_flr_in_process[34] = \<const0> ;
  assign cfg_vf_flr_in_process[33] = \<const0> ;
  assign cfg_vf_flr_in_process[32] = \<const0> ;
  assign cfg_vf_flr_in_process[31] = \<const0> ;
  assign cfg_vf_flr_in_process[30] = \<const0> ;
  assign cfg_vf_flr_in_process[29] = \<const0> ;
  assign cfg_vf_flr_in_process[28] = \<const0> ;
  assign cfg_vf_flr_in_process[27] = \<const0> ;
  assign cfg_vf_flr_in_process[26] = \<const0> ;
  assign cfg_vf_flr_in_process[25] = \<const0> ;
  assign cfg_vf_flr_in_process[24] = \<const0> ;
  assign cfg_vf_flr_in_process[23] = \<const0> ;
  assign cfg_vf_flr_in_process[22] = \<const0> ;
  assign cfg_vf_flr_in_process[21] = \<const0> ;
  assign cfg_vf_flr_in_process[20] = \<const0> ;
  assign cfg_vf_flr_in_process[19] = \<const0> ;
  assign cfg_vf_flr_in_process[18] = \<const0> ;
  assign cfg_vf_flr_in_process[17] = \<const0> ;
  assign cfg_vf_flr_in_process[16] = \<const0> ;
  assign cfg_vf_flr_in_process[15] = \<const0> ;
  assign cfg_vf_flr_in_process[14] = \<const0> ;
  assign cfg_vf_flr_in_process[13] = \<const0> ;
  assign cfg_vf_flr_in_process[12] = \<const0> ;
  assign cfg_vf_flr_in_process[11] = \<const0> ;
  assign cfg_vf_flr_in_process[10] = \<const0> ;
  assign cfg_vf_flr_in_process[9] = \<const0> ;
  assign cfg_vf_flr_in_process[8] = \<const0> ;
  assign cfg_vf_flr_in_process[7] = \<const0> ;
  assign cfg_vf_flr_in_process[6] = \<const0> ;
  assign cfg_vf_flr_in_process[5] = \<const0> ;
  assign cfg_vf_flr_in_process[4] = \<const0> ;
  assign cfg_vf_flr_in_process[3] = \<const0> ;
  assign cfg_vf_flr_in_process[2] = \<const0> ;
  assign cfg_vf_flr_in_process[1] = \<const0> ;
  assign cfg_vf_flr_in_process[0] = \<const0> ;
  assign common_commands_out[25] = \<const0> ;
  assign common_commands_out[24] = \<const0> ;
  assign common_commands_out[23] = \<const0> ;
  assign common_commands_out[22] = \<const0> ;
  assign common_commands_out[21] = \<const0> ;
  assign common_commands_out[20] = \<const0> ;
  assign common_commands_out[19] = \<const0> ;
  assign common_commands_out[18] = \<const0> ;
  assign common_commands_out[17] = \<const0> ;
  assign common_commands_out[16] = \<const0> ;
  assign common_commands_out[15] = \<const0> ;
  assign common_commands_out[14] = \<const0> ;
  assign common_commands_out[13] = \<const0> ;
  assign common_commands_out[12] = \<const0> ;
  assign common_commands_out[11] = \<const0> ;
  assign common_commands_out[10] = \<const0> ;
  assign common_commands_out[9] = \<const0> ;
  assign common_commands_out[8] = \<const0> ;
  assign common_commands_out[7] = \<const0> ;
  assign common_commands_out[6] = \<const0> ;
  assign common_commands_out[5] = \<const0> ;
  assign common_commands_out[4] = \<const0> ;
  assign common_commands_out[3] = \<const0> ;
  assign common_commands_out[2] = \<const0> ;
  assign common_commands_out[1] = \<const0> ;
  assign common_commands_out[0] = \<const0> ;
  assign core_clk = \<const0> ;
  assign cpllfreqlock_usp_in[1] = \<const0> ;
  assign cpllfreqlock_usp_in[0] = \<const0> ;
  assign cpllpd_us_in[1] = \<const0> ;
  assign cpllpd_us_in[0] = \<const0> ;
  assign cpllpd_usp_in[1] = \<const0> ;
  assign cpllpd_usp_in[0] = \<const0> ;
  assign cpllreset_us_in[1] = \<const0> ;
  assign cpllreset_us_in[0] = \<const0> ;
  assign cpllreset_usp_in[1] = \<const0> ;
  assign cpllreset_usp_in[0] = \<const0> ;
  assign cxs0_active_ack_tx = \<const0> ;
  assign cxs0_active_req_rx = \<const0> ;
  assign cxs0_cntl_chk_rx = \<const0> ;
  assign cxs0_cntl_rx[13] = \<const0> ;
  assign cxs0_cntl_rx[12] = \<const0> ;
  assign cxs0_cntl_rx[11] = \<const0> ;
  assign cxs0_cntl_rx[10] = \<const0> ;
  assign cxs0_cntl_rx[9] = \<const0> ;
  assign cxs0_cntl_rx[8] = \<const0> ;
  assign cxs0_cntl_rx[7] = \<const0> ;
  assign cxs0_cntl_rx[6] = \<const0> ;
  assign cxs0_cntl_rx[5] = \<const0> ;
  assign cxs0_cntl_rx[4] = \<const0> ;
  assign cxs0_cntl_rx[3] = \<const0> ;
  assign cxs0_cntl_rx[2] = \<const0> ;
  assign cxs0_cntl_rx[1] = \<const0> ;
  assign cxs0_cntl_rx[0] = \<const0> ;
  assign cxs0_crdgnt_chk_tx = \<const0> ;
  assign cxs0_crdgnt_tx = \<const0> ;
  assign cxs0_crdrtn_chk_rx = \<const0> ;
  assign cxs0_crdrtn_rx = \<const0> ;
  assign cxs0_data_chk_rx[31] = \<const0> ;
  assign cxs0_data_chk_rx[30] = \<const0> ;
  assign cxs0_data_chk_rx[29] = \<const0> ;
  assign cxs0_data_chk_rx[28] = \<const0> ;
  assign cxs0_data_chk_rx[27] = \<const0> ;
  assign cxs0_data_chk_rx[26] = \<const0> ;
  assign cxs0_data_chk_rx[25] = \<const0> ;
  assign cxs0_data_chk_rx[24] = \<const0> ;
  assign cxs0_data_chk_rx[23] = \<const0> ;
  assign cxs0_data_chk_rx[22] = \<const0> ;
  assign cxs0_data_chk_rx[21] = \<const0> ;
  assign cxs0_data_chk_rx[20] = \<const0> ;
  assign cxs0_data_chk_rx[19] = \<const0> ;
  assign cxs0_data_chk_rx[18] = \<const0> ;
  assign cxs0_data_chk_rx[17] = \<const0> ;
  assign cxs0_data_chk_rx[16] = \<const0> ;
  assign cxs0_data_chk_rx[15] = \<const0> ;
  assign cxs0_data_chk_rx[14] = \<const0> ;
  assign cxs0_data_chk_rx[13] = \<const0> ;
  assign cxs0_data_chk_rx[12] = \<const0> ;
  assign cxs0_data_chk_rx[11] = \<const0> ;
  assign cxs0_data_chk_rx[10] = \<const0> ;
  assign cxs0_data_chk_rx[9] = \<const0> ;
  assign cxs0_data_chk_rx[8] = \<const0> ;
  assign cxs0_data_chk_rx[7] = \<const0> ;
  assign cxs0_data_chk_rx[6] = \<const0> ;
  assign cxs0_data_chk_rx[5] = \<const0> ;
  assign cxs0_data_chk_rx[4] = \<const0> ;
  assign cxs0_data_chk_rx[3] = \<const0> ;
  assign cxs0_data_chk_rx[2] = \<const0> ;
  assign cxs0_data_chk_rx[1] = \<const0> ;
  assign cxs0_data_chk_rx[0] = \<const0> ;
  assign cxs0_data_rx[255] = \<const0> ;
  assign cxs0_data_rx[254] = \<const0> ;
  assign cxs0_data_rx[253] = \<const0> ;
  assign cxs0_data_rx[252] = \<const0> ;
  assign cxs0_data_rx[251] = \<const0> ;
  assign cxs0_data_rx[250] = \<const0> ;
  assign cxs0_data_rx[249] = \<const0> ;
  assign cxs0_data_rx[248] = \<const0> ;
  assign cxs0_data_rx[247] = \<const0> ;
  assign cxs0_data_rx[246] = \<const0> ;
  assign cxs0_data_rx[245] = \<const0> ;
  assign cxs0_data_rx[244] = \<const0> ;
  assign cxs0_data_rx[243] = \<const0> ;
  assign cxs0_data_rx[242] = \<const0> ;
  assign cxs0_data_rx[241] = \<const0> ;
  assign cxs0_data_rx[240] = \<const0> ;
  assign cxs0_data_rx[239] = \<const0> ;
  assign cxs0_data_rx[238] = \<const0> ;
  assign cxs0_data_rx[237] = \<const0> ;
  assign cxs0_data_rx[236] = \<const0> ;
  assign cxs0_data_rx[235] = \<const0> ;
  assign cxs0_data_rx[234] = \<const0> ;
  assign cxs0_data_rx[233] = \<const0> ;
  assign cxs0_data_rx[232] = \<const0> ;
  assign cxs0_data_rx[231] = \<const0> ;
  assign cxs0_data_rx[230] = \<const0> ;
  assign cxs0_data_rx[229] = \<const0> ;
  assign cxs0_data_rx[228] = \<const0> ;
  assign cxs0_data_rx[227] = \<const0> ;
  assign cxs0_data_rx[226] = \<const0> ;
  assign cxs0_data_rx[225] = \<const0> ;
  assign cxs0_data_rx[224] = \<const0> ;
  assign cxs0_data_rx[223] = \<const0> ;
  assign cxs0_data_rx[222] = \<const0> ;
  assign cxs0_data_rx[221] = \<const0> ;
  assign cxs0_data_rx[220] = \<const0> ;
  assign cxs0_data_rx[219] = \<const0> ;
  assign cxs0_data_rx[218] = \<const0> ;
  assign cxs0_data_rx[217] = \<const0> ;
  assign cxs0_data_rx[216] = \<const0> ;
  assign cxs0_data_rx[215] = \<const0> ;
  assign cxs0_data_rx[214] = \<const0> ;
  assign cxs0_data_rx[213] = \<const0> ;
  assign cxs0_data_rx[212] = \<const0> ;
  assign cxs0_data_rx[211] = \<const0> ;
  assign cxs0_data_rx[210] = \<const0> ;
  assign cxs0_data_rx[209] = \<const0> ;
  assign cxs0_data_rx[208] = \<const0> ;
  assign cxs0_data_rx[207] = \<const0> ;
  assign cxs0_data_rx[206] = \<const0> ;
  assign cxs0_data_rx[205] = \<const0> ;
  assign cxs0_data_rx[204] = \<const0> ;
  assign cxs0_data_rx[203] = \<const0> ;
  assign cxs0_data_rx[202] = \<const0> ;
  assign cxs0_data_rx[201] = \<const0> ;
  assign cxs0_data_rx[200] = \<const0> ;
  assign cxs0_data_rx[199] = \<const0> ;
  assign cxs0_data_rx[198] = \<const0> ;
  assign cxs0_data_rx[197] = \<const0> ;
  assign cxs0_data_rx[196] = \<const0> ;
  assign cxs0_data_rx[195] = \<const0> ;
  assign cxs0_data_rx[194] = \<const0> ;
  assign cxs0_data_rx[193] = \<const0> ;
  assign cxs0_data_rx[192] = \<const0> ;
  assign cxs0_data_rx[191] = \<const0> ;
  assign cxs0_data_rx[190] = \<const0> ;
  assign cxs0_data_rx[189] = \<const0> ;
  assign cxs0_data_rx[188] = \<const0> ;
  assign cxs0_data_rx[187] = \<const0> ;
  assign cxs0_data_rx[186] = \<const0> ;
  assign cxs0_data_rx[185] = \<const0> ;
  assign cxs0_data_rx[184] = \<const0> ;
  assign cxs0_data_rx[183] = \<const0> ;
  assign cxs0_data_rx[182] = \<const0> ;
  assign cxs0_data_rx[181] = \<const0> ;
  assign cxs0_data_rx[180] = \<const0> ;
  assign cxs0_data_rx[179] = \<const0> ;
  assign cxs0_data_rx[178] = \<const0> ;
  assign cxs0_data_rx[177] = \<const0> ;
  assign cxs0_data_rx[176] = \<const0> ;
  assign cxs0_data_rx[175] = \<const0> ;
  assign cxs0_data_rx[174] = \<const0> ;
  assign cxs0_data_rx[173] = \<const0> ;
  assign cxs0_data_rx[172] = \<const0> ;
  assign cxs0_data_rx[171] = \<const0> ;
  assign cxs0_data_rx[170] = \<const0> ;
  assign cxs0_data_rx[169] = \<const0> ;
  assign cxs0_data_rx[168] = \<const0> ;
  assign cxs0_data_rx[167] = \<const0> ;
  assign cxs0_data_rx[166] = \<const0> ;
  assign cxs0_data_rx[165] = \<const0> ;
  assign cxs0_data_rx[164] = \<const0> ;
  assign cxs0_data_rx[163] = \<const0> ;
  assign cxs0_data_rx[162] = \<const0> ;
  assign cxs0_data_rx[161] = \<const0> ;
  assign cxs0_data_rx[160] = \<const0> ;
  assign cxs0_data_rx[159] = \<const0> ;
  assign cxs0_data_rx[158] = \<const0> ;
  assign cxs0_data_rx[157] = \<const0> ;
  assign cxs0_data_rx[156] = \<const0> ;
  assign cxs0_data_rx[155] = \<const0> ;
  assign cxs0_data_rx[154] = \<const0> ;
  assign cxs0_data_rx[153] = \<const0> ;
  assign cxs0_data_rx[152] = \<const0> ;
  assign cxs0_data_rx[151] = \<const0> ;
  assign cxs0_data_rx[150] = \<const0> ;
  assign cxs0_data_rx[149] = \<const0> ;
  assign cxs0_data_rx[148] = \<const0> ;
  assign cxs0_data_rx[147] = \<const0> ;
  assign cxs0_data_rx[146] = \<const0> ;
  assign cxs0_data_rx[145] = \<const0> ;
  assign cxs0_data_rx[144] = \<const0> ;
  assign cxs0_data_rx[143] = \<const0> ;
  assign cxs0_data_rx[142] = \<const0> ;
  assign cxs0_data_rx[141] = \<const0> ;
  assign cxs0_data_rx[140] = \<const0> ;
  assign cxs0_data_rx[139] = \<const0> ;
  assign cxs0_data_rx[138] = \<const0> ;
  assign cxs0_data_rx[137] = \<const0> ;
  assign cxs0_data_rx[136] = \<const0> ;
  assign cxs0_data_rx[135] = \<const0> ;
  assign cxs0_data_rx[134] = \<const0> ;
  assign cxs0_data_rx[133] = \<const0> ;
  assign cxs0_data_rx[132] = \<const0> ;
  assign cxs0_data_rx[131] = \<const0> ;
  assign cxs0_data_rx[130] = \<const0> ;
  assign cxs0_data_rx[129] = \<const0> ;
  assign cxs0_data_rx[128] = \<const0> ;
  assign cxs0_data_rx[127] = \<const0> ;
  assign cxs0_data_rx[126] = \<const0> ;
  assign cxs0_data_rx[125] = \<const0> ;
  assign cxs0_data_rx[124] = \<const0> ;
  assign cxs0_data_rx[123] = \<const0> ;
  assign cxs0_data_rx[122] = \<const0> ;
  assign cxs0_data_rx[121] = \<const0> ;
  assign cxs0_data_rx[120] = \<const0> ;
  assign cxs0_data_rx[119] = \<const0> ;
  assign cxs0_data_rx[118] = \<const0> ;
  assign cxs0_data_rx[117] = \<const0> ;
  assign cxs0_data_rx[116] = \<const0> ;
  assign cxs0_data_rx[115] = \<const0> ;
  assign cxs0_data_rx[114] = \<const0> ;
  assign cxs0_data_rx[113] = \<const0> ;
  assign cxs0_data_rx[112] = \<const0> ;
  assign cxs0_data_rx[111] = \<const0> ;
  assign cxs0_data_rx[110] = \<const0> ;
  assign cxs0_data_rx[109] = \<const0> ;
  assign cxs0_data_rx[108] = \<const0> ;
  assign cxs0_data_rx[107] = \<const0> ;
  assign cxs0_data_rx[106] = \<const0> ;
  assign cxs0_data_rx[105] = \<const0> ;
  assign cxs0_data_rx[104] = \<const0> ;
  assign cxs0_data_rx[103] = \<const0> ;
  assign cxs0_data_rx[102] = \<const0> ;
  assign cxs0_data_rx[101] = \<const0> ;
  assign cxs0_data_rx[100] = \<const0> ;
  assign cxs0_data_rx[99] = \<const0> ;
  assign cxs0_data_rx[98] = \<const0> ;
  assign cxs0_data_rx[97] = \<const0> ;
  assign cxs0_data_rx[96] = \<const0> ;
  assign cxs0_data_rx[95] = \<const0> ;
  assign cxs0_data_rx[94] = \<const0> ;
  assign cxs0_data_rx[93] = \<const0> ;
  assign cxs0_data_rx[92] = \<const0> ;
  assign cxs0_data_rx[91] = \<const0> ;
  assign cxs0_data_rx[90] = \<const0> ;
  assign cxs0_data_rx[89] = \<const0> ;
  assign cxs0_data_rx[88] = \<const0> ;
  assign cxs0_data_rx[87] = \<const0> ;
  assign cxs0_data_rx[86] = \<const0> ;
  assign cxs0_data_rx[85] = \<const0> ;
  assign cxs0_data_rx[84] = \<const0> ;
  assign cxs0_data_rx[83] = \<const0> ;
  assign cxs0_data_rx[82] = \<const0> ;
  assign cxs0_data_rx[81] = \<const0> ;
  assign cxs0_data_rx[80] = \<const0> ;
  assign cxs0_data_rx[79] = \<const0> ;
  assign cxs0_data_rx[78] = \<const0> ;
  assign cxs0_data_rx[77] = \<const0> ;
  assign cxs0_data_rx[76] = \<const0> ;
  assign cxs0_data_rx[75] = \<const0> ;
  assign cxs0_data_rx[74] = \<const0> ;
  assign cxs0_data_rx[73] = \<const0> ;
  assign cxs0_data_rx[72] = \<const0> ;
  assign cxs0_data_rx[71] = \<const0> ;
  assign cxs0_data_rx[70] = \<const0> ;
  assign cxs0_data_rx[69] = \<const0> ;
  assign cxs0_data_rx[68] = \<const0> ;
  assign cxs0_data_rx[67] = \<const0> ;
  assign cxs0_data_rx[66] = \<const0> ;
  assign cxs0_data_rx[65] = \<const0> ;
  assign cxs0_data_rx[64] = \<const0> ;
  assign cxs0_data_rx[63] = \<const0> ;
  assign cxs0_data_rx[62] = \<const0> ;
  assign cxs0_data_rx[61] = \<const0> ;
  assign cxs0_data_rx[60] = \<const0> ;
  assign cxs0_data_rx[59] = \<const0> ;
  assign cxs0_data_rx[58] = \<const0> ;
  assign cxs0_data_rx[57] = \<const0> ;
  assign cxs0_data_rx[56] = \<const0> ;
  assign cxs0_data_rx[55] = \<const0> ;
  assign cxs0_data_rx[54] = \<const0> ;
  assign cxs0_data_rx[53] = \<const0> ;
  assign cxs0_data_rx[52] = \<const0> ;
  assign cxs0_data_rx[51] = \<const0> ;
  assign cxs0_data_rx[50] = \<const0> ;
  assign cxs0_data_rx[49] = \<const0> ;
  assign cxs0_data_rx[48] = \<const0> ;
  assign cxs0_data_rx[47] = \<const0> ;
  assign cxs0_data_rx[46] = \<const0> ;
  assign cxs0_data_rx[45] = \<const0> ;
  assign cxs0_data_rx[44] = \<const0> ;
  assign cxs0_data_rx[43] = \<const0> ;
  assign cxs0_data_rx[42] = \<const0> ;
  assign cxs0_data_rx[41] = \<const0> ;
  assign cxs0_data_rx[40] = \<const0> ;
  assign cxs0_data_rx[39] = \<const0> ;
  assign cxs0_data_rx[38] = \<const0> ;
  assign cxs0_data_rx[37] = \<const0> ;
  assign cxs0_data_rx[36] = \<const0> ;
  assign cxs0_data_rx[35] = \<const0> ;
  assign cxs0_data_rx[34] = \<const0> ;
  assign cxs0_data_rx[33] = \<const0> ;
  assign cxs0_data_rx[32] = \<const0> ;
  assign cxs0_data_rx[31] = \<const0> ;
  assign cxs0_data_rx[30] = \<const0> ;
  assign cxs0_data_rx[29] = \<const0> ;
  assign cxs0_data_rx[28] = \<const0> ;
  assign cxs0_data_rx[27] = \<const0> ;
  assign cxs0_data_rx[26] = \<const0> ;
  assign cxs0_data_rx[25] = \<const0> ;
  assign cxs0_data_rx[24] = \<const0> ;
  assign cxs0_data_rx[23] = \<const0> ;
  assign cxs0_data_rx[22] = \<const0> ;
  assign cxs0_data_rx[21] = \<const0> ;
  assign cxs0_data_rx[20] = \<const0> ;
  assign cxs0_data_rx[19] = \<const0> ;
  assign cxs0_data_rx[18] = \<const0> ;
  assign cxs0_data_rx[17] = \<const0> ;
  assign cxs0_data_rx[16] = \<const0> ;
  assign cxs0_data_rx[15] = \<const0> ;
  assign cxs0_data_rx[14] = \<const0> ;
  assign cxs0_data_rx[13] = \<const0> ;
  assign cxs0_data_rx[12] = \<const0> ;
  assign cxs0_data_rx[11] = \<const0> ;
  assign cxs0_data_rx[10] = \<const0> ;
  assign cxs0_data_rx[9] = \<const0> ;
  assign cxs0_data_rx[8] = \<const0> ;
  assign cxs0_data_rx[7] = \<const0> ;
  assign cxs0_data_rx[6] = \<const0> ;
  assign cxs0_data_rx[5] = \<const0> ;
  assign cxs0_data_rx[4] = \<const0> ;
  assign cxs0_data_rx[3] = \<const0> ;
  assign cxs0_data_rx[2] = \<const0> ;
  assign cxs0_data_rx[1] = \<const0> ;
  assign cxs0_data_rx[0] = \<const0> ;
  assign cxs0_deact_hint_tx = \<const0> ;
  assign cxs0_valid_chk_rx = \<const0> ;
  assign cxs0_valid_rx = \<const0> ;
  assign dmonfiforeset_us_in[1] = \<const0> ;
  assign dmonfiforeset_us_in[0] = \<const0> ;
  assign dmonfiforeset_usp_in[1] = \<const0> ;
  assign dmonfiforeset_usp_in[0] = \<const0> ;
  assign dmonitorclk_us_in[1] = \<const0> ;
  assign dmonitorclk_us_in[0] = \<const0> ;
  assign dmonitorclk_usp_in[1] = \<const0> ;
  assign dmonitorclk_usp_in[0] = \<const0> ;
  assign drp_do[15] = \<const0> ;
  assign drp_do[14] = \<const0> ;
  assign drp_do[13] = \<const0> ;
  assign drp_do[12] = \<const0> ;
  assign drp_do[11] = \<const0> ;
  assign drp_do[10] = \<const0> ;
  assign drp_do[9] = \<const0> ;
  assign drp_do[8] = \<const0> ;
  assign drp_do[7] = \<const0> ;
  assign drp_do[6] = \<const0> ;
  assign drp_do[5] = \<const0> ;
  assign drp_do[4] = \<const0> ;
  assign drp_do[3] = \<const0> ;
  assign drp_do[2] = \<const0> ;
  assign drp_do[1] = \<const0> ;
  assign drp_do[0] = \<const0> ;
  assign drp_rdy = \<const0> ;
  assign drpaddr_us_in[17] = \<const0> ;
  assign drpaddr_us_in[16] = \<const0> ;
  assign drpaddr_us_in[15] = \<const0> ;
  assign drpaddr_us_in[14] = \<const0> ;
  assign drpaddr_us_in[13] = \<const0> ;
  assign drpaddr_us_in[12] = \<const0> ;
  assign drpaddr_us_in[11] = \<const0> ;
  assign drpaddr_us_in[10] = \<const0> ;
  assign drpaddr_us_in[9] = \<const0> ;
  assign drpaddr_us_in[8] = \<const0> ;
  assign drpaddr_us_in[7] = \<const0> ;
  assign drpaddr_us_in[6] = \<const0> ;
  assign drpaddr_us_in[5] = \<const0> ;
  assign drpaddr_us_in[4] = \<const0> ;
  assign drpaddr_us_in[3] = \<const0> ;
  assign drpaddr_us_in[2] = \<const0> ;
  assign drpaddr_us_in[1] = \<const0> ;
  assign drpaddr_us_in[0] = \<const0> ;
  assign drpaddr_usp_in[19] = \<const0> ;
  assign drpaddr_usp_in[18] = \<const0> ;
  assign drpaddr_usp_in[17] = \<const0> ;
  assign drpaddr_usp_in[16] = \<const0> ;
  assign drpaddr_usp_in[15] = \<const0> ;
  assign drpaddr_usp_in[14] = \<const0> ;
  assign drpaddr_usp_in[13] = \<const0> ;
  assign drpaddr_usp_in[12] = \<const0> ;
  assign drpaddr_usp_in[11] = \<const0> ;
  assign drpaddr_usp_in[10] = \<const0> ;
  assign drpaddr_usp_in[9] = \<const0> ;
  assign drpaddr_usp_in[8] = \<const0> ;
  assign drpaddr_usp_in[7] = \<const0> ;
  assign drpaddr_usp_in[6] = \<const0> ;
  assign drpaddr_usp_in[5] = \<const0> ;
  assign drpaddr_usp_in[4] = \<const0> ;
  assign drpaddr_usp_in[3] = \<const0> ;
  assign drpaddr_usp_in[2] = \<const0> ;
  assign drpaddr_usp_in[1] = \<const0> ;
  assign drpaddr_usp_in[0] = \<const0> ;
  assign drpclk_us_in[1] = \<const0> ;
  assign drpclk_us_in[0] = \<const0> ;
  assign drpclk_usp_in = \<const0> ;
  assign drpdi_us_in[31] = \<const0> ;
  assign drpdi_us_in[30] = \<const0> ;
  assign drpdi_us_in[29] = \<const0> ;
  assign drpdi_us_in[28] = \<const0> ;
  assign drpdi_us_in[27] = \<const0> ;
  assign drpdi_us_in[26] = \<const0> ;
  assign drpdi_us_in[25] = \<const0> ;
  assign drpdi_us_in[24] = \<const0> ;
  assign drpdi_us_in[23] = \<const0> ;
  assign drpdi_us_in[22] = \<const0> ;
  assign drpdi_us_in[21] = \<const0> ;
  assign drpdi_us_in[20] = \<const0> ;
  assign drpdi_us_in[19] = \<const0> ;
  assign drpdi_us_in[18] = \<const0> ;
  assign drpdi_us_in[17] = \<const0> ;
  assign drpdi_us_in[16] = \<const0> ;
  assign drpdi_us_in[15] = \<const0> ;
  assign drpdi_us_in[14] = \<const0> ;
  assign drpdi_us_in[13] = \<const0> ;
  assign drpdi_us_in[12] = \<const0> ;
  assign drpdi_us_in[11] = \<const0> ;
  assign drpdi_us_in[10] = \<const0> ;
  assign drpdi_us_in[9] = \<const0> ;
  assign drpdi_us_in[8] = \<const0> ;
  assign drpdi_us_in[7] = \<const0> ;
  assign drpdi_us_in[6] = \<const0> ;
  assign drpdi_us_in[5] = \<const0> ;
  assign drpdi_us_in[4] = \<const0> ;
  assign drpdi_us_in[3] = \<const0> ;
  assign drpdi_us_in[2] = \<const0> ;
  assign drpdi_us_in[1] = \<const0> ;
  assign drpdi_us_in[0] = \<const0> ;
  assign drpdi_usp_in[31] = \<const0> ;
  assign drpdi_usp_in[30] = \<const0> ;
  assign drpdi_usp_in[29] = \<const0> ;
  assign drpdi_usp_in[28] = \<const0> ;
  assign drpdi_usp_in[27] = \<const0> ;
  assign drpdi_usp_in[26] = \<const0> ;
  assign drpdi_usp_in[25] = \<const0> ;
  assign drpdi_usp_in[24] = \<const0> ;
  assign drpdi_usp_in[23] = \<const0> ;
  assign drpdi_usp_in[22] = \<const0> ;
  assign drpdi_usp_in[21] = \<const0> ;
  assign drpdi_usp_in[20] = \<const0> ;
  assign drpdi_usp_in[19] = \<const0> ;
  assign drpdi_usp_in[18] = \<const0> ;
  assign drpdi_usp_in[17] = \<const0> ;
  assign drpdi_usp_in[16] = \<const0> ;
  assign drpdi_usp_in[15] = \<const0> ;
  assign drpdi_usp_in[14] = \<const0> ;
  assign drpdi_usp_in[13] = \<const0> ;
  assign drpdi_usp_in[12] = \<const0> ;
  assign drpdi_usp_in[11] = \<const0> ;
  assign drpdi_usp_in[10] = \<const0> ;
  assign drpdi_usp_in[9] = \<const0> ;
  assign drpdi_usp_in[8] = \<const0> ;
  assign drpdi_usp_in[7] = \<const0> ;
  assign drpdi_usp_in[6] = \<const0> ;
  assign drpdi_usp_in[5] = \<const0> ;
  assign drpdi_usp_in[4] = \<const0> ;
  assign drpdi_usp_in[3] = \<const0> ;
  assign drpdi_usp_in[2] = \<const0> ;
  assign drpdi_usp_in[1] = \<const0> ;
  assign drpdi_usp_in[0] = \<const0> ;
  assign drpen_us_in[1] = \<const0> ;
  assign drpen_us_in[0] = \<const0> ;
  assign drpen_usp_in[1] = \<const0> ;
  assign drpen_usp_in[0] = \<const0> ;
  assign drprst_usp_in[1] = \<const0> ;
  assign drprst_usp_in[0] = \<const0> ;
  assign drpwe_us_in[1] = \<const0> ;
  assign drpwe_us_in[0] = \<const0> ;
  assign drpwe_usp_in[1] = \<const0> ;
  assign drpwe_usp_in[0] = \<const0> ;
  assign ext_ch_gt_drpclk = \<const0> ;
  assign ext_ch_gt_drpdo[31] = \<const0> ;
  assign ext_ch_gt_drpdo[30] = \<const0> ;
  assign ext_ch_gt_drpdo[29] = \<const0> ;
  assign ext_ch_gt_drpdo[28] = \<const0> ;
  assign ext_ch_gt_drpdo[27] = \<const0> ;
  assign ext_ch_gt_drpdo[26] = \<const0> ;
  assign ext_ch_gt_drpdo[25] = \<const0> ;
  assign ext_ch_gt_drpdo[24] = \<const0> ;
  assign ext_ch_gt_drpdo[23] = \<const0> ;
  assign ext_ch_gt_drpdo[22] = \<const0> ;
  assign ext_ch_gt_drpdo[21] = \<const0> ;
  assign ext_ch_gt_drpdo[20] = \<const0> ;
  assign ext_ch_gt_drpdo[19] = \<const0> ;
  assign ext_ch_gt_drpdo[18] = \<const0> ;
  assign ext_ch_gt_drpdo[17] = \<const0> ;
  assign ext_ch_gt_drpdo[16] = \<const0> ;
  assign ext_ch_gt_drpdo[15] = \<const0> ;
  assign ext_ch_gt_drpdo[14] = \<const0> ;
  assign ext_ch_gt_drpdo[13] = \<const0> ;
  assign ext_ch_gt_drpdo[12] = \<const0> ;
  assign ext_ch_gt_drpdo[11] = \<const0> ;
  assign ext_ch_gt_drpdo[10] = \<const0> ;
  assign ext_ch_gt_drpdo[9] = \<const0> ;
  assign ext_ch_gt_drpdo[8] = \<const0> ;
  assign ext_ch_gt_drpdo[7] = \<const0> ;
  assign ext_ch_gt_drpdo[6] = \<const0> ;
  assign ext_ch_gt_drpdo[5] = \<const0> ;
  assign ext_ch_gt_drpdo[4] = \<const0> ;
  assign ext_ch_gt_drpdo[3] = \<const0> ;
  assign ext_ch_gt_drpdo[2] = \<const0> ;
  assign ext_ch_gt_drpdo[1] = \<const0> ;
  assign ext_ch_gt_drpdo[0] = \<const0> ;
  assign ext_ch_gt_drprdy[1] = \<const0> ;
  assign ext_ch_gt_drprdy[0] = \<const0> ;
  assign ext_phy_clk_bufg_gt_ce = \<const0> ;
  assign ext_phy_clk_bufg_gt_reset = \<const0> ;
  assign ext_phy_clk_bufgtcemask = \<const0> ;
  assign ext_phy_clk_bufgtdiv[8] = \<const0> ;
  assign ext_phy_clk_bufgtdiv[7] = \<const0> ;
  assign ext_phy_clk_bufgtdiv[6] = \<const0> ;
  assign ext_phy_clk_bufgtdiv[5] = \<const0> ;
  assign ext_phy_clk_bufgtdiv[4] = \<const0> ;
  assign ext_phy_clk_bufgtdiv[3] = \<const0> ;
  assign ext_phy_clk_bufgtdiv[2] = \<const0> ;
  assign ext_phy_clk_bufgtdiv[1] = \<const0> ;
  assign ext_phy_clk_bufgtdiv[0] = \<const0> ;
  assign ext_phy_clk_gt_bufgtrstmask = \<const0> ;
  assign ext_phy_clk_rst_idle = \<const0> ;
  assign ext_phy_clk_txoutclk = \<const0> ;
  assign ext_qpll1pd[0] = \<const0> ;
  assign ext_qpll1rate[2] = \<const0> ;
  assign ext_qpll1rate[1] = \<const0> ;
  assign ext_qpll1rate[0] = \<const0> ;
  assign ext_qpll1refclk[0] = \<const0> ;
  assign ext_qpll1reset[0] = \<const0> ;
  assign ext_usp_qpll0pd[0] = \<const0> ;
  assign ext_usp_qpll0reset[0] = \<const0> ;
  assign ext_usp_qpll1pd[0] = \<const0> ;
  assign ext_usp_qpll1reset[0] = \<const0> ;
  assign ext_usp_qpllxrate[2] = \<const0> ;
  assign ext_usp_qpllxrate[1] = \<const0> ;
  assign ext_usp_qpllxrate[0] = \<const0> ;
  assign ext_usp_qpllxrcalenb = \<const0> ;
  assign ext_usp_qpllxrefclk[0] = \<const0> ;
  assign eyescanreset_us_in[1] = \<const0> ;
  assign eyescanreset_us_in[0] = \<const0> ;
  assign eyescanreset_usp_in[1] = \<const0> ;
  assign eyescanreset_usp_in[0] = \<const0> ;
  assign gt_bufgtdiv[8] = \<const0> ;
  assign gt_bufgtdiv[7] = \<const0> ;
  assign gt_bufgtdiv[6] = \<const0> ;
  assign gt_bufgtdiv[5] = \<const0> ;
  assign gt_bufgtdiv[4] = \<const0> ;
  assign gt_bufgtdiv[3] = \<const0> ;
  assign gt_bufgtdiv[2] = \<const0> ;
  assign gt_bufgtdiv[1] = \<const0> ;
  assign gt_bufgtdiv[0] = \<const0> ;
  assign gt_ch_drp_rdy[1] = \<const0> ;
  assign gt_ch_drp_rdy[0] = \<const0> ;
  assign gt_cplllock[1] = \<const0> ;
  assign gt_cplllock[0] = \<const0> ;
  assign gt_dmonitorout[33] = \<const0> ;
  assign gt_dmonitorout[32] = \<const0> ;
  assign gt_dmonitorout[31] = \<const0> ;
  assign gt_dmonitorout[30] = \<const0> ;
  assign gt_dmonitorout[29] = \<const0> ;
  assign gt_dmonitorout[28] = \<const0> ;
  assign gt_dmonitorout[27] = \<const0> ;
  assign gt_dmonitorout[26] = \<const0> ;
  assign gt_dmonitorout[25] = \<const0> ;
  assign gt_dmonitorout[24] = \<const0> ;
  assign gt_dmonitorout[23] = \<const0> ;
  assign gt_dmonitorout[22] = \<const0> ;
  assign gt_dmonitorout[21] = \<const0> ;
  assign gt_dmonitorout[20] = \<const0> ;
  assign gt_dmonitorout[19] = \<const0> ;
  assign gt_dmonitorout[18] = \<const0> ;
  assign gt_dmonitorout[17] = \<const0> ;
  assign gt_dmonitorout[16] = \<const0> ;
  assign gt_dmonitorout[15] = \<const0> ;
  assign gt_dmonitorout[14] = \<const0> ;
  assign gt_dmonitorout[13] = \<const0> ;
  assign gt_dmonitorout[12] = \<const0> ;
  assign gt_dmonitorout[11] = \<const0> ;
  assign gt_dmonitorout[10] = \<const0> ;
  assign gt_dmonitorout[9] = \<const0> ;
  assign gt_dmonitorout[8] = \<const0> ;
  assign gt_dmonitorout[7] = \<const0> ;
  assign gt_dmonitorout[6] = \<const0> ;
  assign gt_dmonitorout[5] = \<const0> ;
  assign gt_dmonitorout[4] = \<const0> ;
  assign gt_dmonitorout[3] = \<const0> ;
  assign gt_dmonitorout[2] = \<const0> ;
  assign gt_dmonitorout[1] = \<const0> ;
  assign gt_dmonitorout[0] = \<const0> ;
  assign gt_drp_clk = \<const0> ;
  assign gt_eyescandataerror[1] = \<const0> ;
  assign gt_eyescandataerror[0] = \<const0> ;
  assign gt_gen34_eios_det[1] = \<const0> ;
  assign gt_gen34_eios_det[0] = \<const0> ;
  assign gt_gtpowergood[1] = \<const0> ;
  assign gt_gtpowergood[0] = \<const0> ;
  assign gt_pcierateidle[1] = \<const0> ;
  assign gt_pcierateidle[0] = \<const0> ;
  assign gt_pcieuserratestart[1] = \<const0> ;
  assign gt_pcieuserratestart[0] = \<const0> ;
  assign gt_phystatus[1] = \<const0> ;
  assign gt_phystatus[0] = \<const0> ;
  assign gt_qpll0lock[0] = \<const0> ;
  assign gt_qpll1lock[0] = \<const0> ;
  assign gt_rxbufstatus[5] = \<const0> ;
  assign gt_rxbufstatus[4] = \<const0> ;
  assign gt_rxbufstatus[3] = \<const0> ;
  assign gt_rxbufstatus[2] = \<const0> ;
  assign gt_rxbufstatus[1] = \<const0> ;
  assign gt_rxbufstatus[0] = \<const0> ;
  assign gt_rxcdrlock[1] = \<const0> ;
  assign gt_rxcdrlock[0] = \<const0> ;
  assign gt_rxcommadet[1] = \<const0> ;
  assign gt_rxcommadet[0] = \<const0> ;
  assign gt_rxdlysresetdone[1] = \<const0> ;
  assign gt_rxdlysresetdone[0] = \<const0> ;
  assign gt_rxoutclk[1] = \<const0> ;
  assign gt_rxoutclk[0] = \<const0> ;
  assign gt_rxoutclkfabric[1] = \<const0> ;
  assign gt_rxoutclkfabric[0] = \<const0> ;
  assign gt_rxoutclkpcs[1] = \<const0> ;
  assign gt_rxoutclkpcs[0] = \<const0> ;
  assign gt_rxphaligndone[1] = \<const0> ;
  assign gt_rxphaligndone[0] = \<const0> ;
  assign gt_rxpmaresetdone[1] = \<const0> ;
  assign gt_rxpmaresetdone[0] = \<const0> ;
  assign gt_rxprbserr[1] = \<const0> ;
  assign gt_rxprbserr[0] = \<const0> ;
  assign gt_rxprbslocked[1] = \<const0> ;
  assign gt_rxprbslocked[0] = \<const0> ;
  assign gt_rxrecclkout[1] = \<const0> ;
  assign gt_rxrecclkout[0] = \<const0> ;
  assign gt_rxresetdone[1] = \<const0> ;
  assign gt_rxresetdone[0] = \<const0> ;
  assign gt_rxstatus[5] = \<const0> ;
  assign gt_rxstatus[4] = \<const0> ;
  assign gt_rxstatus[3] = \<const0> ;
  assign gt_rxstatus[2] = \<const0> ;
  assign gt_rxstatus[1] = \<const0> ;
  assign gt_rxstatus[0] = \<const0> ;
  assign gt_rxsyncdone[1] = \<const0> ;
  assign gt_rxsyncdone[0] = \<const0> ;
  assign gt_rxvalid[1] = \<const0> ;
  assign gt_rxvalid[0] = \<const0> ;
  assign gt_txdlysresetdone[1] = \<const0> ;
  assign gt_txdlysresetdone[0] = \<const0> ;
  assign gt_txelecidle[1] = \<const0> ;
  assign gt_txelecidle[0] = \<const0> ;
  assign gt_txoutclk[1] = \<const0> ;
  assign gt_txoutclk[0] = \<const0> ;
  assign gt_txoutclkfabric[1] = \<const0> ;
  assign gt_txoutclkfabric[0] = \<const0> ;
  assign gt_txoutclkpcs[1] = \<const0> ;
  assign gt_txoutclkpcs[0] = \<const0> ;
  assign gt_txphaligndone[1] = \<const0> ;
  assign gt_txphaligndone[0] = \<const0> ;
  assign gt_txphinitdone[1] = \<const0> ;
  assign gt_txphinitdone[0] = \<const0> ;
  assign gt_txpmaresetdone[1] = \<const0> ;
  assign gt_txpmaresetdone[0] = \<const0> ;
  assign gt_txprogdivresetdone[1] = \<const0> ;
  assign gt_txprogdivresetdone[0] = \<const0> ;
  assign gt_txresetdone[1] = \<const0> ;
  assign gt_txresetdone[0] = \<const0> ;
  assign gt_txsyncdone[1] = \<const0> ;
  assign gt_txsyncdone[0] = \<const0> ;
  assign gthrxn_us_in[1] = \<const0> ;
  assign gthrxn_us_in[0] = \<const0> ;
  assign gthrxp_us_in[1] = \<const0> ;
  assign gthrxp_us_in[0] = \<const0> ;
  assign gtrefclk00_usp_in[0] = \<const0> ;
  assign gtrefclk01_us_in[0] = \<const0> ;
  assign gtrefclk01_usp_in[0] = \<const0> ;
  assign gtrefclk0_us_in[1] = \<const0> ;
  assign gtrefclk0_us_in[0] = \<const0> ;
  assign gtrefclk0_usp_in[1] = \<const0> ;
  assign gtrefclk0_usp_in[0] = \<const0> ;
  assign gtrxreset_us_in[1] = \<const0> ;
  assign gtrxreset_us_in[0] = \<const0> ;
  assign gtrxreset_usp_in[1] = \<const0> ;
  assign gtrxreset_usp_in[0] = \<const0> ;
  assign gttxreset_us_in[1] = \<const0> ;
  assign gttxreset_us_in[0] = \<const0> ;
  assign gttxreset_usp_in[1] = \<const0> ;
  assign gttxreset_usp_in[0] = \<const0> ;
  assign gtwiz_reset_rx_done_us_in = \<const0> ;
  assign gtwiz_reset_rx_done_usp_in = \<const0> ;
  assign gtwiz_reset_tx_done_us_in = \<const0> ;
  assign gtwiz_reset_tx_done_usp_in = \<const0> ;
  assign gtwiz_userclk_rx_active_us_in = \<const0> ;
  assign gtwiz_userclk_rx_active_usp_in = \<const0> ;
  assign gtwiz_userclk_tx_active_us_in = \<const0> ;
  assign gtwiz_userclk_tx_active_usp_in = \<const0> ;
  assign gtwiz_userclk_tx_reset_us_in = \<const0> ;
  assign h2c_dsc_byp_ready_0 = \<const0> ;
  assign h2c_dsc_byp_ready_1 = \<const0> ;
  assign h2c_dsc_byp_ready_2 = \<const0> ;
  assign h2c_dsc_byp_ready_3 = \<const0> ;
  assign h2c_sts_0[7] = \<const0> ;
  assign h2c_sts_0[6] = \<const0> ;
  assign h2c_sts_0[5] = \<const0> ;
  assign h2c_sts_0[4] = \<const0> ;
  assign h2c_sts_0[3] = \<const0> ;
  assign h2c_sts_0[2] = \<const0> ;
  assign h2c_sts_0[1] = \<const0> ;
  assign h2c_sts_0[0] = \<const0> ;
  assign h2c_sts_1[7] = \<const0> ;
  assign h2c_sts_1[6] = \<const0> ;
  assign h2c_sts_1[5] = \<const0> ;
  assign h2c_sts_1[4] = \<const0> ;
  assign h2c_sts_1[3] = \<const0> ;
  assign h2c_sts_1[2] = \<const0> ;
  assign h2c_sts_1[1] = \<const0> ;
  assign h2c_sts_1[0] = \<const0> ;
  assign h2c_sts_2[7] = \<const0> ;
  assign h2c_sts_2[6] = \<const0> ;
  assign h2c_sts_2[5] = \<const0> ;
  assign h2c_sts_2[4] = \<const0> ;
  assign h2c_sts_2[3] = \<const0> ;
  assign h2c_sts_2[2] = \<const0> ;
  assign h2c_sts_2[1] = \<const0> ;
  assign h2c_sts_2[0] = \<const0> ;
  assign h2c_sts_3[7] = \<const0> ;
  assign h2c_sts_3[6] = \<const0> ;
  assign h2c_sts_3[5] = \<const0> ;
  assign h2c_sts_3[4] = \<const0> ;
  assign h2c_sts_3[3] = \<const0> ;
  assign h2c_sts_3[2] = \<const0> ;
  assign h2c_sts_3[1] = \<const0> ;
  assign h2c_sts_3[0] = \<const0> ;
  assign int_dclk_out = \<const0> ;
  assign int_oobclk_out = \<const0> ;
  assign int_pclk_out_slave = \<const0> ;
  assign int_pipe_rxusrclk_out = \<const0> ;
  assign int_qpll1lock_out[0] = \<const0> ;
  assign int_qpll1outclk_out[0] = \<const0> ;
  assign int_qpll1outrefclk_out[0] = \<const0> ;
  assign int_qplllock_out[1] = \<const0> ;
  assign int_qplllock_out[0] = \<const0> ;
  assign int_qplloutclk_out[1] = \<const0> ;
  assign int_qplloutclk_out[0] = \<const0> ;
  assign int_qplloutrefclk_out[1] = \<const0> ;
  assign int_qplloutrefclk_out[0] = \<const0> ;
  assign int_rxoutclk_out[1] = \<const0> ;
  assign int_rxoutclk_out[0] = \<const0> ;
  assign int_userclk1_out = \<const0> ;
  assign int_userclk2_out = \<const0> ;
  assign int_usp_qpll0lock_out[0] = \<const0> ;
  assign int_usp_qpll0outclk_out[0] = \<const0> ;
  assign int_usp_qpll0outrefclk_out[0] = \<const0> ;
  assign int_usp_qpll1lock_out[0] = \<const0> ;
  assign int_usp_qpll1outclk_out[0] = \<const0> ;
  assign int_usp_qpll1outrefclk_out[0] = \<const0> ;
  assign interrupt_out = \<const0> ;
  assign interrupt_out_msi_vec0to31 = \<const0> ;
  assign interrupt_out_msi_vec32to63 = \<const0> ;
  assign interrupt_out_msix_0 = \<const0> ;
  assign interrupt_out_msix_1 = \<const0> ;
  assign interrupt_out_msix_2 = \<const0> ;
  assign interrupt_out_msix_3 = \<const0> ;
  assign loopback_us_in[5] = \<const0> ;
  assign loopback_us_in[4] = \<const0> ;
  assign loopback_us_in[3] = \<const0> ;
  assign loopback_us_in[2] = \<const0> ;
  assign loopback_us_in[1] = \<const0> ;
  assign loopback_us_in[0] = \<const0> ;
  assign loopback_usp_in[5] = \<const0> ;
  assign loopback_usp_in[4] = \<const0> ;
  assign loopback_usp_in[3] = \<const0> ;
  assign loopback_usp_in[2] = \<const0> ;
  assign loopback_usp_in[1] = \<const0> ;
  assign loopback_usp_in[0] = \<const0> ;
  assign m_axi_araddr[63:0] = m_axi_araddr_temp;
  assign m_axi_arburst[1] = \<const0> ;
  assign m_axi_arburst[0] = \^m_axi_arburst [0];
  assign m_axi_arcache[3] = \<const0> ;
  assign m_axi_arcache[2] = \<const0> ;
  assign m_axi_arcache[1] = \<const1> ;
  assign m_axi_arcache[0] = \<const1> ;
  assign m_axi_arid[3] = \<const0> ;
  assign m_axi_arid[2] = \<const0> ;
  assign m_axi_arid[1] = \<const0> ;
  assign m_axi_arid[0] = \<const0> ;
  assign m_axi_arlock = \<const0> ;
  assign m_axi_arprot[2] = \<const0> ;
  assign m_axi_arprot[1] = \<const0> ;
  assign m_axi_arprot[0] = \<const0> ;
  assign m_axi_arsize[2] = \<const0> ;
  assign m_axi_arsize[1:0] = \^m_axi_arsize [1:0];
  assign m_axi_awaddr[63:0] = m_axi_awaddr_temp;
  assign m_axi_awburst[1] = \<const0> ;
  assign m_axi_awburst[0] = \^m_axi_awburst [0];
  assign m_axi_awcache[3] = \<const0> ;
  assign m_axi_awcache[2] = \<const0> ;
  assign m_axi_awcache[1] = \<const1> ;
  assign m_axi_awcache[0] = \<const1> ;
  assign m_axi_awid[3] = \<const0> ;
  assign m_axi_awid[2] = \<const0> ;
  assign m_axi_awid[1] = \<const0> ;
  assign m_axi_awid[0] = \<const0> ;
  assign m_axi_awlock = \<const0> ;
  assign m_axi_awprot[2] = \<const0> ;
  assign m_axi_awprot[1] = \<const0> ;
  assign m_axi_awprot[0] = \<const0> ;
  assign m_axi_awsize[2] = \<const0> ;
  assign m_axi_awsize[1:0] = \^m_axi_awsize [1:0];
  assign m_axi_wuser[7] = \<const0> ;
  assign m_axi_wuser[6] = \<const0> ;
  assign m_axi_wuser[5] = \<const0> ;
  assign m_axi_wuser[4] = \<const0> ;
  assign m_axi_wuser[3] = \<const0> ;
  assign m_axi_wuser[2] = \<const0> ;
  assign m_axi_wuser[1] = \<const0> ;
  assign m_axi_wuser[0] = \<const0> ;
  assign m_axib_araddr[63:0] = m_axib_araddr_temp;
  assign m_axib_arburst[1] = \<const0> ;
  assign m_axib_arburst[0] = \<const1> ;
  assign m_axib_arcache[3] = \<const0> ;
  assign m_axib_arcache[2] = \<const0> ;
  assign m_axib_arcache[1] = \<const1> ;
  assign m_axib_arcache[0] = \<const1> ;
  assign m_axib_arid[3] = \<const0> ;
  assign m_axib_arid[2] = \<const0> ;
  assign m_axib_arid[1] = \<const0> ;
  assign m_axib_arid[0] = \<const0> ;
  assign m_axib_arlock = \<const0> ;
  assign m_axib_arprot[2] = \<const0> ;
  assign m_axib_arprot[1:0] = \^m_axib_arprot [1:0];
  assign m_axib_arsize[2] = \<const0> ;
  assign m_axib_arsize[1:0] = \^m_axib_arsize [1:0];
  assign m_axib_aruser[7] = \<const0> ;
  assign m_axib_aruser[6] = \<const0> ;
  assign m_axib_aruser[5] = \<const0> ;
  assign m_axib_aruser[4] = \<const0> ;
  assign m_axib_aruser[3] = \<const0> ;
  assign m_axib_aruser[2] = \<const0> ;
  assign m_axib_aruser[1] = \<const0> ;
  assign m_axib_aruser[0] = \<const0> ;
  assign m_axib_awaddr[63:0] = m_axib_awaddr_temp;
  assign m_axib_awburst[1] = \<const0> ;
  assign m_axib_awburst[0] = \<const1> ;
  assign m_axib_awcache[3] = \<const0> ;
  assign m_axib_awcache[2] = \<const0> ;
  assign m_axib_awcache[1] = \<const1> ;
  assign m_axib_awcache[0] = \<const1> ;
  assign m_axib_awid[3] = \<const0> ;
  assign m_axib_awid[2] = \<const0> ;
  assign m_axib_awid[1] = \<const0> ;
  assign m_axib_awid[0] = \<const0> ;
  assign m_axib_awlock = \<const0> ;
  assign m_axib_awprot[2] = \<const0> ;
  assign m_axib_awprot[1:0] = \^m_axib_awprot [1:0];
  assign m_axib_awsize[2] = \<const0> ;
  assign m_axib_awsize[1:0] = \^m_axib_awsize [1:0];
  assign m_axib_awuser[7] = \<const0> ;
  assign m_axib_awuser[6] = \<const0> ;
  assign m_axib_awuser[5] = \<const0> ;
  assign m_axib_awuser[4] = \<const0> ;
  assign m_axib_awuser[3] = \<const0> ;
  assign m_axib_awuser[2] = \<const0> ;
  assign m_axib_awuser[1] = \<const0> ;
  assign m_axib_awuser[0] = \<const0> ;
  assign m_axib_wuser[7] = \<const0> ;
  assign m_axib_wuser[6] = \<const0> ;
  assign m_axib_wuser[5] = \<const0> ;
  assign m_axib_wuser[4] = \<const0> ;
  assign m_axib_wuser[3] = \<const0> ;
  assign m_axib_wuser[2] = \<const0> ;
  assign m_axib_wuser[1] = \<const0> ;
  assign m_axib_wuser[0] = \<const0> ;
  assign m_axil_araddr[31] = \<const0> ;
  assign m_axil_araddr[30] = \<const0> ;
  assign m_axil_araddr[29] = \<const0> ;
  assign m_axil_araddr[28] = \<const0> ;
  assign m_axil_araddr[27] = \<const0> ;
  assign m_axil_araddr[26] = \<const0> ;
  assign m_axil_araddr[25] = \<const0> ;
  assign m_axil_araddr[24] = \<const0> ;
  assign m_axil_araddr[23] = \<const0> ;
  assign m_axil_araddr[22] = \<const0> ;
  assign m_axil_araddr[21] = \<const0> ;
  assign m_axil_araddr[20] = \<const0> ;
  assign m_axil_araddr[19] = \<const0> ;
  assign m_axil_araddr[18] = \<const0> ;
  assign m_axil_araddr[17] = \<const0> ;
  assign m_axil_araddr[16] = \<const0> ;
  assign m_axil_araddr[15] = \<const0> ;
  assign m_axil_araddr[14] = \<const0> ;
  assign m_axil_araddr[13] = \<const0> ;
  assign m_axil_araddr[12] = \<const0> ;
  assign m_axil_araddr[11] = \<const0> ;
  assign m_axil_araddr[10] = \<const0> ;
  assign m_axil_araddr[9] = \<const0> ;
  assign m_axil_araddr[8] = \<const0> ;
  assign m_axil_araddr[7] = \<const0> ;
  assign m_axil_araddr[6] = \<const0> ;
  assign m_axil_araddr[5] = \<const0> ;
  assign m_axil_araddr[4] = \<const0> ;
  assign m_axil_araddr[3] = \<const0> ;
  assign m_axil_araddr[2] = \<const0> ;
  assign m_axil_araddr[1] = \<const0> ;
  assign m_axil_araddr[0] = \<const0> ;
  assign m_axil_arprot[2] = \<const0> ;
  assign m_axil_arprot[1] = \<const0> ;
  assign m_axil_arprot[0] = \<const0> ;
  assign m_axil_aruser[10] = \<const0> ;
  assign m_axil_aruser[9] = \<const0> ;
  assign m_axil_aruser[8] = \<const0> ;
  assign m_axil_aruser[7] = \<const0> ;
  assign m_axil_aruser[6] = \<const0> ;
  assign m_axil_aruser[5] = \<const0> ;
  assign m_axil_aruser[4] = \<const0> ;
  assign m_axil_aruser[3] = \<const0> ;
  assign m_axil_aruser[2] = \<const0> ;
  assign m_axil_aruser[1] = \<const0> ;
  assign m_axil_aruser[0] = \<const0> ;
  assign m_axil_arvalid = \<const0> ;
  assign m_axil_awaddr[31] = \<const0> ;
  assign m_axil_awaddr[30] = \<const0> ;
  assign m_axil_awaddr[29] = \<const0> ;
  assign m_axil_awaddr[28] = \<const0> ;
  assign m_axil_awaddr[27] = \<const0> ;
  assign m_axil_awaddr[26] = \<const0> ;
  assign m_axil_awaddr[25] = \<const0> ;
  assign m_axil_awaddr[24] = \<const0> ;
  assign m_axil_awaddr[23] = \<const0> ;
  assign m_axil_awaddr[22] = \<const0> ;
  assign m_axil_awaddr[21] = \<const0> ;
  assign m_axil_awaddr[20] = \<const0> ;
  assign m_axil_awaddr[19] = \<const0> ;
  assign m_axil_awaddr[18] = \<const0> ;
  assign m_axil_awaddr[17] = \<const0> ;
  assign m_axil_awaddr[16] = \<const0> ;
  assign m_axil_awaddr[15] = \<const0> ;
  assign m_axil_awaddr[14] = \<const0> ;
  assign m_axil_awaddr[13] = \<const0> ;
  assign m_axil_awaddr[12] = \<const0> ;
  assign m_axil_awaddr[11] = \<const0> ;
  assign m_axil_awaddr[10] = \<const0> ;
  assign m_axil_awaddr[9] = \<const0> ;
  assign m_axil_awaddr[8] = \<const0> ;
  assign m_axil_awaddr[7] = \<const0> ;
  assign m_axil_awaddr[6] = \<const0> ;
  assign m_axil_awaddr[5] = \<const0> ;
  assign m_axil_awaddr[4] = \<const0> ;
  assign m_axil_awaddr[3] = \<const0> ;
  assign m_axil_awaddr[2] = \<const0> ;
  assign m_axil_awaddr[1] = \<const0> ;
  assign m_axil_awaddr[0] = \<const0> ;
  assign m_axil_awprot[2] = \<const0> ;
  assign m_axil_awprot[1] = \<const0> ;
  assign m_axil_awprot[0] = \<const0> ;
  assign m_axil_awuser[10] = \<const0> ;
  assign m_axil_awuser[9] = \<const0> ;
  assign m_axil_awuser[8] = \<const0> ;
  assign m_axil_awuser[7] = \<const0> ;
  assign m_axil_awuser[6] = \<const0> ;
  assign m_axil_awuser[5] = \<const0> ;
  assign m_axil_awuser[4] = \<const0> ;
  assign m_axil_awuser[3] = \<const0> ;
  assign m_axil_awuser[2] = \<const0> ;
  assign m_axil_awuser[1] = \<const0> ;
  assign m_axil_awuser[0] = \<const0> ;
  assign m_axil_awvalid = \<const0> ;
  assign m_axil_bready = \<const0> ;
  assign m_axil_rready = \<const0> ;
  assign m_axil_wdata[31] = \<const0> ;
  assign m_axil_wdata[30] = \<const0> ;
  assign m_axil_wdata[29] = \<const0> ;
  assign m_axil_wdata[28] = \<const0> ;
  assign m_axil_wdata[27] = \<const0> ;
  assign m_axil_wdata[26] = \<const0> ;
  assign m_axil_wdata[25] = \<const0> ;
  assign m_axil_wdata[24] = \<const0> ;
  assign m_axil_wdata[23] = \<const0> ;
  assign m_axil_wdata[22] = \<const0> ;
  assign m_axil_wdata[21] = \<const0> ;
  assign m_axil_wdata[20] = \<const0> ;
  assign m_axil_wdata[19] = \<const0> ;
  assign m_axil_wdata[18] = \<const0> ;
  assign m_axil_wdata[17] = \<const0> ;
  assign m_axil_wdata[16] = \<const0> ;
  assign m_axil_wdata[15] = \<const0> ;
  assign m_axil_wdata[14] = \<const0> ;
  assign m_axil_wdata[13] = \<const0> ;
  assign m_axil_wdata[12] = \<const0> ;
  assign m_axil_wdata[11] = \<const0> ;
  assign m_axil_wdata[10] = \<const0> ;
  assign m_axil_wdata[9] = \<const0> ;
  assign m_axil_wdata[8] = \<const0> ;
  assign m_axil_wdata[7] = \<const0> ;
  assign m_axil_wdata[6] = \<const0> ;
  assign m_axil_wdata[5] = \<const0> ;
  assign m_axil_wdata[4] = \<const0> ;
  assign m_axil_wdata[3] = \<const0> ;
  assign m_axil_wdata[2] = \<const0> ;
  assign m_axil_wdata[1] = \<const0> ;
  assign m_axil_wdata[0] = \<const0> ;
  assign m_axil_wstrb[3] = \<const0> ;
  assign m_axil_wstrb[2] = \<const0> ;
  assign m_axil_wstrb[1] = \<const0> ;
  assign m_axil_wstrb[0] = \<const0> ;
  assign m_axil_wvalid = \<const0> ;
  assign m_axis_cc_tdata_out[63] = \<const0> ;
  assign m_axis_cc_tdata_out[62] = \<const0> ;
  assign m_axis_cc_tdata_out[61] = \<const0> ;
  assign m_axis_cc_tdata_out[60] = \<const0> ;
  assign m_axis_cc_tdata_out[59] = \<const0> ;
  assign m_axis_cc_tdata_out[58] = \<const0> ;
  assign m_axis_cc_tdata_out[57] = \<const0> ;
  assign m_axis_cc_tdata_out[56] = \<const0> ;
  assign m_axis_cc_tdata_out[55] = \<const0> ;
  assign m_axis_cc_tdata_out[54] = \<const0> ;
  assign m_axis_cc_tdata_out[53] = \<const0> ;
  assign m_axis_cc_tdata_out[52] = \<const0> ;
  assign m_axis_cc_tdata_out[51] = \<const0> ;
  assign m_axis_cc_tdata_out[50] = \<const0> ;
  assign m_axis_cc_tdata_out[49] = \<const0> ;
  assign m_axis_cc_tdata_out[48] = \<const0> ;
  assign m_axis_cc_tdata_out[47] = \<const0> ;
  assign m_axis_cc_tdata_out[46] = \<const0> ;
  assign m_axis_cc_tdata_out[45] = \<const0> ;
  assign m_axis_cc_tdata_out[44] = \<const0> ;
  assign m_axis_cc_tdata_out[43] = \<const0> ;
  assign m_axis_cc_tdata_out[42] = \<const0> ;
  assign m_axis_cc_tdata_out[41] = \<const0> ;
  assign m_axis_cc_tdata_out[40] = \<const0> ;
  assign m_axis_cc_tdata_out[39] = \<const0> ;
  assign m_axis_cc_tdata_out[38] = \<const0> ;
  assign m_axis_cc_tdata_out[37] = \<const0> ;
  assign m_axis_cc_tdata_out[36] = \<const0> ;
  assign m_axis_cc_tdata_out[35] = \<const0> ;
  assign m_axis_cc_tdata_out[34] = \<const0> ;
  assign m_axis_cc_tdata_out[33] = \<const0> ;
  assign m_axis_cc_tdata_out[32] = \<const0> ;
  assign m_axis_cc_tdata_out[31] = \<const0> ;
  assign m_axis_cc_tdata_out[30] = \<const0> ;
  assign m_axis_cc_tdata_out[29] = \<const0> ;
  assign m_axis_cc_tdata_out[28] = \<const0> ;
  assign m_axis_cc_tdata_out[27] = \<const0> ;
  assign m_axis_cc_tdata_out[26] = \<const0> ;
  assign m_axis_cc_tdata_out[25] = \<const0> ;
  assign m_axis_cc_tdata_out[24] = \<const0> ;
  assign m_axis_cc_tdata_out[23] = \<const0> ;
  assign m_axis_cc_tdata_out[22] = \<const0> ;
  assign m_axis_cc_tdata_out[21] = \<const0> ;
  assign m_axis_cc_tdata_out[20] = \<const0> ;
  assign m_axis_cc_tdata_out[19] = \<const0> ;
  assign m_axis_cc_tdata_out[18] = \<const0> ;
  assign m_axis_cc_tdata_out[17] = \<const0> ;
  assign m_axis_cc_tdata_out[16] = \<const0> ;
  assign m_axis_cc_tdata_out[15] = \<const0> ;
  assign m_axis_cc_tdata_out[14] = \<const0> ;
  assign m_axis_cc_tdata_out[13] = \<const0> ;
  assign m_axis_cc_tdata_out[12] = \<const0> ;
  assign m_axis_cc_tdata_out[11] = \<const0> ;
  assign m_axis_cc_tdata_out[10] = \<const0> ;
  assign m_axis_cc_tdata_out[9] = \<const0> ;
  assign m_axis_cc_tdata_out[8] = \<const0> ;
  assign m_axis_cc_tdata_out[7] = \<const0> ;
  assign m_axis_cc_tdata_out[6] = \<const0> ;
  assign m_axis_cc_tdata_out[5] = \<const0> ;
  assign m_axis_cc_tdata_out[4] = \<const0> ;
  assign m_axis_cc_tdata_out[3] = \<const0> ;
  assign m_axis_cc_tdata_out[2] = \<const0> ;
  assign m_axis_cc_tdata_out[1] = \<const0> ;
  assign m_axis_cc_tdata_out[0] = \<const0> ;
  assign m_axis_cc_tkeep_out[1] = \<const0> ;
  assign m_axis_cc_tkeep_out[0] = \<const0> ;
  assign m_axis_cc_tlast_out = \<const0> ;
  assign m_axis_cc_tready_out[3] = \<const0> ;
  assign m_axis_cc_tready_out[2] = \<const0> ;
  assign m_axis_cc_tready_out[1] = \<const0> ;
  assign m_axis_cc_tready_out[0] = \<const0> ;
  assign m_axis_cc_tuser_out[32] = \<const0> ;
  assign m_axis_cc_tuser_out[31] = \<const0> ;
  assign m_axis_cc_tuser_out[30] = \<const0> ;
  assign m_axis_cc_tuser_out[29] = \<const0> ;
  assign m_axis_cc_tuser_out[28] = \<const0> ;
  assign m_axis_cc_tuser_out[27] = \<const0> ;
  assign m_axis_cc_tuser_out[26] = \<const0> ;
  assign m_axis_cc_tuser_out[25] = \<const0> ;
  assign m_axis_cc_tuser_out[24] = \<const0> ;
  assign m_axis_cc_tuser_out[23] = \<const0> ;
  assign m_axis_cc_tuser_out[22] = \<const0> ;
  assign m_axis_cc_tuser_out[21] = \<const0> ;
  assign m_axis_cc_tuser_out[20] = \<const0> ;
  assign m_axis_cc_tuser_out[19] = \<const0> ;
  assign m_axis_cc_tuser_out[18] = \<const0> ;
  assign m_axis_cc_tuser_out[17] = \<const0> ;
  assign m_axis_cc_tuser_out[16] = \<const0> ;
  assign m_axis_cc_tuser_out[15] = \<const0> ;
  assign m_axis_cc_tuser_out[14] = \<const0> ;
  assign m_axis_cc_tuser_out[13] = \<const0> ;
  assign m_axis_cc_tuser_out[12] = \<const0> ;
  assign m_axis_cc_tuser_out[11] = \<const0> ;
  assign m_axis_cc_tuser_out[10] = \<const0> ;
  assign m_axis_cc_tuser_out[9] = \<const0> ;
  assign m_axis_cc_tuser_out[8] = \<const0> ;
  assign m_axis_cc_tuser_out[7] = \<const0> ;
  assign m_axis_cc_tuser_out[6] = \<const0> ;
  assign m_axis_cc_tuser_out[5] = \<const0> ;
  assign m_axis_cc_tuser_out[4] = \<const0> ;
  assign m_axis_cc_tuser_out[3] = \<const0> ;
  assign m_axis_cc_tuser_out[2] = \<const0> ;
  assign m_axis_cc_tuser_out[1] = \<const0> ;
  assign m_axis_cc_tuser_out[0] = \<const0> ;
  assign m_axis_cc_tvalid_out = \<const0> ;
  assign m_axis_cq_tready_sd = \<const0> ;
  assign m_axis_h2c_tdata_0[63] = \<const0> ;
  assign m_axis_h2c_tdata_0[62] = \<const0> ;
  assign m_axis_h2c_tdata_0[61] = \<const0> ;
  assign m_axis_h2c_tdata_0[60] = \<const0> ;
  assign m_axis_h2c_tdata_0[59] = \<const0> ;
  assign m_axis_h2c_tdata_0[58] = \<const0> ;
  assign m_axis_h2c_tdata_0[57] = \<const0> ;
  assign m_axis_h2c_tdata_0[56] = \<const0> ;
  assign m_axis_h2c_tdata_0[55] = \<const0> ;
  assign m_axis_h2c_tdata_0[54] = \<const0> ;
  assign m_axis_h2c_tdata_0[53] = \<const0> ;
  assign m_axis_h2c_tdata_0[52] = \<const0> ;
  assign m_axis_h2c_tdata_0[51] = \<const0> ;
  assign m_axis_h2c_tdata_0[50] = \<const0> ;
  assign m_axis_h2c_tdata_0[49] = \<const0> ;
  assign m_axis_h2c_tdata_0[48] = \<const0> ;
  assign m_axis_h2c_tdata_0[47] = \<const0> ;
  assign m_axis_h2c_tdata_0[46] = \<const0> ;
  assign m_axis_h2c_tdata_0[45] = \<const0> ;
  assign m_axis_h2c_tdata_0[44] = \<const0> ;
  assign m_axis_h2c_tdata_0[43] = \<const0> ;
  assign m_axis_h2c_tdata_0[42] = \<const0> ;
  assign m_axis_h2c_tdata_0[41] = \<const0> ;
  assign m_axis_h2c_tdata_0[40] = \<const0> ;
  assign m_axis_h2c_tdata_0[39] = \<const0> ;
  assign m_axis_h2c_tdata_0[38] = \<const0> ;
  assign m_axis_h2c_tdata_0[37] = \<const0> ;
  assign m_axis_h2c_tdata_0[36] = \<const0> ;
  assign m_axis_h2c_tdata_0[35] = \<const0> ;
  assign m_axis_h2c_tdata_0[34] = \<const0> ;
  assign m_axis_h2c_tdata_0[33] = \<const0> ;
  assign m_axis_h2c_tdata_0[32] = \<const0> ;
  assign m_axis_h2c_tdata_0[31] = \<const0> ;
  assign m_axis_h2c_tdata_0[30] = \<const0> ;
  assign m_axis_h2c_tdata_0[29] = \<const0> ;
  assign m_axis_h2c_tdata_0[28] = \<const0> ;
  assign m_axis_h2c_tdata_0[27] = \<const0> ;
  assign m_axis_h2c_tdata_0[26] = \<const0> ;
  assign m_axis_h2c_tdata_0[25] = \<const0> ;
  assign m_axis_h2c_tdata_0[24] = \<const0> ;
  assign m_axis_h2c_tdata_0[23] = \<const0> ;
  assign m_axis_h2c_tdata_0[22] = \<const0> ;
  assign m_axis_h2c_tdata_0[21] = \<const0> ;
  assign m_axis_h2c_tdata_0[20] = \<const0> ;
  assign m_axis_h2c_tdata_0[19] = \<const0> ;
  assign m_axis_h2c_tdata_0[18] = \<const0> ;
  assign m_axis_h2c_tdata_0[17] = \<const0> ;
  assign m_axis_h2c_tdata_0[16] = \<const0> ;
  assign m_axis_h2c_tdata_0[15] = \<const0> ;
  assign m_axis_h2c_tdata_0[14] = \<const0> ;
  assign m_axis_h2c_tdata_0[13] = \<const0> ;
  assign m_axis_h2c_tdata_0[12] = \<const0> ;
  assign m_axis_h2c_tdata_0[11] = \<const0> ;
  assign m_axis_h2c_tdata_0[10] = \<const0> ;
  assign m_axis_h2c_tdata_0[9] = \<const0> ;
  assign m_axis_h2c_tdata_0[8] = \<const0> ;
  assign m_axis_h2c_tdata_0[7] = \<const0> ;
  assign m_axis_h2c_tdata_0[6] = \<const0> ;
  assign m_axis_h2c_tdata_0[5] = \<const0> ;
  assign m_axis_h2c_tdata_0[4] = \<const0> ;
  assign m_axis_h2c_tdata_0[3] = \<const0> ;
  assign m_axis_h2c_tdata_0[2] = \<const0> ;
  assign m_axis_h2c_tdata_0[1] = \<const0> ;
  assign m_axis_h2c_tdata_0[0] = \<const0> ;
  assign m_axis_h2c_tdata_1[63] = \<const0> ;
  assign m_axis_h2c_tdata_1[62] = \<const0> ;
  assign m_axis_h2c_tdata_1[61] = \<const0> ;
  assign m_axis_h2c_tdata_1[60] = \<const0> ;
  assign m_axis_h2c_tdata_1[59] = \<const0> ;
  assign m_axis_h2c_tdata_1[58] = \<const0> ;
  assign m_axis_h2c_tdata_1[57] = \<const0> ;
  assign m_axis_h2c_tdata_1[56] = \<const0> ;
  assign m_axis_h2c_tdata_1[55] = \<const0> ;
  assign m_axis_h2c_tdata_1[54] = \<const0> ;
  assign m_axis_h2c_tdata_1[53] = \<const0> ;
  assign m_axis_h2c_tdata_1[52] = \<const0> ;
  assign m_axis_h2c_tdata_1[51] = \<const0> ;
  assign m_axis_h2c_tdata_1[50] = \<const0> ;
  assign m_axis_h2c_tdata_1[49] = \<const0> ;
  assign m_axis_h2c_tdata_1[48] = \<const0> ;
  assign m_axis_h2c_tdata_1[47] = \<const0> ;
  assign m_axis_h2c_tdata_1[46] = \<const0> ;
  assign m_axis_h2c_tdata_1[45] = \<const0> ;
  assign m_axis_h2c_tdata_1[44] = \<const0> ;
  assign m_axis_h2c_tdata_1[43] = \<const0> ;
  assign m_axis_h2c_tdata_1[42] = \<const0> ;
  assign m_axis_h2c_tdata_1[41] = \<const0> ;
  assign m_axis_h2c_tdata_1[40] = \<const0> ;
  assign m_axis_h2c_tdata_1[39] = \<const0> ;
  assign m_axis_h2c_tdata_1[38] = \<const0> ;
  assign m_axis_h2c_tdata_1[37] = \<const0> ;
  assign m_axis_h2c_tdata_1[36] = \<const0> ;
  assign m_axis_h2c_tdata_1[35] = \<const0> ;
  assign m_axis_h2c_tdata_1[34] = \<const0> ;
  assign m_axis_h2c_tdata_1[33] = \<const0> ;
  assign m_axis_h2c_tdata_1[32] = \<const0> ;
  assign m_axis_h2c_tdata_1[31] = \<const0> ;
  assign m_axis_h2c_tdata_1[30] = \<const0> ;
  assign m_axis_h2c_tdata_1[29] = \<const0> ;
  assign m_axis_h2c_tdata_1[28] = \<const0> ;
  assign m_axis_h2c_tdata_1[27] = \<const0> ;
  assign m_axis_h2c_tdata_1[26] = \<const0> ;
  assign m_axis_h2c_tdata_1[25] = \<const0> ;
  assign m_axis_h2c_tdata_1[24] = \<const0> ;
  assign m_axis_h2c_tdata_1[23] = \<const0> ;
  assign m_axis_h2c_tdata_1[22] = \<const0> ;
  assign m_axis_h2c_tdata_1[21] = \<const0> ;
  assign m_axis_h2c_tdata_1[20] = \<const0> ;
  assign m_axis_h2c_tdata_1[19] = \<const0> ;
  assign m_axis_h2c_tdata_1[18] = \<const0> ;
  assign m_axis_h2c_tdata_1[17] = \<const0> ;
  assign m_axis_h2c_tdata_1[16] = \<const0> ;
  assign m_axis_h2c_tdata_1[15] = \<const0> ;
  assign m_axis_h2c_tdata_1[14] = \<const0> ;
  assign m_axis_h2c_tdata_1[13] = \<const0> ;
  assign m_axis_h2c_tdata_1[12] = \<const0> ;
  assign m_axis_h2c_tdata_1[11] = \<const0> ;
  assign m_axis_h2c_tdata_1[10] = \<const0> ;
  assign m_axis_h2c_tdata_1[9] = \<const0> ;
  assign m_axis_h2c_tdata_1[8] = \<const0> ;
  assign m_axis_h2c_tdata_1[7] = \<const0> ;
  assign m_axis_h2c_tdata_1[6] = \<const0> ;
  assign m_axis_h2c_tdata_1[5] = \<const0> ;
  assign m_axis_h2c_tdata_1[4] = \<const0> ;
  assign m_axis_h2c_tdata_1[3] = \<const0> ;
  assign m_axis_h2c_tdata_1[2] = \<const0> ;
  assign m_axis_h2c_tdata_1[1] = \<const0> ;
  assign m_axis_h2c_tdata_1[0] = \<const0> ;
  assign m_axis_h2c_tdata_2[63] = \<const0> ;
  assign m_axis_h2c_tdata_2[62] = \<const0> ;
  assign m_axis_h2c_tdata_2[61] = \<const0> ;
  assign m_axis_h2c_tdata_2[60] = \<const0> ;
  assign m_axis_h2c_tdata_2[59] = \<const0> ;
  assign m_axis_h2c_tdata_2[58] = \<const0> ;
  assign m_axis_h2c_tdata_2[57] = \<const0> ;
  assign m_axis_h2c_tdata_2[56] = \<const0> ;
  assign m_axis_h2c_tdata_2[55] = \<const0> ;
  assign m_axis_h2c_tdata_2[54] = \<const0> ;
  assign m_axis_h2c_tdata_2[53] = \<const0> ;
  assign m_axis_h2c_tdata_2[52] = \<const0> ;
  assign m_axis_h2c_tdata_2[51] = \<const0> ;
  assign m_axis_h2c_tdata_2[50] = \<const0> ;
  assign m_axis_h2c_tdata_2[49] = \<const0> ;
  assign m_axis_h2c_tdata_2[48] = \<const0> ;
  assign m_axis_h2c_tdata_2[47] = \<const0> ;
  assign m_axis_h2c_tdata_2[46] = \<const0> ;
  assign m_axis_h2c_tdata_2[45] = \<const0> ;
  assign m_axis_h2c_tdata_2[44] = \<const0> ;
  assign m_axis_h2c_tdata_2[43] = \<const0> ;
  assign m_axis_h2c_tdata_2[42] = \<const0> ;
  assign m_axis_h2c_tdata_2[41] = \<const0> ;
  assign m_axis_h2c_tdata_2[40] = \<const0> ;
  assign m_axis_h2c_tdata_2[39] = \<const0> ;
  assign m_axis_h2c_tdata_2[38] = \<const0> ;
  assign m_axis_h2c_tdata_2[37] = \<const0> ;
  assign m_axis_h2c_tdata_2[36] = \<const0> ;
  assign m_axis_h2c_tdata_2[35] = \<const0> ;
  assign m_axis_h2c_tdata_2[34] = \<const0> ;
  assign m_axis_h2c_tdata_2[33] = \<const0> ;
  assign m_axis_h2c_tdata_2[32] = \<const0> ;
  assign m_axis_h2c_tdata_2[31] = \<const0> ;
  assign m_axis_h2c_tdata_2[30] = \<const0> ;
  assign m_axis_h2c_tdata_2[29] = \<const0> ;
  assign m_axis_h2c_tdata_2[28] = \<const0> ;
  assign m_axis_h2c_tdata_2[27] = \<const0> ;
  assign m_axis_h2c_tdata_2[26] = \<const0> ;
  assign m_axis_h2c_tdata_2[25] = \<const0> ;
  assign m_axis_h2c_tdata_2[24] = \<const0> ;
  assign m_axis_h2c_tdata_2[23] = \<const0> ;
  assign m_axis_h2c_tdata_2[22] = \<const0> ;
  assign m_axis_h2c_tdata_2[21] = \<const0> ;
  assign m_axis_h2c_tdata_2[20] = \<const0> ;
  assign m_axis_h2c_tdata_2[19] = \<const0> ;
  assign m_axis_h2c_tdata_2[18] = \<const0> ;
  assign m_axis_h2c_tdata_2[17] = \<const0> ;
  assign m_axis_h2c_tdata_2[16] = \<const0> ;
  assign m_axis_h2c_tdata_2[15] = \<const0> ;
  assign m_axis_h2c_tdata_2[14] = \<const0> ;
  assign m_axis_h2c_tdata_2[13] = \<const0> ;
  assign m_axis_h2c_tdata_2[12] = \<const0> ;
  assign m_axis_h2c_tdata_2[11] = \<const0> ;
  assign m_axis_h2c_tdata_2[10] = \<const0> ;
  assign m_axis_h2c_tdata_2[9] = \<const0> ;
  assign m_axis_h2c_tdata_2[8] = \<const0> ;
  assign m_axis_h2c_tdata_2[7] = \<const0> ;
  assign m_axis_h2c_tdata_2[6] = \<const0> ;
  assign m_axis_h2c_tdata_2[5] = \<const0> ;
  assign m_axis_h2c_tdata_2[4] = \<const0> ;
  assign m_axis_h2c_tdata_2[3] = \<const0> ;
  assign m_axis_h2c_tdata_2[2] = \<const0> ;
  assign m_axis_h2c_tdata_2[1] = \<const0> ;
  assign m_axis_h2c_tdata_2[0] = \<const0> ;
  assign m_axis_h2c_tdata_3[63] = \<const0> ;
  assign m_axis_h2c_tdata_3[62] = \<const0> ;
  assign m_axis_h2c_tdata_3[61] = \<const0> ;
  assign m_axis_h2c_tdata_3[60] = \<const0> ;
  assign m_axis_h2c_tdata_3[59] = \<const0> ;
  assign m_axis_h2c_tdata_3[58] = \<const0> ;
  assign m_axis_h2c_tdata_3[57] = \<const0> ;
  assign m_axis_h2c_tdata_3[56] = \<const0> ;
  assign m_axis_h2c_tdata_3[55] = \<const0> ;
  assign m_axis_h2c_tdata_3[54] = \<const0> ;
  assign m_axis_h2c_tdata_3[53] = \<const0> ;
  assign m_axis_h2c_tdata_3[52] = \<const0> ;
  assign m_axis_h2c_tdata_3[51] = \<const0> ;
  assign m_axis_h2c_tdata_3[50] = \<const0> ;
  assign m_axis_h2c_tdata_3[49] = \<const0> ;
  assign m_axis_h2c_tdata_3[48] = \<const0> ;
  assign m_axis_h2c_tdata_3[47] = \<const0> ;
  assign m_axis_h2c_tdata_3[46] = \<const0> ;
  assign m_axis_h2c_tdata_3[45] = \<const0> ;
  assign m_axis_h2c_tdata_3[44] = \<const0> ;
  assign m_axis_h2c_tdata_3[43] = \<const0> ;
  assign m_axis_h2c_tdata_3[42] = \<const0> ;
  assign m_axis_h2c_tdata_3[41] = \<const0> ;
  assign m_axis_h2c_tdata_3[40] = \<const0> ;
  assign m_axis_h2c_tdata_3[39] = \<const0> ;
  assign m_axis_h2c_tdata_3[38] = \<const0> ;
  assign m_axis_h2c_tdata_3[37] = \<const0> ;
  assign m_axis_h2c_tdata_3[36] = \<const0> ;
  assign m_axis_h2c_tdata_3[35] = \<const0> ;
  assign m_axis_h2c_tdata_3[34] = \<const0> ;
  assign m_axis_h2c_tdata_3[33] = \<const0> ;
  assign m_axis_h2c_tdata_3[32] = \<const0> ;
  assign m_axis_h2c_tdata_3[31] = \<const0> ;
  assign m_axis_h2c_tdata_3[30] = \<const0> ;
  assign m_axis_h2c_tdata_3[29] = \<const0> ;
  assign m_axis_h2c_tdata_3[28] = \<const0> ;
  assign m_axis_h2c_tdata_3[27] = \<const0> ;
  assign m_axis_h2c_tdata_3[26] = \<const0> ;
  assign m_axis_h2c_tdata_3[25] = \<const0> ;
  assign m_axis_h2c_tdata_3[24] = \<const0> ;
  assign m_axis_h2c_tdata_3[23] = \<const0> ;
  assign m_axis_h2c_tdata_3[22] = \<const0> ;
  assign m_axis_h2c_tdata_3[21] = \<const0> ;
  assign m_axis_h2c_tdata_3[20] = \<const0> ;
  assign m_axis_h2c_tdata_3[19] = \<const0> ;
  assign m_axis_h2c_tdata_3[18] = \<const0> ;
  assign m_axis_h2c_tdata_3[17] = \<const0> ;
  assign m_axis_h2c_tdata_3[16] = \<const0> ;
  assign m_axis_h2c_tdata_3[15] = \<const0> ;
  assign m_axis_h2c_tdata_3[14] = \<const0> ;
  assign m_axis_h2c_tdata_3[13] = \<const0> ;
  assign m_axis_h2c_tdata_3[12] = \<const0> ;
  assign m_axis_h2c_tdata_3[11] = \<const0> ;
  assign m_axis_h2c_tdata_3[10] = \<const0> ;
  assign m_axis_h2c_tdata_3[9] = \<const0> ;
  assign m_axis_h2c_tdata_3[8] = \<const0> ;
  assign m_axis_h2c_tdata_3[7] = \<const0> ;
  assign m_axis_h2c_tdata_3[6] = \<const0> ;
  assign m_axis_h2c_tdata_3[5] = \<const0> ;
  assign m_axis_h2c_tdata_3[4] = \<const0> ;
  assign m_axis_h2c_tdata_3[3] = \<const0> ;
  assign m_axis_h2c_tdata_3[2] = \<const0> ;
  assign m_axis_h2c_tdata_3[1] = \<const0> ;
  assign m_axis_h2c_tdata_3[0] = \<const0> ;
  assign m_axis_h2c_tkeep_0[7] = \<const0> ;
  assign m_axis_h2c_tkeep_0[6] = \<const0> ;
  assign m_axis_h2c_tkeep_0[5] = \<const0> ;
  assign m_axis_h2c_tkeep_0[4] = \<const0> ;
  assign m_axis_h2c_tkeep_0[3] = \<const0> ;
  assign m_axis_h2c_tkeep_0[2] = \<const0> ;
  assign m_axis_h2c_tkeep_0[1] = \<const0> ;
  assign m_axis_h2c_tkeep_0[0] = \<const0> ;
  assign m_axis_h2c_tkeep_1[7] = \<const0> ;
  assign m_axis_h2c_tkeep_1[6] = \<const0> ;
  assign m_axis_h2c_tkeep_1[5] = \<const0> ;
  assign m_axis_h2c_tkeep_1[4] = \<const0> ;
  assign m_axis_h2c_tkeep_1[3] = \<const0> ;
  assign m_axis_h2c_tkeep_1[2] = \<const0> ;
  assign m_axis_h2c_tkeep_1[1] = \<const0> ;
  assign m_axis_h2c_tkeep_1[0] = \<const0> ;
  assign m_axis_h2c_tkeep_2[7] = \<const0> ;
  assign m_axis_h2c_tkeep_2[6] = \<const0> ;
  assign m_axis_h2c_tkeep_2[5] = \<const0> ;
  assign m_axis_h2c_tkeep_2[4] = \<const0> ;
  assign m_axis_h2c_tkeep_2[3] = \<const0> ;
  assign m_axis_h2c_tkeep_2[2] = \<const0> ;
  assign m_axis_h2c_tkeep_2[1] = \<const0> ;
  assign m_axis_h2c_tkeep_2[0] = \<const0> ;
  assign m_axis_h2c_tkeep_3[7] = \<const0> ;
  assign m_axis_h2c_tkeep_3[6] = \<const0> ;
  assign m_axis_h2c_tkeep_3[5] = \<const0> ;
  assign m_axis_h2c_tkeep_3[4] = \<const0> ;
  assign m_axis_h2c_tkeep_3[3] = \<const0> ;
  assign m_axis_h2c_tkeep_3[2] = \<const0> ;
  assign m_axis_h2c_tkeep_3[1] = \<const0> ;
  assign m_axis_h2c_tkeep_3[0] = \<const0> ;
  assign m_axis_h2c_tlast_0 = \<const0> ;
  assign m_axis_h2c_tlast_1 = \<const0> ;
  assign m_axis_h2c_tlast_2 = \<const0> ;
  assign m_axis_h2c_tlast_3 = \<const0> ;
  assign m_axis_h2c_tuser_0[7] = \<const0> ;
  assign m_axis_h2c_tuser_0[6] = \<const0> ;
  assign m_axis_h2c_tuser_0[5] = \<const0> ;
  assign m_axis_h2c_tuser_0[4] = \<const0> ;
  assign m_axis_h2c_tuser_0[3] = \<const0> ;
  assign m_axis_h2c_tuser_0[2] = \<const0> ;
  assign m_axis_h2c_tuser_0[1] = \<const0> ;
  assign m_axis_h2c_tuser_0[0] = \<const0> ;
  assign m_axis_h2c_tuser_1[7] = \<const0> ;
  assign m_axis_h2c_tuser_1[6] = \<const0> ;
  assign m_axis_h2c_tuser_1[5] = \<const0> ;
  assign m_axis_h2c_tuser_1[4] = \<const0> ;
  assign m_axis_h2c_tuser_1[3] = \<const0> ;
  assign m_axis_h2c_tuser_1[2] = \<const0> ;
  assign m_axis_h2c_tuser_1[1] = \<const0> ;
  assign m_axis_h2c_tuser_1[0] = \<const0> ;
  assign m_axis_h2c_tuser_2[7] = \<const0> ;
  assign m_axis_h2c_tuser_2[6] = \<const0> ;
  assign m_axis_h2c_tuser_2[5] = \<const0> ;
  assign m_axis_h2c_tuser_2[4] = \<const0> ;
  assign m_axis_h2c_tuser_2[3] = \<const0> ;
  assign m_axis_h2c_tuser_2[2] = \<const0> ;
  assign m_axis_h2c_tuser_2[1] = \<const0> ;
  assign m_axis_h2c_tuser_2[0] = \<const0> ;
  assign m_axis_h2c_tuser_3[7] = \<const0> ;
  assign m_axis_h2c_tuser_3[6] = \<const0> ;
  assign m_axis_h2c_tuser_3[5] = \<const0> ;
  assign m_axis_h2c_tuser_3[4] = \<const0> ;
  assign m_axis_h2c_tuser_3[3] = \<const0> ;
  assign m_axis_h2c_tuser_3[2] = \<const0> ;
  assign m_axis_h2c_tuser_3[1] = \<const0> ;
  assign m_axis_h2c_tuser_3[0] = \<const0> ;
  assign m_axis_h2c_tvalid_0 = \<const0> ;
  assign m_axis_h2c_tvalid_1 = \<const0> ;
  assign m_axis_h2c_tvalid_2 = \<const0> ;
  assign m_axis_h2c_tvalid_3 = \<const0> ;
  assign m_axis_rc_tready_sd = \<const0> ;
  assign m_axis_rq_tdata_out[63] = \<const0> ;
  assign m_axis_rq_tdata_out[62] = \<const0> ;
  assign m_axis_rq_tdata_out[61] = \<const0> ;
  assign m_axis_rq_tdata_out[60] = \<const0> ;
  assign m_axis_rq_tdata_out[59] = \<const0> ;
  assign m_axis_rq_tdata_out[58] = \<const0> ;
  assign m_axis_rq_tdata_out[57] = \<const0> ;
  assign m_axis_rq_tdata_out[56] = \<const0> ;
  assign m_axis_rq_tdata_out[55] = \<const0> ;
  assign m_axis_rq_tdata_out[54] = \<const0> ;
  assign m_axis_rq_tdata_out[53] = \<const0> ;
  assign m_axis_rq_tdata_out[52] = \<const0> ;
  assign m_axis_rq_tdata_out[51] = \<const0> ;
  assign m_axis_rq_tdata_out[50] = \<const0> ;
  assign m_axis_rq_tdata_out[49] = \<const0> ;
  assign m_axis_rq_tdata_out[48] = \<const0> ;
  assign m_axis_rq_tdata_out[47] = \<const0> ;
  assign m_axis_rq_tdata_out[46] = \<const0> ;
  assign m_axis_rq_tdata_out[45] = \<const0> ;
  assign m_axis_rq_tdata_out[44] = \<const0> ;
  assign m_axis_rq_tdata_out[43] = \<const0> ;
  assign m_axis_rq_tdata_out[42] = \<const0> ;
  assign m_axis_rq_tdata_out[41] = \<const0> ;
  assign m_axis_rq_tdata_out[40] = \<const0> ;
  assign m_axis_rq_tdata_out[39] = \<const0> ;
  assign m_axis_rq_tdata_out[38] = \<const0> ;
  assign m_axis_rq_tdata_out[37] = \<const0> ;
  assign m_axis_rq_tdata_out[36] = \<const0> ;
  assign m_axis_rq_tdata_out[35] = \<const0> ;
  assign m_axis_rq_tdata_out[34] = \<const0> ;
  assign m_axis_rq_tdata_out[33] = \<const0> ;
  assign m_axis_rq_tdata_out[32] = \<const0> ;
  assign m_axis_rq_tdata_out[31] = \<const0> ;
  assign m_axis_rq_tdata_out[30] = \<const0> ;
  assign m_axis_rq_tdata_out[29] = \<const0> ;
  assign m_axis_rq_tdata_out[28] = \<const0> ;
  assign m_axis_rq_tdata_out[27] = \<const0> ;
  assign m_axis_rq_tdata_out[26] = \<const0> ;
  assign m_axis_rq_tdata_out[25] = \<const0> ;
  assign m_axis_rq_tdata_out[24] = \<const0> ;
  assign m_axis_rq_tdata_out[23] = \<const0> ;
  assign m_axis_rq_tdata_out[22] = \<const0> ;
  assign m_axis_rq_tdata_out[21] = \<const0> ;
  assign m_axis_rq_tdata_out[20] = \<const0> ;
  assign m_axis_rq_tdata_out[19] = \<const0> ;
  assign m_axis_rq_tdata_out[18] = \<const0> ;
  assign m_axis_rq_tdata_out[17] = \<const0> ;
  assign m_axis_rq_tdata_out[16] = \<const0> ;
  assign m_axis_rq_tdata_out[15] = \<const0> ;
  assign m_axis_rq_tdata_out[14] = \<const0> ;
  assign m_axis_rq_tdata_out[13] = \<const0> ;
  assign m_axis_rq_tdata_out[12] = \<const0> ;
  assign m_axis_rq_tdata_out[11] = \<const0> ;
  assign m_axis_rq_tdata_out[10] = \<const0> ;
  assign m_axis_rq_tdata_out[9] = \<const0> ;
  assign m_axis_rq_tdata_out[8] = \<const0> ;
  assign m_axis_rq_tdata_out[7] = \<const0> ;
  assign m_axis_rq_tdata_out[6] = \<const0> ;
  assign m_axis_rq_tdata_out[5] = \<const0> ;
  assign m_axis_rq_tdata_out[4] = \<const0> ;
  assign m_axis_rq_tdata_out[3] = \<const0> ;
  assign m_axis_rq_tdata_out[2] = \<const0> ;
  assign m_axis_rq_tdata_out[1] = \<const0> ;
  assign m_axis_rq_tdata_out[0] = \<const0> ;
  assign m_axis_rq_tkeep_out[1] = \<const0> ;
  assign m_axis_rq_tkeep_out[0] = \<const0> ;
  assign m_axis_rq_tlast_out = \<const0> ;
  assign m_axis_rq_tready_out[3] = \<const0> ;
  assign m_axis_rq_tready_out[2] = \<const0> ;
  assign m_axis_rq_tready_out[1] = \<const0> ;
  assign m_axis_rq_tready_out[0] = \<const0> ;
  assign m_axis_rq_tuser_out[59] = \<const0> ;
  assign m_axis_rq_tuser_out[58] = \<const0> ;
  assign m_axis_rq_tuser_out[57] = \<const0> ;
  assign m_axis_rq_tuser_out[56] = \<const0> ;
  assign m_axis_rq_tuser_out[55] = \<const0> ;
  assign m_axis_rq_tuser_out[54] = \<const0> ;
  assign m_axis_rq_tuser_out[53] = \<const0> ;
  assign m_axis_rq_tuser_out[52] = \<const0> ;
  assign m_axis_rq_tuser_out[51] = \<const0> ;
  assign m_axis_rq_tuser_out[50] = \<const0> ;
  assign m_axis_rq_tuser_out[49] = \<const0> ;
  assign m_axis_rq_tuser_out[48] = \<const0> ;
  assign m_axis_rq_tuser_out[47] = \<const0> ;
  assign m_axis_rq_tuser_out[46] = \<const0> ;
  assign m_axis_rq_tuser_out[45] = \<const0> ;
  assign m_axis_rq_tuser_out[44] = \<const0> ;
  assign m_axis_rq_tuser_out[43] = \<const0> ;
  assign m_axis_rq_tuser_out[42] = \<const0> ;
  assign m_axis_rq_tuser_out[41] = \<const0> ;
  assign m_axis_rq_tuser_out[40] = \<const0> ;
  assign m_axis_rq_tuser_out[39] = \<const0> ;
  assign m_axis_rq_tuser_out[38] = \<const0> ;
  assign m_axis_rq_tuser_out[37] = \<const0> ;
  assign m_axis_rq_tuser_out[36] = \<const0> ;
  assign m_axis_rq_tuser_out[35] = \<const0> ;
  assign m_axis_rq_tuser_out[34] = \<const0> ;
  assign m_axis_rq_tuser_out[33] = \<const0> ;
  assign m_axis_rq_tuser_out[32] = \<const0> ;
  assign m_axis_rq_tuser_out[31] = \<const0> ;
  assign m_axis_rq_tuser_out[30] = \<const0> ;
  assign m_axis_rq_tuser_out[29] = \<const0> ;
  assign m_axis_rq_tuser_out[28] = \<const0> ;
  assign m_axis_rq_tuser_out[27] = \<const0> ;
  assign m_axis_rq_tuser_out[26] = \<const0> ;
  assign m_axis_rq_tuser_out[25] = \<const0> ;
  assign m_axis_rq_tuser_out[24] = \<const0> ;
  assign m_axis_rq_tuser_out[23] = \<const0> ;
  assign m_axis_rq_tuser_out[22] = \<const0> ;
  assign m_axis_rq_tuser_out[21] = \<const0> ;
  assign m_axis_rq_tuser_out[20] = \<const0> ;
  assign m_axis_rq_tuser_out[19] = \<const0> ;
  assign m_axis_rq_tuser_out[18] = \<const0> ;
  assign m_axis_rq_tuser_out[17] = \<const0> ;
  assign m_axis_rq_tuser_out[16] = \<const0> ;
  assign m_axis_rq_tuser_out[15] = \<const0> ;
  assign m_axis_rq_tuser_out[14] = \<const0> ;
  assign m_axis_rq_tuser_out[13] = \<const0> ;
  assign m_axis_rq_tuser_out[12] = \<const0> ;
  assign m_axis_rq_tuser_out[11] = \<const0> ;
  assign m_axis_rq_tuser_out[10] = \<const0> ;
  assign m_axis_rq_tuser_out[9] = \<const0> ;
  assign m_axis_rq_tuser_out[8] = \<const0> ;
  assign m_axis_rq_tuser_out[7] = \<const0> ;
  assign m_axis_rq_tuser_out[6] = \<const0> ;
  assign m_axis_rq_tuser_out[5] = \<const0> ;
  assign m_axis_rq_tuser_out[4] = \<const0> ;
  assign m_axis_rq_tuser_out[3] = \<const0> ;
  assign m_axis_rq_tuser_out[2] = \<const0> ;
  assign m_axis_rq_tuser_out[1] = \<const0> ;
  assign m_axis_rq_tuser_out[0] = \<const0> ;
  assign m_axis_rq_tvalid_out = \<const0> ;
  assign m_axis_rx_tkeep_o[7:4] = \^m_axis_rx_tkeep_o [7:4];
  assign m_axis_rx_tkeep_o[3] = \<const0> ;
  assign m_axis_rx_tkeep_o[2] = \<const0> ;
  assign m_axis_rx_tkeep_o[1] = \<const0> ;
  assign m_axis_rx_tkeep_o[0] = \<const0> ;
  assign m_axis_rx_tuser_o[21] = \^m_axis_rx_tuser_o [21];
  assign m_axis_rx_tuser_o[20] = \<const0> ;
  assign m_axis_rx_tuser_o[19:17] = \^m_axis_rx_tuser_o [19:17];
  assign m_axis_rx_tuser_o[16] = \<const0> ;
  assign m_axis_rx_tuser_o[15] = \<const0> ;
  assign m_axis_rx_tuser_o[14] = \^m_axis_rx_tuser_o [14];
  assign m_axis_rx_tuser_o[13] = \<const0> ;
  assign m_axis_rx_tuser_o[12] = \<const0> ;
  assign m_axis_rx_tuser_o[11] = \<const0> ;
  assign m_axis_rx_tuser_o[10] = \<const0> ;
  assign m_axis_rx_tuser_o[9] = \<const0> ;
  assign m_axis_rx_tuser_o[8:0] = \^m_axis_rx_tuser_o [8:0];
  assign mcap_design_switch = \<const0> ;
  assign msix_enable = \<const0> ;
  assign pcie4_cxs0_active_ack_rx_sd = \<const0> ;
  assign pcie4_cxs0_active_req_tx_sd = \<const0> ;
  assign pcie4_cxs0_cntl_chk_tx_sd = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[13] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[12] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[11] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[10] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[9] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[8] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[7] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[6] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[5] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[4] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[3] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[2] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[1] = \<const0> ;
  assign pcie4_cxs0_cntl_tx_sd[0] = \<const0> ;
  assign pcie4_cxs0_crdgnt_chk_rx_sd = \<const0> ;
  assign pcie4_cxs0_crdgnt_rx_sd = \<const0> ;
  assign pcie4_cxs0_crdrtn_chk_tx_sd = \<const0> ;
  assign pcie4_cxs0_crdrtn_tx_sd = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[31] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[30] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[29] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[28] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[27] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[26] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[25] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[24] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[23] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[22] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[21] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[20] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[19] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[18] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[17] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[16] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[15] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[14] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[13] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[12] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[11] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[10] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[9] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[8] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[7] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[6] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[5] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[4] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[3] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[2] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[1] = \<const0> ;
  assign pcie4_cxs0_data_chk_tx_sd[0] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[255] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[254] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[253] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[252] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[251] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[250] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[249] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[248] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[247] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[246] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[245] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[244] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[243] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[242] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[241] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[240] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[239] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[238] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[237] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[236] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[235] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[234] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[233] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[232] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[231] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[230] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[229] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[228] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[227] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[226] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[225] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[224] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[223] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[222] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[221] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[220] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[219] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[218] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[217] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[216] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[215] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[214] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[213] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[212] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[211] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[210] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[209] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[208] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[207] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[206] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[205] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[204] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[203] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[202] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[201] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[200] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[199] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[198] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[197] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[196] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[195] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[194] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[193] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[192] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[191] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[190] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[189] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[188] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[187] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[186] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[185] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[184] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[183] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[182] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[181] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[180] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[179] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[178] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[177] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[176] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[175] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[174] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[173] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[172] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[171] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[170] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[169] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[168] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[167] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[166] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[165] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[164] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[163] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[162] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[161] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[160] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[159] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[158] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[157] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[156] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[155] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[154] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[153] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[152] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[151] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[150] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[149] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[148] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[147] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[146] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[145] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[144] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[143] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[142] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[141] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[140] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[139] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[138] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[137] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[136] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[135] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[134] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[133] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[132] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[131] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[130] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[129] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[128] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[127] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[126] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[125] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[124] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[123] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[122] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[121] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[120] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[119] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[118] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[117] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[116] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[115] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[114] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[113] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[112] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[111] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[110] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[109] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[108] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[107] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[106] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[105] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[104] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[103] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[102] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[101] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[100] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[99] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[98] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[97] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[96] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[95] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[94] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[93] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[92] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[91] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[90] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[89] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[88] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[87] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[86] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[85] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[84] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[83] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[82] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[81] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[80] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[79] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[78] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[77] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[76] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[75] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[74] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[73] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[72] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[71] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[70] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[69] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[68] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[67] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[66] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[65] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[64] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[63] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[62] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[61] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[60] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[59] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[58] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[57] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[56] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[55] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[54] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[53] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[52] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[51] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[50] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[49] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[48] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[47] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[46] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[45] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[44] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[43] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[42] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[41] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[40] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[39] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[38] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[37] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[36] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[35] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[34] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[33] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[32] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[31] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[30] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[29] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[28] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[27] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[26] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[25] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[24] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[23] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[22] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[21] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[20] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[19] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[18] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[17] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[16] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[15] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[14] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[13] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[12] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[11] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[10] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[9] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[8] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[7] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[6] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[5] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[4] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[3] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[2] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[1] = \<const0> ;
  assign pcie4_cxs0_data_tx_sd[0] = \<const0> ;
  assign pcie4_cxs0_deact_hint_rx_sd = \<const0> ;
  assign pcie4_cxs0_valid_chk_tx_sd = \<const0> ;
  assign pcie4_cxs0_valid_tx_sd = \<const0> ;
  assign pcie_cq_np_req_sd[1] = \<const0> ;
  assign pcie_cq_np_req_sd[0] = \<const0> ;
  assign pcieeqrxeqadaptdone_us_in[1] = \<const0> ;
  assign pcieeqrxeqadaptdone_us_in[0] = \<const0> ;
  assign pcieeqrxeqadaptdone_usp_in[1] = \<const0> ;
  assign pcieeqrxeqadaptdone_usp_in[0] = \<const0> ;
  assign pcierateqpll0_usp_in[2] = \<const0> ;
  assign pcierateqpll0_usp_in[1] = \<const0> ;
  assign pcierateqpll0_usp_in[0] = \<const0> ;
  assign pcierateqpll1_usp_in[2] = \<const0> ;
  assign pcierateqpll1_usp_in[1] = \<const0> ;
  assign pcierateqpll1_usp_in[0] = \<const0> ;
  assign pcierstidle_us_in[1] = \<const0> ;
  assign pcierstidle_us_in[0] = \<const0> ;
  assign pcierstidle_usp_in[1] = \<const0> ;
  assign pcierstidle_usp_in[0] = \<const0> ;
  assign pciersttxsyncstart_us_in[1] = \<const0> ;
  assign pciersttxsyncstart_us_in[0] = \<const0> ;
  assign pciersttxsyncstart_usp_in[1] = \<const0> ;
  assign pciersttxsyncstart_usp_in[0] = \<const0> ;
  assign pcieuserratedone_us_in[1] = \<const0> ;
  assign pcieuserratedone_us_in[0] = \<const0> ;
  assign pcieuserratedone_usp_in[1] = \<const0> ;
  assign pcieuserratedone_usp_in[0] = \<const0> ;
  assign pcsrsvdin_us_in[31] = \<const0> ;
  assign pcsrsvdin_us_in[30] = \<const0> ;
  assign pcsrsvdin_us_in[29] = \<const0> ;
  assign pcsrsvdin_us_in[28] = \<const0> ;
  assign pcsrsvdin_us_in[27] = \<const0> ;
  assign pcsrsvdin_us_in[26] = \<const0> ;
  assign pcsrsvdin_us_in[25] = \<const0> ;
  assign pcsrsvdin_us_in[24] = \<const0> ;
  assign pcsrsvdin_us_in[23] = \<const0> ;
  assign pcsrsvdin_us_in[22] = \<const0> ;
  assign pcsrsvdin_us_in[21] = \<const0> ;
  assign pcsrsvdin_us_in[20] = \<const0> ;
  assign pcsrsvdin_us_in[19] = \<const0> ;
  assign pcsrsvdin_us_in[18] = \<const0> ;
  assign pcsrsvdin_us_in[17] = \<const0> ;
  assign pcsrsvdin_us_in[16] = \<const0> ;
  assign pcsrsvdin_us_in[15] = \<const0> ;
  assign pcsrsvdin_us_in[14] = \<const0> ;
  assign pcsrsvdin_us_in[13] = \<const0> ;
  assign pcsrsvdin_us_in[12] = \<const0> ;
  assign pcsrsvdin_us_in[11] = \<const0> ;
  assign pcsrsvdin_us_in[10] = \<const0> ;
  assign pcsrsvdin_us_in[9] = \<const0> ;
  assign pcsrsvdin_us_in[8] = \<const0> ;
  assign pcsrsvdin_us_in[7] = \<const0> ;
  assign pcsrsvdin_us_in[6] = \<const0> ;
  assign pcsrsvdin_us_in[5] = \<const0> ;
  assign pcsrsvdin_us_in[4] = \<const0> ;
  assign pcsrsvdin_us_in[3] = \<const0> ;
  assign pcsrsvdin_us_in[2] = \<const0> ;
  assign pcsrsvdin_us_in[1] = \<const0> ;
  assign pcsrsvdin_us_in[0] = \<const0> ;
  assign phy_prst_n = \<const0> ;
  assign phy_rrst_n = \<const0> ;
  assign phy_rst_fsm[3] = \<const0> ;
  assign phy_rst_fsm[2] = \<const0> ;
  assign phy_rst_fsm[1] = \<const0> ;
  assign phy_rst_fsm[0] = \<const0> ;
  assign phy_rst_idle = \<const0> ;
  assign phy_rxeq_fsm[5] = \<const0> ;
  assign phy_rxeq_fsm[4] = \<const0> ;
  assign phy_rxeq_fsm[3] = \<const0> ;
  assign phy_rxeq_fsm[2] = \<const0> ;
  assign phy_rxeq_fsm[1] = \<const0> ;
  assign phy_rxeq_fsm[0] = \<const0> ;
  assign phy_txeq_ctrl[3] = \<const0> ;
  assign phy_txeq_ctrl[2] = \<const0> ;
  assign phy_txeq_ctrl[1] = \<const0> ;
  assign phy_txeq_ctrl[0] = \<const0> ;
  assign phy_txeq_fsm[5] = \<const0> ;
  assign phy_txeq_fsm[4] = \<const0> ;
  assign phy_txeq_fsm[3] = \<const0> ;
  assign phy_txeq_fsm[2] = \<const0> ;
  assign phy_txeq_fsm[1] = \<const0> ;
  assign phy_txeq_fsm[0] = \<const0> ;
  assign phy_txeq_preset[7] = \<const0> ;
  assign phy_txeq_preset[6] = \<const0> ;
  assign phy_txeq_preset[5] = \<const0> ;
  assign phy_txeq_preset[4] = \<const0> ;
  assign phy_txeq_preset[3] = \<const0> ;
  assign phy_txeq_preset[2] = \<const0> ;
  assign phy_txeq_preset[1] = \<const0> ;
  assign phy_txeq_preset[0] = \<const0> ;
  assign pipe_clk = \<const0> ;
  assign pipe_cpll_lock[1] = \<const0> ;
  assign pipe_cpll_lock[0] = \<const0> ;
  assign pipe_debug[31] = \<const0> ;
  assign pipe_debug[30] = \<const0> ;
  assign pipe_debug[29] = \<const0> ;
  assign pipe_debug[28] = \<const0> ;
  assign pipe_debug[27] = \<const0> ;
  assign pipe_debug[26] = \<const0> ;
  assign pipe_debug[25] = \<const0> ;
  assign pipe_debug[24] = \<const0> ;
  assign pipe_debug[23] = \<const0> ;
  assign pipe_debug[22] = \<const0> ;
  assign pipe_debug[21] = \<const0> ;
  assign pipe_debug[20] = \<const0> ;
  assign pipe_debug[19] = \<const0> ;
  assign pipe_debug[18] = \<const0> ;
  assign pipe_debug[17] = \<const0> ;
  assign pipe_debug[16] = \<const0> ;
  assign pipe_debug[15] = \<const0> ;
  assign pipe_debug[14] = \<const0> ;
  assign pipe_debug[13] = \<const0> ;
  assign pipe_debug[12] = \<const0> ;
  assign pipe_debug[11] = \<const0> ;
  assign pipe_debug[10] = \<const0> ;
  assign pipe_debug[9] = \<const0> ;
  assign pipe_debug[8] = \<const0> ;
  assign pipe_debug[7] = \<const0> ;
  assign pipe_debug[6] = \<const0> ;
  assign pipe_debug[5] = \<const0> ;
  assign pipe_debug[4] = \<const0> ;
  assign pipe_debug[3] = \<const0> ;
  assign pipe_debug[2] = \<const0> ;
  assign pipe_debug[1] = \<const0> ;
  assign pipe_debug[0] = \<const0> ;
  assign pipe_debug_0[1] = \<const0> ;
  assign pipe_debug_0[0] = \<const0> ;
  assign pipe_debug_1[1] = \<const0> ;
  assign pipe_debug_1[0] = \<const0> ;
  assign pipe_debug_2[1] = \<const0> ;
  assign pipe_debug_2[0] = \<const0> ;
  assign pipe_debug_3[1] = \<const0> ;
  assign pipe_debug_3[0] = \<const0> ;
  assign pipe_debug_4[1] = \<const0> ;
  assign pipe_debug_4[0] = \<const0> ;
  assign pipe_debug_5[1] = \<const0> ;
  assign pipe_debug_5[0] = \<const0> ;
  assign pipe_debug_6[1] = \<const0> ;
  assign pipe_debug_6[0] = \<const0> ;
  assign pipe_debug_7[1] = \<const0> ;
  assign pipe_debug_7[0] = \<const0> ;
  assign pipe_debug_8[1] = \<const0> ;
  assign pipe_debug_8[0] = \<const0> ;
  assign pipe_debug_9[1] = \<const0> ;
  assign pipe_debug_9[0] = \<const0> ;
  assign pipe_debug_debug_out_128_0[127] = \<const0> ;
  assign pipe_debug_debug_out_128_0[126] = \<const0> ;
  assign pipe_debug_debug_out_128_0[125] = \<const0> ;
  assign pipe_debug_debug_out_128_0[124] = \<const0> ;
  assign pipe_debug_debug_out_128_0[123] = \<const0> ;
  assign pipe_debug_debug_out_128_0[122] = \<const0> ;
  assign pipe_debug_debug_out_128_0[121] = \<const0> ;
  assign pipe_debug_debug_out_128_0[120] = \<const0> ;
  assign pipe_debug_debug_out_128_0[119] = \<const0> ;
  assign pipe_debug_debug_out_128_0[118] = \<const0> ;
  assign pipe_debug_debug_out_128_0[117] = \<const0> ;
  assign pipe_debug_debug_out_128_0[116] = \<const0> ;
  assign pipe_debug_debug_out_128_0[115] = \<const0> ;
  assign pipe_debug_debug_out_128_0[114] = \<const0> ;
  assign pipe_debug_debug_out_128_0[113] = \<const0> ;
  assign pipe_debug_debug_out_128_0[112] = \<const0> ;
  assign pipe_debug_debug_out_128_0[111] = \<const0> ;
  assign pipe_debug_debug_out_128_0[110] = \<const0> ;
  assign pipe_debug_debug_out_128_0[109] = \<const0> ;
  assign pipe_debug_debug_out_128_0[108] = \<const0> ;
  assign pipe_debug_debug_out_128_0[107] = \<const0> ;
  assign pipe_debug_debug_out_128_0[106] = \<const0> ;
  assign pipe_debug_debug_out_128_0[105] = \<const0> ;
  assign pipe_debug_debug_out_128_0[104] = \<const0> ;
  assign pipe_debug_debug_out_128_0[103] = \<const0> ;
  assign pipe_debug_debug_out_128_0[102] = \<const0> ;
  assign pipe_debug_debug_out_128_0[101] = \<const0> ;
  assign pipe_debug_debug_out_128_0[100] = \<const0> ;
  assign pipe_debug_debug_out_128_0[99] = \<const0> ;
  assign pipe_debug_debug_out_128_0[98] = \<const0> ;
  assign pipe_debug_debug_out_128_0[97] = \<const0> ;
  assign pipe_debug_debug_out_128_0[96] = \<const0> ;
  assign pipe_debug_debug_out_128_0[95] = \<const0> ;
  assign pipe_debug_debug_out_128_0[94] = \<const0> ;
  assign pipe_debug_debug_out_128_0[93] = \<const0> ;
  assign pipe_debug_debug_out_128_0[92] = \<const0> ;
  assign pipe_debug_debug_out_128_0[91] = \<const0> ;
  assign pipe_debug_debug_out_128_0[90] = \<const0> ;
  assign pipe_debug_debug_out_128_0[89] = \<const0> ;
  assign pipe_debug_debug_out_128_0[88] = \<const0> ;
  assign pipe_debug_debug_out_128_0[87] = \<const0> ;
  assign pipe_debug_debug_out_128_0[86] = \<const0> ;
  assign pipe_debug_debug_out_128_0[85] = \<const0> ;
  assign pipe_debug_debug_out_128_0[84] = \<const0> ;
  assign pipe_debug_debug_out_128_0[83] = \<const0> ;
  assign pipe_debug_debug_out_128_0[82] = \<const0> ;
  assign pipe_debug_debug_out_128_0[81] = \<const0> ;
  assign pipe_debug_debug_out_128_0[80] = \<const0> ;
  assign pipe_debug_debug_out_128_0[79] = \<const0> ;
  assign pipe_debug_debug_out_128_0[78] = \<const0> ;
  assign pipe_debug_debug_out_128_0[77] = \<const0> ;
  assign pipe_debug_debug_out_128_0[76] = \<const0> ;
  assign pipe_debug_debug_out_128_0[75] = \<const0> ;
  assign pipe_debug_debug_out_128_0[74] = \<const0> ;
  assign pipe_debug_debug_out_128_0[73] = \<const0> ;
  assign pipe_debug_debug_out_128_0[72] = \<const0> ;
  assign pipe_debug_debug_out_128_0[71] = \<const0> ;
  assign pipe_debug_debug_out_128_0[70] = \<const0> ;
  assign pipe_debug_debug_out_128_0[69] = \<const0> ;
  assign pipe_debug_debug_out_128_0[68] = \<const0> ;
  assign pipe_debug_debug_out_128_0[67] = \<const0> ;
  assign pipe_debug_debug_out_128_0[66] = \<const0> ;
  assign pipe_debug_debug_out_128_0[65] = \<const0> ;
  assign pipe_debug_debug_out_128_0[64] = \<const0> ;
  assign pipe_debug_debug_out_128_0[63] = \<const0> ;
  assign pipe_debug_debug_out_128_0[62] = \<const0> ;
  assign pipe_debug_debug_out_128_0[61] = \<const0> ;
  assign pipe_debug_debug_out_128_0[60] = \<const0> ;
  assign pipe_debug_debug_out_128_0[59] = \<const0> ;
  assign pipe_debug_debug_out_128_0[58] = \<const0> ;
  assign pipe_debug_debug_out_128_0[57] = \<const0> ;
  assign pipe_debug_debug_out_128_0[56] = \<const0> ;
  assign pipe_debug_debug_out_128_0[55] = \<const0> ;
  assign pipe_debug_debug_out_128_0[54] = \<const0> ;
  assign pipe_debug_debug_out_128_0[53] = \<const0> ;
  assign pipe_debug_debug_out_128_0[52] = \<const0> ;
  assign pipe_debug_debug_out_128_0[51] = \<const0> ;
  assign pipe_debug_debug_out_128_0[50] = \<const0> ;
  assign pipe_debug_debug_out_128_0[49] = \<const0> ;
  assign pipe_debug_debug_out_128_0[48] = \<const0> ;
  assign pipe_debug_debug_out_128_0[47] = \<const0> ;
  assign pipe_debug_debug_out_128_0[46] = \<const0> ;
  assign pipe_debug_debug_out_128_0[45] = \<const0> ;
  assign pipe_debug_debug_out_128_0[44] = \<const0> ;
  assign pipe_debug_debug_out_128_0[43] = \<const0> ;
  assign pipe_debug_debug_out_128_0[42] = \<const0> ;
  assign pipe_debug_debug_out_128_0[41] = \<const0> ;
  assign pipe_debug_debug_out_128_0[40] = \<const0> ;
  assign pipe_debug_debug_out_128_0[39] = \<const0> ;
  assign pipe_debug_debug_out_128_0[38] = \<const0> ;
  assign pipe_debug_debug_out_128_0[37] = \<const0> ;
  assign pipe_debug_debug_out_128_0[36] = \<const0> ;
  assign pipe_debug_debug_out_128_0[35] = \<const0> ;
  assign pipe_debug_debug_out_128_0[34] = \<const0> ;
  assign pipe_debug_debug_out_128_0[33] = \<const0> ;
  assign pipe_debug_debug_out_128_0[32] = \<const0> ;
  assign pipe_debug_debug_out_128_0[31] = \<const0> ;
  assign pipe_debug_debug_out_128_0[30] = \<const0> ;
  assign pipe_debug_debug_out_128_0[29] = \<const0> ;
  assign pipe_debug_debug_out_128_0[28] = \<const0> ;
  assign pipe_debug_debug_out_128_0[27] = \<const0> ;
  assign pipe_debug_debug_out_128_0[26] = \<const0> ;
  assign pipe_debug_debug_out_128_0[25] = \<const0> ;
  assign pipe_debug_debug_out_128_0[24] = \<const0> ;
  assign pipe_debug_debug_out_128_0[23] = \<const0> ;
  assign pipe_debug_debug_out_128_0[22] = \<const0> ;
  assign pipe_debug_debug_out_128_0[21] = \<const0> ;
  assign pipe_debug_debug_out_128_0[20] = \<const0> ;
  assign pipe_debug_debug_out_128_0[19] = \<const0> ;
  assign pipe_debug_debug_out_128_0[18] = \<const0> ;
  assign pipe_debug_debug_out_128_0[17] = \<const0> ;
  assign pipe_debug_debug_out_128_0[16] = \<const0> ;
  assign pipe_debug_debug_out_128_0[15] = \<const0> ;
  assign pipe_debug_debug_out_128_0[14] = \<const0> ;
  assign pipe_debug_debug_out_128_0[13] = \<const0> ;
  assign pipe_debug_debug_out_128_0[12] = \<const0> ;
  assign pipe_debug_debug_out_128_0[11] = \<const0> ;
  assign pipe_debug_debug_out_128_0[10] = \<const0> ;
  assign pipe_debug_debug_out_128_0[9] = \<const0> ;
  assign pipe_debug_debug_out_128_0[8] = \<const0> ;
  assign pipe_debug_debug_out_128_0[7] = \<const0> ;
  assign pipe_debug_debug_out_128_0[6] = \<const0> ;
  assign pipe_debug_debug_out_128_0[5] = \<const0> ;
  assign pipe_debug_debug_out_128_0[4] = \<const0> ;
  assign pipe_debug_debug_out_128_0[3] = \<const0> ;
  assign pipe_debug_debug_out_128_0[2] = \<const0> ;
  assign pipe_debug_debug_out_128_0[1] = \<const0> ;
  assign pipe_debug_debug_out_128_0[0] = \<const0> ;
  assign pipe_debug_debug_out_128_1[127] = \<const0> ;
  assign pipe_debug_debug_out_128_1[126] = \<const0> ;
  assign pipe_debug_debug_out_128_1[125] = \<const0> ;
  assign pipe_debug_debug_out_128_1[124] = \<const0> ;
  assign pipe_debug_debug_out_128_1[123] = \<const0> ;
  assign pipe_debug_debug_out_128_1[122] = \<const0> ;
  assign pipe_debug_debug_out_128_1[121] = \<const0> ;
  assign pipe_debug_debug_out_128_1[120] = \<const0> ;
  assign pipe_debug_debug_out_128_1[119] = \<const0> ;
  assign pipe_debug_debug_out_128_1[118] = \<const0> ;
  assign pipe_debug_debug_out_128_1[117] = \<const0> ;
  assign pipe_debug_debug_out_128_1[116] = \<const0> ;
  assign pipe_debug_debug_out_128_1[115] = \<const0> ;
  assign pipe_debug_debug_out_128_1[114] = \<const0> ;
  assign pipe_debug_debug_out_128_1[113] = \<const0> ;
  assign pipe_debug_debug_out_128_1[112] = \<const0> ;
  assign pipe_debug_debug_out_128_1[111] = \<const0> ;
  assign pipe_debug_debug_out_128_1[110] = \<const0> ;
  assign pipe_debug_debug_out_128_1[109] = \<const0> ;
  assign pipe_debug_debug_out_128_1[108] = \<const0> ;
  assign pipe_debug_debug_out_128_1[107] = \<const0> ;
  assign pipe_debug_debug_out_128_1[106] = \<const0> ;
  assign pipe_debug_debug_out_128_1[105] = \<const0> ;
  assign pipe_debug_debug_out_128_1[104] = \<const0> ;
  assign pipe_debug_debug_out_128_1[103] = \<const0> ;
  assign pipe_debug_debug_out_128_1[102] = \<const0> ;
  assign pipe_debug_debug_out_128_1[101] = \<const0> ;
  assign pipe_debug_debug_out_128_1[100] = \<const0> ;
  assign pipe_debug_debug_out_128_1[99] = \<const0> ;
  assign pipe_debug_debug_out_128_1[98] = \<const0> ;
  assign pipe_debug_debug_out_128_1[97] = \<const0> ;
  assign pipe_debug_debug_out_128_1[96] = \<const0> ;
  assign pipe_debug_debug_out_128_1[95] = \<const0> ;
  assign pipe_debug_debug_out_128_1[94] = \<const0> ;
  assign pipe_debug_debug_out_128_1[93] = \<const0> ;
  assign pipe_debug_debug_out_128_1[92] = \<const0> ;
  assign pipe_debug_debug_out_128_1[91] = \<const0> ;
  assign pipe_debug_debug_out_128_1[90] = \<const0> ;
  assign pipe_debug_debug_out_128_1[89] = \<const0> ;
  assign pipe_debug_debug_out_128_1[88] = \<const0> ;
  assign pipe_debug_debug_out_128_1[87] = \<const0> ;
  assign pipe_debug_debug_out_128_1[86] = \<const0> ;
  assign pipe_debug_debug_out_128_1[85] = \<const0> ;
  assign pipe_debug_debug_out_128_1[84] = \<const0> ;
  assign pipe_debug_debug_out_128_1[83] = \<const0> ;
  assign pipe_debug_debug_out_128_1[82] = \<const0> ;
  assign pipe_debug_debug_out_128_1[81] = \<const0> ;
  assign pipe_debug_debug_out_128_1[80] = \<const0> ;
  assign pipe_debug_debug_out_128_1[79] = \<const0> ;
  assign pipe_debug_debug_out_128_1[78] = \<const0> ;
  assign pipe_debug_debug_out_128_1[77] = \<const0> ;
  assign pipe_debug_debug_out_128_1[76] = \<const0> ;
  assign pipe_debug_debug_out_128_1[75] = \<const0> ;
  assign pipe_debug_debug_out_128_1[74] = \<const0> ;
  assign pipe_debug_debug_out_128_1[73] = \<const0> ;
  assign pipe_debug_debug_out_128_1[72] = \<const0> ;
  assign pipe_debug_debug_out_128_1[71] = \<const0> ;
  assign pipe_debug_debug_out_128_1[70] = \<const0> ;
  assign pipe_debug_debug_out_128_1[69] = \<const0> ;
  assign pipe_debug_debug_out_128_1[68] = \<const0> ;
  assign pipe_debug_debug_out_128_1[67] = \<const0> ;
  assign pipe_debug_debug_out_128_1[66] = \<const0> ;
  assign pipe_debug_debug_out_128_1[65] = \<const0> ;
  assign pipe_debug_debug_out_128_1[64] = \<const0> ;
  assign pipe_debug_debug_out_128_1[63] = \<const0> ;
  assign pipe_debug_debug_out_128_1[62] = \<const0> ;
  assign pipe_debug_debug_out_128_1[61] = \<const0> ;
  assign pipe_debug_debug_out_128_1[60] = \<const0> ;
  assign pipe_debug_debug_out_128_1[59] = \<const0> ;
  assign pipe_debug_debug_out_128_1[58] = \<const0> ;
  assign pipe_debug_debug_out_128_1[57] = \<const0> ;
  assign pipe_debug_debug_out_128_1[56] = \<const0> ;
  assign pipe_debug_debug_out_128_1[55] = \<const0> ;
  assign pipe_debug_debug_out_128_1[54] = \<const0> ;
  assign pipe_debug_debug_out_128_1[53] = \<const0> ;
  assign pipe_debug_debug_out_128_1[52] = \<const0> ;
  assign pipe_debug_debug_out_128_1[51] = \<const0> ;
  assign pipe_debug_debug_out_128_1[50] = \<const0> ;
  assign pipe_debug_debug_out_128_1[49] = \<const0> ;
  assign pipe_debug_debug_out_128_1[48] = \<const0> ;
  assign pipe_debug_debug_out_128_1[47] = \<const0> ;
  assign pipe_debug_debug_out_128_1[46] = \<const0> ;
  assign pipe_debug_debug_out_128_1[45] = \<const0> ;
  assign pipe_debug_debug_out_128_1[44] = \<const0> ;
  assign pipe_debug_debug_out_128_1[43] = \<const0> ;
  assign pipe_debug_debug_out_128_1[42] = \<const0> ;
  assign pipe_debug_debug_out_128_1[41] = \<const0> ;
  assign pipe_debug_debug_out_128_1[40] = \<const0> ;
  assign pipe_debug_debug_out_128_1[39] = \<const0> ;
  assign pipe_debug_debug_out_128_1[38] = \<const0> ;
  assign pipe_debug_debug_out_128_1[37] = \<const0> ;
  assign pipe_debug_debug_out_128_1[36] = \<const0> ;
  assign pipe_debug_debug_out_128_1[35] = \<const0> ;
  assign pipe_debug_debug_out_128_1[34] = \<const0> ;
  assign pipe_debug_debug_out_128_1[33] = \<const0> ;
  assign pipe_debug_debug_out_128_1[32] = \<const0> ;
  assign pipe_debug_debug_out_128_1[31] = \<const0> ;
  assign pipe_debug_debug_out_128_1[30] = \<const0> ;
  assign pipe_debug_debug_out_128_1[29] = \<const0> ;
  assign pipe_debug_debug_out_128_1[28] = \<const0> ;
  assign pipe_debug_debug_out_128_1[27] = \<const0> ;
  assign pipe_debug_debug_out_128_1[26] = \<const0> ;
  assign pipe_debug_debug_out_128_1[25] = \<const0> ;
  assign pipe_debug_debug_out_128_1[24] = \<const0> ;
  assign pipe_debug_debug_out_128_1[23] = \<const0> ;
  assign pipe_debug_debug_out_128_1[22] = \<const0> ;
  assign pipe_debug_debug_out_128_1[21] = \<const0> ;
  assign pipe_debug_debug_out_128_1[20] = \<const0> ;
  assign pipe_debug_debug_out_128_1[19] = \<const0> ;
  assign pipe_debug_debug_out_128_1[18] = \<const0> ;
  assign pipe_debug_debug_out_128_1[17] = \<const0> ;
  assign pipe_debug_debug_out_128_1[16] = \<const0> ;
  assign pipe_debug_debug_out_128_1[15] = \<const0> ;
  assign pipe_debug_debug_out_128_1[14] = \<const0> ;
  assign pipe_debug_debug_out_128_1[13] = \<const0> ;
  assign pipe_debug_debug_out_128_1[12] = \<const0> ;
  assign pipe_debug_debug_out_128_1[11] = \<const0> ;
  assign pipe_debug_debug_out_128_1[10] = \<const0> ;
  assign pipe_debug_debug_out_128_1[9] = \<const0> ;
  assign pipe_debug_debug_out_128_1[8] = \<const0> ;
  assign pipe_debug_debug_out_128_1[7] = \<const0> ;
  assign pipe_debug_debug_out_128_1[6] = \<const0> ;
  assign pipe_debug_debug_out_128_1[5] = \<const0> ;
  assign pipe_debug_debug_out_128_1[4] = \<const0> ;
  assign pipe_debug_debug_out_128_1[3] = \<const0> ;
  assign pipe_debug_debug_out_128_1[2] = \<const0> ;
  assign pipe_debug_debug_out_128_1[1] = \<const0> ;
  assign pipe_debug_debug_out_128_1[0] = \<const0> ;
  assign pipe_debug_debug_out_128_2[127] = \<const0> ;
  assign pipe_debug_debug_out_128_2[126] = \<const0> ;
  assign pipe_debug_debug_out_128_2[125] = \<const0> ;
  assign pipe_debug_debug_out_128_2[124] = \<const0> ;
  assign pipe_debug_debug_out_128_2[123] = \<const0> ;
  assign pipe_debug_debug_out_128_2[122] = \<const0> ;
  assign pipe_debug_debug_out_128_2[121] = \<const0> ;
  assign pipe_debug_debug_out_128_2[120] = \<const0> ;
  assign pipe_debug_debug_out_128_2[119] = \<const0> ;
  assign pipe_debug_debug_out_128_2[118] = \<const0> ;
  assign pipe_debug_debug_out_128_2[117] = \<const0> ;
  assign pipe_debug_debug_out_128_2[116] = \<const0> ;
  assign pipe_debug_debug_out_128_2[115] = \<const0> ;
  assign pipe_debug_debug_out_128_2[114] = \<const0> ;
  assign pipe_debug_debug_out_128_2[113] = \<const0> ;
  assign pipe_debug_debug_out_128_2[112] = \<const0> ;
  assign pipe_debug_debug_out_128_2[111] = \<const0> ;
  assign pipe_debug_debug_out_128_2[110] = \<const0> ;
  assign pipe_debug_debug_out_128_2[109] = \<const0> ;
  assign pipe_debug_debug_out_128_2[108] = \<const0> ;
  assign pipe_debug_debug_out_128_2[107] = \<const0> ;
  assign pipe_debug_debug_out_128_2[106] = \<const0> ;
  assign pipe_debug_debug_out_128_2[105] = \<const0> ;
  assign pipe_debug_debug_out_128_2[104] = \<const0> ;
  assign pipe_debug_debug_out_128_2[103] = \<const0> ;
  assign pipe_debug_debug_out_128_2[102] = \<const0> ;
  assign pipe_debug_debug_out_128_2[101] = \<const0> ;
  assign pipe_debug_debug_out_128_2[100] = \<const0> ;
  assign pipe_debug_debug_out_128_2[99] = \<const0> ;
  assign pipe_debug_debug_out_128_2[98] = \<const0> ;
  assign pipe_debug_debug_out_128_2[97] = \<const0> ;
  assign pipe_debug_debug_out_128_2[96] = \<const0> ;
  assign pipe_debug_debug_out_128_2[95] = \<const0> ;
  assign pipe_debug_debug_out_128_2[94] = \<const0> ;
  assign pipe_debug_debug_out_128_2[93] = \<const0> ;
  assign pipe_debug_debug_out_128_2[92] = \<const0> ;
  assign pipe_debug_debug_out_128_2[91] = \<const0> ;
  assign pipe_debug_debug_out_128_2[90] = \<const0> ;
  assign pipe_debug_debug_out_128_2[89] = \<const0> ;
  assign pipe_debug_debug_out_128_2[88] = \<const0> ;
  assign pipe_debug_debug_out_128_2[87] = \<const0> ;
  assign pipe_debug_debug_out_128_2[86] = \<const0> ;
  assign pipe_debug_debug_out_128_2[85] = \<const0> ;
  assign pipe_debug_debug_out_128_2[84] = \<const0> ;
  assign pipe_debug_debug_out_128_2[83] = \<const0> ;
  assign pipe_debug_debug_out_128_2[82] = \<const0> ;
  assign pipe_debug_debug_out_128_2[81] = \<const0> ;
  assign pipe_debug_debug_out_128_2[80] = \<const0> ;
  assign pipe_debug_debug_out_128_2[79] = \<const0> ;
  assign pipe_debug_debug_out_128_2[78] = \<const0> ;
  assign pipe_debug_debug_out_128_2[77] = \<const0> ;
  assign pipe_debug_debug_out_128_2[76] = \<const0> ;
  assign pipe_debug_debug_out_128_2[75] = \<const0> ;
  assign pipe_debug_debug_out_128_2[74] = \<const0> ;
  assign pipe_debug_debug_out_128_2[73] = \<const0> ;
  assign pipe_debug_debug_out_128_2[72] = \<const0> ;
  assign pipe_debug_debug_out_128_2[71] = \<const0> ;
  assign pipe_debug_debug_out_128_2[70] = \<const0> ;
  assign pipe_debug_debug_out_128_2[69] = \<const0> ;
  assign pipe_debug_debug_out_128_2[68] = \<const0> ;
  assign pipe_debug_debug_out_128_2[67] = \<const0> ;
  assign pipe_debug_debug_out_128_2[66] = \<const0> ;
  assign pipe_debug_debug_out_128_2[65] = \<const0> ;
  assign pipe_debug_debug_out_128_2[64] = \<const0> ;
  assign pipe_debug_debug_out_128_2[63] = \<const0> ;
  assign pipe_debug_debug_out_128_2[62] = \<const0> ;
  assign pipe_debug_debug_out_128_2[61] = \<const0> ;
  assign pipe_debug_debug_out_128_2[60] = \<const0> ;
  assign pipe_debug_debug_out_128_2[59] = \<const0> ;
  assign pipe_debug_debug_out_128_2[58] = \<const0> ;
  assign pipe_debug_debug_out_128_2[57] = \<const0> ;
  assign pipe_debug_debug_out_128_2[56] = \<const0> ;
  assign pipe_debug_debug_out_128_2[55] = \<const0> ;
  assign pipe_debug_debug_out_128_2[54] = \<const0> ;
  assign pipe_debug_debug_out_128_2[53] = \<const0> ;
  assign pipe_debug_debug_out_128_2[52] = \<const0> ;
  assign pipe_debug_debug_out_128_2[51] = \<const0> ;
  assign pipe_debug_debug_out_128_2[50] = \<const0> ;
  assign pipe_debug_debug_out_128_2[49] = \<const0> ;
  assign pipe_debug_debug_out_128_2[48] = \<const0> ;
  assign pipe_debug_debug_out_128_2[47] = \<const0> ;
  assign pipe_debug_debug_out_128_2[46] = \<const0> ;
  assign pipe_debug_debug_out_128_2[45] = \<const0> ;
  assign pipe_debug_debug_out_128_2[44] = \<const0> ;
  assign pipe_debug_debug_out_128_2[43] = \<const0> ;
  assign pipe_debug_debug_out_128_2[42] = \<const0> ;
  assign pipe_debug_debug_out_128_2[41] = \<const0> ;
  assign pipe_debug_debug_out_128_2[40] = \<const0> ;
  assign pipe_debug_debug_out_128_2[39] = \<const0> ;
  assign pipe_debug_debug_out_128_2[38] = \<const0> ;
  assign pipe_debug_debug_out_128_2[37] = \<const0> ;
  assign pipe_debug_debug_out_128_2[36] = \<const0> ;
  assign pipe_debug_debug_out_128_2[35] = \<const0> ;
  assign pipe_debug_debug_out_128_2[34] = \<const0> ;
  assign pipe_debug_debug_out_128_2[33] = \<const0> ;
  assign pipe_debug_debug_out_128_2[32] = \<const0> ;
  assign pipe_debug_debug_out_128_2[31] = \<const0> ;
  assign pipe_debug_debug_out_128_2[30] = \<const0> ;
  assign pipe_debug_debug_out_128_2[29] = \<const0> ;
  assign pipe_debug_debug_out_128_2[28] = \<const0> ;
  assign pipe_debug_debug_out_128_2[27] = \<const0> ;
  assign pipe_debug_debug_out_128_2[26] = \<const0> ;
  assign pipe_debug_debug_out_128_2[25] = \<const0> ;
  assign pipe_debug_debug_out_128_2[24] = \<const0> ;
  assign pipe_debug_debug_out_128_2[23] = \<const0> ;
  assign pipe_debug_debug_out_128_2[22] = \<const0> ;
  assign pipe_debug_debug_out_128_2[21] = \<const0> ;
  assign pipe_debug_debug_out_128_2[20] = \<const0> ;
  assign pipe_debug_debug_out_128_2[19] = \<const0> ;
  assign pipe_debug_debug_out_128_2[18] = \<const0> ;
  assign pipe_debug_debug_out_128_2[17] = \<const0> ;
  assign pipe_debug_debug_out_128_2[16] = \<const0> ;
  assign pipe_debug_debug_out_128_2[15] = \<const0> ;
  assign pipe_debug_debug_out_128_2[14] = \<const0> ;
  assign pipe_debug_debug_out_128_2[13] = \<const0> ;
  assign pipe_debug_debug_out_128_2[12] = \<const0> ;
  assign pipe_debug_debug_out_128_2[11] = \<const0> ;
  assign pipe_debug_debug_out_128_2[10] = \<const0> ;
  assign pipe_debug_debug_out_128_2[9] = \<const0> ;
  assign pipe_debug_debug_out_128_2[8] = \<const0> ;
  assign pipe_debug_debug_out_128_2[7] = \<const0> ;
  assign pipe_debug_debug_out_128_2[6] = \<const0> ;
  assign pipe_debug_debug_out_128_2[5] = \<const0> ;
  assign pipe_debug_debug_out_128_2[4] = \<const0> ;
  assign pipe_debug_debug_out_128_2[3] = \<const0> ;
  assign pipe_debug_debug_out_128_2[2] = \<const0> ;
  assign pipe_debug_debug_out_128_2[1] = \<const0> ;
  assign pipe_debug_debug_out_128_2[0] = \<const0> ;
  assign pipe_debug_debug_out_128_3[127] = \<const0> ;
  assign pipe_debug_debug_out_128_3[126] = \<const0> ;
  assign pipe_debug_debug_out_128_3[125] = \<const0> ;
  assign pipe_debug_debug_out_128_3[124] = \<const0> ;
  assign pipe_debug_debug_out_128_3[123] = \<const0> ;
  assign pipe_debug_debug_out_128_3[122] = \<const0> ;
  assign pipe_debug_debug_out_128_3[121] = \<const0> ;
  assign pipe_debug_debug_out_128_3[120] = \<const0> ;
  assign pipe_debug_debug_out_128_3[119] = \<const0> ;
  assign pipe_debug_debug_out_128_3[118] = \<const0> ;
  assign pipe_debug_debug_out_128_3[117] = \<const0> ;
  assign pipe_debug_debug_out_128_3[116] = \<const0> ;
  assign pipe_debug_debug_out_128_3[115] = \<const0> ;
  assign pipe_debug_debug_out_128_3[114] = \<const0> ;
  assign pipe_debug_debug_out_128_3[113] = \<const0> ;
  assign pipe_debug_debug_out_128_3[112] = \<const0> ;
  assign pipe_debug_debug_out_128_3[111] = \<const0> ;
  assign pipe_debug_debug_out_128_3[110] = \<const0> ;
  assign pipe_debug_debug_out_128_3[109] = \<const0> ;
  assign pipe_debug_debug_out_128_3[108] = \<const0> ;
  assign pipe_debug_debug_out_128_3[107] = \<const0> ;
  assign pipe_debug_debug_out_128_3[106] = \<const0> ;
  assign pipe_debug_debug_out_128_3[105] = \<const0> ;
  assign pipe_debug_debug_out_128_3[104] = \<const0> ;
  assign pipe_debug_debug_out_128_3[103] = \<const0> ;
  assign pipe_debug_debug_out_128_3[102] = \<const0> ;
  assign pipe_debug_debug_out_128_3[101] = \<const0> ;
  assign pipe_debug_debug_out_128_3[100] = \<const0> ;
  assign pipe_debug_debug_out_128_3[99] = \<const0> ;
  assign pipe_debug_debug_out_128_3[98] = \<const0> ;
  assign pipe_debug_debug_out_128_3[97] = \<const0> ;
  assign pipe_debug_debug_out_128_3[96] = \<const0> ;
  assign pipe_debug_debug_out_128_3[95] = \<const0> ;
  assign pipe_debug_debug_out_128_3[94] = \<const0> ;
  assign pipe_debug_debug_out_128_3[93] = \<const0> ;
  assign pipe_debug_debug_out_128_3[92] = \<const0> ;
  assign pipe_debug_debug_out_128_3[91] = \<const0> ;
  assign pipe_debug_debug_out_128_3[90] = \<const0> ;
  assign pipe_debug_debug_out_128_3[89] = \<const0> ;
  assign pipe_debug_debug_out_128_3[88] = \<const0> ;
  assign pipe_debug_debug_out_128_3[87] = \<const0> ;
  assign pipe_debug_debug_out_128_3[86] = \<const0> ;
  assign pipe_debug_debug_out_128_3[85] = \<const0> ;
  assign pipe_debug_debug_out_128_3[84] = \<const0> ;
  assign pipe_debug_debug_out_128_3[83] = \<const0> ;
  assign pipe_debug_debug_out_128_3[82] = \<const0> ;
  assign pipe_debug_debug_out_128_3[81] = \<const0> ;
  assign pipe_debug_debug_out_128_3[80] = \<const0> ;
  assign pipe_debug_debug_out_128_3[79] = \<const0> ;
  assign pipe_debug_debug_out_128_3[78] = \<const0> ;
  assign pipe_debug_debug_out_128_3[77] = \<const0> ;
  assign pipe_debug_debug_out_128_3[76] = \<const0> ;
  assign pipe_debug_debug_out_128_3[75] = \<const0> ;
  assign pipe_debug_debug_out_128_3[74] = \<const0> ;
  assign pipe_debug_debug_out_128_3[73] = \<const0> ;
  assign pipe_debug_debug_out_128_3[72] = \<const0> ;
  assign pipe_debug_debug_out_128_3[71] = \<const0> ;
  assign pipe_debug_debug_out_128_3[70] = \<const0> ;
  assign pipe_debug_debug_out_128_3[69] = \<const0> ;
  assign pipe_debug_debug_out_128_3[68] = \<const0> ;
  assign pipe_debug_debug_out_128_3[67] = \<const0> ;
  assign pipe_debug_debug_out_128_3[66] = \<const0> ;
  assign pipe_debug_debug_out_128_3[65] = \<const0> ;
  assign pipe_debug_debug_out_128_3[64] = \<const0> ;
  assign pipe_debug_debug_out_128_3[63] = \<const0> ;
  assign pipe_debug_debug_out_128_3[62] = \<const0> ;
  assign pipe_debug_debug_out_128_3[61] = \<const0> ;
  assign pipe_debug_debug_out_128_3[60] = \<const0> ;
  assign pipe_debug_debug_out_128_3[59] = \<const0> ;
  assign pipe_debug_debug_out_128_3[58] = \<const0> ;
  assign pipe_debug_debug_out_128_3[57] = \<const0> ;
  assign pipe_debug_debug_out_128_3[56] = \<const0> ;
  assign pipe_debug_debug_out_128_3[55] = \<const0> ;
  assign pipe_debug_debug_out_128_3[54] = \<const0> ;
  assign pipe_debug_debug_out_128_3[53] = \<const0> ;
  assign pipe_debug_debug_out_128_3[52] = \<const0> ;
  assign pipe_debug_debug_out_128_3[51] = \<const0> ;
  assign pipe_debug_debug_out_128_3[50] = \<const0> ;
  assign pipe_debug_debug_out_128_3[49] = \<const0> ;
  assign pipe_debug_debug_out_128_3[48] = \<const0> ;
  assign pipe_debug_debug_out_128_3[47] = \<const0> ;
  assign pipe_debug_debug_out_128_3[46] = \<const0> ;
  assign pipe_debug_debug_out_128_3[45] = \<const0> ;
  assign pipe_debug_debug_out_128_3[44] = \<const0> ;
  assign pipe_debug_debug_out_128_3[43] = \<const0> ;
  assign pipe_debug_debug_out_128_3[42] = \<const0> ;
  assign pipe_debug_debug_out_128_3[41] = \<const0> ;
  assign pipe_debug_debug_out_128_3[40] = \<const0> ;
  assign pipe_debug_debug_out_128_3[39] = \<const0> ;
  assign pipe_debug_debug_out_128_3[38] = \<const0> ;
  assign pipe_debug_debug_out_128_3[37] = \<const0> ;
  assign pipe_debug_debug_out_128_3[36] = \<const0> ;
  assign pipe_debug_debug_out_128_3[35] = \<const0> ;
  assign pipe_debug_debug_out_128_3[34] = \<const0> ;
  assign pipe_debug_debug_out_128_3[33] = \<const0> ;
  assign pipe_debug_debug_out_128_3[32] = \<const0> ;
  assign pipe_debug_debug_out_128_3[31] = \<const0> ;
  assign pipe_debug_debug_out_128_3[30] = \<const0> ;
  assign pipe_debug_debug_out_128_3[29] = \<const0> ;
  assign pipe_debug_debug_out_128_3[28] = \<const0> ;
  assign pipe_debug_debug_out_128_3[27] = \<const0> ;
  assign pipe_debug_debug_out_128_3[26] = \<const0> ;
  assign pipe_debug_debug_out_128_3[25] = \<const0> ;
  assign pipe_debug_debug_out_128_3[24] = \<const0> ;
  assign pipe_debug_debug_out_128_3[23] = \<const0> ;
  assign pipe_debug_debug_out_128_3[22] = \<const0> ;
  assign pipe_debug_debug_out_128_3[21] = \<const0> ;
  assign pipe_debug_debug_out_128_3[20] = \<const0> ;
  assign pipe_debug_debug_out_128_3[19] = \<const0> ;
  assign pipe_debug_debug_out_128_3[18] = \<const0> ;
  assign pipe_debug_debug_out_128_3[17] = \<const0> ;
  assign pipe_debug_debug_out_128_3[16] = \<const0> ;
  assign pipe_debug_debug_out_128_3[15] = \<const0> ;
  assign pipe_debug_debug_out_128_3[14] = \<const0> ;
  assign pipe_debug_debug_out_128_3[13] = \<const0> ;
  assign pipe_debug_debug_out_128_3[12] = \<const0> ;
  assign pipe_debug_debug_out_128_3[11] = \<const0> ;
  assign pipe_debug_debug_out_128_3[10] = \<const0> ;
  assign pipe_debug_debug_out_128_3[9] = \<const0> ;
  assign pipe_debug_debug_out_128_3[8] = \<const0> ;
  assign pipe_debug_debug_out_128_3[7] = \<const0> ;
  assign pipe_debug_debug_out_128_3[6] = \<const0> ;
  assign pipe_debug_debug_out_128_3[5] = \<const0> ;
  assign pipe_debug_debug_out_128_3[4] = \<const0> ;
  assign pipe_debug_debug_out_128_3[3] = \<const0> ;
  assign pipe_debug_debug_out_128_3[2] = \<const0> ;
  assign pipe_debug_debug_out_128_3[1] = \<const0> ;
  assign pipe_debug_debug_out_128_3[0] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[15] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[14] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[13] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[12] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[11] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[10] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[9] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[8] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[7] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[6] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[5] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[4] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[3] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[2] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[1] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_0[0] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[15] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[14] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[13] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[12] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[11] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[10] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[9] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[8] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[7] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[6] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[5] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[4] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[3] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[2] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[1] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_1[0] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[15] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[14] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[13] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[12] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[11] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[10] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[9] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[8] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[7] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[6] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[5] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[4] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[3] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[2] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[1] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_2[0] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[15] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[14] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[13] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[12] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[11] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[10] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[9] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[8] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[7] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[6] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[5] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[4] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[3] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[2] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[1] = \<const0> ;
  assign pipe_debug_debug_out_ext_16_3[0] = \<const0> ;
  assign pipe_debug_inject_rx_status[7] = \<const0> ;
  assign pipe_debug_inject_rx_status[6] = \<const0> ;
  assign pipe_debug_inject_rx_status[5] = \<const0> ;
  assign pipe_debug_inject_rx_status[4] = \<const0> ;
  assign pipe_debug_inject_rx_status[3] = \<const0> ;
  assign pipe_debug_inject_rx_status[2] = \<const0> ;
  assign pipe_debug_inject_rx_status[1] = \<const0> ;
  assign pipe_debug_inject_rx_status[0] = \<const0> ;
  assign pipe_debug_inject_tx_status[7] = \<const0> ;
  assign pipe_debug_inject_tx_status[6] = \<const0> ;
  assign pipe_debug_inject_tx_status[5] = \<const0> ;
  assign pipe_debug_inject_tx_status[4] = \<const0> ;
  assign pipe_debug_inject_tx_status[3] = \<const0> ;
  assign pipe_debug_inject_tx_status[2] = \<const0> ;
  assign pipe_debug_inject_tx_status[1] = \<const0> ;
  assign pipe_debug_inject_tx_status[0] = \<const0> ;
  assign pipe_dmonitorout[29] = \<const0> ;
  assign pipe_dmonitorout[28] = \<const0> ;
  assign pipe_dmonitorout[27] = \<const0> ;
  assign pipe_dmonitorout[26] = \<const0> ;
  assign pipe_dmonitorout[25] = \<const0> ;
  assign pipe_dmonitorout[24] = \<const0> ;
  assign pipe_dmonitorout[23] = \<const0> ;
  assign pipe_dmonitorout[22] = \<const0> ;
  assign pipe_dmonitorout[21] = \<const0> ;
  assign pipe_dmonitorout[20] = \<const0> ;
  assign pipe_dmonitorout[19] = \<const0> ;
  assign pipe_dmonitorout[18] = \<const0> ;
  assign pipe_dmonitorout[17] = \<const0> ;
  assign pipe_dmonitorout[16] = \<const0> ;
  assign pipe_dmonitorout[15] = \<const0> ;
  assign pipe_dmonitorout[14] = \<const0> ;
  assign pipe_dmonitorout[13] = \<const0> ;
  assign pipe_dmonitorout[12] = \<const0> ;
  assign pipe_dmonitorout[11] = \<const0> ;
  assign pipe_dmonitorout[10] = \<const0> ;
  assign pipe_dmonitorout[9] = \<const0> ;
  assign pipe_dmonitorout[8] = \<const0> ;
  assign pipe_dmonitorout[7] = \<const0> ;
  assign pipe_dmonitorout[6] = \<const0> ;
  assign pipe_dmonitorout[5] = \<const0> ;
  assign pipe_dmonitorout[4] = \<const0> ;
  assign pipe_dmonitorout[3] = \<const0> ;
  assign pipe_dmonitorout[2] = \<const0> ;
  assign pipe_dmonitorout[1] = \<const0> ;
  assign pipe_dmonitorout[0] = \<const0> ;
  assign pipe_drp_fsm[13] = \<const0> ;
  assign pipe_drp_fsm[12] = \<const0> ;
  assign pipe_drp_fsm[11] = \<const0> ;
  assign pipe_drp_fsm[10] = \<const0> ;
  assign pipe_drp_fsm[9] = \<const0> ;
  assign pipe_drp_fsm[8] = \<const0> ;
  assign pipe_drp_fsm[7] = \<const0> ;
  assign pipe_drp_fsm[6] = \<const0> ;
  assign pipe_drp_fsm[5] = \<const0> ;
  assign pipe_drp_fsm[4] = \<const0> ;
  assign pipe_drp_fsm[3] = \<const0> ;
  assign pipe_drp_fsm[2] = \<const0> ;
  assign pipe_drp_fsm[1] = \<const0> ;
  assign pipe_drp_fsm[0] = \<const0> ;
  assign pipe_eyescandataerror[1] = \<const0> ;
  assign pipe_eyescandataerror[0] = \<const0> ;
  assign pipe_gen3_out = \<const0> ;
  assign pipe_pclk_sel_out[1] = \<const0> ;
  assign pipe_pclk_sel_out[0] = \<const0> ;
  assign pipe_qpll_lock[0] = \<const0> ;
  assign pipe_qrst_fsm[11] = \<const0> ;
  assign pipe_qrst_fsm[10] = \<const0> ;
  assign pipe_qrst_fsm[9] = \<const0> ;
  assign pipe_qrst_fsm[8] = \<const0> ;
  assign pipe_qrst_fsm[7] = \<const0> ;
  assign pipe_qrst_fsm[6] = \<const0> ;
  assign pipe_qrst_fsm[5] = \<const0> ;
  assign pipe_qrst_fsm[4] = \<const0> ;
  assign pipe_qrst_fsm[3] = \<const0> ;
  assign pipe_qrst_fsm[2] = \<const0> ;
  assign pipe_qrst_fsm[1] = \<const0> ;
  assign pipe_qrst_fsm[0] = \<const0> ;
  assign pipe_qrst_idle = \<const0> ;
  assign pipe_rate_fsm[9] = \<const0> ;
  assign pipe_rate_fsm[8] = \<const0> ;
  assign pipe_rate_fsm[7] = \<const0> ;
  assign pipe_rate_fsm[6] = \<const0> ;
  assign pipe_rate_fsm[5] = \<const0> ;
  assign pipe_rate_fsm[4] = \<const0> ;
  assign pipe_rate_fsm[3] = \<const0> ;
  assign pipe_rate_fsm[2] = \<const0> ;
  assign pipe_rate_fsm[1] = \<const0> ;
  assign pipe_rate_fsm[0] = \<const0> ;
  assign pipe_rate_idle = \<const0> ;
  assign pipe_rst_fsm[4] = \<const0> ;
  assign pipe_rst_fsm[3] = \<const0> ;
  assign pipe_rst_fsm[2] = \<const0> ;
  assign pipe_rst_fsm[1] = \<const0> ;
  assign pipe_rst_fsm[0] = \<const0> ;
  assign pipe_rst_idle = \<const0> ;
  assign pipe_rxbufstatus[5] = \<const0> ;
  assign pipe_rxbufstatus[4] = \<const0> ;
  assign pipe_rxbufstatus[3] = \<const0> ;
  assign pipe_rxbufstatus[2] = \<const0> ;
  assign pipe_rxbufstatus[1] = \<const0> ;
  assign pipe_rxbufstatus[0] = \<const0> ;
  assign pipe_rxcommadet[1] = \<const0> ;
  assign pipe_rxcommadet[0] = \<const0> ;
  assign pipe_rxdisperr[15] = \<const0> ;
  assign pipe_rxdisperr[14] = \<const0> ;
  assign pipe_rxdisperr[13] = \<const0> ;
  assign pipe_rxdisperr[12] = \<const0> ;
  assign pipe_rxdisperr[11] = \<const0> ;
  assign pipe_rxdisperr[10] = \<const0> ;
  assign pipe_rxdisperr[9] = \<const0> ;
  assign pipe_rxdisperr[8] = \<const0> ;
  assign pipe_rxdisperr[7] = \<const0> ;
  assign pipe_rxdisperr[6] = \<const0> ;
  assign pipe_rxdisperr[5] = \<const0> ;
  assign pipe_rxdisperr[4] = \<const0> ;
  assign pipe_rxdisperr[3] = \<const0> ;
  assign pipe_rxdisperr[2] = \<const0> ;
  assign pipe_rxdisperr[1] = \<const0> ;
  assign pipe_rxdisperr[0] = \<const0> ;
  assign pipe_rxdlysresetdone[1] = \<const0> ;
  assign pipe_rxdlysresetdone[0] = \<const0> ;
  assign pipe_rxnotintable[15] = \<const0> ;
  assign pipe_rxnotintable[14] = \<const0> ;
  assign pipe_rxnotintable[13] = \<const0> ;
  assign pipe_rxnotintable[12] = \<const0> ;
  assign pipe_rxnotintable[11] = \<const0> ;
  assign pipe_rxnotintable[10] = \<const0> ;
  assign pipe_rxnotintable[9] = \<const0> ;
  assign pipe_rxnotintable[8] = \<const0> ;
  assign pipe_rxnotintable[7] = \<const0> ;
  assign pipe_rxnotintable[6] = \<const0> ;
  assign pipe_rxnotintable[5] = \<const0> ;
  assign pipe_rxnotintable[4] = \<const0> ;
  assign pipe_rxnotintable[3] = \<const0> ;
  assign pipe_rxnotintable[2] = \<const0> ;
  assign pipe_rxnotintable[1] = \<const0> ;
  assign pipe_rxnotintable[0] = \<const0> ;
  assign pipe_rxoutclk_out[1] = \<const0> ;
  assign pipe_rxoutclk_out[0] = \<const0> ;
  assign pipe_rxphaligndone[1] = \<const0> ;
  assign pipe_rxphaligndone[0] = \<const0> ;
  assign pipe_rxpmaresetdone[1] = \<const0> ;
  assign pipe_rxpmaresetdone[0] = \<const0> ;
  assign pipe_rxprbserr[1] = \<const0> ;
  assign pipe_rxprbserr[0] = \<const0> ;
  assign pipe_rxstatus[5] = \<const0> ;
  assign pipe_rxstatus[4] = \<const0> ;
  assign pipe_rxstatus[3] = \<const0> ;
  assign pipe_rxstatus[2] = \<const0> ;
  assign pipe_rxstatus[1] = \<const0> ;
  assign pipe_rxstatus[0] = \<const0> ;
  assign pipe_rxsyncdone[1] = \<const0> ;
  assign pipe_rxsyncdone[0] = \<const0> ;
  assign pipe_sync_fsm_rx[13] = \<const0> ;
  assign pipe_sync_fsm_rx[12] = \<const0> ;
  assign pipe_sync_fsm_rx[11] = \<const0> ;
  assign pipe_sync_fsm_rx[10] = \<const0> ;
  assign pipe_sync_fsm_rx[9] = \<const0> ;
  assign pipe_sync_fsm_rx[8] = \<const0> ;
  assign pipe_sync_fsm_rx[7] = \<const0> ;
  assign pipe_sync_fsm_rx[6] = \<const0> ;
  assign pipe_sync_fsm_rx[5] = \<const0> ;
  assign pipe_sync_fsm_rx[4] = \<const0> ;
  assign pipe_sync_fsm_rx[3] = \<const0> ;
  assign pipe_sync_fsm_rx[2] = \<const0> ;
  assign pipe_sync_fsm_rx[1] = \<const0> ;
  assign pipe_sync_fsm_rx[0] = \<const0> ;
  assign pipe_sync_fsm_tx[11] = \<const0> ;
  assign pipe_sync_fsm_tx[10] = \<const0> ;
  assign pipe_sync_fsm_tx[9] = \<const0> ;
  assign pipe_sync_fsm_tx[8] = \<const0> ;
  assign pipe_sync_fsm_tx[7] = \<const0> ;
  assign pipe_sync_fsm_tx[6] = \<const0> ;
  assign pipe_sync_fsm_tx[5] = \<const0> ;
  assign pipe_sync_fsm_tx[4] = \<const0> ;
  assign pipe_sync_fsm_tx[3] = \<const0> ;
  assign pipe_sync_fsm_tx[2] = \<const0> ;
  assign pipe_sync_fsm_tx[1] = \<const0> ;
  assign pipe_sync_fsm_tx[0] = \<const0> ;
  assign pipe_tx0_powerdown[1] = \<const0> ;
  assign pipe_tx0_powerdown[0] = \<const0> ;
  assign pipe_tx0_rcvr_det = \<const0> ;
  assign pipe_tx_0_sigs[83] = \<const0> ;
  assign pipe_tx_0_sigs[82] = \<const0> ;
  assign pipe_tx_0_sigs[81] = \<const0> ;
  assign pipe_tx_0_sigs[80] = \<const0> ;
  assign pipe_tx_0_sigs[79] = \<const0> ;
  assign pipe_tx_0_sigs[78] = \<const0> ;
  assign pipe_tx_0_sigs[77] = \<const0> ;
  assign pipe_tx_0_sigs[76] = \<const0> ;
  assign pipe_tx_0_sigs[75] = \<const0> ;
  assign pipe_tx_0_sigs[74] = \<const0> ;
  assign pipe_tx_0_sigs[73] = \<const0> ;
  assign pipe_tx_0_sigs[72] = \<const0> ;
  assign pipe_tx_0_sigs[71] = \<const0> ;
  assign pipe_tx_0_sigs[70] = \<const0> ;
  assign pipe_tx_0_sigs[69] = \<const0> ;
  assign pipe_tx_0_sigs[68] = \<const0> ;
  assign pipe_tx_0_sigs[67] = \<const0> ;
  assign pipe_tx_0_sigs[66] = \<const0> ;
  assign pipe_tx_0_sigs[65] = \<const0> ;
  assign pipe_tx_0_sigs[64] = \<const0> ;
  assign pipe_tx_0_sigs[63] = \<const0> ;
  assign pipe_tx_0_sigs[62] = \<const0> ;
  assign pipe_tx_0_sigs[61] = \<const0> ;
  assign pipe_tx_0_sigs[60] = \<const0> ;
  assign pipe_tx_0_sigs[59] = \<const0> ;
  assign pipe_tx_0_sigs[58] = \<const0> ;
  assign pipe_tx_0_sigs[57] = \<const0> ;
  assign pipe_tx_0_sigs[56] = \<const0> ;
  assign pipe_tx_0_sigs[55] = \<const0> ;
  assign pipe_tx_0_sigs[54] = \<const0> ;
  assign pipe_tx_0_sigs[53] = \<const0> ;
  assign pipe_tx_0_sigs[52] = \<const0> ;
  assign pipe_tx_0_sigs[51] = \<const0> ;
  assign pipe_tx_0_sigs[50] = \<const0> ;
  assign pipe_tx_0_sigs[49] = \<const0> ;
  assign pipe_tx_0_sigs[48] = \<const0> ;
  assign pipe_tx_0_sigs[47] = \<const0> ;
  assign pipe_tx_0_sigs[46] = \<const0> ;
  assign pipe_tx_0_sigs[45] = \<const0> ;
  assign pipe_tx_0_sigs[44] = \<const0> ;
  assign pipe_tx_0_sigs[43] = \<const0> ;
  assign pipe_tx_0_sigs[42] = \<const0> ;
  assign pipe_tx_0_sigs[41] = \<const0> ;
  assign pipe_tx_0_sigs[40] = \<const0> ;
  assign pipe_tx_0_sigs[39] = \<const0> ;
  assign pipe_tx_0_sigs[38] = \<const0> ;
  assign pipe_tx_0_sigs[37] = \<const0> ;
  assign pipe_tx_0_sigs[36] = \<const0> ;
  assign pipe_tx_0_sigs[35] = \<const0> ;
  assign pipe_tx_0_sigs[34] = \<const0> ;
  assign pipe_tx_0_sigs[33] = \<const0> ;
  assign pipe_tx_0_sigs[32] = \<const0> ;
  assign pipe_tx_0_sigs[31] = \<const0> ;
  assign pipe_tx_0_sigs[30] = \<const0> ;
  assign pipe_tx_0_sigs[29] = \<const0> ;
  assign pipe_tx_0_sigs[28] = \<const0> ;
  assign pipe_tx_0_sigs[27] = \<const0> ;
  assign pipe_tx_0_sigs[26] = \<const0> ;
  assign pipe_tx_0_sigs[25] = \<const0> ;
  assign pipe_tx_0_sigs[24] = \<const0> ;
  assign pipe_tx_0_sigs[23] = \<const0> ;
  assign pipe_tx_0_sigs[22] = \<const0> ;
  assign pipe_tx_0_sigs[21] = \<const0> ;
  assign pipe_tx_0_sigs[20] = \<const0> ;
  assign pipe_tx_0_sigs[19] = \<const0> ;
  assign pipe_tx_0_sigs[18] = \<const0> ;
  assign pipe_tx_0_sigs[17] = \<const0> ;
  assign pipe_tx_0_sigs[16] = \<const0> ;
  assign pipe_tx_0_sigs[15] = \<const0> ;
  assign pipe_tx_0_sigs[14] = \<const0> ;
  assign pipe_tx_0_sigs[13] = \<const0> ;
  assign pipe_tx_0_sigs[12] = \<const0> ;
  assign pipe_tx_0_sigs[11] = \<const0> ;
  assign pipe_tx_0_sigs[10] = \<const0> ;
  assign pipe_tx_0_sigs[9] = \<const0> ;
  assign pipe_tx_0_sigs[8] = \<const0> ;
  assign pipe_tx_0_sigs[7] = \<const0> ;
  assign pipe_tx_0_sigs[6] = \<const0> ;
  assign pipe_tx_0_sigs[5] = \<const0> ;
  assign pipe_tx_0_sigs[4] = \<const0> ;
  assign pipe_tx_0_sigs[3] = \<const0> ;
  assign pipe_tx_0_sigs[2] = \<const0> ;
  assign pipe_tx_0_sigs[1] = \<const0> ;
  assign pipe_tx_0_sigs[0] = \<const0> ;
  assign pipe_tx_10_sigs[83] = \<const0> ;
  assign pipe_tx_10_sigs[82] = \<const0> ;
  assign pipe_tx_10_sigs[81] = \<const0> ;
  assign pipe_tx_10_sigs[80] = \<const0> ;
  assign pipe_tx_10_sigs[79] = \<const0> ;
  assign pipe_tx_10_sigs[78] = \<const0> ;
  assign pipe_tx_10_sigs[77] = \<const0> ;
  assign pipe_tx_10_sigs[76] = \<const0> ;
  assign pipe_tx_10_sigs[75] = \<const0> ;
  assign pipe_tx_10_sigs[74] = \<const0> ;
  assign pipe_tx_10_sigs[73] = \<const0> ;
  assign pipe_tx_10_sigs[72] = \<const0> ;
  assign pipe_tx_10_sigs[71] = \<const0> ;
  assign pipe_tx_10_sigs[70] = \<const0> ;
  assign pipe_tx_10_sigs[69] = \<const0> ;
  assign pipe_tx_10_sigs[68] = \<const0> ;
  assign pipe_tx_10_sigs[67] = \<const0> ;
  assign pipe_tx_10_sigs[66] = \<const0> ;
  assign pipe_tx_10_sigs[65] = \<const0> ;
  assign pipe_tx_10_sigs[64] = \<const0> ;
  assign pipe_tx_10_sigs[63] = \<const0> ;
  assign pipe_tx_10_sigs[62] = \<const0> ;
  assign pipe_tx_10_sigs[61] = \<const0> ;
  assign pipe_tx_10_sigs[60] = \<const0> ;
  assign pipe_tx_10_sigs[59] = \<const0> ;
  assign pipe_tx_10_sigs[58] = \<const0> ;
  assign pipe_tx_10_sigs[57] = \<const0> ;
  assign pipe_tx_10_sigs[56] = \<const0> ;
  assign pipe_tx_10_sigs[55] = \<const0> ;
  assign pipe_tx_10_sigs[54] = \<const0> ;
  assign pipe_tx_10_sigs[53] = \<const0> ;
  assign pipe_tx_10_sigs[52] = \<const0> ;
  assign pipe_tx_10_sigs[51] = \<const0> ;
  assign pipe_tx_10_sigs[50] = \<const0> ;
  assign pipe_tx_10_sigs[49] = \<const0> ;
  assign pipe_tx_10_sigs[48] = \<const0> ;
  assign pipe_tx_10_sigs[47] = \<const0> ;
  assign pipe_tx_10_sigs[46] = \<const0> ;
  assign pipe_tx_10_sigs[45] = \<const0> ;
  assign pipe_tx_10_sigs[44] = \<const0> ;
  assign pipe_tx_10_sigs[43] = \<const0> ;
  assign pipe_tx_10_sigs[42] = \<const0> ;
  assign pipe_tx_10_sigs[41] = \<const0> ;
  assign pipe_tx_10_sigs[40] = \<const0> ;
  assign pipe_tx_10_sigs[39] = \<const0> ;
  assign pipe_tx_10_sigs[38] = \<const0> ;
  assign pipe_tx_10_sigs[37] = \<const0> ;
  assign pipe_tx_10_sigs[36] = \<const0> ;
  assign pipe_tx_10_sigs[35] = \<const0> ;
  assign pipe_tx_10_sigs[34] = \<const0> ;
  assign pipe_tx_10_sigs[33] = \<const0> ;
  assign pipe_tx_10_sigs[32] = \<const0> ;
  assign pipe_tx_10_sigs[31] = \<const0> ;
  assign pipe_tx_10_sigs[30] = \<const0> ;
  assign pipe_tx_10_sigs[29] = \<const0> ;
  assign pipe_tx_10_sigs[28] = \<const0> ;
  assign pipe_tx_10_sigs[27] = \<const0> ;
  assign pipe_tx_10_sigs[26] = \<const0> ;
  assign pipe_tx_10_sigs[25] = \<const0> ;
  assign pipe_tx_10_sigs[24] = \<const0> ;
  assign pipe_tx_10_sigs[23] = \<const0> ;
  assign pipe_tx_10_sigs[22] = \<const0> ;
  assign pipe_tx_10_sigs[21] = \<const0> ;
  assign pipe_tx_10_sigs[20] = \<const0> ;
  assign pipe_tx_10_sigs[19] = \<const0> ;
  assign pipe_tx_10_sigs[18] = \<const0> ;
  assign pipe_tx_10_sigs[17] = \<const0> ;
  assign pipe_tx_10_sigs[16] = \<const0> ;
  assign pipe_tx_10_sigs[15] = \<const0> ;
  assign pipe_tx_10_sigs[14] = \<const0> ;
  assign pipe_tx_10_sigs[13] = \<const0> ;
  assign pipe_tx_10_sigs[12] = \<const0> ;
  assign pipe_tx_10_sigs[11] = \<const0> ;
  assign pipe_tx_10_sigs[10] = \<const0> ;
  assign pipe_tx_10_sigs[9] = \<const0> ;
  assign pipe_tx_10_sigs[8] = \<const0> ;
  assign pipe_tx_10_sigs[7] = \<const0> ;
  assign pipe_tx_10_sigs[6] = \<const0> ;
  assign pipe_tx_10_sigs[5] = \<const0> ;
  assign pipe_tx_10_sigs[4] = \<const0> ;
  assign pipe_tx_10_sigs[3] = \<const0> ;
  assign pipe_tx_10_sigs[2] = \<const0> ;
  assign pipe_tx_10_sigs[1] = \<const0> ;
  assign pipe_tx_10_sigs[0] = \<const0> ;
  assign pipe_tx_11_sigs[83] = \<const0> ;
  assign pipe_tx_11_sigs[82] = \<const0> ;
  assign pipe_tx_11_sigs[81] = \<const0> ;
  assign pipe_tx_11_sigs[80] = \<const0> ;
  assign pipe_tx_11_sigs[79] = \<const0> ;
  assign pipe_tx_11_sigs[78] = \<const0> ;
  assign pipe_tx_11_sigs[77] = \<const0> ;
  assign pipe_tx_11_sigs[76] = \<const0> ;
  assign pipe_tx_11_sigs[75] = \<const0> ;
  assign pipe_tx_11_sigs[74] = \<const0> ;
  assign pipe_tx_11_sigs[73] = \<const0> ;
  assign pipe_tx_11_sigs[72] = \<const0> ;
  assign pipe_tx_11_sigs[71] = \<const0> ;
  assign pipe_tx_11_sigs[70] = \<const0> ;
  assign pipe_tx_11_sigs[69] = \<const0> ;
  assign pipe_tx_11_sigs[68] = \<const0> ;
  assign pipe_tx_11_sigs[67] = \<const0> ;
  assign pipe_tx_11_sigs[66] = \<const0> ;
  assign pipe_tx_11_sigs[65] = \<const0> ;
  assign pipe_tx_11_sigs[64] = \<const0> ;
  assign pipe_tx_11_sigs[63] = \<const0> ;
  assign pipe_tx_11_sigs[62] = \<const0> ;
  assign pipe_tx_11_sigs[61] = \<const0> ;
  assign pipe_tx_11_sigs[60] = \<const0> ;
  assign pipe_tx_11_sigs[59] = \<const0> ;
  assign pipe_tx_11_sigs[58] = \<const0> ;
  assign pipe_tx_11_sigs[57] = \<const0> ;
  assign pipe_tx_11_sigs[56] = \<const0> ;
  assign pipe_tx_11_sigs[55] = \<const0> ;
  assign pipe_tx_11_sigs[54] = \<const0> ;
  assign pipe_tx_11_sigs[53] = \<const0> ;
  assign pipe_tx_11_sigs[52] = \<const0> ;
  assign pipe_tx_11_sigs[51] = \<const0> ;
  assign pipe_tx_11_sigs[50] = \<const0> ;
  assign pipe_tx_11_sigs[49] = \<const0> ;
  assign pipe_tx_11_sigs[48] = \<const0> ;
  assign pipe_tx_11_sigs[47] = \<const0> ;
  assign pipe_tx_11_sigs[46] = \<const0> ;
  assign pipe_tx_11_sigs[45] = \<const0> ;
  assign pipe_tx_11_sigs[44] = \<const0> ;
  assign pipe_tx_11_sigs[43] = \<const0> ;
  assign pipe_tx_11_sigs[42] = \<const0> ;
  assign pipe_tx_11_sigs[41] = \<const0> ;
  assign pipe_tx_11_sigs[40] = \<const0> ;
  assign pipe_tx_11_sigs[39] = \<const0> ;
  assign pipe_tx_11_sigs[38] = \<const0> ;
  assign pipe_tx_11_sigs[37] = \<const0> ;
  assign pipe_tx_11_sigs[36] = \<const0> ;
  assign pipe_tx_11_sigs[35] = \<const0> ;
  assign pipe_tx_11_sigs[34] = \<const0> ;
  assign pipe_tx_11_sigs[33] = \<const0> ;
  assign pipe_tx_11_sigs[32] = \<const0> ;
  assign pipe_tx_11_sigs[31] = \<const0> ;
  assign pipe_tx_11_sigs[30] = \<const0> ;
  assign pipe_tx_11_sigs[29] = \<const0> ;
  assign pipe_tx_11_sigs[28] = \<const0> ;
  assign pipe_tx_11_sigs[27] = \<const0> ;
  assign pipe_tx_11_sigs[26] = \<const0> ;
  assign pipe_tx_11_sigs[25] = \<const0> ;
  assign pipe_tx_11_sigs[24] = \<const0> ;
  assign pipe_tx_11_sigs[23] = \<const0> ;
  assign pipe_tx_11_sigs[22] = \<const0> ;
  assign pipe_tx_11_sigs[21] = \<const0> ;
  assign pipe_tx_11_sigs[20] = \<const0> ;
  assign pipe_tx_11_sigs[19] = \<const0> ;
  assign pipe_tx_11_sigs[18] = \<const0> ;
  assign pipe_tx_11_sigs[17] = \<const0> ;
  assign pipe_tx_11_sigs[16] = \<const0> ;
  assign pipe_tx_11_sigs[15] = \<const0> ;
  assign pipe_tx_11_sigs[14] = \<const0> ;
  assign pipe_tx_11_sigs[13] = \<const0> ;
  assign pipe_tx_11_sigs[12] = \<const0> ;
  assign pipe_tx_11_sigs[11] = \<const0> ;
  assign pipe_tx_11_sigs[10] = \<const0> ;
  assign pipe_tx_11_sigs[9] = \<const0> ;
  assign pipe_tx_11_sigs[8] = \<const0> ;
  assign pipe_tx_11_sigs[7] = \<const0> ;
  assign pipe_tx_11_sigs[6] = \<const0> ;
  assign pipe_tx_11_sigs[5] = \<const0> ;
  assign pipe_tx_11_sigs[4] = \<const0> ;
  assign pipe_tx_11_sigs[3] = \<const0> ;
  assign pipe_tx_11_sigs[2] = \<const0> ;
  assign pipe_tx_11_sigs[1] = \<const0> ;
  assign pipe_tx_11_sigs[0] = \<const0> ;
  assign pipe_tx_12_sigs[83] = \<const0> ;
  assign pipe_tx_12_sigs[82] = \<const0> ;
  assign pipe_tx_12_sigs[81] = \<const0> ;
  assign pipe_tx_12_sigs[80] = \<const0> ;
  assign pipe_tx_12_sigs[79] = \<const0> ;
  assign pipe_tx_12_sigs[78] = \<const0> ;
  assign pipe_tx_12_sigs[77] = \<const0> ;
  assign pipe_tx_12_sigs[76] = \<const0> ;
  assign pipe_tx_12_sigs[75] = \<const0> ;
  assign pipe_tx_12_sigs[74] = \<const0> ;
  assign pipe_tx_12_sigs[73] = \<const0> ;
  assign pipe_tx_12_sigs[72] = \<const0> ;
  assign pipe_tx_12_sigs[71] = \<const0> ;
  assign pipe_tx_12_sigs[70] = \<const0> ;
  assign pipe_tx_12_sigs[69] = \<const0> ;
  assign pipe_tx_12_sigs[68] = \<const0> ;
  assign pipe_tx_12_sigs[67] = \<const0> ;
  assign pipe_tx_12_sigs[66] = \<const0> ;
  assign pipe_tx_12_sigs[65] = \<const0> ;
  assign pipe_tx_12_sigs[64] = \<const0> ;
  assign pipe_tx_12_sigs[63] = \<const0> ;
  assign pipe_tx_12_sigs[62] = \<const0> ;
  assign pipe_tx_12_sigs[61] = \<const0> ;
  assign pipe_tx_12_sigs[60] = \<const0> ;
  assign pipe_tx_12_sigs[59] = \<const0> ;
  assign pipe_tx_12_sigs[58] = \<const0> ;
  assign pipe_tx_12_sigs[57] = \<const0> ;
  assign pipe_tx_12_sigs[56] = \<const0> ;
  assign pipe_tx_12_sigs[55] = \<const0> ;
  assign pipe_tx_12_sigs[54] = \<const0> ;
  assign pipe_tx_12_sigs[53] = \<const0> ;
  assign pipe_tx_12_sigs[52] = \<const0> ;
  assign pipe_tx_12_sigs[51] = \<const0> ;
  assign pipe_tx_12_sigs[50] = \<const0> ;
  assign pipe_tx_12_sigs[49] = \<const0> ;
  assign pipe_tx_12_sigs[48] = \<const0> ;
  assign pipe_tx_12_sigs[47] = \<const0> ;
  assign pipe_tx_12_sigs[46] = \<const0> ;
  assign pipe_tx_12_sigs[45] = \<const0> ;
  assign pipe_tx_12_sigs[44] = \<const0> ;
  assign pipe_tx_12_sigs[43] = \<const0> ;
  assign pipe_tx_12_sigs[42] = \<const0> ;
  assign pipe_tx_12_sigs[41] = \<const0> ;
  assign pipe_tx_12_sigs[40] = \<const0> ;
  assign pipe_tx_12_sigs[39] = \<const0> ;
  assign pipe_tx_12_sigs[38] = \<const0> ;
  assign pipe_tx_12_sigs[37] = \<const0> ;
  assign pipe_tx_12_sigs[36] = \<const0> ;
  assign pipe_tx_12_sigs[35] = \<const0> ;
  assign pipe_tx_12_sigs[34] = \<const0> ;
  assign pipe_tx_12_sigs[33] = \<const0> ;
  assign pipe_tx_12_sigs[32] = \<const0> ;
  assign pipe_tx_12_sigs[31] = \<const0> ;
  assign pipe_tx_12_sigs[30] = \<const0> ;
  assign pipe_tx_12_sigs[29] = \<const0> ;
  assign pipe_tx_12_sigs[28] = \<const0> ;
  assign pipe_tx_12_sigs[27] = \<const0> ;
  assign pipe_tx_12_sigs[26] = \<const0> ;
  assign pipe_tx_12_sigs[25] = \<const0> ;
  assign pipe_tx_12_sigs[24] = \<const0> ;
  assign pipe_tx_12_sigs[23] = \<const0> ;
  assign pipe_tx_12_sigs[22] = \<const0> ;
  assign pipe_tx_12_sigs[21] = \<const0> ;
  assign pipe_tx_12_sigs[20] = \<const0> ;
  assign pipe_tx_12_sigs[19] = \<const0> ;
  assign pipe_tx_12_sigs[18] = \<const0> ;
  assign pipe_tx_12_sigs[17] = \<const0> ;
  assign pipe_tx_12_sigs[16] = \<const0> ;
  assign pipe_tx_12_sigs[15] = \<const0> ;
  assign pipe_tx_12_sigs[14] = \<const0> ;
  assign pipe_tx_12_sigs[13] = \<const0> ;
  assign pipe_tx_12_sigs[12] = \<const0> ;
  assign pipe_tx_12_sigs[11] = \<const0> ;
  assign pipe_tx_12_sigs[10] = \<const0> ;
  assign pipe_tx_12_sigs[9] = \<const0> ;
  assign pipe_tx_12_sigs[8] = \<const0> ;
  assign pipe_tx_12_sigs[7] = \<const0> ;
  assign pipe_tx_12_sigs[6] = \<const0> ;
  assign pipe_tx_12_sigs[5] = \<const0> ;
  assign pipe_tx_12_sigs[4] = \<const0> ;
  assign pipe_tx_12_sigs[3] = \<const0> ;
  assign pipe_tx_12_sigs[2] = \<const0> ;
  assign pipe_tx_12_sigs[1] = \<const0> ;
  assign pipe_tx_12_sigs[0] = \<const0> ;
  assign pipe_tx_13_sigs[83] = \<const0> ;
  assign pipe_tx_13_sigs[82] = \<const0> ;
  assign pipe_tx_13_sigs[81] = \<const0> ;
  assign pipe_tx_13_sigs[80] = \<const0> ;
  assign pipe_tx_13_sigs[79] = \<const0> ;
  assign pipe_tx_13_sigs[78] = \<const0> ;
  assign pipe_tx_13_sigs[77] = \<const0> ;
  assign pipe_tx_13_sigs[76] = \<const0> ;
  assign pipe_tx_13_sigs[75] = \<const0> ;
  assign pipe_tx_13_sigs[74] = \<const0> ;
  assign pipe_tx_13_sigs[73] = \<const0> ;
  assign pipe_tx_13_sigs[72] = \<const0> ;
  assign pipe_tx_13_sigs[71] = \<const0> ;
  assign pipe_tx_13_sigs[70] = \<const0> ;
  assign pipe_tx_13_sigs[69] = \<const0> ;
  assign pipe_tx_13_sigs[68] = \<const0> ;
  assign pipe_tx_13_sigs[67] = \<const0> ;
  assign pipe_tx_13_sigs[66] = \<const0> ;
  assign pipe_tx_13_sigs[65] = \<const0> ;
  assign pipe_tx_13_sigs[64] = \<const0> ;
  assign pipe_tx_13_sigs[63] = \<const0> ;
  assign pipe_tx_13_sigs[62] = \<const0> ;
  assign pipe_tx_13_sigs[61] = \<const0> ;
  assign pipe_tx_13_sigs[60] = \<const0> ;
  assign pipe_tx_13_sigs[59] = \<const0> ;
  assign pipe_tx_13_sigs[58] = \<const0> ;
  assign pipe_tx_13_sigs[57] = \<const0> ;
  assign pipe_tx_13_sigs[56] = \<const0> ;
  assign pipe_tx_13_sigs[55] = \<const0> ;
  assign pipe_tx_13_sigs[54] = \<const0> ;
  assign pipe_tx_13_sigs[53] = \<const0> ;
  assign pipe_tx_13_sigs[52] = \<const0> ;
  assign pipe_tx_13_sigs[51] = \<const0> ;
  assign pipe_tx_13_sigs[50] = \<const0> ;
  assign pipe_tx_13_sigs[49] = \<const0> ;
  assign pipe_tx_13_sigs[48] = \<const0> ;
  assign pipe_tx_13_sigs[47] = \<const0> ;
  assign pipe_tx_13_sigs[46] = \<const0> ;
  assign pipe_tx_13_sigs[45] = \<const0> ;
  assign pipe_tx_13_sigs[44] = \<const0> ;
  assign pipe_tx_13_sigs[43] = \<const0> ;
  assign pipe_tx_13_sigs[42] = \<const0> ;
  assign pipe_tx_13_sigs[41] = \<const0> ;
  assign pipe_tx_13_sigs[40] = \<const0> ;
  assign pipe_tx_13_sigs[39] = \<const0> ;
  assign pipe_tx_13_sigs[38] = \<const0> ;
  assign pipe_tx_13_sigs[37] = \<const0> ;
  assign pipe_tx_13_sigs[36] = \<const0> ;
  assign pipe_tx_13_sigs[35] = \<const0> ;
  assign pipe_tx_13_sigs[34] = \<const0> ;
  assign pipe_tx_13_sigs[33] = \<const0> ;
  assign pipe_tx_13_sigs[32] = \<const0> ;
  assign pipe_tx_13_sigs[31] = \<const0> ;
  assign pipe_tx_13_sigs[30] = \<const0> ;
  assign pipe_tx_13_sigs[29] = \<const0> ;
  assign pipe_tx_13_sigs[28] = \<const0> ;
  assign pipe_tx_13_sigs[27] = \<const0> ;
  assign pipe_tx_13_sigs[26] = \<const0> ;
  assign pipe_tx_13_sigs[25] = \<const0> ;
  assign pipe_tx_13_sigs[24] = \<const0> ;
  assign pipe_tx_13_sigs[23] = \<const0> ;
  assign pipe_tx_13_sigs[22] = \<const0> ;
  assign pipe_tx_13_sigs[21] = \<const0> ;
  assign pipe_tx_13_sigs[20] = \<const0> ;
  assign pipe_tx_13_sigs[19] = \<const0> ;
  assign pipe_tx_13_sigs[18] = \<const0> ;
  assign pipe_tx_13_sigs[17] = \<const0> ;
  assign pipe_tx_13_sigs[16] = \<const0> ;
  assign pipe_tx_13_sigs[15] = \<const0> ;
  assign pipe_tx_13_sigs[14] = \<const0> ;
  assign pipe_tx_13_sigs[13] = \<const0> ;
  assign pipe_tx_13_sigs[12] = \<const0> ;
  assign pipe_tx_13_sigs[11] = \<const0> ;
  assign pipe_tx_13_sigs[10] = \<const0> ;
  assign pipe_tx_13_sigs[9] = \<const0> ;
  assign pipe_tx_13_sigs[8] = \<const0> ;
  assign pipe_tx_13_sigs[7] = \<const0> ;
  assign pipe_tx_13_sigs[6] = \<const0> ;
  assign pipe_tx_13_sigs[5] = \<const0> ;
  assign pipe_tx_13_sigs[4] = \<const0> ;
  assign pipe_tx_13_sigs[3] = \<const0> ;
  assign pipe_tx_13_sigs[2] = \<const0> ;
  assign pipe_tx_13_sigs[1] = \<const0> ;
  assign pipe_tx_13_sigs[0] = \<const0> ;
  assign pipe_tx_14_sigs[83] = \<const0> ;
  assign pipe_tx_14_sigs[82] = \<const0> ;
  assign pipe_tx_14_sigs[81] = \<const0> ;
  assign pipe_tx_14_sigs[80] = \<const0> ;
  assign pipe_tx_14_sigs[79] = \<const0> ;
  assign pipe_tx_14_sigs[78] = \<const0> ;
  assign pipe_tx_14_sigs[77] = \<const0> ;
  assign pipe_tx_14_sigs[76] = \<const0> ;
  assign pipe_tx_14_sigs[75] = \<const0> ;
  assign pipe_tx_14_sigs[74] = \<const0> ;
  assign pipe_tx_14_sigs[73] = \<const0> ;
  assign pipe_tx_14_sigs[72] = \<const0> ;
  assign pipe_tx_14_sigs[71] = \<const0> ;
  assign pipe_tx_14_sigs[70] = \<const0> ;
  assign pipe_tx_14_sigs[69] = \<const0> ;
  assign pipe_tx_14_sigs[68] = \<const0> ;
  assign pipe_tx_14_sigs[67] = \<const0> ;
  assign pipe_tx_14_sigs[66] = \<const0> ;
  assign pipe_tx_14_sigs[65] = \<const0> ;
  assign pipe_tx_14_sigs[64] = \<const0> ;
  assign pipe_tx_14_sigs[63] = \<const0> ;
  assign pipe_tx_14_sigs[62] = \<const0> ;
  assign pipe_tx_14_sigs[61] = \<const0> ;
  assign pipe_tx_14_sigs[60] = \<const0> ;
  assign pipe_tx_14_sigs[59] = \<const0> ;
  assign pipe_tx_14_sigs[58] = \<const0> ;
  assign pipe_tx_14_sigs[57] = \<const0> ;
  assign pipe_tx_14_sigs[56] = \<const0> ;
  assign pipe_tx_14_sigs[55] = \<const0> ;
  assign pipe_tx_14_sigs[54] = \<const0> ;
  assign pipe_tx_14_sigs[53] = \<const0> ;
  assign pipe_tx_14_sigs[52] = \<const0> ;
  assign pipe_tx_14_sigs[51] = \<const0> ;
  assign pipe_tx_14_sigs[50] = \<const0> ;
  assign pipe_tx_14_sigs[49] = \<const0> ;
  assign pipe_tx_14_sigs[48] = \<const0> ;
  assign pipe_tx_14_sigs[47] = \<const0> ;
  assign pipe_tx_14_sigs[46] = \<const0> ;
  assign pipe_tx_14_sigs[45] = \<const0> ;
  assign pipe_tx_14_sigs[44] = \<const0> ;
  assign pipe_tx_14_sigs[43] = \<const0> ;
  assign pipe_tx_14_sigs[42] = \<const0> ;
  assign pipe_tx_14_sigs[41] = \<const0> ;
  assign pipe_tx_14_sigs[40] = \<const0> ;
  assign pipe_tx_14_sigs[39] = \<const0> ;
  assign pipe_tx_14_sigs[38] = \<const0> ;
  assign pipe_tx_14_sigs[37] = \<const0> ;
  assign pipe_tx_14_sigs[36] = \<const0> ;
  assign pipe_tx_14_sigs[35] = \<const0> ;
  assign pipe_tx_14_sigs[34] = \<const0> ;
  assign pipe_tx_14_sigs[33] = \<const0> ;
  assign pipe_tx_14_sigs[32] = \<const0> ;
  assign pipe_tx_14_sigs[31] = \<const0> ;
  assign pipe_tx_14_sigs[30] = \<const0> ;
  assign pipe_tx_14_sigs[29] = \<const0> ;
  assign pipe_tx_14_sigs[28] = \<const0> ;
  assign pipe_tx_14_sigs[27] = \<const0> ;
  assign pipe_tx_14_sigs[26] = \<const0> ;
  assign pipe_tx_14_sigs[25] = \<const0> ;
  assign pipe_tx_14_sigs[24] = \<const0> ;
  assign pipe_tx_14_sigs[23] = \<const0> ;
  assign pipe_tx_14_sigs[22] = \<const0> ;
  assign pipe_tx_14_sigs[21] = \<const0> ;
  assign pipe_tx_14_sigs[20] = \<const0> ;
  assign pipe_tx_14_sigs[19] = \<const0> ;
  assign pipe_tx_14_sigs[18] = \<const0> ;
  assign pipe_tx_14_sigs[17] = \<const0> ;
  assign pipe_tx_14_sigs[16] = \<const0> ;
  assign pipe_tx_14_sigs[15] = \<const0> ;
  assign pipe_tx_14_sigs[14] = \<const0> ;
  assign pipe_tx_14_sigs[13] = \<const0> ;
  assign pipe_tx_14_sigs[12] = \<const0> ;
  assign pipe_tx_14_sigs[11] = \<const0> ;
  assign pipe_tx_14_sigs[10] = \<const0> ;
  assign pipe_tx_14_sigs[9] = \<const0> ;
  assign pipe_tx_14_sigs[8] = \<const0> ;
  assign pipe_tx_14_sigs[7] = \<const0> ;
  assign pipe_tx_14_sigs[6] = \<const0> ;
  assign pipe_tx_14_sigs[5] = \<const0> ;
  assign pipe_tx_14_sigs[4] = \<const0> ;
  assign pipe_tx_14_sigs[3] = \<const0> ;
  assign pipe_tx_14_sigs[2] = \<const0> ;
  assign pipe_tx_14_sigs[1] = \<const0> ;
  assign pipe_tx_14_sigs[0] = \<const0> ;
  assign pipe_tx_15_sigs[83] = \<const0> ;
  assign pipe_tx_15_sigs[82] = \<const0> ;
  assign pipe_tx_15_sigs[81] = \<const0> ;
  assign pipe_tx_15_sigs[80] = \<const0> ;
  assign pipe_tx_15_sigs[79] = \<const0> ;
  assign pipe_tx_15_sigs[78] = \<const0> ;
  assign pipe_tx_15_sigs[77] = \<const0> ;
  assign pipe_tx_15_sigs[76] = \<const0> ;
  assign pipe_tx_15_sigs[75] = \<const0> ;
  assign pipe_tx_15_sigs[74] = \<const0> ;
  assign pipe_tx_15_sigs[73] = \<const0> ;
  assign pipe_tx_15_sigs[72] = \<const0> ;
  assign pipe_tx_15_sigs[71] = \<const0> ;
  assign pipe_tx_15_sigs[70] = \<const0> ;
  assign pipe_tx_15_sigs[69] = \<const0> ;
  assign pipe_tx_15_sigs[68] = \<const0> ;
  assign pipe_tx_15_sigs[67] = \<const0> ;
  assign pipe_tx_15_sigs[66] = \<const0> ;
  assign pipe_tx_15_sigs[65] = \<const0> ;
  assign pipe_tx_15_sigs[64] = \<const0> ;
  assign pipe_tx_15_sigs[63] = \<const0> ;
  assign pipe_tx_15_sigs[62] = \<const0> ;
  assign pipe_tx_15_sigs[61] = \<const0> ;
  assign pipe_tx_15_sigs[60] = \<const0> ;
  assign pipe_tx_15_sigs[59] = \<const0> ;
  assign pipe_tx_15_sigs[58] = \<const0> ;
  assign pipe_tx_15_sigs[57] = \<const0> ;
  assign pipe_tx_15_sigs[56] = \<const0> ;
  assign pipe_tx_15_sigs[55] = \<const0> ;
  assign pipe_tx_15_sigs[54] = \<const0> ;
  assign pipe_tx_15_sigs[53] = \<const0> ;
  assign pipe_tx_15_sigs[52] = \<const0> ;
  assign pipe_tx_15_sigs[51] = \<const0> ;
  assign pipe_tx_15_sigs[50] = \<const0> ;
  assign pipe_tx_15_sigs[49] = \<const0> ;
  assign pipe_tx_15_sigs[48] = \<const0> ;
  assign pipe_tx_15_sigs[47] = \<const0> ;
  assign pipe_tx_15_sigs[46] = \<const0> ;
  assign pipe_tx_15_sigs[45] = \<const0> ;
  assign pipe_tx_15_sigs[44] = \<const0> ;
  assign pipe_tx_15_sigs[43] = \<const0> ;
  assign pipe_tx_15_sigs[42] = \<const0> ;
  assign pipe_tx_15_sigs[41] = \<const0> ;
  assign pipe_tx_15_sigs[40] = \<const0> ;
  assign pipe_tx_15_sigs[39] = \<const0> ;
  assign pipe_tx_15_sigs[38] = \<const0> ;
  assign pipe_tx_15_sigs[37] = \<const0> ;
  assign pipe_tx_15_sigs[36] = \<const0> ;
  assign pipe_tx_15_sigs[35] = \<const0> ;
  assign pipe_tx_15_sigs[34] = \<const0> ;
  assign pipe_tx_15_sigs[33] = \<const0> ;
  assign pipe_tx_15_sigs[32] = \<const0> ;
  assign pipe_tx_15_sigs[31] = \<const0> ;
  assign pipe_tx_15_sigs[30] = \<const0> ;
  assign pipe_tx_15_sigs[29] = \<const0> ;
  assign pipe_tx_15_sigs[28] = \<const0> ;
  assign pipe_tx_15_sigs[27] = \<const0> ;
  assign pipe_tx_15_sigs[26] = \<const0> ;
  assign pipe_tx_15_sigs[25] = \<const0> ;
  assign pipe_tx_15_sigs[24] = \<const0> ;
  assign pipe_tx_15_sigs[23] = \<const0> ;
  assign pipe_tx_15_sigs[22] = \<const0> ;
  assign pipe_tx_15_sigs[21] = \<const0> ;
  assign pipe_tx_15_sigs[20] = \<const0> ;
  assign pipe_tx_15_sigs[19] = \<const0> ;
  assign pipe_tx_15_sigs[18] = \<const0> ;
  assign pipe_tx_15_sigs[17] = \<const0> ;
  assign pipe_tx_15_sigs[16] = \<const0> ;
  assign pipe_tx_15_sigs[15] = \<const0> ;
  assign pipe_tx_15_sigs[14] = \<const0> ;
  assign pipe_tx_15_sigs[13] = \<const0> ;
  assign pipe_tx_15_sigs[12] = \<const0> ;
  assign pipe_tx_15_sigs[11] = \<const0> ;
  assign pipe_tx_15_sigs[10] = \<const0> ;
  assign pipe_tx_15_sigs[9] = \<const0> ;
  assign pipe_tx_15_sigs[8] = \<const0> ;
  assign pipe_tx_15_sigs[7] = \<const0> ;
  assign pipe_tx_15_sigs[6] = \<const0> ;
  assign pipe_tx_15_sigs[5] = \<const0> ;
  assign pipe_tx_15_sigs[4] = \<const0> ;
  assign pipe_tx_15_sigs[3] = \<const0> ;
  assign pipe_tx_15_sigs[2] = \<const0> ;
  assign pipe_tx_15_sigs[1] = \<const0> ;
  assign pipe_tx_15_sigs[0] = \<const0> ;
  assign pipe_tx_1_sigs[83] = \<const0> ;
  assign pipe_tx_1_sigs[82] = \<const0> ;
  assign pipe_tx_1_sigs[81] = \<const0> ;
  assign pipe_tx_1_sigs[80] = \<const0> ;
  assign pipe_tx_1_sigs[79] = \<const0> ;
  assign pipe_tx_1_sigs[78] = \<const0> ;
  assign pipe_tx_1_sigs[77] = \<const0> ;
  assign pipe_tx_1_sigs[76] = \<const0> ;
  assign pipe_tx_1_sigs[75] = \<const0> ;
  assign pipe_tx_1_sigs[74] = \<const0> ;
  assign pipe_tx_1_sigs[73] = \<const0> ;
  assign pipe_tx_1_sigs[72] = \<const0> ;
  assign pipe_tx_1_sigs[71] = \<const0> ;
  assign pipe_tx_1_sigs[70] = \<const0> ;
  assign pipe_tx_1_sigs[69] = \<const0> ;
  assign pipe_tx_1_sigs[68] = \<const0> ;
  assign pipe_tx_1_sigs[67] = \<const0> ;
  assign pipe_tx_1_sigs[66] = \<const0> ;
  assign pipe_tx_1_sigs[65] = \<const0> ;
  assign pipe_tx_1_sigs[64] = \<const0> ;
  assign pipe_tx_1_sigs[63] = \<const0> ;
  assign pipe_tx_1_sigs[62] = \<const0> ;
  assign pipe_tx_1_sigs[61] = \<const0> ;
  assign pipe_tx_1_sigs[60] = \<const0> ;
  assign pipe_tx_1_sigs[59] = \<const0> ;
  assign pipe_tx_1_sigs[58] = \<const0> ;
  assign pipe_tx_1_sigs[57] = \<const0> ;
  assign pipe_tx_1_sigs[56] = \<const0> ;
  assign pipe_tx_1_sigs[55] = \<const0> ;
  assign pipe_tx_1_sigs[54] = \<const0> ;
  assign pipe_tx_1_sigs[53] = \<const0> ;
  assign pipe_tx_1_sigs[52] = \<const0> ;
  assign pipe_tx_1_sigs[51] = \<const0> ;
  assign pipe_tx_1_sigs[50] = \<const0> ;
  assign pipe_tx_1_sigs[49] = \<const0> ;
  assign pipe_tx_1_sigs[48] = \<const0> ;
  assign pipe_tx_1_sigs[47] = \<const0> ;
  assign pipe_tx_1_sigs[46] = \<const0> ;
  assign pipe_tx_1_sigs[45] = \<const0> ;
  assign pipe_tx_1_sigs[44] = \<const0> ;
  assign pipe_tx_1_sigs[43] = \<const0> ;
  assign pipe_tx_1_sigs[42] = \<const0> ;
  assign pipe_tx_1_sigs[41] = \<const0> ;
  assign pipe_tx_1_sigs[40] = \<const0> ;
  assign pipe_tx_1_sigs[39] = \<const0> ;
  assign pipe_tx_1_sigs[38] = \<const0> ;
  assign pipe_tx_1_sigs[37] = \<const0> ;
  assign pipe_tx_1_sigs[36] = \<const0> ;
  assign pipe_tx_1_sigs[35] = \<const0> ;
  assign pipe_tx_1_sigs[34] = \<const0> ;
  assign pipe_tx_1_sigs[33] = \<const0> ;
  assign pipe_tx_1_sigs[32] = \<const0> ;
  assign pipe_tx_1_sigs[31] = \<const0> ;
  assign pipe_tx_1_sigs[30] = \<const0> ;
  assign pipe_tx_1_sigs[29] = \<const0> ;
  assign pipe_tx_1_sigs[28] = \<const0> ;
  assign pipe_tx_1_sigs[27] = \<const0> ;
  assign pipe_tx_1_sigs[26] = \<const0> ;
  assign pipe_tx_1_sigs[25] = \<const0> ;
  assign pipe_tx_1_sigs[24] = \<const0> ;
  assign pipe_tx_1_sigs[23] = \<const0> ;
  assign pipe_tx_1_sigs[22] = \<const0> ;
  assign pipe_tx_1_sigs[21] = \<const0> ;
  assign pipe_tx_1_sigs[20] = \<const0> ;
  assign pipe_tx_1_sigs[19] = \<const0> ;
  assign pipe_tx_1_sigs[18] = \<const0> ;
  assign pipe_tx_1_sigs[17] = \<const0> ;
  assign pipe_tx_1_sigs[16] = \<const0> ;
  assign pipe_tx_1_sigs[15] = \<const0> ;
  assign pipe_tx_1_sigs[14] = \<const0> ;
  assign pipe_tx_1_sigs[13] = \<const0> ;
  assign pipe_tx_1_sigs[12] = \<const0> ;
  assign pipe_tx_1_sigs[11] = \<const0> ;
  assign pipe_tx_1_sigs[10] = \<const0> ;
  assign pipe_tx_1_sigs[9] = \<const0> ;
  assign pipe_tx_1_sigs[8] = \<const0> ;
  assign pipe_tx_1_sigs[7] = \<const0> ;
  assign pipe_tx_1_sigs[6] = \<const0> ;
  assign pipe_tx_1_sigs[5] = \<const0> ;
  assign pipe_tx_1_sigs[4] = \<const0> ;
  assign pipe_tx_1_sigs[3] = \<const0> ;
  assign pipe_tx_1_sigs[2] = \<const0> ;
  assign pipe_tx_1_sigs[1] = \<const0> ;
  assign pipe_tx_1_sigs[0] = \<const0> ;
  assign pipe_tx_2_sigs[83] = \<const0> ;
  assign pipe_tx_2_sigs[82] = \<const0> ;
  assign pipe_tx_2_sigs[81] = \<const0> ;
  assign pipe_tx_2_sigs[80] = \<const0> ;
  assign pipe_tx_2_sigs[79] = \<const0> ;
  assign pipe_tx_2_sigs[78] = \<const0> ;
  assign pipe_tx_2_sigs[77] = \<const0> ;
  assign pipe_tx_2_sigs[76] = \<const0> ;
  assign pipe_tx_2_sigs[75] = \<const0> ;
  assign pipe_tx_2_sigs[74] = \<const0> ;
  assign pipe_tx_2_sigs[73] = \<const0> ;
  assign pipe_tx_2_sigs[72] = \<const0> ;
  assign pipe_tx_2_sigs[71] = \<const0> ;
  assign pipe_tx_2_sigs[70] = \<const0> ;
  assign pipe_tx_2_sigs[69] = \<const0> ;
  assign pipe_tx_2_sigs[68] = \<const0> ;
  assign pipe_tx_2_sigs[67] = \<const0> ;
  assign pipe_tx_2_sigs[66] = \<const0> ;
  assign pipe_tx_2_sigs[65] = \<const0> ;
  assign pipe_tx_2_sigs[64] = \<const0> ;
  assign pipe_tx_2_sigs[63] = \<const0> ;
  assign pipe_tx_2_sigs[62] = \<const0> ;
  assign pipe_tx_2_sigs[61] = \<const0> ;
  assign pipe_tx_2_sigs[60] = \<const0> ;
  assign pipe_tx_2_sigs[59] = \<const0> ;
  assign pipe_tx_2_sigs[58] = \<const0> ;
  assign pipe_tx_2_sigs[57] = \<const0> ;
  assign pipe_tx_2_sigs[56] = \<const0> ;
  assign pipe_tx_2_sigs[55] = \<const0> ;
  assign pipe_tx_2_sigs[54] = \<const0> ;
  assign pipe_tx_2_sigs[53] = \<const0> ;
  assign pipe_tx_2_sigs[52] = \<const0> ;
  assign pipe_tx_2_sigs[51] = \<const0> ;
  assign pipe_tx_2_sigs[50] = \<const0> ;
  assign pipe_tx_2_sigs[49] = \<const0> ;
  assign pipe_tx_2_sigs[48] = \<const0> ;
  assign pipe_tx_2_sigs[47] = \<const0> ;
  assign pipe_tx_2_sigs[46] = \<const0> ;
  assign pipe_tx_2_sigs[45] = \<const0> ;
  assign pipe_tx_2_sigs[44] = \<const0> ;
  assign pipe_tx_2_sigs[43] = \<const0> ;
  assign pipe_tx_2_sigs[42] = \<const0> ;
  assign pipe_tx_2_sigs[41] = \<const0> ;
  assign pipe_tx_2_sigs[40] = \<const0> ;
  assign pipe_tx_2_sigs[39] = \<const0> ;
  assign pipe_tx_2_sigs[38] = \<const0> ;
  assign pipe_tx_2_sigs[37] = \<const0> ;
  assign pipe_tx_2_sigs[36] = \<const0> ;
  assign pipe_tx_2_sigs[35] = \<const0> ;
  assign pipe_tx_2_sigs[34] = \<const0> ;
  assign pipe_tx_2_sigs[33] = \<const0> ;
  assign pipe_tx_2_sigs[32] = \<const0> ;
  assign pipe_tx_2_sigs[31] = \<const0> ;
  assign pipe_tx_2_sigs[30] = \<const0> ;
  assign pipe_tx_2_sigs[29] = \<const0> ;
  assign pipe_tx_2_sigs[28] = \<const0> ;
  assign pipe_tx_2_sigs[27] = \<const0> ;
  assign pipe_tx_2_sigs[26] = \<const0> ;
  assign pipe_tx_2_sigs[25] = \<const0> ;
  assign pipe_tx_2_sigs[24] = \<const0> ;
  assign pipe_tx_2_sigs[23] = \<const0> ;
  assign pipe_tx_2_sigs[22] = \<const0> ;
  assign pipe_tx_2_sigs[21] = \<const0> ;
  assign pipe_tx_2_sigs[20] = \<const0> ;
  assign pipe_tx_2_sigs[19] = \<const0> ;
  assign pipe_tx_2_sigs[18] = \<const0> ;
  assign pipe_tx_2_sigs[17] = \<const0> ;
  assign pipe_tx_2_sigs[16] = \<const0> ;
  assign pipe_tx_2_sigs[15] = \<const0> ;
  assign pipe_tx_2_sigs[14] = \<const0> ;
  assign pipe_tx_2_sigs[13] = \<const0> ;
  assign pipe_tx_2_sigs[12] = \<const0> ;
  assign pipe_tx_2_sigs[11] = \<const0> ;
  assign pipe_tx_2_sigs[10] = \<const0> ;
  assign pipe_tx_2_sigs[9] = \<const0> ;
  assign pipe_tx_2_sigs[8] = \<const0> ;
  assign pipe_tx_2_sigs[7] = \<const0> ;
  assign pipe_tx_2_sigs[6] = \<const0> ;
  assign pipe_tx_2_sigs[5] = \<const0> ;
  assign pipe_tx_2_sigs[4] = \<const0> ;
  assign pipe_tx_2_sigs[3] = \<const0> ;
  assign pipe_tx_2_sigs[2] = \<const0> ;
  assign pipe_tx_2_sigs[1] = \<const0> ;
  assign pipe_tx_2_sigs[0] = \<const0> ;
  assign pipe_tx_3_sigs[83] = \<const0> ;
  assign pipe_tx_3_sigs[82] = \<const0> ;
  assign pipe_tx_3_sigs[81] = \<const0> ;
  assign pipe_tx_3_sigs[80] = \<const0> ;
  assign pipe_tx_3_sigs[79] = \<const0> ;
  assign pipe_tx_3_sigs[78] = \<const0> ;
  assign pipe_tx_3_sigs[77] = \<const0> ;
  assign pipe_tx_3_sigs[76] = \<const0> ;
  assign pipe_tx_3_sigs[75] = \<const0> ;
  assign pipe_tx_3_sigs[74] = \<const0> ;
  assign pipe_tx_3_sigs[73] = \<const0> ;
  assign pipe_tx_3_sigs[72] = \<const0> ;
  assign pipe_tx_3_sigs[71] = \<const0> ;
  assign pipe_tx_3_sigs[70] = \<const0> ;
  assign pipe_tx_3_sigs[69] = \<const0> ;
  assign pipe_tx_3_sigs[68] = \<const0> ;
  assign pipe_tx_3_sigs[67] = \<const0> ;
  assign pipe_tx_3_sigs[66] = \<const0> ;
  assign pipe_tx_3_sigs[65] = \<const0> ;
  assign pipe_tx_3_sigs[64] = \<const0> ;
  assign pipe_tx_3_sigs[63] = \<const0> ;
  assign pipe_tx_3_sigs[62] = \<const0> ;
  assign pipe_tx_3_sigs[61] = \<const0> ;
  assign pipe_tx_3_sigs[60] = \<const0> ;
  assign pipe_tx_3_sigs[59] = \<const0> ;
  assign pipe_tx_3_sigs[58] = \<const0> ;
  assign pipe_tx_3_sigs[57] = \<const0> ;
  assign pipe_tx_3_sigs[56] = \<const0> ;
  assign pipe_tx_3_sigs[55] = \<const0> ;
  assign pipe_tx_3_sigs[54] = \<const0> ;
  assign pipe_tx_3_sigs[53] = \<const0> ;
  assign pipe_tx_3_sigs[52] = \<const0> ;
  assign pipe_tx_3_sigs[51] = \<const0> ;
  assign pipe_tx_3_sigs[50] = \<const0> ;
  assign pipe_tx_3_sigs[49] = \<const0> ;
  assign pipe_tx_3_sigs[48] = \<const0> ;
  assign pipe_tx_3_sigs[47] = \<const0> ;
  assign pipe_tx_3_sigs[46] = \<const0> ;
  assign pipe_tx_3_sigs[45] = \<const0> ;
  assign pipe_tx_3_sigs[44] = \<const0> ;
  assign pipe_tx_3_sigs[43] = \<const0> ;
  assign pipe_tx_3_sigs[42] = \<const0> ;
  assign pipe_tx_3_sigs[41] = \<const0> ;
  assign pipe_tx_3_sigs[40] = \<const0> ;
  assign pipe_tx_3_sigs[39] = \<const0> ;
  assign pipe_tx_3_sigs[38] = \<const0> ;
  assign pipe_tx_3_sigs[37] = \<const0> ;
  assign pipe_tx_3_sigs[36] = \<const0> ;
  assign pipe_tx_3_sigs[35] = \<const0> ;
  assign pipe_tx_3_sigs[34] = \<const0> ;
  assign pipe_tx_3_sigs[33] = \<const0> ;
  assign pipe_tx_3_sigs[32] = \<const0> ;
  assign pipe_tx_3_sigs[31] = \<const0> ;
  assign pipe_tx_3_sigs[30] = \<const0> ;
  assign pipe_tx_3_sigs[29] = \<const0> ;
  assign pipe_tx_3_sigs[28] = \<const0> ;
  assign pipe_tx_3_sigs[27] = \<const0> ;
  assign pipe_tx_3_sigs[26] = \<const0> ;
  assign pipe_tx_3_sigs[25] = \<const0> ;
  assign pipe_tx_3_sigs[24] = \<const0> ;
  assign pipe_tx_3_sigs[23] = \<const0> ;
  assign pipe_tx_3_sigs[22] = \<const0> ;
  assign pipe_tx_3_sigs[21] = \<const0> ;
  assign pipe_tx_3_sigs[20] = \<const0> ;
  assign pipe_tx_3_sigs[19] = \<const0> ;
  assign pipe_tx_3_sigs[18] = \<const0> ;
  assign pipe_tx_3_sigs[17] = \<const0> ;
  assign pipe_tx_3_sigs[16] = \<const0> ;
  assign pipe_tx_3_sigs[15] = \<const0> ;
  assign pipe_tx_3_sigs[14] = \<const0> ;
  assign pipe_tx_3_sigs[13] = \<const0> ;
  assign pipe_tx_3_sigs[12] = \<const0> ;
  assign pipe_tx_3_sigs[11] = \<const0> ;
  assign pipe_tx_3_sigs[10] = \<const0> ;
  assign pipe_tx_3_sigs[9] = \<const0> ;
  assign pipe_tx_3_sigs[8] = \<const0> ;
  assign pipe_tx_3_sigs[7] = \<const0> ;
  assign pipe_tx_3_sigs[6] = \<const0> ;
  assign pipe_tx_3_sigs[5] = \<const0> ;
  assign pipe_tx_3_sigs[4] = \<const0> ;
  assign pipe_tx_3_sigs[3] = \<const0> ;
  assign pipe_tx_3_sigs[2] = \<const0> ;
  assign pipe_tx_3_sigs[1] = \<const0> ;
  assign pipe_tx_3_sigs[0] = \<const0> ;
  assign pipe_tx_4_sigs[83] = \<const0> ;
  assign pipe_tx_4_sigs[82] = \<const0> ;
  assign pipe_tx_4_sigs[81] = \<const0> ;
  assign pipe_tx_4_sigs[80] = \<const0> ;
  assign pipe_tx_4_sigs[79] = \<const0> ;
  assign pipe_tx_4_sigs[78] = \<const0> ;
  assign pipe_tx_4_sigs[77] = \<const0> ;
  assign pipe_tx_4_sigs[76] = \<const0> ;
  assign pipe_tx_4_sigs[75] = \<const0> ;
  assign pipe_tx_4_sigs[74] = \<const0> ;
  assign pipe_tx_4_sigs[73] = \<const0> ;
  assign pipe_tx_4_sigs[72] = \<const0> ;
  assign pipe_tx_4_sigs[71] = \<const0> ;
  assign pipe_tx_4_sigs[70] = \<const0> ;
  assign pipe_tx_4_sigs[69] = \<const0> ;
  assign pipe_tx_4_sigs[68] = \<const0> ;
  assign pipe_tx_4_sigs[67] = \<const0> ;
  assign pipe_tx_4_sigs[66] = \<const0> ;
  assign pipe_tx_4_sigs[65] = \<const0> ;
  assign pipe_tx_4_sigs[64] = \<const0> ;
  assign pipe_tx_4_sigs[63] = \<const0> ;
  assign pipe_tx_4_sigs[62] = \<const0> ;
  assign pipe_tx_4_sigs[61] = \<const0> ;
  assign pipe_tx_4_sigs[60] = \<const0> ;
  assign pipe_tx_4_sigs[59] = \<const0> ;
  assign pipe_tx_4_sigs[58] = \<const0> ;
  assign pipe_tx_4_sigs[57] = \<const0> ;
  assign pipe_tx_4_sigs[56] = \<const0> ;
  assign pipe_tx_4_sigs[55] = \<const0> ;
  assign pipe_tx_4_sigs[54] = \<const0> ;
  assign pipe_tx_4_sigs[53] = \<const0> ;
  assign pipe_tx_4_sigs[52] = \<const0> ;
  assign pipe_tx_4_sigs[51] = \<const0> ;
  assign pipe_tx_4_sigs[50] = \<const0> ;
  assign pipe_tx_4_sigs[49] = \<const0> ;
  assign pipe_tx_4_sigs[48] = \<const0> ;
  assign pipe_tx_4_sigs[47] = \<const0> ;
  assign pipe_tx_4_sigs[46] = \<const0> ;
  assign pipe_tx_4_sigs[45] = \<const0> ;
  assign pipe_tx_4_sigs[44] = \<const0> ;
  assign pipe_tx_4_sigs[43] = \<const0> ;
  assign pipe_tx_4_sigs[42] = \<const0> ;
  assign pipe_tx_4_sigs[41] = \<const0> ;
  assign pipe_tx_4_sigs[40] = \<const0> ;
  assign pipe_tx_4_sigs[39] = \<const0> ;
  assign pipe_tx_4_sigs[38] = \<const0> ;
  assign pipe_tx_4_sigs[37] = \<const0> ;
  assign pipe_tx_4_sigs[36] = \<const0> ;
  assign pipe_tx_4_sigs[35] = \<const0> ;
  assign pipe_tx_4_sigs[34] = \<const0> ;
  assign pipe_tx_4_sigs[33] = \<const0> ;
  assign pipe_tx_4_sigs[32] = \<const0> ;
  assign pipe_tx_4_sigs[31] = \<const0> ;
  assign pipe_tx_4_sigs[30] = \<const0> ;
  assign pipe_tx_4_sigs[29] = \<const0> ;
  assign pipe_tx_4_sigs[28] = \<const0> ;
  assign pipe_tx_4_sigs[27] = \<const0> ;
  assign pipe_tx_4_sigs[26] = \<const0> ;
  assign pipe_tx_4_sigs[25] = \<const0> ;
  assign pipe_tx_4_sigs[24] = \<const0> ;
  assign pipe_tx_4_sigs[23] = \<const0> ;
  assign pipe_tx_4_sigs[22] = \<const0> ;
  assign pipe_tx_4_sigs[21] = \<const0> ;
  assign pipe_tx_4_sigs[20] = \<const0> ;
  assign pipe_tx_4_sigs[19] = \<const0> ;
  assign pipe_tx_4_sigs[18] = \<const0> ;
  assign pipe_tx_4_sigs[17] = \<const0> ;
  assign pipe_tx_4_sigs[16] = \<const0> ;
  assign pipe_tx_4_sigs[15] = \<const0> ;
  assign pipe_tx_4_sigs[14] = \<const0> ;
  assign pipe_tx_4_sigs[13] = \<const0> ;
  assign pipe_tx_4_sigs[12] = \<const0> ;
  assign pipe_tx_4_sigs[11] = \<const0> ;
  assign pipe_tx_4_sigs[10] = \<const0> ;
  assign pipe_tx_4_sigs[9] = \<const0> ;
  assign pipe_tx_4_sigs[8] = \<const0> ;
  assign pipe_tx_4_sigs[7] = \<const0> ;
  assign pipe_tx_4_sigs[6] = \<const0> ;
  assign pipe_tx_4_sigs[5] = \<const0> ;
  assign pipe_tx_4_sigs[4] = \<const0> ;
  assign pipe_tx_4_sigs[3] = \<const0> ;
  assign pipe_tx_4_sigs[2] = \<const0> ;
  assign pipe_tx_4_sigs[1] = \<const0> ;
  assign pipe_tx_4_sigs[0] = \<const0> ;
  assign pipe_tx_5_sigs[83] = \<const0> ;
  assign pipe_tx_5_sigs[82] = \<const0> ;
  assign pipe_tx_5_sigs[81] = \<const0> ;
  assign pipe_tx_5_sigs[80] = \<const0> ;
  assign pipe_tx_5_sigs[79] = \<const0> ;
  assign pipe_tx_5_sigs[78] = \<const0> ;
  assign pipe_tx_5_sigs[77] = \<const0> ;
  assign pipe_tx_5_sigs[76] = \<const0> ;
  assign pipe_tx_5_sigs[75] = \<const0> ;
  assign pipe_tx_5_sigs[74] = \<const0> ;
  assign pipe_tx_5_sigs[73] = \<const0> ;
  assign pipe_tx_5_sigs[72] = \<const0> ;
  assign pipe_tx_5_sigs[71] = \<const0> ;
  assign pipe_tx_5_sigs[70] = \<const0> ;
  assign pipe_tx_5_sigs[69] = \<const0> ;
  assign pipe_tx_5_sigs[68] = \<const0> ;
  assign pipe_tx_5_sigs[67] = \<const0> ;
  assign pipe_tx_5_sigs[66] = \<const0> ;
  assign pipe_tx_5_sigs[65] = \<const0> ;
  assign pipe_tx_5_sigs[64] = \<const0> ;
  assign pipe_tx_5_sigs[63] = \<const0> ;
  assign pipe_tx_5_sigs[62] = \<const0> ;
  assign pipe_tx_5_sigs[61] = \<const0> ;
  assign pipe_tx_5_sigs[60] = \<const0> ;
  assign pipe_tx_5_sigs[59] = \<const0> ;
  assign pipe_tx_5_sigs[58] = \<const0> ;
  assign pipe_tx_5_sigs[57] = \<const0> ;
  assign pipe_tx_5_sigs[56] = \<const0> ;
  assign pipe_tx_5_sigs[55] = \<const0> ;
  assign pipe_tx_5_sigs[54] = \<const0> ;
  assign pipe_tx_5_sigs[53] = \<const0> ;
  assign pipe_tx_5_sigs[52] = \<const0> ;
  assign pipe_tx_5_sigs[51] = \<const0> ;
  assign pipe_tx_5_sigs[50] = \<const0> ;
  assign pipe_tx_5_sigs[49] = \<const0> ;
  assign pipe_tx_5_sigs[48] = \<const0> ;
  assign pipe_tx_5_sigs[47] = \<const0> ;
  assign pipe_tx_5_sigs[46] = \<const0> ;
  assign pipe_tx_5_sigs[45] = \<const0> ;
  assign pipe_tx_5_sigs[44] = \<const0> ;
  assign pipe_tx_5_sigs[43] = \<const0> ;
  assign pipe_tx_5_sigs[42] = \<const0> ;
  assign pipe_tx_5_sigs[41] = \<const0> ;
  assign pipe_tx_5_sigs[40] = \<const0> ;
  assign pipe_tx_5_sigs[39] = \<const0> ;
  assign pipe_tx_5_sigs[38] = \<const0> ;
  assign pipe_tx_5_sigs[37] = \<const0> ;
  assign pipe_tx_5_sigs[36] = \<const0> ;
  assign pipe_tx_5_sigs[35] = \<const0> ;
  assign pipe_tx_5_sigs[34] = \<const0> ;
  assign pipe_tx_5_sigs[33] = \<const0> ;
  assign pipe_tx_5_sigs[32] = \<const0> ;
  assign pipe_tx_5_sigs[31] = \<const0> ;
  assign pipe_tx_5_sigs[30] = \<const0> ;
  assign pipe_tx_5_sigs[29] = \<const0> ;
  assign pipe_tx_5_sigs[28] = \<const0> ;
  assign pipe_tx_5_sigs[27] = \<const0> ;
  assign pipe_tx_5_sigs[26] = \<const0> ;
  assign pipe_tx_5_sigs[25] = \<const0> ;
  assign pipe_tx_5_sigs[24] = \<const0> ;
  assign pipe_tx_5_sigs[23] = \<const0> ;
  assign pipe_tx_5_sigs[22] = \<const0> ;
  assign pipe_tx_5_sigs[21] = \<const0> ;
  assign pipe_tx_5_sigs[20] = \<const0> ;
  assign pipe_tx_5_sigs[19] = \<const0> ;
  assign pipe_tx_5_sigs[18] = \<const0> ;
  assign pipe_tx_5_sigs[17] = \<const0> ;
  assign pipe_tx_5_sigs[16] = \<const0> ;
  assign pipe_tx_5_sigs[15] = \<const0> ;
  assign pipe_tx_5_sigs[14] = \<const0> ;
  assign pipe_tx_5_sigs[13] = \<const0> ;
  assign pipe_tx_5_sigs[12] = \<const0> ;
  assign pipe_tx_5_sigs[11] = \<const0> ;
  assign pipe_tx_5_sigs[10] = \<const0> ;
  assign pipe_tx_5_sigs[9] = \<const0> ;
  assign pipe_tx_5_sigs[8] = \<const0> ;
  assign pipe_tx_5_sigs[7] = \<const0> ;
  assign pipe_tx_5_sigs[6] = \<const0> ;
  assign pipe_tx_5_sigs[5] = \<const0> ;
  assign pipe_tx_5_sigs[4] = \<const0> ;
  assign pipe_tx_5_sigs[3] = \<const0> ;
  assign pipe_tx_5_sigs[2] = \<const0> ;
  assign pipe_tx_5_sigs[1] = \<const0> ;
  assign pipe_tx_5_sigs[0] = \<const0> ;
  assign pipe_tx_6_sigs[83] = \<const0> ;
  assign pipe_tx_6_sigs[82] = \<const0> ;
  assign pipe_tx_6_sigs[81] = \<const0> ;
  assign pipe_tx_6_sigs[80] = \<const0> ;
  assign pipe_tx_6_sigs[79] = \<const0> ;
  assign pipe_tx_6_sigs[78] = \<const0> ;
  assign pipe_tx_6_sigs[77] = \<const0> ;
  assign pipe_tx_6_sigs[76] = \<const0> ;
  assign pipe_tx_6_sigs[75] = \<const0> ;
  assign pipe_tx_6_sigs[74] = \<const0> ;
  assign pipe_tx_6_sigs[73] = \<const0> ;
  assign pipe_tx_6_sigs[72] = \<const0> ;
  assign pipe_tx_6_sigs[71] = \<const0> ;
  assign pipe_tx_6_sigs[70] = \<const0> ;
  assign pipe_tx_6_sigs[69] = \<const0> ;
  assign pipe_tx_6_sigs[68] = \<const0> ;
  assign pipe_tx_6_sigs[67] = \<const0> ;
  assign pipe_tx_6_sigs[66] = \<const0> ;
  assign pipe_tx_6_sigs[65] = \<const0> ;
  assign pipe_tx_6_sigs[64] = \<const0> ;
  assign pipe_tx_6_sigs[63] = \<const0> ;
  assign pipe_tx_6_sigs[62] = \<const0> ;
  assign pipe_tx_6_sigs[61] = \<const0> ;
  assign pipe_tx_6_sigs[60] = \<const0> ;
  assign pipe_tx_6_sigs[59] = \<const0> ;
  assign pipe_tx_6_sigs[58] = \<const0> ;
  assign pipe_tx_6_sigs[57] = \<const0> ;
  assign pipe_tx_6_sigs[56] = \<const0> ;
  assign pipe_tx_6_sigs[55] = \<const0> ;
  assign pipe_tx_6_sigs[54] = \<const0> ;
  assign pipe_tx_6_sigs[53] = \<const0> ;
  assign pipe_tx_6_sigs[52] = \<const0> ;
  assign pipe_tx_6_sigs[51] = \<const0> ;
  assign pipe_tx_6_sigs[50] = \<const0> ;
  assign pipe_tx_6_sigs[49] = \<const0> ;
  assign pipe_tx_6_sigs[48] = \<const0> ;
  assign pipe_tx_6_sigs[47] = \<const0> ;
  assign pipe_tx_6_sigs[46] = \<const0> ;
  assign pipe_tx_6_sigs[45] = \<const0> ;
  assign pipe_tx_6_sigs[44] = \<const0> ;
  assign pipe_tx_6_sigs[43] = \<const0> ;
  assign pipe_tx_6_sigs[42] = \<const0> ;
  assign pipe_tx_6_sigs[41] = \<const0> ;
  assign pipe_tx_6_sigs[40] = \<const0> ;
  assign pipe_tx_6_sigs[39] = \<const0> ;
  assign pipe_tx_6_sigs[38] = \<const0> ;
  assign pipe_tx_6_sigs[37] = \<const0> ;
  assign pipe_tx_6_sigs[36] = \<const0> ;
  assign pipe_tx_6_sigs[35] = \<const0> ;
  assign pipe_tx_6_sigs[34] = \<const0> ;
  assign pipe_tx_6_sigs[33] = \<const0> ;
  assign pipe_tx_6_sigs[32] = \<const0> ;
  assign pipe_tx_6_sigs[31] = \<const0> ;
  assign pipe_tx_6_sigs[30] = \<const0> ;
  assign pipe_tx_6_sigs[29] = \<const0> ;
  assign pipe_tx_6_sigs[28] = \<const0> ;
  assign pipe_tx_6_sigs[27] = \<const0> ;
  assign pipe_tx_6_sigs[26] = \<const0> ;
  assign pipe_tx_6_sigs[25] = \<const0> ;
  assign pipe_tx_6_sigs[24] = \<const0> ;
  assign pipe_tx_6_sigs[23] = \<const0> ;
  assign pipe_tx_6_sigs[22] = \<const0> ;
  assign pipe_tx_6_sigs[21] = \<const0> ;
  assign pipe_tx_6_sigs[20] = \<const0> ;
  assign pipe_tx_6_sigs[19] = \<const0> ;
  assign pipe_tx_6_sigs[18] = \<const0> ;
  assign pipe_tx_6_sigs[17] = \<const0> ;
  assign pipe_tx_6_sigs[16] = \<const0> ;
  assign pipe_tx_6_sigs[15] = \<const0> ;
  assign pipe_tx_6_sigs[14] = \<const0> ;
  assign pipe_tx_6_sigs[13] = \<const0> ;
  assign pipe_tx_6_sigs[12] = \<const0> ;
  assign pipe_tx_6_sigs[11] = \<const0> ;
  assign pipe_tx_6_sigs[10] = \<const0> ;
  assign pipe_tx_6_sigs[9] = \<const0> ;
  assign pipe_tx_6_sigs[8] = \<const0> ;
  assign pipe_tx_6_sigs[7] = \<const0> ;
  assign pipe_tx_6_sigs[6] = \<const0> ;
  assign pipe_tx_6_sigs[5] = \<const0> ;
  assign pipe_tx_6_sigs[4] = \<const0> ;
  assign pipe_tx_6_sigs[3] = \<const0> ;
  assign pipe_tx_6_sigs[2] = \<const0> ;
  assign pipe_tx_6_sigs[1] = \<const0> ;
  assign pipe_tx_6_sigs[0] = \<const0> ;
  assign pipe_tx_7_sigs[83] = \<const0> ;
  assign pipe_tx_7_sigs[82] = \<const0> ;
  assign pipe_tx_7_sigs[81] = \<const0> ;
  assign pipe_tx_7_sigs[80] = \<const0> ;
  assign pipe_tx_7_sigs[79] = \<const0> ;
  assign pipe_tx_7_sigs[78] = \<const0> ;
  assign pipe_tx_7_sigs[77] = \<const0> ;
  assign pipe_tx_7_sigs[76] = \<const0> ;
  assign pipe_tx_7_sigs[75] = \<const0> ;
  assign pipe_tx_7_sigs[74] = \<const0> ;
  assign pipe_tx_7_sigs[73] = \<const0> ;
  assign pipe_tx_7_sigs[72] = \<const0> ;
  assign pipe_tx_7_sigs[71] = \<const0> ;
  assign pipe_tx_7_sigs[70] = \<const0> ;
  assign pipe_tx_7_sigs[69] = \<const0> ;
  assign pipe_tx_7_sigs[68] = \<const0> ;
  assign pipe_tx_7_sigs[67] = \<const0> ;
  assign pipe_tx_7_sigs[66] = \<const0> ;
  assign pipe_tx_7_sigs[65] = \<const0> ;
  assign pipe_tx_7_sigs[64] = \<const0> ;
  assign pipe_tx_7_sigs[63] = \<const0> ;
  assign pipe_tx_7_sigs[62] = \<const0> ;
  assign pipe_tx_7_sigs[61] = \<const0> ;
  assign pipe_tx_7_sigs[60] = \<const0> ;
  assign pipe_tx_7_sigs[59] = \<const0> ;
  assign pipe_tx_7_sigs[58] = \<const0> ;
  assign pipe_tx_7_sigs[57] = \<const0> ;
  assign pipe_tx_7_sigs[56] = \<const0> ;
  assign pipe_tx_7_sigs[55] = \<const0> ;
  assign pipe_tx_7_sigs[54] = \<const0> ;
  assign pipe_tx_7_sigs[53] = \<const0> ;
  assign pipe_tx_7_sigs[52] = \<const0> ;
  assign pipe_tx_7_sigs[51] = \<const0> ;
  assign pipe_tx_7_sigs[50] = \<const0> ;
  assign pipe_tx_7_sigs[49] = \<const0> ;
  assign pipe_tx_7_sigs[48] = \<const0> ;
  assign pipe_tx_7_sigs[47] = \<const0> ;
  assign pipe_tx_7_sigs[46] = \<const0> ;
  assign pipe_tx_7_sigs[45] = \<const0> ;
  assign pipe_tx_7_sigs[44] = \<const0> ;
  assign pipe_tx_7_sigs[43] = \<const0> ;
  assign pipe_tx_7_sigs[42] = \<const0> ;
  assign pipe_tx_7_sigs[41] = \<const0> ;
  assign pipe_tx_7_sigs[40] = \<const0> ;
  assign pipe_tx_7_sigs[39] = \<const0> ;
  assign pipe_tx_7_sigs[38] = \<const0> ;
  assign pipe_tx_7_sigs[37] = \<const0> ;
  assign pipe_tx_7_sigs[36] = \<const0> ;
  assign pipe_tx_7_sigs[35] = \<const0> ;
  assign pipe_tx_7_sigs[34] = \<const0> ;
  assign pipe_tx_7_sigs[33] = \<const0> ;
  assign pipe_tx_7_sigs[32] = \<const0> ;
  assign pipe_tx_7_sigs[31] = \<const0> ;
  assign pipe_tx_7_sigs[30] = \<const0> ;
  assign pipe_tx_7_sigs[29] = \<const0> ;
  assign pipe_tx_7_sigs[28] = \<const0> ;
  assign pipe_tx_7_sigs[27] = \<const0> ;
  assign pipe_tx_7_sigs[26] = \<const0> ;
  assign pipe_tx_7_sigs[25] = \<const0> ;
  assign pipe_tx_7_sigs[24] = \<const0> ;
  assign pipe_tx_7_sigs[23] = \<const0> ;
  assign pipe_tx_7_sigs[22] = \<const0> ;
  assign pipe_tx_7_sigs[21] = \<const0> ;
  assign pipe_tx_7_sigs[20] = \<const0> ;
  assign pipe_tx_7_sigs[19] = \<const0> ;
  assign pipe_tx_7_sigs[18] = \<const0> ;
  assign pipe_tx_7_sigs[17] = \<const0> ;
  assign pipe_tx_7_sigs[16] = \<const0> ;
  assign pipe_tx_7_sigs[15] = \<const0> ;
  assign pipe_tx_7_sigs[14] = \<const0> ;
  assign pipe_tx_7_sigs[13] = \<const0> ;
  assign pipe_tx_7_sigs[12] = \<const0> ;
  assign pipe_tx_7_sigs[11] = \<const0> ;
  assign pipe_tx_7_sigs[10] = \<const0> ;
  assign pipe_tx_7_sigs[9] = \<const0> ;
  assign pipe_tx_7_sigs[8] = \<const0> ;
  assign pipe_tx_7_sigs[7] = \<const0> ;
  assign pipe_tx_7_sigs[6] = \<const0> ;
  assign pipe_tx_7_sigs[5] = \<const0> ;
  assign pipe_tx_7_sigs[4] = \<const0> ;
  assign pipe_tx_7_sigs[3] = \<const0> ;
  assign pipe_tx_7_sigs[2] = \<const0> ;
  assign pipe_tx_7_sigs[1] = \<const0> ;
  assign pipe_tx_7_sigs[0] = \<const0> ;
  assign pipe_tx_8_sigs[83] = \<const0> ;
  assign pipe_tx_8_sigs[82] = \<const0> ;
  assign pipe_tx_8_sigs[81] = \<const0> ;
  assign pipe_tx_8_sigs[80] = \<const0> ;
  assign pipe_tx_8_sigs[79] = \<const0> ;
  assign pipe_tx_8_sigs[78] = \<const0> ;
  assign pipe_tx_8_sigs[77] = \<const0> ;
  assign pipe_tx_8_sigs[76] = \<const0> ;
  assign pipe_tx_8_sigs[75] = \<const0> ;
  assign pipe_tx_8_sigs[74] = \<const0> ;
  assign pipe_tx_8_sigs[73] = \<const0> ;
  assign pipe_tx_8_sigs[72] = \<const0> ;
  assign pipe_tx_8_sigs[71] = \<const0> ;
  assign pipe_tx_8_sigs[70] = \<const0> ;
  assign pipe_tx_8_sigs[69] = \<const0> ;
  assign pipe_tx_8_sigs[68] = \<const0> ;
  assign pipe_tx_8_sigs[67] = \<const0> ;
  assign pipe_tx_8_sigs[66] = \<const0> ;
  assign pipe_tx_8_sigs[65] = \<const0> ;
  assign pipe_tx_8_sigs[64] = \<const0> ;
  assign pipe_tx_8_sigs[63] = \<const0> ;
  assign pipe_tx_8_sigs[62] = \<const0> ;
  assign pipe_tx_8_sigs[61] = \<const0> ;
  assign pipe_tx_8_sigs[60] = \<const0> ;
  assign pipe_tx_8_sigs[59] = \<const0> ;
  assign pipe_tx_8_sigs[58] = \<const0> ;
  assign pipe_tx_8_sigs[57] = \<const0> ;
  assign pipe_tx_8_sigs[56] = \<const0> ;
  assign pipe_tx_8_sigs[55] = \<const0> ;
  assign pipe_tx_8_sigs[54] = \<const0> ;
  assign pipe_tx_8_sigs[53] = \<const0> ;
  assign pipe_tx_8_sigs[52] = \<const0> ;
  assign pipe_tx_8_sigs[51] = \<const0> ;
  assign pipe_tx_8_sigs[50] = \<const0> ;
  assign pipe_tx_8_sigs[49] = \<const0> ;
  assign pipe_tx_8_sigs[48] = \<const0> ;
  assign pipe_tx_8_sigs[47] = \<const0> ;
  assign pipe_tx_8_sigs[46] = \<const0> ;
  assign pipe_tx_8_sigs[45] = \<const0> ;
  assign pipe_tx_8_sigs[44] = \<const0> ;
  assign pipe_tx_8_sigs[43] = \<const0> ;
  assign pipe_tx_8_sigs[42] = \<const0> ;
  assign pipe_tx_8_sigs[41] = \<const0> ;
  assign pipe_tx_8_sigs[40] = \<const0> ;
  assign pipe_tx_8_sigs[39] = \<const0> ;
  assign pipe_tx_8_sigs[38] = \<const0> ;
  assign pipe_tx_8_sigs[37] = \<const0> ;
  assign pipe_tx_8_sigs[36] = \<const0> ;
  assign pipe_tx_8_sigs[35] = \<const0> ;
  assign pipe_tx_8_sigs[34] = \<const0> ;
  assign pipe_tx_8_sigs[33] = \<const0> ;
  assign pipe_tx_8_sigs[32] = \<const0> ;
  assign pipe_tx_8_sigs[31] = \<const0> ;
  assign pipe_tx_8_sigs[30] = \<const0> ;
  assign pipe_tx_8_sigs[29] = \<const0> ;
  assign pipe_tx_8_sigs[28] = \<const0> ;
  assign pipe_tx_8_sigs[27] = \<const0> ;
  assign pipe_tx_8_sigs[26] = \<const0> ;
  assign pipe_tx_8_sigs[25] = \<const0> ;
  assign pipe_tx_8_sigs[24] = \<const0> ;
  assign pipe_tx_8_sigs[23] = \<const0> ;
  assign pipe_tx_8_sigs[22] = \<const0> ;
  assign pipe_tx_8_sigs[21] = \<const0> ;
  assign pipe_tx_8_sigs[20] = \<const0> ;
  assign pipe_tx_8_sigs[19] = \<const0> ;
  assign pipe_tx_8_sigs[18] = \<const0> ;
  assign pipe_tx_8_sigs[17] = \<const0> ;
  assign pipe_tx_8_sigs[16] = \<const0> ;
  assign pipe_tx_8_sigs[15] = \<const0> ;
  assign pipe_tx_8_sigs[14] = \<const0> ;
  assign pipe_tx_8_sigs[13] = \<const0> ;
  assign pipe_tx_8_sigs[12] = \<const0> ;
  assign pipe_tx_8_sigs[11] = \<const0> ;
  assign pipe_tx_8_sigs[10] = \<const0> ;
  assign pipe_tx_8_sigs[9] = \<const0> ;
  assign pipe_tx_8_sigs[8] = \<const0> ;
  assign pipe_tx_8_sigs[7] = \<const0> ;
  assign pipe_tx_8_sigs[6] = \<const0> ;
  assign pipe_tx_8_sigs[5] = \<const0> ;
  assign pipe_tx_8_sigs[4] = \<const0> ;
  assign pipe_tx_8_sigs[3] = \<const0> ;
  assign pipe_tx_8_sigs[2] = \<const0> ;
  assign pipe_tx_8_sigs[1] = \<const0> ;
  assign pipe_tx_8_sigs[0] = \<const0> ;
  assign pipe_tx_9_sigs[83] = \<const0> ;
  assign pipe_tx_9_sigs[82] = \<const0> ;
  assign pipe_tx_9_sigs[81] = \<const0> ;
  assign pipe_tx_9_sigs[80] = \<const0> ;
  assign pipe_tx_9_sigs[79] = \<const0> ;
  assign pipe_tx_9_sigs[78] = \<const0> ;
  assign pipe_tx_9_sigs[77] = \<const0> ;
  assign pipe_tx_9_sigs[76] = \<const0> ;
  assign pipe_tx_9_sigs[75] = \<const0> ;
  assign pipe_tx_9_sigs[74] = \<const0> ;
  assign pipe_tx_9_sigs[73] = \<const0> ;
  assign pipe_tx_9_sigs[72] = \<const0> ;
  assign pipe_tx_9_sigs[71] = \<const0> ;
  assign pipe_tx_9_sigs[70] = \<const0> ;
  assign pipe_tx_9_sigs[69] = \<const0> ;
  assign pipe_tx_9_sigs[68] = \<const0> ;
  assign pipe_tx_9_sigs[67] = \<const0> ;
  assign pipe_tx_9_sigs[66] = \<const0> ;
  assign pipe_tx_9_sigs[65] = \<const0> ;
  assign pipe_tx_9_sigs[64] = \<const0> ;
  assign pipe_tx_9_sigs[63] = \<const0> ;
  assign pipe_tx_9_sigs[62] = \<const0> ;
  assign pipe_tx_9_sigs[61] = \<const0> ;
  assign pipe_tx_9_sigs[60] = \<const0> ;
  assign pipe_tx_9_sigs[59] = \<const0> ;
  assign pipe_tx_9_sigs[58] = \<const0> ;
  assign pipe_tx_9_sigs[57] = \<const0> ;
  assign pipe_tx_9_sigs[56] = \<const0> ;
  assign pipe_tx_9_sigs[55] = \<const0> ;
  assign pipe_tx_9_sigs[54] = \<const0> ;
  assign pipe_tx_9_sigs[53] = \<const0> ;
  assign pipe_tx_9_sigs[52] = \<const0> ;
  assign pipe_tx_9_sigs[51] = \<const0> ;
  assign pipe_tx_9_sigs[50] = \<const0> ;
  assign pipe_tx_9_sigs[49] = \<const0> ;
  assign pipe_tx_9_sigs[48] = \<const0> ;
  assign pipe_tx_9_sigs[47] = \<const0> ;
  assign pipe_tx_9_sigs[46] = \<const0> ;
  assign pipe_tx_9_sigs[45] = \<const0> ;
  assign pipe_tx_9_sigs[44] = \<const0> ;
  assign pipe_tx_9_sigs[43] = \<const0> ;
  assign pipe_tx_9_sigs[42] = \<const0> ;
  assign pipe_tx_9_sigs[41] = \<const0> ;
  assign pipe_tx_9_sigs[40] = \<const0> ;
  assign pipe_tx_9_sigs[39] = \<const0> ;
  assign pipe_tx_9_sigs[38] = \<const0> ;
  assign pipe_tx_9_sigs[37] = \<const0> ;
  assign pipe_tx_9_sigs[36] = \<const0> ;
  assign pipe_tx_9_sigs[35] = \<const0> ;
  assign pipe_tx_9_sigs[34] = \<const0> ;
  assign pipe_tx_9_sigs[33] = \<const0> ;
  assign pipe_tx_9_sigs[32] = \<const0> ;
  assign pipe_tx_9_sigs[31] = \<const0> ;
  assign pipe_tx_9_sigs[30] = \<const0> ;
  assign pipe_tx_9_sigs[29] = \<const0> ;
  assign pipe_tx_9_sigs[28] = \<const0> ;
  assign pipe_tx_9_sigs[27] = \<const0> ;
  assign pipe_tx_9_sigs[26] = \<const0> ;
  assign pipe_tx_9_sigs[25] = \<const0> ;
  assign pipe_tx_9_sigs[24] = \<const0> ;
  assign pipe_tx_9_sigs[23] = \<const0> ;
  assign pipe_tx_9_sigs[22] = \<const0> ;
  assign pipe_tx_9_sigs[21] = \<const0> ;
  assign pipe_tx_9_sigs[20] = \<const0> ;
  assign pipe_tx_9_sigs[19] = \<const0> ;
  assign pipe_tx_9_sigs[18] = \<const0> ;
  assign pipe_tx_9_sigs[17] = \<const0> ;
  assign pipe_tx_9_sigs[16] = \<const0> ;
  assign pipe_tx_9_sigs[15] = \<const0> ;
  assign pipe_tx_9_sigs[14] = \<const0> ;
  assign pipe_tx_9_sigs[13] = \<const0> ;
  assign pipe_tx_9_sigs[12] = \<const0> ;
  assign pipe_tx_9_sigs[11] = \<const0> ;
  assign pipe_tx_9_sigs[10] = \<const0> ;
  assign pipe_tx_9_sigs[9] = \<const0> ;
  assign pipe_tx_9_sigs[8] = \<const0> ;
  assign pipe_tx_9_sigs[7] = \<const0> ;
  assign pipe_tx_9_sigs[6] = \<const0> ;
  assign pipe_tx_9_sigs[5] = \<const0> ;
  assign pipe_tx_9_sigs[4] = \<const0> ;
  assign pipe_tx_9_sigs[3] = \<const0> ;
  assign pipe_tx_9_sigs[2] = \<const0> ;
  assign pipe_tx_9_sigs[1] = \<const0> ;
  assign pipe_tx_9_sigs[0] = \<const0> ;
  assign pipe_txdlysresetdone[1] = \<const0> ;
  assign pipe_txdlysresetdone[0] = \<const0> ;
  assign pipe_txoutclk_out = \<const0> ;
  assign pipe_txphaligndone[1] = \<const0> ;
  assign pipe_txphaligndone[0] = \<const0> ;
  assign pipe_txphinitdone[1] = \<const0> ;
  assign pipe_txphinitdone[0] = \<const0> ;
  assign qpll0clk_us_in[1] = \<const0> ;
  assign qpll0clk_us_in[0] = \<const0> ;
  assign qpll0freqlock_usp_in[1] = \<const0> ;
  assign qpll0freqlock_usp_in[0] = \<const0> ;
  assign qpll0pd_usp_in[0] = \<const0> ;
  assign qpll0refclk_us_in[1] = \<const0> ;
  assign qpll0refclk_us_in[0] = \<const0> ;
  assign qpll0reset_usp_in[0] = \<const0> ;
  assign qpll1clk_us_in[1] = \<const0> ;
  assign qpll1clk_us_in[0] = \<const0> ;
  assign qpll1freqlock_usp_in[1] = \<const0> ;
  assign qpll1freqlock_usp_in[0] = \<const0> ;
  assign qpll1pd_us_in[0] = \<const0> ;
  assign qpll1pd_usp_in[0] = \<const0> ;
  assign qpll1refclk_us_in[1] = \<const0> ;
  assign qpll1refclk_us_in[0] = \<const0> ;
  assign qpll1reset_us_in[0] = \<const0> ;
  assign qpll1reset_usp_in[0] = \<const0> ;
  assign qpll_drp_clk = \<const0> ;
  assign qpll_drp_gen3 = \<const0> ;
  assign qpll_drp_ovrd = \<const0> ;
  assign qpll_drp_rst_n = \<const0> ;
  assign qpll_drp_start = \<const0> ;
  assign qpll_qplld = \<const0> ;
  assign qpll_qpllreset[1] = \<const0> ;
  assign qpll_qpllreset[0] = \<const0> ;
  assign qpllrsvd2_us_in[4] = \<const0> ;
  assign qpllrsvd2_us_in[3] = \<const0> ;
  assign qpllrsvd2_us_in[2] = \<const0> ;
  assign qpllrsvd2_us_in[1] = \<const0> ;
  assign qpllrsvd2_us_in[0] = \<const0> ;
  assign qpllrsvd3_us_in[4] = \<const0> ;
  assign qpllrsvd3_us_in[3] = \<const0> ;
  assign qpllrsvd3_us_in[2] = \<const0> ;
  assign qpllrsvd3_us_in[1] = \<const0> ;
  assign qpllrsvd3_us_in[0] = \<const0> ;
  assign rcalenb_usp_in[0] = \<const0> ;
  assign rd_interrupt = \<const0> ;
  assign resetovrd_usp_in[1] = \<const0> ;
  assign resetovrd_usp_in[0] = \<const0> ;
  assign rx8b10ben_us_in[1] = \<const0> ;
  assign rx8b10ben_us_in[0] = \<const0> ;
  assign rx8b10ben_usp_in[1] = \<const0> ;
  assign rx8b10ben_usp_in[0] = \<const0> ;
  assign rxbufreset_us_in[1] = \<const0> ;
  assign rxbufreset_us_in[0] = \<const0> ;
  assign rxbufreset_usp_in[1] = \<const0> ;
  assign rxbufreset_usp_in[0] = \<const0> ;
  assign rxcdrfreqreset_usp_in[1] = \<const0> ;
  assign rxcdrfreqreset_usp_in[0] = \<const0> ;
  assign rxcdrhold_us_in[1] = \<const0> ;
  assign rxcdrhold_us_in[0] = \<const0> ;
  assign rxcdrhold_usp_in[1] = \<const0> ;
  assign rxcdrhold_usp_in[0] = \<const0> ;
  assign rxcdrreset_usp_in[1] = \<const0> ;
  assign rxcdrreset_usp_in[0] = \<const0> ;
  assign rxcommadeten_us_in[1] = \<const0> ;
  assign rxcommadeten_us_in[0] = \<const0> ;
  assign rxcommadeten_usp_in[1] = \<const0> ;
  assign rxcommadeten_usp_in[0] = \<const0> ;
  assign rxdfeagchold_us_in[1] = \<const0> ;
  assign rxdfeagchold_us_in[0] = \<const0> ;
  assign rxdfeagchold_usp_in[1] = \<const0> ;
  assign rxdfeagchold_usp_in[0] = \<const0> ;
  assign rxdfecfokhold_us_in[1] = \<const0> ;
  assign rxdfecfokhold_us_in[0] = \<const0> ;
  assign rxdfecfokhold_usp_in[1] = \<const0> ;
  assign rxdfecfokhold_usp_in[0] = \<const0> ;
  assign rxdfekhhold_us_in[1] = \<const0> ;
  assign rxdfekhhold_us_in[0] = \<const0> ;
  assign rxdfekhhold_usp_in[1] = \<const0> ;
  assign rxdfekhhold_usp_in[0] = \<const0> ;
  assign rxdfelfhold_us_in[1] = \<const0> ;
  assign rxdfelfhold_us_in[0] = \<const0> ;
  assign rxdfelfhold_usp_in[1] = \<const0> ;
  assign rxdfelfhold_usp_in[0] = \<const0> ;
  assign rxdfelpmreset_usp_in[1] = \<const0> ;
  assign rxdfelpmreset_usp_in[0] = \<const0> ;
  assign rxdfetap10hold_us_in[1] = \<const0> ;
  assign rxdfetap10hold_us_in[0] = \<const0> ;
  assign rxdfetap10hold_usp_in[1] = \<const0> ;
  assign rxdfetap10hold_usp_in[0] = \<const0> ;
  assign rxdfetap11hold_us_in[1] = \<const0> ;
  assign rxdfetap11hold_us_in[0] = \<const0> ;
  assign rxdfetap11hold_usp_in[1] = \<const0> ;
  assign rxdfetap11hold_usp_in[0] = \<const0> ;
  assign rxdfetap12hold_us_in[1] = \<const0> ;
  assign rxdfetap12hold_us_in[0] = \<const0> ;
  assign rxdfetap12hold_usp_in[1] = \<const0> ;
  assign rxdfetap12hold_usp_in[0] = \<const0> ;
  assign rxdfetap13hold_us_in[1] = \<const0> ;
  assign rxdfetap13hold_us_in[0] = \<const0> ;
  assign rxdfetap13hold_usp_in[1] = \<const0> ;
  assign rxdfetap13hold_usp_in[0] = \<const0> ;
  assign rxdfetap14hold_us_in[1] = \<const0> ;
  assign rxdfetap14hold_us_in[0] = \<const0> ;
  assign rxdfetap14hold_usp_in[1] = \<const0> ;
  assign rxdfetap14hold_usp_in[0] = \<const0> ;
  assign rxdfetap15hold_us_in[1] = \<const0> ;
  assign rxdfetap15hold_us_in[0] = \<const0> ;
  assign rxdfetap15hold_usp_in[1] = \<const0> ;
  assign rxdfetap15hold_usp_in[0] = \<const0> ;
  assign rxdfetap2hold_us_in[1] = \<const0> ;
  assign rxdfetap2hold_us_in[0] = \<const0> ;
  assign rxdfetap2hold_usp_in[1] = \<const0> ;
  assign rxdfetap2hold_usp_in[0] = \<const0> ;
  assign rxdfetap3hold_us_in[1] = \<const0> ;
  assign rxdfetap3hold_us_in[0] = \<const0> ;
  assign rxdfetap3hold_usp_in[1] = \<const0> ;
  assign rxdfetap3hold_usp_in[0] = \<const0> ;
  assign rxdfetap4hold_us_in[1] = \<const0> ;
  assign rxdfetap4hold_us_in[0] = \<const0> ;
  assign rxdfetap4hold_usp_in[1] = \<const0> ;
  assign rxdfetap4hold_usp_in[0] = \<const0> ;
  assign rxdfetap5hold_us_in[1] = \<const0> ;
  assign rxdfetap5hold_us_in[0] = \<const0> ;
  assign rxdfetap5hold_usp_in[1] = \<const0> ;
  assign rxdfetap5hold_usp_in[0] = \<const0> ;
  assign rxdfetap6hold_us_in[1] = \<const0> ;
  assign rxdfetap6hold_us_in[0] = \<const0> ;
  assign rxdfetap6hold_usp_in[1] = \<const0> ;
  assign rxdfetap6hold_usp_in[0] = \<const0> ;
  assign rxdfetap7hold_us_in[1] = \<const0> ;
  assign rxdfetap7hold_us_in[0] = \<const0> ;
  assign rxdfetap7hold_usp_in[1] = \<const0> ;
  assign rxdfetap7hold_usp_in[0] = \<const0> ;
  assign rxdfetap8hold_us_in[1] = \<const0> ;
  assign rxdfetap8hold_us_in[0] = \<const0> ;
  assign rxdfetap8hold_usp_in[1] = \<const0> ;
  assign rxdfetap8hold_usp_in[0] = \<const0> ;
  assign rxdfetap9hold_us_in[1] = \<const0> ;
  assign rxdfetap9hold_us_in[0] = \<const0> ;
  assign rxdfetap9hold_usp_in[1] = \<const0> ;
  assign rxdfetap9hold_usp_in[0] = \<const0> ;
  assign rxdfeuthold_us_in[1] = \<const0> ;
  assign rxdfeuthold_us_in[0] = \<const0> ;
  assign rxdfeuthold_usp_in[1] = \<const0> ;
  assign rxdfeuthold_usp_in[0] = \<const0> ;
  assign rxdfevphold_us_in[1] = \<const0> ;
  assign rxdfevphold_us_in[0] = \<const0> ;
  assign rxdfevphold_usp_in[1] = \<const0> ;
  assign rxdfevphold_usp_in[0] = \<const0> ;
  assign rxlpmen_us_in[1] = \<const0> ;
  assign rxlpmen_us_in[0] = \<const0> ;
  assign rxlpmen_usp_in[1] = \<const0> ;
  assign rxlpmen_usp_in[0] = \<const0> ;
  assign rxlpmgchold_us_in[1] = \<const0> ;
  assign rxlpmgchold_us_in[0] = \<const0> ;
  assign rxlpmgchold_usp_in[1] = \<const0> ;
  assign rxlpmgchold_usp_in[0] = \<const0> ;
  assign rxlpmhfhold_us_in[1] = \<const0> ;
  assign rxlpmhfhold_us_in[0] = \<const0> ;
  assign rxlpmhfhold_usp_in[1] = \<const0> ;
  assign rxlpmhfhold_usp_in[0] = \<const0> ;
  assign rxlpmlfhold_us_in[1] = \<const0> ;
  assign rxlpmlfhold_us_in[0] = \<const0> ;
  assign rxlpmlfhold_usp_in[1] = \<const0> ;
  assign rxlpmlfhold_usp_in[0] = \<const0> ;
  assign rxlpmoshold_us_in[1] = \<const0> ;
  assign rxlpmoshold_us_in[0] = \<const0> ;
  assign rxlpmoshold_usp_in[1] = \<const0> ;
  assign rxlpmoshold_usp_in[0] = \<const0> ;
  assign rxmcommaalignen_us_in[1] = \<const0> ;
  assign rxmcommaalignen_us_in[0] = \<const0> ;
  assign rxmcommaalignen_usp_in[1] = \<const0> ;
  assign rxmcommaalignen_usp_in[0] = \<const0> ;
  assign rxoshold_us_in[1] = \<const0> ;
  assign rxoshold_us_in[0] = \<const0> ;
  assign rxoshold_usp_in[1] = \<const0> ;
  assign rxoshold_usp_in[0] = \<const0> ;
  assign rxpcommaalignen_us_in[1] = \<const0> ;
  assign rxpcommaalignen_us_in[0] = \<const0> ;
  assign rxpcommaalignen_usp_in[1] = \<const0> ;
  assign rxpcommaalignen_usp_in[0] = \<const0> ;
  assign rxpcsreset_usp_in[1] = \<const0> ;
  assign rxpcsreset_usp_in[0] = \<const0> ;
  assign rxpd_us_in[3] = \<const0> ;
  assign rxpd_us_in[2] = \<const0> ;
  assign rxpd_us_in[1] = \<const0> ;
  assign rxpd_us_in[0] = \<const0> ;
  assign rxpd_usp_in[3] = \<const0> ;
  assign rxpd_usp_in[2] = \<const0> ;
  assign rxpd_usp_in[1] = \<const0> ;
  assign rxpd_usp_in[0] = \<const0> ;
  assign rxpmareset_usp_in[1] = \<const0> ;
  assign rxpmareset_usp_in[0] = \<const0> ;
  assign rxpolarity_us_in[1] = \<const0> ;
  assign rxpolarity_us_in[0] = \<const0> ;
  assign rxpolarity_usp_in[1] = \<const0> ;
  assign rxpolarity_usp_in[0] = \<const0> ;
  assign rxprbscntreset_us_in[1] = \<const0> ;
  assign rxprbscntreset_us_in[0] = \<const0> ;
  assign rxprbscntreset_usp_in[1] = \<const0> ;
  assign rxprbscntreset_usp_in[0] = \<const0> ;
  assign rxprbssel_us_in[7] = \<const0> ;
  assign rxprbssel_us_in[6] = \<const0> ;
  assign rxprbssel_us_in[5] = \<const0> ;
  assign rxprbssel_us_in[4] = \<const0> ;
  assign rxprbssel_us_in[3] = \<const0> ;
  assign rxprbssel_us_in[2] = \<const0> ;
  assign rxprbssel_us_in[1] = \<const0> ;
  assign rxprbssel_us_in[0] = \<const0> ;
  assign rxprbssel_usp_in[7] = \<const0> ;
  assign rxprbssel_usp_in[6] = \<const0> ;
  assign rxprbssel_usp_in[5] = \<const0> ;
  assign rxprbssel_usp_in[4] = \<const0> ;
  assign rxprbssel_usp_in[3] = \<const0> ;
  assign rxprbssel_usp_in[2] = \<const0> ;
  assign rxprbssel_usp_in[1] = \<const0> ;
  assign rxprbssel_usp_in[0] = \<const0> ;
  assign rxprogdivreset_us_in[1] = \<const0> ;
  assign rxprogdivreset_us_in[0] = \<const0> ;
  assign rxprogdivreset_usp_in[1] = \<const0> ;
  assign rxprogdivreset_usp_in[0] = \<const0> ;
  assign rxrate_us_in[5] = \<const0> ;
  assign rxrate_us_in[4] = \<const0> ;
  assign rxrate_us_in[3] = \<const0> ;
  assign rxrate_us_in[2] = \<const0> ;
  assign rxrate_us_in[1] = \<const0> ;
  assign rxrate_us_in[0] = \<const0> ;
  assign rxrate_usp_in[5] = \<const0> ;
  assign rxrate_usp_in[4] = \<const0> ;
  assign rxrate_usp_in[3] = \<const0> ;
  assign rxrate_usp_in[2] = \<const0> ;
  assign rxrate_usp_in[1] = \<const0> ;
  assign rxrate_usp_in[0] = \<const0> ;
  assign rxratemode_us_in[1] = \<const0> ;
  assign rxratemode_us_in[0] = \<const0> ;
  assign rxratemode_usp_in[1] = \<const0> ;
  assign rxratemode_usp_in[0] = \<const0> ;
  assign rxslide_us_in[1] = \<const0> ;
  assign rxslide_us_in[0] = \<const0> ;
  assign rxslide_usp_in[1] = \<const0> ;
  assign rxslide_usp_in[0] = \<const0> ;
  assign rxtermination_usp_in[1] = \<const0> ;
  assign rxtermination_usp_in[0] = \<const0> ;
  assign rxuserrdy_us_in[1] = \<const0> ;
  assign rxuserrdy_us_in[0] = \<const0> ;
  assign rxuserrdy_usp_in[1] = \<const0> ;
  assign rxuserrdy_usp_in[0] = \<const0> ;
  assign rxusrclk2_us_in[1] = \<const0> ;
  assign rxusrclk2_us_in[0] = \<const0> ;
  assign rxusrclk2_usp_in[1] = \<const0> ;
  assign rxusrclk2_usp_in[0] = \<const0> ;
  assign rxusrclk_us_in[1] = \<const0> ;
  assign rxusrclk_us_in[0] = \<const0> ;
  assign rxusrclk_usp_in[1] = \<const0> ;
  assign rxusrclk_usp_in[0] = \<const0> ;
  assign s_axi_arready = \<const0> ;
  assign s_axi_awready = \<const0> ;
  assign s_axi_bid[15] = \<const0> ;
  assign s_axi_bid[14] = \<const0> ;
  assign s_axi_bid[13] = \<const0> ;
  assign s_axi_bid[12] = \<const0> ;
  assign s_axi_bid[11] = \<const0> ;
  assign s_axi_bid[10] = \<const0> ;
  assign s_axi_bid[9] = \<const0> ;
  assign s_axi_bid[8] = \<const0> ;
  assign s_axi_bid[7] = \<const0> ;
  assign s_axi_bid[6] = \<const0> ;
  assign s_axi_bid[5] = \<const0> ;
  assign s_axi_bid[4] = \<const0> ;
  assign s_axi_bid[3] = \<const0> ;
  assign s_axi_bid[2] = \<const0> ;
  assign s_axi_bid[1] = \<const0> ;
  assign s_axi_bid[0] = \<const0> ;
  assign s_axi_bresp[1] = \<const0> ;
  assign s_axi_bresp[0] = \<const0> ;
  assign s_axi_bvalid = \<const0> ;
  assign s_axi_rdata[31] = \<const0> ;
  assign s_axi_rdata[30] = \<const0> ;
  assign s_axi_rdata[29] = \<const0> ;
  assign s_axi_rdata[28] = \<const0> ;
  assign s_axi_rdata[27] = \<const0> ;
  assign s_axi_rdata[26] = \<const0> ;
  assign s_axi_rdata[25] = \<const0> ;
  assign s_axi_rdata[24] = \<const0> ;
  assign s_axi_rdata[23] = \<const0> ;
  assign s_axi_rdata[22] = \<const0> ;
  assign s_axi_rdata[21] = \<const0> ;
  assign s_axi_rdata[20] = \<const0> ;
  assign s_axi_rdata[19] = \<const0> ;
  assign s_axi_rdata[18] = \<const0> ;
  assign s_axi_rdata[17] = \<const0> ;
  assign s_axi_rdata[16] = \<const0> ;
  assign s_axi_rdata[15] = \<const0> ;
  assign s_axi_rdata[14] = \<const0> ;
  assign s_axi_rdata[13] = \<const0> ;
  assign s_axi_rdata[12] = \<const0> ;
  assign s_axi_rdata[11] = \<const0> ;
  assign s_axi_rdata[10] = \<const0> ;
  assign s_axi_rdata[9] = \<const0> ;
  assign s_axi_rdata[8] = \<const0> ;
  assign s_axi_rdata[7] = \<const0> ;
  assign s_axi_rdata[6] = \<const0> ;
  assign s_axi_rdata[5] = \<const0> ;
  assign s_axi_rdata[4] = \<const0> ;
  assign s_axi_rdata[3] = \<const0> ;
  assign s_axi_rdata[2] = \<const0> ;
  assign s_axi_rdata[1] = \<const0> ;
  assign s_axi_rdata[0] = \<const0> ;
  assign s_axi_rid[15] = \<const0> ;
  assign s_axi_rid[14] = \<const0> ;
  assign s_axi_rid[13] = \<const0> ;
  assign s_axi_rid[12] = \<const0> ;
  assign s_axi_rid[11] = \<const0> ;
  assign s_axi_rid[10] = \<const0> ;
  assign s_axi_rid[9] = \<const0> ;
  assign s_axi_rid[8] = \<const0> ;
  assign s_axi_rid[7] = \<const0> ;
  assign s_axi_rid[6] = \<const0> ;
  assign s_axi_rid[5] = \<const0> ;
  assign s_axi_rid[4] = \<const0> ;
  assign s_axi_rid[3] = \<const0> ;
  assign s_axi_rid[2] = \<const0> ;
  assign s_axi_rid[1] = \<const0> ;
  assign s_axi_rid[0] = \<const0> ;
  assign s_axi_rlast = \<const0> ;
  assign s_axi_rresp[1] = \<const0> ;
  assign s_axi_rresp[0] = \<const0> ;
  assign s_axi_rvalid = \<const0> ;
  assign s_axi_wready = \<const0> ;
  assign s_axib_arready = \<const0> ;
  assign s_axib_awready = \<const0> ;
  assign s_axib_bid[3] = \<const0> ;
  assign s_axib_bid[2] = \<const0> ;
  assign s_axib_bid[1] = \<const0> ;
  assign s_axib_bid[0] = \<const0> ;
  assign s_axib_bresp[1] = \<const0> ;
  assign s_axib_bresp[0] = \<const0> ;
  assign s_axib_bvalid = \<const0> ;
  assign s_axib_rdata[63] = \<const0> ;
  assign s_axib_rdata[62] = \<const0> ;
  assign s_axib_rdata[61] = \<const0> ;
  assign s_axib_rdata[60] = \<const0> ;
  assign s_axib_rdata[59] = \<const0> ;
  assign s_axib_rdata[58] = \<const0> ;
  assign s_axib_rdata[57] = \<const0> ;
  assign s_axib_rdata[56] = \<const0> ;
  assign s_axib_rdata[55] = \<const0> ;
  assign s_axib_rdata[54] = \<const0> ;
  assign s_axib_rdata[53] = \<const0> ;
  assign s_axib_rdata[52] = \<const0> ;
  assign s_axib_rdata[51] = \<const0> ;
  assign s_axib_rdata[50] = \<const0> ;
  assign s_axib_rdata[49] = \<const0> ;
  assign s_axib_rdata[48] = \<const0> ;
  assign s_axib_rdata[47] = \<const0> ;
  assign s_axib_rdata[46] = \<const0> ;
  assign s_axib_rdata[45] = \<const0> ;
  assign s_axib_rdata[44] = \<const0> ;
  assign s_axib_rdata[43] = \<const0> ;
  assign s_axib_rdata[42] = \<const0> ;
  assign s_axib_rdata[41] = \<const0> ;
  assign s_axib_rdata[40] = \<const0> ;
  assign s_axib_rdata[39] = \<const0> ;
  assign s_axib_rdata[38] = \<const0> ;
  assign s_axib_rdata[37] = \<const0> ;
  assign s_axib_rdata[36] = \<const0> ;
  assign s_axib_rdata[35] = \<const0> ;
  assign s_axib_rdata[34] = \<const0> ;
  assign s_axib_rdata[33] = \<const0> ;
  assign s_axib_rdata[32] = \<const0> ;
  assign s_axib_rdata[31] = \<const0> ;
  assign s_axib_rdata[30] = \<const0> ;
  assign s_axib_rdata[29] = \<const0> ;
  assign s_axib_rdata[28] = \<const0> ;
  assign s_axib_rdata[27] = \<const0> ;
  assign s_axib_rdata[26] = \<const0> ;
  assign s_axib_rdata[25] = \<const0> ;
  assign s_axib_rdata[24] = \<const0> ;
  assign s_axib_rdata[23] = \<const0> ;
  assign s_axib_rdata[22] = \<const0> ;
  assign s_axib_rdata[21] = \<const0> ;
  assign s_axib_rdata[20] = \<const0> ;
  assign s_axib_rdata[19] = \<const0> ;
  assign s_axib_rdata[18] = \<const0> ;
  assign s_axib_rdata[17] = \<const0> ;
  assign s_axib_rdata[16] = \<const0> ;
  assign s_axib_rdata[15] = \<const0> ;
  assign s_axib_rdata[14] = \<const0> ;
  assign s_axib_rdata[13] = \<const0> ;
  assign s_axib_rdata[12] = \<const0> ;
  assign s_axib_rdata[11] = \<const0> ;
  assign s_axib_rdata[10] = \<const0> ;
  assign s_axib_rdata[9] = \<const0> ;
  assign s_axib_rdata[8] = \<const0> ;
  assign s_axib_rdata[7] = \<const0> ;
  assign s_axib_rdata[6] = \<const0> ;
  assign s_axib_rdata[5] = \<const0> ;
  assign s_axib_rdata[4] = \<const0> ;
  assign s_axib_rdata[3] = \<const0> ;
  assign s_axib_rdata[2] = \<const0> ;
  assign s_axib_rdata[1] = \<const0> ;
  assign s_axib_rdata[0] = \<const0> ;
  assign s_axib_rid[3] = \<const0> ;
  assign s_axib_rid[2] = \<const0> ;
  assign s_axib_rid[1] = \<const0> ;
  assign s_axib_rid[0] = \<const0> ;
  assign s_axib_rlast = \<const0> ;
  assign s_axib_rresp[1] = \<const0> ;
  assign s_axib_rresp[0] = \<const0> ;
  assign s_axib_ruser[7] = \<const0> ;
  assign s_axib_ruser[6] = \<const0> ;
  assign s_axib_ruser[5] = \<const0> ;
  assign s_axib_ruser[4] = \<const0> ;
  assign s_axib_ruser[3] = \<const0> ;
  assign s_axib_ruser[2] = \<const0> ;
  assign s_axib_ruser[1] = \<const0> ;
  assign s_axib_ruser[0] = \<const0> ;
  assign s_axib_rvalid = \<const0> ;
  assign s_axib_wready = \<const0> ;
  assign s_axil_arready = \<const0> ;
  assign s_axil_awready = \<const0> ;
  assign s_axil_bresp[1] = \<const0> ;
  assign s_axil_bresp[0] = \<const0> ;
  assign s_axil_bvalid = \<const0> ;
  assign s_axil_rdata[31] = \<const0> ;
  assign s_axil_rdata[30] = \<const0> ;
  assign s_axil_rdata[29] = \<const0> ;
  assign s_axil_rdata[28] = \<const0> ;
  assign s_axil_rdata[27] = \<const0> ;
  assign s_axil_rdata[26] = \<const0> ;
  assign s_axil_rdata[25] = \<const0> ;
  assign s_axil_rdata[24] = \<const0> ;
  assign s_axil_rdata[23] = \<const0> ;
  assign s_axil_rdata[22] = \<const0> ;
  assign s_axil_rdata[21] = \<const0> ;
  assign s_axil_rdata[20] = \<const0> ;
  assign s_axil_rdata[19] = \<const0> ;
  assign s_axil_rdata[18] = \<const0> ;
  assign s_axil_rdata[17] = \<const0> ;
  assign s_axil_rdata[16] = \<const0> ;
  assign s_axil_rdata[15] = \<const0> ;
  assign s_axil_rdata[14] = \<const0> ;
  assign s_axil_rdata[13] = \<const0> ;
  assign s_axil_rdata[12] = \<const0> ;
  assign s_axil_rdata[11] = \<const0> ;
  assign s_axil_rdata[10] = \<const0> ;
  assign s_axil_rdata[9] = \<const0> ;
  assign s_axil_rdata[8] = \<const0> ;
  assign s_axil_rdata[7] = \<const0> ;
  assign s_axil_rdata[6] = \<const0> ;
  assign s_axil_rdata[5] = \<const0> ;
  assign s_axil_rdata[4] = \<const0> ;
  assign s_axil_rdata[3] = \<const0> ;
  assign s_axil_rdata[2] = \<const0> ;
  assign s_axil_rdata[1] = \<const0> ;
  assign s_axil_rdata[0] = \<const0> ;
  assign s_axil_rresp[1] = \<const0> ;
  assign s_axil_rresp[0] = \<const0> ;
  assign s_axil_rvalid = \<const0> ;
  assign s_axil_wready = \<const0> ;
  assign s_axis_c2h_tready_0 = \<const0> ;
  assign s_axis_c2h_tready_1 = \<const0> ;
  assign s_axis_c2h_tready_2 = \<const0> ;
  assign s_axis_c2h_tready_3 = \<const0> ;
  assign s_axis_cc_tdata_sd[63] = \<const0> ;
  assign s_axis_cc_tdata_sd[62] = \<const0> ;
  assign s_axis_cc_tdata_sd[61] = \<const0> ;
  assign s_axis_cc_tdata_sd[60] = \<const0> ;
  assign s_axis_cc_tdata_sd[59] = \<const0> ;
  assign s_axis_cc_tdata_sd[58] = \<const0> ;
  assign s_axis_cc_tdata_sd[57] = \<const0> ;
  assign s_axis_cc_tdata_sd[56] = \<const0> ;
  assign s_axis_cc_tdata_sd[55] = \<const0> ;
  assign s_axis_cc_tdata_sd[54] = \<const0> ;
  assign s_axis_cc_tdata_sd[53] = \<const0> ;
  assign s_axis_cc_tdata_sd[52] = \<const0> ;
  assign s_axis_cc_tdata_sd[51] = \<const0> ;
  assign s_axis_cc_tdata_sd[50] = \<const0> ;
  assign s_axis_cc_tdata_sd[49] = \<const0> ;
  assign s_axis_cc_tdata_sd[48] = \<const0> ;
  assign s_axis_cc_tdata_sd[47] = \<const0> ;
  assign s_axis_cc_tdata_sd[46] = \<const0> ;
  assign s_axis_cc_tdata_sd[45] = \<const0> ;
  assign s_axis_cc_tdata_sd[44] = \<const0> ;
  assign s_axis_cc_tdata_sd[43] = \<const0> ;
  assign s_axis_cc_tdata_sd[42] = \<const0> ;
  assign s_axis_cc_tdata_sd[41] = \<const0> ;
  assign s_axis_cc_tdata_sd[40] = \<const0> ;
  assign s_axis_cc_tdata_sd[39] = \<const0> ;
  assign s_axis_cc_tdata_sd[38] = \<const0> ;
  assign s_axis_cc_tdata_sd[37] = \<const0> ;
  assign s_axis_cc_tdata_sd[36] = \<const0> ;
  assign s_axis_cc_tdata_sd[35] = \<const0> ;
  assign s_axis_cc_tdata_sd[34] = \<const0> ;
  assign s_axis_cc_tdata_sd[33] = \<const0> ;
  assign s_axis_cc_tdata_sd[32] = \<const0> ;
  assign s_axis_cc_tdata_sd[31] = \<const0> ;
  assign s_axis_cc_tdata_sd[30] = \<const0> ;
  assign s_axis_cc_tdata_sd[29] = \<const0> ;
  assign s_axis_cc_tdata_sd[28] = \<const0> ;
  assign s_axis_cc_tdata_sd[27] = \<const0> ;
  assign s_axis_cc_tdata_sd[26] = \<const0> ;
  assign s_axis_cc_tdata_sd[25] = \<const0> ;
  assign s_axis_cc_tdata_sd[24] = \<const0> ;
  assign s_axis_cc_tdata_sd[23] = \<const0> ;
  assign s_axis_cc_tdata_sd[22] = \<const0> ;
  assign s_axis_cc_tdata_sd[21] = \<const0> ;
  assign s_axis_cc_tdata_sd[20] = \<const0> ;
  assign s_axis_cc_tdata_sd[19] = \<const0> ;
  assign s_axis_cc_tdata_sd[18] = \<const0> ;
  assign s_axis_cc_tdata_sd[17] = \<const0> ;
  assign s_axis_cc_tdata_sd[16] = \<const0> ;
  assign s_axis_cc_tdata_sd[15] = \<const0> ;
  assign s_axis_cc_tdata_sd[14] = \<const0> ;
  assign s_axis_cc_tdata_sd[13] = \<const0> ;
  assign s_axis_cc_tdata_sd[12] = \<const0> ;
  assign s_axis_cc_tdata_sd[11] = \<const0> ;
  assign s_axis_cc_tdata_sd[10] = \<const0> ;
  assign s_axis_cc_tdata_sd[9] = \<const0> ;
  assign s_axis_cc_tdata_sd[8] = \<const0> ;
  assign s_axis_cc_tdata_sd[7] = \<const0> ;
  assign s_axis_cc_tdata_sd[6] = \<const0> ;
  assign s_axis_cc_tdata_sd[5] = \<const0> ;
  assign s_axis_cc_tdata_sd[4] = \<const0> ;
  assign s_axis_cc_tdata_sd[3] = \<const0> ;
  assign s_axis_cc_tdata_sd[2] = \<const0> ;
  assign s_axis_cc_tdata_sd[1] = \<const0> ;
  assign s_axis_cc_tdata_sd[0] = \<const0> ;
  assign s_axis_cc_tkeep_sd[1] = \<const0> ;
  assign s_axis_cc_tkeep_sd[0] = \<const0> ;
  assign s_axis_cc_tlast_sd = \<const0> ;
  assign s_axis_cc_tuser_sd[32] = \<const0> ;
  assign s_axis_cc_tuser_sd[31] = \<const0> ;
  assign s_axis_cc_tuser_sd[30] = \<const0> ;
  assign s_axis_cc_tuser_sd[29] = \<const0> ;
  assign s_axis_cc_tuser_sd[28] = \<const0> ;
  assign s_axis_cc_tuser_sd[27] = \<const0> ;
  assign s_axis_cc_tuser_sd[26] = \<const0> ;
  assign s_axis_cc_tuser_sd[25] = \<const0> ;
  assign s_axis_cc_tuser_sd[24] = \<const0> ;
  assign s_axis_cc_tuser_sd[23] = \<const0> ;
  assign s_axis_cc_tuser_sd[22] = \<const0> ;
  assign s_axis_cc_tuser_sd[21] = \<const0> ;
  assign s_axis_cc_tuser_sd[20] = \<const0> ;
  assign s_axis_cc_tuser_sd[19] = \<const0> ;
  assign s_axis_cc_tuser_sd[18] = \<const0> ;
  assign s_axis_cc_tuser_sd[17] = \<const0> ;
  assign s_axis_cc_tuser_sd[16] = \<const0> ;
  assign s_axis_cc_tuser_sd[15] = \<const0> ;
  assign s_axis_cc_tuser_sd[14] = \<const0> ;
  assign s_axis_cc_tuser_sd[13] = \<const0> ;
  assign s_axis_cc_tuser_sd[12] = \<const0> ;
  assign s_axis_cc_tuser_sd[11] = \<const0> ;
  assign s_axis_cc_tuser_sd[10] = \<const0> ;
  assign s_axis_cc_tuser_sd[9] = \<const0> ;
  assign s_axis_cc_tuser_sd[8] = \<const0> ;
  assign s_axis_cc_tuser_sd[7] = \<const0> ;
  assign s_axis_cc_tuser_sd[6] = \<const0> ;
  assign s_axis_cc_tuser_sd[5] = \<const0> ;
  assign s_axis_cc_tuser_sd[4] = \<const0> ;
  assign s_axis_cc_tuser_sd[3] = \<const0> ;
  assign s_axis_cc_tuser_sd[2] = \<const0> ;
  assign s_axis_cc_tuser_sd[1] = \<const0> ;
  assign s_axis_cc_tuser_sd[0] = \<const0> ;
  assign s_axis_cc_tvalid_sd = \<const0> ;
  assign s_axis_cq_tdata_out[63] = \<const0> ;
  assign s_axis_cq_tdata_out[62] = \<const0> ;
  assign s_axis_cq_tdata_out[61] = \<const0> ;
  assign s_axis_cq_tdata_out[60] = \<const0> ;
  assign s_axis_cq_tdata_out[59] = \<const0> ;
  assign s_axis_cq_tdata_out[58] = \<const0> ;
  assign s_axis_cq_tdata_out[57] = \<const0> ;
  assign s_axis_cq_tdata_out[56] = \<const0> ;
  assign s_axis_cq_tdata_out[55] = \<const0> ;
  assign s_axis_cq_tdata_out[54] = \<const0> ;
  assign s_axis_cq_tdata_out[53] = \<const0> ;
  assign s_axis_cq_tdata_out[52] = \<const0> ;
  assign s_axis_cq_tdata_out[51] = \<const0> ;
  assign s_axis_cq_tdata_out[50] = \<const0> ;
  assign s_axis_cq_tdata_out[49] = \<const0> ;
  assign s_axis_cq_tdata_out[48] = \<const0> ;
  assign s_axis_cq_tdata_out[47] = \<const0> ;
  assign s_axis_cq_tdata_out[46] = \<const0> ;
  assign s_axis_cq_tdata_out[45] = \<const0> ;
  assign s_axis_cq_tdata_out[44] = \<const0> ;
  assign s_axis_cq_tdata_out[43] = \<const0> ;
  assign s_axis_cq_tdata_out[42] = \<const0> ;
  assign s_axis_cq_tdata_out[41] = \<const0> ;
  assign s_axis_cq_tdata_out[40] = \<const0> ;
  assign s_axis_cq_tdata_out[39] = \<const0> ;
  assign s_axis_cq_tdata_out[38] = \<const0> ;
  assign s_axis_cq_tdata_out[37] = \<const0> ;
  assign s_axis_cq_tdata_out[36] = \<const0> ;
  assign s_axis_cq_tdata_out[35] = \<const0> ;
  assign s_axis_cq_tdata_out[34] = \<const0> ;
  assign s_axis_cq_tdata_out[33] = \<const0> ;
  assign s_axis_cq_tdata_out[32] = \<const0> ;
  assign s_axis_cq_tdata_out[31] = \<const0> ;
  assign s_axis_cq_tdata_out[30] = \<const0> ;
  assign s_axis_cq_tdata_out[29] = \<const0> ;
  assign s_axis_cq_tdata_out[28] = \<const0> ;
  assign s_axis_cq_tdata_out[27] = \<const0> ;
  assign s_axis_cq_tdata_out[26] = \<const0> ;
  assign s_axis_cq_tdata_out[25] = \<const0> ;
  assign s_axis_cq_tdata_out[24] = \<const0> ;
  assign s_axis_cq_tdata_out[23] = \<const0> ;
  assign s_axis_cq_tdata_out[22] = \<const0> ;
  assign s_axis_cq_tdata_out[21] = \<const0> ;
  assign s_axis_cq_tdata_out[20] = \<const0> ;
  assign s_axis_cq_tdata_out[19] = \<const0> ;
  assign s_axis_cq_tdata_out[18] = \<const0> ;
  assign s_axis_cq_tdata_out[17] = \<const0> ;
  assign s_axis_cq_tdata_out[16] = \<const0> ;
  assign s_axis_cq_tdata_out[15] = \<const0> ;
  assign s_axis_cq_tdata_out[14] = \<const0> ;
  assign s_axis_cq_tdata_out[13] = \<const0> ;
  assign s_axis_cq_tdata_out[12] = \<const0> ;
  assign s_axis_cq_tdata_out[11] = \<const0> ;
  assign s_axis_cq_tdata_out[10] = \<const0> ;
  assign s_axis_cq_tdata_out[9] = \<const0> ;
  assign s_axis_cq_tdata_out[8] = \<const0> ;
  assign s_axis_cq_tdata_out[7] = \<const0> ;
  assign s_axis_cq_tdata_out[6] = \<const0> ;
  assign s_axis_cq_tdata_out[5] = \<const0> ;
  assign s_axis_cq_tdata_out[4] = \<const0> ;
  assign s_axis_cq_tdata_out[3] = \<const0> ;
  assign s_axis_cq_tdata_out[2] = \<const0> ;
  assign s_axis_cq_tdata_out[1] = \<const0> ;
  assign s_axis_cq_tdata_out[0] = \<const0> ;
  assign s_axis_cq_tkeep_out[1] = \<const0> ;
  assign s_axis_cq_tkeep_out[0] = \<const0> ;
  assign s_axis_cq_tlast_out = \<const0> ;
  assign s_axis_cq_tready_out = \<const0> ;
  assign s_axis_cq_tuser_out[84] = \<const0> ;
  assign s_axis_cq_tuser_out[83] = \<const0> ;
  assign s_axis_cq_tuser_out[82] = \<const0> ;
  assign s_axis_cq_tuser_out[81] = \<const0> ;
  assign s_axis_cq_tuser_out[80] = \<const0> ;
  assign s_axis_cq_tuser_out[79] = \<const0> ;
  assign s_axis_cq_tuser_out[78] = \<const0> ;
  assign s_axis_cq_tuser_out[77] = \<const0> ;
  assign s_axis_cq_tuser_out[76] = \<const0> ;
  assign s_axis_cq_tuser_out[75] = \<const0> ;
  assign s_axis_cq_tuser_out[74] = \<const0> ;
  assign s_axis_cq_tuser_out[73] = \<const0> ;
  assign s_axis_cq_tuser_out[72] = \<const0> ;
  assign s_axis_cq_tuser_out[71] = \<const0> ;
  assign s_axis_cq_tuser_out[70] = \<const0> ;
  assign s_axis_cq_tuser_out[69] = \<const0> ;
  assign s_axis_cq_tuser_out[68] = \<const0> ;
  assign s_axis_cq_tuser_out[67] = \<const0> ;
  assign s_axis_cq_tuser_out[66] = \<const0> ;
  assign s_axis_cq_tuser_out[65] = \<const0> ;
  assign s_axis_cq_tuser_out[64] = \<const0> ;
  assign s_axis_cq_tuser_out[63] = \<const0> ;
  assign s_axis_cq_tuser_out[62] = \<const0> ;
  assign s_axis_cq_tuser_out[61] = \<const0> ;
  assign s_axis_cq_tuser_out[60] = \<const0> ;
  assign s_axis_cq_tuser_out[59] = \<const0> ;
  assign s_axis_cq_tuser_out[58] = \<const0> ;
  assign s_axis_cq_tuser_out[57] = \<const0> ;
  assign s_axis_cq_tuser_out[56] = \<const0> ;
  assign s_axis_cq_tuser_out[55] = \<const0> ;
  assign s_axis_cq_tuser_out[54] = \<const0> ;
  assign s_axis_cq_tuser_out[53] = \<const0> ;
  assign s_axis_cq_tuser_out[52] = \<const0> ;
  assign s_axis_cq_tuser_out[51] = \<const0> ;
  assign s_axis_cq_tuser_out[50] = \<const0> ;
  assign s_axis_cq_tuser_out[49] = \<const0> ;
  assign s_axis_cq_tuser_out[48] = \<const0> ;
  assign s_axis_cq_tuser_out[47] = \<const0> ;
  assign s_axis_cq_tuser_out[46] = \<const0> ;
  assign s_axis_cq_tuser_out[45] = \<const0> ;
  assign s_axis_cq_tuser_out[44] = \<const0> ;
  assign s_axis_cq_tuser_out[43] = \<const0> ;
  assign s_axis_cq_tuser_out[42] = \<const0> ;
  assign s_axis_cq_tuser_out[41] = \<const0> ;
  assign s_axis_cq_tuser_out[40] = \<const0> ;
  assign s_axis_cq_tuser_out[39] = \<const0> ;
  assign s_axis_cq_tuser_out[38] = \<const0> ;
  assign s_axis_cq_tuser_out[37] = \<const0> ;
  assign s_axis_cq_tuser_out[36] = \<const0> ;
  assign s_axis_cq_tuser_out[35] = \<const0> ;
  assign s_axis_cq_tuser_out[34] = \<const0> ;
  assign s_axis_cq_tuser_out[33] = \<const0> ;
  assign s_axis_cq_tuser_out[32] = \<const0> ;
  assign s_axis_cq_tuser_out[31] = \<const0> ;
  assign s_axis_cq_tuser_out[30] = \<const0> ;
  assign s_axis_cq_tuser_out[29] = \<const0> ;
  assign s_axis_cq_tuser_out[28] = \<const0> ;
  assign s_axis_cq_tuser_out[27] = \<const0> ;
  assign s_axis_cq_tuser_out[26] = \<const0> ;
  assign s_axis_cq_tuser_out[25] = \<const0> ;
  assign s_axis_cq_tuser_out[24] = \<const0> ;
  assign s_axis_cq_tuser_out[23] = \<const0> ;
  assign s_axis_cq_tuser_out[22] = \<const0> ;
  assign s_axis_cq_tuser_out[21] = \<const0> ;
  assign s_axis_cq_tuser_out[20] = \<const0> ;
  assign s_axis_cq_tuser_out[19] = \<const0> ;
  assign s_axis_cq_tuser_out[18] = \<const0> ;
  assign s_axis_cq_tuser_out[17] = \<const0> ;
  assign s_axis_cq_tuser_out[16] = \<const0> ;
  assign s_axis_cq_tuser_out[15] = \<const0> ;
  assign s_axis_cq_tuser_out[14] = \<const0> ;
  assign s_axis_cq_tuser_out[13] = \<const0> ;
  assign s_axis_cq_tuser_out[12] = \<const0> ;
  assign s_axis_cq_tuser_out[11] = \<const0> ;
  assign s_axis_cq_tuser_out[10] = \<const0> ;
  assign s_axis_cq_tuser_out[9] = \<const0> ;
  assign s_axis_cq_tuser_out[8] = \<const0> ;
  assign s_axis_cq_tuser_out[7] = \<const0> ;
  assign s_axis_cq_tuser_out[6] = \<const0> ;
  assign s_axis_cq_tuser_out[5] = \<const0> ;
  assign s_axis_cq_tuser_out[4] = \<const0> ;
  assign s_axis_cq_tuser_out[3] = \<const0> ;
  assign s_axis_cq_tuser_out[2] = \<const0> ;
  assign s_axis_cq_tuser_out[1] = \<const0> ;
  assign s_axis_cq_tuser_out[0] = \<const0> ;
  assign s_axis_cq_tvalid_out = \<const0> ;
  assign s_axis_rc_tdata_out[63] = \<const0> ;
  assign s_axis_rc_tdata_out[62] = \<const0> ;
  assign s_axis_rc_tdata_out[61] = \<const0> ;
  assign s_axis_rc_tdata_out[60] = \<const0> ;
  assign s_axis_rc_tdata_out[59] = \<const0> ;
  assign s_axis_rc_tdata_out[58] = \<const0> ;
  assign s_axis_rc_tdata_out[57] = \<const0> ;
  assign s_axis_rc_tdata_out[56] = \<const0> ;
  assign s_axis_rc_tdata_out[55] = \<const0> ;
  assign s_axis_rc_tdata_out[54] = \<const0> ;
  assign s_axis_rc_tdata_out[53] = \<const0> ;
  assign s_axis_rc_tdata_out[52] = \<const0> ;
  assign s_axis_rc_tdata_out[51] = \<const0> ;
  assign s_axis_rc_tdata_out[50] = \<const0> ;
  assign s_axis_rc_tdata_out[49] = \<const0> ;
  assign s_axis_rc_tdata_out[48] = \<const0> ;
  assign s_axis_rc_tdata_out[47] = \<const0> ;
  assign s_axis_rc_tdata_out[46] = \<const0> ;
  assign s_axis_rc_tdata_out[45] = \<const0> ;
  assign s_axis_rc_tdata_out[44] = \<const0> ;
  assign s_axis_rc_tdata_out[43] = \<const0> ;
  assign s_axis_rc_tdata_out[42] = \<const0> ;
  assign s_axis_rc_tdata_out[41] = \<const0> ;
  assign s_axis_rc_tdata_out[40] = \<const0> ;
  assign s_axis_rc_tdata_out[39] = \<const0> ;
  assign s_axis_rc_tdata_out[38] = \<const0> ;
  assign s_axis_rc_tdata_out[37] = \<const0> ;
  assign s_axis_rc_tdata_out[36] = \<const0> ;
  assign s_axis_rc_tdata_out[35] = \<const0> ;
  assign s_axis_rc_tdata_out[34] = \<const0> ;
  assign s_axis_rc_tdata_out[33] = \<const0> ;
  assign s_axis_rc_tdata_out[32] = \<const0> ;
  assign s_axis_rc_tdata_out[31] = \<const0> ;
  assign s_axis_rc_tdata_out[30] = \<const0> ;
  assign s_axis_rc_tdata_out[29] = \<const0> ;
  assign s_axis_rc_tdata_out[28] = \<const0> ;
  assign s_axis_rc_tdata_out[27] = \<const0> ;
  assign s_axis_rc_tdata_out[26] = \<const0> ;
  assign s_axis_rc_tdata_out[25] = \<const0> ;
  assign s_axis_rc_tdata_out[24] = \<const0> ;
  assign s_axis_rc_tdata_out[23] = \<const0> ;
  assign s_axis_rc_tdata_out[22] = \<const0> ;
  assign s_axis_rc_tdata_out[21] = \<const0> ;
  assign s_axis_rc_tdata_out[20] = \<const0> ;
  assign s_axis_rc_tdata_out[19] = \<const0> ;
  assign s_axis_rc_tdata_out[18] = \<const0> ;
  assign s_axis_rc_tdata_out[17] = \<const0> ;
  assign s_axis_rc_tdata_out[16] = \<const0> ;
  assign s_axis_rc_tdata_out[15] = \<const0> ;
  assign s_axis_rc_tdata_out[14] = \<const0> ;
  assign s_axis_rc_tdata_out[13] = \<const0> ;
  assign s_axis_rc_tdata_out[12] = \<const0> ;
  assign s_axis_rc_tdata_out[11] = \<const0> ;
  assign s_axis_rc_tdata_out[10] = \<const0> ;
  assign s_axis_rc_tdata_out[9] = \<const0> ;
  assign s_axis_rc_tdata_out[8] = \<const0> ;
  assign s_axis_rc_tdata_out[7] = \<const0> ;
  assign s_axis_rc_tdata_out[6] = \<const0> ;
  assign s_axis_rc_tdata_out[5] = \<const0> ;
  assign s_axis_rc_tdata_out[4] = \<const0> ;
  assign s_axis_rc_tdata_out[3] = \<const0> ;
  assign s_axis_rc_tdata_out[2] = \<const0> ;
  assign s_axis_rc_tdata_out[1] = \<const0> ;
  assign s_axis_rc_tdata_out[0] = \<const0> ;
  assign s_axis_rc_tkeep_out[1] = \<const0> ;
  assign s_axis_rc_tkeep_out[0] = \<const0> ;
  assign s_axis_rc_tlast_out = \<const0> ;
  assign s_axis_rc_tready_out = \<const0> ;
  assign s_axis_rc_tuser_out[74] = \<const0> ;
  assign s_axis_rc_tuser_out[73] = \<const0> ;
  assign s_axis_rc_tuser_out[72] = \<const0> ;
  assign s_axis_rc_tuser_out[71] = \<const0> ;
  assign s_axis_rc_tuser_out[70] = \<const0> ;
  assign s_axis_rc_tuser_out[69] = \<const0> ;
  assign s_axis_rc_tuser_out[68] = \<const0> ;
  assign s_axis_rc_tuser_out[67] = \<const0> ;
  assign s_axis_rc_tuser_out[66] = \<const0> ;
  assign s_axis_rc_tuser_out[65] = \<const0> ;
  assign s_axis_rc_tuser_out[64] = \<const0> ;
  assign s_axis_rc_tuser_out[63] = \<const0> ;
  assign s_axis_rc_tuser_out[62] = \<const0> ;
  assign s_axis_rc_tuser_out[61] = \<const0> ;
  assign s_axis_rc_tuser_out[60] = \<const0> ;
  assign s_axis_rc_tuser_out[59] = \<const0> ;
  assign s_axis_rc_tuser_out[58] = \<const0> ;
  assign s_axis_rc_tuser_out[57] = \<const0> ;
  assign s_axis_rc_tuser_out[56] = \<const0> ;
  assign s_axis_rc_tuser_out[55] = \<const0> ;
  assign s_axis_rc_tuser_out[54] = \<const0> ;
  assign s_axis_rc_tuser_out[53] = \<const0> ;
  assign s_axis_rc_tuser_out[52] = \<const0> ;
  assign s_axis_rc_tuser_out[51] = \<const0> ;
  assign s_axis_rc_tuser_out[50] = \<const0> ;
  assign s_axis_rc_tuser_out[49] = \<const0> ;
  assign s_axis_rc_tuser_out[48] = \<const0> ;
  assign s_axis_rc_tuser_out[47] = \<const0> ;
  assign s_axis_rc_tuser_out[46] = \<const0> ;
  assign s_axis_rc_tuser_out[45] = \<const0> ;
  assign s_axis_rc_tuser_out[44] = \<const0> ;
  assign s_axis_rc_tuser_out[43] = \<const0> ;
  assign s_axis_rc_tuser_out[42] = \<const0> ;
  assign s_axis_rc_tuser_out[41] = \<const0> ;
  assign s_axis_rc_tuser_out[40] = \<const0> ;
  assign s_axis_rc_tuser_out[39] = \<const0> ;
  assign s_axis_rc_tuser_out[38] = \<const0> ;
  assign s_axis_rc_tuser_out[37] = \<const0> ;
  assign s_axis_rc_tuser_out[36] = \<const0> ;
  assign s_axis_rc_tuser_out[35] = \<const0> ;
  assign s_axis_rc_tuser_out[34] = \<const0> ;
  assign s_axis_rc_tuser_out[33] = \<const0> ;
  assign s_axis_rc_tuser_out[32] = \<const0> ;
  assign s_axis_rc_tuser_out[31] = \<const0> ;
  assign s_axis_rc_tuser_out[30] = \<const0> ;
  assign s_axis_rc_tuser_out[29] = \<const0> ;
  assign s_axis_rc_tuser_out[28] = \<const0> ;
  assign s_axis_rc_tuser_out[27] = \<const0> ;
  assign s_axis_rc_tuser_out[26] = \<const0> ;
  assign s_axis_rc_tuser_out[25] = \<const0> ;
  assign s_axis_rc_tuser_out[24] = \<const0> ;
  assign s_axis_rc_tuser_out[23] = \<const0> ;
  assign s_axis_rc_tuser_out[22] = \<const0> ;
  assign s_axis_rc_tuser_out[21] = \<const0> ;
  assign s_axis_rc_tuser_out[20] = \<const0> ;
  assign s_axis_rc_tuser_out[19] = \<const0> ;
  assign s_axis_rc_tuser_out[18] = \<const0> ;
  assign s_axis_rc_tuser_out[17] = \<const0> ;
  assign s_axis_rc_tuser_out[16] = \<const0> ;
  assign s_axis_rc_tuser_out[15] = \<const0> ;
  assign s_axis_rc_tuser_out[14] = \<const0> ;
  assign s_axis_rc_tuser_out[13] = \<const0> ;
  assign s_axis_rc_tuser_out[12] = \<const0> ;
  assign s_axis_rc_tuser_out[11] = \<const0> ;
  assign s_axis_rc_tuser_out[10] = \<const0> ;
  assign s_axis_rc_tuser_out[9] = \<const0> ;
  assign s_axis_rc_tuser_out[8] = \<const0> ;
  assign s_axis_rc_tuser_out[7] = \<const0> ;
  assign s_axis_rc_tuser_out[6] = \<const0> ;
  assign s_axis_rc_tuser_out[5] = \<const0> ;
  assign s_axis_rc_tuser_out[4] = \<const0> ;
  assign s_axis_rc_tuser_out[3] = \<const0> ;
  assign s_axis_rc_tuser_out[2] = \<const0> ;
  assign s_axis_rc_tuser_out[1] = \<const0> ;
  assign s_axis_rc_tuser_out[0] = \<const0> ;
  assign s_axis_rc_tvalid_out = \<const0> ;
  assign s_axis_rq_tdata_sd[63] = \<const0> ;
  assign s_axis_rq_tdata_sd[62] = \<const0> ;
  assign s_axis_rq_tdata_sd[61] = \<const0> ;
  assign s_axis_rq_tdata_sd[60] = \<const0> ;
  assign s_axis_rq_tdata_sd[59] = \<const0> ;
  assign s_axis_rq_tdata_sd[58] = \<const0> ;
  assign s_axis_rq_tdata_sd[57] = \<const0> ;
  assign s_axis_rq_tdata_sd[56] = \<const0> ;
  assign s_axis_rq_tdata_sd[55] = \<const0> ;
  assign s_axis_rq_tdata_sd[54] = \<const0> ;
  assign s_axis_rq_tdata_sd[53] = \<const0> ;
  assign s_axis_rq_tdata_sd[52] = \<const0> ;
  assign s_axis_rq_tdata_sd[51] = \<const0> ;
  assign s_axis_rq_tdata_sd[50] = \<const0> ;
  assign s_axis_rq_tdata_sd[49] = \<const0> ;
  assign s_axis_rq_tdata_sd[48] = \<const0> ;
  assign s_axis_rq_tdata_sd[47] = \<const0> ;
  assign s_axis_rq_tdata_sd[46] = \<const0> ;
  assign s_axis_rq_tdata_sd[45] = \<const0> ;
  assign s_axis_rq_tdata_sd[44] = \<const0> ;
  assign s_axis_rq_tdata_sd[43] = \<const0> ;
  assign s_axis_rq_tdata_sd[42] = \<const0> ;
  assign s_axis_rq_tdata_sd[41] = \<const0> ;
  assign s_axis_rq_tdata_sd[40] = \<const0> ;
  assign s_axis_rq_tdata_sd[39] = \<const0> ;
  assign s_axis_rq_tdata_sd[38] = \<const0> ;
  assign s_axis_rq_tdata_sd[37] = \<const0> ;
  assign s_axis_rq_tdata_sd[36] = \<const0> ;
  assign s_axis_rq_tdata_sd[35] = \<const0> ;
  assign s_axis_rq_tdata_sd[34] = \<const0> ;
  assign s_axis_rq_tdata_sd[33] = \<const0> ;
  assign s_axis_rq_tdata_sd[32] = \<const0> ;
  assign s_axis_rq_tdata_sd[31] = \<const0> ;
  assign s_axis_rq_tdata_sd[30] = \<const0> ;
  assign s_axis_rq_tdata_sd[29] = \<const0> ;
  assign s_axis_rq_tdata_sd[28] = \<const0> ;
  assign s_axis_rq_tdata_sd[27] = \<const0> ;
  assign s_axis_rq_tdata_sd[26] = \<const0> ;
  assign s_axis_rq_tdata_sd[25] = \<const0> ;
  assign s_axis_rq_tdata_sd[24] = \<const0> ;
  assign s_axis_rq_tdata_sd[23] = \<const0> ;
  assign s_axis_rq_tdata_sd[22] = \<const0> ;
  assign s_axis_rq_tdata_sd[21] = \<const0> ;
  assign s_axis_rq_tdata_sd[20] = \<const0> ;
  assign s_axis_rq_tdata_sd[19] = \<const0> ;
  assign s_axis_rq_tdata_sd[18] = \<const0> ;
  assign s_axis_rq_tdata_sd[17] = \<const0> ;
  assign s_axis_rq_tdata_sd[16] = \<const0> ;
  assign s_axis_rq_tdata_sd[15] = \<const0> ;
  assign s_axis_rq_tdata_sd[14] = \<const0> ;
  assign s_axis_rq_tdata_sd[13] = \<const0> ;
  assign s_axis_rq_tdata_sd[12] = \<const0> ;
  assign s_axis_rq_tdata_sd[11] = \<const0> ;
  assign s_axis_rq_tdata_sd[10] = \<const0> ;
  assign s_axis_rq_tdata_sd[9] = \<const0> ;
  assign s_axis_rq_tdata_sd[8] = \<const0> ;
  assign s_axis_rq_tdata_sd[7] = \<const0> ;
  assign s_axis_rq_tdata_sd[6] = \<const0> ;
  assign s_axis_rq_tdata_sd[5] = \<const0> ;
  assign s_axis_rq_tdata_sd[4] = \<const0> ;
  assign s_axis_rq_tdata_sd[3] = \<const0> ;
  assign s_axis_rq_tdata_sd[2] = \<const0> ;
  assign s_axis_rq_tdata_sd[1] = \<const0> ;
  assign s_axis_rq_tdata_sd[0] = \<const0> ;
  assign s_axis_rq_tkeep_sd[1] = \<const0> ;
  assign s_axis_rq_tkeep_sd[0] = \<const0> ;
  assign s_axis_rq_tlast_sd = \<const0> ;
  assign s_axis_rq_tuser_sd[59] = \<const0> ;
  assign s_axis_rq_tuser_sd[58] = \<const0> ;
  assign s_axis_rq_tuser_sd[57] = \<const0> ;
  assign s_axis_rq_tuser_sd[56] = \<const0> ;
  assign s_axis_rq_tuser_sd[55] = \<const0> ;
  assign s_axis_rq_tuser_sd[54] = \<const0> ;
  assign s_axis_rq_tuser_sd[53] = \<const0> ;
  assign s_axis_rq_tuser_sd[52] = \<const0> ;
  assign s_axis_rq_tuser_sd[51] = \<const0> ;
  assign s_axis_rq_tuser_sd[50] = \<const0> ;
  assign s_axis_rq_tuser_sd[49] = \<const0> ;
  assign s_axis_rq_tuser_sd[48] = \<const0> ;
  assign s_axis_rq_tuser_sd[47] = \<const0> ;
  assign s_axis_rq_tuser_sd[46] = \<const0> ;
  assign s_axis_rq_tuser_sd[45] = \<const0> ;
  assign s_axis_rq_tuser_sd[44] = \<const0> ;
  assign s_axis_rq_tuser_sd[43] = \<const0> ;
  assign s_axis_rq_tuser_sd[42] = \<const0> ;
  assign s_axis_rq_tuser_sd[41] = \<const0> ;
  assign s_axis_rq_tuser_sd[40] = \<const0> ;
  assign s_axis_rq_tuser_sd[39] = \<const0> ;
  assign s_axis_rq_tuser_sd[38] = \<const0> ;
  assign s_axis_rq_tuser_sd[37] = \<const0> ;
  assign s_axis_rq_tuser_sd[36] = \<const0> ;
  assign s_axis_rq_tuser_sd[35] = \<const0> ;
  assign s_axis_rq_tuser_sd[34] = \<const0> ;
  assign s_axis_rq_tuser_sd[33] = \<const0> ;
  assign s_axis_rq_tuser_sd[32] = \<const0> ;
  assign s_axis_rq_tuser_sd[31] = \<const0> ;
  assign s_axis_rq_tuser_sd[30] = \<const0> ;
  assign s_axis_rq_tuser_sd[29] = \<const0> ;
  assign s_axis_rq_tuser_sd[28] = \<const0> ;
  assign s_axis_rq_tuser_sd[27] = \<const0> ;
  assign s_axis_rq_tuser_sd[26] = \<const0> ;
  assign s_axis_rq_tuser_sd[25] = \<const0> ;
  assign s_axis_rq_tuser_sd[24] = \<const0> ;
  assign s_axis_rq_tuser_sd[23] = \<const0> ;
  assign s_axis_rq_tuser_sd[22] = \<const0> ;
  assign s_axis_rq_tuser_sd[21] = \<const0> ;
  assign s_axis_rq_tuser_sd[20] = \<const0> ;
  assign s_axis_rq_tuser_sd[19] = \<const0> ;
  assign s_axis_rq_tuser_sd[18] = \<const0> ;
  assign s_axis_rq_tuser_sd[17] = \<const0> ;
  assign s_axis_rq_tuser_sd[16] = \<const0> ;
  assign s_axis_rq_tuser_sd[15] = \<const0> ;
  assign s_axis_rq_tuser_sd[14] = \<const0> ;
  assign s_axis_rq_tuser_sd[13] = \<const0> ;
  assign s_axis_rq_tuser_sd[12] = \<const0> ;
  assign s_axis_rq_tuser_sd[11] = \<const0> ;
  assign s_axis_rq_tuser_sd[10] = \<const0> ;
  assign s_axis_rq_tuser_sd[9] = \<const0> ;
  assign s_axis_rq_tuser_sd[8] = \<const0> ;
  assign s_axis_rq_tuser_sd[7] = \<const0> ;
  assign s_axis_rq_tuser_sd[6] = \<const0> ;
  assign s_axis_rq_tuser_sd[5] = \<const0> ;
  assign s_axis_rq_tuser_sd[4] = \<const0> ;
  assign s_axis_rq_tuser_sd[3] = \<const0> ;
  assign s_axis_rq_tuser_sd[2] = \<const0> ;
  assign s_axis_rq_tuser_sd[1] = \<const0> ;
  assign s_axis_rq_tuser_sd[0] = \<const0> ;
  assign s_axis_rq_tvalid_sd = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[63] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[62] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[61] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[60] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[59] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[58] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[57] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[56] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[55] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[54] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[53] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[52] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[51] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[50] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[49] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[48] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[47] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[46] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[45] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[44] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[43] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[42] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[41] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[40] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[39] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[38] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[37] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[36] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[35] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[34] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[33] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[32] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[31] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[30] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[29] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[28] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[27] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[26] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[25] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[24] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[23] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[22] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[21] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[20] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[19] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[18] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[17] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[16] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[15] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[14] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[13] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[12] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[11] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[10] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[9] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[8] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[7] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[6] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[5] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[4] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[3] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[2] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[1] = \<const0> ;
  assign sc0_ats_m_axis_cq_tdata[0] = \<const0> ;
  assign sc0_ats_m_axis_cq_tkeep[7] = \<const0> ;
  assign sc0_ats_m_axis_cq_tkeep[6] = \<const0> ;
  assign sc0_ats_m_axis_cq_tkeep[5] = \<const0> ;
  assign sc0_ats_m_axis_cq_tkeep[4] = \<const0> ;
  assign sc0_ats_m_axis_cq_tkeep[3] = \<const0> ;
  assign sc0_ats_m_axis_cq_tkeep[2] = \<const0> ;
  assign sc0_ats_m_axis_cq_tkeep[1] = \<const0> ;
  assign sc0_ats_m_axis_cq_tkeep[0] = \<const0> ;
  assign sc0_ats_m_axis_cq_tlast = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[84] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[83] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[82] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[81] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[80] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[79] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[78] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[77] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[76] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[75] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[74] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[73] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[72] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[71] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[70] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[69] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[68] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[67] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[66] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[65] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[64] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[63] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[62] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[61] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[60] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[59] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[58] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[57] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[56] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[55] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[54] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[53] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[52] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[51] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[50] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[49] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[48] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[47] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[46] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[45] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[44] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[43] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[42] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[41] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[40] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[39] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[38] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[37] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[36] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[35] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[34] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[33] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[32] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[31] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[30] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[29] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[28] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[27] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[26] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[25] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[24] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[23] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[22] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[21] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[20] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[19] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[18] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[17] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[16] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[15] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[14] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[13] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[12] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[11] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[10] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[9] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[8] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[7] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[6] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[5] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[4] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[3] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[2] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[1] = \<const0> ;
  assign sc0_ats_m_axis_cq_tuser[0] = \<const0> ;
  assign sc0_ats_m_axis_cq_tvalid = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[63] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[62] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[61] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[60] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[59] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[58] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[57] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[56] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[55] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[54] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[53] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[52] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[51] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[50] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[49] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[48] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[47] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[46] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[45] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[44] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[43] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[42] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[41] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[40] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[39] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[38] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[37] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[36] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[35] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[34] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[33] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[32] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[31] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[30] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[29] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[28] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[27] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[26] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[25] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[24] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[23] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[22] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[21] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[20] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[19] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[18] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[17] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[16] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[15] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[14] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[13] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[12] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[11] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[10] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[9] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[8] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[7] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[6] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[5] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[4] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[3] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[2] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[1] = \<const0> ;
  assign sc0_ats_m_axis_rc_tdata[0] = \<const0> ;
  assign sc0_ats_m_axis_rc_tkeep[7] = \<const0> ;
  assign sc0_ats_m_axis_rc_tkeep[6] = \<const0> ;
  assign sc0_ats_m_axis_rc_tkeep[5] = \<const0> ;
  assign sc0_ats_m_axis_rc_tkeep[4] = \<const0> ;
  assign sc0_ats_m_axis_rc_tkeep[3] = \<const0> ;
  assign sc0_ats_m_axis_rc_tkeep[2] = \<const0> ;
  assign sc0_ats_m_axis_rc_tkeep[1] = \<const0> ;
  assign sc0_ats_m_axis_rc_tkeep[0] = \<const0> ;
  assign sc0_ats_m_axis_rc_tlast = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[74] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[73] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[72] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[71] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[70] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[69] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[68] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[67] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[66] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[65] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[64] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[63] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[62] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[61] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[60] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[59] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[58] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[57] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[56] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[55] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[54] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[53] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[52] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[51] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[50] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[49] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[48] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[47] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[46] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[45] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[44] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[43] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[42] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[41] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[40] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[39] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[38] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[37] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[36] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[35] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[34] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[33] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[32] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[31] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[30] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[29] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[28] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[27] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[26] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[25] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[24] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[23] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[22] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[21] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[20] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[19] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[18] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[17] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[16] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[15] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[14] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[13] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[12] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[11] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[10] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[9] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[8] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[7] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[6] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[5] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[4] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[3] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[2] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[1] = \<const0> ;
  assign sc0_ats_m_axis_rc_tuser[0] = \<const0> ;
  assign sc0_ats_m_axis_rc_tvalid = \<const0> ;
  assign sc0_ats_s_axis_cc_tready = \<const0> ;
  assign sc0_ats_s_axis_rq_tready = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[63] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[62] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[61] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[60] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[59] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[58] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[57] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[56] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[55] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[54] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[53] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[52] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[51] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[50] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[49] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[48] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[47] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[46] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[45] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[44] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[43] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[42] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[41] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[40] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[39] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[38] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[37] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[36] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[35] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[34] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[33] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[32] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[31] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[30] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[29] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[28] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[27] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[26] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[25] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[24] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[23] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[22] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[21] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[20] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[19] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[18] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[17] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[16] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[15] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[14] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[13] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[12] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[11] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[10] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[9] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[8] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[7] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[6] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[5] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[4] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[3] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[2] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[1] = \<const0> ;
  assign sc1_ats_m_axis_cq_tdata[0] = \<const0> ;
  assign sc1_ats_m_axis_cq_tkeep[7] = \<const0> ;
  assign sc1_ats_m_axis_cq_tkeep[6] = \<const0> ;
  assign sc1_ats_m_axis_cq_tkeep[5] = \<const0> ;
  assign sc1_ats_m_axis_cq_tkeep[4] = \<const0> ;
  assign sc1_ats_m_axis_cq_tkeep[3] = \<const0> ;
  assign sc1_ats_m_axis_cq_tkeep[2] = \<const0> ;
  assign sc1_ats_m_axis_cq_tkeep[1] = \<const0> ;
  assign sc1_ats_m_axis_cq_tkeep[0] = \<const0> ;
  assign sc1_ats_m_axis_cq_tlast = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[84] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[83] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[82] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[81] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[80] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[79] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[78] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[77] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[76] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[75] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[74] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[73] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[72] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[71] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[70] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[69] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[68] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[67] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[66] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[65] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[64] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[63] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[62] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[61] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[60] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[59] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[58] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[57] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[56] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[55] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[54] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[53] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[52] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[51] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[50] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[49] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[48] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[47] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[46] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[45] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[44] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[43] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[42] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[41] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[40] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[39] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[38] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[37] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[36] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[35] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[34] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[33] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[32] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[31] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[30] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[29] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[28] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[27] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[26] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[25] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[24] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[23] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[22] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[21] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[20] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[19] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[18] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[17] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[16] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[15] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[14] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[13] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[12] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[11] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[10] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[9] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[8] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[7] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[6] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[5] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[4] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[3] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[2] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[1] = \<const0> ;
  assign sc1_ats_m_axis_cq_tuser[0] = \<const0> ;
  assign sc1_ats_m_axis_cq_tvalid = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[63] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[62] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[61] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[60] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[59] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[58] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[57] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[56] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[55] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[54] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[53] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[52] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[51] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[50] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[49] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[48] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[47] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[46] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[45] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[44] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[43] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[42] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[41] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[40] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[39] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[38] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[37] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[36] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[35] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[34] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[33] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[32] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[31] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[30] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[29] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[28] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[27] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[26] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[25] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[24] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[23] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[22] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[21] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[20] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[19] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[18] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[17] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[16] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[15] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[14] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[13] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[12] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[11] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[10] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[9] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[8] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[7] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[6] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[5] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[4] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[3] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[2] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[1] = \<const0> ;
  assign sc1_ats_m_axis_rc_tdata[0] = \<const0> ;
  assign sc1_ats_m_axis_rc_tkeep[7] = \<const0> ;
  assign sc1_ats_m_axis_rc_tkeep[6] = \<const0> ;
  assign sc1_ats_m_axis_rc_tkeep[5] = \<const0> ;
  assign sc1_ats_m_axis_rc_tkeep[4] = \<const0> ;
  assign sc1_ats_m_axis_rc_tkeep[3] = \<const0> ;
  assign sc1_ats_m_axis_rc_tkeep[2] = \<const0> ;
  assign sc1_ats_m_axis_rc_tkeep[1] = \<const0> ;
  assign sc1_ats_m_axis_rc_tkeep[0] = \<const0> ;
  assign sc1_ats_m_axis_rc_tlast = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[74] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[73] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[72] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[71] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[70] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[69] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[68] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[67] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[66] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[65] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[64] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[63] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[62] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[61] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[60] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[59] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[58] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[57] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[56] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[55] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[54] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[53] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[52] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[51] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[50] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[49] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[48] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[47] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[46] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[45] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[44] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[43] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[42] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[41] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[40] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[39] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[38] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[37] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[36] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[35] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[34] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[33] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[32] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[31] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[30] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[29] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[28] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[27] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[26] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[25] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[24] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[23] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[22] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[21] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[20] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[19] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[18] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[17] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[16] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[15] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[14] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[13] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[12] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[11] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[10] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[9] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[8] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[7] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[6] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[5] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[4] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[3] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[2] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[1] = \<const0> ;
  assign sc1_ats_m_axis_rc_tuser[0] = \<const0> ;
  assign sc1_ats_m_axis_rc_tvalid = \<const0> ;
  assign sc1_ats_s_axis_cc_tready = \<const0> ;
  assign sc1_ats_s_axis_rq_tready = \<const0> ;
  assign startup_cfgclk = \<const0> ;
  assign startup_cfgmclk = \<const0> ;
  assign startup_di[3] = \<const0> ;
  assign startup_di[2] = \<const0> ;
  assign startup_di[1] = \<const0> ;
  assign startup_di[0] = \<const0> ;
  assign startup_eos = \<const0> ;
  assign startup_preq = \<const0> ;
  assign sys_clk_bufg = \<const0> ;
  assign sys_clk_ce_out = \<const0> ;
  assign tx8b10ben_us_in[1] = \<const0> ;
  assign tx8b10ben_us_in[0] = \<const0> ;
  assign tx8b10ben_usp_in[1] = \<const0> ;
  assign tx8b10ben_usp_in[0] = \<const0> ;
  assign txctrl0_us_in[31] = \<const0> ;
  assign txctrl0_us_in[30] = \<const0> ;
  assign txctrl0_us_in[29] = \<const0> ;
  assign txctrl0_us_in[28] = \<const0> ;
  assign txctrl0_us_in[27] = \<const0> ;
  assign txctrl0_us_in[26] = \<const0> ;
  assign txctrl0_us_in[25] = \<const0> ;
  assign txctrl0_us_in[24] = \<const0> ;
  assign txctrl0_us_in[23] = \<const0> ;
  assign txctrl0_us_in[22] = \<const0> ;
  assign txctrl0_us_in[21] = \<const0> ;
  assign txctrl0_us_in[20] = \<const0> ;
  assign txctrl0_us_in[19] = \<const0> ;
  assign txctrl0_us_in[18] = \<const0> ;
  assign txctrl0_us_in[17] = \<const0> ;
  assign txctrl0_us_in[16] = \<const0> ;
  assign txctrl0_us_in[15] = \<const0> ;
  assign txctrl0_us_in[14] = \<const0> ;
  assign txctrl0_us_in[13] = \<const0> ;
  assign txctrl0_us_in[12] = \<const0> ;
  assign txctrl0_us_in[11] = \<const0> ;
  assign txctrl0_us_in[10] = \<const0> ;
  assign txctrl0_us_in[9] = \<const0> ;
  assign txctrl0_us_in[8] = \<const0> ;
  assign txctrl0_us_in[7] = \<const0> ;
  assign txctrl0_us_in[6] = \<const0> ;
  assign txctrl0_us_in[5] = \<const0> ;
  assign txctrl0_us_in[4] = \<const0> ;
  assign txctrl0_us_in[3] = \<const0> ;
  assign txctrl0_us_in[2] = \<const0> ;
  assign txctrl0_us_in[1] = \<const0> ;
  assign txctrl0_us_in[0] = \<const0> ;
  assign txctrl0_usp_in[31] = \<const0> ;
  assign txctrl0_usp_in[30] = \<const0> ;
  assign txctrl0_usp_in[29] = \<const0> ;
  assign txctrl0_usp_in[28] = \<const0> ;
  assign txctrl0_usp_in[27] = \<const0> ;
  assign txctrl0_usp_in[26] = \<const0> ;
  assign txctrl0_usp_in[25] = \<const0> ;
  assign txctrl0_usp_in[24] = \<const0> ;
  assign txctrl0_usp_in[23] = \<const0> ;
  assign txctrl0_usp_in[22] = \<const0> ;
  assign txctrl0_usp_in[21] = \<const0> ;
  assign txctrl0_usp_in[20] = \<const0> ;
  assign txctrl0_usp_in[19] = \<const0> ;
  assign txctrl0_usp_in[18] = \<const0> ;
  assign txctrl0_usp_in[17] = \<const0> ;
  assign txctrl0_usp_in[16] = \<const0> ;
  assign txctrl0_usp_in[15] = \<const0> ;
  assign txctrl0_usp_in[14] = \<const0> ;
  assign txctrl0_usp_in[13] = \<const0> ;
  assign txctrl0_usp_in[12] = \<const0> ;
  assign txctrl0_usp_in[11] = \<const0> ;
  assign txctrl0_usp_in[10] = \<const0> ;
  assign txctrl0_usp_in[9] = \<const0> ;
  assign txctrl0_usp_in[8] = \<const0> ;
  assign txctrl0_usp_in[7] = \<const0> ;
  assign txctrl0_usp_in[6] = \<const0> ;
  assign txctrl0_usp_in[5] = \<const0> ;
  assign txctrl0_usp_in[4] = \<const0> ;
  assign txctrl0_usp_in[3] = \<const0> ;
  assign txctrl0_usp_in[2] = \<const0> ;
  assign txctrl0_usp_in[1] = \<const0> ;
  assign txctrl0_usp_in[0] = \<const0> ;
  assign txctrl1_us_in[31] = \<const0> ;
  assign txctrl1_us_in[30] = \<const0> ;
  assign txctrl1_us_in[29] = \<const0> ;
  assign txctrl1_us_in[28] = \<const0> ;
  assign txctrl1_us_in[27] = \<const0> ;
  assign txctrl1_us_in[26] = \<const0> ;
  assign txctrl1_us_in[25] = \<const0> ;
  assign txctrl1_us_in[24] = \<const0> ;
  assign txctrl1_us_in[23] = \<const0> ;
  assign txctrl1_us_in[22] = \<const0> ;
  assign txctrl1_us_in[21] = \<const0> ;
  assign txctrl1_us_in[20] = \<const0> ;
  assign txctrl1_us_in[19] = \<const0> ;
  assign txctrl1_us_in[18] = \<const0> ;
  assign txctrl1_us_in[17] = \<const0> ;
  assign txctrl1_us_in[16] = \<const0> ;
  assign txctrl1_us_in[15] = \<const0> ;
  assign txctrl1_us_in[14] = \<const0> ;
  assign txctrl1_us_in[13] = \<const0> ;
  assign txctrl1_us_in[12] = \<const0> ;
  assign txctrl1_us_in[11] = \<const0> ;
  assign txctrl1_us_in[10] = \<const0> ;
  assign txctrl1_us_in[9] = \<const0> ;
  assign txctrl1_us_in[8] = \<const0> ;
  assign txctrl1_us_in[7] = \<const0> ;
  assign txctrl1_us_in[6] = \<const0> ;
  assign txctrl1_us_in[5] = \<const0> ;
  assign txctrl1_us_in[4] = \<const0> ;
  assign txctrl1_us_in[3] = \<const0> ;
  assign txctrl1_us_in[2] = \<const0> ;
  assign txctrl1_us_in[1] = \<const0> ;
  assign txctrl1_us_in[0] = \<const0> ;
  assign txctrl1_usp_in[31] = \<const0> ;
  assign txctrl1_usp_in[30] = \<const0> ;
  assign txctrl1_usp_in[29] = \<const0> ;
  assign txctrl1_usp_in[28] = \<const0> ;
  assign txctrl1_usp_in[27] = \<const0> ;
  assign txctrl1_usp_in[26] = \<const0> ;
  assign txctrl1_usp_in[25] = \<const0> ;
  assign txctrl1_usp_in[24] = \<const0> ;
  assign txctrl1_usp_in[23] = \<const0> ;
  assign txctrl1_usp_in[22] = \<const0> ;
  assign txctrl1_usp_in[21] = \<const0> ;
  assign txctrl1_usp_in[20] = \<const0> ;
  assign txctrl1_usp_in[19] = \<const0> ;
  assign txctrl1_usp_in[18] = \<const0> ;
  assign txctrl1_usp_in[17] = \<const0> ;
  assign txctrl1_usp_in[16] = \<const0> ;
  assign txctrl1_usp_in[15] = \<const0> ;
  assign txctrl1_usp_in[14] = \<const0> ;
  assign txctrl1_usp_in[13] = \<const0> ;
  assign txctrl1_usp_in[12] = \<const0> ;
  assign txctrl1_usp_in[11] = \<const0> ;
  assign txctrl1_usp_in[10] = \<const0> ;
  assign txctrl1_usp_in[9] = \<const0> ;
  assign txctrl1_usp_in[8] = \<const0> ;
  assign txctrl1_usp_in[7] = \<const0> ;
  assign txctrl1_usp_in[6] = \<const0> ;
  assign txctrl1_usp_in[5] = \<const0> ;
  assign txctrl1_usp_in[4] = \<const0> ;
  assign txctrl1_usp_in[3] = \<const0> ;
  assign txctrl1_usp_in[2] = \<const0> ;
  assign txctrl1_usp_in[1] = \<const0> ;
  assign txctrl1_usp_in[0] = \<const0> ;
  assign txctrl2_us_in[15] = \<const0> ;
  assign txctrl2_us_in[14] = \<const0> ;
  assign txctrl2_us_in[13] = \<const0> ;
  assign txctrl2_us_in[12] = \<const0> ;
  assign txctrl2_us_in[11] = \<const0> ;
  assign txctrl2_us_in[10] = \<const0> ;
  assign txctrl2_us_in[9] = \<const0> ;
  assign txctrl2_us_in[8] = \<const0> ;
  assign txctrl2_us_in[7] = \<const0> ;
  assign txctrl2_us_in[6] = \<const0> ;
  assign txctrl2_us_in[5] = \<const0> ;
  assign txctrl2_us_in[4] = \<const0> ;
  assign txctrl2_us_in[3] = \<const0> ;
  assign txctrl2_us_in[2] = \<const0> ;
  assign txctrl2_us_in[1] = \<const0> ;
  assign txctrl2_us_in[0] = \<const0> ;
  assign txctrl2_usp_in[15] = \<const0> ;
  assign txctrl2_usp_in[14] = \<const0> ;
  assign txctrl2_usp_in[13] = \<const0> ;
  assign txctrl2_usp_in[12] = \<const0> ;
  assign txctrl2_usp_in[11] = \<const0> ;
  assign txctrl2_usp_in[10] = \<const0> ;
  assign txctrl2_usp_in[9] = \<const0> ;
  assign txctrl2_usp_in[8] = \<const0> ;
  assign txctrl2_usp_in[7] = \<const0> ;
  assign txctrl2_usp_in[6] = \<const0> ;
  assign txctrl2_usp_in[5] = \<const0> ;
  assign txctrl2_usp_in[4] = \<const0> ;
  assign txctrl2_usp_in[3] = \<const0> ;
  assign txctrl2_usp_in[2] = \<const0> ;
  assign txctrl2_usp_in[1] = \<const0> ;
  assign txctrl2_usp_in[0] = \<const0> ;
  assign txdata_us_in[255] = \<const0> ;
  assign txdata_us_in[254] = \<const0> ;
  assign txdata_us_in[253] = \<const0> ;
  assign txdata_us_in[252] = \<const0> ;
  assign txdata_us_in[251] = \<const0> ;
  assign txdata_us_in[250] = \<const0> ;
  assign txdata_us_in[249] = \<const0> ;
  assign txdata_us_in[248] = \<const0> ;
  assign txdata_us_in[247] = \<const0> ;
  assign txdata_us_in[246] = \<const0> ;
  assign txdata_us_in[245] = \<const0> ;
  assign txdata_us_in[244] = \<const0> ;
  assign txdata_us_in[243] = \<const0> ;
  assign txdata_us_in[242] = \<const0> ;
  assign txdata_us_in[241] = \<const0> ;
  assign txdata_us_in[240] = \<const0> ;
  assign txdata_us_in[239] = \<const0> ;
  assign txdata_us_in[238] = \<const0> ;
  assign txdata_us_in[237] = \<const0> ;
  assign txdata_us_in[236] = \<const0> ;
  assign txdata_us_in[235] = \<const0> ;
  assign txdata_us_in[234] = \<const0> ;
  assign txdata_us_in[233] = \<const0> ;
  assign txdata_us_in[232] = \<const0> ;
  assign txdata_us_in[231] = \<const0> ;
  assign txdata_us_in[230] = \<const0> ;
  assign txdata_us_in[229] = \<const0> ;
  assign txdata_us_in[228] = \<const0> ;
  assign txdata_us_in[227] = \<const0> ;
  assign txdata_us_in[226] = \<const0> ;
  assign txdata_us_in[225] = \<const0> ;
  assign txdata_us_in[224] = \<const0> ;
  assign txdata_us_in[223] = \<const0> ;
  assign txdata_us_in[222] = \<const0> ;
  assign txdata_us_in[221] = \<const0> ;
  assign txdata_us_in[220] = \<const0> ;
  assign txdata_us_in[219] = \<const0> ;
  assign txdata_us_in[218] = \<const0> ;
  assign txdata_us_in[217] = \<const0> ;
  assign txdata_us_in[216] = \<const0> ;
  assign txdata_us_in[215] = \<const0> ;
  assign txdata_us_in[214] = \<const0> ;
  assign txdata_us_in[213] = \<const0> ;
  assign txdata_us_in[212] = \<const0> ;
  assign txdata_us_in[211] = \<const0> ;
  assign txdata_us_in[210] = \<const0> ;
  assign txdata_us_in[209] = \<const0> ;
  assign txdata_us_in[208] = \<const0> ;
  assign txdata_us_in[207] = \<const0> ;
  assign txdata_us_in[206] = \<const0> ;
  assign txdata_us_in[205] = \<const0> ;
  assign txdata_us_in[204] = \<const0> ;
  assign txdata_us_in[203] = \<const0> ;
  assign txdata_us_in[202] = \<const0> ;
  assign txdata_us_in[201] = \<const0> ;
  assign txdata_us_in[200] = \<const0> ;
  assign txdata_us_in[199] = \<const0> ;
  assign txdata_us_in[198] = \<const0> ;
  assign txdata_us_in[197] = \<const0> ;
  assign txdata_us_in[196] = \<const0> ;
  assign txdata_us_in[195] = \<const0> ;
  assign txdata_us_in[194] = \<const0> ;
  assign txdata_us_in[193] = \<const0> ;
  assign txdata_us_in[192] = \<const0> ;
  assign txdata_us_in[191] = \<const0> ;
  assign txdata_us_in[190] = \<const0> ;
  assign txdata_us_in[189] = \<const0> ;
  assign txdata_us_in[188] = \<const0> ;
  assign txdata_us_in[187] = \<const0> ;
  assign txdata_us_in[186] = \<const0> ;
  assign txdata_us_in[185] = \<const0> ;
  assign txdata_us_in[184] = \<const0> ;
  assign txdata_us_in[183] = \<const0> ;
  assign txdata_us_in[182] = \<const0> ;
  assign txdata_us_in[181] = \<const0> ;
  assign txdata_us_in[180] = \<const0> ;
  assign txdata_us_in[179] = \<const0> ;
  assign txdata_us_in[178] = \<const0> ;
  assign txdata_us_in[177] = \<const0> ;
  assign txdata_us_in[176] = \<const0> ;
  assign txdata_us_in[175] = \<const0> ;
  assign txdata_us_in[174] = \<const0> ;
  assign txdata_us_in[173] = \<const0> ;
  assign txdata_us_in[172] = \<const0> ;
  assign txdata_us_in[171] = \<const0> ;
  assign txdata_us_in[170] = \<const0> ;
  assign txdata_us_in[169] = \<const0> ;
  assign txdata_us_in[168] = \<const0> ;
  assign txdata_us_in[167] = \<const0> ;
  assign txdata_us_in[166] = \<const0> ;
  assign txdata_us_in[165] = \<const0> ;
  assign txdata_us_in[164] = \<const0> ;
  assign txdata_us_in[163] = \<const0> ;
  assign txdata_us_in[162] = \<const0> ;
  assign txdata_us_in[161] = \<const0> ;
  assign txdata_us_in[160] = \<const0> ;
  assign txdata_us_in[159] = \<const0> ;
  assign txdata_us_in[158] = \<const0> ;
  assign txdata_us_in[157] = \<const0> ;
  assign txdata_us_in[156] = \<const0> ;
  assign txdata_us_in[155] = \<const0> ;
  assign txdata_us_in[154] = \<const0> ;
  assign txdata_us_in[153] = \<const0> ;
  assign txdata_us_in[152] = \<const0> ;
  assign txdata_us_in[151] = \<const0> ;
  assign txdata_us_in[150] = \<const0> ;
  assign txdata_us_in[149] = \<const0> ;
  assign txdata_us_in[148] = \<const0> ;
  assign txdata_us_in[147] = \<const0> ;
  assign txdata_us_in[146] = \<const0> ;
  assign txdata_us_in[145] = \<const0> ;
  assign txdata_us_in[144] = \<const0> ;
  assign txdata_us_in[143] = \<const0> ;
  assign txdata_us_in[142] = \<const0> ;
  assign txdata_us_in[141] = \<const0> ;
  assign txdata_us_in[140] = \<const0> ;
  assign txdata_us_in[139] = \<const0> ;
  assign txdata_us_in[138] = \<const0> ;
  assign txdata_us_in[137] = \<const0> ;
  assign txdata_us_in[136] = \<const0> ;
  assign txdata_us_in[135] = \<const0> ;
  assign txdata_us_in[134] = \<const0> ;
  assign txdata_us_in[133] = \<const0> ;
  assign txdata_us_in[132] = \<const0> ;
  assign txdata_us_in[131] = \<const0> ;
  assign txdata_us_in[130] = \<const0> ;
  assign txdata_us_in[129] = \<const0> ;
  assign txdata_us_in[128] = \<const0> ;
  assign txdata_us_in[127] = \<const0> ;
  assign txdata_us_in[126] = \<const0> ;
  assign txdata_us_in[125] = \<const0> ;
  assign txdata_us_in[124] = \<const0> ;
  assign txdata_us_in[123] = \<const0> ;
  assign txdata_us_in[122] = \<const0> ;
  assign txdata_us_in[121] = \<const0> ;
  assign txdata_us_in[120] = \<const0> ;
  assign txdata_us_in[119] = \<const0> ;
  assign txdata_us_in[118] = \<const0> ;
  assign txdata_us_in[117] = \<const0> ;
  assign txdata_us_in[116] = \<const0> ;
  assign txdata_us_in[115] = \<const0> ;
  assign txdata_us_in[114] = \<const0> ;
  assign txdata_us_in[113] = \<const0> ;
  assign txdata_us_in[112] = \<const0> ;
  assign txdata_us_in[111] = \<const0> ;
  assign txdata_us_in[110] = \<const0> ;
  assign txdata_us_in[109] = \<const0> ;
  assign txdata_us_in[108] = \<const0> ;
  assign txdata_us_in[107] = \<const0> ;
  assign txdata_us_in[106] = \<const0> ;
  assign txdata_us_in[105] = \<const0> ;
  assign txdata_us_in[104] = \<const0> ;
  assign txdata_us_in[103] = \<const0> ;
  assign txdata_us_in[102] = \<const0> ;
  assign txdata_us_in[101] = \<const0> ;
  assign txdata_us_in[100] = \<const0> ;
  assign txdata_us_in[99] = \<const0> ;
  assign txdata_us_in[98] = \<const0> ;
  assign txdata_us_in[97] = \<const0> ;
  assign txdata_us_in[96] = \<const0> ;
  assign txdata_us_in[95] = \<const0> ;
  assign txdata_us_in[94] = \<const0> ;
  assign txdata_us_in[93] = \<const0> ;
  assign txdata_us_in[92] = \<const0> ;
  assign txdata_us_in[91] = \<const0> ;
  assign txdata_us_in[90] = \<const0> ;
  assign txdata_us_in[89] = \<const0> ;
  assign txdata_us_in[88] = \<const0> ;
  assign txdata_us_in[87] = \<const0> ;
  assign txdata_us_in[86] = \<const0> ;
  assign txdata_us_in[85] = \<const0> ;
  assign txdata_us_in[84] = \<const0> ;
  assign txdata_us_in[83] = \<const0> ;
  assign txdata_us_in[82] = \<const0> ;
  assign txdata_us_in[81] = \<const0> ;
  assign txdata_us_in[80] = \<const0> ;
  assign txdata_us_in[79] = \<const0> ;
  assign txdata_us_in[78] = \<const0> ;
  assign txdata_us_in[77] = \<const0> ;
  assign txdata_us_in[76] = \<const0> ;
  assign txdata_us_in[75] = \<const0> ;
  assign txdata_us_in[74] = \<const0> ;
  assign txdata_us_in[73] = \<const0> ;
  assign txdata_us_in[72] = \<const0> ;
  assign txdata_us_in[71] = \<const0> ;
  assign txdata_us_in[70] = \<const0> ;
  assign txdata_us_in[69] = \<const0> ;
  assign txdata_us_in[68] = \<const0> ;
  assign txdata_us_in[67] = \<const0> ;
  assign txdata_us_in[66] = \<const0> ;
  assign txdata_us_in[65] = \<const0> ;
  assign txdata_us_in[64] = \<const0> ;
  assign txdata_us_in[63] = \<const0> ;
  assign txdata_us_in[62] = \<const0> ;
  assign txdata_us_in[61] = \<const0> ;
  assign txdata_us_in[60] = \<const0> ;
  assign txdata_us_in[59] = \<const0> ;
  assign txdata_us_in[58] = \<const0> ;
  assign txdata_us_in[57] = \<const0> ;
  assign txdata_us_in[56] = \<const0> ;
  assign txdata_us_in[55] = \<const0> ;
  assign txdata_us_in[54] = \<const0> ;
  assign txdata_us_in[53] = \<const0> ;
  assign txdata_us_in[52] = \<const0> ;
  assign txdata_us_in[51] = \<const0> ;
  assign txdata_us_in[50] = \<const0> ;
  assign txdata_us_in[49] = \<const0> ;
  assign txdata_us_in[48] = \<const0> ;
  assign txdata_us_in[47] = \<const0> ;
  assign txdata_us_in[46] = \<const0> ;
  assign txdata_us_in[45] = \<const0> ;
  assign txdata_us_in[44] = \<const0> ;
  assign txdata_us_in[43] = \<const0> ;
  assign txdata_us_in[42] = \<const0> ;
  assign txdata_us_in[41] = \<const0> ;
  assign txdata_us_in[40] = \<const0> ;
  assign txdata_us_in[39] = \<const0> ;
  assign txdata_us_in[38] = \<const0> ;
  assign txdata_us_in[37] = \<const0> ;
  assign txdata_us_in[36] = \<const0> ;
  assign txdata_us_in[35] = \<const0> ;
  assign txdata_us_in[34] = \<const0> ;
  assign txdata_us_in[33] = \<const0> ;
  assign txdata_us_in[32] = \<const0> ;
  assign txdata_us_in[31] = \<const0> ;
  assign txdata_us_in[30] = \<const0> ;
  assign txdata_us_in[29] = \<const0> ;
  assign txdata_us_in[28] = \<const0> ;
  assign txdata_us_in[27] = \<const0> ;
  assign txdata_us_in[26] = \<const0> ;
  assign txdata_us_in[25] = \<const0> ;
  assign txdata_us_in[24] = \<const0> ;
  assign txdata_us_in[23] = \<const0> ;
  assign txdata_us_in[22] = \<const0> ;
  assign txdata_us_in[21] = \<const0> ;
  assign txdata_us_in[20] = \<const0> ;
  assign txdata_us_in[19] = \<const0> ;
  assign txdata_us_in[18] = \<const0> ;
  assign txdata_us_in[17] = \<const0> ;
  assign txdata_us_in[16] = \<const0> ;
  assign txdata_us_in[15] = \<const0> ;
  assign txdata_us_in[14] = \<const0> ;
  assign txdata_us_in[13] = \<const0> ;
  assign txdata_us_in[12] = \<const0> ;
  assign txdata_us_in[11] = \<const0> ;
  assign txdata_us_in[10] = \<const0> ;
  assign txdata_us_in[9] = \<const0> ;
  assign txdata_us_in[8] = \<const0> ;
  assign txdata_us_in[7] = \<const0> ;
  assign txdata_us_in[6] = \<const0> ;
  assign txdata_us_in[5] = \<const0> ;
  assign txdata_us_in[4] = \<const0> ;
  assign txdata_us_in[3] = \<const0> ;
  assign txdata_us_in[2] = \<const0> ;
  assign txdata_us_in[1] = \<const0> ;
  assign txdata_us_in[0] = \<const0> ;
  assign txdata_usp_in[255] = \<const0> ;
  assign txdata_usp_in[254] = \<const0> ;
  assign txdata_usp_in[253] = \<const0> ;
  assign txdata_usp_in[252] = \<const0> ;
  assign txdata_usp_in[251] = \<const0> ;
  assign txdata_usp_in[250] = \<const0> ;
  assign txdata_usp_in[249] = \<const0> ;
  assign txdata_usp_in[248] = \<const0> ;
  assign txdata_usp_in[247] = \<const0> ;
  assign txdata_usp_in[246] = \<const0> ;
  assign txdata_usp_in[245] = \<const0> ;
  assign txdata_usp_in[244] = \<const0> ;
  assign txdata_usp_in[243] = \<const0> ;
  assign txdata_usp_in[242] = \<const0> ;
  assign txdata_usp_in[241] = \<const0> ;
  assign txdata_usp_in[240] = \<const0> ;
  assign txdata_usp_in[239] = \<const0> ;
  assign txdata_usp_in[238] = \<const0> ;
  assign txdata_usp_in[237] = \<const0> ;
  assign txdata_usp_in[236] = \<const0> ;
  assign txdata_usp_in[235] = \<const0> ;
  assign txdata_usp_in[234] = \<const0> ;
  assign txdata_usp_in[233] = \<const0> ;
  assign txdata_usp_in[232] = \<const0> ;
  assign txdata_usp_in[231] = \<const0> ;
  assign txdata_usp_in[230] = \<const0> ;
  assign txdata_usp_in[229] = \<const0> ;
  assign txdata_usp_in[228] = \<const0> ;
  assign txdata_usp_in[227] = \<const0> ;
  assign txdata_usp_in[226] = \<const0> ;
  assign txdata_usp_in[225] = \<const0> ;
  assign txdata_usp_in[224] = \<const0> ;
  assign txdata_usp_in[223] = \<const0> ;
  assign txdata_usp_in[222] = \<const0> ;
  assign txdata_usp_in[221] = \<const0> ;
  assign txdata_usp_in[220] = \<const0> ;
  assign txdata_usp_in[219] = \<const0> ;
  assign txdata_usp_in[218] = \<const0> ;
  assign txdata_usp_in[217] = \<const0> ;
  assign txdata_usp_in[216] = \<const0> ;
  assign txdata_usp_in[215] = \<const0> ;
  assign txdata_usp_in[214] = \<const0> ;
  assign txdata_usp_in[213] = \<const0> ;
  assign txdata_usp_in[212] = \<const0> ;
  assign txdata_usp_in[211] = \<const0> ;
  assign txdata_usp_in[210] = \<const0> ;
  assign txdata_usp_in[209] = \<const0> ;
  assign txdata_usp_in[208] = \<const0> ;
  assign txdata_usp_in[207] = \<const0> ;
  assign txdata_usp_in[206] = \<const0> ;
  assign txdata_usp_in[205] = \<const0> ;
  assign txdata_usp_in[204] = \<const0> ;
  assign txdata_usp_in[203] = \<const0> ;
  assign txdata_usp_in[202] = \<const0> ;
  assign txdata_usp_in[201] = \<const0> ;
  assign txdata_usp_in[200] = \<const0> ;
  assign txdata_usp_in[199] = \<const0> ;
  assign txdata_usp_in[198] = \<const0> ;
  assign txdata_usp_in[197] = \<const0> ;
  assign txdata_usp_in[196] = \<const0> ;
  assign txdata_usp_in[195] = \<const0> ;
  assign txdata_usp_in[194] = \<const0> ;
  assign txdata_usp_in[193] = \<const0> ;
  assign txdata_usp_in[192] = \<const0> ;
  assign txdata_usp_in[191] = \<const0> ;
  assign txdata_usp_in[190] = \<const0> ;
  assign txdata_usp_in[189] = \<const0> ;
  assign txdata_usp_in[188] = \<const0> ;
  assign txdata_usp_in[187] = \<const0> ;
  assign txdata_usp_in[186] = \<const0> ;
  assign txdata_usp_in[185] = \<const0> ;
  assign txdata_usp_in[184] = \<const0> ;
  assign txdata_usp_in[183] = \<const0> ;
  assign txdata_usp_in[182] = \<const0> ;
  assign txdata_usp_in[181] = \<const0> ;
  assign txdata_usp_in[180] = \<const0> ;
  assign txdata_usp_in[179] = \<const0> ;
  assign txdata_usp_in[178] = \<const0> ;
  assign txdata_usp_in[177] = \<const0> ;
  assign txdata_usp_in[176] = \<const0> ;
  assign txdata_usp_in[175] = \<const0> ;
  assign txdata_usp_in[174] = \<const0> ;
  assign txdata_usp_in[173] = \<const0> ;
  assign txdata_usp_in[172] = \<const0> ;
  assign txdata_usp_in[171] = \<const0> ;
  assign txdata_usp_in[170] = \<const0> ;
  assign txdata_usp_in[169] = \<const0> ;
  assign txdata_usp_in[168] = \<const0> ;
  assign txdata_usp_in[167] = \<const0> ;
  assign txdata_usp_in[166] = \<const0> ;
  assign txdata_usp_in[165] = \<const0> ;
  assign txdata_usp_in[164] = \<const0> ;
  assign txdata_usp_in[163] = \<const0> ;
  assign txdata_usp_in[162] = \<const0> ;
  assign txdata_usp_in[161] = \<const0> ;
  assign txdata_usp_in[160] = \<const0> ;
  assign txdata_usp_in[159] = \<const0> ;
  assign txdata_usp_in[158] = \<const0> ;
  assign txdata_usp_in[157] = \<const0> ;
  assign txdata_usp_in[156] = \<const0> ;
  assign txdata_usp_in[155] = \<const0> ;
  assign txdata_usp_in[154] = \<const0> ;
  assign txdata_usp_in[153] = \<const0> ;
  assign txdata_usp_in[152] = \<const0> ;
  assign txdata_usp_in[151] = \<const0> ;
  assign txdata_usp_in[150] = \<const0> ;
  assign txdata_usp_in[149] = \<const0> ;
  assign txdata_usp_in[148] = \<const0> ;
  assign txdata_usp_in[147] = \<const0> ;
  assign txdata_usp_in[146] = \<const0> ;
  assign txdata_usp_in[145] = \<const0> ;
  assign txdata_usp_in[144] = \<const0> ;
  assign txdata_usp_in[143] = \<const0> ;
  assign txdata_usp_in[142] = \<const0> ;
  assign txdata_usp_in[141] = \<const0> ;
  assign txdata_usp_in[140] = \<const0> ;
  assign txdata_usp_in[139] = \<const0> ;
  assign txdata_usp_in[138] = \<const0> ;
  assign txdata_usp_in[137] = \<const0> ;
  assign txdata_usp_in[136] = \<const0> ;
  assign txdata_usp_in[135] = \<const0> ;
  assign txdata_usp_in[134] = \<const0> ;
  assign txdata_usp_in[133] = \<const0> ;
  assign txdata_usp_in[132] = \<const0> ;
  assign txdata_usp_in[131] = \<const0> ;
  assign txdata_usp_in[130] = \<const0> ;
  assign txdata_usp_in[129] = \<const0> ;
  assign txdata_usp_in[128] = \<const0> ;
  assign txdata_usp_in[127] = \<const0> ;
  assign txdata_usp_in[126] = \<const0> ;
  assign txdata_usp_in[125] = \<const0> ;
  assign txdata_usp_in[124] = \<const0> ;
  assign txdata_usp_in[123] = \<const0> ;
  assign txdata_usp_in[122] = \<const0> ;
  assign txdata_usp_in[121] = \<const0> ;
  assign txdata_usp_in[120] = \<const0> ;
  assign txdata_usp_in[119] = \<const0> ;
  assign txdata_usp_in[118] = \<const0> ;
  assign txdata_usp_in[117] = \<const0> ;
  assign txdata_usp_in[116] = \<const0> ;
  assign txdata_usp_in[115] = \<const0> ;
  assign txdata_usp_in[114] = \<const0> ;
  assign txdata_usp_in[113] = \<const0> ;
  assign txdata_usp_in[112] = \<const0> ;
  assign txdata_usp_in[111] = \<const0> ;
  assign txdata_usp_in[110] = \<const0> ;
  assign txdata_usp_in[109] = \<const0> ;
  assign txdata_usp_in[108] = \<const0> ;
  assign txdata_usp_in[107] = \<const0> ;
  assign txdata_usp_in[106] = \<const0> ;
  assign txdata_usp_in[105] = \<const0> ;
  assign txdata_usp_in[104] = \<const0> ;
  assign txdata_usp_in[103] = \<const0> ;
  assign txdata_usp_in[102] = \<const0> ;
  assign txdata_usp_in[101] = \<const0> ;
  assign txdata_usp_in[100] = \<const0> ;
  assign txdata_usp_in[99] = \<const0> ;
  assign txdata_usp_in[98] = \<const0> ;
  assign txdata_usp_in[97] = \<const0> ;
  assign txdata_usp_in[96] = \<const0> ;
  assign txdata_usp_in[95] = \<const0> ;
  assign txdata_usp_in[94] = \<const0> ;
  assign txdata_usp_in[93] = \<const0> ;
  assign txdata_usp_in[92] = \<const0> ;
  assign txdata_usp_in[91] = \<const0> ;
  assign txdata_usp_in[90] = \<const0> ;
  assign txdata_usp_in[89] = \<const0> ;
  assign txdata_usp_in[88] = \<const0> ;
  assign txdata_usp_in[87] = \<const0> ;
  assign txdata_usp_in[86] = \<const0> ;
  assign txdata_usp_in[85] = \<const0> ;
  assign txdata_usp_in[84] = \<const0> ;
  assign txdata_usp_in[83] = \<const0> ;
  assign txdata_usp_in[82] = \<const0> ;
  assign txdata_usp_in[81] = \<const0> ;
  assign txdata_usp_in[80] = \<const0> ;
  assign txdata_usp_in[79] = \<const0> ;
  assign txdata_usp_in[78] = \<const0> ;
  assign txdata_usp_in[77] = \<const0> ;
  assign txdata_usp_in[76] = \<const0> ;
  assign txdata_usp_in[75] = \<const0> ;
  assign txdata_usp_in[74] = \<const0> ;
  assign txdata_usp_in[73] = \<const0> ;
  assign txdata_usp_in[72] = \<const0> ;
  assign txdata_usp_in[71] = \<const0> ;
  assign txdata_usp_in[70] = \<const0> ;
  assign txdata_usp_in[69] = \<const0> ;
  assign txdata_usp_in[68] = \<const0> ;
  assign txdata_usp_in[67] = \<const0> ;
  assign txdata_usp_in[66] = \<const0> ;
  assign txdata_usp_in[65] = \<const0> ;
  assign txdata_usp_in[64] = \<const0> ;
  assign txdata_usp_in[63] = \<const0> ;
  assign txdata_usp_in[62] = \<const0> ;
  assign txdata_usp_in[61] = \<const0> ;
  assign txdata_usp_in[60] = \<const0> ;
  assign txdata_usp_in[59] = \<const0> ;
  assign txdata_usp_in[58] = \<const0> ;
  assign txdata_usp_in[57] = \<const0> ;
  assign txdata_usp_in[56] = \<const0> ;
  assign txdata_usp_in[55] = \<const0> ;
  assign txdata_usp_in[54] = \<const0> ;
  assign txdata_usp_in[53] = \<const0> ;
  assign txdata_usp_in[52] = \<const0> ;
  assign txdata_usp_in[51] = \<const0> ;
  assign txdata_usp_in[50] = \<const0> ;
  assign txdata_usp_in[49] = \<const0> ;
  assign txdata_usp_in[48] = \<const0> ;
  assign txdata_usp_in[47] = \<const0> ;
  assign txdata_usp_in[46] = \<const0> ;
  assign txdata_usp_in[45] = \<const0> ;
  assign txdata_usp_in[44] = \<const0> ;
  assign txdata_usp_in[43] = \<const0> ;
  assign txdata_usp_in[42] = \<const0> ;
  assign txdata_usp_in[41] = \<const0> ;
  assign txdata_usp_in[40] = \<const0> ;
  assign txdata_usp_in[39] = \<const0> ;
  assign txdata_usp_in[38] = \<const0> ;
  assign txdata_usp_in[37] = \<const0> ;
  assign txdata_usp_in[36] = \<const0> ;
  assign txdata_usp_in[35] = \<const0> ;
  assign txdata_usp_in[34] = \<const0> ;
  assign txdata_usp_in[33] = \<const0> ;
  assign txdata_usp_in[32] = \<const0> ;
  assign txdata_usp_in[31] = \<const0> ;
  assign txdata_usp_in[30] = \<const0> ;
  assign txdata_usp_in[29] = \<const0> ;
  assign txdata_usp_in[28] = \<const0> ;
  assign txdata_usp_in[27] = \<const0> ;
  assign txdata_usp_in[26] = \<const0> ;
  assign txdata_usp_in[25] = \<const0> ;
  assign txdata_usp_in[24] = \<const0> ;
  assign txdata_usp_in[23] = \<const0> ;
  assign txdata_usp_in[22] = \<const0> ;
  assign txdata_usp_in[21] = \<const0> ;
  assign txdata_usp_in[20] = \<const0> ;
  assign txdata_usp_in[19] = \<const0> ;
  assign txdata_usp_in[18] = \<const0> ;
  assign txdata_usp_in[17] = \<const0> ;
  assign txdata_usp_in[16] = \<const0> ;
  assign txdata_usp_in[15] = \<const0> ;
  assign txdata_usp_in[14] = \<const0> ;
  assign txdata_usp_in[13] = \<const0> ;
  assign txdata_usp_in[12] = \<const0> ;
  assign txdata_usp_in[11] = \<const0> ;
  assign txdata_usp_in[10] = \<const0> ;
  assign txdata_usp_in[9] = \<const0> ;
  assign txdata_usp_in[8] = \<const0> ;
  assign txdata_usp_in[7] = \<const0> ;
  assign txdata_usp_in[6] = \<const0> ;
  assign txdata_usp_in[5] = \<const0> ;
  assign txdata_usp_in[4] = \<const0> ;
  assign txdata_usp_in[3] = \<const0> ;
  assign txdata_usp_in[2] = \<const0> ;
  assign txdata_usp_in[1] = \<const0> ;
  assign txdata_usp_in[0] = \<const0> ;
  assign txdeemph_us_in[1] = \<const0> ;
  assign txdeemph_us_in[0] = \<const0> ;
  assign txdeemph_usp_in[3] = \<const0> ;
  assign txdeemph_usp_in[2] = \<const0> ;
  assign txdeemph_usp_in[1] = \<const0> ;
  assign txdeemph_usp_in[0] = \<const0> ;
  assign txdetectrx_us_in[1] = \<const0> ;
  assign txdetectrx_us_in[0] = \<const0> ;
  assign txdetectrx_usp_in[1] = \<const0> ;
  assign txdetectrx_usp_in[0] = \<const0> ;
  assign txdiffctrl_us_in[7] = \<const0> ;
  assign txdiffctrl_us_in[6] = \<const0> ;
  assign txdiffctrl_us_in[5] = \<const0> ;
  assign txdiffctrl_us_in[4] = \<const0> ;
  assign txdiffctrl_us_in[3] = \<const0> ;
  assign txdiffctrl_us_in[2] = \<const0> ;
  assign txdiffctrl_us_in[1] = \<const0> ;
  assign txdiffctrl_us_in[0] = \<const0> ;
  assign txdiffctrl_usp_in[9] = \<const0> ;
  assign txdiffctrl_usp_in[8] = \<const0> ;
  assign txdiffctrl_usp_in[7] = \<const0> ;
  assign txdiffctrl_usp_in[6] = \<const0> ;
  assign txdiffctrl_usp_in[5] = \<const0> ;
  assign txdiffctrl_usp_in[4] = \<const0> ;
  assign txdiffctrl_usp_in[3] = \<const0> ;
  assign txdiffctrl_usp_in[2] = \<const0> ;
  assign txdiffctrl_usp_in[1] = \<const0> ;
  assign txdiffctrl_usp_in[0] = \<const0> ;
  assign txdlybypass_us_in[1] = \<const0> ;
  assign txdlybypass_us_in[0] = \<const0> ;
  assign txdlybypass_usp_in[1] = \<const0> ;
  assign txdlybypass_usp_in[0] = \<const0> ;
  assign txdlyen_us_in[1] = \<const0> ;
  assign txdlyen_us_in[0] = \<const0> ;
  assign txdlyen_usp_in[1] = \<const0> ;
  assign txdlyen_usp_in[0] = \<const0> ;
  assign txdlyhold_us_in[1] = \<const0> ;
  assign txdlyhold_us_in[0] = \<const0> ;
  assign txdlyhold_usp_in[1] = \<const0> ;
  assign txdlyhold_usp_in[0] = \<const0> ;
  assign txdlyovrden_us_in[1] = \<const0> ;
  assign txdlyovrden_us_in[0] = \<const0> ;
  assign txdlyovrden_usp_in[1] = \<const0> ;
  assign txdlyovrden_usp_in[0] = \<const0> ;
  assign txdlysreset_us_in[1] = \<const0> ;
  assign txdlysreset_us_in[0] = \<const0> ;
  assign txdlysreset_usp_in[1] = \<const0> ;
  assign txdlysreset_usp_in[0] = \<const0> ;
  assign txdlyupdown_us_in[1] = \<const0> ;
  assign txdlyupdown_us_in[0] = \<const0> ;
  assign txdlyupdown_usp_in[1] = \<const0> ;
  assign txdlyupdown_usp_in[0] = \<const0> ;
  assign txelecidle_us_in[1] = \<const0> ;
  assign txelecidle_us_in[0] = \<const0> ;
  assign txelecidle_usp_in[1] = \<const0> ;
  assign txelecidle_usp_in[0] = \<const0> ;
  assign txinhibit_us_in[1] = \<const0> ;
  assign txinhibit_us_in[0] = \<const0> ;
  assign txmaincursor_us_in[13] = \<const0> ;
  assign txmaincursor_us_in[12] = \<const0> ;
  assign txmaincursor_us_in[11] = \<const0> ;
  assign txmaincursor_us_in[10] = \<const0> ;
  assign txmaincursor_us_in[9] = \<const0> ;
  assign txmaincursor_us_in[8] = \<const0> ;
  assign txmaincursor_us_in[7] = \<const0> ;
  assign txmaincursor_us_in[6] = \<const0> ;
  assign txmaincursor_us_in[5] = \<const0> ;
  assign txmaincursor_us_in[4] = \<const0> ;
  assign txmaincursor_us_in[3] = \<const0> ;
  assign txmaincursor_us_in[2] = \<const0> ;
  assign txmaincursor_us_in[1] = \<const0> ;
  assign txmaincursor_us_in[0] = \<const0> ;
  assign txmaincursor_usp_in[13] = \<const0> ;
  assign txmaincursor_usp_in[12] = \<const0> ;
  assign txmaincursor_usp_in[11] = \<const0> ;
  assign txmaincursor_usp_in[10] = \<const0> ;
  assign txmaincursor_usp_in[9] = \<const0> ;
  assign txmaincursor_usp_in[8] = \<const0> ;
  assign txmaincursor_usp_in[7] = \<const0> ;
  assign txmaincursor_usp_in[6] = \<const0> ;
  assign txmaincursor_usp_in[5] = \<const0> ;
  assign txmaincursor_usp_in[4] = \<const0> ;
  assign txmaincursor_usp_in[3] = \<const0> ;
  assign txmaincursor_usp_in[2] = \<const0> ;
  assign txmaincursor_usp_in[1] = \<const0> ;
  assign txmaincursor_usp_in[0] = \<const0> ;
  assign txmargin_us_in[5] = \<const0> ;
  assign txmargin_us_in[4] = \<const0> ;
  assign txmargin_us_in[3] = \<const0> ;
  assign txmargin_us_in[2] = \<const0> ;
  assign txmargin_us_in[1] = \<const0> ;
  assign txmargin_us_in[0] = \<const0> ;
  assign txmargin_usp_in[5] = \<const0> ;
  assign txmargin_usp_in[4] = \<const0> ;
  assign txmargin_usp_in[3] = \<const0> ;
  assign txmargin_usp_in[2] = \<const0> ;
  assign txmargin_usp_in[1] = \<const0> ;
  assign txmargin_usp_in[0] = \<const0> ;
  assign txoutclksel_us_in[5] = \<const0> ;
  assign txoutclksel_us_in[4] = \<const0> ;
  assign txoutclksel_us_in[3] = \<const0> ;
  assign txoutclksel_us_in[2] = \<const0> ;
  assign txoutclksel_us_in[1] = \<const0> ;
  assign txoutclksel_us_in[0] = \<const0> ;
  assign txoutclksel_usp_in[5] = \<const0> ;
  assign txoutclksel_usp_in[4] = \<const0> ;
  assign txoutclksel_usp_in[3] = \<const0> ;
  assign txoutclksel_usp_in[2] = \<const0> ;
  assign txoutclksel_usp_in[1] = \<const0> ;
  assign txoutclksel_usp_in[0] = \<const0> ;
  assign txpcsreset_usp_in[1] = \<const0> ;
  assign txpcsreset_usp_in[0] = \<const0> ;
  assign txpd_us_in[3] = \<const0> ;
  assign txpd_us_in[2] = \<const0> ;
  assign txpd_us_in[1] = \<const0> ;
  assign txpd_us_in[0] = \<const0> ;
  assign txpd_usp_in[3] = \<const0> ;
  assign txpd_usp_in[2] = \<const0> ;
  assign txpd_usp_in[1] = \<const0> ;
  assign txpd_usp_in[0] = \<const0> ;
  assign txpdelecidlemode_usp_in[1] = \<const0> ;
  assign txpdelecidlemode_usp_in[0] = \<const0> ;
  assign txphalign_us_in[1] = \<const0> ;
  assign txphalign_us_in[0] = \<const0> ;
  assign txphalign_usp_in[1] = \<const0> ;
  assign txphalign_usp_in[0] = \<const0> ;
  assign txphalignen_us_in[1] = \<const0> ;
  assign txphalignen_us_in[0] = \<const0> ;
  assign txphalignen_usp_in[1] = \<const0> ;
  assign txphalignen_usp_in[0] = \<const0> ;
  assign txphdlypd_us_in[1] = \<const0> ;
  assign txphdlypd_us_in[0] = \<const0> ;
  assign txphdlypd_usp_in[1] = \<const0> ;
  assign txphdlypd_usp_in[0] = \<const0> ;
  assign txphdlyreset_us_in[1] = \<const0> ;
  assign txphdlyreset_us_in[0] = \<const0> ;
  assign txphdlyreset_usp_in[1] = \<const0> ;
  assign txphdlyreset_usp_in[0] = \<const0> ;
  assign txphdlytstclk_us_in[1] = \<const0> ;
  assign txphdlytstclk_us_in[0] = \<const0> ;
  assign txphdlytstclk_usp_in[1] = \<const0> ;
  assign txphdlytstclk_usp_in[0] = \<const0> ;
  assign txphinit_us_in[1] = \<const0> ;
  assign txphinit_us_in[0] = \<const0> ;
  assign txphinit_usp_in[1] = \<const0> ;
  assign txphinit_usp_in[0] = \<const0> ;
  assign txphovrden_us_in[1] = \<const0> ;
  assign txphovrden_us_in[0] = \<const0> ;
  assign txphovrden_usp_in[1] = \<const0> ;
  assign txphovrden_usp_in[0] = \<const0> ;
  assign txpisopd_usp_in[1] = \<const0> ;
  assign txpisopd_usp_in[0] = \<const0> ;
  assign txpmareset_usp_in[1] = \<const0> ;
  assign txpmareset_usp_in[0] = \<const0> ;
  assign txpostcursor_us_in[9] = \<const0> ;
  assign txpostcursor_us_in[8] = \<const0> ;
  assign txpostcursor_us_in[7] = \<const0> ;
  assign txpostcursor_us_in[6] = \<const0> ;
  assign txpostcursor_us_in[5] = \<const0> ;
  assign txpostcursor_us_in[4] = \<const0> ;
  assign txpostcursor_us_in[3] = \<const0> ;
  assign txpostcursor_us_in[2] = \<const0> ;
  assign txpostcursor_us_in[1] = \<const0> ;
  assign txpostcursor_us_in[0] = \<const0> ;
  assign txpostcursor_usp_in[9] = \<const0> ;
  assign txpostcursor_usp_in[8] = \<const0> ;
  assign txpostcursor_usp_in[7] = \<const0> ;
  assign txpostcursor_usp_in[6] = \<const0> ;
  assign txpostcursor_usp_in[5] = \<const0> ;
  assign txpostcursor_usp_in[4] = \<const0> ;
  assign txpostcursor_usp_in[3] = \<const0> ;
  assign txpostcursor_usp_in[2] = \<const0> ;
  assign txpostcursor_usp_in[1] = \<const0> ;
  assign txpostcursor_usp_in[0] = \<const0> ;
  assign txprbsforceerr_us_in[1] = \<const0> ;
  assign txprbsforceerr_us_in[0] = \<const0> ;
  assign txprbsforceerr_usp_in[1] = \<const0> ;
  assign txprbsforceerr_usp_in[0] = \<const0> ;
  assign txprbssel_us_in[7] = \<const0> ;
  assign txprbssel_us_in[6] = \<const0> ;
  assign txprbssel_us_in[5] = \<const0> ;
  assign txprbssel_us_in[4] = \<const0> ;
  assign txprbssel_us_in[3] = \<const0> ;
  assign txprbssel_us_in[2] = \<const0> ;
  assign txprbssel_us_in[1] = \<const0> ;
  assign txprbssel_us_in[0] = \<const0> ;
  assign txprbssel_usp_in[7] = \<const0> ;
  assign txprbssel_usp_in[6] = \<const0> ;
  assign txprbssel_usp_in[5] = \<const0> ;
  assign txprbssel_usp_in[4] = \<const0> ;
  assign txprbssel_usp_in[3] = \<const0> ;
  assign txprbssel_usp_in[2] = \<const0> ;
  assign txprbssel_usp_in[1] = \<const0> ;
  assign txprbssel_usp_in[0] = \<const0> ;
  assign txprecursor_us_in[9] = \<const0> ;
  assign txprecursor_us_in[8] = \<const0> ;
  assign txprecursor_us_in[7] = \<const0> ;
  assign txprecursor_us_in[6] = \<const0> ;
  assign txprecursor_us_in[5] = \<const0> ;
  assign txprecursor_us_in[4] = \<const0> ;
  assign txprecursor_us_in[3] = \<const0> ;
  assign txprecursor_us_in[2] = \<const0> ;
  assign txprecursor_us_in[1] = \<const0> ;
  assign txprecursor_us_in[0] = \<const0> ;
  assign txprecursor_usp_in[9] = \<const0> ;
  assign txprecursor_usp_in[8] = \<const0> ;
  assign txprecursor_usp_in[7] = \<const0> ;
  assign txprecursor_usp_in[6] = \<const0> ;
  assign txprecursor_usp_in[5] = \<const0> ;
  assign txprecursor_usp_in[4] = \<const0> ;
  assign txprecursor_usp_in[3] = \<const0> ;
  assign txprecursor_usp_in[2] = \<const0> ;
  assign txprecursor_usp_in[1] = \<const0> ;
  assign txprecursor_usp_in[0] = \<const0> ;
  assign txprogdivreset_us_in[1] = \<const0> ;
  assign txprogdivreset_us_in[0] = \<const0> ;
  assign txprogdivreset_usp_in[1] = \<const0> ;
  assign txprogdivreset_usp_in[0] = \<const0> ;
  assign txrate_us_in[5] = \<const0> ;
  assign txrate_us_in[4] = \<const0> ;
  assign txrate_us_in[3] = \<const0> ;
  assign txrate_us_in[2] = \<const0> ;
  assign txrate_us_in[1] = \<const0> ;
  assign txrate_us_in[0] = \<const0> ;
  assign txrate_usp_in[5] = \<const0> ;
  assign txrate_usp_in[4] = \<const0> ;
  assign txrate_usp_in[3] = \<const0> ;
  assign txrate_usp_in[2] = \<const0> ;
  assign txrate_usp_in[1] = \<const0> ;
  assign txrate_usp_in[0] = \<const0> ;
  assign txswing_us_in[1] = \<const0> ;
  assign txswing_us_in[0] = \<const0> ;
  assign txswing_usp_in[1] = \<const0> ;
  assign txswing_usp_in[0] = \<const0> ;
  assign txsyncallin_us_in[1] = \<const0> ;
  assign txsyncallin_us_in[0] = \<const0> ;
  assign txsyncallin_usp_in[1] = \<const0> ;
  assign txsyncallin_usp_in[0] = \<const0> ;
  assign txsyncin_us_in[1] = \<const0> ;
  assign txsyncin_us_in[0] = \<const0> ;
  assign txsyncin_usp_in[1] = \<const0> ;
  assign txsyncin_usp_in[0] = \<const0> ;
  assign txsyncmode_us_in[1] = \<const0> ;
  assign txsyncmode_us_in[0] = \<const0> ;
  assign txsyncmode_usp_in[1] = \<const0> ;
  assign txsyncmode_usp_in[0] = \<const0> ;
  assign txuserrdy_us_in[1] = \<const0> ;
  assign txuserrdy_us_in[0] = \<const0> ;
  assign txuserrdy_usp_in[1] = \<const0> ;
  assign txuserrdy_usp_in[0] = \<const0> ;
  assign txusrclk2_us_in[1] = \<const0> ;
  assign txusrclk2_us_in[0] = \<const0> ;
  assign txusrclk2_usp_in[1] = \<const0> ;
  assign txusrclk2_usp_in[0] = \<const0> ;
  assign txusrclk_us_in[1] = \<const0> ;
  assign txusrclk_us_in[0] = \<const0> ;
  assign txusrclk_usp_in[1] = \<const0> ;
  assign txusrclk_usp_in[0] = \<const0> ;
  assign usr_flr_clr = \<const0> ;
  assign usr_flr_fnc[7] = \<const0> ;
  assign usr_flr_fnc[6] = \<const0> ;
  assign usr_flr_fnc[5] = \<const0> ;
  assign usr_flr_fnc[4] = \<const0> ;
  assign usr_flr_fnc[3] = \<const0> ;
  assign usr_flr_fnc[2] = \<const0> ;
  assign usr_flr_fnc[1] = \<const0> ;
  assign usr_flr_fnc[0] = \<const0> ;
  assign usr_flr_set = \<const0> ;
  assign wr_interrupt = \<const0> ;
  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(n_0_0));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(n_0_1));
  LUT1 #(
    .INIT(2'h2)) 
    i_100
       (.I0(1'b0),
        .O(n_0_100));
  LUT1 #(
    .INIT(2'h2)) 
    i_101
       (.I0(1'b0),
        .O(n_0_101));
  LUT1 #(
    .INIT(2'h2)) 
    i_102
       (.I0(1'b0),
        .O(n_0_102));
  LUT1 #(
    .INIT(2'h2)) 
    i_103
       (.I0(1'b0),
        .O(n_0_103));
  LUT1 #(
    .INIT(2'h2)) 
    i_104
       (.I0(1'b0),
        .O(n_0_104));
  LUT1 #(
    .INIT(2'h2)) 
    i_105
       (.I0(1'b0),
        .O(n_0_105));
  LUT1 #(
    .INIT(2'h2)) 
    i_106
       (.I0(1'b0),
        .O(n_0_106));
  LUT1 #(
    .INIT(2'h2)) 
    i_107
       (.I0(1'b0),
        .O(n_0_107));
  LUT1 #(
    .INIT(2'h2)) 
    i_108
       (.I0(1'b0),
        .O(n_0_108));
  LUT1 #(
    .INIT(2'h2)) 
    i_109
       (.I0(1'b0),
        .O(n_0_109));
  LUT1 #(
    .INIT(2'h2)) 
    i_110
       (.I0(1'b0),
        .O(n_0_110));
  LUT1 #(
    .INIT(2'h2)) 
    i_111
       (.I0(1'b0),
        .O(n_0_111));
  LUT1 #(
    .INIT(2'h2)) 
    i_112
       (.I0(1'b0),
        .O(n_0_112));
  LUT1 #(
    .INIT(2'h2)) 
    i_113
       (.I0(1'b0),
        .O(n_0_113));
  LUT1 #(
    .INIT(2'h2)) 
    i_114
       (.I0(1'b0),
        .O(n_0_114));
  LUT1 #(
    .INIT(2'h2)) 
    i_115
       (.I0(1'b0),
        .O(n_0_115));
  LUT1 #(
    .INIT(2'h2)) 
    i_116
       (.I0(1'b0),
        .O(n_0_116));
  LUT1 #(
    .INIT(2'h2)) 
    i_117
       (.I0(1'b0),
        .O(n_0_117));
  LUT1 #(
    .INIT(2'h2)) 
    i_118
       (.I0(1'b0),
        .O(n_0_118));
  LUT1 #(
    .INIT(2'h2)) 
    i_119
       (.I0(1'b0),
        .O(n_0_119));
  LUT1 #(
    .INIT(2'h2)) 
    i_120
       (.I0(1'b0),
        .O(n_0_120));
  LUT1 #(
    .INIT(2'h2)) 
    i_121
       (.I0(1'b0),
        .O(n_0_121));
  LUT1 #(
    .INIT(2'h2)) 
    i_122
       (.I0(1'b0),
        .O(n_0_122));
  LUT1 #(
    .INIT(2'h2)) 
    i_123
       (.I0(1'b0),
        .O(n_0_123));
  LUT1 #(
    .INIT(2'h2)) 
    i_124
       (.I0(1'b0),
        .O(n_0_124));
  LUT1 #(
    .INIT(2'h2)) 
    i_125
       (.I0(1'b0),
        .O(n_0_125));
  LUT1 #(
    .INIT(2'h2)) 
    i_126
       (.I0(1'b0),
        .O(n_0_126));
  LUT1 #(
    .INIT(2'h2)) 
    i_127
       (.I0(1'b0),
        .O(n_0_127));
  LUT1 #(
    .INIT(2'h2)) 
    i_128
       (.I0(1'b0),
        .O(n_0_128));
  LUT1 #(
    .INIT(2'h2)) 
    i_129
       (.I0(1'b0),
        .O(n_0_129));
  LUT1 #(
    .INIT(2'h2)) 
    i_130
       (.I0(1'b0),
        .O(n_0_130));
  LUT1 #(
    .INIT(2'h2)) 
    i_131
       (.I0(1'b0),
        .O(n_0_131));
  LUT1 #(
    .INIT(2'h2)) 
    i_132
       (.I0(1'b0),
        .O(n_0_132));
  LUT1 #(
    .INIT(2'h2)) 
    i_133
       (.I0(1'b0),
        .O(n_0_133));
  LUT1 #(
    .INIT(2'h2)) 
    i_134
       (.I0(1'b0),
        .O(n_0_134));
  LUT1 #(
    .INIT(2'h2)) 
    i_135
       (.I0(1'b0),
        .O(n_0_135));
  LUT1 #(
    .INIT(2'h2)) 
    i_136
       (.I0(1'b0),
        .O(n_0_136));
  LUT1 #(
    .INIT(2'h2)) 
    i_137
       (.I0(1'b0),
        .O(n_0_137));
  LUT1 #(
    .INIT(2'h2)) 
    i_138
       (.I0(1'b0),
        .O(n_0_138));
  LUT1 #(
    .INIT(2'h2)) 
    i_139
       (.I0(1'b0),
        .O(n_0_139));
  LUT1 #(
    .INIT(2'h2)) 
    i_140
       (.I0(1'b0),
        .O(n_0_140));
  LUT1 #(
    .INIT(2'h2)) 
    i_141
       (.I0(1'b0),
        .O(n_0_141));
  LUT1 #(
    .INIT(2'h2)) 
    i_142
       (.I0(1'b0),
        .O(n_0_142));
  LUT1 #(
    .INIT(2'h2)) 
    i_143
       (.I0(1'b0),
        .O(n_0_143));
  LUT1 #(
    .INIT(2'h2)) 
    i_144
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[31]));
  LUT1 #(
    .INIT(2'h2)) 
    i_145
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[30]));
  LUT1 #(
    .INIT(2'h2)) 
    i_146
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[29]));
  LUT1 #(
    .INIT(2'h2)) 
    i_147
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[28]));
  LUT1 #(
    .INIT(2'h2)) 
    i_148
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[27]));
  LUT1 #(
    .INIT(2'h2)) 
    i_149
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[26]));
  LUT1 #(
    .INIT(2'h2)) 
    i_150
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[25]));
  LUT1 #(
    .INIT(2'h2)) 
    i_151
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[24]));
  LUT1 #(
    .INIT(2'h2)) 
    i_152
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[23]));
  LUT1 #(
    .INIT(2'h2)) 
    i_153
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[22]));
  LUT1 #(
    .INIT(2'h2)) 
    i_154
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[21]));
  LUT1 #(
    .INIT(2'h2)) 
    i_155
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[20]));
  LUT1 #(
    .INIT(2'h2)) 
    i_156
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[19]));
  LUT1 #(
    .INIT(2'h2)) 
    i_157
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[18]));
  LUT1 #(
    .INIT(2'h2)) 
    i_158
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[17]));
  LUT1 #(
    .INIT(2'h2)) 
    i_159
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[16]));
  LUT1 #(
    .INIT(2'h2)) 
    i_16
       (.I0(1'b1),
        .O(n_0_16));
  LUT1 #(
    .INIT(2'h2)) 
    i_160
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[15]));
  LUT1 #(
    .INIT(2'h2)) 
    i_161
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[14]));
  LUT1 #(
    .INIT(2'h2)) 
    i_162
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[13]));
  LUT1 #(
    .INIT(2'h2)) 
    i_163
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[12]));
  LUT1 #(
    .INIT(2'h2)) 
    i_164
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[11]));
  LUT1 #(
    .INIT(2'h2)) 
    i_165
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[10]));
  LUT1 #(
    .INIT(2'h2)) 
    i_166
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[9]));
  LUT1 #(
    .INIT(2'h2)) 
    i_167
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[8]));
  LUT1 #(
    .INIT(2'h2)) 
    i_168
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[7]));
  LUT1 #(
    .INIT(2'h2)) 
    i_169
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[6]));
  LUT1 #(
    .INIT(2'h2)) 
    i_17
       (.I0(1'b1),
        .O(n_0_17));
  LUT1 #(
    .INIT(2'h2)) 
    i_170
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[5]));
  LUT1 #(
    .INIT(2'h2)) 
    i_171
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[4]));
  LUT1 #(
    .INIT(2'h2)) 
    i_172
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[3]));
  LUT1 #(
    .INIT(2'h2)) 
    i_173
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_174
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_175
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_176
       (.I0(1'b0),
        .O(blk_cfg_ext_read_data_valid));
  LUT1 #(
    .INIT(2'h2)) 
    i_177
       (.I0(1'b0),
        .O(n_0_177));
  LUT1 #(
    .INIT(2'h2)) 
    i_178
       (.I0(1'b0),
        .O(n_0_178));
  LUT1 #(
    .INIT(2'h2)) 
    i_179
       (.I0(1'b0),
        .O(n_0_179));
  LUT1 #(
    .INIT(2'h2)) 
    i_18
       (.I0(1'b1),
        .O(n_0_18));
  LUT1 #(
    .INIT(2'h2)) 
    i_180
       (.I0(1'b0),
        .O(n_0_180));
  LUT1 #(
    .INIT(2'h2)) 
    i_181
       (.I0(1'b0),
        .O(n_0_181));
  LUT1 #(
    .INIT(2'h2)) 
    i_182
       (.I0(1'b0),
        .O(n_0_182));
  LUT1 #(
    .INIT(2'h2)) 
    i_183
       (.I0(1'b0),
        .O(n_0_183));
  LUT1 #(
    .INIT(2'h2)) 
    i_184
       (.I0(1'b0),
        .O(n_0_184));
  LUT1 #(
    .INIT(2'h2)) 
    i_185
       (.I0(1'b0),
        .O(n_0_185));
  LUT1 #(
    .INIT(2'h2)) 
    i_186
       (.I0(1'b0),
        .O(n_0_186));
  LUT1 #(
    .INIT(2'h2)) 
    i_187
       (.I0(1'b0),
        .O(n_0_187));
  LUT1 #(
    .INIT(2'h2)) 
    i_188
       (.I0(1'b0),
        .O(n_0_188));
  LUT1 #(
    .INIT(2'h2)) 
    i_189
       (.I0(1'b0),
        .O(n_0_189));
  LUT1 #(
    .INIT(2'h2)) 
    i_19
       (.I0(1'b1),
        .O(n_0_19));
  LUT1 #(
    .INIT(2'h2)) 
    i_190
       (.I0(1'b0),
        .O(n_0_190));
  LUT1 #(
    .INIT(2'h2)) 
    i_191
       (.I0(1'b0),
        .O(n_0_191));
  LUT1 #(
    .INIT(2'h2)) 
    i_192
       (.I0(1'b0),
        .O(n_0_192));
  LUT1 #(
    .INIT(2'h2)) 
    i_193
       (.I0(1'b0),
        .O(n_0_193));
  LUT1 #(
    .INIT(2'h2)) 
    i_194
       (.I0(1'b0),
        .O(n_0_194));
  LUT1 #(
    .INIT(2'h2)) 
    i_195
       (.I0(1'b0),
        .O(n_0_195));
  LUT1 #(
    .INIT(2'h2)) 
    i_196
       (.I0(1'b0),
        .O(n_0_196));
  LUT1 #(
    .INIT(2'h2)) 
    i_197
       (.I0(1'b0),
        .O(n_0_197));
  LUT1 #(
    .INIT(2'h2)) 
    i_198
       (.I0(1'b0),
        .O(n_0_198));
  LUT1 #(
    .INIT(2'h2)) 
    i_199
       (.I0(1'b0),
        .O(n_0_199));
  LUT1 #(
    .INIT(2'h2)) 
    i_20
       (.I0(1'b1),
        .O(n_0_20));
  LUT1 #(
    .INIT(2'h2)) 
    i_200
       (.I0(1'b0),
        .O(n_0_200));
  LUT1 #(
    .INIT(2'h2)) 
    i_201
       (.I0(1'b0),
        .O(n_0_201));
  LUT1 #(
    .INIT(2'h2)) 
    i_202
       (.I0(1'b0),
        .O(n_0_202));
  LUT1 #(
    .INIT(2'h2)) 
    i_203
       (.I0(1'b0),
        .O(n_0_203));
  LUT1 #(
    .INIT(2'h2)) 
    i_204
       (.I0(1'b0),
        .O(n_0_204));
  LUT1 #(
    .INIT(2'h2)) 
    i_205
       (.I0(1'b0),
        .O(n_0_205));
  LUT1 #(
    .INIT(2'h2)) 
    i_206
       (.I0(1'b0),
        .O(n_0_206));
  LUT1 #(
    .INIT(2'h2)) 
    i_207
       (.I0(1'b0),
        .O(n_0_207));
  LUT1 #(
    .INIT(2'h2)) 
    i_208
       (.I0(1'b0),
        .O(n_0_208));
  LUT1 #(
    .INIT(2'h2)) 
    i_209
       (.I0(1'b0),
        .O(n_0_209));
  LUT1 #(
    .INIT(2'h2)) 
    i_21
       (.I0(1'b1),
        .O(n_0_21));
  LUT1 #(
    .INIT(2'h2)) 
    i_210
       (.I0(1'b0),
        .O(n_0_210));
  LUT1 #(
    .INIT(2'h2)) 
    i_211
       (.I0(1'b0),
        .O(n_0_211));
  LUT1 #(
    .INIT(2'h2)) 
    i_212
       (.I0(1'b0),
        .O(n_0_212));
  LUT1 #(
    .INIT(2'h2)) 
    i_213
       (.I0(1'b0),
        .O(n_0_213));
  LUT1 #(
    .INIT(2'h2)) 
    i_214
       (.I0(1'b0),
        .O(n_0_214));
  LUT1 #(
    .INIT(2'h2)) 
    i_215
       (.I0(1'b0),
        .O(n_0_215));
  LUT1 #(
    .INIT(2'h2)) 
    i_216
       (.I0(1'b0),
        .O(n_0_216));
  LUT1 #(
    .INIT(2'h2)) 
    i_217
       (.I0(1'b0),
        .O(n_0_217));
  LUT1 #(
    .INIT(2'h2)) 
    i_218
       (.I0(1'b0),
        .O(n_0_218));
  LUT1 #(
    .INIT(2'h2)) 
    i_219
       (.I0(1'b0),
        .O(n_0_219));
  LUT1 #(
    .INIT(2'h2)) 
    i_22
       (.I0(1'b1),
        .O(n_0_22));
  LUT1 #(
    .INIT(2'h2)) 
    i_220
       (.I0(1'b0),
        .O(n_0_220));
  LUT1 #(
    .INIT(2'h2)) 
    i_221
       (.I0(1'b0),
        .O(n_0_221));
  LUT1 #(
    .INIT(2'h2)) 
    i_222
       (.I0(1'b0),
        .O(n_0_222));
  LUT1 #(
    .INIT(2'h2)) 
    i_223
       (.I0(1'b0),
        .O(n_0_223));
  LUT1 #(
    .INIT(2'h2)) 
    i_224
       (.I0(1'b0),
        .O(n_0_224));
  LUT1 #(
    .INIT(2'h2)) 
    i_225
       (.I0(1'b0),
        .O(n_0_225));
  LUT1 #(
    .INIT(2'h2)) 
    i_226
       (.I0(1'b0),
        .O(n_0_226));
  LUT1 #(
    .INIT(2'h2)) 
    i_227
       (.I0(1'b0),
        .O(n_0_227));
  LUT1 #(
    .INIT(2'h2)) 
    i_228
       (.I0(1'b0),
        .O(n_0_228));
  LUT1 #(
    .INIT(2'h2)) 
    i_229
       (.I0(1'b0),
        .O(n_0_229));
  LUT1 #(
    .INIT(2'h2)) 
    i_23
       (.I0(1'b1),
        .O(n_0_23));
  LUT1 #(
    .INIT(2'h2)) 
    i_230
       (.I0(1'b0),
        .O(n_0_230));
  LUT1 #(
    .INIT(2'h2)) 
    i_231
       (.I0(1'b0),
        .O(n_0_231));
  LUT1 #(
    .INIT(2'h2)) 
    i_232
       (.I0(1'b0),
        .O(n_0_232));
  LUT1 #(
    .INIT(2'h2)) 
    i_233
       (.I0(1'b0),
        .O(n_0_233));
  LUT1 #(
    .INIT(2'h2)) 
    i_234
       (.I0(1'b0),
        .O(n_0_234));
  LUT1 #(
    .INIT(2'h2)) 
    i_235
       (.I0(1'b0),
        .O(n_0_235));
  LUT1 #(
    .INIT(2'h2)) 
    i_236
       (.I0(1'b0),
        .O(n_0_236));
  LUT1 #(
    .INIT(2'h2)) 
    i_237
       (.I0(1'b0),
        .O(n_0_237));
  LUT1 #(
    .INIT(2'h2)) 
    i_238
       (.I0(1'b0),
        .O(n_0_238));
  LUT1 #(
    .INIT(2'h2)) 
    i_239
       (.I0(1'b0),
        .O(n_0_239));
  LUT1 #(
    .INIT(2'h2)) 
    i_240
       (.I0(1'b0),
        .O(n_0_240));
  LUT1 #(
    .INIT(2'h2)) 
    i_241
       (.I0(1'b0),
        .O(n_0_241));
  LUT1 #(
    .INIT(2'h2)) 
    i_242
       (.I0(1'b0),
        .O(n_0_242));
  LUT1 #(
    .INIT(2'h2)) 
    i_243
       (.I0(1'b0),
        .O(n_0_243));
  LUT1 #(
    .INIT(2'h2)) 
    i_244
       (.I0(1'b0),
        .O(n_0_244));
  LUT1 #(
    .INIT(2'h2)) 
    i_245
       (.I0(1'b0),
        .O(n_0_245));
  LUT1 #(
    .INIT(2'h2)) 
    i_246
       (.I0(1'b0),
        .O(n_0_246));
  LUT1 #(
    .INIT(2'h2)) 
    i_247
       (.I0(1'b0),
        .O(n_0_247));
  LUT1 #(
    .INIT(2'h2)) 
    i_248
       (.I0(1'b0),
        .O(n_0_248));
  LUT1 #(
    .INIT(2'h2)) 
    i_249
       (.I0(1'b0),
        .O(n_0_249));
  LUT1 #(
    .INIT(2'h2)) 
    i_250
       (.I0(1'b0),
        .O(n_0_250));
  LUT1 #(
    .INIT(2'h2)) 
    i_251
       (.I0(1'b0),
        .O(n_0_251));
  LUT1 #(
    .INIT(2'h2)) 
    i_252
       (.I0(1'b0),
        .O(n_0_252));
  LUT1 #(
    .INIT(2'h2)) 
    i_253
       (.I0(1'b0),
        .O(n_0_253));
  LUT1 #(
    .INIT(2'h2)) 
    i_254
       (.I0(1'b0),
        .O(n_0_254));
  LUT1 #(
    .INIT(2'h2)) 
    i_255
       (.I0(1'b0),
        .O(n_0_255));
  LUT1 #(
    .INIT(2'h2)) 
    i_256
       (.I0(1'b0),
        .O(n_0_256));
  LUT1 #(
    .INIT(2'h2)) 
    i_257
       (.I0(1'b0),
        .O(n_0_257));
  LUT1 #(
    .INIT(2'h2)) 
    i_258
       (.I0(1'b0),
        .O(n_0_258));
  LUT1 #(
    .INIT(2'h2)) 
    i_259
       (.I0(1'b0),
        .O(n_0_259));
  LUT1 #(
    .INIT(2'h2)) 
    i_260
       (.I0(1'b0),
        .O(n_0_260));
  LUT1 #(
    .INIT(2'h2)) 
    i_261
       (.I0(1'b0),
        .O(n_0_261));
  LUT1 #(
    .INIT(2'h2)) 
    i_262
       (.I0(1'b0),
        .O(n_0_262));
  LUT1 #(
    .INIT(2'h2)) 
    i_263
       (.I0(1'b0),
        .O(n_0_263));
  LUT1 #(
    .INIT(2'h2)) 
    i_264
       (.I0(1'b0),
        .O(n_0_264));
  LUT1 #(
    .INIT(2'h2)) 
    i_265
       (.I0(1'b0),
        .O(n_0_265));
  LUT1 #(
    .INIT(2'h2)) 
    i_266
       (.I0(1'b0),
        .O(n_0_266));
  LUT1 #(
    .INIT(2'h2)) 
    i_267
       (.I0(1'b0),
        .O(n_0_267));
  LUT1 #(
    .INIT(2'h2)) 
    i_268
       (.I0(1'b0),
        .O(n_0_268));
  LUT1 #(
    .INIT(2'h2)) 
    i_269
       (.I0(1'b0),
        .O(n_0_269));
  LUT1 #(
    .INIT(2'h2)) 
    i_270
       (.I0(1'b0),
        .O(n_0_270));
  LUT1 #(
    .INIT(2'h2)) 
    i_271
       (.I0(1'b0),
        .O(n_0_271));
  LUT1 #(
    .INIT(2'h2)) 
    i_272
       (.I0(1'b0),
        .O(n_0_272));
  LUT1 #(
    .INIT(2'h2)) 
    i_273
       (.I0(1'b0),
        .O(n_0_273));
  LUT1 #(
    .INIT(2'h2)) 
    i_274
       (.I0(1'b0),
        .O(n_0_274));
  LUT1 #(
    .INIT(2'h2)) 
    i_275
       (.I0(1'b0),
        .O(n_0_275));
  LUT1 #(
    .INIT(2'h2)) 
    i_276
       (.I0(1'b0),
        .O(n_0_276));
  LUT1 #(
    .INIT(2'h2)) 
    i_277
       (.I0(1'b0),
        .O(n_0_277));
  LUT1 #(
    .INIT(2'h2)) 
    i_278
       (.I0(1'b0),
        .O(n_0_278));
  LUT1 #(
    .INIT(2'h2)) 
    i_279
       (.I0(1'b0),
        .O(n_0_279));
  LUT1 #(
    .INIT(2'h2)) 
    i_280
       (.I0(1'b0),
        .O(n_0_280));
  LUT1 #(
    .INIT(2'h2)) 
    i_281
       (.I0(1'b0),
        .O(n_0_281));
  LUT1 #(
    .INIT(2'h2)) 
    i_282
       (.I0(1'b0),
        .O(n_0_282));
  LUT1 #(
    .INIT(2'h2)) 
    i_283
       (.I0(1'b0),
        .O(n_0_283));
  LUT1 #(
    .INIT(2'h2)) 
    i_284
       (.I0(1'b0),
        .O(n_0_284));
  LUT1 #(
    .INIT(2'h2)) 
    i_285
       (.I0(1'b0),
        .O(n_0_285));
  LUT1 #(
    .INIT(2'h2)) 
    i_286
       (.I0(1'b0),
        .O(n_0_286));
  LUT1 #(
    .INIT(2'h2)) 
    i_287
       (.I0(1'b0),
        .O(n_0_287));
  LUT1 #(
    .INIT(2'h2)) 
    i_288
       (.I0(1'b0),
        .O(n_0_288));
  LUT1 #(
    .INIT(2'h2)) 
    i_289
       (.I0(1'b0),
        .O(n_0_289));
  LUT1 #(
    .INIT(2'h2)) 
    i_290
       (.I0(1'b0),
        .O(n_0_290));
  LUT1 #(
    .INIT(2'h2)) 
    i_291
       (.I0(1'b0),
        .O(n_0_291));
  LUT1 #(
    .INIT(2'h2)) 
    i_292
       (.I0(1'b0),
        .O(n_0_292));
  LUT1 #(
    .INIT(2'h2)) 
    i_293
       (.I0(1'b0),
        .O(n_0_293));
  LUT1 #(
    .INIT(2'h2)) 
    i_294
       (.I0(1'b0),
        .O(n_0_294));
  LUT1 #(
    .INIT(2'h2)) 
    i_295
       (.I0(1'b0),
        .O(n_0_295));
  LUT1 #(
    .INIT(2'h2)) 
    i_296
       (.I0(1'b0),
        .O(n_0_296));
  LUT1 #(
    .INIT(2'h2)) 
    i_297
       (.I0(1'b0),
        .O(n_0_297));
  LUT1 #(
    .INIT(2'h2)) 
    i_298
       (.I0(1'b0),
        .O(n_0_298));
  LUT1 #(
    .INIT(2'h2)) 
    i_299
       (.I0(1'b0),
        .O(n_0_299));
  LUT1 #(
    .INIT(2'h2)) 
    i_300
       (.I0(1'b0),
        .O(n_0_300));
  LUT1 #(
    .INIT(2'h2)) 
    i_301
       (.I0(1'b0),
        .O(n_0_301));
  LUT1 #(
    .INIT(2'h2)) 
    i_302
       (.I0(1'b0),
        .O(n_0_302));
  LUT1 #(
    .INIT(2'h2)) 
    i_303
       (.I0(1'b0),
        .O(n_0_303));
  LUT1 #(
    .INIT(2'h2)) 
    i_304
       (.I0(1'b0),
        .O(n_0_304));
  LUT1 #(
    .INIT(2'h2)) 
    i_305
       (.I0(1'b0),
        .O(n_0_305));
  LUT1 #(
    .INIT(2'h2)) 
    i_306
       (.I0(1'b0),
        .O(n_0_306));
  LUT1 #(
    .INIT(2'h2)) 
    i_307
       (.I0(1'b0),
        .O(n_0_307));
  LUT1 #(
    .INIT(2'h2)) 
    i_308
       (.I0(1'b0),
        .O(n_0_308));
  LUT1 #(
    .INIT(2'h2)) 
    i_309
       (.I0(1'b0),
        .O(n_0_309));
  LUT1 #(
    .INIT(2'h2)) 
    i_310
       (.I0(1'b0),
        .O(n_0_310));
  LUT1 #(
    .INIT(2'h2)) 
    i_311
       (.I0(1'b0),
        .O(n_0_311));
  LUT1 #(
    .INIT(2'h2)) 
    i_312
       (.I0(1'b0),
        .O(n_0_312));
  LUT1 #(
    .INIT(2'h2)) 
    i_313
       (.I0(1'b0),
        .O(n_0_313));
  LUT1 #(
    .INIT(2'h2)) 
    i_314
       (.I0(1'b0),
        .O(n_0_314));
  LUT1 #(
    .INIT(2'h2)) 
    i_315
       (.I0(1'b0),
        .O(n_0_315));
  LUT1 #(
    .INIT(2'h2)) 
    i_316
       (.I0(1'b0),
        .O(n_0_316));
  LUT1 #(
    .INIT(2'h2)) 
    i_317
       (.I0(1'b0),
        .O(n_0_317));
  LUT1 #(
    .INIT(2'h2)) 
    i_318
       (.I0(1'b0),
        .O(n_0_318));
  LUT1 #(
    .INIT(2'h2)) 
    i_319
       (.I0(1'b0),
        .O(n_0_319));
  LUT1 #(
    .INIT(2'h2)) 
    i_320
       (.I0(1'b0),
        .O(n_0_320));
  LUT1 #(
    .INIT(2'h2)) 
    i_321
       (.I0(1'b0),
        .O(n_0_321));
  LUT1 #(
    .INIT(2'h2)) 
    i_322
       (.I0(1'b0),
        .O(n_0_322));
  LUT1 #(
    .INIT(2'h2)) 
    i_323
       (.I0(1'b0),
        .O(n_0_323));
  LUT1 #(
    .INIT(2'h2)) 
    i_324
       (.I0(1'b0),
        .O(n_0_324));
  LUT1 #(
    .INIT(2'h2)) 
    i_325
       (.I0(1'b0),
        .O(n_0_325));
  LUT1 #(
    .INIT(2'h2)) 
    i_326
       (.I0(1'b0),
        .O(n_0_326));
  LUT1 #(
    .INIT(2'h2)) 
    i_327
       (.I0(1'b0),
        .O(n_0_327));
  LUT1 #(
    .INIT(2'h2)) 
    i_328
       (.I0(1'b0),
        .O(n_0_328));
  LUT1 #(
    .INIT(2'h2)) 
    i_329
       (.I0(1'b0),
        .O(n_0_329));
  LUT1 #(
    .INIT(2'h2)) 
    i_330
       (.I0(1'b0),
        .O(n_0_330));
  LUT1 #(
    .INIT(2'h2)) 
    i_331
       (.I0(1'b0),
        .O(n_0_331));
  LUT1 #(
    .INIT(2'h2)) 
    i_332
       (.I0(1'b0),
        .O(n_0_332));
  LUT1 #(
    .INIT(2'h2)) 
    i_333
       (.I0(1'b0),
        .O(n_0_333));
  LUT1 #(
    .INIT(2'h2)) 
    i_334
       (.I0(1'b0),
        .O(n_0_334));
  LUT1 #(
    .INIT(2'h2)) 
    i_335
       (.I0(1'b0),
        .O(n_0_335));
  LUT1 #(
    .INIT(2'h2)) 
    i_336
       (.I0(1'b0),
        .O(n_0_336));
  LUT1 #(
    .INIT(2'h2)) 
    i_337
       (.I0(1'b0),
        .O(n_0_337));
  LUT1 #(
    .INIT(2'h2)) 
    i_338
       (.I0(1'b0),
        .O(n_0_338));
  LUT1 #(
    .INIT(2'h2)) 
    i_339
       (.I0(1'b0),
        .O(n_0_339));
  LUT1 #(
    .INIT(2'h2)) 
    i_340
       (.I0(1'b0),
        .O(n_0_340));
  LUT1 #(
    .INIT(2'h2)) 
    i_341
       (.I0(1'b0),
        .O(blk_cfg_ext_read_received));
  LUT1 #(
    .INIT(2'h2)) 
    i_342
       (.I0(1'b0),
        .O(blk_cfg_ext_write_received));
  LUT1 #(
    .INIT(2'h2)) 
    i_343
       (.I0(1'b0),
        .O(blk_cfg_ext_register_number[9]));
  LUT1 #(
    .INIT(2'h2)) 
    i_344
       (.I0(1'b0),
        .O(blk_cfg_ext_register_number[8]));
  LUT1 #(
    .INIT(2'h2)) 
    i_345
       (.I0(1'b0),
        .O(blk_cfg_ext_register_number[7]));
  LUT1 #(
    .INIT(2'h2)) 
    i_346
       (.I0(1'b0),
        .O(blk_cfg_ext_register_number[6]));
  LUT1 #(
    .INIT(2'h2)) 
    i_347
       (.I0(1'b0),
        .O(blk_cfg_ext_register_number[5]));
  LUT1 #(
    .INIT(2'h2)) 
    i_348
       (.I0(1'b0),
        .O(blk_cfg_ext_register_number[4]));
  LUT1 #(
    .INIT(2'h2)) 
    i_349
       (.I0(1'b0),
        .O(blk_cfg_ext_register_number[3]));
  LUT1 #(
    .INIT(2'h2)) 
    i_350
       (.I0(1'b0),
        .O(blk_cfg_ext_register_number[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_351
       (.I0(1'b0),
        .O(blk_cfg_ext_register_number[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_352
       (.I0(1'b0),
        .O(blk_cfg_ext_register_number[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_353
       (.I0(1'b0),
        .O(blk_cfg_ext_function_number[7]));
  LUT1 #(
    .INIT(2'h2)) 
    i_354
       (.I0(1'b0),
        .O(blk_cfg_ext_function_number[6]));
  LUT1 #(
    .INIT(2'h2)) 
    i_355
       (.I0(1'b0),
        .O(blk_cfg_ext_function_number[5]));
  LUT1 #(
    .INIT(2'h2)) 
    i_356
       (.I0(1'b0),
        .O(blk_cfg_ext_function_number[4]));
  LUT1 #(
    .INIT(2'h2)) 
    i_357
       (.I0(1'b0),
        .O(blk_cfg_ext_function_number[3]));
  LUT1 #(
    .INIT(2'h2)) 
    i_358
       (.I0(1'b0),
        .O(blk_cfg_ext_function_number[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_359
       (.I0(1'b0),
        .O(blk_cfg_ext_function_number[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_360
       (.I0(1'b0),
        .O(blk_cfg_ext_function_number[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_361
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[31]));
  LUT1 #(
    .INIT(2'h2)) 
    i_362
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[30]));
  LUT1 #(
    .INIT(2'h2)) 
    i_363
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[29]));
  LUT1 #(
    .INIT(2'h2)) 
    i_364
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[28]));
  LUT1 #(
    .INIT(2'h2)) 
    i_365
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[27]));
  LUT1 #(
    .INIT(2'h2)) 
    i_366
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[26]));
  LUT1 #(
    .INIT(2'h2)) 
    i_367
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[25]));
  LUT1 #(
    .INIT(2'h2)) 
    i_368
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[24]));
  LUT1 #(
    .INIT(2'h2)) 
    i_369
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[23]));
  LUT1 #(
    .INIT(2'h2)) 
    i_370
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[22]));
  LUT1 #(
    .INIT(2'h2)) 
    i_371
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[21]));
  LUT1 #(
    .INIT(2'h2)) 
    i_372
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[20]));
  LUT1 #(
    .INIT(2'h2)) 
    i_373
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[19]));
  LUT1 #(
    .INIT(2'h2)) 
    i_374
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[18]));
  LUT1 #(
    .INIT(2'h2)) 
    i_375
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[17]));
  LUT1 #(
    .INIT(2'h2)) 
    i_376
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[16]));
  LUT1 #(
    .INIT(2'h2)) 
    i_377
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[15]));
  LUT1 #(
    .INIT(2'h2)) 
    i_378
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[14]));
  LUT1 #(
    .INIT(2'h2)) 
    i_379
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[13]));
  LUT1 #(
    .INIT(2'h2)) 
    i_380
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[12]));
  LUT1 #(
    .INIT(2'h2)) 
    i_381
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[11]));
  LUT1 #(
    .INIT(2'h2)) 
    i_382
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[10]));
  LUT1 #(
    .INIT(2'h2)) 
    i_383
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[9]));
  LUT1 #(
    .INIT(2'h2)) 
    i_384
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[8]));
  LUT1 #(
    .INIT(2'h2)) 
    i_385
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[7]));
  LUT1 #(
    .INIT(2'h2)) 
    i_386
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[6]));
  LUT1 #(
    .INIT(2'h2)) 
    i_387
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[5]));
  LUT1 #(
    .INIT(2'h2)) 
    i_388
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[4]));
  LUT1 #(
    .INIT(2'h2)) 
    i_389
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[3]));
  LUT1 #(
    .INIT(2'h2)) 
    i_390
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_391
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_392
       (.I0(1'b0),
        .O(blk_cfg_ext_write_data[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_393
       (.I0(1'b0),
        .O(blk_cfg_ext_write_byte_enable[3]));
  LUT1 #(
    .INIT(2'h2)) 
    i_394
       (.I0(1'b0),
        .O(blk_cfg_ext_write_byte_enable[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_395
       (.I0(1'b0),
        .O(blk_cfg_ext_write_byte_enable[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_396
       (.I0(1'b0),
        .O(blk_cfg_ext_write_byte_enable[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_397
       (.I0(1'b0),
        .O(n_0_397));
  LUT1 #(
    .INIT(2'h2)) 
    i_398
       (.I0(1'b0),
        .O(n_0_398));
  LUT1 #(
    .INIT(2'h2)) 
    i_399
       (.I0(1'b0),
        .O(n_0_399));
  LUT1 #(
    .INIT(2'h2)) 
    i_400
       (.I0(1'b0),
        .O(n_0_400));
  LUT1 #(
    .INIT(2'h2)) 
    i_401
       (.I0(1'b0),
        .O(n_0_401));
  LUT1 #(
    .INIT(2'h2)) 
    i_402
       (.I0(1'b0),
        .O(n_0_402));
  LUT1 #(
    .INIT(2'h2)) 
    i_403
       (.I0(1'b0),
        .O(n_0_403));
  LUT1 #(
    .INIT(2'h2)) 
    i_404
       (.I0(1'b0),
        .O(n_0_404));
  LUT1 #(
    .INIT(2'h2)) 
    i_405
       (.I0(1'b0),
        .O(n_0_405));
  LUT1 #(
    .INIT(2'h2)) 
    i_406
       (.I0(1'b0),
        .O(n_0_406));
  LUT1 #(
    .INIT(2'h2)) 
    i_407
       (.I0(1'b0),
        .O(n_0_407));
  LUT1 #(
    .INIT(2'h2)) 
    i_408
       (.I0(1'b0),
        .O(n_0_408));
  LUT1 #(
    .INIT(2'h2)) 
    i_409
       (.I0(1'b0),
        .O(n_0_409));
  LUT1 #(
    .INIT(2'h2)) 
    i_410
       (.I0(1'b0),
        .O(n_0_410));
  LUT1 #(
    .INIT(2'h2)) 
    i_411
       (.I0(1'b0),
        .O(n_0_411));
  LUT1 #(
    .INIT(2'h2)) 
    i_412
       (.I0(1'b0),
        .O(n_0_412));
  LUT1 #(
    .INIT(2'h2)) 
    i_413
       (.I0(1'b0),
        .O(n_0_413));
  LUT1 #(
    .INIT(2'h2)) 
    i_414
       (.I0(1'b0),
        .O(n_0_414));
  LUT1 #(
    .INIT(2'h2)) 
    i_415
       (.I0(1'b0),
        .O(n_0_415));
  LUT1 #(
    .INIT(2'h2)) 
    i_416
       (.I0(1'b0),
        .O(n_0_416));
  LUT1 #(
    .INIT(2'h2)) 
    i_417
       (.I0(1'b0),
        .O(n_0_417));
  LUT1 #(
    .INIT(2'h2)) 
    i_418
       (.I0(1'b0),
        .O(n_0_418));
  LUT1 #(
    .INIT(2'h2)) 
    i_419
       (.I0(1'b0),
        .O(n_0_419));
  LUT1 #(
    .INIT(2'h2)) 
    i_42
       (.I0(1'b0),
        .O(n_0_42));
  LUT1 #(
    .INIT(2'h2)) 
    i_420
       (.I0(1'b0),
        .O(n_0_420));
  LUT1 #(
    .INIT(2'h2)) 
    i_421
       (.I0(1'b0),
        .O(n_0_421));
  LUT1 #(
    .INIT(2'h2)) 
    i_422
       (.I0(1'b0),
        .O(n_0_422));
  LUT1 #(
    .INIT(2'h2)) 
    i_423
       (.I0(1'b0),
        .O(n_0_423));
  LUT1 #(
    .INIT(2'h2)) 
    i_424
       (.I0(1'b0),
        .O(n_0_424));
  LUT1 #(
    .INIT(2'h2)) 
    i_425
       (.I0(1'b0),
        .O(n_0_425));
  LUT1 #(
    .INIT(2'h2)) 
    i_426
       (.I0(1'b0),
        .O(n_0_426));
  LUT1 #(
    .INIT(2'h2)) 
    i_427
       (.I0(1'b0),
        .O(n_0_427));
  LUT1 #(
    .INIT(2'h2)) 
    i_428
       (.I0(1'b0),
        .O(n_0_428));
  LUT1 #(
    .INIT(2'h2)) 
    i_429
       (.I0(1'b0),
        .O(n_0_429));
  LUT1 #(
    .INIT(2'h2)) 
    i_43
       (.I0(1'b0),
        .O(n_0_43));
  LUT1 #(
    .INIT(2'h2)) 
    i_430
       (.I0(1'b0),
        .O(n_0_430));
  LUT1 #(
    .INIT(2'h2)) 
    i_431
       (.I0(1'b0),
        .O(n_0_431));
  LUT1 #(
    .INIT(2'h2)) 
    i_432
       (.I0(1'b0),
        .O(n_0_432));
  LUT1 #(
    .INIT(2'h2)) 
    i_433
       (.I0(1'b0),
        .O(n_0_433));
  LUT1 #(
    .INIT(2'h2)) 
    i_434
       (.I0(1'b0),
        .O(n_0_434));
  LUT1 #(
    .INIT(2'h2)) 
    i_435
       (.I0(1'b0),
        .O(n_0_435));
  LUT1 #(
    .INIT(2'h2)) 
    i_436
       (.I0(1'b0),
        .O(n_0_436));
  LUT1 #(
    .INIT(2'h2)) 
    i_437
       (.I0(1'b0),
        .O(n_0_437));
  LUT1 #(
    .INIT(2'h2)) 
    i_438
       (.I0(1'b0),
        .O(n_0_438));
  LUT1 #(
    .INIT(2'h2)) 
    i_439
       (.I0(1'b0),
        .O(n_0_439));
  LUT1 #(
    .INIT(2'h2)) 
    i_44
       (.I0(1'b0),
        .O(n_0_44));
  LUT1 #(
    .INIT(2'h2)) 
    i_440
       (.I0(1'b0),
        .O(n_0_440));
  LUT1 #(
    .INIT(2'h2)) 
    i_441
       (.I0(1'b0),
        .O(n_0_441));
  LUT1 #(
    .INIT(2'h2)) 
    i_442
       (.I0(1'b0),
        .O(n_0_442));
  LUT1 #(
    .INIT(2'h2)) 
    i_443
       (.I0(1'b0),
        .O(n_0_443));
  LUT1 #(
    .INIT(2'h2)) 
    i_444
       (.I0(1'b0),
        .O(n_0_444));
  LUT1 #(
    .INIT(2'h2)) 
    i_445
       (.I0(1'b0),
        .O(n_0_445));
  LUT1 #(
    .INIT(2'h2)) 
    i_446
       (.I0(1'b0),
        .O(n_0_446));
  LUT1 #(
    .INIT(2'h2)) 
    i_447
       (.I0(1'b0),
        .O(n_0_447));
  LUT1 #(
    .INIT(2'h2)) 
    i_448
       (.I0(1'b0),
        .O(n_0_448));
  LUT1 #(
    .INIT(2'h2)) 
    i_449
       (.I0(1'b0),
        .O(n_0_449));
  LUT1 #(
    .INIT(2'h2)) 
    i_45
       (.I0(1'b0),
        .O(n_0_45));
  LUT1 #(
    .INIT(2'h2)) 
    i_450
       (.I0(1'b0),
        .O(n_0_450));
  LUT1 #(
    .INIT(2'h2)) 
    i_451
       (.I0(1'b0),
        .O(n_0_451));
  LUT1 #(
    .INIT(2'h2)) 
    i_452
       (.I0(1'b0),
        .O(n_0_452));
  LUT1 #(
    .INIT(2'h2)) 
    i_453
       (.I0(1'b0),
        .O(n_0_453));
  LUT1 #(
    .INIT(2'h2)) 
    i_454
       (.I0(1'b0),
        .O(n_0_454));
  LUT1 #(
    .INIT(2'h2)) 
    i_455
       (.I0(1'b0),
        .O(n_0_455));
  LUT1 #(
    .INIT(2'h2)) 
    i_456
       (.I0(1'b0),
        .O(n_0_456));
  LUT1 #(
    .INIT(2'h2)) 
    i_457
       (.I0(1'b0),
        .O(n_0_457));
  LUT1 #(
    .INIT(2'h2)) 
    i_458
       (.I0(1'b0),
        .O(n_0_458));
  LUT1 #(
    .INIT(2'h2)) 
    i_459
       (.I0(1'b0),
        .O(n_0_459));
  LUT1 #(
    .INIT(2'h2)) 
    i_46
       (.I0(1'b0),
        .O(n_0_46));
  LUT1 #(
    .INIT(2'h2)) 
    i_460
       (.I0(1'b0),
        .O(n_0_460));
  LUT1 #(
    .INIT(2'h2)) 
    i_461
       (.I0(1'b0),
        .O(n_0_461));
  LUT1 #(
    .INIT(2'h2)) 
    i_462
       (.I0(1'b0),
        .O(n_0_462));
  LUT1 #(
    .INIT(2'h2)) 
    i_463
       (.I0(1'b0),
        .O(n_0_463));
  LUT1 #(
    .INIT(2'h2)) 
    i_464
       (.I0(1'b0),
        .O(n_0_464));
  LUT1 #(
    .INIT(2'h2)) 
    i_465
       (.I0(1'b0),
        .O(n_0_465));
  LUT1 #(
    .INIT(2'h2)) 
    i_466
       (.I0(1'b0),
        .O(n_0_466));
  LUT1 #(
    .INIT(2'h2)) 
    i_467
       (.I0(1'b0),
        .O(n_0_467));
  LUT1 #(
    .INIT(2'h2)) 
    i_468
       (.I0(1'b0),
        .O(n_0_468));
  LUT1 #(
    .INIT(2'h2)) 
    i_469
       (.I0(1'b0),
        .O(n_0_469));
  LUT1 #(
    .INIT(2'h2)) 
    i_47
       (.I0(1'b0),
        .O(n_0_47));
  LUT1 #(
    .INIT(2'h2)) 
    i_470
       (.I0(1'b0),
        .O(n_0_470));
  LUT1 #(
    .INIT(2'h2)) 
    i_471
       (.I0(1'b0),
        .O(n_0_471));
  LUT1 #(
    .INIT(2'h2)) 
    i_472
       (.I0(1'b0),
        .O(n_0_472));
  LUT1 #(
    .INIT(2'h2)) 
    i_473
       (.I0(1'b0),
        .O(n_0_473));
  LUT1 #(
    .INIT(2'h2)) 
    i_474
       (.I0(1'b0),
        .O(n_0_474));
  LUT1 #(
    .INIT(2'h2)) 
    i_475
       (.I0(1'b0),
        .O(n_0_475));
  LUT1 #(
    .INIT(2'h2)) 
    i_476
       (.I0(1'b0),
        .O(n_0_476));
  LUT1 #(
    .INIT(2'h2)) 
    i_477
       (.I0(1'b0),
        .O(n_0_477));
  LUT1 #(
    .INIT(2'h2)) 
    i_478
       (.I0(1'b0),
        .O(n_0_478));
  LUT1 #(
    .INIT(2'h2)) 
    i_479
       (.I0(1'b0),
        .O(n_0_479));
  LUT1 #(
    .INIT(2'h2)) 
    i_48
       (.I0(1'b0),
        .O(n_0_48));
  LUT1 #(
    .INIT(2'h2)) 
    i_480
       (.I0(1'b0),
        .O(n_0_480));
  LUT1 #(
    .INIT(2'h2)) 
    i_481
       (.I0(1'b0),
        .O(n_0_481));
  LUT1 #(
    .INIT(2'h2)) 
    i_482
       (.I0(1'b0),
        .O(n_0_482));
  LUT1 #(
    .INIT(2'h2)) 
    i_49
       (.I0(1'b0),
        .O(n_0_49));
  LUT1 #(
    .INIT(2'h2)) 
    i_62
       (.I0(1'b0),
        .O(n_0_62));
  LUT1 #(
    .INIT(2'h2)) 
    i_63
       (.I0(1'b0),
        .O(n_0_63));
  LUT1 #(
    .INIT(2'h2)) 
    i_64
       (.I0(1'b0),
        .O(n_0_64));
  LUT1 #(
    .INIT(2'h2)) 
    i_65
       (.I0(1'b0),
        .O(n_0_65));
  LUT1 #(
    .INIT(2'h2)) 
    i_66
       (.I0(1'b0),
        .O(n_0_66));
  LUT1 #(
    .INIT(2'h2)) 
    i_67
       (.I0(1'b0),
        .O(n_0_67));
  LUT1 #(
    .INIT(2'h2)) 
    i_68
       (.I0(1'b0),
        .O(n_0_68));
  LUT1 #(
    .INIT(2'h2)) 
    i_69
       (.I0(1'b0),
        .O(n_0_69));
  LUT1 #(
    .INIT(2'h2)) 
    i_78
       (.I0(1'b0),
        .O(n_0_78));
  LUT1 #(
    .INIT(2'h2)) 
    i_79
       (.I0(1'b0),
        .O(n_0_79));
  LUT1 #(
    .INIT(2'h2)) 
    i_80
       (.I0(1'b0),
        .O(n_0_80));
  LUT1 #(
    .INIT(2'h2)) 
    i_81
       (.I0(1'b0),
        .O(n_0_81));
  LUT1 #(
    .INIT(2'h2)) 
    i_82
       (.I0(1'b0),
        .O(n_0_82));
  LUT1 #(
    .INIT(2'h2)) 
    i_83
       (.I0(1'b0),
        .O(n_0_83));
  LUT1 #(
    .INIT(2'h2)) 
    i_84
       (.I0(1'b0),
        .O(n_0_84));
  LUT1 #(
    .INIT(2'h2)) 
    i_85
       (.I0(1'b0),
        .O(n_0_85));
  LUT1 #(
    .INIT(2'h2)) 
    i_86
       (.I0(1'b0),
        .O(n_0_86));
  LUT1 #(
    .INIT(2'h2)) 
    i_87
       (.I0(1'b0),
        .O(n_0_87));
  LUT1 #(
    .INIT(2'h2)) 
    i_88
       (.I0(1'b0),
        .O(n_0_88));
  LUT1 #(
    .INIT(2'h2)) 
    i_89
       (.I0(1'b0),
        .O(n_0_89));
  LUT1 #(
    .INIT(2'h2)) 
    i_90
       (.I0(1'b0),
        .O(n_0_90));
  LUT1 #(
    .INIT(2'h2)) 
    i_91
       (.I0(1'b0),
        .O(n_0_91));
  LUT1 #(
    .INIT(2'h2)) 
    i_92
       (.I0(1'b0),
        .O(n_0_92));
  LUT1 #(
    .INIT(2'h2)) 
    i_93
       (.I0(1'b0),
        .O(n_0_93));
  LUT1 #(
    .INIT(2'h2)) 
    i_94
       (.I0(1'b0),
        .O(n_0_94));
  LUT1 #(
    .INIT(2'h2)) 
    i_95
       (.I0(1'b0),
        .O(n_0_95));
  LUT1 #(
    .INIT(2'h2)) 
    i_96
       (.I0(1'b0),
        .O(n_0_96));
  LUT1 #(
    .INIT(2'h2)) 
    i_97
       (.I0(1'b0),
        .O(n_0_97));
  LUT1 #(
    .INIT(2'h2)) 
    i_98
       (.I0(1'b0),
        .O(n_0_98));
  LUT1 #(
    .INIT(2'h2)) 
    i_99
       (.I0(1'b0),
        .O(n_0_99));
  (* AXI4MM_ULTRA = "0" *) 
  (* C2H_DAT_DEPTH = "512" *) 
  (* C2H_DAT_DEPTH_BITS = "9" *) 
  (* C_C2H_NUM_CHNL = "1" *) 
  (* C_DATA_WIDTH = "64" *) 
  (* C_H2C_NUM_CHNL = "1" *) 
  (* C_M_NUM_CQ_AXI_WRITE_SCALE = "1" *) 
  (* C_NUMQ_PER_CHNL = "256" *) 
  (* C_NUM_AXI_DSC_CPL_DID = "64" *) 
  (* C_NUM_C2H_PCIE_DSC_CPL_DID = "1024" *) 
  (* C_NUM_PCIE_DSC_CPL_DID = "256" *) 
  (* C_SLAVE_READ_64OS_EN = "0" *) 
  (* DATA_FIFO_ECC_ENABLE = "0" *) 
  (* DSC_AXI_CPL_DID_WIDTH = "6" *) 
  (* DSC_C2H_PCIE_CPL_DID_WIDTH = "10" *) 
  (* DSC_PCIE_CPL_DID_WIDTH = "8" *) 
  (* ECC_ENABLE = "0" *) 
  (* ENABLE_ERROR_INJECTION = "FALSE" *) 
  (* H2C_DAT_DEPTH = "512" *) 
  (* H2C_DAT_DEPTH_BITS = "9" *) 
  (* IMPL_TARGET = "SOFT" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* MASTER_RD_DEPTH = "512" *) 
  (* MASTER_RD_DEPTH_BITS = "9" *) 
  (* MM_SLAVE_EN = "0" *) 
  (* NUM_TOTQ = "512" *) 
  (* PARITY_ENABLE = "1" *) 
  (* SHELL_BRIDGE = "0" *) 
  (* TCQ = "1" *) 
  (* TOTQ_WIDTH = "9" *) 
  (* is_du_within_envelope = "true" *) 
  xdma_0_xdma_v4_1_29_udma_ram_top ram_top
       (.\mi_c2h0_dat\.radr (\mi_c2h0_dat\.radr ),
        .\mi_c2h0_dat\.rdat ({\NLW_ram_top_mi_c2h0_dat\.rdat_UNCONNECTED [511:64],\mi_c2h0_dat\.rdat }),
        .\mi_c2h0_dat\.rdbe (\NLW_ram_top_mi_c2h0_dat\.rdbe_UNCONNECTED ),
        .\mi_c2h0_dat\.ren (1'b1),
        .\mi_c2h0_dat\.rpar (\NLW_ram_top_mi_c2h0_dat\.rpar_UNCONNECTED [63:0]),
        .\mi_c2h0_dat\.rsbe (\NLW_ram_top_mi_c2h0_dat\.rsbe_UNCONNECTED ),
        .\mi_c2h0_dat\.wadr (\mi_c2h0_dat\.wadr ),
        .\mi_c2h0_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_c2h0_dat\.wdat }),
        .\mi_c2h0_dat\.wen (\mi_c2h0_dat\.wen ),
        .\mi_c2h0_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h1_dat\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h1_dat\.rdat (\NLW_ram_top_mi_c2h1_dat\.rdat_UNCONNECTED [511:0]),
        .\mi_c2h1_dat\.rdbe (\NLW_ram_top_mi_c2h1_dat\.rdbe_UNCONNECTED ),
        .\mi_c2h1_dat\.ren (1'b1),
        .\mi_c2h1_dat\.rpar (\NLW_ram_top_mi_c2h1_dat\.rpar_UNCONNECTED [63:0]),
        .\mi_c2h1_dat\.rsbe (\NLW_ram_top_mi_c2h1_dat\.rsbe_UNCONNECTED ),
        .\mi_c2h1_dat\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h1_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h1_dat\.wen ({1'b0,1'b0}),
        .\mi_c2h1_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h2_dat\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h2_dat\.rdat (\NLW_ram_top_mi_c2h2_dat\.rdat_UNCONNECTED [511:0]),
        .\mi_c2h2_dat\.rdbe (\NLW_ram_top_mi_c2h2_dat\.rdbe_UNCONNECTED ),
        .\mi_c2h2_dat\.ren (1'b1),
        .\mi_c2h2_dat\.rpar (\NLW_ram_top_mi_c2h2_dat\.rpar_UNCONNECTED [63:0]),
        .\mi_c2h2_dat\.rsbe (\NLW_ram_top_mi_c2h2_dat\.rsbe_UNCONNECTED ),
        .\mi_c2h2_dat\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h2_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h2_dat\.wen ({1'b0,1'b0}),
        .\mi_c2h2_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h3_dat\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h3_dat\.rdat (\NLW_ram_top_mi_c2h3_dat\.rdat_UNCONNECTED [511:0]),
        .\mi_c2h3_dat\.rdbe (\NLW_ram_top_mi_c2h3_dat\.rdbe_UNCONNECTED ),
        .\mi_c2h3_dat\.ren (1'b1),
        .\mi_c2h3_dat\.rpar (\NLW_ram_top_mi_c2h3_dat\.rpar_UNCONNECTED [63:0]),
        .\mi_c2h3_dat\.rsbe (\NLW_ram_top_mi_c2h3_dat\.rsbe_UNCONNECTED ),
        .\mi_c2h3_dat\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h3_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h3_dat\.wen ({1'b0,1'b0}),
        .\mi_c2h3_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpld\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpld\.rdat (\NLW_ram_top_mi_c2h_axi_dsc_cpld\.rdat_UNCONNECTED [511:0]),
        .\mi_c2h_axi_dsc_cpld\.rdbe (\NLW_ram_top_mi_c2h_axi_dsc_cpld\.rdbe_UNCONNECTED ),
        .\mi_c2h_axi_dsc_cpld\.ren (1'b0),
        .\mi_c2h_axi_dsc_cpld\.rpar (\NLW_ram_top_mi_c2h_axi_dsc_cpld\.rpar_UNCONNECTED [63:0]),
        .\mi_c2h_axi_dsc_cpld\.rsbe (\NLW_ram_top_mi_c2h_axi_dsc_cpld\.rsbe_UNCONNECTED ),
        .\mi_c2h_axi_dsc_cpld\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpld\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpld\.wen ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpld\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpli\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpli\.rdat (\NLW_ram_top_mi_c2h_axi_dsc_cpli\.rdat_UNCONNECTED [79:0]),
        .\mi_c2h_axi_dsc_cpli\.rdbe (\NLW_ram_top_mi_c2h_axi_dsc_cpli\.rdbe_UNCONNECTED ),
        .\mi_c2h_axi_dsc_cpli\.ren (1'b0),
        .\mi_c2h_axi_dsc_cpli\.rpar (\NLW_ram_top_mi_c2h_axi_dsc_cpli\.rpar_UNCONNECTED [3:0]),
        .\mi_c2h_axi_dsc_cpli\.rsbe (\NLW_ram_top_mi_c2h_axi_dsc_cpli\.rsbe_UNCONNECTED ),
        .\mi_c2h_axi_dsc_cpli\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpli\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpli\.wen ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpli\.wpar ({1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_pcie_dsc_cpld\.radr ({1'b0,\mi_c2h_pcie_dsc_cpld\.radr }),
        .\mi_c2h_pcie_dsc_cpld\.rdat ({\NLW_ram_top_mi_c2h_pcie_dsc_cpld\.rdat_UNCONNECTED [511:64],\mi_c2h_pcie_dsc_cpld\.rdat }),
        .\mi_c2h_pcie_dsc_cpld\.rdbe (\NLW_ram_top_mi_c2h_pcie_dsc_cpld\.rdbe_UNCONNECTED ),
        .\mi_c2h_pcie_dsc_cpld\.ren (1'b1),
        .\mi_c2h_pcie_dsc_cpld\.rpar (\NLW_ram_top_mi_c2h_pcie_dsc_cpld\.rpar_UNCONNECTED [63:0]),
        .\mi_c2h_pcie_dsc_cpld\.rsbe (\NLW_ram_top_mi_c2h_pcie_dsc_cpld\.rsbe_UNCONNECTED ),
        .\mi_c2h_pcie_dsc_cpld\.wadr ({1'b0,\mi_c2h_pcie_dsc_cpld\.wadr }),
        .\mi_c2h_pcie_dsc_cpld\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_c2h_pcie_dsc_cpld\.wdat }),
        .\mi_c2h_pcie_dsc_cpld\.wen ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_c2h_pcie_dsc_cpld\.wen }),
        .\mi_c2h_pcie_dsc_cpld\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_pcie_dsc_cpli\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_pcie_dsc_cpli\.rdat (\NLW_ram_top_mi_c2h_pcie_dsc_cpli\.rdat_UNCONNECTED [79:0]),
        .\mi_c2h_pcie_dsc_cpli\.rdbe (\NLW_ram_top_mi_c2h_pcie_dsc_cpli\.rdbe_UNCONNECTED ),
        .\mi_c2h_pcie_dsc_cpli\.ren (1'b0),
        .\mi_c2h_pcie_dsc_cpli\.rpar (\NLW_ram_top_mi_c2h_pcie_dsc_cpli\.rpar_UNCONNECTED [3:0]),
        .\mi_c2h_pcie_dsc_cpli\.rsbe (\NLW_ram_top_mi_c2h_pcie_dsc_cpli\.rsbe_UNCONNECTED ),
        .\mi_c2h_pcie_dsc_cpli\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_pcie_dsc_cpli\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_pcie_dsc_cpli\.wen ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_pcie_dsc_cpli\.wpar ({1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_rd_brg_dat\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_rd_brg_dat\.rdat (\NLW_ram_top_mi_c2h_rd_brg_dat\.rdat_UNCONNECTED [511:0]),
        .\mi_c2h_rd_brg_dat\.rdbe (\NLW_ram_top_mi_c2h_rd_brg_dat\.rdbe_UNCONNECTED ),
        .\mi_c2h_rd_brg_dat\.ren (1'b0),
        .\mi_c2h_rd_brg_dat\.rpar (\NLW_ram_top_mi_c2h_rd_brg_dat\.rpar_UNCONNECTED [63:0]),
        .\mi_c2h_rd_brg_dat\.rsbe (\NLW_ram_top_mi_c2h_rd_brg_dat\.rsbe_UNCONNECTED ),
        .\mi_c2h_rd_brg_dat\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_rd_brg_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_rd_brg_dat\.wen ({1'b0,1'b0}),
        .\mi_c2h_rd_brg_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_wr_brg_dat\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_wr_brg_dat\.rdat (\NLW_ram_top_mi_c2h_wr_brg_dat\.rdat_UNCONNECTED [511:0]),
        .\mi_c2h_wr_brg_dat\.rdbe (\NLW_ram_top_mi_c2h_wr_brg_dat\.rdbe_UNCONNECTED ),
        .\mi_c2h_wr_brg_dat\.ren (1'b0),
        .\mi_c2h_wr_brg_dat\.rpar (\NLW_ram_top_mi_c2h_wr_brg_dat\.rpar_UNCONNECTED [63:0]),
        .\mi_c2h_wr_brg_dat\.rsbe (\NLW_ram_top_mi_c2h_wr_brg_dat\.rsbe_UNCONNECTED ),
        .\mi_c2h_wr_brg_dat\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_wr_brg_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_wr_brg_dat\.wen ({1'b0,1'b0}),
        .\mi_c2h_wr_brg_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_dsc_crd_rcv\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_dsc_crd_rcv\.rdat (\NLW_ram_top_mi_dsc_crd_rcv\.rdat_UNCONNECTED [15:0]),
        .\mi_dsc_crd_rcv\.rdbe (\NLW_ram_top_mi_dsc_crd_rcv\.rdbe_UNCONNECTED ),
        .\mi_dsc_crd_rcv\.ren (1'b0),
        .\mi_dsc_crd_rcv\.rpar (\NLW_ram_top_mi_dsc_crd_rcv\.rpar_UNCONNECTED [1:0]),
        .\mi_dsc_crd_rcv\.rsbe (\NLW_ram_top_mi_dsc_crd_rcv\.rsbe_UNCONNECTED ),
        .\mi_dsc_crd_rcv\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_dsc_crd_rcv\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_dsc_crd_rcv\.wen (1'b0),
        .\mi_dsc_crd_rcv\.wpar ({1'b0,1'b0}),
        .\mi_h2c0_dat\.radr (\mi_h2c0_dat\.radr ),
        .\mi_h2c0_dat\.rdat ({\NLW_ram_top_mi_h2c0_dat\.rdat_UNCONNECTED [511:64],\mi_h2c0_dat\.rdat }),
        .\mi_h2c0_dat\.rdbe (\NLW_ram_top_mi_h2c0_dat\.rdbe_UNCONNECTED ),
        .\mi_h2c0_dat\.ren (1'b1),
        .\mi_h2c0_dat\.rpar (\NLW_ram_top_mi_h2c0_dat\.rpar_UNCONNECTED [63:0]),
        .\mi_h2c0_dat\.rsbe (\NLW_ram_top_mi_h2c0_dat\.rsbe_UNCONNECTED ),
        .\mi_h2c0_dat\.wadr (\mi_h2c0_dat\.wadr ),
        .\mi_h2c0_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_h2c0_dat\.wdat }),
        .\mi_h2c0_dat\.wen (\mi_h2c0_dat\.wen ),
        .\mi_h2c0_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_h2c0_dat\.wpar }),
        .\mi_h2c1_dat\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c1_dat\.rdat (\NLW_ram_top_mi_h2c1_dat\.rdat_UNCONNECTED [511:0]),
        .\mi_h2c1_dat\.rdbe (\NLW_ram_top_mi_h2c1_dat\.rdbe_UNCONNECTED ),
        .\mi_h2c1_dat\.ren (1'b1),
        .\mi_h2c1_dat\.rpar (\NLW_ram_top_mi_h2c1_dat\.rpar_UNCONNECTED [63:0]),
        .\mi_h2c1_dat\.rsbe (\NLW_ram_top_mi_h2c1_dat\.rsbe_UNCONNECTED ),
        .\mi_h2c1_dat\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c1_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c1_dat\.wen ({1'b0,1'b0}),
        .\mi_h2c1_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c2_dat\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c2_dat\.rdat (\NLW_ram_top_mi_h2c2_dat\.rdat_UNCONNECTED [511:0]),
        .\mi_h2c2_dat\.rdbe (\NLW_ram_top_mi_h2c2_dat\.rdbe_UNCONNECTED ),
        .\mi_h2c2_dat\.ren (1'b1),
        .\mi_h2c2_dat\.rpar (\NLW_ram_top_mi_h2c2_dat\.rpar_UNCONNECTED [63:0]),
        .\mi_h2c2_dat\.rsbe (\NLW_ram_top_mi_h2c2_dat\.rsbe_UNCONNECTED ),
        .\mi_h2c2_dat\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c2_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c2_dat\.wen ({1'b0,1'b0}),
        .\mi_h2c2_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c3_dat\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c3_dat\.rdat (\NLW_ram_top_mi_h2c3_dat\.rdat_UNCONNECTED [511:0]),
        .\mi_h2c3_dat\.rdbe (\NLW_ram_top_mi_h2c3_dat\.rdbe_UNCONNECTED ),
        .\mi_h2c3_dat\.ren (1'b1),
        .\mi_h2c3_dat\.rpar (\NLW_ram_top_mi_h2c3_dat\.rpar_UNCONNECTED [63:0]),
        .\mi_h2c3_dat\.rsbe (\NLW_ram_top_mi_h2c3_dat\.rsbe_UNCONNECTED ),
        .\mi_h2c3_dat\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c3_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c3_dat\.wen ({1'b0,1'b0}),
        .\mi_h2c3_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpld\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpld\.rdat (\NLW_ram_top_mi_h2c_axi_dsc_cpld\.rdat_UNCONNECTED [511:0]),
        .\mi_h2c_axi_dsc_cpld\.rdbe (\NLW_ram_top_mi_h2c_axi_dsc_cpld\.rdbe_UNCONNECTED ),
        .\mi_h2c_axi_dsc_cpld\.ren (1'b0),
        .\mi_h2c_axi_dsc_cpld\.rpar (\NLW_ram_top_mi_h2c_axi_dsc_cpld\.rpar_UNCONNECTED [63:0]),
        .\mi_h2c_axi_dsc_cpld\.rsbe (\NLW_ram_top_mi_h2c_axi_dsc_cpld\.rsbe_UNCONNECTED ),
        .\mi_h2c_axi_dsc_cpld\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpld\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpld\.wen ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpld\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpli\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpli\.rdat (\NLW_ram_top_mi_h2c_axi_dsc_cpli\.rdat_UNCONNECTED [79:0]),
        .\mi_h2c_axi_dsc_cpli\.rdbe (\NLW_ram_top_mi_h2c_axi_dsc_cpli\.rdbe_UNCONNECTED ),
        .\mi_h2c_axi_dsc_cpli\.ren (1'b0),
        .\mi_h2c_axi_dsc_cpli\.rpar (\NLW_ram_top_mi_h2c_axi_dsc_cpli\.rpar_UNCONNECTED [3:0]),
        .\mi_h2c_axi_dsc_cpli\.rsbe (\NLW_ram_top_mi_h2c_axi_dsc_cpli\.rsbe_UNCONNECTED ),
        .\mi_h2c_axi_dsc_cpli\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpli\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpli\.wen ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpli\.wpar ({1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpld\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpld\.rdat (\NLW_ram_top_mi_h2c_pcie_dsc_cpld\.rdat_UNCONNECTED [511:0]),
        .\mi_h2c_pcie_dsc_cpld\.rdbe (\NLW_ram_top_mi_h2c_pcie_dsc_cpld\.rdbe_UNCONNECTED ),
        .\mi_h2c_pcie_dsc_cpld\.ren (1'b0),
        .\mi_h2c_pcie_dsc_cpld\.rpar (\NLW_ram_top_mi_h2c_pcie_dsc_cpld\.rpar_UNCONNECTED [63:0]),
        .\mi_h2c_pcie_dsc_cpld\.rsbe (\NLW_ram_top_mi_h2c_pcie_dsc_cpld\.rsbe_UNCONNECTED ),
        .\mi_h2c_pcie_dsc_cpld\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpld\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpld\.wen ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpld\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpli\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpli\.rdat (\NLW_ram_top_mi_h2c_pcie_dsc_cpli\.rdat_UNCONNECTED [79:0]),
        .\mi_h2c_pcie_dsc_cpli\.rdbe (\NLW_ram_top_mi_h2c_pcie_dsc_cpli\.rdbe_UNCONNECTED ),
        .\mi_h2c_pcie_dsc_cpli\.ren (1'b0),
        .\mi_h2c_pcie_dsc_cpli\.rpar (\NLW_ram_top_mi_h2c_pcie_dsc_cpli\.rpar_UNCONNECTED [3:0]),
        .\mi_h2c_pcie_dsc_cpli\.rsbe (\NLW_ram_top_mi_h2c_pcie_dsc_cpli\.rsbe_UNCONNECTED ),
        .\mi_h2c_pcie_dsc_cpli\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpli\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpli\.wen ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpli\.wpar ({1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_rd_brg_dat\.radr (\mi_h2c_rd_brg_dat\.radr ),
        .\mi_h2c_rd_brg_dat\.rdat ({\NLW_ram_top_mi_h2c_rd_brg_dat\.rdat_UNCONNECTED [511:64],\mi_h2c_rd_brg_dat\.rdat }),
        .\mi_h2c_rd_brg_dat\.rdbe (\NLW_ram_top_mi_h2c_rd_brg_dat\.rdbe_UNCONNECTED ),
        .\mi_h2c_rd_brg_dat\.ren (1'b1),
        .\mi_h2c_rd_brg_dat\.rpar (\NLW_ram_top_mi_h2c_rd_brg_dat\.rpar_UNCONNECTED [63:0]),
        .\mi_h2c_rd_brg_dat\.rsbe (\NLW_ram_top_mi_h2c_rd_brg_dat\.rsbe_UNCONNECTED ),
        .\mi_h2c_rd_brg_dat\.wadr (\mi_h2c_rd_brg_dat\.wadr ),
        .\mi_h2c_rd_brg_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_h2c_rd_brg_dat\.wdat }),
        .\mi_h2c_rd_brg_dat\.wen ({1'b0,\mi_h2c_rd_brg_dat\.wen }),
        .\mi_h2c_rd_brg_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_wr_brg_dat\.radr ({1'b0,1'b0,\mi_h2c_wr_brg_dat\.radr }),
        .\mi_h2c_wr_brg_dat\.rdat ({\NLW_ram_top_mi_h2c_wr_brg_dat\.rdat_UNCONNECTED [511:64],\mi_h2c_wr_brg_dat\.rdat }),
        .\mi_h2c_wr_brg_dat\.rdbe (\NLW_ram_top_mi_h2c_wr_brg_dat\.rdbe_UNCONNECTED ),
        .\mi_h2c_wr_brg_dat\.ren (1'b1),
        .\mi_h2c_wr_brg_dat\.rpar ({\NLW_ram_top_mi_h2c_wr_brg_dat\.rpar_UNCONNECTED [63:8],\mi_h2c_wr_brg_dat\.rpar }),
        .\mi_h2c_wr_brg_dat\.rsbe (\NLW_ram_top_mi_h2c_wr_brg_dat\.rsbe_UNCONNECTED ),
        .\mi_h2c_wr_brg_dat\.wadr ({1'b0,1'b0,\mi_h2c_wr_brg_dat\.wadr }),
        .\mi_h2c_wr_brg_dat\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_h2c_wr_brg_dat\.wdat }),
        .\mi_h2c_wr_brg_dat\.wen ({1'b0,\mi_h2c_wr_brg_dat\.wen }),
        .\mi_h2c_wr_brg_dat\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_hw_ctxt\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_hw_ctxt\.rdat (\NLW_ram_top_mi_hw_ctxt\.rdat_UNCONNECTED [31:0]),
        .\mi_hw_ctxt\.rdbe (\NLW_ram_top_mi_hw_ctxt\.rdbe_UNCONNECTED ),
        .\mi_hw_ctxt\.ren (1'b0),
        .\mi_hw_ctxt\.rpar (\NLW_ram_top_mi_hw_ctxt\.rpar_UNCONNECTED [7:0]),
        .\mi_hw_ctxt\.rsbe (\NLW_ram_top_mi_hw_ctxt\.rsbe_UNCONNECTED ),
        .\mi_hw_ctxt\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_hw_ctxt\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_hw_ctxt\.wen (1'b0),
        .\mi_hw_ctxt\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_sw_ctxt\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_sw_ctxt\.rdat (\NLW_ram_top_mi_sw_ctxt\.rdat_UNCONNECTED [127:0]),
        .\mi_sw_ctxt\.rdbe (\NLW_ram_top_mi_sw_ctxt\.rdbe_UNCONNECTED ),
        .\mi_sw_ctxt\.ren (1'b0),
        .\mi_sw_ctxt\.rpar (\NLW_ram_top_mi_sw_ctxt\.rpar_UNCONNECTED [7:0]),
        .\mi_sw_ctxt\.rsbe (\NLW_ram_top_mi_sw_ctxt\.rsbe_UNCONNECTED ),
        .\mi_sw_ctxt\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_sw_ctxt\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_sw_ctxt\.wen ({1'b0,1'b0,1'b0,1'b0}),
        .\mi_sw_ctxt\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_wb_base_ctxt\.radr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_wb_base_ctxt\.rdat (\NLW_ram_top_mi_wb_base_ctxt\.rdat_UNCONNECTED [127:0]),
        .\mi_wb_base_ctxt\.rdbe (\NLW_ram_top_mi_wb_base_ctxt\.rdbe_UNCONNECTED ),
        .\mi_wb_base_ctxt\.ren (1'b0),
        .\mi_wb_base_ctxt\.rpar (\NLW_ram_top_mi_wb_base_ctxt\.rpar_UNCONNECTED [7:0]),
        .\mi_wb_base_ctxt\.rsbe (\NLW_ram_top_mi_wb_base_ctxt\.rsbe_UNCONNECTED ),
        .\mi_wb_base_ctxt\.wadr ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_wb_base_ctxt\.wdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_wb_base_ctxt\.wen ({1'b0,1'b0}),
        .\mi_wb_base_ctxt\.wpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .user_clk(axi_aclk),
        .user_reset(dma_soft_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDCE sys_rst_n_reg2_reg
       (.C(axi_aclk),
        .CE(1'b1),
        .CLR(sys_rst_n_reg_i_1_n_0),
        .D(sys_rst_n_reg),
        .Q(sys_rst_n_reg2));
  LUT1 #(
    .INIT(2'h1)) 
    sys_rst_n_reg_i_1
       (.I0(sys_rst_n),
        .O(sys_rst_n_reg_i_1_n_0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDCE sys_rst_n_reg_reg
       (.C(axi_aclk),
        .CE(1'b1),
        .CLR(sys_rst_n_reg_i_1_n_0),
        .D(1'b1),
        .Q(sys_rst_n_reg));
  (* AXI4MM_ULTRA = "0" *) 
  (* AXIL_ADR_WIDTH = "32" *) 
  (* AXIL_DAT_WIDTH = "32" *) 
  (* AXI_DSC_ENG_EN = "0" *) 
  (* AXI_WBK_ENG_EN = "0" *) 
  (* AXSIZE_BYTE_ACCESS_EN = "FALSE" *) 
  (* BACKPRESSURE = "0" *) 
  (* BAR0_APERTURE_SIZE = "32" *) 
  (* BAR1_APERTURE_SIZE = "16" *) 
  (* BAR2_APERTURE_SIZE = "64" *) 
  (* BARLITE0 = "7" *) 
  (* BARLITE1 = "0" *) 
  (* BARLITE2 = "7" *) 
  (* C2H_WB = "1" *) 
  (* C2H_XDMA_CHNL = "8'b00001111" *) 
  (* C_ADDR_ALGN = "1" *) 
  (* C_ADDR_BITS = "64" *) 
  (* C_ATS_CAP_NEXTPTR = "12'b000000000000" *) 
  (* C_ATS_ENABLE = "FALSE" *) 
  (* C_ATS_OFFSET = "30'b000000000000000000000100100000" *) 
  (* C_AXIBAR2PCIEATTR_0 = "3'b000" *) 
  (* C_AXIBAR2PCIEATTR_1 = "3'b000" *) 
  (* C_AXIBAR2PCIEATTR_2 = "3'b000" *) 
  (* C_AXIBAR2PCIEATTR_3 = "3'b000" *) 
  (* C_AXIBAR2PCIEATTR_4 = "3'b000" *) 
  (* C_AXIBAR2PCIEATTR_5 = "3'b000" *) 
  (* C_AXIBAR2PCIEBAR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR2PCIEBAR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR2PCIEBAR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR2PCIEBAR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR2PCIEBAR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR2PCIEBAR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_AS_0 = "1" *) 
  (* C_AXIBAR_AS_1 = "1" *) 
  (* C_AXIBAR_AS_2 = "1" *) 
  (* C_AXIBAR_AS_3 = "1" *) 
  (* C_AXIBAR_AS_4 = "1" *) 
  (* C_AXIBAR_AS_5 = "1" *) 
  (* C_AXIBAR_HIGHADDR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_HIGHADDR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_HIGHADDR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_HIGHADDR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_HIGHADDR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_HIGHADDR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_AXIBAR_NOXLATE = "0" *) 
  (* C_AXIBAR_NUM = "6" *) 
  (* C_AXIBAR_REGIONEN = "0" *) 
  (* C_AXI_BUSER_WIDTH = "1" *) 
  (* C_AXI_RUSER_WIDTH = "8" *) 
  (* C_AXI_WUSER_WIDTH = "8" *) 
  (* C_BASEADDR = "4096" *) 
  (* C_C2H_NUM_CHNL = "1" *) 
  (* C_C2H_NUM_RIDS = "16" *) 
  (* C_C2H_RID_WIDTH = "8" *) 
  (* C_C2H_TUSER_WIDTH = "64" *) 
  (* C_COMP_TIMEOUT = "1" *) 
  (* C_DATA_WIDTH = "64" *) 
  (* C_DAT_BRAM_DEPTH = "512" *) 
  (* C_DEVICE_NUMBER = "0" *) 
  (* C_DSC_BRAM_DEPTH = "512" *) 
  (* C_DSC_DEPTH = "512" *) 
  (* C_DSC_MAGIC_EN = "1" *) 
  (* C_ECC_ENABLE = "0" *) 
  (* C_ENABLE_RESOURCE_REDUCTION = "FALSE" *) 
  (* C_EP_LINK_PARTNER_RCB = "0" *) 
  (* C_ERRC_DEC_EN = "0" *) 
  (* C_FAMILY = "artix7" *) 
  (* C_FF_ON_INT_IF = "FALSE" *) 
  (* C_H2C_NUM_CHNL = "1" *) 
  (* C_H2C_NUM_RIDS = "32" *) 
  (* C_H2C_RID_WIDTH = "8" *) 
  (* C_H2C_TUSER_WIDTH = "48" *) 
  (* C_HIGHADDR = "8191" *) 
  (* C_IGNORE_SIZE_AXI_SLAVE = "1" *) 
  (* C_INCLUDE_BAROFFSET_REG = "1" *) 
  (* C_INCLUDE_RC = "0" *) 
  (* C_INTX_RX_PIN_EN = "1" *) 
  (* C_INV_QUEUE_DEPTH = "5'b00000" *) 
  (* C_LAST_CORE_CAP_ADDR = "12'b000100000000" *) 
  (* C_MAX_NUM_CHNL = "1" *) 
  (* C_MSIX_INT_TABLE_EN = "0" *) 
  (* C_MSIX_RX_PIN_EN = "1" *) 
  (* C_MSI_ENABLED = "TRUE" *) 
  (* C_MSI_RX_PIN_EN = "0" *) 
  (* C_MULTQ_MAX_QID = "32" *) 
  (* C_MULTQ_MAX_RING_DEPTH = "8192" *) 
  (* C_M_AXIL_ARUSER_WIDTH = "8" *) 
  (* C_M_AXIL_AWUSER_WIDTH = "8" *) 
  (* C_M_AXIS_DATA_WIDTH = "64" *) 
  (* C_M_AXIS_RC_USER_WIDTH = "75" *) 
  (* C_M_AXIS_RQ_USER_WIDTH = "60" *) 
  (* C_M_AXI_ADDR_WIDTH = "64" *) 
  (* C_M_AXI_ARUSER_WIDTH = "8" *) 
  (* C_M_AXI_AWUSER_WIDTH = "8" *) 
  (* C_M_AXI_AXCACHE_EN = "0" *) 
  (* C_M_AXI_DATA_WIDTH = "64" *) 
  (* C_M_AXI_ID_WIDTH = "4" *) 
  (* C_M_INT_W_ORDER_EN = "0" *) 
  (* C_M_KEEP_WIDTH = "2" *) 
  (* C_M_NUM_AXI_READ = "16" *) 
  (* C_M_NUM_AXI_WRITE = "16" *) 
  (* C_M_NUM_CQ_AXI_READ = "8" *) 
  (* C_M_NUM_CQ_AXI_READQ = "2" *) 
  (* C_M_NUM_CQ_AXI_WRITE = "4" *) 
  (* C_M_NUM_CQ_AXI_WRITE_SCALE = "1" *) 
  (* C_NUMQ_PER_CHNL = "256" *) 
  (* C_NUM_AXI_DSC_CPL_DID = "64" *) 
  (* C_NUM_DSC_AXI_RID = "32" *) 
  (* C_NUM_DSC_PCIE_RID = "32" *) 
  (* C_NUM_MSIX_VECTORS = "32" *) 
  (* C_NUM_PCIE_DSC_CPL_DID = "256" *) 
  (* C_NUM_PCIE_TAGS = "64" *) 
  (* C_NUM_USER_INTR = "9" *) 
  (* C_NUM_USER_NEW_INTR = "6" *) 
  (* C_NUM_USR_IRQ = "1" *) 
  (* C_OLD_BRIDGE_TIMEOUT = "0" *) 
  (* C_OST_PR_CAP = "0" *) 
  (* C_PAGE_SIZE = "4096" *) 
  (* C_PARITY_CHECK = "0" *) 
  (* C_PARITY_GEN = "0" *) 
  (* C_PARITY_PROP = "0" *) 
  (* C_PCIEBAR2AXIBAR_0 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_0_SEC = "0" *) 
  (* C_PCIEBAR2AXIBAR_1 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_1_SEC = "0" *) 
  (* C_PCIEBAR2AXIBAR_2 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_2_SEC = "0" *) 
  (* C_PCIEBAR2AXIBAR_3 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_3_SEC = "0" *) 
  (* C_PCIEBAR2AXIBAR_4 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_4_SEC = "0" *) 
  (* C_PCIEBAR2AXIBAR_5 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_5_SEC = "0" *) 
  (* C_PCIEBAR2AXIBAR_6 = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_PCIEBAR2AXIBAR_6_SEC = "0" *) 
  (* C_PCIEBAR_AS = "1" *) 
  (* C_PCIEBAR_LEN_0 = "16" *) 
  (* C_PCIEBAR_LEN_1 = "20" *) 
  (* C_PCIEBAR_LEN_2 = "64" *) 
  (* C_PCIEBAR_LEN_3 = "64" *) 
  (* C_PCIEBAR_LEN_4 = "64" *) 
  (* C_PCIEBAR_LEN_5 = "64" *) 
  (* C_PCIEBAR_LEN_6 = "7" *) 
  (* C_PCIEBAR_NUM = "6" *) 
  (* C_PCIE_PFS_ENABLED = "1" *) 
  (* C_PCIE_PFS_SUPPORTED = "1" *) 
  (* C_PCIE_TDATA_WIDTH = "256" *) 
  (* C_PCIE_VFS_ENABLED = "0" *) 
  (* C_PCIE_VFS_SUPPORTED = "0" *) 
  (* C_PRI_ENABLE = "FALSE" *) 
  (* C_PR_CAP_NEXTPTR = "12'b000000000000" *) 
  (* C_PR_OFFSET = "30'b000000000000000000000100100100" *) 
  (* C_RD_BUFFER_ADDR_SIZE = "9" *) 
  (* C_RD_BUFFER_SIZE_BITS = "5" *) 
  (* C_SDMA_C2H_DESC_BYTES = "16" *) 
  (* C_SDMA_C2H_PERQ_DESC_STORE = "256" *) 
  (* C_SDMA_H2C_DESC_BYTES = "16" *) 
  (* C_SDMA_H2C_DESC_CMD_WIDTH = "128" *) 
  (* C_SDMA_H2C_PERQ_DESC_CMD_STORE = "128" *) 
  (* C_SDMA_MAX_BUF_SIZE = "4096" *) 
  (* C_SDMA_MIN_BUF_SIZE = "1024" *) 
  (* C_SLAVE_ERROR_POISON = "1'b1" *) 
  (* C_SLAVE_READ_64OS_EN = "0" *) 
  (* C_SMMU_EN = "0" *) 
  (* C_SRIOV_EN = "0" *) 
  (* C_S_AXIS_CC_USER_WIDTH = "33" *) 
  (* C_S_AXIS_CQ_USER_WIDTH = "85" *) 
  (* C_S_AXIS_DATA_WIDTH = "64" *) 
  (* C_S_AXI_ADDR_WIDTH = "64" *) 
  (* C_S_AXI_DATA_WIDTH = "64" *) 
  (* C_S_AXI_ID_WIDTH = "4" *) 
  (* C_S_AXI_REG_ENABLE = "1" *) 
  (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *) 
  (* C_S_KEEP_WIDTH = "2" *) 
  (* C_S_NUM_AXI_READ = "8" *) 
  (* C_S_NUM_AXI_WRITE = "8" *) 
  (* C_TIMEOUT0_SEL = "4'b1110" *) 
  (* C_TIMEOUT1_SEL = "4'b1111" *) 
  (* C_TIMEOUT_MULT = "3'b011" *) 
  (* C_USER_PTR = "16'b0000000011011000" *) 
  (* C_VSEC_CAP_ADDR = "12'b000100101000" *) 
  (* C_VSEC_CAP_LAST = "FALSE" *) 
  (* C_VSEC_ID = "16'b0000000000000000" *) 
  (* DMA_2RP = "FALSE" *) 
  (* DMA_EN = "1" *) 
  (* DMA_MM = "1" *) 
  (* DMA_ST = "0" *) 
  (* DSC_BYPASS_RD = "0" *) 
  (* DSC_BYPASS_WR = "0" *) 
  (* FUNC_MODE = "1" *) 
  (* H2C_XDMA_CHNL = "8'b00001111" *) 
  (* IMPL_TARGET = "SOFT" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* MM_SLAVE_EN = "0" *) 
  (* MPL_SIZE = "4096" *) 
  (* MRS_SIZE = "4096" *) 
  (* MSIX_PCIE_INTERNAL = "0" *) 
  (* MSIX_RX_DECODE_EN = "FALSE" *) 
  (* MSIX_VEC_NUM = "1024" *) 
  (* MULTQ_CHNL = "8'b00000000" *) 
  (* MULTQ_LL_CHNL = "8'b00001111" *) 
  (* MULTQ_MAX_CHNL = "48'b100000100000100000100000100000100000100000100000" *) 
  (* MULT_PF_DESIGN = "0" *) 
  (* PCIE_DSC_ENG_EN = "1" *) 
  (* PCIE_WBK_ENG_EN = "1" *) 
  (* PF0_MSIX_TAR_ID = "6'b001000" *) 
  (* PF1_MSIX_TAR_ID = "6'b001001" *) 
  (* PF_SWAP = "FALSE" *) 
  (* PL_DISABLE_UPCONFIG_CAPABLE = "FALSE" *) 
  (* PL_LINK_CAP_MAX_LINK_SPEED = "2" *) 
  (* PMON_EN = "1" *) 
  (* PROG_USR_IRQ_VEC_MAP = "0" *) 
  (* RBAR_ENABLE = "FALSE" *) 
  (* RQ_SEQ_NUM_IGNORE = "0" *) 
  (* RUN_BIT_FIX = "0" *) 
  (* SHELL_BRIDGE = "0" *) 
  (* STS_WIDTH = "8" *) 
  (* TCQ = "1" *) 
  (* TWO_AXILITE_BAR = "0" *) 
  (* USE_ATTR = "0" *) 
  (* USR_INT_EXPN = "0" *) 
  (* USR_MPL_SIZE = "4096" *) 
  (* USR_MRS_SIZE = "4096" *) 
  (* VERSION = "6" *) 
  (* XDMA_DSC_ENG = "1" *) 
  (* is_du_within_envelope = "true" *) 
  xdma_0_xdma_v4_1_29_udma_wrapper udma_wrapper
       (.\attr_dma[axi_slv_brdg_base_addr] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[axi_slv_multq_base_addr] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[axi_slv_xdma_base_addr] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[axibar_num] ({1'b0,1'b0,1'b0}),
        .\attr_dma[barlite0] ({1'b1,1'b1,1'b1}),
        .\attr_dma[barlite1] ({1'b0,1'b0,1'b0}),
        .\attr_dma[bypass_msix] (1'b0),
        .\attr_dma[ch_c2h_axi_dsc] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[ch_en] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[ch_h2c_axi_dsc] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[ch_multq] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[ch_multq_ll] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[ch_multq_max][0] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[ch_multq_max][1] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[ch_multq_max][2] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[ch_multq_max][3] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[ch_pfid][0] ({1'b0,1'b0}),
        .\attr_dma[ch_pfid][1] ({1'b0,1'b0}),
        .\attr_dma[ch_pfid][2] ({1'b0,1'b0}),
        .\attr_dma[ch_pfid][3] ({1'b0,1'b0}),
        .\attr_dma[ch_stream] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[cq_rcfg_en] (1'b1),
        .\attr_dma[data_width] ({1'b0,1'b0,1'b0}),
        .\attr_dma[enable] (1'b0),
        .\attr_dma[mask50] ({1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}),
        .\attr_dma[metering_enable] (1'b1),
        .\attr_dma[msi_rx_decode_en] (1'b1),
        .\attr_dma[pcie_if_parity_check] (1'b0),
        .\attr_dma[pciebar_num] ({1'b0,1'b0,1'b0}),
        .\attr_dma[root_port] (1'b0),
        .\attr_dma[rq_rcfg_en] (1'b0),
        .\attr_dma[slvlite_base0] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[slvlite_base1] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][axi_parity_chk_dis] (1'b0),
        .\attr_dma[spare][axi_slv_brdge_range] (1'b0),
        .\attr_dma[spare][axim_auser_mode] (1'b0),
        .\attr_dma[spare][axis_h2c_ext_cmp_en] (1'b0),
        .\attr_dma[spare][bdg_mst_rw_rlx_dis] (1'b0),
        .\attr_dma[spare][brdg_rro_en] (1'b0),
        .\attr_dma[spare][brdg_slv_pasid_en] (1'b0),
        .\attr_dma[spare][brdg_slv_pasid_offset] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][brdg_slv_shared_rdwr_pasid_dis] (1'b0),
        .\attr_dma[spare][brdg_slv_wr_pasid_offset] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][cfg_mgmt_ep_wr_dis] (1'b0),
        .\attr_dma[spare][cfg_space_delay_en] (1'b0),
        .\attr_dma[spare][dis_acc_irq] (1'b0),
        .\attr_dma[spare][dis_c2h_ctxt_mgr_fix] (1'b0),
        .\attr_dma[spare][dis_crdt_coal_depth_fix] (1'b0),
        .\attr_dma[spare][dis_h2c_sbe_dbe_err_fix] (1'b0),
        .\attr_dma[spare][dis_h2c_wrb_on_src_err_fix] (1'b0),
        .\attr_dma[spare][dis_pfch_evict_cache_fix] (1'b0),
        .\attr_dma[spare][dis_pfch_evict_lru_fix] (1'b0),
        .\attr_dma[spare][dis_timer_stall_fix] (1'b0),
        .\attr_dma[spare][dis_wrb_bad_cidx_chk_fix] (1'b0),
        .\attr_dma[spare][dis_wrb_prty_chk_fix] (1'b0),
        .\attr_dma[spare][dis_xdma_wcp_err_bsy_clr] (1'b0),
        .\attr_dma[spare][disable_port_id_check] (1'b0),
        .\attr_dma[spare][dma_aximm_rsp_clr] (1'b0),
        .\attr_dma[spare][dma_bar_ext_en] (1'b0),
        .\attr_dma[spare][dma_mm_linkdown_reset_dis] (1'b0),
        .\attr_dma[spare][dma_rq_0len_dis] (1'b0),
        .\attr_dma[spare][dma_rst_rc_rdy] (1'b0),
        .\attr_dma[spare][dsc_ctxt_err_on_rcp_flr_dis] (1'b0),
        .\attr_dma[spare][dsc_ctxt_err_on_rcp_ur_ca_dis] (1'b0),
        .\attr_dma[spare][dsc_ctxt_is_mm_en] (1'b0),
        .\attr_dma[spare][dsc_ecc_chk_dis] (1'b0),
        .\attr_dma[spare][dsc_qinv_on_err_dis] (1'b0),
        .\attr_dma[spare][dsc_rcp_evt_pri] (1'b0),
        .\attr_dma[spare][dsc_stall_irq_fl_dis] (1'b0),
        .\attr_dma[spare][dsc_upd_ovf_dis] (1'b0),
        .\attr_dma[spare][exp_rom_bar_to_axil] (1'b0),
        .\attr_dma[spare][fab_wb_dis] (1'b0),
        .\attr_dma[spare][fabric_reset_en] (1'b0),
        .\attr_dma[spare][fix_dbe_parity_dis] (1'b0),
        .\attr_dma[spare][full_upd_fix_dis] (1'b0),
        .\attr_dma[spare][ign_byp_irq_arm] (1'b0),
        .\attr_dma[spare][ign_pidx_upd_on_irq_arm] (1'b0),
        .\attr_dma[spare][mdma_dsc_wb_chk_all] (1'b0),
        .\attr_dma[spare][mdma_dsc_wb_imm_all] (1'b0),
        .\attr_dma[spare][mdma_eng_err_halt] (1'b0),
        .\attr_dma[spare][mdma_one_err_wb_dis] (1'b0),
        .\attr_dma[spare][mdma_sw_ctxt_clr_all] (1'b0),
        .\attr_dma[spare][mgmt_flr_done_en] (1'b0),
        .\attr_dma[spare][mgmt_flr_done_src_dis] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][misc_cap] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][mm_err_wbk_fix_dis] (1'b0),
        .\attr_dma[spare][mm_wbrq_ovf_fix_dis] (1'b0),
        .\attr_dma[spare][pasid_en] (1'b0),
        .\attr_dma[spare][pcie_mpl_reg_en] (1'b0),
        .\attr_dma[spare][pcie_mrs_reg_en] (1'b0),
        .\attr_dma[spare][pcie_rc_unmask_uc] (1'b0),
        .\attr_dma[spare][pcie_rq_pf_flr_check_dis] (1'b0),
        .\attr_dma[spare][pcie_rq_vf_bme_check_dis] (1'b0),
        .\attr_dma[spare][pcie_rq_vf_flr_check_dis] (1'b0),
        .\attr_dma[spare][qinv_arb_stall] (1'b0),
        .\attr_dma[spare][qinv_cnt_limit] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][qinv_limit_en] (1'b0),
        .\attr_dma[spare][rcv_crd_chk_dis] (1'b0),
        .\attr_dma[spare][rq_flr_check_dis] (1'b0),
        .\attr_dma[spare][rrq_disable_en] (1'b0),
        .\attr_dma[spare][rsv_use_h2c_data_aln] (1'b0),
        .\attr_dma[spare][shared_rdwr_pasid_dis] (1'b0),
        .\attr_dma[spare][slv_bresp_fix_dis] (1'b0),
        .\attr_dma[spare][slv_fnc_msk] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][st_rx_msg_if_en] (1'b0),
        .\attr_dma[spare][sw_crdt_fix_dis] (1'b0),
        .\attr_dma[spare][system_id] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][system_id_ovr] (1'b0),
        .\attr_dma[spare][tcp_timeout_exp] ({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][tm_dsc_sts_pidx_en] (1'b0),
        .\attr_dma[spare][trq_timeout_dat] (1'b0),
        .\attr_dma[spare][trq_timeout_rsp] (1'b0),
        .\attr_dma[spare][unused] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][use_stm_dsc_format] (1'b0),
        .\attr_dma[spare][vf_bar_num] ({1'b0,1'b0,1'b0}),
        .\attr_dma[spare][wb_sts_all] (1'b0),
        .\attr_dma[spare][wr_cmp_fix_dis] (1'b0),
        .\attr_dma[spare][xdma_byp_eng_flr_done] (1'b0),
        .\attr_dma[spare][xdma_c2h_axi_wr_cache][0] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][xdma_c2h_axi_wr_cache][1] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][xdma_c2h_axi_wr_cache][2] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][xdma_c2h_axi_wr_cache][3] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][xdma_c2h_axi_wr_sec] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][xdma_drain_dat_en] (1'b0),
        .\attr_dma[spare][xdma_drain_dsc_en] (1'b0),
        .\attr_dma[spare][xdma_h2c_axi_rd_cache][0] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][xdma_h2c_axi_rd_cache][1] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][xdma_h2c_axi_rd_cache][2] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][xdma_h2c_axi_rd_cache][3] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma[spare][xdma_h2c_axi_rd_sec] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[0][as] (1'b0),
        .\attr_dma_axibar2pciebar[0][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[0][base] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[0][highaddr] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[1][as] (1'b0),
        .\attr_dma_axibar2pciebar[1][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[1][base] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[1][highaddr] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[2][as] (1'b0),
        .\attr_dma_axibar2pciebar[2][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[2][base] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[2][highaddr] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[3][as] (1'b0),
        .\attr_dma_axibar2pciebar[3][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[3][base] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[3][highaddr] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[4][as] (1'b0),
        .\attr_dma_axibar2pciebar[4][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[4][base] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[4][highaddr] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[5][as] (1'b0),
        .\attr_dma_axibar2pciebar[5][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[5][base] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_axibar2pciebar[5][highaddr] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][0][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][0][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][0][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][0][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][0][len] ({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][0][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][0][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][0][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][1][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][1][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][1][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][1][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][1][len] ({1'b0,1'b0,1'b0,1'b1,1'b0,1'b1,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][1][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][1][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][1][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][2][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][2][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][2][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][2][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][2][len] ({1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][2][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][2][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][2][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][3][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][3][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][3][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][3][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][3][len] ({1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][3][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][3][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][3][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][4][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][4][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][4][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][4][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][4][len] ({1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][4][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][4][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][4][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][5][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][5][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][5][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][5][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][5][len] ({1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][5][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][5][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][5][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][6][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][6][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][6][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][6][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][6][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}),
        .\attr_dma_pciebar2axibar_pf[0][6][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[0][6][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[0][6][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][0][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][0][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][0][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][0][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][0][len] ({1'b0,1'b0,1'b0,1'b1,1'b1,1'b0,1'b0,1'b1}),
        .\attr_dma_pciebar2axibar_pf[1][0][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][0][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][0][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][1][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][1][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][1][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][1][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][1][len] ({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b1}),
        .\attr_dma_pciebar2axibar_pf[1][1][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][1][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][1][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][2][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][2][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][2][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][2][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][2][len] ({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b1}),
        .\attr_dma_pciebar2axibar_pf[1][2][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][2][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][2][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][3][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][3][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][3][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][3][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][3][len] ({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b1}),
        .\attr_dma_pciebar2axibar_pf[1][3][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][3][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][3][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][4][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][4][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][4][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][4][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][4][len] ({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b1}),
        .\attr_dma_pciebar2axibar_pf[1][4][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][4][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][4][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][5][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][5][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][5][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][5][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][5][len] ({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b1}),
        .\attr_dma_pciebar2axibar_pf[1][5][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][5][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][5][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][6][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][6][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][6][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][6][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][6][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}),
        .\attr_dma_pciebar2axibar_pf[1][6][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[1][6][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[1][6][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][0][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][0][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][0][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][0][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][0][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][0][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][0][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][0][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][1][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][1][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][1][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][1][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][1][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][1][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][1][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][1][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][2][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][2][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][2][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][2][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][2][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][2][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][2][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][2][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][3][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][3][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][3][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][3][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][3][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][3][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][3][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][3][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][4][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][4][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][4][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][4][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][4][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][4][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][4][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][4][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][5][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][5][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][5][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][5][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][5][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][5][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][5][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][5][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][6][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][6][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][6][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][6][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][6][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][6][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[2][6][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[2][6][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][0][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][0][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][0][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][0][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][0][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][0][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][0][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][0][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][1][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][1][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][1][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][1][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][1][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][1][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][1][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][1][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][2][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][2][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][2][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][2][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][2][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][2][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][2][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][2][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][3][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][3][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][3][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][3][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][3][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][3][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][3][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][3][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][4][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][4][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][4][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][4][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][4][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][4][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][4][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][4][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][5][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][5][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][5][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][5][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][5][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][5][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][5][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][5][sec_vf] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][6][bar] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][6][bar_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][6][cache] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][6][cache_vf] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][6][len] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][6][len_vf] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pciebar2axibar_pf[3][6][sec] (1'b0),
        .\attr_dma_pciebar2axibar_pf[3][6][sec_vf] (1'b0),
        .\attr_dma_pf[0][ch_alloc] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[0][firstvf_offset] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[0][multq_bits] ({1'b0,1'b0,1'b0}),
        .\attr_dma_pf[0][multq_chbits] ({1'b0,1'b0}),
        .\attr_dma_pf[0][multq_maxq] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[0][multq_vfqbits] ({1'b0,1'b0,1'b0}),
        .\attr_dma_pf[0][num_vfs] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[0][vfmaxq] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[1][ch_alloc] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[1][firstvf_offset] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[1][multq_bits] ({1'b0,1'b0,1'b0}),
        .\attr_dma_pf[1][multq_chbits] ({1'b0,1'b0}),
        .\attr_dma_pf[1][multq_maxq] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[1][multq_vfqbits] ({1'b0,1'b0,1'b0}),
        .\attr_dma_pf[1][num_vfs] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[1][vfmaxq] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[2][ch_alloc] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[2][firstvf_offset] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[2][multq_bits] ({1'b0,1'b0,1'b0}),
        .\attr_dma_pf[2][multq_chbits] ({1'b0,1'b0}),
        .\attr_dma_pf[2][multq_maxq] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[2][multq_vfqbits] ({1'b0,1'b0,1'b0}),
        .\attr_dma_pf[2][num_vfs] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[2][vfmaxq] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[3][ch_alloc] ({1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[3][firstvf_offset] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[3][multq_bits] ({1'b0,1'b0,1'b0}),
        .\attr_dma_pf[3][multq_chbits] ({1'b0,1'b0}),
        .\attr_dma_pf[3][multq_maxq] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[3][multq_vfqbits] ({1'b0,1'b0,1'b0}),
        .\attr_dma_pf[3][num_vfs] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\attr_dma_pf[3][vfmaxq] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_aresetn(NLW_udma_wrapper_axi_aresetn_UNCONNECTED),
        .blk_cfg_ext_function_number_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .blk_cfg_ext_read_data_o(NLW_udma_wrapper_blk_cfg_ext_read_data_o_UNCONNECTED[31:0]),
        .blk_cfg_ext_read_data_valid_o(NLW_udma_wrapper_blk_cfg_ext_read_data_valid_o_UNCONNECTED),
        .blk_cfg_ext_read_received_i(1'b0),
        .blk_cfg_ext_register_number_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .blk_cfg_ext_write_byte_enable_i({1'b0,1'b0,1'b0,1'b0}),
        .blk_cfg_ext_write_data_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .blk_cfg_ext_write_received_i(1'b0),
        .\c2h_desc_avail_inc_num[0] (\NLW_udma_wrapper_c2h_desc_avail_inc_num[0]_UNCONNECTED [12:0]),
        .\c2h_desc_avail_inc_qid[0] (\NLW_udma_wrapper_c2h_desc_avail_inc_qid[0]_UNCONNECTED [4:0]),
        .c2h_desc_avail_inc_vld(NLW_udma_wrapper_c2h_desc_avail_inc_vld_UNCONNECTED[0]),
        .c2h_dsc_byp_ctl({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_dst_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_len({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_dsc_byp_load(1'b0),
        .c2h_dsc_byp_ready(NLW_udma_wrapper_c2h_dsc_byp_ready_UNCONNECTED[0]),
        .c2h_dsc_byp_src_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .c2h_pktin_accept(NLW_udma_wrapper_c2h_pktin_accept_UNCONNECTED[0]),
        .\c2h_pktin_drop[0] (\NLW_udma_wrapper_c2h_pktin_drop[0]_UNCONNECTED [7:0]),
        .c2h_sts(NLW_udma_wrapper_c2h_sts_UNCONNECTED[7:0]),
        .cfg_status_ats_en(NLW_udma_wrapper_cfg_status_ats_en_UNCONNECTED),
        .cfg_status_ats_stu(NLW_udma_wrapper_cfg_status_ats_stu_UNCONNECTED[4:0]),
        .cfg_status_clr_s(1'b0),
        .cfg_status_ost_pr_alloc(NLW_udma_wrapper_cfg_status_ost_pr_alloc_UNCONNECTED[31:0]),
        .cfg_status_pr_en(NLW_udma_wrapper_cfg_status_pr_en_UNCONNECTED),
        .cfg_status_pr_rf(NLW_udma_wrapper_cfg_status_pr_rf_UNCONNECTED),
        .cfg_status_pr_rst(NLW_udma_wrapper_cfg_status_pr_rst_UNCONNECTED),
        .cfg_status_pr_uprgi(NLW_udma_wrapper_cfg_status_pr_uprgi_UNCONNECTED),
        .cfg_status_set_rf(1'b0),
        .cfg_status_set_s(1'b0),
        .cfg_status_set_uprgi(1'b0),
        .\dsc_in\.crd[num] (\NLW_udma_wrapper_dsc_in\.crd[num]_UNCONNECTED [8:0]),
        .\dsc_in\.crd[qid] (\NLW_udma_wrapper_dsc_in\.crd[qid]_UNCONNECTED [7:0]),
        .\dsc_in\.crd[vld] (\NLW_udma_wrapper_dsc_in\.crd[vld]_UNCONNECTED ),
        .\dsc_in\.dsc[chn] ({1'b0,1'b0}),
        .\dsc_in\.dsc[cidx] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\dsc_in\.dsc[dir] (1'b0),
        .\dsc_in\.dsc[dsc] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\dsc_in\.dsc[qid] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\dsc_in\.dsc[qst] ({1'b0,1'b0,1'b0,1'b0}),
        .\dsc_in\.dsc[siz] ({1'b0,1'b0,1'b0}),
        .\dsc_in\.dsc[vld] ({1'b0,1'b0,1'b0,1'b0}),
        .\dsc_in\.dsc[wbi] (1'b0),
        .\dsc_in\.dsc[wbi_chk] (1'b0),
        .\dsc_out\.crd[chn] ({1'b0,1'b0}),
        .\dsc_out\.crd[clr] (1'b0),
        .\dsc_out\.crd[num] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\dsc_out\.crd[qid] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\dsc_out\.crd[vld] (1'b0),
        .\dsc_out\.dsc[chn] (\NLW_udma_wrapper_dsc_out\.dsc[chn]_UNCONNECTED [1:0]),
        .\dsc_out\.dsc[cidx] (\NLW_udma_wrapper_dsc_out\.dsc[cidx]_UNCONNECTED [15:0]),
        .\dsc_out\.dsc[dir] (\NLW_udma_wrapper_dsc_out\.dsc[dir]_UNCONNECTED ),
        .\dsc_out\.dsc[dsc] (\NLW_udma_wrapper_dsc_out\.dsc[dsc]_UNCONNECTED [255:0]),
        .\dsc_out\.dsc[qid] (\NLW_udma_wrapper_dsc_out\.dsc[qid]_UNCONNECTED [7:0]),
        .\dsc_out\.dsc[qst] (\NLW_udma_wrapper_dsc_out\.dsc[qst]_UNCONNECTED [3:0]),
        .\dsc_out\.dsc[siz] (\NLW_udma_wrapper_dsc_out\.dsc[siz]_UNCONNECTED [2:0]),
        .\dsc_out\.dsc[vld] (\NLW_udma_wrapper_dsc_out\.dsc[vld]_UNCONNECTED [3:0]),
        .\dsc_out\.dsc[wbi] (\NLW_udma_wrapper_dsc_out\.dsc[wbi]_UNCONNECTED ),
        .\dsc_out\.dsc[wbi_chk] (\NLW_udma_wrapper_dsc_out\.dsc[wbi_chk]_UNCONNECTED ),
        .\fabric_in\.flr_done_fnc ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\fabric_in\.flr_done_vld (1'b0),
        .\fabric_in\.usr_irq_clr (1'b0),
        .\fabric_in\.usr_irq_fnc ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\fabric_in\.usr_irq_set (1'b0),
        .\fabric_in\.usr_irq_vec ({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\fabric_out\.c2h_dsc_avail_inc_chn (\NLW_udma_wrapper_fabric_out\.c2h_dsc_avail_inc_chn_UNCONNECTED [1:0]),
        .\fabric_out\.c2h_dsc_avail_inc_num (\NLW_udma_wrapper_fabric_out\.c2h_dsc_avail_inc_num_UNCONNECTED [15:0]),
        .\fabric_out\.c2h_dsc_avail_inc_qid (\NLW_udma_wrapper_fabric_out\.c2h_dsc_avail_inc_qid_UNCONNECTED [7:0]),
        .\fabric_out\.c2h_dsc_avail_inc_state (\NLW_udma_wrapper_fabric_out\.c2h_dsc_avail_inc_state_UNCONNECTED [1:0]),
        .\fabric_out\.c2h_dsc_avail_inc_vld (\NLW_udma_wrapper_fabric_out\.c2h_dsc_avail_inc_vld_UNCONNECTED ),
        .\fabric_out\.c2h_sts[0] (\NLW_udma_wrapper_fabric_out\.c2h_sts[0]_UNCONNECTED [7:0]),
        .\fabric_out\.c2h_sts[1] (\NLW_udma_wrapper_fabric_out\.c2h_sts[1]_UNCONNECTED [7:0]),
        .\fabric_out\.c2h_sts[2] (\NLW_udma_wrapper_fabric_out\.c2h_sts[2]_UNCONNECTED [7:0]),
        .\fabric_out\.c2h_sts[3] (\NLW_udma_wrapper_fabric_out\.c2h_sts[3]_UNCONNECTED [7:0]),
        .\fabric_out\.flr_clr (\NLW_udma_wrapper_fabric_out\.flr_clr_UNCONNECTED ),
        .\fabric_out\.flr_fnc (\NLW_udma_wrapper_fabric_out\.flr_fnc_UNCONNECTED [7:0]),
        .\fabric_out\.flr_set (\NLW_udma_wrapper_fabric_out\.flr_set_UNCONNECTED ),
        .\fabric_out\.h2c_sts[0] (\NLW_udma_wrapper_fabric_out\.h2c_sts[0]_UNCONNECTED [7:0]),
        .\fabric_out\.h2c_sts[1] (\NLW_udma_wrapper_fabric_out\.h2c_sts[1]_UNCONNECTED [7:0]),
        .\fabric_out\.h2c_sts[2] (\NLW_udma_wrapper_fabric_out\.h2c_sts[2]_UNCONNECTED [7:0]),
        .\fabric_out\.h2c_sts[3] (\NLW_udma_wrapper_fabric_out\.h2c_sts[3]_UNCONNECTED [7:0]),
        .\fabric_out\.s_axis_c2h_tstat (\NLW_udma_wrapper_fabric_out\.s_axis_c2h_tstat_UNCONNECTED [7:0]),
        .\fabric_out\.s_axis_c2h_tstat_chn (\NLW_udma_wrapper_fabric_out\.s_axis_c2h_tstat_chn_UNCONNECTED [1:0]),
        .\fabric_out\.s_axis_c2h_tstat_qid (\NLW_udma_wrapper_fabric_out\.s_axis_c2h_tstat_qid_UNCONNECTED [4:0]),
        .\fabric_out\.s_axis_c2h_tstat_vld (\NLW_udma_wrapper_fabric_out\.s_axis_c2h_tstat_vld_UNCONNECTED ),
        .\fabric_out\.usr_irq_fail (\NLW_udma_wrapper_fabric_out\.usr_irq_fail_UNCONNECTED ),
        .\fabric_out\.usr_irq_rfnc (\NLW_udma_wrapper_fabric_out\.usr_irq_rfnc_UNCONNECTED [7:0]),
        .\fabric_out\.usr_irq_rvec (\NLW_udma_wrapper_fabric_out\.usr_irq_rvec_UNCONNECTED [4:0]),
        .\fabric_out\.usr_irq_sent (\NLW_udma_wrapper_fabric_out\.usr_irq_sent_UNCONNECTED ),
        .h2c_desc_cmd_in_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_desc_cmd_in_qid({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_desc_cmd_in_rdy(NLW_udma_wrapper_h2c_desc_cmd_in_rdy_UNCONNECTED),
        .h2c_desc_cmd_in_vld(1'b0),
        .h2c_desc_cmd_out_data(NLW_udma_wrapper_h2c_desc_cmd_out_data_UNCONNECTED[127:0]),
        .h2c_desc_cmd_out_qid(NLW_udma_wrapper_h2c_desc_cmd_out_qid_UNCONNECTED[4:0]),
        .h2c_desc_cmd_out_qrdy({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .h2c_desc_cmd_out_rdy(1'b0),
        .h2c_desc_cmd_out_vld(NLW_udma_wrapper_h2c_desc_cmd_out_vld_UNCONNECTED),
        .h2c_dsc_byp_ctl({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_dst_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_len({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_dsc_byp_load(1'b0),
        .h2c_dsc_byp_ready(NLW_udma_wrapper_h2c_dsc_byp_ready_UNCONNECTED[0]),
        .h2c_dsc_byp_src_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .h2c_sts(NLW_udma_wrapper_h2c_sts_UNCONNECTED[7:0]),
        .link_up(user_lnk_up),
        .m_axi_araddr(m_axi_araddr_temp),
        .m_axi_arburst({NLW_udma_wrapper_m_axi_arburst_UNCONNECTED[1],\^m_axi_arburst [0]}),
        .m_axi_arcache(NLW_udma_wrapper_m_axi_arcache_UNCONNECTED[3:0]),
        .m_axi_arid(NLW_udma_wrapper_m_axi_arid_UNCONNECTED[3:0]),
        .m_axi_arlen(m_axi_arlen),
        .m_axi_arlock(NLW_udma_wrapper_m_axi_arlock_UNCONNECTED),
        .m_axi_arprot(NLW_udma_wrapper_m_axi_arprot_UNCONNECTED[2:0]),
        .m_axi_arready(m_axi_arready),
        .m_axi_arsize({NLW_udma_wrapper_m_axi_arsize_UNCONNECTED[2],\^m_axi_arsize [1:0]}),
        .m_axi_arvalid(m_axi_arvalid),
        .m_axi_awaddr(m_axi_awaddr_temp),
        .m_axi_awburst({NLW_udma_wrapper_m_axi_awburst_UNCONNECTED[1],\^m_axi_awburst [0]}),
        .m_axi_awcache(NLW_udma_wrapper_m_axi_awcache_UNCONNECTED[3:0]),
        .m_axi_awid(NLW_udma_wrapper_m_axi_awid_UNCONNECTED[3:0]),
        .m_axi_awlen(m_axi_awlen),
        .m_axi_awlock(NLW_udma_wrapper_m_axi_awlock_UNCONNECTED),
        .m_axi_awprot(NLW_udma_wrapper_m_axi_awprot_UNCONNECTED[2:0]),
        .m_axi_awready(m_axi_awready),
        .m_axi_awsize({NLW_udma_wrapper_m_axi_awsize_UNCONNECTED[2],\^m_axi_awsize [1:0]}),
        .m_axi_awvalid(m_axi_awvalid),
        .m_axi_bid(m_axi_bid),
        .m_axi_bready(m_axi_bready),
        .m_axi_bresp(m_axi_bresp),
        .m_axi_bvalid(m_axi_bvalid),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rdataeccparity({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rid(m_axi_rid),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rresp(m_axi_rresp),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_wdata(m_axi_wdata),
        .m_axi_wdataeccparity(NLW_udma_wrapper_m_axi_wdataeccparity_UNCONNECTED[7:0]),
        .m_axi_wlast(m_axi_wlast),
        .m_axi_wready(m_axi_wready),
        .m_axi_wstrb(m_axi_wstrb),
        .m_axi_wvalid(m_axi_wvalid),
        .m_axib_araddr(m_axib_araddr_temp),
        .m_axib_arburst(NLW_udma_wrapper_m_axib_arburst_UNCONNECTED[1:0]),
        .m_axib_arcache(NLW_udma_wrapper_m_axib_arcache_UNCONNECTED[3:0]),
        .m_axib_arid(NLW_udma_wrapper_m_axib_arid_UNCONNECTED[3:0]),
        .m_axib_arlen(m_axib_arlen),
        .m_axib_arlock(NLW_udma_wrapper_m_axib_arlock_UNCONNECTED),
        .m_axib_arprot({NLW_udma_wrapper_m_axib_arprot_UNCONNECTED[2],\^m_axib_arprot [1:0]}),
        .m_axib_arready(m_axib_arready),
        .m_axib_arsize({NLW_udma_wrapper_m_axib_arsize_UNCONNECTED[2],\^m_axib_arsize [1:0]}),
        .m_axib_aruser(NLW_udma_wrapper_m_axib_aruser_UNCONNECTED[7:0]),
        .m_axib_arvalid(m_axib_arvalid),
        .m_axib_awaddr(m_axib_awaddr_temp),
        .m_axib_awburst(NLW_udma_wrapper_m_axib_awburst_UNCONNECTED[1:0]),
        .m_axib_awcache(NLW_udma_wrapper_m_axib_awcache_UNCONNECTED[3:0]),
        .m_axib_awid(NLW_udma_wrapper_m_axib_awid_UNCONNECTED[3:0]),
        .m_axib_awlen(m_axib_awlen),
        .m_axib_awlock(NLW_udma_wrapper_m_axib_awlock_UNCONNECTED),
        .m_axib_awprot({NLW_udma_wrapper_m_axib_awprot_UNCONNECTED[2],\^m_axib_awprot [1:0]}),
        .m_axib_awready(m_axib_awready),
        .m_axib_awsize({NLW_udma_wrapper_m_axib_awsize_UNCONNECTED[2],\^m_axib_awsize [1:0]}),
        .m_axib_awuser(NLW_udma_wrapper_m_axib_awuser_UNCONNECTED[7:0]),
        .m_axib_awvalid(m_axib_awvalid),
        .m_axib_bid({1'b0,1'b0,1'b0,1'b0}),
        .m_axib_bready(m_axib_bready),
        .m_axib_bresp({1'b0,1'b0}),
        .m_axib_bvalid(m_axib_bvalid),
        .m_axib_rdata(m_axib_rdata),
        .m_axib_rdataeccparity({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axib_rid({1'b0,1'b0,1'b0,1'b0}),
        .m_axib_rlast(m_axib_rlast),
        .m_axib_rready(m_axib_rready),
        .m_axib_rresp(m_axib_rresp),
        .m_axib_rvalid(m_axib_rvalid),
        .m_axib_wdata(m_axib_wdata),
        .m_axib_wdataeccparity({udma_wrapper_n_12224,udma_wrapper_n_12225,udma_wrapper_n_12226,udma_wrapper_n_12227,udma_wrapper_n_12228,udma_wrapper_n_12229,udma_wrapper_n_12230,udma_wrapper_n_12231}),
        .m_axib_wlast(m_axib_wlast),
        .m_axib_wready(m_axib_wready),
        .m_axib_wstrb(m_axib_wstrb),
        .m_axib_wvalid(m_axib_wvalid),
        .m_axil_araddr({udma_wrapper_n_12673,udma_wrapper_n_12674,udma_wrapper_n_12675,udma_wrapper_n_12676,udma_wrapper_n_12677,udma_wrapper_n_12678,udma_wrapper_n_12679,udma_wrapper_n_12680,udma_wrapper_n_12681,udma_wrapper_n_12682,udma_wrapper_n_12683,udma_wrapper_n_12684,udma_wrapper_n_12685,udma_wrapper_n_12686,udma_wrapper_n_12687,udma_wrapper_n_12688,udma_wrapper_n_12689,udma_wrapper_n_12690,udma_wrapper_n_12691,udma_wrapper_n_12692,udma_wrapper_n_12693,udma_wrapper_n_12694,udma_wrapper_n_12695,udma_wrapper_n_12696,udma_wrapper_n_12697,udma_wrapper_n_12698,udma_wrapper_n_12699,udma_wrapper_n_12700,udma_wrapper_n_12701,udma_wrapper_n_12702,udma_wrapper_n_12703,udma_wrapper_n_12704}),
        .m_axil_arprot(NLW_udma_wrapper_m_axil_arprot_UNCONNECTED[2:0]),
        .m_axil_arready(1'b0),
        .m_axil_aruser(NLW_udma_wrapper_m_axil_aruser_UNCONNECTED[7:0]),
        .m_axil_arvalid(NLW_udma_wrapper_m_axil_arvalid_UNCONNECTED),
        .m_axil_awaddr({udma_wrapper_n_12591,udma_wrapper_n_12592,udma_wrapper_n_12593,udma_wrapper_n_12594,udma_wrapper_n_12595,udma_wrapper_n_12596,udma_wrapper_n_12597,udma_wrapper_n_12598,udma_wrapper_n_12599,udma_wrapper_n_12600,udma_wrapper_n_12601,udma_wrapper_n_12602,udma_wrapper_n_12603,udma_wrapper_n_12604,udma_wrapper_n_12605,udma_wrapper_n_12606,udma_wrapper_n_12607,udma_wrapper_n_12608,udma_wrapper_n_12609,udma_wrapper_n_12610,udma_wrapper_n_12611,udma_wrapper_n_12612,udma_wrapper_n_12613,udma_wrapper_n_12614,udma_wrapper_n_12615,udma_wrapper_n_12616,udma_wrapper_n_12617,udma_wrapper_n_12618,udma_wrapper_n_12619,udma_wrapper_n_12620,udma_wrapper_n_12621,udma_wrapper_n_12622}),
        .m_axil_awprot(NLW_udma_wrapper_m_axil_awprot_UNCONNECTED[2:0]),
        .m_axil_awready(1'b0),
        .m_axil_awuser(NLW_udma_wrapper_m_axil_awuser_UNCONNECTED[7:0]),
        .m_axil_awvalid(NLW_udma_wrapper_m_axil_awvalid_UNCONNECTED),
        .m_axil_bready(NLW_udma_wrapper_m_axil_bready_UNCONNECTED),
        .m_axil_bresp({1'b0,1'b0}),
        .m_axil_bvalid(1'b0),
        .m_axil_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axil_rready(NLW_udma_wrapper_m_axil_rready_UNCONNECTED),
        .m_axil_rresp({1'b0,1'b0}),
        .m_axil_rvalid(1'b0),
        .m_axil_wdata({udma_wrapper_n_12635,udma_wrapper_n_12636,udma_wrapper_n_12637,udma_wrapper_n_12638,udma_wrapper_n_12639,udma_wrapper_n_12640,udma_wrapper_n_12641,udma_wrapper_n_12642,udma_wrapper_n_12643,udma_wrapper_n_12644,udma_wrapper_n_12645,udma_wrapper_n_12646,udma_wrapper_n_12647,udma_wrapper_n_12648,udma_wrapper_n_12649,udma_wrapper_n_12650,udma_wrapper_n_12651,udma_wrapper_n_12652,udma_wrapper_n_12653,udma_wrapper_n_12654,udma_wrapper_n_12655,udma_wrapper_n_12656,udma_wrapper_n_12657,udma_wrapper_n_12658,udma_wrapper_n_12659,udma_wrapper_n_12660,udma_wrapper_n_12661,udma_wrapper_n_12662,udma_wrapper_n_12663,udma_wrapper_n_12664,udma_wrapper_n_12665,udma_wrapper_n_12666}),
        .m_axil_wready(1'b0),
        .m_axil_wstrb({udma_wrapper_n_12667,udma_wrapper_n_12668,udma_wrapper_n_12669,udma_wrapper_n_12670}),
        .m_axil_wvalid(NLW_udma_wrapper_m_axil_wvalid_UNCONNECTED),
        .\m_axis_cc\.tdata ({udma_wrapper_n_10858,udma_wrapper_n_10859,udma_wrapper_n_10860,udma_wrapper_n_10861,udma_wrapper_n_10862,udma_wrapper_n_10863,udma_wrapper_n_10864,udma_wrapper_n_10865,udma_wrapper_n_10866,udma_wrapper_n_10867,udma_wrapper_n_10868,udma_wrapper_n_10869,udma_wrapper_n_10870,udma_wrapper_n_10871,udma_wrapper_n_10872,udma_wrapper_n_10873,udma_wrapper_n_10874,udma_wrapper_n_10875,udma_wrapper_n_10876,udma_wrapper_n_10877,udma_wrapper_n_10878,udma_wrapper_n_10879,udma_wrapper_n_10880,udma_wrapper_n_10881,udma_wrapper_n_10882,udma_wrapper_n_10883,udma_wrapper_n_10884,udma_wrapper_n_10885,udma_wrapper_n_10886,udma_wrapper_n_10887,udma_wrapper_n_10888,udma_wrapper_n_10889,udma_wrapper_n_10890,udma_wrapper_n_10891,udma_wrapper_n_10892,udma_wrapper_n_10893,udma_wrapper_n_10894,udma_wrapper_n_10895,udma_wrapper_n_10896,udma_wrapper_n_10897,udma_wrapper_n_10898,udma_wrapper_n_10899,udma_wrapper_n_10900,udma_wrapper_n_10901,udma_wrapper_n_10902,udma_wrapper_n_10903,udma_wrapper_n_10904,udma_wrapper_n_10905,udma_wrapper_n_10906,udma_wrapper_n_10907,udma_wrapper_n_10908,udma_wrapper_n_10909,udma_wrapper_n_10910,udma_wrapper_n_10911,udma_wrapper_n_10912,udma_wrapper_n_10913,udma_wrapper_n_10914,udma_wrapper_n_10915,udma_wrapper_n_10916,udma_wrapper_n_10917,udma_wrapper_n_10918,udma_wrapper_n_10919,udma_wrapper_n_10920,udma_wrapper_n_10921}),
        .\m_axis_cc\.tkeep (\NLW_udma_wrapper_m_axis_cc\.tkeep_UNCONNECTED [1:0]),
        .\m_axis_cc\.tlast (udma_wrapper_n_10955),
        .\m_axis_cc\.tready (xdma_0_pcie2_to_pcie3_wrapper_i_n_312),
        .\m_axis_cc\.tuser (\NLW_udma_wrapper_m_axis_cc\.tuser_UNCONNECTED [32:0]),
        .\m_axis_cc\.tvalid (udma_wrapper_n_10958),
        .m_axis_cq_tdata(NLW_udma_wrapper_m_axis_cq_tdata_UNCONNECTED[63:0]),
        .m_axis_cq_tkeep(NLW_udma_wrapper_m_axis_cq_tkeep_UNCONNECTED[1:0]),
        .m_axis_cq_tlast(NLW_udma_wrapper_m_axis_cq_tlast_UNCONNECTED),
        .m_axis_cq_tready(1'b0),
        .m_axis_cq_tuser(NLW_udma_wrapper_m_axis_cq_tuser_UNCONNECTED[84:0]),
        .m_axis_cq_tvalid(NLW_udma_wrapper_m_axis_cq_tvalid_UNCONNECTED),
        .m_axis_h2c_tdata(NLW_udma_wrapper_m_axis_h2c_tdata_UNCONNECTED[63:0]),
        .m_axis_h2c_tkeep(NLW_udma_wrapper_m_axis_h2c_tkeep_UNCONNECTED[7:0]),
        .m_axis_h2c_tlast(NLW_udma_wrapper_m_axis_h2c_tlast_UNCONNECTED[0]),
        .m_axis_h2c_tparity(NLW_udma_wrapper_m_axis_h2c_tparity_UNCONNECTED[7:0]),
        .m_axis_h2c_tready(1'b0),
        .m_axis_h2c_tuser(NLW_udma_wrapper_m_axis_h2c_tuser_UNCONNECTED[47:0]),
        .m_axis_h2c_tvalid(NLW_udma_wrapper_m_axis_h2c_tvalid_UNCONNECTED[0]),
        .\m_axis_rq\.tdata ({udma_wrapper_n_10730,udma_wrapper_n_10731,udma_wrapper_n_10732,udma_wrapper_n_10733,udma_wrapper_n_10734,udma_wrapper_n_10735,udma_wrapper_n_10736,udma_wrapper_n_10737,udma_wrapper_n_10738,udma_wrapper_n_10739,udma_wrapper_n_10740,udma_wrapper_n_10741,udma_wrapper_n_10742,udma_wrapper_n_10743,udma_wrapper_n_10744,udma_wrapper_n_10745,udma_wrapper_n_10746,udma_wrapper_n_10747,udma_wrapper_n_10748,udma_wrapper_n_10749,udma_wrapper_n_10750,udma_wrapper_n_10751,udma_wrapper_n_10752,udma_wrapper_n_10753,udma_wrapper_n_10754,udma_wrapper_n_10755,udma_wrapper_n_10756,udma_wrapper_n_10757,udma_wrapper_n_10758,udma_wrapper_n_10759,udma_wrapper_n_10760,udma_wrapper_n_10761,udma_wrapper_n_10762,udma_wrapper_n_10763,udma_wrapper_n_10764,udma_wrapper_n_10765,udma_wrapper_n_10766,udma_wrapper_n_10767,udma_wrapper_n_10768,udma_wrapper_n_10769,udma_wrapper_n_10770,udma_wrapper_n_10771,udma_wrapper_n_10772,udma_wrapper_n_10773,udma_wrapper_n_10774,udma_wrapper_n_10775,udma_wrapper_n_10776,udma_wrapper_n_10777,udma_wrapper_n_10778,udma_wrapper_n_10779,udma_wrapper_n_10780,udma_wrapper_n_10781,udma_wrapper_n_10782,udma_wrapper_n_10783,udma_wrapper_n_10784,udma_wrapper_n_10785,udma_wrapper_n_10786,udma_wrapper_n_10787,udma_wrapper_n_10788,udma_wrapper_n_10789,udma_wrapper_n_10790,udma_wrapper_n_10791,udma_wrapper_n_10792,udma_wrapper_n_10793}),
        .\m_axis_rq\.tkeep (\NLW_udma_wrapper_m_axis_rq\.tkeep_UNCONNECTED [1:0]),
        .\m_axis_rq\.tlast (udma_wrapper_n_10794),
        .\m_axis_rq\.tready (xdma_0_pcie2_to_pcie3_wrapper_i_n_168),
        .\m_axis_rq\.tuser ({\NLW_udma_wrapper_m_axis_rq\.tuser_UNCONNECTED [59:28],udma_wrapper_n_10827,udma_wrapper_n_10828,udma_wrapper_n_10829,udma_wrapper_n_10830,\NLW_udma_wrapper_m_axis_rq\.tuser_UNCONNECTED [23:8],udma_wrapper_n_10847,udma_wrapper_n_10848,udma_wrapper_n_10849,udma_wrapper_n_10850,udma_wrapper_n_10851,udma_wrapper_n_10852,udma_wrapper_n_10853,udma_wrapper_n_10854}),
        .\m_axis_rq\.tvalid (udma_wrapper_n_10857),
        .\mi_c2h0_dat\.radr (\mi_c2h0_dat\.radr ),
        .\mi_c2h0_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_c2h0_dat\.rdat }),
        .\mi_c2h0_dat\.rdbe (1'b0),
        .\mi_c2h0_dat\.ren (\NLW_udma_wrapper_mi_c2h0_dat\.ren_UNCONNECTED ),
        .\mi_c2h0_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h0_dat\.rsbe (1'b0),
        .\mi_c2h0_dat\.wadr (\mi_c2h0_dat\.wadr ),
        .\mi_c2h0_dat\.wdat ({\NLW_udma_wrapper_mi_c2h0_dat\.wdat_UNCONNECTED [511:64],\mi_c2h0_dat\.wdat }),
        .\mi_c2h0_dat\.wen (\mi_c2h0_dat\.wen ),
        .\mi_c2h0_dat\.wpar (\NLW_udma_wrapper_mi_c2h0_dat\.wpar_UNCONNECTED [63:0]),
        .\mi_c2h1_dat\.radr (\NLW_udma_wrapper_mi_c2h1_dat\.radr_UNCONNECTED [8:0]),
        .\mi_c2h1_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h1_dat\.rdbe (1'b0),
        .\mi_c2h1_dat\.ren (\NLW_udma_wrapper_mi_c2h1_dat\.ren_UNCONNECTED ),
        .\mi_c2h1_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h1_dat\.rsbe (1'b0),
        .\mi_c2h1_dat\.wadr (\NLW_udma_wrapper_mi_c2h1_dat\.wadr_UNCONNECTED [8:0]),
        .\mi_c2h1_dat\.wdat (\NLW_udma_wrapper_mi_c2h1_dat\.wdat_UNCONNECTED [511:0]),
        .\mi_c2h1_dat\.wen (\NLW_udma_wrapper_mi_c2h1_dat\.wen_UNCONNECTED [1:0]),
        .\mi_c2h1_dat\.wpar (\NLW_udma_wrapper_mi_c2h1_dat\.wpar_UNCONNECTED [63:0]),
        .\mi_c2h2_dat\.radr (\NLW_udma_wrapper_mi_c2h2_dat\.radr_UNCONNECTED [8:0]),
        .\mi_c2h2_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h2_dat\.rdbe (1'b0),
        .\mi_c2h2_dat\.ren (\NLW_udma_wrapper_mi_c2h2_dat\.ren_UNCONNECTED ),
        .\mi_c2h2_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h2_dat\.rsbe (1'b0),
        .\mi_c2h2_dat\.wadr (\NLW_udma_wrapper_mi_c2h2_dat\.wadr_UNCONNECTED [8:0]),
        .\mi_c2h2_dat\.wdat (\NLW_udma_wrapper_mi_c2h2_dat\.wdat_UNCONNECTED [511:0]),
        .\mi_c2h2_dat\.wen (\NLW_udma_wrapper_mi_c2h2_dat\.wen_UNCONNECTED [1:0]),
        .\mi_c2h2_dat\.wpar (\NLW_udma_wrapper_mi_c2h2_dat\.wpar_UNCONNECTED [63:0]),
        .\mi_c2h3_dat\.radr (\NLW_udma_wrapper_mi_c2h3_dat\.radr_UNCONNECTED [8:0]),
        .\mi_c2h3_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h3_dat\.rdbe (1'b0),
        .\mi_c2h3_dat\.ren (\NLW_udma_wrapper_mi_c2h3_dat\.ren_UNCONNECTED ),
        .\mi_c2h3_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h3_dat\.rsbe (1'b0),
        .\mi_c2h3_dat\.wadr (\NLW_udma_wrapper_mi_c2h3_dat\.wadr_UNCONNECTED [8:0]),
        .\mi_c2h3_dat\.wdat (\NLW_udma_wrapper_mi_c2h3_dat\.wdat_UNCONNECTED [511:0]),
        .\mi_c2h3_dat\.wen (\NLW_udma_wrapper_mi_c2h3_dat\.wen_UNCONNECTED [1:0]),
        .\mi_c2h3_dat\.wpar (\NLW_udma_wrapper_mi_c2h3_dat\.wpar_UNCONNECTED [63:0]),
        .\mi_c2h_axi_dsc_cpld\.radr (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.radr_UNCONNECTED [9:0]),
        .\mi_c2h_axi_dsc_cpld\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpld\.rdbe (1'b0),
        .\mi_c2h_axi_dsc_cpld\.ren (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.ren_UNCONNECTED ),
        .\mi_c2h_axi_dsc_cpld\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpld\.rsbe (1'b0),
        .\mi_c2h_axi_dsc_cpld\.wadr (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.wadr_UNCONNECTED [9:0]),
        .\mi_c2h_axi_dsc_cpld\.wdat (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.wdat_UNCONNECTED [511:0]),
        .\mi_c2h_axi_dsc_cpld\.wen (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.wen_UNCONNECTED [7:0]),
        .\mi_c2h_axi_dsc_cpld\.wpar (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpld\.wpar_UNCONNECTED [63:0]),
        .\mi_c2h_axi_dsc_cpli\.radr (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.radr_UNCONNECTED [9:0]),
        .\mi_c2h_axi_dsc_cpli\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpli\.rdbe (1'b0),
        .\mi_c2h_axi_dsc_cpli\.ren (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.ren_UNCONNECTED ),
        .\mi_c2h_axi_dsc_cpli\.rpar ({1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_axi_dsc_cpli\.rsbe (1'b0),
        .\mi_c2h_axi_dsc_cpli\.wadr (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.wadr_UNCONNECTED [9:0]),
        .\mi_c2h_axi_dsc_cpli\.wdat (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.wdat_UNCONNECTED [79:0]),
        .\mi_c2h_axi_dsc_cpli\.wen (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.wen_UNCONNECTED [7:0]),
        .\mi_c2h_axi_dsc_cpli\.wpar (\NLW_udma_wrapper_mi_c2h_axi_dsc_cpli\.wpar_UNCONNECTED [3:0]),
        .\mi_c2h_pcie_dsc_cpld\.radr ({\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.radr_UNCONNECTED [9],\mi_c2h_pcie_dsc_cpld\.radr }),
        .\mi_c2h_pcie_dsc_cpld\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_c2h_pcie_dsc_cpld\.rdat }),
        .\mi_c2h_pcie_dsc_cpld\.rdbe (1'b0),
        .\mi_c2h_pcie_dsc_cpld\.ren (\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.ren_UNCONNECTED ),
        .\mi_c2h_pcie_dsc_cpld\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_pcie_dsc_cpld\.rsbe (1'b0),
        .\mi_c2h_pcie_dsc_cpld\.wadr ({\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.wadr_UNCONNECTED [9],\mi_c2h_pcie_dsc_cpld\.wadr }),
        .\mi_c2h_pcie_dsc_cpld\.wdat ({\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.wdat_UNCONNECTED [511:64],\mi_c2h_pcie_dsc_cpld\.wdat }),
        .\mi_c2h_pcie_dsc_cpld\.wen ({\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.wen_UNCONNECTED [7:1],\mi_c2h_pcie_dsc_cpld\.wen }),
        .\mi_c2h_pcie_dsc_cpld\.wpar (\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpld\.wpar_UNCONNECTED [63:0]),
        .\mi_c2h_pcie_dsc_cpli\.radr (\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.radr_UNCONNECTED [9:0]),
        .\mi_c2h_pcie_dsc_cpli\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_pcie_dsc_cpli\.rdbe (1'b0),
        .\mi_c2h_pcie_dsc_cpli\.ren (\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.ren_UNCONNECTED ),
        .\mi_c2h_pcie_dsc_cpli\.rpar ({1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_pcie_dsc_cpli\.rsbe (1'b0),
        .\mi_c2h_pcie_dsc_cpli\.wadr (\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.wadr_UNCONNECTED [9:0]),
        .\mi_c2h_pcie_dsc_cpli\.wdat (\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.wdat_UNCONNECTED [79:0]),
        .\mi_c2h_pcie_dsc_cpli\.wen (\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.wen_UNCONNECTED [7:0]),
        .\mi_c2h_pcie_dsc_cpli\.wpar (\NLW_udma_wrapper_mi_c2h_pcie_dsc_cpli\.wpar_UNCONNECTED [3:0]),
        .\mi_c2h_rd_brg_dat\.radr (\NLW_udma_wrapper_mi_c2h_rd_brg_dat\.radr_UNCONNECTED [9:0]),
        .\mi_c2h_rd_brg_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_rd_brg_dat\.rdbe (1'b0),
        .\mi_c2h_rd_brg_dat\.ren (\NLW_udma_wrapper_mi_c2h_rd_brg_dat\.ren_UNCONNECTED ),
        .\mi_c2h_rd_brg_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_rd_brg_dat\.rsbe (1'b0),
        .\mi_c2h_rd_brg_dat\.wadr (\NLW_udma_wrapper_mi_c2h_rd_brg_dat\.wadr_UNCONNECTED [9:0]),
        .\mi_c2h_rd_brg_dat\.wdat (\NLW_udma_wrapper_mi_c2h_rd_brg_dat\.wdat_UNCONNECTED [511:0]),
        .\mi_c2h_rd_brg_dat\.wen (\NLW_udma_wrapper_mi_c2h_rd_brg_dat\.wen_UNCONNECTED [1:0]),
        .\mi_c2h_rd_brg_dat\.wpar (\NLW_udma_wrapper_mi_c2h_rd_brg_dat\.wpar_UNCONNECTED [63:0]),
        .\mi_c2h_wr_brg_dat\.radr (\NLW_udma_wrapper_mi_c2h_wr_brg_dat\.radr_UNCONNECTED [8:0]),
        .\mi_c2h_wr_brg_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_wr_brg_dat\.rdbe (1'b0),
        .\mi_c2h_wr_brg_dat\.ren (\NLW_udma_wrapper_mi_c2h_wr_brg_dat\.ren_UNCONNECTED ),
        .\mi_c2h_wr_brg_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_c2h_wr_brg_dat\.rsbe (1'b0),
        .\mi_c2h_wr_brg_dat\.wadr (\NLW_udma_wrapper_mi_c2h_wr_brg_dat\.wadr_UNCONNECTED [8:0]),
        .\mi_c2h_wr_brg_dat\.wdat (\NLW_udma_wrapper_mi_c2h_wr_brg_dat\.wdat_UNCONNECTED [511:0]),
        .\mi_c2h_wr_brg_dat\.wen (\NLW_udma_wrapper_mi_c2h_wr_brg_dat\.wen_UNCONNECTED [1:0]),
        .\mi_c2h_wr_brg_dat\.wpar (\NLW_udma_wrapper_mi_c2h_wr_brg_dat\.wpar_UNCONNECTED [63:0]),
        .\mi_dsc_crd_rcv\.radr (\NLW_udma_wrapper_mi_dsc_crd_rcv\.radr_UNCONNECTED [11:0]),
        .\mi_dsc_crd_rcv\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_dsc_crd_rcv\.rdbe (1'b0),
        .\mi_dsc_crd_rcv\.ren (\NLW_udma_wrapper_mi_dsc_crd_rcv\.ren_UNCONNECTED ),
        .\mi_dsc_crd_rcv\.rpar ({1'b0,1'b0}),
        .\mi_dsc_crd_rcv\.rsbe (1'b0),
        .\mi_dsc_crd_rcv\.wadr (\NLW_udma_wrapper_mi_dsc_crd_rcv\.wadr_UNCONNECTED [11:0]),
        .\mi_dsc_crd_rcv\.wdat (\NLW_udma_wrapper_mi_dsc_crd_rcv\.wdat_UNCONNECTED [15:0]),
        .\mi_dsc_crd_rcv\.wen (\NLW_udma_wrapper_mi_dsc_crd_rcv\.wen_UNCONNECTED ),
        .\mi_dsc_crd_rcv\.wpar (\NLW_udma_wrapper_mi_dsc_crd_rcv\.wpar_UNCONNECTED [1:0]),
        .\mi_h2c0_dat\.radr (\mi_h2c0_dat\.radr ),
        .\mi_h2c0_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_h2c0_dat\.rdat }),
        .\mi_h2c0_dat\.rdbe (1'b0),
        .\mi_h2c0_dat\.ren (\NLW_udma_wrapper_mi_h2c0_dat\.ren_UNCONNECTED ),
        .\mi_h2c0_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c0_dat\.rsbe (1'b0),
        .\mi_h2c0_dat\.wadr (\mi_h2c0_dat\.wadr ),
        .\mi_h2c0_dat\.wdat ({\NLW_udma_wrapper_mi_h2c0_dat\.wdat_UNCONNECTED [511:64],\mi_h2c0_dat\.wdat }),
        .\mi_h2c0_dat\.wen (\mi_h2c0_dat\.wen ),
        .\mi_h2c0_dat\.wpar ({\NLW_udma_wrapper_mi_h2c0_dat\.wpar_UNCONNECTED [63:8],\mi_h2c0_dat\.wpar }),
        .\mi_h2c1_dat\.radr (\NLW_udma_wrapper_mi_h2c1_dat\.radr_UNCONNECTED [8:0]),
        .\mi_h2c1_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c1_dat\.rdbe (1'b0),
        .\mi_h2c1_dat\.ren (\NLW_udma_wrapper_mi_h2c1_dat\.ren_UNCONNECTED ),
        .\mi_h2c1_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c1_dat\.rsbe (1'b0),
        .\mi_h2c1_dat\.wadr (\NLW_udma_wrapper_mi_h2c1_dat\.wadr_UNCONNECTED [8:0]),
        .\mi_h2c1_dat\.wdat (\NLW_udma_wrapper_mi_h2c1_dat\.wdat_UNCONNECTED [511:0]),
        .\mi_h2c1_dat\.wen (\NLW_udma_wrapper_mi_h2c1_dat\.wen_UNCONNECTED [1:0]),
        .\mi_h2c1_dat\.wpar (\NLW_udma_wrapper_mi_h2c1_dat\.wpar_UNCONNECTED [63:0]),
        .\mi_h2c2_dat\.radr (\NLW_udma_wrapper_mi_h2c2_dat\.radr_UNCONNECTED [8:0]),
        .\mi_h2c2_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c2_dat\.rdbe (1'b0),
        .\mi_h2c2_dat\.ren (\NLW_udma_wrapper_mi_h2c2_dat\.ren_UNCONNECTED ),
        .\mi_h2c2_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c2_dat\.rsbe (1'b0),
        .\mi_h2c2_dat\.wadr (\NLW_udma_wrapper_mi_h2c2_dat\.wadr_UNCONNECTED [8:0]),
        .\mi_h2c2_dat\.wdat (\NLW_udma_wrapper_mi_h2c2_dat\.wdat_UNCONNECTED [511:0]),
        .\mi_h2c2_dat\.wen (\NLW_udma_wrapper_mi_h2c2_dat\.wen_UNCONNECTED [1:0]),
        .\mi_h2c2_dat\.wpar (\NLW_udma_wrapper_mi_h2c2_dat\.wpar_UNCONNECTED [63:0]),
        .\mi_h2c3_dat\.radr (\NLW_udma_wrapper_mi_h2c3_dat\.radr_UNCONNECTED [8:0]),
        .\mi_h2c3_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c3_dat\.rdbe (1'b0),
        .\mi_h2c3_dat\.ren (\NLW_udma_wrapper_mi_h2c3_dat\.ren_UNCONNECTED ),
        .\mi_h2c3_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c3_dat\.rsbe (1'b0),
        .\mi_h2c3_dat\.wadr (\NLW_udma_wrapper_mi_h2c3_dat\.wadr_UNCONNECTED [8:0]),
        .\mi_h2c3_dat\.wdat (\NLW_udma_wrapper_mi_h2c3_dat\.wdat_UNCONNECTED [511:0]),
        .\mi_h2c3_dat\.wen (\NLW_udma_wrapper_mi_h2c3_dat\.wen_UNCONNECTED [1:0]),
        .\mi_h2c3_dat\.wpar (\NLW_udma_wrapper_mi_h2c3_dat\.wpar_UNCONNECTED [63:0]),
        .\mi_h2c_axi_dsc_cpld\.radr (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.radr_UNCONNECTED [9:0]),
        .\mi_h2c_axi_dsc_cpld\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpld\.rdbe (1'b0),
        .\mi_h2c_axi_dsc_cpld\.ren (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.ren_UNCONNECTED ),
        .\mi_h2c_axi_dsc_cpld\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpld\.rsbe (1'b0),
        .\mi_h2c_axi_dsc_cpld\.wadr (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.wadr_UNCONNECTED [9:0]),
        .\mi_h2c_axi_dsc_cpld\.wdat (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.wdat_UNCONNECTED [511:0]),
        .\mi_h2c_axi_dsc_cpld\.wen (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.wen_UNCONNECTED [7:0]),
        .\mi_h2c_axi_dsc_cpld\.wpar (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpld\.wpar_UNCONNECTED [63:0]),
        .\mi_h2c_axi_dsc_cpli\.radr (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.radr_UNCONNECTED [9:0]),
        .\mi_h2c_axi_dsc_cpli\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpli\.rdbe (1'b0),
        .\mi_h2c_axi_dsc_cpli\.ren (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.ren_UNCONNECTED ),
        .\mi_h2c_axi_dsc_cpli\.rpar ({1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_axi_dsc_cpli\.rsbe (1'b0),
        .\mi_h2c_axi_dsc_cpli\.wadr (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.wadr_UNCONNECTED [9:0]),
        .\mi_h2c_axi_dsc_cpli\.wdat (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.wdat_UNCONNECTED [79:0]),
        .\mi_h2c_axi_dsc_cpli\.wen (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.wen_UNCONNECTED [7:0]),
        .\mi_h2c_axi_dsc_cpli\.wpar (\NLW_udma_wrapper_mi_h2c_axi_dsc_cpli\.wpar_UNCONNECTED [3:0]),
        .\mi_h2c_pcie_dsc_cpld\.radr (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.radr_UNCONNECTED [9:0]),
        .\mi_h2c_pcie_dsc_cpld\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpld\.rdbe (1'b0),
        .\mi_h2c_pcie_dsc_cpld\.ren (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.ren_UNCONNECTED ),
        .\mi_h2c_pcie_dsc_cpld\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpld\.rsbe (1'b0),
        .\mi_h2c_pcie_dsc_cpld\.wadr (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.wadr_UNCONNECTED [9:0]),
        .\mi_h2c_pcie_dsc_cpld\.wdat (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.wdat_UNCONNECTED [511:0]),
        .\mi_h2c_pcie_dsc_cpld\.wen (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.wen_UNCONNECTED [7:0]),
        .\mi_h2c_pcie_dsc_cpld\.wpar (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpld\.wpar_UNCONNECTED [63:0]),
        .\mi_h2c_pcie_dsc_cpli\.radr (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.radr_UNCONNECTED [9:0]),
        .\mi_h2c_pcie_dsc_cpli\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpli\.rdbe (1'b0),
        .\mi_h2c_pcie_dsc_cpli\.ren (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.ren_UNCONNECTED ),
        .\mi_h2c_pcie_dsc_cpli\.rpar ({1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_pcie_dsc_cpli\.rsbe (1'b0),
        .\mi_h2c_pcie_dsc_cpli\.wadr (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.wadr_UNCONNECTED [9:0]),
        .\mi_h2c_pcie_dsc_cpli\.wdat (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.wdat_UNCONNECTED [79:0]),
        .\mi_h2c_pcie_dsc_cpli\.wen (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.wen_UNCONNECTED [7:0]),
        .\mi_h2c_pcie_dsc_cpli\.wpar (\NLW_udma_wrapper_mi_h2c_pcie_dsc_cpli\.wpar_UNCONNECTED [3:0]),
        .\mi_h2c_rd_brg_dat\.radr (\mi_h2c_rd_brg_dat\.radr ),
        .\mi_h2c_rd_brg_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_h2c_rd_brg_dat\.rdat }),
        .\mi_h2c_rd_brg_dat\.rdbe (1'b0),
        .\mi_h2c_rd_brg_dat\.ren (\NLW_udma_wrapper_mi_h2c_rd_brg_dat\.ren_UNCONNECTED ),
        .\mi_h2c_rd_brg_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_h2c_rd_brg_dat\.rsbe (1'b0),
        .\mi_h2c_rd_brg_dat\.wadr (\mi_h2c_rd_brg_dat\.wadr ),
        .\mi_h2c_rd_brg_dat\.wdat ({\NLW_udma_wrapper_mi_h2c_rd_brg_dat\.wdat_UNCONNECTED [511:64],\mi_h2c_rd_brg_dat\.wdat }),
        .\mi_h2c_rd_brg_dat\.wen ({\NLW_udma_wrapper_mi_h2c_rd_brg_dat\.wen_UNCONNECTED [1],\mi_h2c_rd_brg_dat\.wen }),
        .\mi_h2c_rd_brg_dat\.wpar (\NLW_udma_wrapper_mi_h2c_rd_brg_dat\.wpar_UNCONNECTED [63:0]),
        .\mi_h2c_wr_brg_dat\.radr ({\NLW_udma_wrapper_mi_h2c_wr_brg_dat\.radr_UNCONNECTED [10:9],\mi_h2c_wr_brg_dat\.radr }),
        .\mi_h2c_wr_brg_dat\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_h2c_wr_brg_dat\.rdat }),
        .\mi_h2c_wr_brg_dat\.rdbe (1'b0),
        .\mi_h2c_wr_brg_dat\.ren (\NLW_udma_wrapper_mi_h2c_wr_brg_dat\.ren_UNCONNECTED ),
        .\mi_h2c_wr_brg_dat\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\mi_h2c_wr_brg_dat\.rpar }),
        .\mi_h2c_wr_brg_dat\.rsbe (1'b0),
        .\mi_h2c_wr_brg_dat\.wadr ({\NLW_udma_wrapper_mi_h2c_wr_brg_dat\.wadr_UNCONNECTED [10:9],\mi_h2c_wr_brg_dat\.wadr }),
        .\mi_h2c_wr_brg_dat\.wdat ({\NLW_udma_wrapper_mi_h2c_wr_brg_dat\.wdat_UNCONNECTED [511:64],\mi_h2c_wr_brg_dat\.wdat }),
        .\mi_h2c_wr_brg_dat\.wen ({\NLW_udma_wrapper_mi_h2c_wr_brg_dat\.wen_UNCONNECTED [1],\mi_h2c_wr_brg_dat\.wen }),
        .\mi_h2c_wr_brg_dat\.wpar (\NLW_udma_wrapper_mi_h2c_wr_brg_dat\.wpar_UNCONNECTED [63:0]),
        .\mi_hw_ctxt\.radr (\NLW_udma_wrapper_mi_hw_ctxt\.radr_UNCONNECTED [11:0]),
        .\mi_hw_ctxt\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_hw_ctxt\.rdbe (1'b0),
        .\mi_hw_ctxt\.ren (\NLW_udma_wrapper_mi_hw_ctxt\.ren_UNCONNECTED ),
        .\mi_hw_ctxt\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_hw_ctxt\.rsbe (1'b0),
        .\mi_hw_ctxt\.wadr (\NLW_udma_wrapper_mi_hw_ctxt\.wadr_UNCONNECTED [11:0]),
        .\mi_hw_ctxt\.wdat (\NLW_udma_wrapper_mi_hw_ctxt\.wdat_UNCONNECTED [31:0]),
        .\mi_hw_ctxt\.wen (\NLW_udma_wrapper_mi_hw_ctxt\.wen_UNCONNECTED ),
        .\mi_hw_ctxt\.wpar (\NLW_udma_wrapper_mi_hw_ctxt\.wpar_UNCONNECTED [7:0]),
        .\mi_sw_ctxt\.radr (\NLW_udma_wrapper_mi_sw_ctxt\.radr_UNCONNECTED [11:0]),
        .\mi_sw_ctxt\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_sw_ctxt\.rdbe (1'b0),
        .\mi_sw_ctxt\.ren (\NLW_udma_wrapper_mi_sw_ctxt\.ren_UNCONNECTED ),
        .\mi_sw_ctxt\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_sw_ctxt\.rsbe (1'b0),
        .\mi_sw_ctxt\.wadr (\NLW_udma_wrapper_mi_sw_ctxt\.wadr_UNCONNECTED [11:0]),
        .\mi_sw_ctxt\.wdat (\NLW_udma_wrapper_mi_sw_ctxt\.wdat_UNCONNECTED [127:0]),
        .\mi_sw_ctxt\.wen (\NLW_udma_wrapper_mi_sw_ctxt\.wen_UNCONNECTED [3:0]),
        .\mi_sw_ctxt\.wpar (\NLW_udma_wrapper_mi_sw_ctxt\.wpar_UNCONNECTED [7:0]),
        .\mi_wb_base_ctxt\.radr (\NLW_udma_wrapper_mi_wb_base_ctxt\.radr_UNCONNECTED [11:0]),
        .\mi_wb_base_ctxt\.rdat ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_wb_base_ctxt\.rdbe (1'b0),
        .\mi_wb_base_ctxt\.ren (\NLW_udma_wrapper_mi_wb_base_ctxt\.ren_UNCONNECTED ),
        .\mi_wb_base_ctxt\.rpar ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\mi_wb_base_ctxt\.rsbe (1'b0),
        .\mi_wb_base_ctxt\.wadr (\NLW_udma_wrapper_mi_wb_base_ctxt\.wadr_UNCONNECTED [11:0]),
        .\mi_wb_base_ctxt\.wdat (\NLW_udma_wrapper_mi_wb_base_ctxt\.wdat_UNCONNECTED [63:0]),
        .\mi_wb_base_ctxt\.wen (\NLW_udma_wrapper_mi_wb_base_ctxt\.wen_UNCONNECTED [1:0]),
        .\mi_wb_base_ctxt\.wpar (\NLW_udma_wrapper_mi_wb_base_ctxt\.wpar_UNCONNECTED [7:0]),
        .\pcie_dma_gic\.interrupt (\NLW_udma_wrapper_pcie_dma_gic\.interrupt_UNCONNECTED [6:0]),
        .\pcie_dma_in\.cfg_current_speed ({1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_err_cor_out (1'b0),
        .\pcie_dma_in\.cfg_err_fatal_out (1'b0),
        .\pcie_dma_in\.cfg_err_nonfatal_out (1'b0),
        .\pcie_dma_in\.cfg_ext_function_number ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_ext_read_received (1'b0),
        .\pcie_dma_in\.cfg_ext_register_number ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_ext_write_byte_enable ({1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_ext_write_data ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_ext_write_received (1'b0),
        .\pcie_dma_in\.cfg_fc_nph (\pcie_dma_in\.cfg_fc_nph ),
        .\pcie_dma_in\.cfg_flr_in_process ({1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_function_status ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_hot_reset_out (1'b0),
        .\pcie_dma_in\.cfg_interrupt_msi_enable (msi_enable),
        .\pcie_dma_in\.cfg_interrupt_msi_fail (1'b0),
        .\pcie_dma_in\.cfg_interrupt_msi_mask_update (1'b0),
        .\pcie_dma_in\.cfg_interrupt_msi_sent (xdma_0_pcie2_to_pcie3_wrapper_i_n_167),
        .\pcie_dma_in\.cfg_interrupt_msix_enable ({1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_interrupt_msix_fail (1'b0),
        .\pcie_dma_in\.cfg_interrupt_msix_mask ({1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_interrupt_msix_sent (1'b0),
        .\pcie_dma_in\.cfg_interrupt_msix_vf_enable ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_interrupt_msix_vf_mask ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_interrupt_sent (\pcie_dma_in\.cfg_interrupt_sent ),
        .\pcie_dma_in\.cfg_local_error (1'b0),
        .\pcie_dma_in\.cfg_ltssm_state ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_max_payload ({xdma_0_pcie2_to_pcie3_wrapper_i_n_136,xdma_0_pcie2_to_pcie3_wrapper_i_n_137,xdma_0_pcie2_to_pcie3_wrapper_i_n_138}),
        .\pcie_dma_in\.cfg_max_read_req ({xdma_0_pcie2_to_pcie3_wrapper_i_n_133,xdma_0_pcie2_to_pcie3_wrapper_i_n_134,xdma_0_pcie2_to_pcie3_wrapper_i_n_135}),
        .\pcie_dma_in\.cfg_mgmt_read_data ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_mgmt_read_write_done (1'b0),
        .\pcie_dma_in\.cfg_msg_received (1'b0),
        .\pcie_dma_in\.cfg_msg_received_data ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_msg_received_type ({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_msg_transmit_done (1'b0),
        .\pcie_dma_in\.cfg_negotiated_width ({1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_per_func_status_data ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.cfg_per_function_update_done (1'b0),
        .\pcie_dma_in\.cfg_phy_link_down (\pcie_dma_in\.cfg_phy_link_down ),
        .\pcie_dma_in\.cfg_phy_link_status ({1'b0,1'b0}),
        .\pcie_dma_in\.cfg_pl_status_change (1'b0),
        .\pcie_dma_in\.cfg_vf_flr_in_process ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.pcie_cq_np_req_count ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.pcie_rq_seq_num0 (\pcie_dma_in\.pcie_rq_seq_num0 ),
        .\pcie_dma_in\.pcie_rq_seq_num1 ({1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_in\.pcie_rq_seq_num_vld0 (\pcie_dma_in\.pcie_rq_seq_num_vld0 ),
        .\pcie_dma_in\.pcie_rq_seq_num_vld1 (1'b0),
        .\pcie_dma_in\.pcie_tfc_nph_av ({1'b0,1'b0,1'b0,1'b0}),
        .\pcie_dma_out\.cfg_config_space_enable (\NLW_udma_wrapper_pcie_dma_out\.cfg_config_space_enable_UNCONNECTED ),
        .\pcie_dma_out\.cfg_ds_bus_number (\NLW_udma_wrapper_pcie_dma_out\.cfg_ds_bus_number_UNCONNECTED [7:0]),
        .\pcie_dma_out\.cfg_ds_device_number (\NLW_udma_wrapper_pcie_dma_out\.cfg_ds_device_number_UNCONNECTED [4:0]),
        .\pcie_dma_out\.cfg_ds_function_number (\NLW_udma_wrapper_pcie_dma_out\.cfg_ds_function_number_UNCONNECTED [2:0]),
        .\pcie_dma_out\.cfg_ds_port_number (\NLW_udma_wrapper_pcie_dma_out\.cfg_ds_port_number_UNCONNECTED [7:0]),
        .\pcie_dma_out\.cfg_dsn (\NLW_udma_wrapper_pcie_dma_out\.cfg_dsn_UNCONNECTED [63:0]),
        .\pcie_dma_out\.cfg_err_cor_in (\NLW_udma_wrapper_pcie_dma_out\.cfg_err_cor_in_UNCONNECTED ),
        .\pcie_dma_out\.cfg_err_uncor_in (\NLW_udma_wrapper_pcie_dma_out\.cfg_err_uncor_in_UNCONNECTED ),
        .\pcie_dma_out\.cfg_ext_read_data (\NLW_udma_wrapper_pcie_dma_out\.cfg_ext_read_data_UNCONNECTED [31:0]),
        .\pcie_dma_out\.cfg_ext_read_data_valid (\NLW_udma_wrapper_pcie_dma_out\.cfg_ext_read_data_valid_UNCONNECTED ),
        .\pcie_dma_out\.cfg_fc_sel ({\NLW_udma_wrapper_pcie_dma_out\.cfg_fc_sel_UNCONNECTED [2:1],cfg_fc_sel}),
        .\pcie_dma_out\.cfg_flr_done (\NLW_udma_wrapper_pcie_dma_out\.cfg_flr_done_UNCONNECTED [3:0]),
        .\pcie_dma_out\.cfg_hot_reset_in (\NLW_udma_wrapper_pcie_dma_out\.cfg_hot_reset_in_UNCONNECTED ),
        .\pcie_dma_out\.cfg_interrupt_int ({\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_int_UNCONNECTED [3:1],cfg_interrupt_int}),
        .\pcie_dma_out\.cfg_interrupt_msi_attr (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_attr_UNCONNECTED [2:0]),
        .\pcie_dma_out\.cfg_interrupt_msi_function_number (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_function_number_UNCONNECTED [3:0]),
        .\pcie_dma_out\.cfg_interrupt_msi_int (cfg_interrupt_msi_int),
        .\pcie_dma_out\.cfg_interrupt_msi_pending_status (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_pending_status_UNCONNECTED [31:0]),
        .\pcie_dma_out\.cfg_interrupt_msi_pending_status_data_enable (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_pending_status_data_enable_UNCONNECTED ),
        .\pcie_dma_out\.cfg_interrupt_msi_pending_status_function_num (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_pending_status_function_num_UNCONNECTED [3:0]),
        .\pcie_dma_out\.cfg_interrupt_msi_tph_present (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_tph_present_UNCONNECTED ),
        .\pcie_dma_out\.cfg_interrupt_msi_tph_st_tag (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_tph_st_tag_UNCONNECTED [8:0]),
        .\pcie_dma_out\.cfg_interrupt_msi_tph_type (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msi_tph_type_UNCONNECTED [1:0]),
        .\pcie_dma_out\.cfg_interrupt_msix_address (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msix_address_UNCONNECTED [255:0]),
        .\pcie_dma_out\.cfg_interrupt_msix_data (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msix_data_UNCONNECTED [31:0]),
        .\pcie_dma_out\.cfg_interrupt_msix_int (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_msix_int_UNCONNECTED ),
        .\pcie_dma_out\.cfg_interrupt_pending (\NLW_udma_wrapper_pcie_dma_out\.cfg_interrupt_pending_UNCONNECTED [3:0]),
        .\pcie_dma_out\.cfg_link_training_enable (\NLW_udma_wrapper_pcie_dma_out\.cfg_link_training_enable_UNCONNECTED ),
        .\pcie_dma_out\.cfg_mgmt_addr (\NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_addr_UNCONNECTED [18:0]),
        .\pcie_dma_out\.cfg_mgmt_byte_enable (\NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_byte_enable_UNCONNECTED [3:0]),
        .\pcie_dma_out\.cfg_mgmt_function_number (\NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_function_number_UNCONNECTED [7:0]),
        .\pcie_dma_out\.cfg_mgmt_read (\NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_read_UNCONNECTED ),
        .\pcie_dma_out\.cfg_mgmt_type1_cfg_reg_access (\NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_type1_cfg_reg_access_UNCONNECTED ),
        .\pcie_dma_out\.cfg_mgmt_write (\NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_write_UNCONNECTED ),
        .\pcie_dma_out\.cfg_mgmt_write_data (\NLW_udma_wrapper_pcie_dma_out\.cfg_mgmt_write_data_UNCONNECTED [31:0]),
        .\pcie_dma_out\.cfg_msg_transmit (\NLW_udma_wrapper_pcie_dma_out\.cfg_msg_transmit_UNCONNECTED ),
        .\pcie_dma_out\.cfg_msg_transmit_data (\NLW_udma_wrapper_pcie_dma_out\.cfg_msg_transmit_data_UNCONNECTED [31:0]),
        .\pcie_dma_out\.cfg_msg_transmit_type (\NLW_udma_wrapper_pcie_dma_out\.cfg_msg_transmit_type_UNCONNECTED [2:0]),
        .\pcie_dma_out\.cfg_per_func_status_control (\NLW_udma_wrapper_pcie_dma_out\.cfg_per_func_status_control_UNCONNECTED [2:0]),
        .\pcie_dma_out\.cfg_per_function_logic_request (\NLW_udma_wrapper_pcie_dma_out\.cfg_per_function_logic_request_UNCONNECTED ),
        .\pcie_dma_out\.cfg_per_function_number (\NLW_udma_wrapper_pcie_dma_out\.cfg_per_function_number_UNCONNECTED [6:0]),
        .\pcie_dma_out\.cfg_per_function_output_request (\NLW_udma_wrapper_pcie_dma_out\.cfg_per_function_output_request_UNCONNECTED ),
        .\pcie_dma_out\.cfg_vf_flr_done (\NLW_udma_wrapper_pcie_dma_out\.cfg_vf_flr_done_UNCONNECTED ),
        .\pcie_dma_out\.cfg_vf_flr_func_num (\NLW_udma_wrapper_pcie_dma_out\.cfg_vf_flr_func_num_UNCONNECTED [7:0]),
        .\pcie_dma_out\.pcie_cq_np_req ({\NLW_udma_wrapper_pcie_dma_out\.pcie_cq_np_req_UNCONNECTED [1],\pcie_dma_out\.pcie_cq_np_req }),
        .pf1_lite_ext({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rbar_bar_size({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rbar_function_number({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rbar_write_enable_bar0(1'b0),
        .rbar_write_enable_bar1(1'b0),
        .rbar_write_enable_bar2(1'b0),
        .rbar_write_enable_bar3(1'b0),
        .rbar_write_enable_bar4(1'b0),
        .rbar_write_enable_bar5(1'b0),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_udma_wrapper_s_axi_arready_UNCONNECTED),
        .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_udma_wrapper_s_axi_awready_UNCONNECTED),
        .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_udma_wrapper_s_axi_bid_UNCONNECTED[3:0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_udma_wrapper_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_bvalid(NLW_udma_wrapper_s_axi_bvalid_UNCONNECTED),
        .s_axi_rdata(NLW_udma_wrapper_s_axi_rdata_UNCONNECTED[63:0]),
        .s_axi_rdataeccparity(NLW_udma_wrapper_s_axi_rdataeccparity_UNCONNECTED[7:0]),
        .s_axi_rid(NLW_udma_wrapper_s_axi_rid_UNCONNECTED[3:0]),
        .s_axi_rlast(NLW_udma_wrapper_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_udma_wrapper_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_rvalid(NLW_udma_wrapper_s_axi_rvalid_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wdataeccparity({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_udma_wrapper_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wvalid(1'b0),
        .s_axil_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,n_0_319,n_0_320,n_0_321,n_0_322,n_0_323,n_0_324,n_0_325,n_0_326,n_0_327,n_0_328,n_0_329,n_0_330,n_0_331,n_0_332,n_0_333,n_0_334,n_0_335,n_0_336}),
        .s_axil_arprot({1'b0,1'b0,1'b0}),
        .s_axil_arready(udma_wrapper_n_12723),
        .s_axil_arvalid(n_0_337),
        .s_axil_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,n_0_248,n_0_249,n_0_250,n_0_251,n_0_252,n_0_253,n_0_254,n_0_255,n_0_256,n_0_257,n_0_258,n_0_259,n_0_260,n_0_261,n_0_262,n_0_263,n_0_264,n_0_265}),
        .s_axil_awprot({1'b0,1'b0,1'b0}),
        .s_axil_awready(udma_wrapper_n_12718),
        .s_axil_awvalid(n_0_266),
        .s_axil_bready(n_0_304),
        .s_axil_bresp(NLW_udma_wrapper_s_axil_bresp_UNCONNECTED[1:0]),
        .s_axil_bvalid(udma_wrapper_n_12720),
        .s_axil_rdata({udma_wrapper_n_12724,udma_wrapper_n_12725,udma_wrapper_n_12726,udma_wrapper_n_12727,udma_wrapper_n_12728,udma_wrapper_n_12729,udma_wrapper_n_12730,udma_wrapper_n_12731,udma_wrapper_n_12732,udma_wrapper_n_12733,udma_wrapper_n_12734,udma_wrapper_n_12735,udma_wrapper_n_12736,udma_wrapper_n_12737,udma_wrapper_n_12738,udma_wrapper_n_12739,udma_wrapper_n_12740,udma_wrapper_n_12741,udma_wrapper_n_12742,udma_wrapper_n_12743,udma_wrapper_n_12744,udma_wrapper_n_12745,udma_wrapper_n_12746,udma_wrapper_n_12747,udma_wrapper_n_12748,udma_wrapper_n_12749,udma_wrapper_n_12750,udma_wrapper_n_12751,udma_wrapper_n_12752,udma_wrapper_n_12753,udma_wrapper_n_12754,udma_wrapper_n_12755}),
        .s_axil_rready(n_0_338),
        .s_axil_rresp(NLW_udma_wrapper_s_axil_rresp_UNCONNECTED[1:0]),
        .s_axil_rvalid(udma_wrapper_n_12758),
        .s_axil_wdata({n_0_267,n_0_268,n_0_269,n_0_270,n_0_271,n_0_272,n_0_273,n_0_274,n_0_275,n_0_276,n_0_277,n_0_278,n_0_279,n_0_280,n_0_281,n_0_282,n_0_283,n_0_284,n_0_285,n_0_286,n_0_287,n_0_288,n_0_289,n_0_290,n_0_291,n_0_292,n_0_293,n_0_294,n_0_295,n_0_296,n_0_297,n_0_298}),
        .s_axil_wready(udma_wrapper_n_12719),
        .s_axil_wstrb({n_0_299,n_0_300,n_0_301,n_0_302}),
        .s_axil_wvalid(n_0_303),
        .s_axis_c2h_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tkeep({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tlast(1'b0),
        .s_axis_c2h_tparity({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tready(NLW_udma_wrapper_s_axis_c2h_tready_UNCONNECTED[0]),
        .s_axis_c2h_tuser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_c2h_tvalid(1'b0),
        .\s_axis_cq\.tdata ({xdma_0_pcie2_to_pcie3_wrapper_i_n_241,xdma_0_pcie2_to_pcie3_wrapper_i_n_242,xdma_0_pcie2_to_pcie3_wrapper_i_n_243,xdma_0_pcie2_to_pcie3_wrapper_i_n_244,xdma_0_pcie2_to_pcie3_wrapper_i_n_245,xdma_0_pcie2_to_pcie3_wrapper_i_n_246,xdma_0_pcie2_to_pcie3_wrapper_i_n_247,xdma_0_pcie2_to_pcie3_wrapper_i_n_248,xdma_0_pcie2_to_pcie3_wrapper_i_n_249,xdma_0_pcie2_to_pcie3_wrapper_i_n_250,xdma_0_pcie2_to_pcie3_wrapper_i_n_251,xdma_0_pcie2_to_pcie3_wrapper_i_n_252,xdma_0_pcie2_to_pcie3_wrapper_i_n_253,xdma_0_pcie2_to_pcie3_wrapper_i_n_254,xdma_0_pcie2_to_pcie3_wrapper_i_n_255,xdma_0_pcie2_to_pcie3_wrapper_i_n_256,xdma_0_pcie2_to_pcie3_wrapper_i_n_257,xdma_0_pcie2_to_pcie3_wrapper_i_n_258,xdma_0_pcie2_to_pcie3_wrapper_i_n_259,xdma_0_pcie2_to_pcie3_wrapper_i_n_260,xdma_0_pcie2_to_pcie3_wrapper_i_n_261,xdma_0_pcie2_to_pcie3_wrapper_i_n_262,xdma_0_pcie2_to_pcie3_wrapper_i_n_263,xdma_0_pcie2_to_pcie3_wrapper_i_n_264,xdma_0_pcie2_to_pcie3_wrapper_i_n_265,xdma_0_pcie2_to_pcie3_wrapper_i_n_266,xdma_0_pcie2_to_pcie3_wrapper_i_n_267,xdma_0_pcie2_to_pcie3_wrapper_i_n_268,xdma_0_pcie2_to_pcie3_wrapper_i_n_269,xdma_0_pcie2_to_pcie3_wrapper_i_n_270,xdma_0_pcie2_to_pcie3_wrapper_i_n_271,xdma_0_pcie2_to_pcie3_wrapper_i_n_272,xdma_0_pcie2_to_pcie3_wrapper_i_n_273,xdma_0_pcie2_to_pcie3_wrapper_i_n_274,xdma_0_pcie2_to_pcie3_wrapper_i_n_275,xdma_0_pcie2_to_pcie3_wrapper_i_n_276,xdma_0_pcie2_to_pcie3_wrapper_i_n_277,xdma_0_pcie2_to_pcie3_wrapper_i_n_278,xdma_0_pcie2_to_pcie3_wrapper_i_n_279,xdma_0_pcie2_to_pcie3_wrapper_i_n_280,xdma_0_pcie2_to_pcie3_wrapper_i_n_281,xdma_0_pcie2_to_pcie3_wrapper_i_n_282,xdma_0_pcie2_to_pcie3_wrapper_i_n_283,xdma_0_pcie2_to_pcie3_wrapper_i_n_284,xdma_0_pcie2_to_pcie3_wrapper_i_n_285,xdma_0_pcie2_to_pcie3_wrapper_i_n_286,xdma_0_pcie2_to_pcie3_wrapper_i_n_287,xdma_0_pcie2_to_pcie3_wrapper_i_n_288,xdma_0_pcie2_to_pcie3_wrapper_i_n_289,xdma_0_pcie2_to_pcie3_wrapper_i_n_290,xdma_0_pcie2_to_pcie3_wrapper_i_n_291,xdma_0_pcie2_to_pcie3_wrapper_i_n_292,xdma_0_pcie2_to_pcie3_wrapper_i_n_293,xdma_0_pcie2_to_pcie3_wrapper_i_n_294,xdma_0_pcie2_to_pcie3_wrapper_i_n_295,xdma_0_pcie2_to_pcie3_wrapper_i_n_296,xdma_0_pcie2_to_pcie3_wrapper_i_n_297,xdma_0_pcie2_to_pcie3_wrapper_i_n_298,xdma_0_pcie2_to_pcie3_wrapper_i_n_299,xdma_0_pcie2_to_pcie3_wrapper_i_n_300,xdma_0_pcie2_to_pcie3_wrapper_i_n_301,xdma_0_pcie2_to_pcie3_wrapper_i_n_302,xdma_0_pcie2_to_pcie3_wrapper_i_n_303,xdma_0_pcie2_to_pcie3_wrapper_i_n_304}),
        .\s_axis_cq\.tkeep ({1'b0,1'b0}),
        .\s_axis_cq\.tlast (xdma_0_pcie2_to_pcie3_wrapper_i_n_311),
        .\s_axis_cq\.tready ({\NLW_udma_wrapper_s_axis_cq\.tready_UNCONNECTED [21:1],udma_wrapper_n_11002}),
        .\s_axis_cq\.tuser ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,xdma_0_pcie2_to_pcie3_wrapper_i_n_305,1'b0,1'b0,1'b0,xdma_0_pcie2_to_pcie3_wrapper_i_n_306,xdma_0_pcie2_to_pcie3_wrapper_i_n_307,xdma_0_pcie2_to_pcie3_wrapper_i_n_308,xdma_0_pcie2_to_pcie3_wrapper_i_n_309}),
        .\s_axis_cq\.tvalid (xdma_0_pcie2_to_pcie3_wrapper_i_n_310),
        .\s_axis_rc\.tdata ({xdma_0_pcie2_to_pcie3_wrapper_i_n_177,xdma_0_pcie2_to_pcie3_wrapper_i_n_178,xdma_0_pcie2_to_pcie3_wrapper_i_n_179,xdma_0_pcie2_to_pcie3_wrapper_i_n_180,xdma_0_pcie2_to_pcie3_wrapper_i_n_181,xdma_0_pcie2_to_pcie3_wrapper_i_n_182,xdma_0_pcie2_to_pcie3_wrapper_i_n_183,xdma_0_pcie2_to_pcie3_wrapper_i_n_184,xdma_0_pcie2_to_pcie3_wrapper_i_n_185,xdma_0_pcie2_to_pcie3_wrapper_i_n_186,xdma_0_pcie2_to_pcie3_wrapper_i_n_187,xdma_0_pcie2_to_pcie3_wrapper_i_n_188,xdma_0_pcie2_to_pcie3_wrapper_i_n_189,xdma_0_pcie2_to_pcie3_wrapper_i_n_190,xdma_0_pcie2_to_pcie3_wrapper_i_n_191,xdma_0_pcie2_to_pcie3_wrapper_i_n_192,xdma_0_pcie2_to_pcie3_wrapper_i_n_193,xdma_0_pcie2_to_pcie3_wrapper_i_n_194,xdma_0_pcie2_to_pcie3_wrapper_i_n_195,xdma_0_pcie2_to_pcie3_wrapper_i_n_196,xdma_0_pcie2_to_pcie3_wrapper_i_n_197,xdma_0_pcie2_to_pcie3_wrapper_i_n_198,xdma_0_pcie2_to_pcie3_wrapper_i_n_199,xdma_0_pcie2_to_pcie3_wrapper_i_n_200,xdma_0_pcie2_to_pcie3_wrapper_i_n_201,xdma_0_pcie2_to_pcie3_wrapper_i_n_202,xdma_0_pcie2_to_pcie3_wrapper_i_n_203,xdma_0_pcie2_to_pcie3_wrapper_i_n_204,xdma_0_pcie2_to_pcie3_wrapper_i_n_205,xdma_0_pcie2_to_pcie3_wrapper_i_n_206,xdma_0_pcie2_to_pcie3_wrapper_i_n_207,xdma_0_pcie2_to_pcie3_wrapper_i_n_208,xdma_0_pcie2_to_pcie3_wrapper_i_n_209,xdma_0_pcie2_to_pcie3_wrapper_i_n_210,xdma_0_pcie2_to_pcie3_wrapper_i_n_211,xdma_0_pcie2_to_pcie3_wrapper_i_n_212,xdma_0_pcie2_to_pcie3_wrapper_i_n_213,xdma_0_pcie2_to_pcie3_wrapper_i_n_214,xdma_0_pcie2_to_pcie3_wrapper_i_n_215,xdma_0_pcie2_to_pcie3_wrapper_i_n_216,xdma_0_pcie2_to_pcie3_wrapper_i_n_217,xdma_0_pcie2_to_pcie3_wrapper_i_n_218,xdma_0_pcie2_to_pcie3_wrapper_i_n_219,xdma_0_pcie2_to_pcie3_wrapper_i_n_220,xdma_0_pcie2_to_pcie3_wrapper_i_n_221,xdma_0_pcie2_to_pcie3_wrapper_i_n_222,xdma_0_pcie2_to_pcie3_wrapper_i_n_223,xdma_0_pcie2_to_pcie3_wrapper_i_n_224,xdma_0_pcie2_to_pcie3_wrapper_i_n_225,xdma_0_pcie2_to_pcie3_wrapper_i_n_226,xdma_0_pcie2_to_pcie3_wrapper_i_n_227,xdma_0_pcie2_to_pcie3_wrapper_i_n_228,xdma_0_pcie2_to_pcie3_wrapper_i_n_229,xdma_0_pcie2_to_pcie3_wrapper_i_n_230,xdma_0_pcie2_to_pcie3_wrapper_i_n_231,xdma_0_pcie2_to_pcie3_wrapper_i_n_232,xdma_0_pcie2_to_pcie3_wrapper_i_n_233,xdma_0_pcie2_to_pcie3_wrapper_i_n_234,xdma_0_pcie2_to_pcie3_wrapper_i_n_235,xdma_0_pcie2_to_pcie3_wrapper_i_n_236,xdma_0_pcie2_to_pcie3_wrapper_i_n_237,xdma_0_pcie2_to_pcie3_wrapper_i_n_238,xdma_0_pcie2_to_pcie3_wrapper_i_n_239,xdma_0_pcie2_to_pcie3_wrapper_i_n_240}),
        .\s_axis_rc\.tkeep ({xdma_0_pcie2_to_pcie3_wrapper_i_n_170,xdma_0_pcie2_to_pcie3_wrapper_i_n_171}),
        .\s_axis_rc\.tlast (xdma_0_pcie2_to_pcie3_wrapper_i_n_176),
        .\s_axis_rc\.tready ({\NLW_udma_wrapper_s_axis_rc\.tready_UNCONNECTED [21:1],\axis_rc\.tready }),
        .\s_axis_rc\.tuser ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,xdma_0_pcie2_to_pcie3_wrapper_i_n_172,1'b0,xdma_0_pcie2_to_pcie3_wrapper_i_n_173,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,xdma_0_pcie2_to_pcie3_wrapper_i_n_174,1'b0,1'b0,1'b0,xdma_0_pcie2_to_pcie3_wrapper_i_n_175,1'b0,1'b0,1'b0}),
        .\s_axis_rc\.tvalid (1'b0),
        .s_axis_rq_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_rq_tkeep({1'b0,1'b0}),
        .s_axis_rq_tlast(1'b0),
        .s_axis_rq_tready(NLW_udma_wrapper_s_axis_rq_tready_UNCONNECTED),
        .s_axis_rq_tuser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_rq_tvalid(1'b0),
        .sys_reset(dma_soft_reset),
        .user_cfg_ext_function_number_o(NLW_udma_wrapper_user_cfg_ext_function_number_o_UNCONNECTED[7:0]),
        .user_cfg_ext_read_data_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .user_cfg_ext_read_data_valid_i(1'b0),
        .user_cfg_ext_read_received_o(NLW_udma_wrapper_user_cfg_ext_read_received_o_UNCONNECTED),
        .user_cfg_ext_register_number_o(NLW_udma_wrapper_user_cfg_ext_register_number_o_UNCONNECTED[9:0]),
        .user_cfg_ext_write_byte_enable_o(NLW_udma_wrapper_user_cfg_ext_write_byte_enable_o_UNCONNECTED[3:0]),
        .user_cfg_ext_write_data_o(NLW_udma_wrapper_user_cfg_ext_write_data_o_UNCONNECTED[31:0]),
        .user_cfg_ext_write_received_o(NLW_udma_wrapper_user_cfg_ext_write_received_o_UNCONNECTED),
        .user_clk(axi_aclk),
        .usr_flr_clr(NLW_udma_wrapper_usr_flr_clr_UNCONNECTED),
        .usr_flr_done_fnc({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .usr_flr_done_vld(1'b0),
        .usr_flr_fnc(NLW_udma_wrapper_usr_flr_fnc_UNCONNECTED[7:0]),
        .usr_flr_set(NLW_udma_wrapper_usr_flr_set_UNCONNECTED),
        .usr_irq_ack(usr_irq_ack),
        .usr_irq_fail(NLW_udma_wrapper_usr_irq_fail_UNCONNECTED),
        .usr_irq_function_number({n_0_339,n_0_340}),
        .usr_irq_req(usr_irq_req));
  xdma_0_pcie2_to_pcie3_wrapper xdma_0_pcie2_to_pcie3_wrapper_i
       (.CLK(axi_aclk),
        .D({udma_wrapper_n_10730,udma_wrapper_n_10731,udma_wrapper_n_10732,udma_wrapper_n_10733,udma_wrapper_n_10734,udma_wrapper_n_10735,udma_wrapper_n_10736,udma_wrapper_n_10737,udma_wrapper_n_10738,udma_wrapper_n_10739,udma_wrapper_n_10740,udma_wrapper_n_10741,udma_wrapper_n_10742,udma_wrapper_n_10743,udma_wrapper_n_10744,udma_wrapper_n_10745,udma_wrapper_n_10746,udma_wrapper_n_10747,udma_wrapper_n_10748,udma_wrapper_n_10749,udma_wrapper_n_10750,udma_wrapper_n_10751,udma_wrapper_n_10752,udma_wrapper_n_10753,udma_wrapper_n_10754,udma_wrapper_n_10755,udma_wrapper_n_10756,udma_wrapper_n_10757,udma_wrapper_n_10758,udma_wrapper_n_10759,udma_wrapper_n_10760,udma_wrapper_n_10761,udma_wrapper_n_10762,udma_wrapper_n_10763,udma_wrapper_n_10764,udma_wrapper_n_10765,udma_wrapper_n_10766,udma_wrapper_n_10767,udma_wrapper_n_10768,udma_wrapper_n_10769,udma_wrapper_n_10770,udma_wrapper_n_10771,udma_wrapper_n_10772,udma_wrapper_n_10773,udma_wrapper_n_10774,udma_wrapper_n_10775,udma_wrapper_n_10776,udma_wrapper_n_10777,udma_wrapper_n_10778,udma_wrapper_n_10779,udma_wrapper_n_10780,udma_wrapper_n_10781,udma_wrapper_n_10782,udma_wrapper_n_10783,udma_wrapper_n_10784,udma_wrapper_n_10785,udma_wrapper_n_10786,udma_wrapper_n_10787,udma_wrapper_n_10788,udma_wrapper_n_10789,udma_wrapper_n_10790,udma_wrapper_n_10791,udma_wrapper_n_10792,udma_wrapper_n_10793}),
        .cfg_aer_interrupt_msgnum_i(cfg_aer_interrupt_msgnum_i),
        .cfg_bus_number_o(cfg_bus_number_o),
        .cfg_dcommand({xdma_0_pcie2_to_pcie3_wrapper_i_n_133,xdma_0_pcie2_to_pcie3_wrapper_i_n_134,xdma_0_pcie2_to_pcie3_wrapper_i_n_135,xdma_0_pcie2_to_pcie3_wrapper_i_n_136,xdma_0_pcie2_to_pcie3_wrapper_i_n_137,xdma_0_pcie2_to_pcie3_wrapper_i_n_138}),
        .cfg_device_number_o(cfg_device_number_o),
        .cfg_dsn_i(cfg_dsn_i),
        .cfg_err_aer_headerlog_i(cfg_err_aer_headerlog_i),
        .cfg_err_tlp_cpl_header_i(cfg_err_tlp_cpl_header_i),
        .cfg_function_number_o(cfg_function_number_o),
        .cfg_interrupt_di_i(cfg_interrupt_di_i),
        .cfg_interrupt_mmenable(msi_vector_width),
        .cfg_interrupt_msienable(msi_enable),
        .cfg_mgmt_di_i(cfg_mgmt_di_i),
        .cfg_mgmt_do(cfg_mgmt_read_data),
        .cfg_mgmt_dwaddr_i(cfg_mgmt_dwaddr_i),
        .cfg_mgmt_rd_wr_done(cfg_mgmt_read_write_done),
        .cfg_pciecap_interrupt_msgnum_i(cfg_pciecap_interrupt_msgnum_i),
        .cfg_pm_force_state_i(cfg_pm_force_state_i),
        .cfg_to_turnoff_o(cfg_to_turnoff_o),
        .cfg_turnoff_ok_i(cfg_turnoff_ok_i),
        .fc_nph(\pcie_dma_in\.cfg_fc_nph ),
        .fc_sel_i(fc_sel_i),
        .\gtp_channel.gtpe2_channel_i (pci_exp_rxn),
        .\gtp_common.gtpe2_common_i (sys_clk),
        .\m_axis_cc\.tdata ({udma_wrapper_n_10858,udma_wrapper_n_10859,udma_wrapper_n_10860,udma_wrapper_n_10861,udma_wrapper_n_10862,udma_wrapper_n_10863,udma_wrapper_n_10864,udma_wrapper_n_10865,udma_wrapper_n_10866,udma_wrapper_n_10867,udma_wrapper_n_10868,udma_wrapper_n_10869,udma_wrapper_n_10870,udma_wrapper_n_10871,udma_wrapper_n_10872,udma_wrapper_n_10873,udma_wrapper_n_10874,udma_wrapper_n_10875,udma_wrapper_n_10876,udma_wrapper_n_10877,udma_wrapper_n_10878,udma_wrapper_n_10879,udma_wrapper_n_10880,udma_wrapper_n_10881,udma_wrapper_n_10882,udma_wrapper_n_10883,udma_wrapper_n_10884,udma_wrapper_n_10885,udma_wrapper_n_10886,udma_wrapper_n_10887,udma_wrapper_n_10888,udma_wrapper_n_10889,udma_wrapper_n_10890,udma_wrapper_n_10891,udma_wrapper_n_10892,udma_wrapper_n_10893,udma_wrapper_n_10894,udma_wrapper_n_10895,udma_wrapper_n_10896,udma_wrapper_n_10897,udma_wrapper_n_10898,udma_wrapper_n_10899,udma_wrapper_n_10900,udma_wrapper_n_10901,udma_wrapper_n_10902,udma_wrapper_n_10903,udma_wrapper_n_10904,udma_wrapper_n_10905,udma_wrapper_n_10906,udma_wrapper_n_10907,udma_wrapper_n_10908,udma_wrapper_n_10909,udma_wrapper_n_10910,udma_wrapper_n_10911,udma_wrapper_n_10912,udma_wrapper_n_10913,udma_wrapper_n_10914,udma_wrapper_n_10915,udma_wrapper_n_10916,udma_wrapper_n_10917,udma_wrapper_n_10918,udma_wrapper_n_10919,udma_wrapper_n_10920,udma_wrapper_n_10921}),
        .\m_axis_cc\.tlast (udma_wrapper_n_10955),
        .\m_axis_cc\.tready (xdma_0_pcie2_to_pcie3_wrapper_i_n_312),
        .\m_axis_cc\.tvalid (udma_wrapper_n_10958),
        .\m_axis_rq\.tlast (udma_wrapper_n_10794),
        .\m_axis_rq\.tready (xdma_0_pcie2_to_pcie3_wrapper_i_n_168),
        .\m_axis_rq\.tvalid (udma_wrapper_n_10857),
        .m_axis_rx_tdata_o(m_axis_rx_tdata_o),
        .m_axis_rx_tkeep_o(\^m_axis_rx_tkeep_o ),
        .m_axis_rx_tlast_o(m_axis_rx_tlast_o),
        .m_axis_rx_tready_i(m_axis_rx_tready_i),
        .m_axis_rx_tuser_o({\^m_axis_rx_tuser_o [21],\^m_axis_rx_tuser_o [19:17],\^m_axis_rx_tuser_o [14],\^m_axis_rx_tuser_o [8:0]}),
        .m_axis_rx_tvalid_o(m_axis_rx_tvalid_o),
        .out(pci_exp_rxp),
        .pci_exp_txn(pci_exp_txn),
        .pci_exp_txp(pci_exp_txp),
        .pcie_block_i(cfg_mgmt_byte_enable),
        .pcie_block_i_0(cfg_mgmt_write),
        .pcie_block_i_1(cfg_mgmt_read),
        .pcie_block_i_2(cfg_mgmt_type1_cfg_reg_access),
        .pcie_block_i_3(cfg_mgmt_write_data),
        .pcie_block_i_4(cfg_mgmt_addr[9:0]),
        .\pcie_dma_in\.cfg_interrupt_msi_sent (xdma_0_pcie2_to_pcie3_wrapper_i_n_167),
        .\pcie_dma_in\.cfg_interrupt_sent (\pcie_dma_in\.cfg_interrupt_sent ),
        .\pcie_dma_in\.cfg_phy_link_down (\pcie_dma_in\.cfg_phy_link_down ),
        .\pcie_dma_in\.pcie_rq_seq_num0 (\pcie_dma_in\.pcie_rq_seq_num0 ),
        .\pcie_dma_in\.pcie_rq_seq_num_vld0 (\pcie_dma_in\.pcie_rq_seq_num_vld0 ),
        .\pcie_dma_out\.cfg_fc_sel (cfg_fc_sel),
        .\pcie_dma_out\.cfg_interrupt_int (cfg_interrupt_int),
        .\pcie_dma_out\.cfg_interrupt_msi_int (cfg_interrupt_msi_int),
        .\pcie_dma_out\.pcie_cq_np_req (\pcie_dma_out\.pcie_cq_np_req ),
        .pl_directed_link_auton_i(pl_directed_link_auton_i),
        .pl_directed_link_change_i(pl_directed_link_change_i),
        .pl_directed_link_speed_i(pl_directed_link_speed_i),
        .pl_directed_link_width_i(pl_directed_link_width_i),
        .pl_upstream_prefer_deemph_i(pl_upstream_prefer_deemph_i),
        .reset_n_reg2_reg(sys_rst_n),
        .rx_np_ok_i(rx_np_ok_i),
        .rx_np_req_i(rx_np_req_i),
        .s_aresetn(\xdma_0_cfg_sideband_i/p_9_in ),
        .\s_axis_cq\.tdata ({xdma_0_pcie2_to_pcie3_wrapper_i_n_241,xdma_0_pcie2_to_pcie3_wrapper_i_n_242,xdma_0_pcie2_to_pcie3_wrapper_i_n_243,xdma_0_pcie2_to_pcie3_wrapper_i_n_244,xdma_0_pcie2_to_pcie3_wrapper_i_n_245,xdma_0_pcie2_to_pcie3_wrapper_i_n_246,xdma_0_pcie2_to_pcie3_wrapper_i_n_247,xdma_0_pcie2_to_pcie3_wrapper_i_n_248,xdma_0_pcie2_to_pcie3_wrapper_i_n_249,xdma_0_pcie2_to_pcie3_wrapper_i_n_250,xdma_0_pcie2_to_pcie3_wrapper_i_n_251,xdma_0_pcie2_to_pcie3_wrapper_i_n_252,xdma_0_pcie2_to_pcie3_wrapper_i_n_253,xdma_0_pcie2_to_pcie3_wrapper_i_n_254,xdma_0_pcie2_to_pcie3_wrapper_i_n_255,xdma_0_pcie2_to_pcie3_wrapper_i_n_256,xdma_0_pcie2_to_pcie3_wrapper_i_n_257,xdma_0_pcie2_to_pcie3_wrapper_i_n_258,xdma_0_pcie2_to_pcie3_wrapper_i_n_259,xdma_0_pcie2_to_pcie3_wrapper_i_n_260,xdma_0_pcie2_to_pcie3_wrapper_i_n_261,xdma_0_pcie2_to_pcie3_wrapper_i_n_262,xdma_0_pcie2_to_pcie3_wrapper_i_n_263,xdma_0_pcie2_to_pcie3_wrapper_i_n_264,xdma_0_pcie2_to_pcie3_wrapper_i_n_265,xdma_0_pcie2_to_pcie3_wrapper_i_n_266,xdma_0_pcie2_to_pcie3_wrapper_i_n_267,xdma_0_pcie2_to_pcie3_wrapper_i_n_268,xdma_0_pcie2_to_pcie3_wrapper_i_n_269,xdma_0_pcie2_to_pcie3_wrapper_i_n_270,xdma_0_pcie2_to_pcie3_wrapper_i_n_271,xdma_0_pcie2_to_pcie3_wrapper_i_n_272,xdma_0_pcie2_to_pcie3_wrapper_i_n_273,xdma_0_pcie2_to_pcie3_wrapper_i_n_274,xdma_0_pcie2_to_pcie3_wrapper_i_n_275,xdma_0_pcie2_to_pcie3_wrapper_i_n_276,xdma_0_pcie2_to_pcie3_wrapper_i_n_277,xdma_0_pcie2_to_pcie3_wrapper_i_n_278,xdma_0_pcie2_to_pcie3_wrapper_i_n_279,xdma_0_pcie2_to_pcie3_wrapper_i_n_280,xdma_0_pcie2_to_pcie3_wrapper_i_n_281,xdma_0_pcie2_to_pcie3_wrapper_i_n_282,xdma_0_pcie2_to_pcie3_wrapper_i_n_283,xdma_0_pcie2_to_pcie3_wrapper_i_n_284,xdma_0_pcie2_to_pcie3_wrapper_i_n_285,xdma_0_pcie2_to_pcie3_wrapper_i_n_286,xdma_0_pcie2_to_pcie3_wrapper_i_n_287,xdma_0_pcie2_to_pcie3_wrapper_i_n_288,xdma_0_pcie2_to_pcie3_wrapper_i_n_289,xdma_0_pcie2_to_pcie3_wrapper_i_n_290,xdma_0_pcie2_to_pcie3_wrapper_i_n_291,xdma_0_pcie2_to_pcie3_wrapper_i_n_292,xdma_0_pcie2_to_pcie3_wrapper_i_n_293,xdma_0_pcie2_to_pcie3_wrapper_i_n_294,xdma_0_pcie2_to_pcie3_wrapper_i_n_295,xdma_0_pcie2_to_pcie3_wrapper_i_n_296,xdma_0_pcie2_to_pcie3_wrapper_i_n_297,xdma_0_pcie2_to_pcie3_wrapper_i_n_298,xdma_0_pcie2_to_pcie3_wrapper_i_n_299,xdma_0_pcie2_to_pcie3_wrapper_i_n_300,xdma_0_pcie2_to_pcie3_wrapper_i_n_301,xdma_0_pcie2_to_pcie3_wrapper_i_n_302,xdma_0_pcie2_to_pcie3_wrapper_i_n_303,xdma_0_pcie2_to_pcie3_wrapper_i_n_304}),
        .\s_axis_cq\.tlast (xdma_0_pcie2_to_pcie3_wrapper_i_n_311),
        .\s_axis_cq\.tready (udma_wrapper_n_11002),
        .\s_axis_cq\.tuser ({xdma_0_pcie2_to_pcie3_wrapper_i_n_305,xdma_0_pcie2_to_pcie3_wrapper_i_n_306,xdma_0_pcie2_to_pcie3_wrapper_i_n_307,xdma_0_pcie2_to_pcie3_wrapper_i_n_308,xdma_0_pcie2_to_pcie3_wrapper_i_n_309}),
        .\s_axis_cq\.tvalid (xdma_0_pcie2_to_pcie3_wrapper_i_n_310),
        .\s_axis_rc\.tdata ({xdma_0_pcie2_to_pcie3_wrapper_i_n_177,xdma_0_pcie2_to_pcie3_wrapper_i_n_178,xdma_0_pcie2_to_pcie3_wrapper_i_n_179,xdma_0_pcie2_to_pcie3_wrapper_i_n_180,xdma_0_pcie2_to_pcie3_wrapper_i_n_181,xdma_0_pcie2_to_pcie3_wrapper_i_n_182,xdma_0_pcie2_to_pcie3_wrapper_i_n_183,xdma_0_pcie2_to_pcie3_wrapper_i_n_184,xdma_0_pcie2_to_pcie3_wrapper_i_n_185,xdma_0_pcie2_to_pcie3_wrapper_i_n_186,xdma_0_pcie2_to_pcie3_wrapper_i_n_187,xdma_0_pcie2_to_pcie3_wrapper_i_n_188,xdma_0_pcie2_to_pcie3_wrapper_i_n_189,xdma_0_pcie2_to_pcie3_wrapper_i_n_190,xdma_0_pcie2_to_pcie3_wrapper_i_n_191,xdma_0_pcie2_to_pcie3_wrapper_i_n_192,xdma_0_pcie2_to_pcie3_wrapper_i_n_193,xdma_0_pcie2_to_pcie3_wrapper_i_n_194,xdma_0_pcie2_to_pcie3_wrapper_i_n_195,xdma_0_pcie2_to_pcie3_wrapper_i_n_196,xdma_0_pcie2_to_pcie3_wrapper_i_n_197,xdma_0_pcie2_to_pcie3_wrapper_i_n_198,xdma_0_pcie2_to_pcie3_wrapper_i_n_199,xdma_0_pcie2_to_pcie3_wrapper_i_n_200,xdma_0_pcie2_to_pcie3_wrapper_i_n_201,xdma_0_pcie2_to_pcie3_wrapper_i_n_202,xdma_0_pcie2_to_pcie3_wrapper_i_n_203,xdma_0_pcie2_to_pcie3_wrapper_i_n_204,xdma_0_pcie2_to_pcie3_wrapper_i_n_205,xdma_0_pcie2_to_pcie3_wrapper_i_n_206,xdma_0_pcie2_to_pcie3_wrapper_i_n_207,xdma_0_pcie2_to_pcie3_wrapper_i_n_208,xdma_0_pcie2_to_pcie3_wrapper_i_n_209,xdma_0_pcie2_to_pcie3_wrapper_i_n_210,xdma_0_pcie2_to_pcie3_wrapper_i_n_211,xdma_0_pcie2_to_pcie3_wrapper_i_n_212,xdma_0_pcie2_to_pcie3_wrapper_i_n_213,xdma_0_pcie2_to_pcie3_wrapper_i_n_214,xdma_0_pcie2_to_pcie3_wrapper_i_n_215,xdma_0_pcie2_to_pcie3_wrapper_i_n_216,xdma_0_pcie2_to_pcie3_wrapper_i_n_217,xdma_0_pcie2_to_pcie3_wrapper_i_n_218,xdma_0_pcie2_to_pcie3_wrapper_i_n_219,xdma_0_pcie2_to_pcie3_wrapper_i_n_220,xdma_0_pcie2_to_pcie3_wrapper_i_n_221,xdma_0_pcie2_to_pcie3_wrapper_i_n_222,xdma_0_pcie2_to_pcie3_wrapper_i_n_223,xdma_0_pcie2_to_pcie3_wrapper_i_n_224,xdma_0_pcie2_to_pcie3_wrapper_i_n_225,xdma_0_pcie2_to_pcie3_wrapper_i_n_226,xdma_0_pcie2_to_pcie3_wrapper_i_n_227,xdma_0_pcie2_to_pcie3_wrapper_i_n_228,xdma_0_pcie2_to_pcie3_wrapper_i_n_229,xdma_0_pcie2_to_pcie3_wrapper_i_n_230,xdma_0_pcie2_to_pcie3_wrapper_i_n_231,xdma_0_pcie2_to_pcie3_wrapper_i_n_232,xdma_0_pcie2_to_pcie3_wrapper_i_n_233,xdma_0_pcie2_to_pcie3_wrapper_i_n_234,xdma_0_pcie2_to_pcie3_wrapper_i_n_235,xdma_0_pcie2_to_pcie3_wrapper_i_n_236,xdma_0_pcie2_to_pcie3_wrapper_i_n_237,xdma_0_pcie2_to_pcie3_wrapper_i_n_238,xdma_0_pcie2_to_pcie3_wrapper_i_n_239,xdma_0_pcie2_to_pcie3_wrapper_i_n_240}),
        .\s_axis_rc\.tkeep ({xdma_0_pcie2_to_pcie3_wrapper_i_n_170,xdma_0_pcie2_to_pcie3_wrapper_i_n_171}),
        .\s_axis_rc\.tlast (xdma_0_pcie2_to_pcie3_wrapper_i_n_176),
        .\s_axis_rc\.tready (\axis_rc\.tready ),
        .\s_axis_rc\.tuser ({xdma_0_pcie2_to_pcie3_wrapper_i_n_172,xdma_0_pcie2_to_pcie3_wrapper_i_n_173,xdma_0_pcie2_to_pcie3_wrapper_i_n_174,xdma_0_pcie2_to_pcie3_wrapper_i_n_175}),
        .s_axis_rq_tuser({udma_wrapper_n_10827,udma_wrapper_n_10828,udma_wrapper_n_10829,udma_wrapper_n_10830,udma_wrapper_n_10847,udma_wrapper_n_10848,udma_wrapper_n_10849,udma_wrapper_n_10850,udma_wrapper_n_10851,udma_wrapper_n_10852,udma_wrapper_n_10853,udma_wrapper_n_10854}),
        .s_axis_tx_tdata_i(s_axis_tx_tdata_i),
        .s_axis_tx_tkeep_i(s_axis_tx_tkeep_i[7]),
        .s_axis_tx_tlast_i(s_axis_tx_tlast_i),
        .s_axis_tx_tready_o(s_axis_tx_tready_o),
        .s_axis_tx_tuser_i(s_axis_tx_tuser_i),
        .s_axis_tx_tvalid_i(s_axis_tx_tvalid_i),
        .tx_cfg_gnt_i(tx_cfg_gnt_i),
        .user_lnk_up(user_lnk_up),
        .user_reset_out(dma_soft_reset));
endmodule

module xdma_0_dma_cpl
   (in_packet_q,
    Q,
    \s_axis_rc\.tkeep ,
    \s_axis_rc\.tuser ,
    \s_axis_rc\.tlast ,
    \s_axis_rc\.tdata ,
    in_packet_q_reg_0,
    user_clk_out,
    user_reset_out,
    \s_axis_rc\.tready ,
    m_axis_tvalid,
    m_axis_tdata,
    D,
    \rc_64.wr_compl_status_reg[2]_0 ,
    \rc_64.wr_byte_reg[11]_0 ,
    \rc_64.wr_cid_reg[15]_0 ,
    \rc_64.wr_tc_reg[2]_0 ,
    \rc_64.wr_attr_reg[2]_0 ,
    \rc_64.wr_data_reg[31]_0 );
  output in_packet_q;
  output [1:0]Q;
  output [1:0]\s_axis_rc\.tkeep ;
  output [3:0]\s_axis_rc\.tuser ;
  output \s_axis_rc\.tlast ;
  output [63:0]\s_axis_rc\.tdata ;
  input in_packet_q_reg_0;
  input user_clk_out;
  input user_reset_out;
  input [0:0]\s_axis_rc\.tready ;
  input m_axis_tvalid;
  input [62:0]m_axis_tdata;
  input [9:0]D;
  input [2:0]\rc_64.wr_compl_status_reg[2]_0 ;
  input [11:0]\rc_64.wr_byte_reg[11]_0 ;
  input [15:0]\rc_64.wr_cid_reg[15]_0 ;
  input [2:0]\rc_64.wr_tc_reg[2]_0 ;
  input [2:0]\rc_64.wr_attr_reg[2]_0 ;
  input [31:0]\rc_64.wr_data_reg[31]_0 ;

  wire [9:0]D;
  wire [1:0]Q;
  wire [11:0]current_dw_count;
  wire [63:0]data1;
  wire in_packet_q;
  wire in_packet_q_reg_0;
  wire [62:0]m_axis_tdata;
  wire m_axis_tvalid;
  wire [46:16]p_0_out;
  wire [30:30]p_0_out__0;
  wire [13:13]p_0_out__0__0;
  wire [7:0]p_1_in;
  wire \rc_64.current_dw_count[0]_i_1_n_0 ;
  wire \rc_64.current_dw_count[10]_i_1_n_0 ;
  wire \rc_64.current_dw_count[11]_i_1_n_0 ;
  wire \rc_64.current_dw_count[1]_i_1_n_0 ;
  wire \rc_64.current_dw_count[2]_i_1_n_0 ;
  wire \rc_64.current_dw_count[3]_i_1_n_0 ;
  wire \rc_64.current_dw_count[3]_i_3_n_0 ;
  wire \rc_64.current_dw_count[3]_i_4_n_0 ;
  wire \rc_64.current_dw_count[4]_i_1_n_0 ;
  wire \rc_64.current_dw_count[5]_i_1_n_0 ;
  wire \rc_64.current_dw_count[6]_i_1_n_0 ;
  wire \rc_64.current_dw_count[7]_i_1_n_0 ;
  wire \rc_64.current_dw_count[8]_i_1_n_0 ;
  wire \rc_64.current_dw_count[9]_i_1_n_0 ;
  wire \rc_64.current_dw_count_reg[11]_i_2_n_1 ;
  wire \rc_64.current_dw_count_reg[11]_i_2_n_2 ;
  wire \rc_64.current_dw_count_reg[11]_i_2_n_3 ;
  wire \rc_64.current_dw_count_reg[11]_i_2_n_4 ;
  wire \rc_64.current_dw_count_reg[11]_i_2_n_5 ;
  wire \rc_64.current_dw_count_reg[11]_i_2_n_6 ;
  wire \rc_64.current_dw_count_reg[11]_i_2_n_7 ;
  wire \rc_64.current_dw_count_reg[3]_i_2_n_0 ;
  wire \rc_64.current_dw_count_reg[3]_i_2_n_1 ;
  wire \rc_64.current_dw_count_reg[3]_i_2_n_2 ;
  wire \rc_64.current_dw_count_reg[3]_i_2_n_3 ;
  wire \rc_64.current_dw_count_reg[3]_i_2_n_4 ;
  wire \rc_64.current_dw_count_reg[3]_i_2_n_5 ;
  wire \rc_64.current_dw_count_reg[3]_i_2_n_6 ;
  wire \rc_64.current_dw_count_reg[3]_i_2_n_7 ;
  wire \rc_64.current_dw_count_reg[7]_i_2_n_0 ;
  wire \rc_64.current_dw_count_reg[7]_i_2_n_1 ;
  wire \rc_64.current_dw_count_reg[7]_i_2_n_2 ;
  wire \rc_64.current_dw_count_reg[7]_i_2_n_3 ;
  wire \rc_64.current_dw_count_reg[7]_i_2_n_4 ;
  wire \rc_64.current_dw_count_reg[7]_i_2_n_5 ;
  wire \rc_64.current_dw_count_reg[7]_i_2_n_6 ;
  wire \rc_64.current_dw_count_reg[7]_i_2_n_7 ;
  wire \rc_64.state[0]_i_2_n_0 ;
  wire \rc_64.state[0]_i_3_n_0 ;
  wire \rc_64.state[1]_i_2_n_0 ;
  wire \rc_64.state[2]_i_1_n_0 ;
  wire \rc_64.state[2]_i_3_n_0 ;
  wire \rc_64.state[2]_i_4_n_0 ;
  wire \rc_64.state[2]_i_5_n_0 ;
  wire \rc_64.state[2]_i_6_n_0 ;
  wire \rc_64.state_reg_n_0_[2] ;
  wire [2:0]\rc_64.wr_attr_reg[2]_0 ;
  wire [11:0]\rc_64.wr_byte_reg[11]_0 ;
  wire [15:0]\rc_64.wr_cid_reg[15]_0 ;
  wire [2:0]\rc_64.wr_compl_status_reg[2]_0 ;
  wire \rc_64.wr_data[32]_i_1_n_0 ;
  wire \rc_64.wr_data[33]_i_1_n_0 ;
  wire \rc_64.wr_data[34]_i_1_n_0 ;
  wire \rc_64.wr_data[35]_i_1_n_0 ;
  wire \rc_64.wr_data[36]_i_1_n_0 ;
  wire \rc_64.wr_data[37]_i_1_n_0 ;
  wire \rc_64.wr_data[38]_i_1_n_0 ;
  wire \rc_64.wr_data[39]_i_1_n_0 ;
  wire \rc_64.wr_data[40]_i_1_n_0 ;
  wire \rc_64.wr_data[41]_i_1_n_0 ;
  wire \rc_64.wr_data[42]_i_1_n_0 ;
  wire \rc_64.wr_data[43]_i_1_n_0 ;
  wire \rc_64.wr_data[44]_i_1_n_0 ;
  wire \rc_64.wr_data[45]_i_1_n_0 ;
  wire \rc_64.wr_data[46]_i_1_n_0 ;
  wire \rc_64.wr_data[47]_i_1_n_0 ;
  wire \rc_64.wr_data[48]_i_1_n_0 ;
  wire \rc_64.wr_data[49]_i_1_n_0 ;
  wire \rc_64.wr_data[50]_i_1_n_0 ;
  wire \rc_64.wr_data[51]_i_1_n_0 ;
  wire \rc_64.wr_data[52]_i_1_n_0 ;
  wire \rc_64.wr_data[53]_i_1_n_0 ;
  wire \rc_64.wr_data[54]_i_1_n_0 ;
  wire \rc_64.wr_data[55]_i_1_n_0 ;
  wire \rc_64.wr_data[56]_i_1_n_0 ;
  wire \rc_64.wr_data[57]_i_1_n_0 ;
  wire \rc_64.wr_data[58]_i_1_n_0 ;
  wire \rc_64.wr_data[59]_i_1_n_0 ;
  wire \rc_64.wr_data[60]_i_1_n_0 ;
  wire \rc_64.wr_data[61]_i_1_n_0 ;
  wire \rc_64.wr_data[62]_i_1_n_0 ;
  wire \rc_64.wr_data[63]_i_1_n_0 ;
  wire [31:0]\rc_64.wr_data_reg[31]_0 ;
  wire \rc_64.wr_data_reg_n_0_[32] ;
  wire \rc_64.wr_data_reg_n_0_[33] ;
  wire \rc_64.wr_data_reg_n_0_[34] ;
  wire \rc_64.wr_data_reg_n_0_[35] ;
  wire \rc_64.wr_data_reg_n_0_[36] ;
  wire \rc_64.wr_data_reg_n_0_[37] ;
  wire \rc_64.wr_data_reg_n_0_[38] ;
  wire \rc_64.wr_data_reg_n_0_[39] ;
  wire \rc_64.wr_data_reg_n_0_[40] ;
  wire \rc_64.wr_data_reg_n_0_[41] ;
  wire \rc_64.wr_data_reg_n_0_[42] ;
  wire \rc_64.wr_data_reg_n_0_[43] ;
  wire \rc_64.wr_data_reg_n_0_[44] ;
  wire \rc_64.wr_data_reg_n_0_[45] ;
  wire \rc_64.wr_data_reg_n_0_[46] ;
  wire \rc_64.wr_data_reg_n_0_[47] ;
  wire \rc_64.wr_data_reg_n_0_[48] ;
  wire \rc_64.wr_data_reg_n_0_[49] ;
  wire \rc_64.wr_data_reg_n_0_[50] ;
  wire \rc_64.wr_data_reg_n_0_[51] ;
  wire \rc_64.wr_data_reg_n_0_[52] ;
  wire \rc_64.wr_data_reg_n_0_[53] ;
  wire \rc_64.wr_data_reg_n_0_[54] ;
  wire \rc_64.wr_data_reg_n_0_[55] ;
  wire \rc_64.wr_data_reg_n_0_[56] ;
  wire \rc_64.wr_data_reg_n_0_[57] ;
  wire \rc_64.wr_data_reg_n_0_[58] ;
  wire \rc_64.wr_data_reg_n_0_[59] ;
  wire \rc_64.wr_data_reg_n_0_[60] ;
  wire \rc_64.wr_data_reg_n_0_[61] ;
  wire \rc_64.wr_data_reg_n_0_[62] ;
  wire \rc_64.wr_data_reg_n_0_[63] ;
  wire \rc_64.wr_ep_i_1_n_0 ;
  wire \rc_64.wr_len_reg_n_0_[0] ;
  wire \rc_64.wr_len_reg_n_0_[1] ;
  wire \rc_64.wr_len_reg_n_0_[2] ;
  wire \rc_64.wr_len_reg_n_0_[3] ;
  wire \rc_64.wr_len_reg_n_0_[4] ;
  wire \rc_64.wr_len_reg_n_0_[5] ;
  wire \rc_64.wr_len_reg_n_0_[6] ;
  wire \rc_64.wr_len_reg_n_0_[7] ;
  wire \rc_64.wr_len_reg_n_0_[8] ;
  wire \rc_64.wr_len_reg_n_0_[9] ;
  wire \rc_64.wr_tag[7]_i_1_n_0 ;
  wire [2:0]\rc_64.wr_tc_reg[2]_0 ;
  wire [63:0]\s_axis_rc\.tdata ;
  wire [1:0]\s_axis_rc\.tkeep ;
  wire \s_axis_rc\.tlast ;
  wire [0:0]\s_axis_rc\.tready ;
  wire [3:0]\s_axis_rc\.tuser ;
  wire [1:1]s_axis_rc_tkeep0;
  wire [2:0]state;
  wire udma_wrapper_i_156_n_0;
  wire udma_wrapper_i_157_n_0;
  wire udma_wrapper_i_158_n_0;
  wire udma_wrapper_i_159_n_0;
  wire udma_wrapper_i_161_n_0;
  wire udma_wrapper_i_163_n_0;
  wire udma_wrapper_i_164_n_0;
  wire udma_wrapper_i_165_n_0;
  wire udma_wrapper_i_166_n_0;
  wire udma_wrapper_i_166_n_1;
  wire udma_wrapper_i_166_n_2;
  wire udma_wrapper_i_166_n_3;
  wire udma_wrapper_i_166_n_4;
  wire udma_wrapper_i_166_n_5;
  wire udma_wrapper_i_166_n_6;
  wire udma_wrapper_i_166_n_7;
  wire udma_wrapper_i_167_n_0;
  wire udma_wrapper_i_168_n_0;
  wire udma_wrapper_i_169_n_0;
  wire udma_wrapper_i_170_n_0;
  wire udma_wrapper_i_170_n_1;
  wire udma_wrapper_i_170_n_2;
  wire udma_wrapper_i_170_n_3;
  wire udma_wrapper_i_170_n_4;
  wire udma_wrapper_i_170_n_5;
  wire udma_wrapper_i_170_n_6;
  wire udma_wrapper_i_170_n_7;
  wire udma_wrapper_i_171_n_0;
  wire udma_wrapper_i_172_n_0;
  wire udma_wrapper_i_241_n_0;
  wire udma_wrapper_i_242_n_0;
  wire udma_wrapper_i_242_n_1;
  wire udma_wrapper_i_242_n_2;
  wire udma_wrapper_i_242_n_3;
  wire udma_wrapper_i_243_n_0;
  wire udma_wrapper_i_244_n_0;
  wire udma_wrapper_i_245_n_0;
  wire udma_wrapper_i_246_n_0;
  wire udma_wrapper_i_247_n_1;
  wire udma_wrapper_i_247_n_2;
  wire udma_wrapper_i_247_n_3;
  wire udma_wrapper_i_247_n_4;
  wire udma_wrapper_i_247_n_5;
  wire udma_wrapper_i_247_n_6;
  wire udma_wrapper_i_247_n_7;
  wire udma_wrapper_i_248_n_0;
  wire udma_wrapper_i_249_n_0;
  wire udma_wrapper_i_250_n_0;
  wire udma_wrapper_i_251_n_0;
  wire udma_wrapper_i_252_n_0;
  wire udma_wrapper_i_253_n_0;
  wire udma_wrapper_i_254_n_0;
  wire udma_wrapper_i_255_n_0;
  wire udma_wrapper_i_256_n_0;
  wire udma_wrapper_i_266_n_0;
  wire udma_wrapper_i_267_n_0;
  wire udma_wrapper_i_268_n_0;
  wire udma_wrapper_i_269_n_0;
  wire udma_wrapper_i_270_n_0;
  wire udma_wrapper_i_271_n_0;
  wire udma_wrapper_i_272_n_0;
  wire udma_wrapper_i_273_n_0;
  wire udma_wrapper_i_274_n_0;
  wire udma_wrapper_i_275_n_0;
  wire udma_wrapper_i_276_n_0;
  wire udma_wrapper_i_277_n_0;
  wire udma_wrapper_i_278_n_0;
  wire udma_wrapper_i_279_n_0;
  wire user_clk_out;
  wire user_reset_out;
  wire wr_compl_status;
  wire [3:3]\NLW_rc_64.current_dw_count_reg[11]_i_2_CO_UNCONNECTED ;
  wire [3:1]NLW_udma_wrapper_i_160_CO_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_i_160_O_UNCONNECTED;
  wire [3:0]NLW_udma_wrapper_i_242_O_UNCONNECTED;
  wire [3:3]NLW_udma_wrapper_i_247_CO_UNCONNECTED;

  FDRE in_packet_q_reg
       (.C(user_clk_out),
        .CE(1'b1),
        .D(in_packet_q_reg_0),
        .Q(in_packet_q),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1915" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[0]_i_1 
       (.I0(\rc_64.current_dw_count_reg[3]_i_2_n_7 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1910" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[10]_i_1 
       (.I0(\rc_64.current_dw_count_reg[11]_i_2_n_5 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1910" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[11]_i_1 
       (.I0(\rc_64.current_dw_count_reg[11]_i_2_n_4 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1914" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[1]_i_1 
       (.I0(\rc_64.current_dw_count_reg[3]_i_2_n_6 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1914" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[2]_i_1 
       (.I0(\rc_64.current_dw_count_reg[3]_i_2_n_5 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1913" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[3]_i_1 
       (.I0(\rc_64.current_dw_count_reg[3]_i_2_n_4 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h4B)) 
    \rc_64.current_dw_count[3]_i_3 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(current_dw_count[1]),
        .O(\rc_64.current_dw_count[3]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hE1)) 
    \rc_64.current_dw_count[3]_i_4 
       (.I0(Q[0]),
        .I1(\rc_64.state_reg_n_0_[2] ),
        .I2(current_dw_count[0]),
        .O(\rc_64.current_dw_count[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1913" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[4]_i_1 
       (.I0(\rc_64.current_dw_count_reg[7]_i_2_n_7 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1911" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[5]_i_1 
       (.I0(\rc_64.current_dw_count_reg[7]_i_2_n_6 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1912" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[6]_i_1 
       (.I0(\rc_64.current_dw_count_reg[7]_i_2_n_5 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1912" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[7]_i_1 
       (.I0(\rc_64.current_dw_count_reg[7]_i_2_n_4 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1911" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[8]_i_1 
       (.I0(\rc_64.current_dw_count_reg[11]_i_2_n_7 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1909" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rc_64.current_dw_count[9]_i_1 
       (.I0(\rc_64.current_dw_count_reg[11]_i_2_n_6 ),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.current_dw_count[9]_i_1_n_0 ));
  FDRE \rc_64.current_dw_count_reg[0] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[0]_i_1_n_0 ),
        .Q(current_dw_count[0]),
        .R(user_reset_out));
  FDRE \rc_64.current_dw_count_reg[10] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[10]_i_1_n_0 ),
        .Q(current_dw_count[10]),
        .R(user_reset_out));
  FDRE \rc_64.current_dw_count_reg[11] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[11]_i_1_n_0 ),
        .Q(current_dw_count[11]),
        .R(user_reset_out));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \rc_64.current_dw_count_reg[11]_i_2 
       (.CI(\rc_64.current_dw_count_reg[7]_i_2_n_0 ),
        .CO({\NLW_rc_64.current_dw_count_reg[11]_i_2_CO_UNCONNECTED [3],\rc_64.current_dw_count_reg[11]_i_2_n_1 ,\rc_64.current_dw_count_reg[11]_i_2_n_2 ,\rc_64.current_dw_count_reg[11]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\rc_64.current_dw_count_reg[11]_i_2_n_4 ,\rc_64.current_dw_count_reg[11]_i_2_n_5 ,\rc_64.current_dw_count_reg[11]_i_2_n_6 ,\rc_64.current_dw_count_reg[11]_i_2_n_7 }),
        .S(current_dw_count[11:8]));
  FDRE \rc_64.current_dw_count_reg[1] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[1]_i_1_n_0 ),
        .Q(current_dw_count[1]),
        .R(user_reset_out));
  FDRE \rc_64.current_dw_count_reg[2] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[2]_i_1_n_0 ),
        .Q(current_dw_count[2]),
        .R(user_reset_out));
  FDRE \rc_64.current_dw_count_reg[3] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[3]_i_1_n_0 ),
        .Q(current_dw_count[3]),
        .R(user_reset_out));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \rc_64.current_dw_count_reg[3]_i_2 
       (.CI(1'b0),
        .CO({\rc_64.current_dw_count_reg[3]_i_2_n_0 ,\rc_64.current_dw_count_reg[3]_i_2_n_1 ,\rc_64.current_dw_count_reg[3]_i_2_n_2 ,\rc_64.current_dw_count_reg[3]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,current_dw_count[1:0]}),
        .O({\rc_64.current_dw_count_reg[3]_i_2_n_4 ,\rc_64.current_dw_count_reg[3]_i_2_n_5 ,\rc_64.current_dw_count_reg[3]_i_2_n_6 ,\rc_64.current_dw_count_reg[3]_i_2_n_7 }),
        .S({current_dw_count[3:2],\rc_64.current_dw_count[3]_i_3_n_0 ,\rc_64.current_dw_count[3]_i_4_n_0 }));
  FDRE \rc_64.current_dw_count_reg[4] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[4]_i_1_n_0 ),
        .Q(current_dw_count[4]),
        .R(user_reset_out));
  FDRE \rc_64.current_dw_count_reg[5] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[5]_i_1_n_0 ),
        .Q(current_dw_count[5]),
        .R(user_reset_out));
  FDRE \rc_64.current_dw_count_reg[6] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[6]_i_1_n_0 ),
        .Q(current_dw_count[6]),
        .R(user_reset_out));
  FDRE \rc_64.current_dw_count_reg[7] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[7]_i_1_n_0 ),
        .Q(current_dw_count[7]),
        .R(user_reset_out));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \rc_64.current_dw_count_reg[7]_i_2 
       (.CI(\rc_64.current_dw_count_reg[3]_i_2_n_0 ),
        .CO({\rc_64.current_dw_count_reg[7]_i_2_n_0 ,\rc_64.current_dw_count_reg[7]_i_2_n_1 ,\rc_64.current_dw_count_reg[7]_i_2_n_2 ,\rc_64.current_dw_count_reg[7]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\rc_64.current_dw_count_reg[7]_i_2_n_4 ,\rc_64.current_dw_count_reg[7]_i_2_n_5 ,\rc_64.current_dw_count_reg[7]_i_2_n_6 ,\rc_64.current_dw_count_reg[7]_i_2_n_7 }),
        .S(current_dw_count[7:4]));
  FDRE \rc_64.current_dw_count_reg[8] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[8]_i_1_n_0 ),
        .Q(current_dw_count[8]),
        .R(user_reset_out));
  FDRE \rc_64.current_dw_count_reg[9] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.current_dw_count[9]_i_1_n_0 ),
        .Q(current_dw_count[9]),
        .R(user_reset_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFA8AA)) 
    \rc_64.state[0]_i_1 
       (.I0(\rc_64.state[2]_i_5_n_0 ),
        .I1(udma_wrapper_i_165_n_0),
        .I2(\rc_64.state[2]_i_4_n_0 ),
        .I3(\s_axis_rc\.tready ),
        .I4(\rc_64.state[0]_i_2_n_0 ),
        .I5(\rc_64.state[0]_i_3_n_0 ),
        .O(state[0]));
  (* SOFT_HLUTNM = "soft_lutpair1902" *) 
  LUT5 #(
    .INIT(32'h00F10000)) 
    \rc_64.state[0]_i_2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .I3(in_packet_q),
        .I4(m_axis_tvalid),
        .O(\rc_64.state[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1903" *) 
  LUT5 #(
    .INIT(32'h0020000C)) 
    \rc_64.state[0]_i_3 
       (.I0(udma_wrapper_i_241_n_0),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\rc_64.state_reg_n_0_[2] ),
        .I4(\s_axis_rc\.tready ),
        .O(\rc_64.state[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFBAAAA)) 
    \rc_64.state[1]_i_1 
       (.I0(\rc_64.state[1]_i_2_n_0 ),
        .I1(\s_axis_rc\.tready ),
        .I2(\rc_64.state[2]_i_4_n_0 ),
        .I3(udma_wrapper_i_165_n_0),
        .I4(\rc_64.state[2]_i_5_n_0 ),
        .O(state[1]));
  LUT6 #(
    .INIT(64'h0130010000300030)) 
    \rc_64.state[1]_i_2 
       (.I0(\rc_64.state[2]_i_6_n_0 ),
        .I1(\rc_64.state_reg_n_0_[2] ),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(udma_wrapper_i_241_n_0),
        .I5(\s_axis_rc\.tready ),
        .O(\rc_64.state[1]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h1F)) 
    \rc_64.state[2]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .O(\rc_64.state[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAEAAAA)) 
    \rc_64.state[2]_i_2 
       (.I0(\rc_64.state[2]_i_3_n_0 ),
        .I1(\s_axis_rc\.tready ),
        .I2(\rc_64.state[2]_i_4_n_0 ),
        .I3(udma_wrapper_i_165_n_0),
        .I4(\rc_64.state[2]_i_5_n_0 ),
        .O(state[2]));
  LUT6 #(
    .INIT(64'h000000A000300000)) 
    \rc_64.state[2]_i_3 
       (.I0(\rc_64.state[2]_i_6_n_0 ),
        .I1(udma_wrapper_i_241_n_0),
        .I2(\s_axis_rc\.tready ),
        .I3(\rc_64.state_reg_n_0_[2] ),
        .I4(Q[1]),
        .I5(Q[0]),
        .O(\rc_64.state[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1907" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \rc_64.state[2]_i_4 
       (.I0(udma_wrapper_i_170_n_4),
        .I1(udma_wrapper_i_170_n_5),
        .I2(udma_wrapper_i_166_n_7),
        .O(\rc_64.state[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1903" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.state[2]_i_5 
       (.I0(\rc_64.state_reg_n_0_[2] ),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\rc_64.state[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFEFEFEFFFEFEFEFE)) 
    \rc_64.state[2]_i_6 
       (.I0(p_0_out[44]),
        .I1(p_0_out[43]),
        .I2(p_0_out[45]),
        .I3(udma_wrapper_i_241_n_0),
        .I4(\rc_64.wr_len_reg_n_0_[1] ),
        .I5(\rc_64.wr_len_reg_n_0_[0] ),
        .O(\rc_64.state[2]_i_6_n_0 ));
  FDRE \rc_64.state_reg[0] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(state[0]),
        .Q(Q[0]),
        .R(user_reset_out));
  FDRE \rc_64.state_reg[1] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(state[1]),
        .Q(Q[1]),
        .R(user_reset_out));
  FDRE \rc_64.state_reg[2] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(state[2]),
        .Q(\rc_64.state_reg_n_0_[2] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_attr_reg[0] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_attr_reg[2]_0 [0]),
        .Q(data1[28]),
        .R(user_reset_out));
  FDRE \rc_64.wr_attr_reg[1] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_attr_reg[2]_0 [1]),
        .Q(data1[29]),
        .R(user_reset_out));
  FDRE \rc_64.wr_attr_reg[2] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_attr_reg[2]_0 [2]),
        .Q(data1[30]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[0] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [0]),
        .Q(p_0_out[16]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[10] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [10]),
        .Q(p_0_out[26]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[11] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [11]),
        .Q(p_0_out[27]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[1] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [1]),
        .Q(p_0_out[17]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[2] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [2]),
        .Q(p_0_out[18]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[3] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [3]),
        .Q(p_0_out[19]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[4] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [4]),
        .Q(p_0_out[20]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[5] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [5]),
        .Q(p_0_out[21]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[6] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [6]),
        .Q(p_0_out[22]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[7] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [7]),
        .Q(p_0_out[23]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[8] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [8]),
        .Q(p_0_out[24]),
        .R(user_reset_out));
  FDRE \rc_64.wr_byte_reg[9] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_byte_reg[11]_0 [9]),
        .Q(p_0_out[25]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[0] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [0]),
        .Q(data1[8]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[10] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [10]),
        .Q(data1[18]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[11] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [11]),
        .Q(data1[19]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[12] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [12]),
        .Q(data1[20]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[13] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [13]),
        .Q(data1[21]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[14] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [14]),
        .Q(data1[22]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[15] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [15]),
        .Q(data1[23]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[1] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [1]),
        .Q(data1[9]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[2] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [2]),
        .Q(data1[10]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[3] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [3]),
        .Q(data1[11]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[4] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [4]),
        .Q(data1[12]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[5] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [5]),
        .Q(data1[13]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[6] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [6]),
        .Q(data1[14]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[7] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [7]),
        .Q(data1[15]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[8] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [8]),
        .Q(data1[16]),
        .R(user_reset_out));
  FDRE \rc_64.wr_cid_reg[9] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_cid_reg[15]_0 [9]),
        .Q(data1[17]),
        .R(user_reset_out));
  FDRE \rc_64.wr_compl_status_reg[0] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_compl_status_reg[2]_0 [0]),
        .Q(p_0_out[43]),
        .R(user_reset_out));
  FDRE \rc_64.wr_compl_status_reg[1] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_compl_status_reg[2]_0 [1]),
        .Q(p_0_out[44]),
        .R(user_reset_out));
  FDRE \rc_64.wr_compl_status_reg[2] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_compl_status_reg[2]_0 [2]),
        .Q(p_0_out[45]),
        .R(user_reset_out));
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[32]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[55]),
        .O(\rc_64.wr_data[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1934" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[33]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[56]),
        .O(\rc_64.wr_data[33]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1934" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[34]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[57]),
        .O(\rc_64.wr_data[34]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1933" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[35]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[58]),
        .O(\rc_64.wr_data[35]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1933" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[36]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[59]),
        .O(\rc_64.wr_data[36]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1932" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[37]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[60]),
        .O(\rc_64.wr_data[37]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1932" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[38]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[61]),
        .O(\rc_64.wr_data[38]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1931" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[39]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[62]),
        .O(\rc_64.wr_data[39]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1931" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[40]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[47]),
        .O(\rc_64.wr_data[40]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1930" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[41]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[48]),
        .O(\rc_64.wr_data[41]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1930" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[42]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[49]),
        .O(\rc_64.wr_data[42]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1929" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[43]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[50]),
        .O(\rc_64.wr_data[43]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1929" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[44]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[51]),
        .O(\rc_64.wr_data[44]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1928" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[45]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[52]),
        .O(\rc_64.wr_data[45]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1928" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[46]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[53]),
        .O(\rc_64.wr_data[46]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1927" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[47]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[54]),
        .O(\rc_64.wr_data[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1927" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[48]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[39]),
        .O(\rc_64.wr_data[48]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1926" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[49]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[40]),
        .O(\rc_64.wr_data[49]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1926" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[50]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[41]),
        .O(\rc_64.wr_data[50]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1925" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[51]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[42]),
        .O(\rc_64.wr_data[51]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1925" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[52]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[43]),
        .O(\rc_64.wr_data[52]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1924" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[53]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[44]),
        .O(\rc_64.wr_data[53]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1924" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[54]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[45]),
        .O(\rc_64.wr_data[54]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1923" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[55]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[46]),
        .O(\rc_64.wr_data[55]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1923" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[56]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[31]),
        .O(\rc_64.wr_data[56]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1922" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[57]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[32]),
        .O(\rc_64.wr_data[57]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1922" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[58]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[33]),
        .O(\rc_64.wr_data[58]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1921" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[59]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[34]),
        .O(\rc_64.wr_data[59]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1921" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[60]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[35]),
        .O(\rc_64.wr_data[60]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1920" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[61]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[36]),
        .O(\rc_64.wr_data[61]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1920" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[62]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[37]),
        .O(\rc_64.wr_data[62]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1915" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_data[63]_i_1 
       (.I0(Q[1]),
        .I1(m_axis_tdata[38]),
        .O(\rc_64.wr_data[63]_i_1_n_0 ));
  FDRE \rc_64.wr_data_reg[0] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [0]),
        .Q(data1[32]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[10] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [10]),
        .Q(data1[42]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[11] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [11]),
        .Q(data1[43]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[12] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [12]),
        .Q(data1[44]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[13] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [13]),
        .Q(data1[45]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[14] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [14]),
        .Q(data1[46]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[15] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [15]),
        .Q(data1[47]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[16] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [16]),
        .Q(data1[48]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[17] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [17]),
        .Q(data1[49]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[18] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [18]),
        .Q(data1[50]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[19] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [19]),
        .Q(data1[51]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[1] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [1]),
        .Q(data1[33]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[20] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [20]),
        .Q(data1[52]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[21] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [21]),
        .Q(data1[53]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[22] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [22]),
        .Q(data1[54]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[23] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [23]),
        .Q(data1[55]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[24] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [24]),
        .Q(data1[56]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[25] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [25]),
        .Q(data1[57]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[26] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [26]),
        .Q(data1[58]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[27] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [27]),
        .Q(data1[59]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[28] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [28]),
        .Q(data1[60]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[29] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [29]),
        .Q(data1[61]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[2] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [2]),
        .Q(data1[34]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[30] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [30]),
        .Q(data1[62]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[31] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [31]),
        .Q(data1[63]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[32] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[32]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[32] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[33] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[33]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[33] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[34] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[34]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[34] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[35] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[35]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[35] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[36] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[36]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[36] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[37] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[37]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[37] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[38] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[38]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[38] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[39] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[39]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[39] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[3] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [3]),
        .Q(data1[35]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[40] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[40]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[40] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[41] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[41]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[41] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[42] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[42]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[42] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[43] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[43]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[43] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[44] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[44]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[44] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[45] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[45]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[45] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[46] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[46]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[46] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[47] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[47]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[47] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[48] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[48]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[48] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[49] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[49]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[49] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[4] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [4]),
        .Q(data1[36]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[50] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[50]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[50] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[51] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[51]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[51] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[52] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[52]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[52] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[53] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[53]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[53] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[54] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[54]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[54] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[55] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[55]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[55] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[56] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[56]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[56] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[57] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[57]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[57] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[58] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[58]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[58] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[59] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[59]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[59] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[5] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [5]),
        .Q(data1[37]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[60] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[60]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[60] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[61] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[61]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[61] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[62] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[62]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[62] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[63] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data[63]_i_1_n_0 ),
        .Q(\rc_64.wr_data_reg_n_0_[63] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[6] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [6]),
        .Q(data1[38]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[7] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [7]),
        .Q(data1[39]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[8] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [8]),
        .Q(data1[40]),
        .R(user_reset_out));
  FDRE \rc_64.wr_data_reg[9] 
       (.C(user_clk_out),
        .CE(\rc_64.state[2]_i_1_n_0 ),
        .D(\rc_64.wr_data_reg[31]_0 [9]),
        .Q(data1[41]),
        .R(user_reset_out));
  LUT6 #(
    .INIT(64'hFFFFFFEF00000020)) 
    \rc_64.wr_ep_i_1 
       (.I0(m_axis_tdata[13]),
        .I1(in_packet_q),
        .I2(m_axis_tvalid),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(p_0_out[46]),
        .O(\rc_64.wr_ep_i_1_n_0 ));
  FDRE \rc_64.wr_ep_reg 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\rc_64.wr_ep_i_1_n_0 ),
        .Q(p_0_out[46]),
        .R(user_reset_out));
  LUT2 #(
    .INIT(4'h1)) 
    \rc_64.wr_len[9]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(wr_compl_status));
  FDRE \rc_64.wr_len_reg[0] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(D[0]),
        .Q(\rc_64.wr_len_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_len_reg[1] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(D[1]),
        .Q(\rc_64.wr_len_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_len_reg[2] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(D[2]),
        .Q(\rc_64.wr_len_reg_n_0_[2] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_len_reg[3] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(D[3]),
        .Q(\rc_64.wr_len_reg_n_0_[3] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_len_reg[4] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(D[4]),
        .Q(\rc_64.wr_len_reg_n_0_[4] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_len_reg[5] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(D[5]),
        .Q(\rc_64.wr_len_reg_n_0_[5] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_len_reg[6] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(D[6]),
        .Q(\rc_64.wr_len_reg_n_0_[6] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_len_reg[7] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(D[7]),
        .Q(\rc_64.wr_len_reg_n_0_[7] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_len_reg[8] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(D[8]),
        .Q(\rc_64.wr_len_reg_n_0_[8] ),
        .R(user_reset_out));
  FDRE \rc_64.wr_len_reg[9] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(D[9]),
        .Q(\rc_64.wr_len_reg_n_0_[9] ),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair1919" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_tag[0]_i_1 
       (.I0(Q[0]),
        .I1(m_axis_tdata[7]),
        .O(p_1_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair1919" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_tag[1]_i_1 
       (.I0(Q[0]),
        .I1(m_axis_tdata[8]),
        .O(p_1_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair1918" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_tag[2]_i_1 
       (.I0(Q[0]),
        .I1(m_axis_tdata[9]),
        .O(p_1_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair1918" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_tag[3]_i_1 
       (.I0(Q[0]),
        .I1(m_axis_tdata[10]),
        .O(p_1_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair1917" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_tag[4]_i_1 
       (.I0(Q[0]),
        .I1(m_axis_tdata[11]),
        .O(p_1_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair1917" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_tag[5]_i_1 
       (.I0(Q[0]),
        .I1(m_axis_tdata[12]),
        .O(p_1_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair1916" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_tag[6]_i_1 
       (.I0(Q[0]),
        .I1(m_axis_tdata[13]),
        .O(p_1_in[6]));
  LUT3 #(
    .INIT(8'h13)) 
    \rc_64.wr_tag[7]_i_1 
       (.I0(\rc_64.state_reg_n_0_[2] ),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\rc_64.wr_tag[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1916" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rc_64.wr_tag[7]_i_2 
       (.I0(Q[0]),
        .I1(m_axis_tdata[14]),
        .O(p_1_in[7]));
  FDRE \rc_64.wr_tag_reg[0] 
       (.C(user_clk_out),
        .CE(\rc_64.wr_tag[7]_i_1_n_0 ),
        .D(p_1_in[0]),
        .Q(data1[0]),
        .R(user_reset_out));
  FDRE \rc_64.wr_tag_reg[1] 
       (.C(user_clk_out),
        .CE(\rc_64.wr_tag[7]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(data1[1]),
        .R(user_reset_out));
  FDRE \rc_64.wr_tag_reg[2] 
       (.C(user_clk_out),
        .CE(\rc_64.wr_tag[7]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(data1[2]),
        .R(user_reset_out));
  FDRE \rc_64.wr_tag_reg[3] 
       (.C(user_clk_out),
        .CE(\rc_64.wr_tag[7]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(data1[3]),
        .R(user_reset_out));
  FDRE \rc_64.wr_tag_reg[4] 
       (.C(user_clk_out),
        .CE(\rc_64.wr_tag[7]_i_1_n_0 ),
        .D(p_1_in[4]),
        .Q(data1[4]),
        .R(user_reset_out));
  FDRE \rc_64.wr_tag_reg[5] 
       (.C(user_clk_out),
        .CE(\rc_64.wr_tag[7]_i_1_n_0 ),
        .D(p_1_in[5]),
        .Q(data1[5]),
        .R(user_reset_out));
  FDRE \rc_64.wr_tag_reg[6] 
       (.C(user_clk_out),
        .CE(\rc_64.wr_tag[7]_i_1_n_0 ),
        .D(p_1_in[6]),
        .Q(data1[6]),
        .R(user_reset_out));
  FDRE \rc_64.wr_tag_reg[7] 
       (.C(user_clk_out),
        .CE(\rc_64.wr_tag[7]_i_1_n_0 ),
        .D(p_1_in[7]),
        .Q(data1[7]),
        .R(user_reset_out));
  FDRE \rc_64.wr_tc_reg[0] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_tc_reg[2]_0 [0]),
        .Q(data1[25]),
        .R(user_reset_out));
  FDRE \rc_64.wr_tc_reg[1] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_tc_reg[2]_0 [1]),
        .Q(data1[26]),
        .R(user_reset_out));
  FDRE \rc_64.wr_tc_reg[2] 
       (.C(user_clk_out),
        .CE(wr_compl_status),
        .D(\rc_64.wr_tc_reg[2]_0 [2]),
        .Q(data1[27]),
        .R(user_reset_out));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_10
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[56] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[56]),
        .I4(m_axis_tdata[23]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [56]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_11
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[55] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[55]),
        .I4(m_axis_tdata[22]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [55]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_12
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[54] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[54]),
        .I4(m_axis_tdata[21]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [54]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_13
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[53] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[53]),
        .I4(m_axis_tdata[20]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [53]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_14
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[52] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[52]),
        .I4(m_axis_tdata[19]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [52]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_15
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[51] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[51]),
        .I4(m_axis_tdata[18]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [51]));
  LUT5 #(
    .INIT(32'h00002420)) 
    udma_wrapper_i_156
       (.I0(Q[1]),
        .I1(\rc_64.state_reg_n_0_[2] ),
        .I2(Q[0]),
        .I3(udma_wrapper_i_159_n_0),
        .I4(user_reset_out),
        .O(udma_wrapper_i_156_n_0));
  LUT5 #(
    .INIT(32'h00000206)) 
    udma_wrapper_i_157
       (.I0(Q[1]),
        .I1(\rc_64.state_reg_n_0_[2] ),
        .I2(Q[0]),
        .I3(udma_wrapper_i_159_n_0),
        .I4(user_reset_out),
        .O(udma_wrapper_i_157_n_0));
  LUT4 #(
    .INIT(16'h0010)) 
    udma_wrapper_i_158
       (.I0(user_reset_out),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\rc_64.state_reg_n_0_[2] ),
        .O(udma_wrapper_i_158_n_0));
  LUT3 #(
    .INIT(8'hFD)) 
    udma_wrapper_i_159
       (.I0(\rc_64.wr_len_reg_n_0_[0] ),
        .I1(\rc_64.wr_len_reg_n_0_[1] ),
        .I2(udma_wrapper_i_241_n_0),
        .O(udma_wrapper_i_159_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_16
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[50] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[50]),
        .I4(m_axis_tdata[17]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [50]));
  (* COMPARATOR_THRESHOLD = "11" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 udma_wrapper_i_160
       (.CI(udma_wrapper_i_242_n_0),
        .CO({NLW_udma_wrapper_i_160_CO_UNCONNECTED[3:1],p_0_out__0}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,udma_wrapper_i_243_n_0}),
        .O(NLW_udma_wrapper_i_160_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,udma_wrapper_i_244_n_0}));
  (* SOFT_HLUTNM = "soft_lutpair1908" *) 
  LUT4 #(
    .INIT(16'h3008)) 
    udma_wrapper_i_161
       (.I0(udma_wrapper_i_159_n_0),
        .I1(\rc_64.state_reg_n_0_[2] ),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(udma_wrapper_i_161_n_0));
  LUT3 #(
    .INIT(8'hFE)) 
    udma_wrapper_i_162
       (.I0(p_0_out[45]),
        .I1(p_0_out[43]),
        .I2(p_0_out[44]),
        .O(p_0_out__0__0));
  LUT6 #(
    .INIT(64'h4444444444444404)) 
    udma_wrapper_i_163
       (.I0(user_reset_out),
        .I1(udma_wrapper_i_245_n_0),
        .I2(udma_wrapper_i_159_n_0),
        .I3(p_0_out[45]),
        .I4(p_0_out[43]),
        .I5(p_0_out[44]),
        .O(udma_wrapper_i_163_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1908" *) 
  LUT4 #(
    .INIT(16'h0042)) 
    udma_wrapper_i_164
       (.I0(\rc_64.state_reg_n_0_[2] ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(user_reset_out),
        .O(udma_wrapper_i_164_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1904" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    udma_wrapper_i_165
       (.I0(udma_wrapper_i_246_n_0),
        .I1(udma_wrapper_i_247_n_5),
        .I2(udma_wrapper_i_166_n_4),
        .I3(udma_wrapper_i_166_n_6),
        .O(udma_wrapper_i_165_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 udma_wrapper_i_166
       (.CI(udma_wrapper_i_170_n_0),
        .CO({udma_wrapper_i_166_n_0,udma_wrapper_i_166_n_1,udma_wrapper_i_166_n_2,udma_wrapper_i_166_n_3}),
        .CYINIT(1'b0),
        .DI({\rc_64.wr_len_reg_n_0_[7] ,\rc_64.wr_len_reg_n_0_[6] ,\rc_64.wr_len_reg_n_0_[5] ,\rc_64.wr_len_reg_n_0_[4] }),
        .O({udma_wrapper_i_166_n_4,udma_wrapper_i_166_n_5,udma_wrapper_i_166_n_6,udma_wrapper_i_166_n_7}),
        .S({udma_wrapper_i_248_n_0,udma_wrapper_i_249_n_0,udma_wrapper_i_250_n_0,udma_wrapper_i_251_n_0}));
  (* SOFT_HLUTNM = "soft_lutpair1907" *) 
  LUT4 #(
    .INIT(16'h0007)) 
    udma_wrapper_i_167
       (.I0(udma_wrapper_i_170_n_7),
        .I1(udma_wrapper_i_170_n_6),
        .I2(udma_wrapper_i_170_n_4),
        .I3(udma_wrapper_i_170_n_5),
        .O(udma_wrapper_i_167_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1901" *) 
  LUT5 #(
    .INIT(32'h00000004)) 
    udma_wrapper_i_168
       (.I0(user_reset_out),
        .I1(\rc_64.state_reg_n_0_[2] ),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(udma_wrapper_i_159_n_0),
        .O(udma_wrapper_i_168_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1900" *) 
  LUT5 #(
    .INIT(32'h01000010)) 
    udma_wrapper_i_169
       (.I0(user_reset_out),
        .I1(\rc_64.state[2]_i_4_n_0 ),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(udma_wrapper_i_169_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_17
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[49] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[49]),
        .I4(m_axis_tdata[16]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [49]));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 udma_wrapper_i_170
       (.CI(1'b0),
        .CO({udma_wrapper_i_170_n_0,udma_wrapper_i_170_n_1,udma_wrapper_i_170_n_2,udma_wrapper_i_170_n_3}),
        .CYINIT(1'b1),
        .DI({\rc_64.wr_len_reg_n_0_[3] ,\rc_64.wr_len_reg_n_0_[2] ,\rc_64.wr_len_reg_n_0_[1] ,\rc_64.wr_len_reg_n_0_[0] }),
        .O({udma_wrapper_i_170_n_4,udma_wrapper_i_170_n_5,udma_wrapper_i_170_n_6,udma_wrapper_i_170_n_7}),
        .S({udma_wrapper_i_252_n_0,udma_wrapper_i_253_n_0,udma_wrapper_i_254_n_0,udma_wrapper_i_255_n_0}));
  LUT6 #(
    .INIT(64'h0000000000041014)) 
    udma_wrapper_i_171
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .I3(p_0_out__0__0),
        .I4(udma_wrapper_i_159_n_0),
        .I5(user_reset_out),
        .O(udma_wrapper_i_171_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    udma_wrapper_i_172
       (.I0(udma_wrapper_i_170_n_5),
        .I1(udma_wrapper_i_170_n_4),
        .O(udma_wrapper_i_172_n_0));
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    udma_wrapper_i_173
       (.I0(udma_wrapper_i_246_n_0),
        .I1(udma_wrapper_i_256_n_0),
        .I2(\rc_64.state[2]_i_4_n_0 ),
        .I3(udma_wrapper_i_170_n_7),
        .I4(udma_wrapper_i_170_n_6),
        .O(s_axis_rc_tkeep0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_18
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[48] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[48]),
        .I4(m_axis_tdata[15]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [48]));
  (* SOFT_HLUTNM = "soft_lutpair1906" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_19
       (.I0(data1[47]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(\rc_64.wr_data_reg_n_0_[47] ),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [47]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_20
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[46] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[46]),
        .I4(p_0_out[46]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [46]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_21
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[45] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[45]),
        .I4(p_0_out[45]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [45]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_22
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[44] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[44]),
        .I4(p_0_out[44]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [44]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_23
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[43] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[43]),
        .I4(p_0_out[43]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [43]));
  (* SOFT_HLUTNM = "soft_lutpair1905" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_24
       (.I0(data1[42]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(\rc_64.wr_data_reg_n_0_[42] ),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [42]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    udma_wrapper_i_241
       (.I0(\rc_64.wr_len_reg_n_0_[8] ),
        .I1(\rc_64.wr_len_reg_n_0_[9] ),
        .I2(\rc_64.wr_len_reg_n_0_[3] ),
        .I3(\rc_64.wr_len_reg_n_0_[2] ),
        .I4(udma_wrapper_i_266_n_0),
        .O(udma_wrapper_i_241_n_0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 udma_wrapper_i_242
       (.CI(1'b0),
        .CO({udma_wrapper_i_242_n_0,udma_wrapper_i_242_n_1,udma_wrapper_i_242_n_2,udma_wrapper_i_242_n_3}),
        .CYINIT(udma_wrapper_i_267_n_0),
        .DI({udma_wrapper_i_268_n_0,udma_wrapper_i_269_n_0,udma_wrapper_i_270_n_0,udma_wrapper_i_271_n_0}),
        .O(NLW_udma_wrapper_i_242_O_UNCONNECTED[3:0]),
        .S({udma_wrapper_i_272_n_0,udma_wrapper_i_273_n_0,udma_wrapper_i_274_n_0,udma_wrapper_i_275_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    udma_wrapper_i_243
       (.I0(\rc_64.wr_len_reg_n_0_[8] ),
        .I1(p_0_out[26]),
        .I2(p_0_out[27]),
        .I3(\rc_64.wr_len_reg_n_0_[9] ),
        .O(udma_wrapper_i_243_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    udma_wrapper_i_244
       (.I0(p_0_out[27]),
        .I1(\rc_64.wr_len_reg_n_0_[9] ),
        .I2(p_0_out[26]),
        .I3(\rc_64.wr_len_reg_n_0_[8] ),
        .O(udma_wrapper_i_244_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1902" *) 
  LUT3 #(
    .INIT(8'h04)) 
    udma_wrapper_i_245
       (.I0(\rc_64.state_reg_n_0_[2] ),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(udma_wrapper_i_245_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    udma_wrapper_i_246
       (.I0(udma_wrapper_i_247_n_7),
        .I1(udma_wrapper_i_247_n_4),
        .I2(udma_wrapper_i_166_n_5),
        .I3(udma_wrapper_i_247_n_6),
        .O(udma_wrapper_i_246_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 udma_wrapper_i_247
       (.CI(udma_wrapper_i_166_n_0),
        .CO({NLW_udma_wrapper_i_247_CO_UNCONNECTED[3],udma_wrapper_i_247_n_1,udma_wrapper_i_247_n_2,udma_wrapper_i_247_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,\rc_64.wr_len_reg_n_0_[9] ,\rc_64.wr_len_reg_n_0_[8] }),
        .O({udma_wrapper_i_247_n_4,udma_wrapper_i_247_n_5,udma_wrapper_i_247_n_6,udma_wrapper_i_247_n_7}),
        .S({udma_wrapper_i_276_n_0,udma_wrapper_i_277_n_0,udma_wrapper_i_278_n_0,udma_wrapper_i_279_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_248
       (.I0(\rc_64.wr_len_reg_n_0_[7] ),
        .I1(current_dw_count[7]),
        .O(udma_wrapper_i_248_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_249
       (.I0(\rc_64.wr_len_reg_n_0_[6] ),
        .I1(current_dw_count[6]),
        .O(udma_wrapper_i_249_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_25
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[41] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[41]),
        .I4(\rc_64.wr_len_reg_n_0_[9] ),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [41]));
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_250
       (.I0(\rc_64.wr_len_reg_n_0_[5] ),
        .I1(current_dw_count[5]),
        .O(udma_wrapper_i_250_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_251
       (.I0(\rc_64.wr_len_reg_n_0_[4] ),
        .I1(current_dw_count[4]),
        .O(udma_wrapper_i_251_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_252
       (.I0(\rc_64.wr_len_reg_n_0_[3] ),
        .I1(current_dw_count[3]),
        .O(udma_wrapper_i_252_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_253
       (.I0(\rc_64.wr_len_reg_n_0_[2] ),
        .I1(current_dw_count[2]),
        .O(udma_wrapper_i_253_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_254
       (.I0(\rc_64.wr_len_reg_n_0_[1] ),
        .I1(current_dw_count[1]),
        .O(udma_wrapper_i_254_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_255
       (.I0(\rc_64.wr_len_reg_n_0_[0] ),
        .I1(current_dw_count[0]),
        .O(udma_wrapper_i_255_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1904" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    udma_wrapper_i_256
       (.I0(udma_wrapper_i_166_n_6),
        .I1(udma_wrapper_i_166_n_4),
        .I2(udma_wrapper_i_247_n_5),
        .O(udma_wrapper_i_256_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_26
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[40] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[40]),
        .I4(\rc_64.wr_len_reg_n_0_[8] ),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [40]));
  LUT4 #(
    .INIT(16'hFFFE)) 
    udma_wrapper_i_266
       (.I0(\rc_64.wr_len_reg_n_0_[4] ),
        .I1(\rc_64.wr_len_reg_n_0_[5] ),
        .I2(\rc_64.wr_len_reg_n_0_[6] ),
        .I3(\rc_64.wr_len_reg_n_0_[7] ),
        .O(udma_wrapper_i_266_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    udma_wrapper_i_267
       (.I0(p_0_out[17]),
        .I1(p_0_out[16]),
        .O(udma_wrapper_i_267_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    udma_wrapper_i_268
       (.I0(\rc_64.wr_len_reg_n_0_[6] ),
        .I1(p_0_out[24]),
        .I2(p_0_out[25]),
        .I3(\rc_64.wr_len_reg_n_0_[7] ),
        .O(udma_wrapper_i_268_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    udma_wrapper_i_269
       (.I0(\rc_64.wr_len_reg_n_0_[4] ),
        .I1(p_0_out[22]),
        .I2(p_0_out[23]),
        .I3(\rc_64.wr_len_reg_n_0_[5] ),
        .O(udma_wrapper_i_269_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_27
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[39] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[39]),
        .I4(\rc_64.wr_len_reg_n_0_[7] ),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [39]));
  LUT4 #(
    .INIT(16'h2F02)) 
    udma_wrapper_i_270
       (.I0(\rc_64.wr_len_reg_n_0_[2] ),
        .I1(p_0_out[20]),
        .I2(p_0_out[21]),
        .I3(\rc_64.wr_len_reg_n_0_[3] ),
        .O(udma_wrapper_i_270_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    udma_wrapper_i_271
       (.I0(\rc_64.wr_len_reg_n_0_[0] ),
        .I1(p_0_out[18]),
        .I2(p_0_out[19]),
        .I3(\rc_64.wr_len_reg_n_0_[1] ),
        .O(udma_wrapper_i_271_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    udma_wrapper_i_272
       (.I0(p_0_out[25]),
        .I1(\rc_64.wr_len_reg_n_0_[7] ),
        .I2(p_0_out[24]),
        .I3(\rc_64.wr_len_reg_n_0_[6] ),
        .O(udma_wrapper_i_272_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    udma_wrapper_i_273
       (.I0(p_0_out[23]),
        .I1(\rc_64.wr_len_reg_n_0_[5] ),
        .I2(p_0_out[22]),
        .I3(\rc_64.wr_len_reg_n_0_[4] ),
        .O(udma_wrapper_i_273_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    udma_wrapper_i_274
       (.I0(p_0_out[21]),
        .I1(\rc_64.wr_len_reg_n_0_[3] ),
        .I2(p_0_out[20]),
        .I3(\rc_64.wr_len_reg_n_0_[2] ),
        .O(udma_wrapper_i_274_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    udma_wrapper_i_275
       (.I0(p_0_out[19]),
        .I1(\rc_64.wr_len_reg_n_0_[1] ),
        .I2(p_0_out[18]),
        .I3(\rc_64.wr_len_reg_n_0_[0] ),
        .O(udma_wrapper_i_275_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    udma_wrapper_i_276
       (.I0(current_dw_count[11]),
        .O(udma_wrapper_i_276_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    udma_wrapper_i_277
       (.I0(current_dw_count[10]),
        .O(udma_wrapper_i_277_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_278
       (.I0(\rc_64.wr_len_reg_n_0_[9] ),
        .I1(current_dw_count[9]),
        .O(udma_wrapper_i_278_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_279
       (.I0(\rc_64.wr_len_reg_n_0_[8] ),
        .I1(current_dw_count[8]),
        .O(udma_wrapper_i_279_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_28
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[38] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[38]),
        .I4(\rc_64.wr_len_reg_n_0_[6] ),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [38]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_29
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[37] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[37]),
        .I4(\rc_64.wr_len_reg_n_0_[5] ),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [37]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_3
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[63] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[63]),
        .I4(m_axis_tdata[30]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [63]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_30
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[36] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[36]),
        .I4(\rc_64.wr_len_reg_n_0_[4] ),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [36]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_31
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[35] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[35]),
        .I4(\rc_64.wr_len_reg_n_0_[3] ),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [35]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_32
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[34] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[34]),
        .I4(\rc_64.wr_len_reg_n_0_[2] ),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [34]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_33
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[33] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[33]),
        .I4(\rc_64.wr_len_reg_n_0_[1] ),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [33]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_34
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[32] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[32]),
        .I4(\rc_64.wr_len_reg_n_0_[0] ),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [32]));
  LUT6 #(
    .INIT(64'h0004400000004000)) 
    udma_wrapper_i_35
       (.I0(user_reset_out),
        .I1(data1[63]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\rc_64.state_reg_n_0_[2] ),
        .I5(udma_wrapper_i_159_n_0),
        .O(\s_axis_rc\.tdata [31]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_36
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[62]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[30]),
        .I4(p_0_out__0),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [30]));
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_37
       (.I0(data1[29]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(data1[61]),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [29]));
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_38
       (.I0(data1[28]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(data1[60]),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [28]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_39
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[59]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[27]),
        .I4(p_0_out[27]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [27]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_4
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[62] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[62]),
        .I4(m_axis_tdata[29]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [62]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_40
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[58]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[26]),
        .I4(p_0_out[26]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [26]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_41
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[57]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[25]),
        .I4(p_0_out[25]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [25]));
  LUT5 #(
    .INIT(32'h8888F888)) 
    udma_wrapper_i_42
       (.I0(p_0_out[24]),
        .I1(udma_wrapper_i_158_n_0),
        .I2(udma_wrapper_i_161_n_0),
        .I3(data1[56]),
        .I4(user_reset_out),
        .O(\s_axis_rc\.tdata [24]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_43
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[55]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[23]),
        .I4(p_0_out[23]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [23]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_44
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[54]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[22]),
        .I4(p_0_out[22]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [22]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_45
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[53]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[21]),
        .I4(p_0_out[21]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [21]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_46
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[52]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[20]),
        .I4(p_0_out[20]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [20]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_47
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[51]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[19]),
        .I4(p_0_out[19]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [19]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_48
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[50]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[18]),
        .I4(p_0_out[18]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [18]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_49
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[49]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[17]),
        .I4(p_0_out[17]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [17]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_5
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[61] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[61]),
        .I4(m_axis_tdata[28]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [61]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_50
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[48]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[16]),
        .I4(p_0_out[16]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [16]));
  (* SOFT_HLUTNM = "soft_lutpair1906" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_51
       (.I0(data1[15]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(data1[47]),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [15]));
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_52
       (.I0(data1[14]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(data1[46]),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [14]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_53
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[45]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[13]),
        .I4(p_0_out__0__0),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [13]));
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_54
       (.I0(data1[12]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(data1[44]),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [12]));
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_55
       (.I0(data1[11]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(data1[43]),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [11]));
  (* SOFT_HLUTNM = "soft_lutpair1905" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_56
       (.I0(data1[10]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(data1[42]),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [10]));
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_57
       (.I0(data1[9]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(data1[41]),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [9]));
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_58
       (.I0(data1[8]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(data1[40]),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [8]));
  LUT4 #(
    .INIT(16'hF888)) 
    udma_wrapper_i_59
       (.I0(data1[7]),
        .I1(udma_wrapper_i_157_n_0),
        .I2(data1[39]),
        .I3(udma_wrapper_i_156_n_0),
        .O(\s_axis_rc\.tdata [7]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_6
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[60] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[60]),
        .I4(m_axis_tdata[27]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [60]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_60
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[38]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[6]),
        .I4(m_axis_tdata[6]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [6]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_61
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[37]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[5]),
        .I4(m_axis_tdata[5]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [5]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_62
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[36]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[4]),
        .I4(m_axis_tdata[4]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [4]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_63
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[35]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[3]),
        .I4(m_axis_tdata[3]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [3]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_64
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[34]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[2]),
        .I4(m_axis_tdata[2]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [2]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_65
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[33]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[1]),
        .I4(m_axis_tdata[1]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [1]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_66
       (.I0(udma_wrapper_i_156_n_0),
        .I1(data1[32]),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[0]),
        .I4(m_axis_tdata[0]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [0]));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAEAAAA)) 
    udma_wrapper_i_67
       (.I0(udma_wrapper_i_163_n_0),
        .I1(udma_wrapper_i_164_n_0),
        .I2(udma_wrapper_i_165_n_0),
        .I3(udma_wrapper_i_166_n_7),
        .I4(udma_wrapper_i_167_n_0),
        .I5(udma_wrapper_i_168_n_0),
        .O(\s_axis_rc\.tlast ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAEEE)) 
    udma_wrapper_i_68
       (.I0(udma_wrapper_i_163_n_0),
        .I1(udma_wrapper_i_169_n_0),
        .I2(udma_wrapper_i_170_n_6),
        .I3(udma_wrapper_i_170_n_7),
        .I4(udma_wrapper_i_165_n_0),
        .I5(udma_wrapper_i_168_n_0),
        .O(\s_axis_rc\.tuser [3]));
  (* SOFT_HLUTNM = "soft_lutpair1909" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    udma_wrapper_i_69
       (.I0(user_reset_out),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\rc_64.state_reg_n_0_[2] ),
        .O(\s_axis_rc\.tuser [2]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_7
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[59] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[59]),
        .I4(m_axis_tdata[26]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [59]));
  LUT6 #(
    .INIT(64'hFFFFFFFEAAAAAAAA)) 
    udma_wrapper_i_70
       (.I0(udma_wrapper_i_171_n_0),
        .I1(udma_wrapper_i_172_n_0),
        .I2(udma_wrapper_i_170_n_6),
        .I3(udma_wrapper_i_166_n_7),
        .I4(udma_wrapper_i_165_n_0),
        .I5(udma_wrapper_i_164_n_0),
        .O(\s_axis_rc\.tuser [1]));
  (* SOFT_HLUTNM = "soft_lutpair1901" *) 
  LUT5 #(
    .INIT(32'h03000020)) 
    udma_wrapper_i_71
       (.I0(udma_wrapper_i_159_n_0),
        .I1(user_reset_out),
        .I2(\rc_64.state_reg_n_0_[2] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\s_axis_rc\.tuser [0]));
  LUT6 #(
    .INIT(64'hAABAAAAAAABEAABA)) 
    udma_wrapper_i_72
       (.I0(udma_wrapper_i_171_n_0),
        .I1(\rc_64.state_reg_n_0_[2] ),
        .I2(Q[0]),
        .I3(user_reset_out),
        .I4(s_axis_rc_tkeep0),
        .I5(Q[1]),
        .O(\s_axis_rc\.tkeep [1]));
  (* SOFT_HLUTNM = "soft_lutpair1900" *) 
  LUT4 #(
    .INIT(16'h0056)) 
    udma_wrapper_i_73
       (.I0(\rc_64.state_reg_n_0_[2] ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(user_reset_out),
        .O(\s_axis_rc\.tkeep [0]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_8
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[58] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[58]),
        .I4(m_axis_tdata[25]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [58]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_9
       (.I0(udma_wrapper_i_156_n_0),
        .I1(\rc_64.wr_data_reg_n_0_[57] ),
        .I2(udma_wrapper_i_157_n_0),
        .I3(data1[57]),
        .I4(m_axis_tdata[24]),
        .I5(udma_wrapper_i_158_n_0),
        .O(\s_axis_rc\.tdata [57]));
endmodule

module xdma_0_dma_req
   (\pcie_dma_in\.pcie_rq_seq_num0 ,
    s_axis_tx_req_tlast,
    \FSM_sequential_tx_64.state_reg[1]_0 ,
    s_axis_tx_req_tvalid,
    tready_thrtl_reg,
    \Head_reg[23] ,
    \Head_reg[22] ,
    \Head_reg[21] ,
    \Head_reg[20] ,
    \Head_reg[19] ,
    \Head_reg[18] ,
    \Head_reg[17] ,
    \Head_reg[16] ,
    \Head_reg[31] ,
    \Head_reg[30] ,
    \Head_reg[29] ,
    \Head_reg[28] ,
    \Head_reg[27] ,
    \Head_reg[26] ,
    \tx_64.wr_data_reg[7]_0 ,
    \tx_64.wr_data_reg[4]_0 ,
    \tx_64.wr_data_reg[3]_0 ,
    \tx_64.wr_data_reg[2]_0 ,
    \tx_64.wr_data_reg[1]_0 ,
    \tx_64.wr_data_reg[0]_0 ,
    \tx_64.wr_data_reg[15]_0 ,
    \tx_64.wr_data_reg[11]_0 ,
    \tx_64.wr_data_reg[9]_0 ,
    \tx_64.wr_data_reg[8]_0 ,
    \tx_64.wr_data_reg[23]_0 ,
    \tx_64.wr_data_reg[21]_0 ,
    \tx_64.wr_data_reg[25]_0 ,
    \tx_64.wr_data_reg[24]_0 ,
    \FSM_sequential_transfer_SM_reg[1] ,
    \FSM_sequential_transfer_SM_reg[1]_0 ,
    \m_axis_rq\.tready ,
    s_axis_tx_req_tdata,
    user_reset_out,
    user_clk_out,
    s_axis_tx_tready,
    transfer_SM,
    s_axis_tx_tlast_reg,
    \m_axis_cc\.tlast ,
    s_axis_tx_tgt_tvalid,
    \tx_64.req_addr_reg[63]_0 ,
    s_axis_tx_tgt_tdata,
    s_axis_tx_tgt_tkeep,
    s_axis_tx_req_tready,
    \m_axis_rq\.tlast ,
    \m_axis_rq\.tvalid ,
    cfg_function_number_o,
    cfg_device_number_o,
    cfg_bus_number_o,
    s_axis_rq_tuser);
  output [3:0]\pcie_dma_in\.pcie_rq_seq_num0 ;
  output s_axis_tx_req_tlast;
  output \FSM_sequential_tx_64.state_reg[1]_0 ;
  output s_axis_tx_req_tvalid;
  output tready_thrtl_reg;
  output \Head_reg[23] ;
  output \Head_reg[22] ;
  output \Head_reg[21] ;
  output \Head_reg[20] ;
  output \Head_reg[19] ;
  output \Head_reg[18] ;
  output \Head_reg[17] ;
  output \Head_reg[16] ;
  output \Head_reg[31] ;
  output \Head_reg[30] ;
  output \Head_reg[29] ;
  output \Head_reg[28] ;
  output \Head_reg[27] ;
  output \Head_reg[26] ;
  output \tx_64.wr_data_reg[7]_0 ;
  output \tx_64.wr_data_reg[4]_0 ;
  output \tx_64.wr_data_reg[3]_0 ;
  output \tx_64.wr_data_reg[2]_0 ;
  output \tx_64.wr_data_reg[1]_0 ;
  output \tx_64.wr_data_reg[0]_0 ;
  output \tx_64.wr_data_reg[15]_0 ;
  output \tx_64.wr_data_reg[11]_0 ;
  output \tx_64.wr_data_reg[9]_0 ;
  output \tx_64.wr_data_reg[8]_0 ;
  output \tx_64.wr_data_reg[23]_0 ;
  output \tx_64.wr_data_reg[21]_0 ;
  output \tx_64.wr_data_reg[25]_0 ;
  output \tx_64.wr_data_reg[24]_0 ;
  output \FSM_sequential_transfer_SM_reg[1] ;
  output \FSM_sequential_transfer_SM_reg[1]_0 ;
  output \m_axis_rq\.tready ;
  output [35:0]s_axis_tx_req_tdata;
  input user_reset_out;
  input user_clk_out;
  input s_axis_tx_tready;
  input [1:0]transfer_SM;
  input s_axis_tx_tlast_reg;
  input \m_axis_cc\.tlast ;
  input s_axis_tx_tgt_tvalid;
  input [63:0]\tx_64.req_addr_reg[63]_0 ;
  input [27:0]s_axis_tx_tgt_tdata;
  input [0:0]s_axis_tx_tgt_tkeep;
  input s_axis_tx_req_tready;
  input \m_axis_rq\.tlast ;
  input \m_axis_rq\.tvalid ;
  input [2:0]cfg_function_number_o;
  input [4:0]cfg_device_number_o;
  input [7:0]cfg_bus_number_o;
  input [11:0]s_axis_rq_tuser;

  wire \FSM_sequential_transfer_SM_reg[1] ;
  wire \FSM_sequential_transfer_SM_reg[1]_0 ;
  wire \FSM_sequential_tx_64.state[0]_i_1_n_0 ;
  wire \FSM_sequential_tx_64.state[0]_i_2_n_0 ;
  wire \FSM_sequential_tx_64.state[0]_i_3_n_0 ;
  wire \FSM_sequential_tx_64.state[0]_i_4_n_0 ;
  wire \FSM_sequential_tx_64.state[0]_i_5_n_0 ;
  wire \FSM_sequential_tx_64.state[0]_i_6_n_0 ;
  wire \FSM_sequential_tx_64.state[0]_i_7_n_0 ;
  wire \FSM_sequential_tx_64.state[1]_i_1_n_0 ;
  wire \FSM_sequential_tx_64.state[1]_i_2_n_0 ;
  wire \FSM_sequential_tx_64.state[1]_i_3_n_0 ;
  wire \FSM_sequential_tx_64.state[1]_i_4_n_0 ;
  wire \FSM_sequential_tx_64.state[1]_i_5_n_0 ;
  wire \FSM_sequential_tx_64.state[1]_i_6_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_10_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_11_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_12_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_13_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_14_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_15_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_16_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_17_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_1_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_22_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_23_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_24_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_25_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_26_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_27_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_28_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_29_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_2_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_30_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_31_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_32_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_33_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_36_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_37_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_38_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_39_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_3_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_40_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_41_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_42_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_43_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_44_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_45_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_46_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_47_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_48_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_49_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_4_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_50_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_5_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_6_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_8_n_0 ;
  wire \FSM_sequential_tx_64.state[2]_i_9_n_0 ;
  wire \FSM_sequential_tx_64.state_reg[1]_0 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_18_n_2 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_18_n_3 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_18_n_5 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_18_n_6 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_18_n_7 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_19_n_0 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_19_n_1 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_19_n_2 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_19_n_3 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_19_n_4 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_19_n_5 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_19_n_6 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_19_n_7 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_20_n_1 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_20_n_2 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_20_n_3 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_21_n_2 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_21_n_3 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_34_n_0 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_34_n_1 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_34_n_2 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_34_n_3 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_7_n_0 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_7_n_1 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_7_n_2 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_7_n_3 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_7_n_4 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_7_n_5 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_7_n_6 ;
  wire \FSM_sequential_tx_64.state_reg[2]_i_7_n_7 ;
  wire \Head_reg[16] ;
  wire \Head_reg[17] ;
  wire \Head_reg[18] ;
  wire \Head_reg[19] ;
  wire \Head_reg[20] ;
  wire \Head_reg[21] ;
  wire \Head_reg[22] ;
  wire \Head_reg[23] ;
  wire \Head_reg[26] ;
  wire \Head_reg[27] ;
  wire \Head_reg[28] ;
  wire \Head_reg[29] ;
  wire \Head_reg[30] ;
  wire \Head_reg[31] ;
  wire [7:0]cfg_bus_number_o;
  wire [4:0]cfg_device_number_o;
  wire [2:0]cfg_function_number_o;
  wire [10:0]current_dw_count;
  wire [10:1]dw_count;
  wire [10:10]in26;
  wire in_packet_q;
  wire in_packet_q_i_1_n_0;
  wire \m_axis_cc\.tlast ;
  wire \m_axis_rq\.tlast ;
  wire \m_axis_rq\.tready ;
  wire \m_axis_rq\.tvalid ;
  wire [63:0]p_0_in;
  wire [39:10]p_0_out;
  wire [3:0]\pcie_dma_in\.pcie_rq_seq_num0 ;
  wire req_at;
  wire [9:0]req_len;
  wire [11:0]s_axis_rq_tuser;
  wire [35:0]s_axis_tx_req_tdata;
  wire s_axis_tx_req_tlast;
  wire s_axis_tx_req_tready;
  wire s_axis_tx_req_tvalid;
  wire \s_axis_tx_tdata[0]_i_2_n_0 ;
  wire \s_axis_tx_tdata[10]_i_5_n_0 ;
  wire \s_axis_tx_tdata[11]_i_5_n_0 ;
  wire \s_axis_tx_tdata[12]_i_5_n_0 ;
  wire \s_axis_tx_tdata[13]_i_2_n_0 ;
  wire \s_axis_tx_tdata[13]_i_3_n_0 ;
  wire \s_axis_tx_tdata[14]_i_5_n_0 ;
  wire \s_axis_tx_tdata[15]_i_2_n_0 ;
  wire \s_axis_tx_tdata[16]_i_2_n_0 ;
  wire \s_axis_tx_tdata[17]_i_2_n_0 ;
  wire \s_axis_tx_tdata[18]_i_5_n_0 ;
  wire \s_axis_tx_tdata[19]_i_2_n_0 ;
  wire \s_axis_tx_tdata[1]_i_2_n_0 ;
  wire \s_axis_tx_tdata[20]_i_5_n_0 ;
  wire \s_axis_tx_tdata[21]_i_5_n_0 ;
  wire \s_axis_tx_tdata[22]_i_5_n_0 ;
  wire \s_axis_tx_tdata[23]_i_2_n_0 ;
  wire \s_axis_tx_tdata[24]_i_2_n_0 ;
  wire \s_axis_tx_tdata[25]_i_2_n_0 ;
  wire \s_axis_tx_tdata[26]_i_2_n_0 ;
  wire \s_axis_tx_tdata[27]_i_2_n_0 ;
  wire \s_axis_tx_tdata[28]_i_2_n_0 ;
  wire \s_axis_tx_tdata[29]_i_4_n_0 ;
  wire \s_axis_tx_tdata[29]_i_5_n_0 ;
  wire \s_axis_tx_tdata[29]_i_6_n_0 ;
  wire \s_axis_tx_tdata[29]_i_7_n_0 ;
  wire \s_axis_tx_tdata[2]_i_5_n_0 ;
  wire \s_axis_tx_tdata[30]_i_5_n_0 ;
  wire \s_axis_tx_tdata[31]_i_2_n_0 ;
  wire \s_axis_tx_tdata[31]_i_3_n_0 ;
  wire \s_axis_tx_tdata[31]_i_5_n_0 ;
  wire \s_axis_tx_tdata[31]_i_6_n_0 ;
  wire \s_axis_tx_tdata[34]_i_2_n_0 ;
  wire \s_axis_tx_tdata[35]_i_2_n_0 ;
  wire \s_axis_tx_tdata[36]_i_2_n_0 ;
  wire \s_axis_tx_tdata[37]_i_2_n_0 ;
  wire \s_axis_tx_tdata[38]_i_2_n_0 ;
  wire \s_axis_tx_tdata[39]_i_2_n_0 ;
  wire \s_axis_tx_tdata[3]_i_5_n_0 ;
  wire \s_axis_tx_tdata[40]_i_2_n_0 ;
  wire \s_axis_tx_tdata[41]_i_2_n_0 ;
  wire \s_axis_tx_tdata[42]_i_2_n_0 ;
  wire \s_axis_tx_tdata[43]_i_2_n_0 ;
  wire \s_axis_tx_tdata[44]_i_2_n_0 ;
  wire \s_axis_tx_tdata[45]_i_2_n_0 ;
  wire \s_axis_tx_tdata[46]_i_2_n_0 ;
  wire \s_axis_tx_tdata[47]_i_2_n_0 ;
  wire \s_axis_tx_tdata[47]_i_3_n_0 ;
  wire \s_axis_tx_tdata[47]_i_5_n_0 ;
  wire \s_axis_tx_tdata[47]_i_6_n_0 ;
  wire \s_axis_tx_tdata[48]_i_4_n_0 ;
  wire \s_axis_tx_tdata[49]_i_4_n_0 ;
  wire \s_axis_tx_tdata[4]_i_5_n_0 ;
  wire \s_axis_tx_tdata[50]_i_4_n_0 ;
  wire \s_axis_tx_tdata[51]_i_4_n_0 ;
  wire \s_axis_tx_tdata[52]_i_4_n_0 ;
  wire \s_axis_tx_tdata[53]_i_4_n_0 ;
  wire \s_axis_tx_tdata[54]_i_4_n_0 ;
  wire \s_axis_tx_tdata[55]_i_7_n_0 ;
  wire \s_axis_tx_tdata[56]_i_5_n_0 ;
  wire \s_axis_tx_tdata[57]_i_5_n_0 ;
  wire \s_axis_tx_tdata[58]_i_5_n_0 ;
  wire \s_axis_tx_tdata[59]_i_5_n_0 ;
  wire \s_axis_tx_tdata[5]_i_5_n_0 ;
  wire \s_axis_tx_tdata[60]_i_5_n_0 ;
  wire \s_axis_tx_tdata[61]_i_5_n_0 ;
  wire \s_axis_tx_tdata[62]_i_5_n_0 ;
  wire \s_axis_tx_tdata[63]_i_7_n_0 ;
  wire \s_axis_tx_tdata[6]_i_5_n_0 ;
  wire \s_axis_tx_tdata[7]_i_4_n_0 ;
  wire \s_axis_tx_tdata[8]_i_5_n_0 ;
  wire \s_axis_tx_tdata[9]_i_5_n_0 ;
  wire [27:0]s_axis_tx_tgt_tdata;
  wire [0:0]s_axis_tx_tgt_tkeep;
  wire s_axis_tx_tgt_tvalid;
  wire [10:1]s_axis_tx_tkeep3;
  wire \s_axis_tx_tkeep[7]_i_11_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_12_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_15_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_16_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_17_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_18_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_19_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_20_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_21_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_22_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_23_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_24_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_25_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_26_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_27_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_28_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_29_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_2_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_30_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_31_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_32_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_33_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_34_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_35_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_36_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_37_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_38_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_39_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_3_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_40_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_41_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_42_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_43_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_44_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_45_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_47_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_48_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_49_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_4_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_5_n_0 ;
  wire \s_axis_tx_tkeep[7]_i_9_n_0 ;
  wire \s_axis_tx_tkeep_reg[7]_i_10_n_2 ;
  wire \s_axis_tx_tkeep_reg[7]_i_10_n_3 ;
  wire \s_axis_tx_tkeep_reg[7]_i_10_n_5 ;
  wire \s_axis_tx_tkeep_reg[7]_i_10_n_6 ;
  wire \s_axis_tx_tkeep_reg[7]_i_10_n_7 ;
  wire \s_axis_tx_tkeep_reg[7]_i_13_n_0 ;
  wire \s_axis_tx_tkeep_reg[7]_i_13_n_1 ;
  wire \s_axis_tx_tkeep_reg[7]_i_13_n_2 ;
  wire \s_axis_tx_tkeep_reg[7]_i_13_n_3 ;
  wire \s_axis_tx_tkeep_reg[7]_i_14_n_0 ;
  wire \s_axis_tx_tkeep_reg[7]_i_14_n_1 ;
  wire \s_axis_tx_tkeep_reg[7]_i_14_n_2 ;
  wire \s_axis_tx_tkeep_reg[7]_i_14_n_3 ;
  wire \s_axis_tx_tkeep_reg[7]_i_46_n_2 ;
  wire \s_axis_tx_tkeep_reg[7]_i_46_n_3 ;
  wire \s_axis_tx_tkeep_reg[7]_i_7_n_0 ;
  wire \s_axis_tx_tkeep_reg[7]_i_7_n_1 ;
  wire \s_axis_tx_tkeep_reg[7]_i_7_n_2 ;
  wire \s_axis_tx_tkeep_reg[7]_i_7_n_3 ;
  wire \s_axis_tx_tkeep_reg[7]_i_7_n_4 ;
  wire \s_axis_tx_tkeep_reg[7]_i_7_n_5 ;
  wire \s_axis_tx_tkeep_reg[7]_i_7_n_6 ;
  wire \s_axis_tx_tkeep_reg[7]_i_7_n_7 ;
  wire \s_axis_tx_tkeep_reg[7]_i_8_n_0 ;
  wire \s_axis_tx_tkeep_reg[7]_i_8_n_1 ;
  wire \s_axis_tx_tkeep_reg[7]_i_8_n_2 ;
  wire \s_axis_tx_tkeep_reg[7]_i_8_n_3 ;
  wire \s_axis_tx_tkeep_reg[7]_i_8_n_4 ;
  wire \s_axis_tx_tkeep_reg[7]_i_8_n_5 ;
  wire \s_axis_tx_tkeep_reg[7]_i_8_n_6 ;
  wire \s_axis_tx_tkeep_reg[7]_i_8_n_7 ;
  wire s_axis_tx_tlast_reg;
  wire s_axis_tx_tready;
  wire [3:0]seq_num;
  wire [2:0]state;
  wire state3;
  wire [1:0]transfer_SM;
  wire tready_thrtl_reg;
  wire \tx_64.current_dw_count[10]_i_1_n_0 ;
  wire \tx_64.current_dw_count[10]_i_3_n_0 ;
  wire \tx_64.current_dw_count[10]_i_4_n_0 ;
  wire \tx_64.current_dw_count[3]_i_2_n_0 ;
  wire \tx_64.current_dw_count[4]_i_2_n_0 ;
  wire \tx_64.current_dw_count[5]_i_2_n_0 ;
  wire \tx_64.current_dw_count[6]_i_2_n_0 ;
  wire \tx_64.current_dw_count[7]_i_2_n_0 ;
  wire \tx_64.current_dw_count[8]_i_2_n_0 ;
  wire \tx_64.current_dw_count[9]_i_2_n_0 ;
  wire \tx_64.current_dw_count_reg_n_0_[0] ;
  wire \tx_64.current_dw_count_reg_n_0_[10] ;
  wire \tx_64.current_dw_count_reg_n_0_[1] ;
  wire \tx_64.current_dw_count_reg_n_0_[2] ;
  wire \tx_64.current_dw_count_reg_n_0_[3] ;
  wire \tx_64.current_dw_count_reg_n_0_[4] ;
  wire \tx_64.current_dw_count_reg_n_0_[5] ;
  wire \tx_64.current_dw_count_reg_n_0_[6] ;
  wire \tx_64.current_dw_count_reg_n_0_[7] ;
  wire \tx_64.current_dw_count_reg_n_0_[8] ;
  wire \tx_64.current_dw_count_reg_n_0_[9] ;
  wire \tx_64.dw_count[10]_i_1_n_0 ;
  wire \tx_64.dw_count[10]_i_3_n_0 ;
  wire \tx_64.dw_count[6]_i_2_n_0 ;
  wire \tx_64.dw_count[7]_i_2_n_0 ;
  wire \tx_64.dw_count_reg_n_0_[10] ;
  wire \tx_64.dw_count_reg_n_0_[1] ;
  wire \tx_64.dw_count_reg_n_0_[2] ;
  wire \tx_64.dw_count_reg_n_0_[3] ;
  wire \tx_64.dw_count_reg_n_0_[4] ;
  wire \tx_64.dw_count_reg_n_0_[5] ;
  wire \tx_64.dw_count_reg_n_0_[6] ;
  wire \tx_64.dw_count_reg_n_0_[7] ;
  wire \tx_64.dw_count_reg_n_0_[8] ;
  wire \tx_64.dw_count_reg_n_0_[9] ;
  wire \tx_64.req_4dw_i_1_n_0 ;
  wire \tx_64.req_4dw_i_2_n_0 ;
  wire \tx_64.req_4dw_i_3_n_0 ;
  wire \tx_64.req_4dw_i_4_n_0 ;
  wire \tx_64.req_4dw_i_5_n_0 ;
  wire \tx_64.req_4dw_i_6_n_0 ;
  wire \tx_64.req_4dw_i_7_n_0 ;
  wire \tx_64.req_4dw_reg_n_0 ;
  wire [63:0]\tx_64.req_addr_reg[63]_0 ;
  wire \tx_64.req_len[9]_i_1_n_0 ;
  wire \tx_64.req_len_reg_n_0_[0] ;
  wire \tx_64.req_len_reg_n_0_[1] ;
  wire \tx_64.req_len_reg_n_0_[2] ;
  wire \tx_64.req_len_reg_n_0_[3] ;
  wire \tx_64.req_len_reg_n_0_[4] ;
  wire \tx_64.req_len_reg_n_0_[5] ;
  wire \tx_64.req_len_reg_n_0_[6] ;
  wire \tx_64.req_len_reg_n_0_[7] ;
  wire \tx_64.req_len_reg_n_0_[8] ;
  wire \tx_64.req_len_reg_n_0_[9] ;
  wire \tx_64.wr_data_reg[0]_0 ;
  wire \tx_64.wr_data_reg[11]_0 ;
  wire \tx_64.wr_data_reg[15]_0 ;
  wire \tx_64.wr_data_reg[1]_0 ;
  wire \tx_64.wr_data_reg[21]_0 ;
  wire \tx_64.wr_data_reg[23]_0 ;
  wire \tx_64.wr_data_reg[24]_0 ;
  wire \tx_64.wr_data_reg[25]_0 ;
  wire \tx_64.wr_data_reg[2]_0 ;
  wire \tx_64.wr_data_reg[3]_0 ;
  wire \tx_64.wr_data_reg[4]_0 ;
  wire \tx_64.wr_data_reg[7]_0 ;
  wire \tx_64.wr_data_reg[8]_0 ;
  wire \tx_64.wr_data_reg[9]_0 ;
  wire udma_wrapper_i_264_n_0;
  wire udma_wrapper_i_265_n_0;
  wire udma_wrapper_i_265_n_1;
  wire udma_wrapper_i_265_n_2;
  wire udma_wrapper_i_265_n_3;
  wire udma_wrapper_i_281_n_0;
  wire udma_wrapper_i_282_n_0;
  wire udma_wrapper_i_283_n_0;
  wire udma_wrapper_i_284_n_0;
  wire udma_wrapper_i_285_n_0;
  wire udma_wrapper_i_286_n_0;
  wire udma_wrapper_i_287_n_0;
  wire udma_wrapper_i_288_n_0;
  wire udma_wrapper_i_289_n_0;
  wire udma_wrapper_i_290_n_0;
  wire udma_wrapper_i_291_n_0;
  wire user_clk_out;
  wire user_reset_out;
  wire wr_data;
  wire [63:0]wreq_data_le;
  wire [3:2]\NLW_FSM_sequential_tx_64.state_reg[2]_i_18_CO_UNCONNECTED ;
  wire [3:3]\NLW_FSM_sequential_tx_64.state_reg[2]_i_18_O_UNCONNECTED ;
  wire [3:0]\NLW_FSM_sequential_tx_64.state_reg[2]_i_20_O_UNCONNECTED ;
  wire [3:2]\NLW_FSM_sequential_tx_64.state_reg[2]_i_21_CO_UNCONNECTED ;
  wire [3:0]\NLW_FSM_sequential_tx_64.state_reg[2]_i_21_O_UNCONNECTED ;
  wire [3:0]\NLW_FSM_sequential_tx_64.state_reg[2]_i_34_O_UNCONNECTED ;
  wire [3:2]\NLW_s_axis_tx_tkeep_reg[7]_i_10_CO_UNCONNECTED ;
  wire [3:3]\NLW_s_axis_tx_tkeep_reg[7]_i_10_O_UNCONNECTED ;
  wire [0:0]\NLW_s_axis_tx_tkeep_reg[7]_i_13_O_UNCONNECTED ;
  wire [3:2]\NLW_s_axis_tx_tkeep_reg[7]_i_46_CO_UNCONNECTED ;
  wire [3:3]\NLW_s_axis_tx_tkeep_reg[7]_i_46_O_UNCONNECTED ;
  wire [3:0]NLW_udma_wrapper_i_265_O_UNCONNECTED;

  LUT6 #(
    .INIT(64'h777777770F0F0F00)) 
    \FSM_sequential_transfer_SM[0]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(s_axis_tx_tready),
        .I2(transfer_SM[1]),
        .I3(s_axis_tx_tgt_tvalid),
        .I4(s_axis_tx_req_tvalid),
        .I5(transfer_SM[0]),
        .O(tready_thrtl_reg));
  (* SOFT_HLUTNM = "soft_lutpair1945" *) 
  LUT4 #(
    .INIT(16'h0332)) 
    \FSM_sequential_transfer_SM[0]_i_3 
       (.I0(state[0]),
        .I1(user_reset_out),
        .I2(state[1]),
        .I3(state[2]),
        .O(s_axis_tx_req_tvalid));
  LUT6 #(
    .INIT(64'hF0002222F0000000)) 
    \FSM_sequential_transfer_SM[1]_i_3 
       (.I0(s_axis_tx_tlast_reg),
        .I1(user_reset_out),
        .I2(s_axis_tx_req_tlast),
        .I3(s_axis_tx_req_tvalid),
        .I4(transfer_SM[1]),
        .I5(\m_axis_cc\.tlast ),
        .O(\FSM_sequential_tx_64.state_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hFEEEFFFFFEEE0000)) 
    \FSM_sequential_tx_64.state[0]_i_1 
       (.I0(\FSM_sequential_tx_64.state[0]_i_2_n_0 ),
        .I1(\FSM_sequential_tx_64.state[0]_i_3_n_0 ),
        .I2(\FSM_sequential_tx_64.state[2]_i_3_n_0 ),
        .I3(\FSM_sequential_tx_64.state[0]_i_4_n_0 ),
        .I4(\FSM_sequential_tx_64.state[2]_i_6_n_0 ),
        .I5(state[0]),
        .O(\FSM_sequential_tx_64.state[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF04550400)) 
    \FSM_sequential_tx_64.state[0]_i_2 
       (.I0(state[1]),
        .I1(\m_axis_rq\.tvalid ),
        .I2(in_packet_q),
        .I3(\FSM_sequential_tx_64.state[0]_i_5_n_0 ),
        .I4(\FSM_sequential_tx_64.state[2]_i_10_n_0 ),
        .I5(\FSM_sequential_tx_64.state[0]_i_6_n_0 ),
        .O(\FSM_sequential_tx_64.state[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000F40000000000)) 
    \FSM_sequential_tx_64.state[0]_i_3 
       (.I0(in_packet_q),
        .I1(\m_axis_rq\.tvalid ),
        .I2(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .I3(s_axis_tx_req_tready),
        .I4(state[0]),
        .I5(\FSM_sequential_tx_64.state[1]_i_6_n_0 ),
        .O(\FSM_sequential_tx_64.state[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0080808000800080)) 
    \FSM_sequential_tx_64.state[0]_i_4 
       (.I0(state[0]),
        .I1(\tx_64.req_4dw_reg_n_0 ),
        .I2(state[1]),
        .I3(state[2]),
        .I4(in_packet_q),
        .I5(\m_axis_rq\.tvalid ),
        .O(\FSM_sequential_tx_64.state[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1949" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_tx_64.state[0]_i_5 
       (.I0(state[2]),
        .I1(state[0]),
        .O(\FSM_sequential_tx_64.state[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h5500550055005D00)) 
    \FSM_sequential_tx_64.state[0]_i_6 
       (.I0(s_axis_tx_req_tready),
        .I1(\FSM_sequential_tx_64.state[0]_i_7_n_0 ),
        .I2(\FSM_sequential_tx_64.state_reg[2]_i_21_n_2 ),
        .I3(state[0]),
        .I4(state3),
        .I5(\tx_64.req_4dw_reg_n_0 ),
        .O(\FSM_sequential_tx_64.state[0]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1944" *) 
  LUT4 #(
    .INIT(16'h2F00)) 
    \FSM_sequential_tx_64.state[0]_i_7 
       (.I0(\m_axis_rq\.tvalid ),
        .I1(in_packet_q),
        .I2(state[2]),
        .I3(state[1]),
        .O(\FSM_sequential_tx_64.state[0]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \FSM_sequential_tx_64.state[1]_i_1 
       (.I0(\FSM_sequential_tx_64.state[1]_i_2_n_0 ),
        .I1(\FSM_sequential_tx_64.state[2]_i_3_n_0 ),
        .I2(\FSM_sequential_tx_64.state[1]_i_3_n_0 ),
        .I3(\FSM_sequential_tx_64.state[2]_i_6_n_0 ),
        .I4(state[1]),
        .O(\FSM_sequential_tx_64.state[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1941" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    \FSM_sequential_tx_64.state[1]_i_2 
       (.I0(state[0]),
        .I1(\tx_64.req_4dw_reg_n_0 ),
        .I2(state[2]),
        .I3(state[1]),
        .O(\FSM_sequential_tx_64.state[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEFFAEAEAEAEAE)) 
    \FSM_sequential_tx_64.state[1]_i_3 
       (.I0(\FSM_sequential_tx_64.state[1]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state[1]_i_5_n_0 ),
        .I2(\FSM_sequential_tx_64.state[2]_i_10_n_0 ),
        .I3(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .I4(state[0]),
        .I5(\FSM_sequential_tx_64.state[1]_i_6_n_0 ),
        .O(\FSM_sequential_tx_64.state[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h4444444C44444444)) 
    \FSM_sequential_tx_64.state[1]_i_4 
       (.I0(s_axis_tx_req_tready),
        .I1(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .I2(\tx_64.req_4dw_reg_n_0 ),
        .I3(\FSM_sequential_tx_64.state_reg[2]_i_21_n_2 ),
        .I4(state3),
        .I5(state[0]),
        .O(\FSM_sequential_tx_64.state[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h1000000000000000)) 
    \FSM_sequential_tx_64.state[1]_i_5 
       (.I0(state[1]),
        .I1(state[2]),
        .I2(state[0]),
        .I3(s_axis_tx_tready),
        .I4(transfer_SM[1]),
        .I5(transfer_SM[0]),
        .O(\FSM_sequential_tx_64.state[1]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1948" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \FSM_sequential_tx_64.state[1]_i_6 
       (.I0(\tx_64.req_len_reg_n_0_[1] ),
        .I1(\tx_64.req_len_reg_n_0_[0] ),
        .I2(\FSM_sequential_tx_64.state[2]_i_12_n_0 ),
        .O(\FSM_sequential_tx_64.state[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFF2FFFFFFF20000)) 
    \FSM_sequential_tx_64.state[2]_i_1 
       (.I0(\FSM_sequential_tx_64.state[2]_i_2_n_0 ),
        .I1(\FSM_sequential_tx_64.state[2]_i_3_n_0 ),
        .I2(\FSM_sequential_tx_64.state[2]_i_4_n_0 ),
        .I3(\FSM_sequential_tx_64.state[2]_i_5_n_0 ),
        .I4(\FSM_sequential_tx_64.state[2]_i_6_n_0 ),
        .I5(state[2]),
        .O(\FSM_sequential_tx_64.state[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \FSM_sequential_tx_64.state[2]_i_10 
       (.I0(\tx_64.req_addr_reg[63]_0 [11]),
        .I1(\tx_64.req_addr_reg[63]_0 [12]),
        .I2(\tx_64.req_addr_reg[63]_0 [14]),
        .I3(\tx_64.req_addr_reg[63]_0 [13]),
        .O(\FSM_sequential_tx_64.state[2]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1947" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \FSM_sequential_tx_64.state[2]_i_11 
       (.I0(\tx_64.req_4dw_reg_n_0 ),
        .I1(state3),
        .I2(\FSM_sequential_tx_64.state_reg[2]_i_21_n_2 ),
        .O(\FSM_sequential_tx_64.state[2]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_sequential_tx_64.state[2]_i_12 
       (.I0(\tx_64.req_len_reg_n_0_[2] ),
        .I1(\tx_64.req_len_reg_n_0_[3] ),
        .I2(\tx_64.req_len_reg_n_0_[8] ),
        .I3(\tx_64.req_len_reg_n_0_[9] ),
        .I4(udma_wrapper_i_282_n_0),
        .I5(\FSM_sequential_tx_64.state[2]_i_22_n_0 ),
        .O(\FSM_sequential_tx_64.state[2]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1948" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_tx_64.state[2]_i_13 
       (.I0(\tx_64.req_len_reg_n_0_[1] ),
        .I1(\tx_64.req_len_reg_n_0_[0] ),
        .O(\FSM_sequential_tx_64.state[2]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h6A95)) 
    \FSM_sequential_tx_64.state[2]_i_14 
       (.I0(\tx_64.req_len_reg_n_0_[3] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[2] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[3] ),
        .O(\FSM_sequential_tx_64.state[2]_i_14_n_0 ));
  LUT3 #(
    .INIT(8'h69)) 
    \FSM_sequential_tx_64.state[2]_i_15 
       (.I0(\tx_64.req_len_reg_n_0_[2] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[2] ),
        .O(\FSM_sequential_tx_64.state[2]_i_15_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \FSM_sequential_tx_64.state[2]_i_16 
       (.I0(\tx_64.req_len_reg_n_0_[1] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[1] ),
        .O(\FSM_sequential_tx_64.state[2]_i_16_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \FSM_sequential_tx_64.state[2]_i_17 
       (.I0(\tx_64.req_len_reg_n_0_[0] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[0] ),
        .O(\FSM_sequential_tx_64.state[2]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \FSM_sequential_tx_64.state[2]_i_2 
       (.I0(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .I1(\tx_64.req_4dw_reg_n_0 ),
        .I2(state[0]),
        .I3(s_axis_tx_tready),
        .I4(transfer_SM[1]),
        .I5(transfer_SM[0]),
        .O(\FSM_sequential_tx_64.state[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1943" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_tx_64.state[2]_i_22 
       (.I0(\tx_64.req_len_reg_n_0_[6] ),
        .I1(\tx_64.req_len_reg_n_0_[7] ),
        .O(\FSM_sequential_tx_64.state[2]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'h08000000F7FFFFFF)) 
    \FSM_sequential_tx_64.state[2]_i_23 
       (.I0(\tx_64.current_dw_count_reg_n_0_[9] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[7] ),
        .I2(\tx_64.current_dw_count[6]_i_2_n_0 ),
        .I3(\tx_64.current_dw_count_reg_n_0_[6] ),
        .I4(\tx_64.current_dw_count_reg_n_0_[8] ),
        .I5(\tx_64.current_dw_count_reg_n_0_[10] ),
        .O(\FSM_sequential_tx_64.state[2]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hAA6AAAAA55955555)) 
    \FSM_sequential_tx_64.state[2]_i_24 
       (.I0(\tx_64.req_len_reg_n_0_[9] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[8] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[6] ),
        .I3(\tx_64.current_dw_count[6]_i_2_n_0 ),
        .I4(\tx_64.current_dw_count_reg_n_0_[7] ),
        .I5(\tx_64.current_dw_count_reg_n_0_[9] ),
        .O(\FSM_sequential_tx_64.state[2]_i_24_n_0 ));
  LUT5 #(
    .INIT(32'hA6AA5955)) 
    \FSM_sequential_tx_64.state[2]_i_25 
       (.I0(\tx_64.req_len_reg_n_0_[8] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[7] ),
        .I2(\tx_64.current_dw_count[6]_i_2_n_0 ),
        .I3(\tx_64.current_dw_count_reg_n_0_[6] ),
        .I4(\tx_64.current_dw_count_reg_n_0_[8] ),
        .O(\FSM_sequential_tx_64.state[2]_i_25_n_0 ));
  LUT4 #(
    .INIT(16'hA659)) 
    \FSM_sequential_tx_64.state[2]_i_26 
       (.I0(\tx_64.req_len_reg_n_0_[7] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[6] ),
        .I2(\tx_64.current_dw_count[6]_i_2_n_0 ),
        .I3(\tx_64.current_dw_count_reg_n_0_[7] ),
        .O(\FSM_sequential_tx_64.state[2]_i_26_n_0 ));
  LUT3 #(
    .INIT(8'h96)) 
    \FSM_sequential_tx_64.state[2]_i_27 
       (.I0(\tx_64.req_len_reg_n_0_[6] ),
        .I1(\tx_64.current_dw_count[6]_i_2_n_0 ),
        .I2(\tx_64.current_dw_count_reg_n_0_[6] ),
        .O(\FSM_sequential_tx_64.state[2]_i_27_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAA95555555)) 
    \FSM_sequential_tx_64.state[2]_i_28 
       (.I0(\tx_64.req_len_reg_n_0_[5] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[4] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[2] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I4(\tx_64.current_dw_count_reg_n_0_[3] ),
        .I5(\tx_64.current_dw_count_reg_n_0_[5] ),
        .O(\FSM_sequential_tx_64.state[2]_i_28_n_0 ));
  LUT5 #(
    .INIT(32'h6AAA9555)) 
    \FSM_sequential_tx_64.state[2]_i_29 
       (.I0(\tx_64.req_len_reg_n_0_[4] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[3] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[2] ),
        .I4(\tx_64.current_dw_count_reg_n_0_[4] ),
        .O(\FSM_sequential_tx_64.state[2]_i_29_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFEA)) 
    \FSM_sequential_tx_64.state[2]_i_3 
       (.I0(\FSM_sequential_tx_64.state_reg[2]_i_7_n_5 ),
        .I1(\FSM_sequential_tx_64.state_reg[2]_i_7_n_6 ),
        .I2(\FSM_sequential_tx_64.state_reg[2]_i_7_n_7 ),
        .I3(\FSM_sequential_tx_64.state[2]_i_8_n_0 ),
        .I4(\FSM_sequential_tx_64.state[2]_i_9_n_0 ),
        .O(\FSM_sequential_tx_64.state[2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h04B0004B)) 
    \FSM_sequential_tx_64.state[2]_i_30 
       (.I0(\tx_64.dw_count[10]_i_3_n_0 ),
        .I1(\tx_64.dw_count_reg_n_0_[8] ),
        .I2(\tx_64.req_len_reg_n_0_[9] ),
        .I3(\tx_64.dw_count_reg_n_0_[10] ),
        .I4(\tx_64.dw_count_reg_n_0_[9] ),
        .O(\FSM_sequential_tx_64.state[2]_i_30_n_0 ));
  LUT6 #(
    .INIT(64'h8600001010008600)) 
    \FSM_sequential_tx_64.state[2]_i_31 
       (.I0(\tx_64.req_len_reg_n_0_[6] ),
        .I1(\FSM_sequential_tx_64.state[2]_i_39_n_0 ),
        .I2(\tx_64.dw_count_reg_n_0_[6] ),
        .I3(\FSM_sequential_tx_64.state[2]_i_40_n_0 ),
        .I4(\tx_64.req_len_reg_n_0_[7] ),
        .I5(\tx_64.dw_count_reg_n_0_[7] ),
        .O(\FSM_sequential_tx_64.state[2]_i_31_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF82000082)) 
    \FSM_sequential_tx_64.state[2]_i_32 
       (.I0(\FSM_sequential_tx_64.state[2]_i_41_n_0 ),
        .I1(\tx_64.req_len_reg_n_0_[4] ),
        .I2(\tx_64.dw_count_reg_n_0_[4] ),
        .I3(\tx_64.req_len_reg_n_0_[5] ),
        .I4(\tx_64.dw_count_reg_n_0_[5] ),
        .I5(\FSM_sequential_tx_64.state[2]_i_42_n_0 ),
        .O(\FSM_sequential_tx_64.state[2]_i_32_n_0 ));
  LUT5 #(
    .INIT(32'h00090060)) 
    \FSM_sequential_tx_64.state[2]_i_33 
       (.I0(\tx_64.req_len_reg_n_0_[2] ),
        .I1(\tx_64.dw_count_reg_n_0_[2] ),
        .I2(\tx_64.dw_count_reg_n_0_[1] ),
        .I3(\tx_64.req_len_reg_n_0_[0] ),
        .I4(\tx_64.req_len_reg_n_0_[1] ),
        .O(\FSM_sequential_tx_64.state[2]_i_33_n_0 ));
  LUT4 #(
    .INIT(16'hBF40)) 
    \FSM_sequential_tx_64.state[2]_i_35 
       (.I0(\tx_64.dw_count[10]_i_3_n_0 ),
        .I1(\tx_64.dw_count_reg_n_0_[8] ),
        .I2(\tx_64.dw_count_reg_n_0_[9] ),
        .I3(\tx_64.dw_count_reg_n_0_[10] ),
        .O(in26));
  LUT5 #(
    .INIT(32'h73071031)) 
    \FSM_sequential_tx_64.state[2]_i_36 
       (.I0(\tx_64.req_len_reg_n_0_[8] ),
        .I1(\tx_64.req_len_reg_n_0_[9] ),
        .I2(\tx_64.dw_count_reg_n_0_[8] ),
        .I3(\tx_64.dw_count[10]_i_3_n_0 ),
        .I4(\tx_64.dw_count_reg_n_0_[9] ),
        .O(\FSM_sequential_tx_64.state[2]_i_36_n_0 ));
  LUT4 #(
    .INIT(16'h5595)) 
    \FSM_sequential_tx_64.state[2]_i_37 
       (.I0(\tx_64.dw_count_reg_n_0_[10] ),
        .I1(\tx_64.dw_count_reg_n_0_[9] ),
        .I2(\tx_64.dw_count_reg_n_0_[8] ),
        .I3(\tx_64.dw_count[10]_i_3_n_0 ),
        .O(\FSM_sequential_tx_64.state[2]_i_37_n_0 ));
  LUT5 #(
    .INIT(32'h92040492)) 
    \FSM_sequential_tx_64.state[2]_i_38 
       (.I0(\tx_64.dw_count[10]_i_3_n_0 ),
        .I1(\tx_64.dw_count_reg_n_0_[8] ),
        .I2(\tx_64.req_len_reg_n_0_[8] ),
        .I3(\tx_64.req_len_reg_n_0_[9] ),
        .I4(\tx_64.dw_count_reg_n_0_[9] ),
        .O(\FSM_sequential_tx_64.state[2]_i_38_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1937" *) 
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    \FSM_sequential_tx_64.state[2]_i_39 
       (.I0(\tx_64.dw_count_reg_n_0_[4] ),
        .I1(\tx_64.dw_count_reg_n_0_[2] ),
        .I2(\tx_64.dw_count_reg_n_0_[1] ),
        .I3(\tx_64.dw_count_reg_n_0_[3] ),
        .I4(\tx_64.dw_count_reg_n_0_[5] ),
        .O(\FSM_sequential_tx_64.state[2]_i_39_n_0 ));
  LUT6 #(
    .INIT(64'h0C0A000000000000)) 
    \FSM_sequential_tx_64.state[2]_i_4 
       (.I0(\FSM_sequential_tx_64.state[2]_i_10_n_0 ),
        .I1(\FSM_sequential_tx_64.state[2]_i_11_n_0 ),
        .I2(state[2]),
        .I3(state[1]),
        .I4(s_axis_tx_req_tready),
        .I5(state[0]),
        .O(\FSM_sequential_tx_64.state[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1956" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \FSM_sequential_tx_64.state[2]_i_40 
       (.I0(\tx_64.dw_count_reg_n_0_[8] ),
        .I1(\tx_64.req_len_reg_n_0_[8] ),
        .O(\FSM_sequential_tx_64.state[2]_i_40_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1942" *) 
  LUT4 #(
    .INIT(16'h7807)) 
    \FSM_sequential_tx_64.state[2]_i_41 
       (.I0(\tx_64.dw_count_reg_n_0_[1] ),
        .I1(\tx_64.dw_count_reg_n_0_[2] ),
        .I2(\tx_64.dw_count_reg_n_0_[3] ),
        .I3(\tx_64.req_len_reg_n_0_[3] ),
        .O(\FSM_sequential_tx_64.state[2]_i_41_n_0 ));
  LUT6 #(
    .INIT(64'h0010010001000010)) 
    \FSM_sequential_tx_64.state[2]_i_42 
       (.I0(\tx_64.dw_count[7]_i_2_n_0 ),
        .I1(\tx_64.req_len_reg_n_0_[3] ),
        .I2(\tx_64.req_len_reg_n_0_[4] ),
        .I3(\tx_64.dw_count_reg_n_0_[4] ),
        .I4(\tx_64.req_len_reg_n_0_[5] ),
        .I5(\tx_64.dw_count_reg_n_0_[5] ),
        .O(\FSM_sequential_tx_64.state[2]_i_42_n_0 ));
  LUT5 #(
    .INIT(32'h73071031)) 
    \FSM_sequential_tx_64.state[2]_i_43 
       (.I0(\tx_64.req_len_reg_n_0_[6] ),
        .I1(\tx_64.req_len_reg_n_0_[7] ),
        .I2(\tx_64.dw_count_reg_n_0_[6] ),
        .I3(\FSM_sequential_tx_64.state[2]_i_39_n_0 ),
        .I4(\tx_64.dw_count_reg_n_0_[7] ),
        .O(\FSM_sequential_tx_64.state[2]_i_43_n_0 ));
  LUT6 #(
    .INIT(64'h7307737310311010)) 
    \FSM_sequential_tx_64.state[2]_i_44 
       (.I0(\tx_64.req_len_reg_n_0_[4] ),
        .I1(\tx_64.req_len_reg_n_0_[5] ),
        .I2(\tx_64.dw_count_reg_n_0_[4] ),
        .I3(\tx_64.dw_count[6]_i_2_n_0 ),
        .I4(\tx_64.dw_count_reg_n_0_[3] ),
        .I5(\tx_64.dw_count_reg_n_0_[5] ),
        .O(\FSM_sequential_tx_64.state[2]_i_44_n_0 ));
  LUT5 #(
    .INIT(32'h052B2B0A)) 
    \FSM_sequential_tx_64.state[2]_i_45 
       (.I0(\tx_64.dw_count_reg_n_0_[3] ),
        .I1(\tx_64.req_len_reg_n_0_[2] ),
        .I2(\tx_64.req_len_reg_n_0_[3] ),
        .I3(\tx_64.dw_count_reg_n_0_[2] ),
        .I4(\tx_64.dw_count_reg_n_0_[1] ),
        .O(\FSM_sequential_tx_64.state[2]_i_45_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_sequential_tx_64.state[2]_i_46 
       (.I0(\tx_64.req_len_reg_n_0_[1] ),
        .I1(\tx_64.dw_count_reg_n_0_[1] ),
        .O(\FSM_sequential_tx_64.state[2]_i_46_n_0 ));
  LUT5 #(
    .INIT(32'h90092442)) 
    \FSM_sequential_tx_64.state[2]_i_47 
       (.I0(\FSM_sequential_tx_64.state[2]_i_39_n_0 ),
        .I1(\tx_64.dw_count_reg_n_0_[6] ),
        .I2(\tx_64.req_len_reg_n_0_[7] ),
        .I3(\tx_64.dw_count_reg_n_0_[7] ),
        .I4(\tx_64.req_len_reg_n_0_[6] ),
        .O(\FSM_sequential_tx_64.state[2]_i_47_n_0 ));
  LUT6 #(
    .INIT(64'hD20000D20D20200D)) 
    \FSM_sequential_tx_64.state[2]_i_48 
       (.I0(\tx_64.dw_count_reg_n_0_[3] ),
        .I1(\tx_64.dw_count[6]_i_2_n_0 ),
        .I2(\tx_64.dw_count_reg_n_0_[4] ),
        .I3(\tx_64.req_len_reg_n_0_[5] ),
        .I4(\tx_64.dw_count_reg_n_0_[5] ),
        .I5(\tx_64.req_len_reg_n_0_[4] ),
        .O(\FSM_sequential_tx_64.state[2]_i_48_n_0 ));
  LUT5 #(
    .INIT(32'h60180681)) 
    \FSM_sequential_tx_64.state[2]_i_49 
       (.I0(\tx_64.dw_count_reg_n_0_[2] ),
        .I1(\tx_64.dw_count_reg_n_0_[1] ),
        .I2(\tx_64.dw_count_reg_n_0_[3] ),
        .I3(\tx_64.req_len_reg_n_0_[2] ),
        .I4(\tx_64.req_len_reg_n_0_[3] ),
        .O(\FSM_sequential_tx_64.state[2]_i_49_n_0 ));
  LUT6 #(
    .INIT(64'h3300330000400000)) 
    \FSM_sequential_tx_64.state[2]_i_5 
       (.I0(\FSM_sequential_tx_64.state[2]_i_12_n_0 ),
        .I1(s_axis_tx_req_tready),
        .I2(\FSM_sequential_tx_64.state[2]_i_13_n_0 ),
        .I3(state[0]),
        .I4(state[1]),
        .I5(state[2]),
        .O(\FSM_sequential_tx_64.state[2]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'h12)) 
    \FSM_sequential_tx_64.state[2]_i_50 
       (.I0(\tx_64.dw_count_reg_n_0_[1] ),
        .I1(\tx_64.req_len_reg_n_0_[0] ),
        .I2(\tx_64.req_len_reg_n_0_[1] ),
        .O(\FSM_sequential_tx_64.state[2]_i_50_n_0 ));
  LUT6 #(
    .INIT(64'h5555FFFF5555D555)) 
    \FSM_sequential_tx_64.state[2]_i_6 
       (.I0(state[2]),
        .I1(s_axis_tx_tready),
        .I2(transfer_SM[1]),
        .I3(transfer_SM[0]),
        .I4(state[1]),
        .I5(state[0]),
        .O(\FSM_sequential_tx_64.state[2]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \FSM_sequential_tx_64.state[2]_i_8 
       (.I0(\FSM_sequential_tx_64.state_reg[2]_i_18_n_7 ),
        .I1(\FSM_sequential_tx_64.state_reg[2]_i_19_n_4 ),
        .I2(\FSM_sequential_tx_64.state_reg[2]_i_18_n_5 ),
        .I3(\FSM_sequential_tx_64.state_reg[2]_i_18_n_6 ),
        .O(\FSM_sequential_tx_64.state[2]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \FSM_sequential_tx_64.state[2]_i_9 
       (.I0(\FSM_sequential_tx_64.state_reg[2]_i_19_n_7 ),
        .I1(\FSM_sequential_tx_64.state_reg[2]_i_7_n_4 ),
        .I2(\FSM_sequential_tx_64.state_reg[2]_i_19_n_5 ),
        .I3(\FSM_sequential_tx_64.state_reg[2]_i_19_n_6 ),
        .O(\FSM_sequential_tx_64.state[2]_i_9_n_0 ));
  (* FSM_ENCODED_STATES = "TX_DATA:010,TX_DATA_N:011,TX_NEW:100,TX_WAIT:101,TX_IDLE:000,TX_DW0_DW1:001" *) 
  FDRE \FSM_sequential_tx_64.state_reg[0] 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\FSM_sequential_tx_64.state[0]_i_1_n_0 ),
        .Q(state[0]),
        .R(user_reset_out));
  (* FSM_ENCODED_STATES = "TX_DATA:010,TX_DATA_N:011,TX_NEW:100,TX_WAIT:101,TX_IDLE:000,TX_DW0_DW1:001" *) 
  FDRE \FSM_sequential_tx_64.state_reg[1] 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\FSM_sequential_tx_64.state[1]_i_1_n_0 ),
        .Q(state[1]),
        .R(user_reset_out));
  (* FSM_ENCODED_STATES = "TX_DATA:010,TX_DATA_N:011,TX_NEW:100,TX_WAIT:101,TX_IDLE:000,TX_DW0_DW1:001" *) 
  FDRE \FSM_sequential_tx_64.state_reg[2] 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\FSM_sequential_tx_64.state[2]_i_1_n_0 ),
        .Q(state[2]),
        .R(user_reset_out));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \FSM_sequential_tx_64.state_reg[2]_i_18 
       (.CI(\FSM_sequential_tx_64.state_reg[2]_i_19_n_0 ),
        .CO({\NLW_FSM_sequential_tx_64.state_reg[2]_i_18_CO_UNCONNECTED [3:2],\FSM_sequential_tx_64.state_reg[2]_i_18_n_2 ,\FSM_sequential_tx_64.state_reg[2]_i_18_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,\tx_64.req_len_reg_n_0_[9] ,\tx_64.req_len_reg_n_0_[8] }),
        .O({\NLW_FSM_sequential_tx_64.state_reg[2]_i_18_O_UNCONNECTED [3],\FSM_sequential_tx_64.state_reg[2]_i_18_n_5 ,\FSM_sequential_tx_64.state_reg[2]_i_18_n_6 ,\FSM_sequential_tx_64.state_reg[2]_i_18_n_7 }),
        .S({1'b0,\FSM_sequential_tx_64.state[2]_i_23_n_0 ,\FSM_sequential_tx_64.state[2]_i_24_n_0 ,\FSM_sequential_tx_64.state[2]_i_25_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \FSM_sequential_tx_64.state_reg[2]_i_19 
       (.CI(\FSM_sequential_tx_64.state_reg[2]_i_7_n_0 ),
        .CO({\FSM_sequential_tx_64.state_reg[2]_i_19_n_0 ,\FSM_sequential_tx_64.state_reg[2]_i_19_n_1 ,\FSM_sequential_tx_64.state_reg[2]_i_19_n_2 ,\FSM_sequential_tx_64.state_reg[2]_i_19_n_3 }),
        .CYINIT(1'b0),
        .DI({\tx_64.req_len_reg_n_0_[7] ,\tx_64.req_len_reg_n_0_[6] ,\tx_64.req_len_reg_n_0_[5] ,\tx_64.req_len_reg_n_0_[4] }),
        .O({\FSM_sequential_tx_64.state_reg[2]_i_19_n_4 ,\FSM_sequential_tx_64.state_reg[2]_i_19_n_5 ,\FSM_sequential_tx_64.state_reg[2]_i_19_n_6 ,\FSM_sequential_tx_64.state_reg[2]_i_19_n_7 }),
        .S({\FSM_sequential_tx_64.state[2]_i_26_n_0 ,\FSM_sequential_tx_64.state[2]_i_27_n_0 ,\FSM_sequential_tx_64.state[2]_i_28_n_0 ,\FSM_sequential_tx_64.state[2]_i_29_n_0 }));
  CARRY4 \FSM_sequential_tx_64.state_reg[2]_i_20 
       (.CI(1'b0),
        .CO({state3,\FSM_sequential_tx_64.state_reg[2]_i_20_n_1 ,\FSM_sequential_tx_64.state_reg[2]_i_20_n_2 ,\FSM_sequential_tx_64.state_reg[2]_i_20_n_3 }),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\NLW_FSM_sequential_tx_64.state_reg[2]_i_20_O_UNCONNECTED [3:0]),
        .S({\FSM_sequential_tx_64.state[2]_i_30_n_0 ,\FSM_sequential_tx_64.state[2]_i_31_n_0 ,\FSM_sequential_tx_64.state[2]_i_32_n_0 ,\FSM_sequential_tx_64.state[2]_i_33_n_0 }));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 \FSM_sequential_tx_64.state_reg[2]_i_21 
       (.CI(\FSM_sequential_tx_64.state_reg[2]_i_34_n_0 ),
        .CO({\NLW_FSM_sequential_tx_64.state_reg[2]_i_21_CO_UNCONNECTED [3:2],\FSM_sequential_tx_64.state_reg[2]_i_21_n_2 ,\FSM_sequential_tx_64.state_reg[2]_i_21_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,in26,\FSM_sequential_tx_64.state[2]_i_36_n_0 }),
        .O(\NLW_FSM_sequential_tx_64.state_reg[2]_i_21_O_UNCONNECTED [3:0]),
        .S({1'b0,1'b0,\FSM_sequential_tx_64.state[2]_i_37_n_0 ,\FSM_sequential_tx_64.state[2]_i_38_n_0 }));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 \FSM_sequential_tx_64.state_reg[2]_i_34 
       (.CI(1'b0),
        .CO({\FSM_sequential_tx_64.state_reg[2]_i_34_n_0 ,\FSM_sequential_tx_64.state_reg[2]_i_34_n_1 ,\FSM_sequential_tx_64.state_reg[2]_i_34_n_2 ,\FSM_sequential_tx_64.state_reg[2]_i_34_n_3 }),
        .CYINIT(1'b0),
        .DI({\FSM_sequential_tx_64.state[2]_i_43_n_0 ,\FSM_sequential_tx_64.state[2]_i_44_n_0 ,\FSM_sequential_tx_64.state[2]_i_45_n_0 ,\FSM_sequential_tx_64.state[2]_i_46_n_0 }),
        .O(\NLW_FSM_sequential_tx_64.state_reg[2]_i_34_O_UNCONNECTED [3:0]),
        .S({\FSM_sequential_tx_64.state[2]_i_47_n_0 ,\FSM_sequential_tx_64.state[2]_i_48_n_0 ,\FSM_sequential_tx_64.state[2]_i_49_n_0 ,\FSM_sequential_tx_64.state[2]_i_50_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \FSM_sequential_tx_64.state_reg[2]_i_7 
       (.CI(1'b0),
        .CO({\FSM_sequential_tx_64.state_reg[2]_i_7_n_0 ,\FSM_sequential_tx_64.state_reg[2]_i_7_n_1 ,\FSM_sequential_tx_64.state_reg[2]_i_7_n_2 ,\FSM_sequential_tx_64.state_reg[2]_i_7_n_3 }),
        .CYINIT(1'b1),
        .DI({\tx_64.req_len_reg_n_0_[3] ,\tx_64.req_len_reg_n_0_[2] ,\tx_64.req_len_reg_n_0_[1] ,\tx_64.req_len_reg_n_0_[0] }),
        .O({\FSM_sequential_tx_64.state_reg[2]_i_7_n_4 ,\FSM_sequential_tx_64.state_reg[2]_i_7_n_5 ,\FSM_sequential_tx_64.state_reg[2]_i_7_n_6 ,\FSM_sequential_tx_64.state_reg[2]_i_7_n_7 }),
        .S({\FSM_sequential_tx_64.state[2]_i_14_n_0 ,\FSM_sequential_tx_64.state[2]_i_15_n_0 ,\FSM_sequential_tx_64.state[2]_i_16_n_0 ,\FSM_sequential_tx_64.state[2]_i_17_n_0 }));
  LUT5 #(
    .INIT(32'h05444444)) 
    in_packet_q_i_1
       (.I0(user_reset_out),
        .I1(in_packet_q),
        .I2(\m_axis_rq\.tlast ),
        .I3(\m_axis_rq\.tvalid ),
        .I4(s_axis_tx_req_tready),
        .O(in_packet_q_i_1_n_0));
  FDRE in_packet_q_reg
       (.C(user_clk_out),
        .CE(1'b1),
        .D(in_packet_q_i_1_n_0),
        .Q(in_packet_q),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[0]_i_1 
       (.I0(wreq_data_le[0]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[0]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[0]),
        .O(\tx_64.wr_data_reg[24]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[0]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [0]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[0]),
        .I4(wreq_data_le[32]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[10]_i_3 
       (.I0(\s_axis_tx_tdata[10]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[42]),
        .I3(wreq_data_le[10]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[8]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[10]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(p_0_out[10]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[42]),
        .I4(p_0_in[10]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[10]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[11]_i_3 
       (.I0(\s_axis_tx_tdata[11]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[43]),
        .I3(wreq_data_le[11]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[9]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[11]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(p_0_out[11]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[43]),
        .I4(p_0_in[11]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[11]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[12]_i_3 
       (.I0(\s_axis_tx_tdata[12]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[44]),
        .I3(wreq_data_le[12]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[10]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[12]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [60]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[44]),
        .I4(p_0_in[12]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[12]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFEEEFFFFFEEE0000)) 
    \s_axis_tx_tdata[13]_i_1 
       (.I0(\s_axis_tx_tdata[13]_i_2_n_0 ),
        .I1(\s_axis_tx_tdata[13]_i_3_n_0 ),
        .I2(wreq_data_le[13]),
        .I3(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I4(transfer_SM[1]),
        .I5(s_axis_tx_tgt_tdata[2]),
        .O(\tx_64.wr_data_reg[21]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[13]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [61]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[45]),
        .I4(p_0_in[13]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000001800000000)) 
    \s_axis_tx_tdata[13]_i_3 
       (.I0(state[0]),
        .I1(state[1]),
        .I2(state[2]),
        .I3(\tx_64.req_4dw_reg_n_0 ),
        .I4(user_reset_out),
        .I5(wreq_data_le[45]),
        .O(\s_axis_tx_tdata[13]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[14]_i_3 
       (.I0(\s_axis_tx_tdata[14]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[46]),
        .I3(wreq_data_le[14]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[11]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[14]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [15]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[46]),
        .I4(p_0_in[14]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[14]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[15]_i_1 
       (.I0(wreq_data_le[15]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[15]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[3]),
        .O(\tx_64.wr_data_reg[23]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[15]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I1(p_0_in[47]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[15]),
        .I4(wreq_data_le[47]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[15]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[16]_i_1 
       (.I0(wreq_data_le[16]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[16]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[4]),
        .O(\tx_64.wr_data_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[16]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I1(p_0_in[48]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[16]),
        .I4(wreq_data_le[48]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[16]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[17]_i_1 
       (.I0(wreq_data_le[17]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[17]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[5]),
        .O(\tx_64.wr_data_reg[9]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[17]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I1(p_0_in[49]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[17]),
        .I4(wreq_data_le[49]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[17]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[18]_i_3 
       (.I0(\s_axis_tx_tdata[18]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[50]),
        .I3(wreq_data_le[18]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[12]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[18]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [62]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[50]),
        .I4(p_0_in[18]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[18]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[19]_i_1 
       (.I0(wreq_data_le[19]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[19]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[6]),
        .O(\tx_64.wr_data_reg[11]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[19]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I1(p_0_in[51]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[19]),
        .I4(wreq_data_le[51]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[19]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[1]_i_1 
       (.I0(wreq_data_le[1]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[1]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[1]),
        .O(\tx_64.wr_data_reg[25]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[1]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [1]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[1]),
        .I4(wreq_data_le[33]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[20]_i_3 
       (.I0(\s_axis_tx_tdata[20]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[52]),
        .I3(wreq_data_le[20]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[13]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[20]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [57]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[52]),
        .I4(p_0_in[20]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[20]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[21]_i_3 
       (.I0(\s_axis_tx_tdata[21]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[53]),
        .I3(wreq_data_le[21]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[14]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[21]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [58]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[53]),
        .I4(p_0_in[21]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[21]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[22]_i_3 
       (.I0(\s_axis_tx_tdata[22]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[54]),
        .I3(wreq_data_le[22]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[15]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[22]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [59]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[54]),
        .I4(p_0_in[22]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[22]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[23]_i_1 
       (.I0(wreq_data_le[23]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[23]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[7]),
        .O(\tx_64.wr_data_reg[15]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[23]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I1(p_0_in[55]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[23]),
        .I4(wreq_data_le[55]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[23]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[24]_i_1 
       (.I0(wreq_data_le[24]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[24]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[8]),
        .O(\tx_64.wr_data_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[24]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I1(p_0_in[56]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[24]),
        .I4(wreq_data_le[56]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[24]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[25]_i_1 
       (.I0(wreq_data_le[25]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[25]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[9]),
        .O(\tx_64.wr_data_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[25]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I1(p_0_in[57]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[25]),
        .I4(wreq_data_le[57]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[25]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[26]_i_1 
       (.I0(wreq_data_le[26]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[26]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[10]),
        .O(\tx_64.wr_data_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[26]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I1(p_0_in[58]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[26]),
        .I4(wreq_data_le[58]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[26]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[27]_i_1 
       (.I0(wreq_data_le[27]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[27]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[11]),
        .O(\tx_64.wr_data_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[27]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I1(p_0_in[59]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[27]),
        .I4(wreq_data_le[59]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[27]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[28]_i_1 
       (.I0(wreq_data_le[28]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[28]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[12]),
        .O(\tx_64.wr_data_reg[4]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[28]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I1(p_0_in[60]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[28]),
        .I4(wreq_data_le[60]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[28]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFEA)) 
    \s_axis_tx_tdata[29]_i_3 
       (.I0(\s_axis_tx_tdata[29]_i_4_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[61]),
        .I3(\s_axis_tx_tdata[29]_i_5_n_0 ),
        .I4(\s_axis_tx_tdata[29]_i_6_n_0 ),
        .O(s_axis_tx_req_tdata[16]));
  LUT6 #(
    .INIT(64'h88F8888888888888)) 
    \s_axis_tx_tdata[29]_i_4 
       (.I0(p_0_in[61]),
        .I1(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I2(\s_axis_tx_tdata[29]_i_7_n_0 ),
        .I3(state[1]),
        .I4(state[0]),
        .I5(p_0_in[29]),
        .O(\s_axis_tx_tdata[29]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000040000000808)) 
    \s_axis_tx_tdata[29]_i_5 
       (.I0(state[0]),
        .I1(\tx_64.req_4dw_reg_n_0 ),
        .I2(user_reset_out),
        .I3(p_0_in[29]),
        .I4(state[2]),
        .I5(state[1]),
        .O(\s_axis_tx_tdata[29]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000080000004800)) 
    \s_axis_tx_tdata[29]_i_6 
       (.I0(state[0]),
        .I1(\tx_64.req_4dw_reg_n_0 ),
        .I2(state[2]),
        .I3(wreq_data_le[29]),
        .I4(user_reset_out),
        .I5(state[1]),
        .O(\s_axis_tx_tdata[29]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1947" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \s_axis_tx_tdata[29]_i_7 
       (.I0(\tx_64.req_4dw_reg_n_0 ),
        .I1(user_reset_out),
        .O(\s_axis_tx_tdata[29]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[2]_i_3 
       (.I0(\s_axis_tx_tdata[2]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[34]),
        .I3(wreq_data_le[2]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[0]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[2]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [2]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[34]),
        .I4(p_0_in[2]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[2]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[30]_i_3 
       (.I0(\s_axis_tx_tdata[30]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[62]),
        .I3(wreq_data_le[30]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[17]));
  LUT6 #(
    .INIT(64'hFFFFF222F222F222)) 
    \s_axis_tx_tdata[30]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\FSM_sequential_tx_64.state[2]_i_10_n_0 ),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[62]),
        .I4(p_0_in[30]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[30]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[31]_i_1 
       (.I0(wreq_data_le[31]),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[31]_i_3_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[13]),
        .O(\tx_64.wr_data_reg[7]_0 ));
  LUT5 #(
    .INIT(32'h04000040)) 
    \s_axis_tx_tdata[31]_i_2 
       (.I0(user_reset_out),
        .I1(\tx_64.req_4dw_reg_n_0 ),
        .I2(state[2]),
        .I3(state[1]),
        .I4(state[0]),
        .O(\s_axis_tx_tdata[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[31]_i_3 
       (.I0(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I1(p_0_in[63]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[31]),
        .I4(wreq_data_le[63]),
        .I5(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[31]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00100100)) 
    \s_axis_tx_tdata[31]_i_5 
       (.I0(user_reset_out),
        .I1(\tx_64.req_4dw_reg_n_0 ),
        .I2(state[2]),
        .I3(state[1]),
        .I4(state[0]),
        .O(\s_axis_tx_tdata[31]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h01000010)) 
    \s_axis_tx_tdata[31]_i_6 
       (.I0(user_reset_out),
        .I1(\tx_64.req_4dw_reg_n_0 ),
        .I2(state[2]),
        .I3(state[1]),
        .I4(state[0]),
        .O(\s_axis_tx_tdata[31]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[32]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(p_0_out[32]),
        .I2(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I3(wreq_data_le[32]),
        .I4(\tx_64.req_addr_reg[63]_0 [24]),
        .I5(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[18]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[33]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(p_0_out[33]),
        .I2(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I3(wreq_data_le[33]),
        .I4(\tx_64.req_addr_reg[63]_0 [25]),
        .I5(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[19]));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[34]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [26]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[34]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[14]),
        .O(\Head_reg[26] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[34]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(p_0_out[34]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[34]),
        .I4(wreq_data_le[34]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[34]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[35]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [27]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[35]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[15]),
        .O(\Head_reg[27] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[35]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(p_0_out[35]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[35]),
        .I4(wreq_data_le[35]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[35]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[36]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [28]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[36]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[16]),
        .O(\Head_reg[28] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[36]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(p_0_out[36]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[36]),
        .I4(wreq_data_le[36]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[36]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[37]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [29]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[37]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[17]),
        .O(\Head_reg[29] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[37]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(p_0_out[37]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[37]),
        .I4(wreq_data_le[37]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[37]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[38]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [30]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[38]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[18]),
        .O(\Head_reg[30] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[38]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(p_0_out[38]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[38]),
        .I4(wreq_data_le[38]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[38]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[39]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [31]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[39]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[19]),
        .O(\Head_reg[31] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[39]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(p_0_out[39]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[39]),
        .I4(wreq_data_le[39]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[39]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[3]_i_3 
       (.I0(\s_axis_tx_tdata[3]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[35]),
        .I3(wreq_data_le[3]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[1]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[3]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [3]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[35]),
        .I4(p_0_in[3]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[3]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[40]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [16]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[40]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[20]),
        .O(\Head_reg[16] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[40]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [32]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[40]),
        .I4(wreq_data_le[40]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[40]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[41]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [17]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[41]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[21]),
        .O(\Head_reg[17] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[41]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [33]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[41]),
        .I4(wreq_data_le[41]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[41]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[42]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [18]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[42]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[22]),
        .O(\Head_reg[18] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[42]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [34]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[42]),
        .I4(wreq_data_le[42]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[42]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[43]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [19]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[43]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[23]),
        .O(\Head_reg[19] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[43]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [35]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[43]),
        .I4(wreq_data_le[43]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[43]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[44]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [20]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[44]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[24]),
        .O(\Head_reg[20] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[44]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [36]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[44]),
        .I4(wreq_data_le[44]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[44]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[45]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [21]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[45]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[25]),
        .O(\Head_reg[21] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[45]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [37]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[45]),
        .I4(wreq_data_le[45]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[45]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[46]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [22]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[46]_i_2_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[26]),
        .O(\Head_reg[22] ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[46]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [38]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[46]),
        .I4(wreq_data_le[46]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[46]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \s_axis_tx_tdata[47]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [23]),
        .I1(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .I2(\s_axis_tx_tdata[47]_i_3_n_0 ),
        .I3(transfer_SM[1]),
        .I4(s_axis_tx_tgt_tdata[27]),
        .O(\Head_reg[23] ));
  LUT5 #(
    .INIT(32'h00100110)) 
    \s_axis_tx_tdata[47]_i_2 
       (.I0(user_reset_out),
        .I1(\tx_64.req_4dw_reg_n_0 ),
        .I2(state[1]),
        .I3(state[2]),
        .I4(state[0]),
        .O(\s_axis_tx_tdata[47]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[47]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [39]),
        .I2(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .I3(p_0_in[47]),
        .I4(wreq_data_le[47]),
        .I5(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(\s_axis_tx_tdata[47]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \s_axis_tx_tdata[47]_i_5 
       (.I0(user_reset_out),
        .I1(state[1]),
        .I2(state[0]),
        .I3(state[2]),
        .O(\s_axis_tx_tdata[47]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h00400400)) 
    \s_axis_tx_tdata[47]_i_6 
       (.I0(user_reset_out),
        .I1(\tx_64.req_4dw_reg_n_0 ),
        .I2(state[2]),
        .I3(state[1]),
        .I4(state[0]),
        .O(\s_axis_tx_tdata[47]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[48]_i_3 
       (.I0(\s_axis_tx_tdata[48]_i_4_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[48]),
        .I3(\tx_64.req_addr_reg[63]_0 [8]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[20]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[48]_i_4 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_function_number_o[0]),
        .I3(\tx_64.req_addr_reg[63]_0 [16]),
        .I4(p_0_in[48]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[48]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[49]_i_3 
       (.I0(\s_axis_tx_tdata[49]_i_4_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[49]),
        .I3(\tx_64.req_addr_reg[63]_0 [9]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[21]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[49]_i_4 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_function_number_o[1]),
        .I3(\tx_64.req_addr_reg[63]_0 [17]),
        .I4(p_0_in[49]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[49]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[4]_i_3 
       (.I0(\s_axis_tx_tdata[4]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[36]),
        .I3(wreq_data_le[4]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[2]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[4]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [4]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[36]),
        .I4(p_0_in[4]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[4]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[50]_i_3 
       (.I0(\s_axis_tx_tdata[50]_i_4_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[50]),
        .I3(\tx_64.req_addr_reg[63]_0 [10]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[22]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[50]_i_4 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_function_number_o[2]),
        .I3(\tx_64.req_addr_reg[63]_0 [18]),
        .I4(p_0_in[50]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[50]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[51]_i_3 
       (.I0(\s_axis_tx_tdata[51]_i_4_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[51]),
        .I3(\tx_64.req_addr_reg[63]_0 [11]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[23]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[51]_i_4 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_device_number_o[0]),
        .I3(\tx_64.req_addr_reg[63]_0 [19]),
        .I4(p_0_in[51]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[51]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[52]_i_3 
       (.I0(\s_axis_tx_tdata[52]_i_4_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[52]),
        .I3(\tx_64.req_addr_reg[63]_0 [12]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[24]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[52]_i_4 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_device_number_o[1]),
        .I3(\tx_64.req_addr_reg[63]_0 [20]),
        .I4(p_0_in[52]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[52]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[53]_i_3 
       (.I0(\s_axis_tx_tdata[53]_i_4_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[53]),
        .I3(\tx_64.req_addr_reg[63]_0 [13]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[25]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[53]_i_4 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_device_number_o[2]),
        .I3(\tx_64.req_addr_reg[63]_0 [21]),
        .I4(p_0_in[53]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[53]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[54]_i_3 
       (.I0(\s_axis_tx_tdata[54]_i_4_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[54]),
        .I3(\tx_64.req_addr_reg[63]_0 [14]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[26]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[54]_i_4 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_device_number_o[3]),
        .I3(\tx_64.req_addr_reg[63]_0 [22]),
        .I4(p_0_in[54]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[54]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[55]_i_3 
       (.I0(\s_axis_tx_tdata[55]_i_7_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[55]),
        .I3(\tx_64.req_addr_reg[63]_0 [15]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[27]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[55]_i_7 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_device_number_o[4]),
        .I3(\tx_64.req_addr_reg[63]_0 [23]),
        .I4(p_0_in[55]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[55]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[56]_i_3 
       (.I0(\s_axis_tx_tdata[56]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[56]),
        .I3(\tx_64.req_addr_reg[63]_0 [0]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[28]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[56]_i_5 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_bus_number_o[0]),
        .I3(\tx_64.req_addr_reg[63]_0 [24]),
        .I4(p_0_in[56]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[56]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[57]_i_3 
       (.I0(\s_axis_tx_tdata[57]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[57]),
        .I3(\tx_64.req_addr_reg[63]_0 [1]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[29]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[57]_i_5 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_bus_number_o[1]),
        .I3(\tx_64.req_addr_reg[63]_0 [25]),
        .I4(p_0_in[57]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[57]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[58]_i_3 
       (.I0(\s_axis_tx_tdata[58]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[58]),
        .I3(\tx_64.req_addr_reg[63]_0 [2]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[30]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[58]_i_5 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_bus_number_o[2]),
        .I3(\tx_64.req_addr_reg[63]_0 [26]),
        .I4(p_0_in[58]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[58]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[59]_i_3 
       (.I0(\s_axis_tx_tdata[59]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[59]),
        .I3(\tx_64.req_addr_reg[63]_0 [3]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[31]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[59]_i_5 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_bus_number_o[3]),
        .I3(\tx_64.req_addr_reg[63]_0 [27]),
        .I4(p_0_in[59]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[59]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[5]_i_3 
       (.I0(\s_axis_tx_tdata[5]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[37]),
        .I3(wreq_data_le[5]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[3]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[5]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [5]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[37]),
        .I4(p_0_in[5]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[5]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[60]_i_3 
       (.I0(\s_axis_tx_tdata[60]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[60]),
        .I3(\tx_64.req_addr_reg[63]_0 [4]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[32]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[60]_i_5 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_bus_number_o[4]),
        .I3(\tx_64.req_addr_reg[63]_0 [28]),
        .I4(p_0_in[60]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[60]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[61]_i_3 
       (.I0(\s_axis_tx_tdata[61]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[61]),
        .I3(\tx_64.req_addr_reg[63]_0 [5]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[33]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[61]_i_5 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_bus_number_o[5]),
        .I3(\tx_64.req_addr_reg[63]_0 [29]),
        .I4(p_0_in[61]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[61]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[62]_i_3 
       (.I0(\s_axis_tx_tdata[62]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[62]),
        .I3(\tx_64.req_addr_reg[63]_0 [6]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[34]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[62]_i_5 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_bus_number_o[6]),
        .I3(\tx_64.req_addr_reg[63]_0 [30]),
        .I4(p_0_in[62]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[62]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[63]_i_5 
       (.I0(\s_axis_tx_tdata[63]_i_7_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .I2(wreq_data_le[63]),
        .I3(\tx_64.req_addr_reg[63]_0 [7]),
        .I4(\s_axis_tx_tdata[47]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[35]));
  LUT6 #(
    .INIT(64'hFFFFC840C840C840)) 
    \s_axis_tx_tdata[63]_i_7 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I2(cfg_bus_number_o[7]),
        .I3(\tx_64.req_addr_reg[63]_0 [31]),
        .I4(p_0_in[63]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[63]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[6]_i_3 
       (.I0(\s_axis_tx_tdata[6]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[38]),
        .I3(wreq_data_le[6]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[4]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[6]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [6]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[38]),
        .I4(p_0_in[6]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[6]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[7]_i_3 
       (.I0(\s_axis_tx_tdata[7]_i_4_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[39]),
        .I3(wreq_data_le[7]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[5]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[7]_i_4 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [7]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[39]),
        .I4(p_0_in[7]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[7]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[8]_i_3 
       (.I0(\s_axis_tx_tdata[8]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[40]),
        .I3(wreq_data_le[8]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[6]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[8]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [8]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[40]),
        .I4(p_0_in[8]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[8]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \s_axis_tx_tdata[9]_i_3 
       (.I0(\s_axis_tx_tdata[9]_i_5_n_0 ),
        .I1(\s_axis_tx_tdata[31]_i_6_n_0 ),
        .I2(wreq_data_le[41]),
        .I3(wreq_data_le[9]),
        .I4(\s_axis_tx_tdata[31]_i_2_n_0 ),
        .O(s_axis_tx_req_tdata[7]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[9]_i_5 
       (.I0(\s_axis_tx_tdata[47]_i_5_n_0 ),
        .I1(\tx_64.req_addr_reg[63]_0 [9]),
        .I2(\s_axis_tx_tdata[31]_i_5_n_0 ),
        .I3(p_0_in[41]),
        .I4(p_0_in[9]),
        .I5(\s_axis_tx_tdata[47]_i_6_n_0 ),
        .O(\s_axis_tx_tdata[9]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFE0000)) 
    \s_axis_tx_tkeep[7]_i_1 
       (.I0(\s_axis_tx_tkeep[7]_i_2_n_0 ),
        .I1(\s_axis_tx_tkeep[7]_i_3_n_0 ),
        .I2(\s_axis_tx_tkeep[7]_i_4_n_0 ),
        .I3(\s_axis_tx_tkeep[7]_i_5_n_0 ),
        .I4(transfer_SM[1]),
        .I5(s_axis_tx_tgt_tkeep),
        .O(\FSM_sequential_transfer_SM_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair1945" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \s_axis_tx_tkeep[7]_i_11 
       (.I0(state[0]),
        .I1(state[2]),
        .I2(user_reset_out),
        .O(\s_axis_tx_tkeep[7]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_12 
       (.I0(\tx_64.req_len_reg_n_0_[0] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[0] ),
        .O(\s_axis_tx_tkeep[7]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h00000E3C0000023C)) 
    \s_axis_tx_tkeep[7]_i_15 
       (.I0(\s_axis_tx_tkeep_reg[7]_i_7_n_5 ),
        .I1(state[0]),
        .I2(state[1]),
        .I3(state[2]),
        .I4(user_reset_out),
        .I5(\tx_64.req_4dw_reg_n_0 ),
        .O(\s_axis_tx_tkeep[7]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0000FFFE0000)) 
    \s_axis_tx_tkeep[7]_i_16 
       (.I0(s_axis_tx_tkeep3[6]),
        .I1(s_axis_tx_tkeep3[9]),
        .I2(s_axis_tx_tkeep3[10]),
        .I3(s_axis_tx_tkeep3[8]),
        .I4(\s_axis_tx_tkeep[7]_i_11_n_0 ),
        .I5(s_axis_tx_tkeep3[7]),
        .O(\s_axis_tx_tkeep[7]_i_16_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_17 
       (.I0(\tx_64.current_dw_count_reg_n_0_[3] ),
        .I1(\tx_64.req_len_reg_n_0_[3] ),
        .O(\s_axis_tx_tkeep[7]_i_17_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \s_axis_tx_tkeep[7]_i_18 
       (.I0(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I1(\tx_64.req_len_reg_n_0_[1] ),
        .O(\s_axis_tx_tkeep[7]_i_18_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \s_axis_tx_tkeep[7]_i_19 
       (.I0(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I1(\tx_64.req_len_reg_n_0_[0] ),
        .O(\s_axis_tx_tkeep[7]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0000FFFE0000)) 
    \s_axis_tx_tkeep[7]_i_2 
       (.I0(\s_axis_tx_tkeep_reg[7]_i_7_n_4 ),
        .I1(\s_axis_tx_tkeep_reg[7]_i_8_n_5 ),
        .I2(\s_axis_tx_tkeep_reg[7]_i_8_n_4 ),
        .I3(\s_axis_tx_tkeep_reg[7]_i_8_n_6 ),
        .I4(\s_axis_tx_tkeep[7]_i_9_n_0 ),
        .I5(\s_axis_tx_tkeep_reg[7]_i_8_n_7 ),
        .O(\s_axis_tx_tkeep[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \s_axis_tx_tkeep[7]_i_20 
       (.I0(\tx_64.req_len_reg_n_0_[0] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[0] ),
        .O(\s_axis_tx_tkeep[7]_i_20_n_0 ));
  LUT4 #(
    .INIT(16'hB44B)) 
    \s_axis_tx_tkeep[7]_i_21 
       (.I0(\tx_64.req_len_reg_n_0_[2] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[2] ),
        .I2(\tx_64.req_len_reg_n_0_[3] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[3] ),
        .O(\s_axis_tx_tkeep[7]_i_21_n_0 ));
  LUT4 #(
    .INIT(16'hB44B)) 
    \s_axis_tx_tkeep[7]_i_22 
       (.I0(\tx_64.req_len_reg_n_0_[1] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I2(\tx_64.req_len_reg_n_0_[2] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[2] ),
        .O(\s_axis_tx_tkeep[7]_i_22_n_0 ));
  LUT4 #(
    .INIT(16'h2DD2)) 
    \s_axis_tx_tkeep[7]_i_23 
       (.I0(\tx_64.req_len_reg_n_0_[0] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I2(\tx_64.req_len_reg_n_0_[1] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[1] ),
        .O(\s_axis_tx_tkeep[7]_i_23_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_24 
       (.I0(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I1(\tx_64.req_len_reg_n_0_[0] ),
        .O(\s_axis_tx_tkeep[7]_i_24_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_25 
       (.I0(\tx_64.current_dw_count_reg_n_0_[7] ),
        .I1(\tx_64.req_len_reg_n_0_[7] ),
        .O(\s_axis_tx_tkeep[7]_i_25_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_26 
       (.I0(\tx_64.current_dw_count_reg_n_0_[6] ),
        .I1(\tx_64.req_len_reg_n_0_[6] ),
        .O(\s_axis_tx_tkeep[7]_i_26_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_27 
       (.I0(\tx_64.current_dw_count_reg_n_0_[5] ),
        .I1(\tx_64.req_len_reg_n_0_[5] ),
        .O(\s_axis_tx_tkeep[7]_i_27_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_28 
       (.I0(\tx_64.current_dw_count_reg_n_0_[4] ),
        .I1(\tx_64.req_len_reg_n_0_[4] ),
        .O(\s_axis_tx_tkeep[7]_i_28_n_0 ));
  LUT4 #(
    .INIT(16'hB44B)) 
    \s_axis_tx_tkeep[7]_i_29 
       (.I0(\tx_64.req_len_reg_n_0_[6] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[6] ),
        .I2(\tx_64.req_len_reg_n_0_[7] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[7] ),
        .O(\s_axis_tx_tkeep[7]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF000FEEEF000)) 
    \s_axis_tx_tkeep[7]_i_3 
       (.I0(\s_axis_tx_tkeep_reg[7]_i_10_n_6 ),
        .I1(\s_axis_tx_tkeep_reg[7]_i_10_n_7 ),
        .I2(\s_axis_tx_tkeep[7]_i_11_n_0 ),
        .I3(\s_axis_tx_tkeep[7]_i_12_n_0 ),
        .I4(\s_axis_tx_tkeep[7]_i_9_n_0 ),
        .I5(\s_axis_tx_tkeep_reg[7]_i_10_n_5 ),
        .O(\s_axis_tx_tkeep[7]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hB44B)) 
    \s_axis_tx_tkeep[7]_i_30 
       (.I0(\tx_64.req_len_reg_n_0_[5] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[5] ),
        .I2(\tx_64.req_len_reg_n_0_[6] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[6] ),
        .O(\s_axis_tx_tkeep[7]_i_30_n_0 ));
  LUT4 #(
    .INIT(16'hB44B)) 
    \s_axis_tx_tkeep[7]_i_31 
       (.I0(\tx_64.req_len_reg_n_0_[4] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[4] ),
        .I2(\tx_64.req_len_reg_n_0_[5] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[5] ),
        .O(\s_axis_tx_tkeep[7]_i_31_n_0 ));
  LUT4 #(
    .INIT(16'hB44B)) 
    \s_axis_tx_tkeep[7]_i_32 
       (.I0(\tx_64.req_len_reg_n_0_[3] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[3] ),
        .I2(\tx_64.req_len_reg_n_0_[4] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[4] ),
        .O(\s_axis_tx_tkeep[7]_i_32_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_33 
       (.I0(\tx_64.current_dw_count_reg_n_0_[9] ),
        .I1(\tx_64.req_len_reg_n_0_[9] ),
        .O(\s_axis_tx_tkeep[7]_i_33_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_34 
       (.I0(\tx_64.current_dw_count_reg_n_0_[8] ),
        .I1(\tx_64.req_len_reg_n_0_[8] ),
        .O(\s_axis_tx_tkeep[7]_i_34_n_0 ));
  LUT3 #(
    .INIT(8'h2D)) 
    \s_axis_tx_tkeep[7]_i_35 
       (.I0(\tx_64.current_dw_count_reg_n_0_[9] ),
        .I1(\tx_64.req_len_reg_n_0_[9] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[10] ),
        .O(\s_axis_tx_tkeep[7]_i_35_n_0 ));
  LUT4 #(
    .INIT(16'hB44B)) 
    \s_axis_tx_tkeep[7]_i_36 
       (.I0(\tx_64.req_len_reg_n_0_[8] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[8] ),
        .I2(\tx_64.req_len_reg_n_0_[9] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[9] ),
        .O(\s_axis_tx_tkeep[7]_i_36_n_0 ));
  LUT4 #(
    .INIT(16'hB44B)) 
    \s_axis_tx_tkeep[7]_i_37 
       (.I0(\tx_64.req_len_reg_n_0_[7] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[7] ),
        .I2(\tx_64.req_len_reg_n_0_[8] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[8] ),
        .O(\s_axis_tx_tkeep[7]_i_37_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_38 
       (.I0(\tx_64.req_len_reg_n_0_[3] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[3] ),
        .O(\s_axis_tx_tkeep[7]_i_38_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_39 
       (.I0(\tx_64.req_len_reg_n_0_[2] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[2] ),
        .O(\s_axis_tx_tkeep[7]_i_39_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0000FFFE0000)) 
    \s_axis_tx_tkeep[7]_i_4 
       (.I0(s_axis_tx_tkeep3[1]),
        .I1(s_axis_tx_tkeep3[4]),
        .I2(s_axis_tx_tkeep3[5]),
        .I3(s_axis_tx_tkeep3[3]),
        .I4(\s_axis_tx_tkeep[7]_i_11_n_0 ),
        .I5(s_axis_tx_tkeep3[2]),
        .O(\s_axis_tx_tkeep[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_40 
       (.I0(\tx_64.req_len_reg_n_0_[1] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[1] ),
        .O(\s_axis_tx_tkeep[7]_i_40_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_41 
       (.I0(\tx_64.req_len_reg_n_0_[0] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[0] ),
        .O(\s_axis_tx_tkeep[7]_i_41_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_42 
       (.I0(\tx_64.req_len_reg_n_0_[7] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[7] ),
        .O(\s_axis_tx_tkeep[7]_i_42_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_43 
       (.I0(\tx_64.req_len_reg_n_0_[6] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[6] ),
        .O(\s_axis_tx_tkeep[7]_i_43_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_44 
       (.I0(\tx_64.req_len_reg_n_0_[5] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[5] ),
        .O(\s_axis_tx_tkeep[7]_i_44_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_45 
       (.I0(\tx_64.req_len_reg_n_0_[4] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[4] ),
        .O(\s_axis_tx_tkeep[7]_i_45_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \s_axis_tx_tkeep[7]_i_47 
       (.I0(\tx_64.current_dw_count_reg_n_0_[10] ),
        .O(\s_axis_tx_tkeep[7]_i_47_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_48 
       (.I0(\tx_64.req_len_reg_n_0_[9] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[9] ),
        .O(\s_axis_tx_tkeep[7]_i_48_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \s_axis_tx_tkeep[7]_i_49 
       (.I0(\tx_64.req_len_reg_n_0_[8] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[8] ),
        .O(\s_axis_tx_tkeep[7]_i_49_n_0 ));
  LUT5 #(
    .INIT(32'hFFFDFCFC)) 
    \s_axis_tx_tkeep[7]_i_5 
       (.I0(\s_axis_tx_tkeep_reg[7]_i_7_n_7 ),
        .I1(\s_axis_tx_tkeep[7]_i_15_n_0 ),
        .I2(\s_axis_tx_tkeep[7]_i_16_n_0 ),
        .I3(\s_axis_tx_tkeep_reg[7]_i_7_n_6 ),
        .I4(\s_axis_tx_tkeep[7]_i_9_n_0 ),
        .O(\s_axis_tx_tkeep[7]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1936" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \s_axis_tx_tkeep[7]_i_9 
       (.I0(user_reset_out),
        .I1(state[1]),
        .I2(state[2]),
        .I3(state[0]),
        .O(\s_axis_tx_tkeep[7]_i_9_n_0 ));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \s_axis_tx_tkeep_reg[7]_i_10 
       (.CI(\s_axis_tx_tkeep_reg[7]_i_8_n_0 ),
        .CO({\NLW_s_axis_tx_tkeep_reg[7]_i_10_CO_UNCONNECTED [3:2],\s_axis_tx_tkeep_reg[7]_i_10_n_2 ,\s_axis_tx_tkeep_reg[7]_i_10_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,\s_axis_tx_tkeep[7]_i_33_n_0 ,\s_axis_tx_tkeep[7]_i_34_n_0 }),
        .O({\NLW_s_axis_tx_tkeep_reg[7]_i_10_O_UNCONNECTED [3],\s_axis_tx_tkeep_reg[7]_i_10_n_5 ,\s_axis_tx_tkeep_reg[7]_i_10_n_6 ,\s_axis_tx_tkeep_reg[7]_i_10_n_7 }),
        .S({1'b0,\s_axis_tx_tkeep[7]_i_35_n_0 ,\s_axis_tx_tkeep[7]_i_36_n_0 ,\s_axis_tx_tkeep[7]_i_37_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \s_axis_tx_tkeep_reg[7]_i_13 
       (.CI(1'b0),
        .CO({\s_axis_tx_tkeep_reg[7]_i_13_n_0 ,\s_axis_tx_tkeep_reg[7]_i_13_n_1 ,\s_axis_tx_tkeep_reg[7]_i_13_n_2 ,\s_axis_tx_tkeep_reg[7]_i_13_n_3 }),
        .CYINIT(1'b1),
        .DI({\tx_64.req_len_reg_n_0_[3] ,\tx_64.req_len_reg_n_0_[2] ,\tx_64.req_len_reg_n_0_[1] ,\tx_64.req_len_reg_n_0_[0] }),
        .O({s_axis_tx_tkeep3[3:1],\NLW_s_axis_tx_tkeep_reg[7]_i_13_O_UNCONNECTED [0]}),
        .S({\s_axis_tx_tkeep[7]_i_38_n_0 ,\s_axis_tx_tkeep[7]_i_39_n_0 ,\s_axis_tx_tkeep[7]_i_40_n_0 ,\s_axis_tx_tkeep[7]_i_41_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \s_axis_tx_tkeep_reg[7]_i_14 
       (.CI(\s_axis_tx_tkeep_reg[7]_i_13_n_0 ),
        .CO({\s_axis_tx_tkeep_reg[7]_i_14_n_0 ,\s_axis_tx_tkeep_reg[7]_i_14_n_1 ,\s_axis_tx_tkeep_reg[7]_i_14_n_2 ,\s_axis_tx_tkeep_reg[7]_i_14_n_3 }),
        .CYINIT(1'b0),
        .DI({\tx_64.req_len_reg_n_0_[7] ,\tx_64.req_len_reg_n_0_[6] ,\tx_64.req_len_reg_n_0_[5] ,\tx_64.req_len_reg_n_0_[4] }),
        .O(s_axis_tx_tkeep3[7:4]),
        .S({\s_axis_tx_tkeep[7]_i_42_n_0 ,\s_axis_tx_tkeep[7]_i_43_n_0 ,\s_axis_tx_tkeep[7]_i_44_n_0 ,\s_axis_tx_tkeep[7]_i_45_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \s_axis_tx_tkeep_reg[7]_i_46 
       (.CI(\s_axis_tx_tkeep_reg[7]_i_14_n_0 ),
        .CO({\NLW_s_axis_tx_tkeep_reg[7]_i_46_CO_UNCONNECTED [3:2],\s_axis_tx_tkeep_reg[7]_i_46_n_2 ,\s_axis_tx_tkeep_reg[7]_i_46_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,\tx_64.req_len_reg_n_0_[9] ,\tx_64.req_len_reg_n_0_[8] }),
        .O({\NLW_s_axis_tx_tkeep_reg[7]_i_46_O_UNCONNECTED [3],s_axis_tx_tkeep3[10:8]}),
        .S({1'b0,\s_axis_tx_tkeep[7]_i_47_n_0 ,\s_axis_tx_tkeep[7]_i_48_n_0 ,\s_axis_tx_tkeep[7]_i_49_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \s_axis_tx_tkeep_reg[7]_i_7 
       (.CI(1'b0),
        .CO({\s_axis_tx_tkeep_reg[7]_i_7_n_0 ,\s_axis_tx_tkeep_reg[7]_i_7_n_1 ,\s_axis_tx_tkeep_reg[7]_i_7_n_2 ,\s_axis_tx_tkeep_reg[7]_i_7_n_3 }),
        .CYINIT(1'b1),
        .DI({\s_axis_tx_tkeep[7]_i_17_n_0 ,\s_axis_tx_tkeep[7]_i_18_n_0 ,\s_axis_tx_tkeep[7]_i_19_n_0 ,\s_axis_tx_tkeep[7]_i_20_n_0 }),
        .O({\s_axis_tx_tkeep_reg[7]_i_7_n_4 ,\s_axis_tx_tkeep_reg[7]_i_7_n_5 ,\s_axis_tx_tkeep_reg[7]_i_7_n_6 ,\s_axis_tx_tkeep_reg[7]_i_7_n_7 }),
        .S({\s_axis_tx_tkeep[7]_i_21_n_0 ,\s_axis_tx_tkeep[7]_i_22_n_0 ,\s_axis_tx_tkeep[7]_i_23_n_0 ,\s_axis_tx_tkeep[7]_i_24_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \s_axis_tx_tkeep_reg[7]_i_8 
       (.CI(\s_axis_tx_tkeep_reg[7]_i_7_n_0 ),
        .CO({\s_axis_tx_tkeep_reg[7]_i_8_n_0 ,\s_axis_tx_tkeep_reg[7]_i_8_n_1 ,\s_axis_tx_tkeep_reg[7]_i_8_n_2 ,\s_axis_tx_tkeep_reg[7]_i_8_n_3 }),
        .CYINIT(1'b0),
        .DI({\s_axis_tx_tkeep[7]_i_25_n_0 ,\s_axis_tx_tkeep[7]_i_26_n_0 ,\s_axis_tx_tkeep[7]_i_27_n_0 ,\s_axis_tx_tkeep[7]_i_28_n_0 }),
        .O({\s_axis_tx_tkeep_reg[7]_i_8_n_4 ,\s_axis_tx_tkeep_reg[7]_i_8_n_5 ,\s_axis_tx_tkeep_reg[7]_i_8_n_6 ,\s_axis_tx_tkeep_reg[7]_i_8_n_7 }),
        .S({\s_axis_tx_tkeep[7]_i_29_n_0 ,\s_axis_tx_tkeep[7]_i_30_n_0 ,\s_axis_tx_tkeep[7]_i_31_n_0 ,\s_axis_tx_tkeep[7]_i_32_n_0 }));
  LUT4 #(
    .INIT(16'hB888)) 
    s_axis_tx_tlast_i_1
       (.I0(s_axis_tx_req_tlast),
        .I1(transfer_SM[1]),
        .I2(s_axis_tx_tlast_reg),
        .I3(\m_axis_cc\.tlast ),
        .O(\FSM_sequential_transfer_SM_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1941" *) 
  LUT5 #(
    .INIT(32'h40400004)) 
    \tx_64.current_dw_count[0]_i_1 
       (.I0(state[2]),
        .I1(state[1]),
        .I2(state[0]),
        .I3(\tx_64.req_4dw_reg_n_0 ),
        .I4(\tx_64.current_dw_count_reg_n_0_[0] ),
        .O(current_dw_count[0]));
  LUT5 #(
    .INIT(32'h03020B0B)) 
    \tx_64.current_dw_count[10]_i_1 
       (.I0(s_axis_tx_req_tready),
        .I1(state[1]),
        .I2(user_reset_out),
        .I3(state[0]),
        .I4(state[2]),
        .O(\tx_64.current_dw_count[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h9999009C00000000)) 
    \tx_64.current_dw_count[10]_i_2 
       (.I0(\tx_64.current_dw_count[10]_i_3_n_0 ),
        .I1(\tx_64.current_dw_count_reg_n_0_[10] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I3(\tx_64.req_4dw_reg_n_0 ),
        .I4(state[0]),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(current_dw_count[10]));
  (* SOFT_HLUTNM = "soft_lutpair1939" *) 
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \tx_64.current_dw_count[10]_i_3 
       (.I0(\tx_64.current_dw_count_reg_n_0_[8] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[6] ),
        .I2(\tx_64.current_dw_count[6]_i_2_n_0 ),
        .I3(\tx_64.current_dw_count_reg_n_0_[7] ),
        .I4(\tx_64.current_dw_count_reg_n_0_[9] ),
        .O(\tx_64.current_dw_count[10]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1944" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \tx_64.current_dw_count[10]_i_4 
       (.I0(state[1]),
        .I1(state[2]),
        .O(\tx_64.current_dw_count[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0001000000F40000)) 
    \tx_64.current_dw_count[1]_i_1 
       (.I0(\tx_64.req_4dw_reg_n_0 ),
        .I1(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I2(state[0]),
        .I3(state[2]),
        .I4(state[1]),
        .I5(\tx_64.current_dw_count_reg_n_0_[1] ),
        .O(current_dw_count[1]));
  LUT6 #(
    .INIT(64'h6666006C00000000)) 
    \tx_64.current_dw_count[2]_i_1 
       (.I0(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[2] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I3(\tx_64.req_4dw_reg_n_0 ),
        .I4(state[0]),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(current_dw_count[2]));
  LUT6 #(
    .INIT(64'h9999009C00000000)) 
    \tx_64.current_dw_count[3]_i_1 
       (.I0(\tx_64.current_dw_count[3]_i_2_n_0 ),
        .I1(\tx_64.current_dw_count_reg_n_0_[3] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I3(\tx_64.req_4dw_reg_n_0 ),
        .I4(state[0]),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(current_dw_count[3]));
  (* SOFT_HLUTNM = "soft_lutpair1946" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \tx_64.current_dw_count[3]_i_2 
       (.I0(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[2] ),
        .O(\tx_64.current_dw_count[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9999009C00000000)) 
    \tx_64.current_dw_count[4]_i_1 
       (.I0(\tx_64.current_dw_count[4]_i_2_n_0 ),
        .I1(\tx_64.current_dw_count_reg_n_0_[4] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I3(\tx_64.req_4dw_reg_n_0 ),
        .I4(state[0]),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(current_dw_count[4]));
  (* SOFT_HLUTNM = "soft_lutpair1946" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \tx_64.current_dw_count[4]_i_2 
       (.I0(\tx_64.current_dw_count_reg_n_0_[2] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[3] ),
        .O(\tx_64.current_dw_count[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9999009C00000000)) 
    \tx_64.current_dw_count[5]_i_1 
       (.I0(\tx_64.current_dw_count[5]_i_2_n_0 ),
        .I1(\tx_64.current_dw_count_reg_n_0_[5] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I3(\tx_64.req_4dw_reg_n_0 ),
        .I4(state[0]),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(current_dw_count[5]));
  (* SOFT_HLUTNM = "soft_lutpair1935" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \tx_64.current_dw_count[5]_i_2 
       (.I0(\tx_64.current_dw_count_reg_n_0_[3] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[2] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[4] ),
        .O(\tx_64.current_dw_count[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9999009C00000000)) 
    \tx_64.current_dw_count[6]_i_1 
       (.I0(\tx_64.current_dw_count[6]_i_2_n_0 ),
        .I1(\tx_64.current_dw_count_reg_n_0_[6] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I3(\tx_64.req_4dw_reg_n_0 ),
        .I4(state[0]),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(current_dw_count[6]));
  (* SOFT_HLUTNM = "soft_lutpair1935" *) 
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    \tx_64.current_dw_count[6]_i_2 
       (.I0(\tx_64.current_dw_count_reg_n_0_[4] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[2] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[3] ),
        .I4(\tx_64.current_dw_count_reg_n_0_[5] ),
        .O(\tx_64.current_dw_count[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9999009C00000000)) 
    \tx_64.current_dw_count[7]_i_1 
       (.I0(\tx_64.current_dw_count[7]_i_2_n_0 ),
        .I1(\tx_64.current_dw_count_reg_n_0_[7] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I3(\tx_64.req_4dw_reg_n_0 ),
        .I4(state[0]),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(current_dw_count[7]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \tx_64.current_dw_count[7]_i_2 
       (.I0(\tx_64.current_dw_count_reg_n_0_[5] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[3] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[2] ),
        .I4(\tx_64.current_dw_count_reg_n_0_[4] ),
        .I5(\tx_64.current_dw_count_reg_n_0_[6] ),
        .O(\tx_64.current_dw_count[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9999009C00000000)) 
    \tx_64.current_dw_count[8]_i_1 
       (.I0(\tx_64.current_dw_count[8]_i_2_n_0 ),
        .I1(\tx_64.current_dw_count_reg_n_0_[8] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I3(\tx_64.req_4dw_reg_n_0 ),
        .I4(state[0]),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(current_dw_count[8]));
  LUT3 #(
    .INIT(8'hDF)) 
    \tx_64.current_dw_count[8]_i_2 
       (.I0(\tx_64.current_dw_count_reg_n_0_[6] ),
        .I1(\tx_64.current_dw_count[6]_i_2_n_0 ),
        .I2(\tx_64.current_dw_count_reg_n_0_[7] ),
        .O(\tx_64.current_dw_count[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9999009C00000000)) 
    \tx_64.current_dw_count[9]_i_1 
       (.I0(\tx_64.current_dw_count[9]_i_2_n_0 ),
        .I1(\tx_64.current_dw_count_reg_n_0_[9] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I3(\tx_64.req_4dw_reg_n_0 ),
        .I4(state[0]),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(current_dw_count[9]));
  (* SOFT_HLUTNM = "soft_lutpair1939" *) 
  LUT4 #(
    .INIT(16'hDFFF)) 
    \tx_64.current_dw_count[9]_i_2 
       (.I0(\tx_64.current_dw_count_reg_n_0_[7] ),
        .I1(\tx_64.current_dw_count[6]_i_2_n_0 ),
        .I2(\tx_64.current_dw_count_reg_n_0_[6] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[8] ),
        .O(\tx_64.current_dw_count[9]_i_2_n_0 ));
  FDRE \tx_64.current_dw_count_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.current_dw_count[10]_i_1_n_0 ),
        .D(current_dw_count[0]),
        .Q(\tx_64.current_dw_count_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \tx_64.current_dw_count_reg[10] 
       (.C(user_clk_out),
        .CE(\tx_64.current_dw_count[10]_i_1_n_0 ),
        .D(current_dw_count[10]),
        .Q(\tx_64.current_dw_count_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \tx_64.current_dw_count_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.current_dw_count[10]_i_1_n_0 ),
        .D(current_dw_count[1]),
        .Q(\tx_64.current_dw_count_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \tx_64.current_dw_count_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.current_dw_count[10]_i_1_n_0 ),
        .D(current_dw_count[2]),
        .Q(\tx_64.current_dw_count_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \tx_64.current_dw_count_reg[3] 
       (.C(user_clk_out),
        .CE(\tx_64.current_dw_count[10]_i_1_n_0 ),
        .D(current_dw_count[3]),
        .Q(\tx_64.current_dw_count_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \tx_64.current_dw_count_reg[4] 
       (.C(user_clk_out),
        .CE(\tx_64.current_dw_count[10]_i_1_n_0 ),
        .D(current_dw_count[4]),
        .Q(\tx_64.current_dw_count_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \tx_64.current_dw_count_reg[5] 
       (.C(user_clk_out),
        .CE(\tx_64.current_dw_count[10]_i_1_n_0 ),
        .D(current_dw_count[5]),
        .Q(\tx_64.current_dw_count_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \tx_64.current_dw_count_reg[6] 
       (.C(user_clk_out),
        .CE(\tx_64.current_dw_count[10]_i_1_n_0 ),
        .D(current_dw_count[6]),
        .Q(\tx_64.current_dw_count_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \tx_64.current_dw_count_reg[7] 
       (.C(user_clk_out),
        .CE(\tx_64.current_dw_count[10]_i_1_n_0 ),
        .D(current_dw_count[7]),
        .Q(\tx_64.current_dw_count_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \tx_64.current_dw_count_reg[8] 
       (.C(user_clk_out),
        .CE(\tx_64.current_dw_count[10]_i_1_n_0 ),
        .D(current_dw_count[8]),
        .Q(\tx_64.current_dw_count_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \tx_64.current_dw_count_reg[9] 
       (.C(user_clk_out),
        .CE(\tx_64.current_dw_count[10]_i_1_n_0 ),
        .D(current_dw_count[9]),
        .Q(\tx_64.current_dw_count_reg_n_0_[9] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000FFFFC0005555)) 
    \tx_64.dw_count[10]_i_1 
       (.I0(state[0]),
        .I1(transfer_SM[0]),
        .I2(transfer_SM[1]),
        .I3(s_axis_tx_tready),
        .I4(state[1]),
        .I5(state[2]),
        .O(\tx_64.dw_count[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4040404004404040)) 
    \tx_64.dw_count[10]_i_2 
       (.I0(state[2]),
        .I1(state[1]),
        .I2(\tx_64.dw_count_reg_n_0_[10] ),
        .I3(\tx_64.dw_count_reg_n_0_[9] ),
        .I4(\tx_64.dw_count_reg_n_0_[8] ),
        .I5(\tx_64.dw_count[10]_i_3_n_0 ),
        .O(dw_count[10]));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \tx_64.dw_count[10]_i_3 
       (.I0(\tx_64.dw_count_reg_n_0_[6] ),
        .I1(\tx_64.dw_count_reg_n_0_[4] ),
        .I2(\tx_64.dw_count[6]_i_2_n_0 ),
        .I3(\tx_64.dw_count_reg_n_0_[3] ),
        .I4(\tx_64.dw_count_reg_n_0_[5] ),
        .I5(\tx_64.dw_count_reg_n_0_[7] ),
        .O(\tx_64.dw_count[10]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1949" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \tx_64.dw_count[1]_i_1 
       (.I0(state[2]),
        .I1(state[1]),
        .I2(\tx_64.dw_count_reg_n_0_[1] ),
        .O(dw_count[1]));
  (* SOFT_HLUTNM = "soft_lutpair1940" *) 
  LUT4 #(
    .INIT(16'h0600)) 
    \tx_64.dw_count[2]_i_1 
       (.I0(\tx_64.dw_count_reg_n_0_[2] ),
        .I1(\tx_64.dw_count_reg_n_0_[1] ),
        .I2(state[2]),
        .I3(state[1]),
        .O(dw_count[2]));
  (* SOFT_HLUTNM = "soft_lutpair1940" *) 
  LUT5 #(
    .INIT(32'h006A0000)) 
    \tx_64.dw_count[3]_i_1 
       (.I0(\tx_64.dw_count_reg_n_0_[3] ),
        .I1(\tx_64.dw_count_reg_n_0_[1] ),
        .I2(\tx_64.dw_count_reg_n_0_[2] ),
        .I3(state[2]),
        .I4(state[1]),
        .O(dw_count[3]));
  LUT6 #(
    .INIT(64'h00006AAA00000000)) 
    \tx_64.dw_count[4]_i_1 
       (.I0(\tx_64.dw_count_reg_n_0_[4] ),
        .I1(\tx_64.dw_count_reg_n_0_[2] ),
        .I2(\tx_64.dw_count_reg_n_0_[1] ),
        .I3(\tx_64.dw_count_reg_n_0_[3] ),
        .I4(state[2]),
        .I5(state[1]),
        .O(dw_count[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAA00000000)) 
    \tx_64.dw_count[5]_i_1 
       (.I0(\tx_64.dw_count_reg_n_0_[5] ),
        .I1(\tx_64.dw_count_reg_n_0_[3] ),
        .I2(\tx_64.dw_count_reg_n_0_[1] ),
        .I3(\tx_64.dw_count_reg_n_0_[2] ),
        .I4(\tx_64.dw_count_reg_n_0_[4] ),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(dw_count[5]));
  LUT6 #(
    .INIT(64'hA6AAAAAA00000000)) 
    \tx_64.dw_count[6]_i_1 
       (.I0(\tx_64.dw_count_reg_n_0_[6] ),
        .I1(\tx_64.dw_count_reg_n_0_[4] ),
        .I2(\tx_64.dw_count[6]_i_2_n_0 ),
        .I3(\tx_64.dw_count_reg_n_0_[3] ),
        .I4(\tx_64.dw_count_reg_n_0_[5] ),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(dw_count[6]));
  (* SOFT_HLUTNM = "soft_lutpair1942" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \tx_64.dw_count[6]_i_2 
       (.I0(\tx_64.dw_count_reg_n_0_[1] ),
        .I1(\tx_64.dw_count_reg_n_0_[2] ),
        .O(\tx_64.dw_count[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hA6AAAAAA00000000)) 
    \tx_64.dw_count[7]_i_1 
       (.I0(\tx_64.dw_count_reg_n_0_[7] ),
        .I1(\tx_64.dw_count_reg_n_0_[5] ),
        .I2(\tx_64.dw_count[7]_i_2_n_0 ),
        .I3(\tx_64.dw_count_reg_n_0_[4] ),
        .I4(\tx_64.dw_count_reg_n_0_[6] ),
        .I5(\tx_64.current_dw_count[10]_i_4_n_0 ),
        .O(dw_count[7]));
  (* SOFT_HLUTNM = "soft_lutpair1937" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \tx_64.dw_count[7]_i_2 
       (.I0(\tx_64.dw_count_reg_n_0_[2] ),
        .I1(\tx_64.dw_count_reg_n_0_[1] ),
        .I2(\tx_64.dw_count_reg_n_0_[3] ),
        .O(\tx_64.dw_count[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1938" *) 
  LUT4 #(
    .INIT(16'h0900)) 
    \tx_64.dw_count[8]_i_1 
       (.I0(\tx_64.dw_count_reg_n_0_[8] ),
        .I1(\tx_64.dw_count[10]_i_3_n_0 ),
        .I2(state[2]),
        .I3(state[1]),
        .O(dw_count[8]));
  (* SOFT_HLUTNM = "soft_lutpair1938" *) 
  LUT5 #(
    .INIT(32'h009A0000)) 
    \tx_64.dw_count[9]_i_1 
       (.I0(\tx_64.dw_count_reg_n_0_[9] ),
        .I1(\tx_64.dw_count[10]_i_3_n_0 ),
        .I2(\tx_64.dw_count_reg_n_0_[8] ),
        .I3(state[2]),
        .I4(state[1]),
        .O(dw_count[9]));
  FDRE \tx_64.dw_count_reg[10] 
       (.C(user_clk_out),
        .CE(\tx_64.dw_count[10]_i_1_n_0 ),
        .D(dw_count[10]),
        .Q(\tx_64.dw_count_reg_n_0_[10] ),
        .R(user_reset_out));
  FDRE \tx_64.dw_count_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.dw_count[10]_i_1_n_0 ),
        .D(dw_count[1]),
        .Q(\tx_64.dw_count_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.dw_count_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.dw_count[10]_i_1_n_0 ),
        .D(dw_count[2]),
        .Q(\tx_64.dw_count_reg_n_0_[2] ),
        .R(user_reset_out));
  FDRE \tx_64.dw_count_reg[3] 
       (.C(user_clk_out),
        .CE(\tx_64.dw_count[10]_i_1_n_0 ),
        .D(dw_count[3]),
        .Q(\tx_64.dw_count_reg_n_0_[3] ),
        .R(user_reset_out));
  FDRE \tx_64.dw_count_reg[4] 
       (.C(user_clk_out),
        .CE(\tx_64.dw_count[10]_i_1_n_0 ),
        .D(dw_count[4]),
        .Q(\tx_64.dw_count_reg_n_0_[4] ),
        .R(user_reset_out));
  FDRE \tx_64.dw_count_reg[5] 
       (.C(user_clk_out),
        .CE(\tx_64.dw_count[10]_i_1_n_0 ),
        .D(dw_count[5]),
        .Q(\tx_64.dw_count_reg_n_0_[5] ),
        .R(user_reset_out));
  FDRE \tx_64.dw_count_reg[6] 
       (.C(user_clk_out),
        .CE(\tx_64.dw_count[10]_i_1_n_0 ),
        .D(dw_count[6]),
        .Q(\tx_64.dw_count_reg_n_0_[6] ),
        .R(user_reset_out));
  FDRE \tx_64.dw_count_reg[7] 
       (.C(user_clk_out),
        .CE(\tx_64.dw_count[10]_i_1_n_0 ),
        .D(dw_count[7]),
        .Q(\tx_64.dw_count_reg_n_0_[7] ),
        .R(user_reset_out));
  FDRE \tx_64.dw_count_reg[8] 
       (.C(user_clk_out),
        .CE(\tx_64.dw_count[10]_i_1_n_0 ),
        .D(dw_count[8]),
        .Q(\tx_64.dw_count_reg_n_0_[8] ),
        .R(user_reset_out));
  FDRE \tx_64.dw_count_reg[9] 
       (.C(user_clk_out),
        .CE(\tx_64.dw_count[10]_i_1_n_0 ),
        .D(dw_count[9]),
        .Q(\tx_64.dw_count_reg_n_0_[9] ),
        .R(user_reset_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \tx_64.req_4dw_i_1 
       (.I0(\tx_64.req_4dw_i_2_n_0 ),
        .I1(\tx_64.req_4dw_i_3_n_0 ),
        .I2(\tx_64.req_4dw_i_4_n_0 ),
        .I3(\tx_64.req_4dw_i_5_n_0 ),
        .I4(\tx_64.req_4dw_i_6_n_0 ),
        .I5(\tx_64.req_4dw_i_7_n_0 ),
        .O(\tx_64.req_4dw_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \tx_64.req_4dw_i_2 
       (.I0(\tx_64.req_addr_reg[63]_0 [38]),
        .I1(\tx_64.req_addr_reg[63]_0 [39]),
        .I2(\tx_64.req_addr_reg[63]_0 [36]),
        .I3(\tx_64.req_addr_reg[63]_0 [37]),
        .I4(\tx_64.req_addr_reg[63]_0 [35]),
        .I5(\tx_64.req_addr_reg[63]_0 [34]),
        .O(\tx_64.req_4dw_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \tx_64.req_4dw_i_3 
       (.I0(\tx_64.req_addr_reg[63]_0 [44]),
        .I1(\tx_64.req_addr_reg[63]_0 [45]),
        .I2(\tx_64.req_addr_reg[63]_0 [42]),
        .I3(\tx_64.req_addr_reg[63]_0 [43]),
        .I4(\tx_64.req_addr_reg[63]_0 [41]),
        .I5(\tx_64.req_addr_reg[63]_0 [40]),
        .O(\tx_64.req_4dw_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \tx_64.req_4dw_i_4 
       (.I0(\tx_64.req_addr_reg[63]_0 [56]),
        .I1(\tx_64.req_addr_reg[63]_0 [63]),
        .I2(\tx_64.req_addr_reg[63]_0 [54]),
        .I3(\tx_64.req_addr_reg[63]_0 [55]),
        .I4(\tx_64.req_addr_reg[63]_0 [53]),
        .I5(\tx_64.req_addr_reg[63]_0 [52]),
        .O(\tx_64.req_4dw_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \tx_64.req_4dw_i_5 
       (.I0(\tx_64.req_addr_reg[63]_0 [50]),
        .I1(\tx_64.req_addr_reg[63]_0 [51]),
        .I2(\tx_64.req_addr_reg[63]_0 [48]),
        .I3(\tx_64.req_addr_reg[63]_0 [49]),
        .I4(\tx_64.req_addr_reg[63]_0 [47]),
        .I5(\tx_64.req_addr_reg[63]_0 [46]),
        .O(\tx_64.req_4dw_i_5_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \tx_64.req_4dw_i_6 
       (.I0(\tx_64.req_addr_reg[63]_0 [60]),
        .I1(\tx_64.req_addr_reg[63]_0 [61]),
        .O(\tx_64.req_4dw_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \tx_64.req_4dw_i_7 
       (.I0(\tx_64.req_addr_reg[63]_0 [32]),
        .I1(\tx_64.req_addr_reg[63]_0 [33]),
        .I2(\tx_64.req_addr_reg[63]_0 [58]),
        .I3(\tx_64.req_addr_reg[63]_0 [59]),
        .I4(\tx_64.req_addr_reg[63]_0 [57]),
        .I5(\tx_64.req_addr_reg[63]_0 [62]),
        .O(\tx_64.req_4dw_i_7_n_0 ));
  FDRE \tx_64.req_4dw_reg 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_4dw_i_1_n_0 ),
        .Q(\tx_64.req_4dw_reg_n_0 ),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[10] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [10]),
        .Q(p_0_in[42]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[11] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [11]),
        .Q(p_0_in[43]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[12] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [12]),
        .Q(p_0_in[44]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[13] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [13]),
        .Q(p_0_in[45]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[14] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [14]),
        .Q(p_0_in[46]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[15] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [15]),
        .Q(p_0_in[47]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[16] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [16]),
        .Q(p_0_in[48]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[17] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [17]),
        .Q(p_0_in[49]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[18] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [18]),
        .Q(p_0_in[50]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[19] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [19]),
        .Q(p_0_in[51]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[20] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [20]),
        .Q(p_0_in[52]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[21] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [21]),
        .Q(p_0_in[53]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[22] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [22]),
        .Q(p_0_in[54]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[23] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [23]),
        .Q(p_0_in[55]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[24] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [24]),
        .Q(p_0_in[56]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[25] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [25]),
        .Q(p_0_in[57]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[26] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [26]),
        .Q(p_0_in[58]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[27] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [27]),
        .Q(p_0_in[59]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[28] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [28]),
        .Q(p_0_in[60]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[29] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [29]),
        .Q(p_0_in[61]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[2] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [2]),
        .Q(p_0_in[34]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[30] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [30]),
        .Q(p_0_in[62]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[31] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [31]),
        .Q(p_0_in[63]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[32] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [32]),
        .Q(p_0_in[0]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[33] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [33]),
        .Q(p_0_in[1]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[34] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [34]),
        .Q(p_0_in[2]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[35] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [35]),
        .Q(p_0_in[3]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[36] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [36]),
        .Q(p_0_in[4]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[37] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [37]),
        .Q(p_0_in[5]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[38] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [38]),
        .Q(p_0_in[6]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[39] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [39]),
        .Q(p_0_in[7]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[3] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [3]),
        .Q(p_0_in[35]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[40] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [40]),
        .Q(p_0_in[8]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[41] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [41]),
        .Q(p_0_in[9]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[42] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [42]),
        .Q(p_0_in[10]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[43] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [43]),
        .Q(p_0_in[11]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[44] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [44]),
        .Q(p_0_in[12]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[45] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [45]),
        .Q(p_0_in[13]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[46] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [46]),
        .Q(p_0_in[14]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[47] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [47]),
        .Q(p_0_in[15]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[48] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [48]),
        .Q(p_0_in[16]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[49] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [49]),
        .Q(p_0_in[17]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[4] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [4]),
        .Q(p_0_in[36]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[50] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [50]),
        .Q(p_0_in[18]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[51] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [51]),
        .Q(p_0_in[19]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[52] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [52]),
        .Q(p_0_in[20]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[53] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [53]),
        .Q(p_0_in[21]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[54] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [54]),
        .Q(p_0_in[22]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[55] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [55]),
        .Q(p_0_in[23]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[56] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [56]),
        .Q(p_0_in[24]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[57] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [57]),
        .Q(p_0_in[25]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[58] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [58]),
        .Q(p_0_in[26]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[59] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [59]),
        .Q(p_0_in[27]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[5] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [5]),
        .Q(p_0_in[37]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[60] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [60]),
        .Q(p_0_in[28]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[61] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [61]),
        .Q(p_0_in[29]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[62] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [62]),
        .Q(p_0_in[30]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[63] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [63]),
        .Q(p_0_in[31]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[6] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [6]),
        .Q(p_0_in[38]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[7] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [7]),
        .Q(p_0_in[39]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[8] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [8]),
        .Q(p_0_in[40]),
        .R(user_reset_out));
  FDRE \tx_64.req_addr_reg[9] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [9]),
        .Q(p_0_in[41]),
        .R(user_reset_out));
  LUT6 #(
    .INIT(64'h0404000400000004)) 
    \tx_64.req_at[1]_i_1 
       (.I0(state[1]),
        .I1(\m_axis_rq\.tvalid ),
        .I2(in_packet_q),
        .I3(state[0]),
        .I4(state[2]),
        .I5(s_axis_tx_req_tready),
        .O(req_at));
  FDRE \tx_64.req_at_reg[0] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [0]),
        .Q(p_0_out[10]),
        .R(user_reset_out));
  FDRE \tx_64.req_at_reg[1] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(\tx_64.req_addr_reg[63]_0 [1]),
        .Q(p_0_out[11]),
        .R(user_reset_out));
  FDRE \tx_64.req_fbe_reg[0] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[0]),
        .Q(p_0_out[32]),
        .R(user_reset_out));
  FDRE \tx_64.req_fbe_reg[1] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[1]),
        .Q(p_0_out[33]),
        .R(user_reset_out));
  FDRE \tx_64.req_fbe_reg[2] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[2]),
        .Q(p_0_out[34]),
        .R(user_reset_out));
  FDRE \tx_64.req_fbe_reg[3] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[3]),
        .Q(p_0_out[35]),
        .R(user_reset_out));
  FDRE \tx_64.req_lbe_reg[0] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[4]),
        .Q(p_0_out[36]),
        .R(user_reset_out));
  FDRE \tx_64.req_lbe_reg[1] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[5]),
        .Q(p_0_out[37]),
        .R(user_reset_out));
  FDRE \tx_64.req_lbe_reg[2] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[6]),
        .Q(p_0_out[38]),
        .R(user_reset_out));
  FDRE \tx_64.req_lbe_reg[3] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[7]),
        .Q(p_0_out[39]),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair1950" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \tx_64.req_len[0]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [0]),
        .I1(state[0]),
        .I2(state[2]),
        .O(req_len[0]));
  (* SOFT_HLUTNM = "soft_lutpair1950" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \tx_64.req_len[1]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [1]),
        .I1(state[0]),
        .I2(state[2]),
        .O(req_len[1]));
  (* SOFT_HLUTNM = "soft_lutpair1951" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \tx_64.req_len[2]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [2]),
        .I1(state[0]),
        .I2(state[2]),
        .O(req_len[2]));
  (* SOFT_HLUTNM = "soft_lutpair1951" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \tx_64.req_len[3]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [3]),
        .I1(state[0]),
        .I2(state[2]),
        .O(req_len[3]));
  (* SOFT_HLUTNM = "soft_lutpair1952" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \tx_64.req_len[4]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [4]),
        .I1(state[0]),
        .I2(state[2]),
        .O(req_len[4]));
  (* SOFT_HLUTNM = "soft_lutpair1952" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \tx_64.req_len[5]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [5]),
        .I1(state[0]),
        .I2(state[2]),
        .O(req_len[5]));
  (* SOFT_HLUTNM = "soft_lutpair1953" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \tx_64.req_len[6]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [6]),
        .I1(state[0]),
        .I2(state[2]),
        .O(req_len[6]));
  (* SOFT_HLUTNM = "soft_lutpair1953" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \tx_64.req_len[7]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [7]),
        .I1(state[0]),
        .I2(state[2]),
        .O(req_len[7]));
  (* SOFT_HLUTNM = "soft_lutpair1954" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \tx_64.req_len[8]_i_1 
       (.I0(\tx_64.req_addr_reg[63]_0 [8]),
        .I1(state[0]),
        .I2(state[2]),
        .O(req_len[8]));
  LUT3 #(
    .INIT(8'h0D)) 
    \tx_64.req_len[9]_i_1 
       (.I0(state[2]),
        .I1(state[0]),
        .I2(state[1]),
        .O(\tx_64.req_len[9]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1954" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \tx_64.req_len[9]_i_2 
       (.I0(\tx_64.req_addr_reg[63]_0 [9]),
        .I1(state[0]),
        .I2(state[2]),
        .O(req_len[9]));
  FDRE \tx_64.req_len_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_len[9]_i_1_n_0 ),
        .D(req_len[0]),
        .Q(\tx_64.req_len_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_len[9]_i_1_n_0 ),
        .D(req_len[1]),
        .Q(\tx_64.req_len_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.req_len[9]_i_1_n_0 ),
        .D(req_len[2]),
        .Q(\tx_64.req_len_reg_n_0_[2] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[3] 
       (.C(user_clk_out),
        .CE(\tx_64.req_len[9]_i_1_n_0 ),
        .D(req_len[3]),
        .Q(\tx_64.req_len_reg_n_0_[3] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[4] 
       (.C(user_clk_out),
        .CE(\tx_64.req_len[9]_i_1_n_0 ),
        .D(req_len[4]),
        .Q(\tx_64.req_len_reg_n_0_[4] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[5] 
       (.C(user_clk_out),
        .CE(\tx_64.req_len[9]_i_1_n_0 ),
        .D(req_len[5]),
        .Q(\tx_64.req_len_reg_n_0_[5] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[6] 
       (.C(user_clk_out),
        .CE(\tx_64.req_len[9]_i_1_n_0 ),
        .D(req_len[6]),
        .Q(\tx_64.req_len_reg_n_0_[6] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[7] 
       (.C(user_clk_out),
        .CE(\tx_64.req_len[9]_i_1_n_0 ),
        .D(req_len[7]),
        .Q(\tx_64.req_len_reg_n_0_[7] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[8] 
       (.C(user_clk_out),
        .CE(\tx_64.req_len[9]_i_1_n_0 ),
        .D(req_len[8]),
        .Q(\tx_64.req_len_reg_n_0_[8] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[9] 
       (.C(user_clk_out),
        .CE(\tx_64.req_len[9]_i_1_n_0 ),
        .D(req_len[9]),
        .Q(\tx_64.req_len_reg_n_0_[9] ),
        .R(user_reset_out));
  FDRE \tx_64.seq_num_reg[0] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[8]),
        .Q(seq_num[0]),
        .R(user_reset_out));
  FDRE \tx_64.seq_num_reg[1] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[9]),
        .Q(seq_num[1]),
        .R(user_reset_out));
  FDRE \tx_64.seq_num_reg[2] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[10]),
        .Q(seq_num[2]),
        .R(user_reset_out));
  FDRE \tx_64.seq_num_reg[3] 
       (.C(user_clk_out),
        .CE(req_at),
        .D(s_axis_rq_tuser[11]),
        .Q(seq_num[3]),
        .R(user_reset_out));
  LUT5 #(
    .INIT(32'h40000000)) 
    \tx_64.wr_data[63]_i_1 
       (.I0(state[2]),
        .I1(state[1]),
        .I2(s_axis_tx_tready),
        .I3(transfer_SM[1]),
        .I4(transfer_SM[0]),
        .O(wr_data));
  FDRE \tx_64.wr_data_reg[0] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [0]),
        .Q(wreq_data_le[24]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[10] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [10]),
        .Q(wreq_data_le[18]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[11] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [11]),
        .Q(wreq_data_le[19]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[12] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [12]),
        .Q(wreq_data_le[20]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[13] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [13]),
        .Q(wreq_data_le[21]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[14] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [14]),
        .Q(wreq_data_le[22]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[15] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [15]),
        .Q(wreq_data_le[23]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[16] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [16]),
        .Q(wreq_data_le[8]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[17] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [17]),
        .Q(wreq_data_le[9]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[18] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [18]),
        .Q(wreq_data_le[10]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[19] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [19]),
        .Q(wreq_data_le[11]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[1] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [1]),
        .Q(wreq_data_le[25]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[20] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [20]),
        .Q(wreq_data_le[12]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[21] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [21]),
        .Q(wreq_data_le[13]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[22] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [22]),
        .Q(wreq_data_le[14]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[23] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [23]),
        .Q(wreq_data_le[15]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[24] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [24]),
        .Q(wreq_data_le[0]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[25] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [25]),
        .Q(wreq_data_le[1]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[26] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [26]),
        .Q(wreq_data_le[2]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[27] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [27]),
        .Q(wreq_data_le[3]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[28] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [28]),
        .Q(wreq_data_le[4]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[29] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [29]),
        .Q(wreq_data_le[5]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[2] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [2]),
        .Q(wreq_data_le[26]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[30] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [30]),
        .Q(wreq_data_le[6]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[31] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [31]),
        .Q(wreq_data_le[7]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[32] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [32]),
        .Q(wreq_data_le[56]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[33] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [33]),
        .Q(wreq_data_le[57]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[34] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [34]),
        .Q(wreq_data_le[58]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[35] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [35]),
        .Q(wreq_data_le[59]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[36] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [36]),
        .Q(wreq_data_le[60]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[37] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [37]),
        .Q(wreq_data_le[61]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[38] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [38]),
        .Q(wreq_data_le[62]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[39] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [39]),
        .Q(wreq_data_le[63]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[3] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [3]),
        .Q(wreq_data_le[27]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[40] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [40]),
        .Q(wreq_data_le[48]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[41] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [41]),
        .Q(wreq_data_le[49]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[42] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [42]),
        .Q(wreq_data_le[50]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[43] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [43]),
        .Q(wreq_data_le[51]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[44] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [44]),
        .Q(wreq_data_le[52]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[45] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [45]),
        .Q(wreq_data_le[53]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[46] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [46]),
        .Q(wreq_data_le[54]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[47] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [47]),
        .Q(wreq_data_le[55]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[48] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [48]),
        .Q(wreq_data_le[40]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[49] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [49]),
        .Q(wreq_data_le[41]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[4] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [4]),
        .Q(wreq_data_le[28]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[50] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [50]),
        .Q(wreq_data_le[42]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[51] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [51]),
        .Q(wreq_data_le[43]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[52] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [52]),
        .Q(wreq_data_le[44]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[53] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [53]),
        .Q(wreq_data_le[45]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[54] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [54]),
        .Q(wreq_data_le[46]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[55] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [55]),
        .Q(wreq_data_le[47]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[56] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [56]),
        .Q(wreq_data_le[32]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[57] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [57]),
        .Q(wreq_data_le[33]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[58] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [58]),
        .Q(wreq_data_le[34]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[59] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [59]),
        .Q(wreq_data_le[35]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[5] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [5]),
        .Q(wreq_data_le[29]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[60] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [60]),
        .Q(wreq_data_le[36]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[61] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [61]),
        .Q(wreq_data_le[37]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[62] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [62]),
        .Q(wreq_data_le[38]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[63] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [63]),
        .Q(wreq_data_le[39]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[6] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [6]),
        .Q(wreq_data_le[30]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[7] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [7]),
        .Q(wreq_data_le[31]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[8] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [8]),
        .Q(wreq_data_le[16]),
        .R(user_reset_out));
  FDRE \tx_64.wr_data_reg[9] 
       (.C(user_clk_out),
        .CE(wr_data),
        .D(\tx_64.req_addr_reg[63]_0 [9]),
        .Q(wreq_data_le[17]),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair1936" *) 
  LUT5 #(
    .INIT(32'hFFFFFFA1)) 
    udma_wrapper_i_1
       (.I0(state[2]),
        .I1(state[0]),
        .I2(state[1]),
        .I3(s_axis_tx_req_tready),
        .I4(user_reset_out),
        .O(\m_axis_rq\.tready ));
  LUT5 #(
    .INIT(32'h80000000)) 
    udma_wrapper_i_149
       (.I0(s_axis_tx_req_tlast),
        .I1(s_axis_tx_tready),
        .I2(transfer_SM[1]),
        .I3(transfer_SM[0]),
        .I4(seq_num[3]),
        .O(\pcie_dma_in\.pcie_rq_seq_num0 [3]));
  LUT5 #(
    .INIT(32'h80000000)) 
    udma_wrapper_i_150
       (.I0(s_axis_tx_req_tlast),
        .I1(s_axis_tx_tready),
        .I2(transfer_SM[1]),
        .I3(transfer_SM[0]),
        .I4(seq_num[2]),
        .O(\pcie_dma_in\.pcie_rq_seq_num0 [2]));
  LUT5 #(
    .INIT(32'h80000000)) 
    udma_wrapper_i_151
       (.I0(s_axis_tx_req_tlast),
        .I1(s_axis_tx_tready),
        .I2(transfer_SM[1]),
        .I3(transfer_SM[0]),
        .I4(seq_num[1]),
        .O(\pcie_dma_in\.pcie_rq_seq_num0 [1]));
  LUT5 #(
    .INIT(32'h80000000)) 
    udma_wrapper_i_152
       (.I0(s_axis_tx_req_tlast),
        .I1(s_axis_tx_tready),
        .I2(transfer_SM[1]),
        .I3(transfer_SM[0]),
        .I4(seq_num[0]),
        .O(\pcie_dma_in\.pcie_rq_seq_num0 [0]));
  LUT6 #(
    .INIT(64'h0000000000EAFF00)) 
    udma_wrapper_i_240
       (.I0(udma_wrapper_i_264_n_0),
        .I1(state[0]),
        .I2(udma_wrapper_i_265_n_0),
        .I3(state[2]),
        .I4(state[1]),
        .I5(user_reset_out),
        .O(s_axis_tx_req_tlast));
  LUT6 #(
    .INIT(64'h0000000000200000)) 
    udma_wrapper_i_264
       (.I0(udma_wrapper_i_281_n_0),
        .I1(udma_wrapper_i_282_n_0),
        .I2(udma_wrapper_i_283_n_0),
        .I3(state[0]),
        .I4(\tx_64.req_len_reg_n_0_[0] ),
        .I5(\tx_64.req_len_reg_n_0_[1] ),
        .O(udma_wrapper_i_264_n_0));
  CARRY4 udma_wrapper_i_265
       (.CI(1'b0),
        .CO({udma_wrapper_i_265_n_0,udma_wrapper_i_265_n_1,udma_wrapper_i_265_n_2,udma_wrapper_i_265_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_udma_wrapper_i_265_O_UNCONNECTED[3:0]),
        .S({udma_wrapper_i_284_n_0,udma_wrapper_i_285_n_0,udma_wrapper_i_286_n_0,udma_wrapper_i_287_n_0}));
  LUT2 #(
    .INIT(4'h1)) 
    udma_wrapper_i_281
       (.I0(\tx_64.req_len_reg_n_0_[2] ),
        .I1(\tx_64.req_len_reg_n_0_[3] ),
        .O(udma_wrapper_i_281_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1955" *) 
  LUT2 #(
    .INIT(4'hE)) 
    udma_wrapper_i_282
       (.I0(\tx_64.req_len_reg_n_0_[4] ),
        .I1(\tx_64.req_len_reg_n_0_[5] ),
        .O(udma_wrapper_i_282_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1943" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    udma_wrapper_i_283
       (.I0(\tx_64.req_len_reg_n_0_[9] ),
        .I1(\tx_64.req_len_reg_n_0_[8] ),
        .I2(\tx_64.req_len_reg_n_0_[7] ),
        .I3(\tx_64.req_len_reg_n_0_[6] ),
        .O(udma_wrapper_i_283_n_0));
  LUT4 #(
    .INIT(16'h1086)) 
    udma_wrapper_i_284
       (.I0(\tx_64.current_dw_count[9]_i_2_n_0 ),
        .I1(\tx_64.req_len_reg_n_0_[9] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[9] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[10] ),
        .O(udma_wrapper_i_284_n_0));
  LUT6 #(
    .INIT(64'h9200000404009200)) 
    udma_wrapper_i_285
       (.I0(\tx_64.current_dw_count[6]_i_2_n_0 ),
        .I1(\tx_64.current_dw_count_reg_n_0_[6] ),
        .I2(\tx_64.req_len_reg_n_0_[6] ),
        .I3(udma_wrapper_i_288_n_0),
        .I4(\tx_64.req_len_reg_n_0_[7] ),
        .I5(\tx_64.current_dw_count_reg_n_0_[7] ),
        .O(udma_wrapper_i_285_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0001)) 
    udma_wrapper_i_286
       (.I0(\tx_64.req_len_reg_n_0_[3] ),
        .I1(\tx_64.req_len_reg_n_0_[4] ),
        .I2(\tx_64.req_len_reg_n_0_[5] ),
        .I3(\tx_64.current_dw_count[6]_i_2_n_0 ),
        .I4(udma_wrapper_i_289_n_0),
        .I5(udma_wrapper_i_290_n_0),
        .O(udma_wrapper_i_286_n_0));
  LUT6 #(
    .INIT(64'h2100002148000048)) 
    udma_wrapper_i_287
       (.I0(\tx_64.req_len_reg_n_0_[2] ),
        .I1(\tx_64.current_dw_count_reg_n_0_[1] ),
        .I2(\tx_64.current_dw_count_reg_n_0_[2] ),
        .I3(\tx_64.req_len_reg_n_0_[0] ),
        .I4(\tx_64.current_dw_count_reg_n_0_[0] ),
        .I5(\tx_64.req_len_reg_n_0_[1] ),
        .O(udma_wrapper_i_287_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1956" *) 
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_288
       (.I0(\tx_64.current_dw_count_reg_n_0_[8] ),
        .I1(\tx_64.req_len_reg_n_0_[8] ),
        .O(udma_wrapper_i_288_n_0));
  LUT6 #(
    .INIT(64'h8200008200008200)) 
    udma_wrapper_i_289
       (.I0(udma_wrapper_i_291_n_0),
        .I1(\tx_64.current_dw_count_reg_n_0_[4] ),
        .I2(\tx_64.req_len_reg_n_0_[4] ),
        .I3(\tx_64.req_len_reg_n_0_[3] ),
        .I4(\tx_64.current_dw_count_reg_n_0_[3] ),
        .I5(\tx_64.current_dw_count[3]_i_2_n_0 ),
        .O(udma_wrapper_i_289_n_0));
  LUT6 #(
    .INIT(64'h0100000400010000)) 
    udma_wrapper_i_290
       (.I0(\tx_64.current_dw_count[4]_i_2_n_0 ),
        .I1(\tx_64.current_dw_count_reg_n_0_[4] ),
        .I2(\tx_64.req_len_reg_n_0_[3] ),
        .I3(\tx_64.current_dw_count_reg_n_0_[5] ),
        .I4(\tx_64.req_len_reg_n_0_[4] ),
        .I5(\tx_64.req_len_reg_n_0_[5] ),
        .O(udma_wrapper_i_290_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1955" *) 
  LUT2 #(
    .INIT(4'h9)) 
    udma_wrapper_i_291
       (.I0(\tx_64.current_dw_count_reg_n_0_[5] ),
        .I1(\tx_64.req_len_reg_n_0_[5] ),
        .O(udma_wrapper_i_291_n_0));
endmodule

(* CHECK_LICENSE_TYPE = "pcie2_fifo_generator_dma_cpl,fifo_generator_v13_1_5,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "pcie2_fifo_generator_dma_cpl" *) 
(* X_CORE_INFO = "fifo_generator_v13_1_5,Vivado 2024.1" *) 
module xdma_0_pcie2_fifo_generator_dma_cpl
   (s_aclk,
    s_aresetn,
    s_axis_tvalid,
    s_axis_tready,
    s_axis_tdata,
    s_axis_tkeep,
    s_axis_tlast,
    s_axis_tuser,
    m_axis_tvalid,
    m_axis_tready,
    m_axis_tdata,
    m_axis_tkeep,
    m_axis_tlast,
    m_axis_tuser,
    axis_prog_full);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 slave_aclk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slave_aclk, ASSOCIATED_BUSIF S_AXIS:S_AXI, ASSOCIATED_RESET s_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input s_aclk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 slave_aresetn RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slave_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_aresetn;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input s_axis_tvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output s_axis_tready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [63:0]s_axis_tdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *) input [7:0]s_axis_tkeep;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) input s_axis_tlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input [21:0]s_axis_tuser;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output m_axis_tvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input m_axis_tready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [63:0]m_axis_tdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *) output [7:0]m_axis_tkeep;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *) output m_axis_tlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *) output [21:0]m_axis_tuser;
  output axis_prog_full;

  wire \<const0> ;
  wire [63:0]m_axis_tdata;
  wire m_axis_tlast;
  wire m_axis_tready;
  wire m_axis_tvalid;
  wire s_aclk;
  wire s_aresetn;
  wire [63:0]s_axis_tdata;
  wire [7:0]s_axis_tkeep;
  wire s_axis_tlast;
  wire s_axis_tready;
  wire [21:0]s_axis_tuser;
  wire s_axis_tvalid;
  wire NLW_U0_almost_empty_UNCONNECTED;
  wire NLW_U0_almost_full_UNCONNECTED;
  wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
  wire NLW_U0_axi_ar_overflow_UNCONNECTED;
  wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
  wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
  wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
  wire NLW_U0_axi_ar_underflow_UNCONNECTED;
  wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
  wire NLW_U0_axi_aw_overflow_UNCONNECTED;
  wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
  wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
  wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
  wire NLW_U0_axi_aw_underflow_UNCONNECTED;
  wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
  wire NLW_U0_axi_b_overflow_UNCONNECTED;
  wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
  wire NLW_U0_axi_b_prog_full_UNCONNECTED;
  wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
  wire NLW_U0_axi_b_underflow_UNCONNECTED;
  wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
  wire NLW_U0_axi_r_overflow_UNCONNECTED;
  wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
  wire NLW_U0_axi_r_prog_full_UNCONNECTED;
  wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
  wire NLW_U0_axi_r_underflow_UNCONNECTED;
  wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
  wire NLW_U0_axi_w_overflow_UNCONNECTED;
  wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
  wire NLW_U0_axi_w_prog_full_UNCONNECTED;
  wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
  wire NLW_U0_axi_w_underflow_UNCONNECTED;
  wire NLW_U0_axis_dbiterr_UNCONNECTED;
  wire NLW_U0_axis_overflow_UNCONNECTED;
  wire NLW_U0_axis_prog_empty_UNCONNECTED;
  wire NLW_U0_axis_prog_full_UNCONNECTED;
  wire NLW_U0_axis_sbiterr_UNCONNECTED;
  wire NLW_U0_axis_underflow_UNCONNECTED;
  wire NLW_U0_dbiterr_UNCONNECTED;
  wire NLW_U0_empty_UNCONNECTED;
  wire NLW_U0_full_UNCONNECTED;
  wire NLW_U0_m_axi_arvalid_UNCONNECTED;
  wire NLW_U0_m_axi_awvalid_UNCONNECTED;
  wire NLW_U0_m_axi_bready_UNCONNECTED;
  wire NLW_U0_m_axi_rready_UNCONNECTED;
  wire NLW_U0_m_axi_wlast_UNCONNECTED;
  wire NLW_U0_m_axi_wvalid_UNCONNECTED;
  wire NLW_U0_overflow_UNCONNECTED;
  wire NLW_U0_prog_empty_UNCONNECTED;
  wire NLW_U0_prog_full_UNCONNECTED;
  wire NLW_U0_rd_rst_busy_UNCONNECTED;
  wire NLW_U0_s_axi_arready_UNCONNECTED;
  wire NLW_U0_s_axi_awready_UNCONNECTED;
  wire NLW_U0_s_axi_bvalid_UNCONNECTED;
  wire NLW_U0_s_axi_rlast_UNCONNECTED;
  wire NLW_U0_s_axi_rvalid_UNCONNECTED;
  wire NLW_U0_s_axi_wready_UNCONNECTED;
  wire NLW_U0_sbiterr_UNCONNECTED;
  wire NLW_U0_underflow_UNCONNECTED;
  wire NLW_U0_valid_UNCONNECTED;
  wire NLW_U0_wr_ack_UNCONNECTED;
  wire NLW_U0_wr_rst_busy_UNCONNECTED;
  wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
  wire [6:0]NLW_U0_axis_data_count_UNCONNECTED;
  wire [6:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
  wire [6:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
  wire [9:0]NLW_U0_data_count_UNCONNECTED;
  wire [17:0]NLW_U0_dout_UNCONNECTED;
  wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
  wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
  wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
  wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
  wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
  wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
  wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
  wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
  wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
  wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
  wire [7:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
  wire [7:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
  wire [21:0]NLW_U0_m_axis_tuser_UNCONNECTED;
  wire [9:0]NLW_U0_rd_data_count_UNCONNECTED;
  wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
  wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
  wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
  wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
  wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
  wire [9:0]NLW_U0_wr_data_count_UNCONNECTED;

  assign axis_prog_full = \<const0> ;
  assign m_axis_tkeep[7] = \<const0> ;
  assign m_axis_tkeep[6] = \<const0> ;
  assign m_axis_tkeep[5] = \<const0> ;
  assign m_axis_tkeep[4] = \<const0> ;
  assign m_axis_tkeep[3] = \<const0> ;
  assign m_axis_tkeep[2] = \<const0> ;
  assign m_axis_tkeep[1] = \<const0> ;
  assign m_axis_tkeep[0] = \<const0> ;
  assign m_axis_tuser[21] = \<const0> ;
  assign m_axis_tuser[20] = \<const0> ;
  assign m_axis_tuser[19] = \<const0> ;
  assign m_axis_tuser[18] = \<const0> ;
  assign m_axis_tuser[17] = \<const0> ;
  assign m_axis_tuser[16] = \<const0> ;
  assign m_axis_tuser[15] = \<const0> ;
  assign m_axis_tuser[14] = \<const0> ;
  assign m_axis_tuser[13] = \<const0> ;
  assign m_axis_tuser[12] = \<const0> ;
  assign m_axis_tuser[11] = \<const0> ;
  assign m_axis_tuser[10] = \<const0> ;
  assign m_axis_tuser[9] = \<const0> ;
  assign m_axis_tuser[8] = \<const0> ;
  assign m_axis_tuser[7] = \<const0> ;
  assign m_axis_tuser[6] = \<const0> ;
  assign m_axis_tuser[5] = \<const0> ;
  assign m_axis_tuser[4] = \<const0> ;
  assign m_axis_tuser[3] = \<const0> ;
  assign m_axis_tuser[2] = \<const0> ;
  assign m_axis_tuser[1] = \<const0> ;
  assign m_axis_tuser[0] = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_ADD_NGC_CONSTRAINT = "0" *) 
  (* C_APPLICATION_TYPE_AXIS = "0" *) 
  (* C_APPLICATION_TYPE_RACH = "0" *) 
  (* C_APPLICATION_TYPE_RDCH = "0" *) 
  (* C_APPLICATION_TYPE_WACH = "0" *) 
  (* C_APPLICATION_TYPE_WDCH = "0" *) 
  (* C_APPLICATION_TYPE_WRCH = "0" *) 
  (* C_AXIS_TDATA_WIDTH = "64" *) 
  (* C_AXIS_TDEST_WIDTH = "1" *) 
  (* C_AXIS_TID_WIDTH = "1" *) 
  (* C_AXIS_TKEEP_WIDTH = "8" *) 
  (* C_AXIS_TSTRB_WIDTH = "8" *) 
  (* C_AXIS_TUSER_WIDTH = "22" *) 
  (* C_AXIS_TYPE = "0" *) 
  (* C_AXI_ADDR_WIDTH = "32" *) 
  (* C_AXI_ARUSER_WIDTH = "1" *) 
  (* C_AXI_AWUSER_WIDTH = "1" *) 
  (* C_AXI_BUSER_WIDTH = "1" *) 
  (* C_AXI_DATA_WIDTH = "64" *) 
  (* C_AXI_ID_WIDTH = "1" *) 
  (* C_AXI_LEN_WIDTH = "8" *) 
  (* C_AXI_LOCK_WIDTH = "1" *) 
  (* C_AXI_RUSER_WIDTH = "1" *) 
  (* C_AXI_TYPE = "1" *) 
  (* C_AXI_WUSER_WIDTH = "1" *) 
  (* C_COMMON_CLOCK = "1" *) 
  (* C_COUNT_TYPE = "0" *) 
  (* C_DATA_COUNT_WIDTH = "10" *) 
  (* C_DEFAULT_VALUE = "BlankString" *) 
  (* C_DIN_WIDTH = "18" *) 
  (* C_DIN_WIDTH_AXIS = "95" *) 
  (* C_DIN_WIDTH_RACH = "32" *) 
  (* C_DIN_WIDTH_RDCH = "64" *) 
  (* C_DIN_WIDTH_WACH = "32" *) 
  (* C_DIN_WIDTH_WDCH = "64" *) 
  (* C_DIN_WIDTH_WRCH = "2" *) 
  (* C_DOUT_RST_VAL = "0" *) 
  (* C_DOUT_WIDTH = "18" *) 
  (* C_ENABLE_RLOCS = "0" *) 
  (* C_ENABLE_RST_SYNC = "1" *) 
  (* C_EN_SAFETY_CKT = "0" *) 
  (* C_ERROR_INJECTION_TYPE = "0" *) 
  (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) 
  (* C_FAMILY = "artix7" *) 
  (* C_FULL_FLAGS_RST_VAL = "1" *) 
  (* C_HAS_ALMOST_EMPTY = "0" *) 
  (* C_HAS_ALMOST_FULL = "0" *) 
  (* C_HAS_AXIS_TDATA = "1" *) 
  (* C_HAS_AXIS_TDEST = "0" *) 
  (* C_HAS_AXIS_TID = "0" *) 
  (* C_HAS_AXIS_TKEEP = "1" *) 
  (* C_HAS_AXIS_TLAST = "1" *) 
  (* C_HAS_AXIS_TREADY = "1" *) 
  (* C_HAS_AXIS_TSTRB = "0" *) 
  (* C_HAS_AXIS_TUSER = "1" *) 
  (* C_HAS_AXI_ARUSER = "0" *) 
  (* C_HAS_AXI_AWUSER = "0" *) 
  (* C_HAS_AXI_BUSER = "0" *) 
  (* C_HAS_AXI_ID = "0" *) 
  (* C_HAS_AXI_RD_CHANNEL = "1" *) 
  (* C_HAS_AXI_RUSER = "0" *) 
  (* C_HAS_AXI_WR_CHANNEL = "1" *) 
  (* C_HAS_AXI_WUSER = "0" *) 
  (* C_HAS_BACKUP = "0" *) 
  (* C_HAS_DATA_COUNT = "0" *) 
  (* C_HAS_DATA_COUNTS_AXIS = "0" *) 
  (* C_HAS_DATA_COUNTS_RACH = "0" *) 
  (* C_HAS_DATA_COUNTS_RDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WACH = "0" *) 
  (* C_HAS_DATA_COUNTS_WDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WRCH = "0" *) 
  (* C_HAS_INT_CLK = "0" *) 
  (* C_HAS_MASTER_CE = "0" *) 
  (* C_HAS_MEMINIT_FILE = "0" *) 
  (* C_HAS_OVERFLOW = "0" *) 
  (* C_HAS_PROG_FLAGS_AXIS = "0" *) 
  (* C_HAS_PROG_FLAGS_RACH = "0" *) 
  (* C_HAS_PROG_FLAGS_RDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WACH = "0" *) 
  (* C_HAS_PROG_FLAGS_WDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WRCH = "0" *) 
  (* C_HAS_RD_DATA_COUNT = "0" *) 
  (* C_HAS_RD_RST = "0" *) 
  (* C_HAS_RST = "1" *) 
  (* C_HAS_SLAVE_CE = "0" *) 
  (* C_HAS_SRST = "0" *) 
  (* C_HAS_UNDERFLOW = "0" *) 
  (* C_HAS_VALID = "0" *) 
  (* C_HAS_WR_ACK = "0" *) 
  (* C_HAS_WR_DATA_COUNT = "0" *) 
  (* C_HAS_WR_RST = "0" *) 
  (* C_IMPLEMENTATION_TYPE = "0" *) 
  (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RACH = "2" *) 
  (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WACH = "2" *) 
  (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WRCH = "2" *) 
  (* C_INIT_WR_PNTR_VAL = "0" *) 
  (* C_INTERFACE_TYPE = "1" *) 
  (* C_MEMORY_TYPE = "1" *) 
  (* C_MIF_FILE_NAME = "BlankString" *) 
  (* C_MSGON_VAL = "1" *) 
  (* C_OPTIMIZATION_MODE = "0" *) 
  (* C_OVERFLOW_LOW = "0" *) 
  (* C_POWER_SAVING_MODE = "0" *) 
  (* C_PRELOAD_LATENCY = "1" *) 
  (* C_PRELOAD_REGS = "0" *) 
  (* C_PRIM_FIFO_TYPE = "4kx4" *) 
  (* C_PRIM_FIFO_TYPE_AXIS = "512x72" *) 
  (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) 
  (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) 
  (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "62" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "14" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "14" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "14" *) 
  (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) 
  (* C_PROG_EMPTY_TYPE = "0" *) 
  (* C_PROG_EMPTY_TYPE_AXIS = "0" *) 
  (* C_PROG_EMPTY_TYPE_RACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_RDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WRCH = "0" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "45" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "15" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "15" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "15" *) 
  (* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *) 
  (* C_PROG_FULL_TYPE = "0" *) 
  (* C_PROG_FULL_TYPE_AXIS = "1" *) 
  (* C_PROG_FULL_TYPE_RACH = "0" *) 
  (* C_PROG_FULL_TYPE_RDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WACH = "0" *) 
  (* C_PROG_FULL_TYPE_WDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WRCH = "0" *) 
  (* C_RACH_TYPE = "0" *) 
  (* C_RDCH_TYPE = "0" *) 
  (* C_RD_DATA_COUNT_WIDTH = "10" *) 
  (* C_RD_DEPTH = "1024" *) 
  (* C_RD_FREQ = "1" *) 
  (* C_RD_PNTR_WIDTH = "10" *) 
  (* C_REG_SLICE_MODE_AXIS = "0" *) 
  (* C_REG_SLICE_MODE_RACH = "0" *) 
  (* C_REG_SLICE_MODE_RDCH = "0" *) 
  (* C_REG_SLICE_MODE_WACH = "0" *) 
  (* C_REG_SLICE_MODE_WDCH = "0" *) 
  (* C_REG_SLICE_MODE_WRCH = "0" *) 
  (* C_SELECT_XPM = "0" *) 
  (* C_SYNCHRONIZER_STAGE = "2" *) 
  (* C_UNDERFLOW_LOW = "0" *) 
  (* C_USE_COMMON_OVERFLOW = "0" *) 
  (* C_USE_COMMON_UNDERFLOW = "0" *) 
  (* C_USE_DEFAULT_SETTINGS = "0" *) 
  (* C_USE_DOUT_RST = "1" *) 
  (* C_USE_ECC = "0" *) 
  (* C_USE_ECC_AXIS = "0" *) 
  (* C_USE_ECC_RACH = "0" *) 
  (* C_USE_ECC_RDCH = "0" *) 
  (* C_USE_ECC_WACH = "0" *) 
  (* C_USE_ECC_WDCH = "0" *) 
  (* C_USE_ECC_WRCH = "0" *) 
  (* C_USE_EMBEDDED_REG = "0" *) 
  (* C_USE_FIFO16_FLAGS = "0" *) 
  (* C_USE_FWFT_DATA_COUNT = "0" *) 
  (* C_USE_PIPELINE_REG = "0" *) 
  (* C_VALID_LOW = "0" *) 
  (* C_WACH_TYPE = "0" *) 
  (* C_WDCH_TYPE = "0" *) 
  (* C_WRCH_TYPE = "0" *) 
  (* C_WR_ACK_LOW = "0" *) 
  (* C_WR_DATA_COUNT_WIDTH = "10" *) 
  (* C_WR_DEPTH = "1024" *) 
  (* C_WR_DEPTH_AXIS = "64" *) 
  (* C_WR_DEPTH_RACH = "16" *) 
  (* C_WR_DEPTH_RDCH = "1024" *) 
  (* C_WR_DEPTH_WACH = "16" *) 
  (* C_WR_DEPTH_WDCH = "1024" *) 
  (* C_WR_DEPTH_WRCH = "16" *) 
  (* C_WR_FREQ = "1" *) 
  (* C_WR_PNTR_WIDTH = "10" *) 
  (* C_WR_PNTR_WIDTH_AXIS = "6" *) 
  (* C_WR_PNTR_WIDTH_RACH = "4" *) 
  (* C_WR_PNTR_WIDTH_RDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WACH = "4" *) 
  (* C_WR_PNTR_WIDTH_WDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WRCH = "4" *) 
  (* C_WR_RESPONSE_LATENCY = "1" *) 
  (* is_du_within_envelope = "true" *) 
  xdma_0_fifo_generator_v13_1_5 U0
       (.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
        .almost_full(NLW_U0_almost_full_UNCONNECTED),
        .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
        .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
        .axi_ar_injectdbiterr(1'b0),
        .axi_ar_injectsbiterr(1'b0),
        .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
        .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
        .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
        .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
        .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
        .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
        .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
        .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
        .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
        .axi_aw_injectdbiterr(1'b0),
        .axi_aw_injectsbiterr(1'b0),
        .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
        .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
        .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
        .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
        .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
        .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
        .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
        .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
        .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
        .axi_b_injectdbiterr(1'b0),
        .axi_b_injectsbiterr(1'b0),
        .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
        .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
        .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
        .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
        .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
        .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
        .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
        .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
        .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
        .axi_r_injectdbiterr(1'b0),
        .axi_r_injectsbiterr(1'b0),
        .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
        .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
        .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
        .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
        .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
        .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
        .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
        .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
        .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
        .axi_w_injectdbiterr(1'b0),
        .axi_w_injectsbiterr(1'b0),
        .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
        .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
        .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
        .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
        .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
        .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
        .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
        .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[6:0]),
        .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
        .axis_injectdbiterr(1'b0),
        .axis_injectsbiterr(1'b0),
        .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
        .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
        .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
        .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[6:0]),
        .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
        .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
        .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[6:0]),
        .backup(1'b0),
        .backup_marker(1'b0),
        .clk(1'b0),
        .data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
        .dbiterr(NLW_U0_dbiterr_UNCONNECTED),
        .din({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .dout(NLW_U0_dout_UNCONNECTED[17:0]),
        .empty(NLW_U0_empty_UNCONNECTED),
        .full(NLW_U0_full_UNCONNECTED),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .int_clk(1'b0),
        .m_aclk(1'b0),
        .m_aclk_en(1'b0),
        .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
        .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
        .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
        .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
        .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
        .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
        .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
        .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
        .m_axi_arready(1'b0),
        .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
        .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
        .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
        .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
        .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
        .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
        .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
        .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
        .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
        .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
        .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
        .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
        .m_axi_awready(1'b0),
        .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
        .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
        .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
        .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
        .m_axi_bid(1'b0),
        .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
        .m_axi_bresp({1'b0,1'b0}),
        .m_axi_buser(1'b0),
        .m_axi_bvalid(1'b0),
        .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rid(1'b0),
        .m_axi_rlast(1'b0),
        .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
        .m_axi_rresp({1'b0,1'b0}),
        .m_axi_ruser(1'b0),
        .m_axi_rvalid(1'b0),
        .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
        .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
        .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
        .m_axi_wready(1'b0),
        .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
        .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
        .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
        .m_axis_tdata(m_axis_tdata),
        .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
        .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
        .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[7:0]),
        .m_axis_tlast(m_axis_tlast),
        .m_axis_tready(m_axis_tready),
        .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[7:0]),
        .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[21:0]),
        .m_axis_tvalid(m_axis_tvalid),
        .overflow(NLW_U0_overflow_UNCONNECTED),
        .prog_empty(NLW_U0_prog_empty_UNCONNECTED),
        .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full(NLW_U0_prog_full_UNCONNECTED),
        .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rd_clk(1'b0),
        .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[9:0]),
        .rd_en(1'b0),
        .rd_rst(1'b0),
        .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
        .rst(1'b0),
        .s_aclk(s_aclk),
        .s_aclk_en(1'b0),
        .s_aresetn(s_aresetn),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arid(1'b0),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlock(1'b0),
        .s_axi_arprot({1'b0,1'b0,1'b0}),
        .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
        .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_aruser(1'b0),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awid(1'b0),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlock(1'b0),
        .s_axi_awprot({1'b0,1'b0,1'b0}),
        .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
        .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awuser(1'b0),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
        .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
        .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
        .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
        .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
        .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wid(1'b0),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wuser(1'b0),
        .s_axi_wvalid(1'b0),
        .s_axis_tdata(s_axis_tdata),
        .s_axis_tdest(1'b0),
        .s_axis_tid(1'b0),
        .s_axis_tkeep({s_axis_tkeep[7:4],1'b1,1'b1,1'b1,1'b1}),
        .s_axis_tlast(s_axis_tlast),
        .s_axis_tready(s_axis_tready),
        .s_axis_tstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tuser({s_axis_tuser[21],1'b0,s_axis_tuser[19:17],1'b0,1'b0,s_axis_tuser[14],1'b0,1'b0,1'b0,1'b0,1'b0,s_axis_tuser[8:0]}),
        .s_axis_tvalid(s_axis_tvalid),
        .sbiterr(NLW_U0_sbiterr_UNCONNECTED),
        .sleep(1'b0),
        .srst(1'b0),
        .underflow(NLW_U0_underflow_UNCONNECTED),
        .valid(NLW_U0_valid_UNCONNECTED),
        .wr_ack(NLW_U0_wr_ack_UNCONNECTED),
        .wr_clk(1'b0),
        .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[9:0]),
        .wr_en(1'b0),
        .wr_rst(1'b0),
        .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule

(* CHECK_LICENSE_TYPE = "pcie2_fifo_generator_tgt_brdg,fifo_generator_v13_1_5,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "pcie2_fifo_generator_tgt_brdg" *) 
(* X_CORE_INFO = "fifo_generator_v13_1_5,Vivado 2024.1" *) 
module xdma_0_pcie2_fifo_generator_tgt_brdg
   (s_aclk,
    s_aresetn,
    s_axis_tvalid,
    s_axis_tready,
    s_axis_tdata,
    s_axis_tkeep,
    s_axis_tlast,
    s_axis_tuser,
    m_axis_tvalid,
    m_axis_tready,
    m_axis_tdata,
    m_axis_tkeep,
    m_axis_tlast,
    m_axis_tuser,
    axis_prog_full);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 slave_aclk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slave_aclk, ASSOCIATED_BUSIF S_AXIS:S_AXI, ASSOCIATED_RESET s_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input s_aclk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 slave_aresetn RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slave_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_aresetn;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input s_axis_tvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output s_axis_tready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [63:0]s_axis_tdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *) input [7:0]s_axis_tkeep;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) input s_axis_tlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input [21:0]s_axis_tuser;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output m_axis_tvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input m_axis_tready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [63:0]m_axis_tdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *) output [7:0]m_axis_tkeep;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *) output m_axis_tlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *) output [21:0]m_axis_tuser;
  output axis_prog_full;

  wire \<const0> ;
  wire [63:0]m_axis_tdata;
  wire m_axis_tlast;
  wire m_axis_tready;
  wire [6:2]\^m_axis_tuser ;
  wire m_axis_tvalid;
  wire s_aclk;
  wire s_aresetn;
  wire [63:0]s_axis_tdata;
  wire [7:0]s_axis_tkeep;
  wire s_axis_tlast;
  wire s_axis_tready;
  wire [21:0]s_axis_tuser;
  wire s_axis_tvalid;
  wire NLW_U0_almost_empty_UNCONNECTED;
  wire NLW_U0_almost_full_UNCONNECTED;
  wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
  wire NLW_U0_axi_ar_overflow_UNCONNECTED;
  wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
  wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
  wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
  wire NLW_U0_axi_ar_underflow_UNCONNECTED;
  wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
  wire NLW_U0_axi_aw_overflow_UNCONNECTED;
  wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
  wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
  wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
  wire NLW_U0_axi_aw_underflow_UNCONNECTED;
  wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
  wire NLW_U0_axi_b_overflow_UNCONNECTED;
  wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
  wire NLW_U0_axi_b_prog_full_UNCONNECTED;
  wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
  wire NLW_U0_axi_b_underflow_UNCONNECTED;
  wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
  wire NLW_U0_axi_r_overflow_UNCONNECTED;
  wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
  wire NLW_U0_axi_r_prog_full_UNCONNECTED;
  wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
  wire NLW_U0_axi_r_underflow_UNCONNECTED;
  wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
  wire NLW_U0_axi_w_overflow_UNCONNECTED;
  wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
  wire NLW_U0_axi_w_prog_full_UNCONNECTED;
  wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
  wire NLW_U0_axi_w_underflow_UNCONNECTED;
  wire NLW_U0_axis_dbiterr_UNCONNECTED;
  wire NLW_U0_axis_overflow_UNCONNECTED;
  wire NLW_U0_axis_prog_empty_UNCONNECTED;
  wire NLW_U0_axis_prog_full_UNCONNECTED;
  wire NLW_U0_axis_sbiterr_UNCONNECTED;
  wire NLW_U0_axis_underflow_UNCONNECTED;
  wire NLW_U0_dbiterr_UNCONNECTED;
  wire NLW_U0_empty_UNCONNECTED;
  wire NLW_U0_full_UNCONNECTED;
  wire NLW_U0_m_axi_arvalid_UNCONNECTED;
  wire NLW_U0_m_axi_awvalid_UNCONNECTED;
  wire NLW_U0_m_axi_bready_UNCONNECTED;
  wire NLW_U0_m_axi_rready_UNCONNECTED;
  wire NLW_U0_m_axi_wlast_UNCONNECTED;
  wire NLW_U0_m_axi_wvalid_UNCONNECTED;
  wire NLW_U0_overflow_UNCONNECTED;
  wire NLW_U0_prog_empty_UNCONNECTED;
  wire NLW_U0_prog_full_UNCONNECTED;
  wire NLW_U0_rd_rst_busy_UNCONNECTED;
  wire NLW_U0_s_axi_arready_UNCONNECTED;
  wire NLW_U0_s_axi_awready_UNCONNECTED;
  wire NLW_U0_s_axi_bvalid_UNCONNECTED;
  wire NLW_U0_s_axi_rlast_UNCONNECTED;
  wire NLW_U0_s_axi_rvalid_UNCONNECTED;
  wire NLW_U0_s_axi_wready_UNCONNECTED;
  wire NLW_U0_sbiterr_UNCONNECTED;
  wire NLW_U0_underflow_UNCONNECTED;
  wire NLW_U0_valid_UNCONNECTED;
  wire NLW_U0_wr_ack_UNCONNECTED;
  wire NLW_U0_wr_rst_busy_UNCONNECTED;
  wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axis_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
  wire [9:0]NLW_U0_data_count_UNCONNECTED;
  wire [17:0]NLW_U0_dout_UNCONNECTED;
  wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
  wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
  wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
  wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
  wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
  wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
  wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
  wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
  wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
  wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
  wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
  wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
  wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
  wire [7:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
  wire [7:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
  wire [21:0]NLW_U0_m_axis_tuser_UNCONNECTED;
  wire [9:0]NLW_U0_rd_data_count_UNCONNECTED;
  wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
  wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
  wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
  wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
  wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
  wire [9:0]NLW_U0_wr_data_count_UNCONNECTED;

  assign axis_prog_full = \<const0> ;
  assign m_axis_tkeep[7] = \<const0> ;
  assign m_axis_tkeep[6] = \<const0> ;
  assign m_axis_tkeep[5] = \<const0> ;
  assign m_axis_tkeep[4] = \<const0> ;
  assign m_axis_tkeep[3] = \<const0> ;
  assign m_axis_tkeep[2] = \<const0> ;
  assign m_axis_tkeep[1] = \<const0> ;
  assign m_axis_tkeep[0] = \<const0> ;
  assign m_axis_tuser[21] = \<const0> ;
  assign m_axis_tuser[20] = \<const0> ;
  assign m_axis_tuser[19] = \<const0> ;
  assign m_axis_tuser[18] = \<const0> ;
  assign m_axis_tuser[17] = \<const0> ;
  assign m_axis_tuser[16] = \<const0> ;
  assign m_axis_tuser[15] = \<const0> ;
  assign m_axis_tuser[14] = \<const0> ;
  assign m_axis_tuser[13] = \<const0> ;
  assign m_axis_tuser[12] = \<const0> ;
  assign m_axis_tuser[11] = \<const0> ;
  assign m_axis_tuser[10] = \<const0> ;
  assign m_axis_tuser[9] = \<const0> ;
  assign m_axis_tuser[8] = \<const0> ;
  assign m_axis_tuser[7] = \<const0> ;
  assign m_axis_tuser[6:2] = \^m_axis_tuser [6:2];
  assign m_axis_tuser[1] = \<const0> ;
  assign m_axis_tuser[0] = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_ADD_NGC_CONSTRAINT = "0" *) 
  (* C_APPLICATION_TYPE_AXIS = "0" *) 
  (* C_APPLICATION_TYPE_RACH = "0" *) 
  (* C_APPLICATION_TYPE_RDCH = "0" *) 
  (* C_APPLICATION_TYPE_WACH = "0" *) 
  (* C_APPLICATION_TYPE_WDCH = "0" *) 
  (* C_APPLICATION_TYPE_WRCH = "0" *) 
  (* C_AXIS_TDATA_WIDTH = "64" *) 
  (* C_AXIS_TDEST_WIDTH = "1" *) 
  (* C_AXIS_TID_WIDTH = "1" *) 
  (* C_AXIS_TKEEP_WIDTH = "8" *) 
  (* C_AXIS_TSTRB_WIDTH = "8" *) 
  (* C_AXIS_TUSER_WIDTH = "22" *) 
  (* C_AXIS_TYPE = "0" *) 
  (* C_AXI_ADDR_WIDTH = "32" *) 
  (* C_AXI_ARUSER_WIDTH = "1" *) 
  (* C_AXI_AWUSER_WIDTH = "1" *) 
  (* C_AXI_BUSER_WIDTH = "1" *) 
  (* C_AXI_DATA_WIDTH = "64" *) 
  (* C_AXI_ID_WIDTH = "1" *) 
  (* C_AXI_LEN_WIDTH = "8" *) 
  (* C_AXI_LOCK_WIDTH = "1" *) 
  (* C_AXI_RUSER_WIDTH = "1" *) 
  (* C_AXI_TYPE = "1" *) 
  (* C_AXI_WUSER_WIDTH = "1" *) 
  (* C_COMMON_CLOCK = "1" *) 
  (* C_COUNT_TYPE = "0" *) 
  (* C_DATA_COUNT_WIDTH = "10" *) 
  (* C_DEFAULT_VALUE = "BlankString" *) 
  (* C_DIN_WIDTH = "18" *) 
  (* C_DIN_WIDTH_AXIS = "95" *) 
  (* C_DIN_WIDTH_RACH = "32" *) 
  (* C_DIN_WIDTH_RDCH = "64" *) 
  (* C_DIN_WIDTH_WACH = "32" *) 
  (* C_DIN_WIDTH_WDCH = "64" *) 
  (* C_DIN_WIDTH_WRCH = "2" *) 
  (* C_DOUT_RST_VAL = "0" *) 
  (* C_DOUT_WIDTH = "18" *) 
  (* C_ENABLE_RLOCS = "0" *) 
  (* C_ENABLE_RST_SYNC = "1" *) 
  (* C_EN_SAFETY_CKT = "0" *) 
  (* C_ERROR_INJECTION_TYPE = "0" *) 
  (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) 
  (* C_FAMILY = "artix7" *) 
  (* C_FULL_FLAGS_RST_VAL = "1" *) 
  (* C_HAS_ALMOST_EMPTY = "0" *) 
  (* C_HAS_ALMOST_FULL = "0" *) 
  (* C_HAS_AXIS_TDATA = "1" *) 
  (* C_HAS_AXIS_TDEST = "0" *) 
  (* C_HAS_AXIS_TID = "0" *) 
  (* C_HAS_AXIS_TKEEP = "1" *) 
  (* C_HAS_AXIS_TLAST = "1" *) 
  (* C_HAS_AXIS_TREADY = "1" *) 
  (* C_HAS_AXIS_TSTRB = "0" *) 
  (* C_HAS_AXIS_TUSER = "1" *) 
  (* C_HAS_AXI_ARUSER = "0" *) 
  (* C_HAS_AXI_AWUSER = "0" *) 
  (* C_HAS_AXI_BUSER = "0" *) 
  (* C_HAS_AXI_ID = "0" *) 
  (* C_HAS_AXI_RD_CHANNEL = "1" *) 
  (* C_HAS_AXI_RUSER = "0" *) 
  (* C_HAS_AXI_WR_CHANNEL = "1" *) 
  (* C_HAS_AXI_WUSER = "0" *) 
  (* C_HAS_BACKUP = "0" *) 
  (* C_HAS_DATA_COUNT = "0" *) 
  (* C_HAS_DATA_COUNTS_AXIS = "0" *) 
  (* C_HAS_DATA_COUNTS_RACH = "0" *) 
  (* C_HAS_DATA_COUNTS_RDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WACH = "0" *) 
  (* C_HAS_DATA_COUNTS_WDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WRCH = "0" *) 
  (* C_HAS_INT_CLK = "0" *) 
  (* C_HAS_MASTER_CE = "0" *) 
  (* C_HAS_MEMINIT_FILE = "0" *) 
  (* C_HAS_OVERFLOW = "0" *) 
  (* C_HAS_PROG_FLAGS_AXIS = "0" *) 
  (* C_HAS_PROG_FLAGS_RACH = "0" *) 
  (* C_HAS_PROG_FLAGS_RDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WACH = "0" *) 
  (* C_HAS_PROG_FLAGS_WDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WRCH = "0" *) 
  (* C_HAS_RD_DATA_COUNT = "0" *) 
  (* C_HAS_RD_RST = "0" *) 
  (* C_HAS_RST = "1" *) 
  (* C_HAS_SLAVE_CE = "0" *) 
  (* C_HAS_SRST = "0" *) 
  (* C_HAS_UNDERFLOW = "0" *) 
  (* C_HAS_VALID = "0" *) 
  (* C_HAS_WR_ACK = "0" *) 
  (* C_HAS_WR_DATA_COUNT = "0" *) 
  (* C_HAS_WR_RST = "0" *) 
  (* C_IMPLEMENTATION_TYPE = "0" *) 
  (* C_IMPLEMENTATION_TYPE_AXIS = "2" *) 
  (* C_IMPLEMENTATION_TYPE_RACH = "2" *) 
  (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WACH = "2" *) 
  (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WRCH = "2" *) 
  (* C_INIT_WR_PNTR_VAL = "0" *) 
  (* C_INTERFACE_TYPE = "1" *) 
  (* C_MEMORY_TYPE = "1" *) 
  (* C_MIF_FILE_NAME = "BlankString" *) 
  (* C_MSGON_VAL = "1" *) 
  (* C_OPTIMIZATION_MODE = "0" *) 
  (* C_OVERFLOW_LOW = "0" *) 
  (* C_POWER_SAVING_MODE = "0" *) 
  (* C_PRELOAD_LATENCY = "1" *) 
  (* C_PRELOAD_REGS = "0" *) 
  (* C_PRIM_FIFO_TYPE = "4kx4" *) 
  (* C_PRIM_FIFO_TYPE_AXIS = "512x72" *) 
  (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) 
  (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) 
  (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "14" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "14" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "14" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "14" *) 
  (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) 
  (* C_PROG_EMPTY_TYPE = "0" *) 
  (* C_PROG_EMPTY_TYPE_AXIS = "0" *) 
  (* C_PROG_EMPTY_TYPE_RACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_RDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WRCH = "0" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "9" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "15" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "15" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "15" *) 
  (* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *) 
  (* C_PROG_FULL_TYPE = "0" *) 
  (* C_PROG_FULL_TYPE_AXIS = "1" *) 
  (* C_PROG_FULL_TYPE_RACH = "0" *) 
  (* C_PROG_FULL_TYPE_RDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WACH = "0" *) 
  (* C_PROG_FULL_TYPE_WDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WRCH = "0" *) 
  (* C_RACH_TYPE = "0" *) 
  (* C_RDCH_TYPE = "0" *) 
  (* C_RD_DATA_COUNT_WIDTH = "10" *) 
  (* C_RD_DEPTH = "1024" *) 
  (* C_RD_FREQ = "1" *) 
  (* C_RD_PNTR_WIDTH = "10" *) 
  (* C_REG_SLICE_MODE_AXIS = "0" *) 
  (* C_REG_SLICE_MODE_RACH = "0" *) 
  (* C_REG_SLICE_MODE_RDCH = "0" *) 
  (* C_REG_SLICE_MODE_WACH = "0" *) 
  (* C_REG_SLICE_MODE_WDCH = "0" *) 
  (* C_REG_SLICE_MODE_WRCH = "0" *) 
  (* C_SELECT_XPM = "0" *) 
  (* C_SYNCHRONIZER_STAGE = "2" *) 
  (* C_UNDERFLOW_LOW = "0" *) 
  (* C_USE_COMMON_OVERFLOW = "0" *) 
  (* C_USE_COMMON_UNDERFLOW = "0" *) 
  (* C_USE_DEFAULT_SETTINGS = "0" *) 
  (* C_USE_DOUT_RST = "1" *) 
  (* C_USE_ECC = "0" *) 
  (* C_USE_ECC_AXIS = "0" *) 
  (* C_USE_ECC_RACH = "0" *) 
  (* C_USE_ECC_RDCH = "0" *) 
  (* C_USE_ECC_WACH = "0" *) 
  (* C_USE_ECC_WDCH = "0" *) 
  (* C_USE_ECC_WRCH = "0" *) 
  (* C_USE_EMBEDDED_REG = "0" *) 
  (* C_USE_FIFO16_FLAGS = "0" *) 
  (* C_USE_FWFT_DATA_COUNT = "0" *) 
  (* C_USE_PIPELINE_REG = "0" *) 
  (* C_VALID_LOW = "0" *) 
  (* C_WACH_TYPE = "0" *) 
  (* C_WDCH_TYPE = "0" *) 
  (* C_WRCH_TYPE = "0" *) 
  (* C_WR_ACK_LOW = "0" *) 
  (* C_WR_DATA_COUNT_WIDTH = "10" *) 
  (* C_WR_DEPTH = "1024" *) 
  (* C_WR_DEPTH_AXIS = "16" *) 
  (* C_WR_DEPTH_RACH = "16" *) 
  (* C_WR_DEPTH_RDCH = "1024" *) 
  (* C_WR_DEPTH_WACH = "16" *) 
  (* C_WR_DEPTH_WDCH = "1024" *) 
  (* C_WR_DEPTH_WRCH = "16" *) 
  (* C_WR_FREQ = "1" *) 
  (* C_WR_PNTR_WIDTH = "10" *) 
  (* C_WR_PNTR_WIDTH_AXIS = "4" *) 
  (* C_WR_PNTR_WIDTH_RACH = "4" *) 
  (* C_WR_PNTR_WIDTH_RDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WACH = "4" *) 
  (* C_WR_PNTR_WIDTH_WDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WRCH = "4" *) 
  (* C_WR_RESPONSE_LATENCY = "1" *) 
  (* is_du_within_envelope = "true" *) 
  xdma_0_fifo_generator_v13_1_5__parameterized1 U0
       (.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
        .almost_full(NLW_U0_almost_full_UNCONNECTED),
        .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
        .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
        .axi_ar_injectdbiterr(1'b0),
        .axi_ar_injectsbiterr(1'b0),
        .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
        .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
        .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
        .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
        .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
        .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
        .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
        .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
        .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
        .axi_aw_injectdbiterr(1'b0),
        .axi_aw_injectsbiterr(1'b0),
        .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
        .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
        .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
        .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
        .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
        .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
        .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
        .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
        .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
        .axi_b_injectdbiterr(1'b0),
        .axi_b_injectsbiterr(1'b0),
        .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
        .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
        .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
        .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
        .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
        .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
        .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
        .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
        .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
        .axi_r_injectdbiterr(1'b0),
        .axi_r_injectsbiterr(1'b0),
        .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
        .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
        .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
        .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
        .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
        .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
        .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
        .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
        .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
        .axi_w_injectdbiterr(1'b0),
        .axi_w_injectsbiterr(1'b0),
        .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
        .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
        .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
        .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
        .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
        .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
        .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
        .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[4:0]),
        .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
        .axis_injectdbiterr(1'b0),
        .axis_injectsbiterr(1'b0),
        .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
        .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
        .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
        .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[4:0]),
        .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
        .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
        .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[4:0]),
        .backup(1'b0),
        .backup_marker(1'b0),
        .clk(1'b0),
        .data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
        .dbiterr(NLW_U0_dbiterr_UNCONNECTED),
        .din({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .dout(NLW_U0_dout_UNCONNECTED[17:0]),
        .empty(NLW_U0_empty_UNCONNECTED),
        .full(NLW_U0_full_UNCONNECTED),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .int_clk(1'b0),
        .m_aclk(1'b0),
        .m_aclk_en(1'b0),
        .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
        .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
        .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
        .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
        .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
        .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
        .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
        .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
        .m_axi_arready(1'b0),
        .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
        .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
        .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
        .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
        .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
        .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
        .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
        .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
        .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
        .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
        .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
        .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
        .m_axi_awready(1'b0),
        .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
        .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
        .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
        .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
        .m_axi_bid(1'b0),
        .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
        .m_axi_bresp({1'b0,1'b0}),
        .m_axi_buser(1'b0),
        .m_axi_bvalid(1'b0),
        .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rid(1'b0),
        .m_axi_rlast(1'b0),
        .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
        .m_axi_rresp({1'b0,1'b0}),
        .m_axi_ruser(1'b0),
        .m_axi_rvalid(1'b0),
        .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
        .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
        .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
        .m_axi_wready(1'b0),
        .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
        .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
        .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
        .m_axis_tdata(m_axis_tdata),
        .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
        .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
        .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[7:0]),
        .m_axis_tlast(m_axis_tlast),
        .m_axis_tready(m_axis_tready),
        .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[7:0]),
        .m_axis_tuser({NLW_U0_m_axis_tuser_UNCONNECTED[21:7],\^m_axis_tuser ,NLW_U0_m_axis_tuser_UNCONNECTED[1:0]}),
        .m_axis_tvalid(m_axis_tvalid),
        .overflow(NLW_U0_overflow_UNCONNECTED),
        .prog_empty(NLW_U0_prog_empty_UNCONNECTED),
        .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full(NLW_U0_prog_full_UNCONNECTED),
        .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rd_clk(1'b0),
        .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[9:0]),
        .rd_en(1'b0),
        .rd_rst(1'b0),
        .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
        .rst(1'b0),
        .s_aclk(s_aclk),
        .s_aclk_en(1'b0),
        .s_aresetn(s_aresetn),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arid(1'b0),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlock(1'b0),
        .s_axi_arprot({1'b0,1'b0,1'b0}),
        .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
        .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_aruser(1'b0),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awid(1'b0),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlock(1'b0),
        .s_axi_awprot({1'b0,1'b0,1'b0}),
        .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
        .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awuser(1'b0),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
        .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
        .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
        .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
        .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
        .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wid(1'b0),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wuser(1'b0),
        .s_axi_wvalid(1'b0),
        .s_axis_tdata(s_axis_tdata),
        .s_axis_tdest(1'b0),
        .s_axis_tid(1'b0),
        .s_axis_tkeep({s_axis_tkeep[7],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tlast(s_axis_tlast),
        .s_axis_tready(s_axis_tready),
        .s_axis_tstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tuser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_axis_tuser[8:0]}),
        .s_axis_tvalid(s_axis_tvalid),
        .sbiterr(NLW_U0_sbiterr_UNCONNECTED),
        .sleep(1'b0),
        .srst(1'b0),
        .underflow(NLW_U0_underflow_UNCONNECTED),
        .valid(NLW_U0_valid_UNCONNECTED),
        .wr_ack(NLW_U0_wr_ack_UNCONNECTED),
        .wr_clk(1'b0),
        .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[9:0]),
        .wr_en(1'b0),
        .wr_rst(1'b0),
        .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule

(* CHECK_LICENSE_TYPE = "xdma_0_pcie2_ip,xdma_0_pcie2_ip_pcie2_top,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "xdma_0_pcie2_ip_pcie2_top,Vivado 2024.1" *) 
module xdma_0_pcie2_ip
   (pci_exp_txp,
    pci_exp_txn,
    pci_exp_rxp,
    pci_exp_rxn,
    user_clk_out,
    user_reset_out,
    user_lnk_up,
    user_app_rdy,
    tx_buf_av,
    tx_cfg_req,
    tx_err_drop,
    s_axis_tx_tready,
    s_axis_tx_tdata,
    s_axis_tx_tkeep,
    s_axis_tx_tlast,
    s_axis_tx_tvalid,
    s_axis_tx_tuser,
    tx_cfg_gnt,
    m_axis_rx_tdata,
    m_axis_rx_tkeep,
    m_axis_rx_tlast,
    m_axis_rx_tvalid,
    m_axis_rx_tready,
    m_axis_rx_tuser,
    rx_np_ok,
    rx_np_req,
    fc_cpld,
    fc_cplh,
    fc_npd,
    fc_nph,
    fc_pd,
    fc_ph,
    fc_sel,
    cfg_mgmt_do,
    cfg_mgmt_rd_wr_done,
    cfg_status,
    cfg_command,
    cfg_dstatus,
    cfg_dcommand,
    cfg_lstatus,
    cfg_lcommand,
    cfg_dcommand2,
    cfg_pcie_link_state,
    cfg_pmcsr_pme_en,
    cfg_pmcsr_powerstate,
    cfg_pmcsr_pme_status,
    cfg_received_func_lvl_rst,
    cfg_mgmt_di,
    cfg_mgmt_byte_en,
    cfg_mgmt_dwaddr,
    cfg_mgmt_wr_en,
    cfg_mgmt_rd_en,
    cfg_mgmt_wr_readonly,
    cfg_err_ecrc,
    cfg_err_ur,
    cfg_err_cpl_timeout,
    cfg_err_cpl_unexpect,
    cfg_err_cpl_abort,
    cfg_err_posted,
    cfg_err_cor,
    cfg_err_atomic_egress_blocked,
    cfg_err_internal_cor,
    cfg_err_malformed,
    cfg_err_mc_blocked,
    cfg_err_poisoned,
    cfg_err_norecovery,
    cfg_err_tlp_cpl_header,
    cfg_err_cpl_rdy,
    cfg_err_locked,
    cfg_err_acs,
    cfg_err_internal_uncor,
    cfg_trn_pending,
    cfg_pm_halt_aspm_l0s,
    cfg_pm_halt_aspm_l1,
    cfg_pm_force_state_en,
    cfg_pm_force_state,
    cfg_dsn,
    cfg_interrupt,
    cfg_interrupt_rdy,
    cfg_interrupt_assert,
    cfg_interrupt_di,
    cfg_interrupt_do,
    cfg_interrupt_mmenable,
    cfg_interrupt_msienable,
    cfg_interrupt_msixenable,
    cfg_interrupt_msixfm,
    cfg_interrupt_stat,
    cfg_pciecap_interrupt_msgnum,
    cfg_to_turnoff,
    cfg_turnoff_ok,
    cfg_bus_number,
    cfg_device_number,
    cfg_function_number,
    cfg_pm_wake,
    cfg_pm_send_pme_to,
    cfg_ds_bus_number,
    cfg_ds_device_number,
    cfg_ds_function_number,
    cfg_mgmt_wr_rw1c_as_rw,
    cfg_msg_received,
    cfg_msg_data,
    cfg_bridge_serr_en,
    cfg_slot_control_electromech_il_ctl_pulse,
    cfg_root_control_syserr_corr_err_en,
    cfg_root_control_syserr_non_fatal_err_en,
    cfg_root_control_syserr_fatal_err_en,
    cfg_root_control_pme_int_en,
    cfg_aer_rooterr_corr_err_reporting_en,
    cfg_aer_rooterr_non_fatal_err_reporting_en,
    cfg_aer_rooterr_fatal_err_reporting_en,
    cfg_aer_rooterr_corr_err_received,
    cfg_aer_rooterr_non_fatal_err_received,
    cfg_aer_rooterr_fatal_err_received,
    cfg_msg_received_err_cor,
    cfg_msg_received_err_non_fatal,
    cfg_msg_received_err_fatal,
    cfg_msg_received_pm_as_nak,
    cfg_msg_received_pm_pme,
    cfg_msg_received_pme_to_ack,
    cfg_msg_received_assert_int_a,
    cfg_msg_received_assert_int_b,
    cfg_msg_received_assert_int_c,
    cfg_msg_received_assert_int_d,
    cfg_msg_received_deassert_int_a,
    cfg_msg_received_deassert_int_b,
    cfg_msg_received_deassert_int_c,
    cfg_msg_received_deassert_int_d,
    cfg_msg_received_setslotpowerlimit,
    pl_directed_link_change,
    pl_directed_link_width,
    pl_directed_link_speed,
    pl_directed_link_auton,
    pl_upstream_prefer_deemph,
    pl_sel_lnk_rate,
    pl_sel_lnk_width,
    pl_ltssm_state,
    pl_lane_reversal_mode,
    pl_phy_lnk_up,
    pl_tx_pm_state,
    pl_rx_pm_state,
    pl_link_upcfg_cap,
    pl_link_gen2_cap,
    pl_link_partner_gen2_supported,
    pl_initial_link_width,
    pl_directed_change_done,
    pl_received_hot_rst,
    pl_transmit_hot_rst,
    pl_downstream_deemph_source,
    cfg_err_aer_headerlog,
    cfg_aer_interrupt_msgnum,
    cfg_err_aer_headerlog_set,
    cfg_aer_ecrc_check_en,
    cfg_aer_ecrc_gen_en,
    cfg_vc_tcvc_map,
    sys_clk,
    sys_rst_n);
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txp" *) output [1:0]pci_exp_txp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txn" *) output [1:0]pci_exp_txn;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxp" *) input [1:0]pci_exp_rxp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxn" *) input [1:0]pci_exp_rxn;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.user_clk_out CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.user_clk_out, ASSOCIATED_BUSIF m_axis_rx:s_axis_tx, FREQ_HZ 125000000, ASSOCIATED_RESET user_reset_out, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) output user_clk_out;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.user_reset_out RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.user_reset_out, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) output user_reset_out;
  output user_lnk_up;
  output user_app_rdy;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_buf_av" *) output [5:0]tx_buf_av;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_cfg_req" *) output tx_cfg_req;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_err_drop" *) output tx_err_drop;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TREADY" *) output s_axis_tx_tready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TDATA" *) input [63:0]s_axis_tx_tdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TKEEP" *) input [7:0]s_axis_tx_tkeep;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TLAST" *) input s_axis_tx_tlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TVALID" *) input s_axis_tx_tvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 s_axis_tx TUSER" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axis_tx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input [3:0]s_axis_tx_tuser;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control tx_cfg_gnt" *) input tx_cfg_gnt;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TDATA" *) output [63:0]m_axis_rx_tdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TKEEP" *) output [7:0]m_axis_rx_tkeep;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TLAST" *) output m_axis_rx_tlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TVALID" *) output m_axis_rx_tvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TREADY" *) input m_axis_rx_tready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 m_axis_rx TUSER" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axis_rx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output [21:0]m_axis_rx_tuser;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_ok" *) input rx_np_ok;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_req" *) input rx_np_req;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLD" *) output [11:0]fc_cpld;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLH" *) output [7:0]fc_cplh;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPD" *) output [11:0]fc_npd;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPH" *) output [7:0]fc_nph;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PD" *) output [11:0]fc_pd;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PH" *) output [7:0]fc_ph;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc SEL" *) input [2:0]fc_sel;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_DATA" *) output [31:0]cfg_mgmt_do;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_WRITE_DONE" *) output cfg_mgmt_rd_wr_done;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status status" *) output [15:0]cfg_status;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status command" *) output [15:0]cfg_command;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dstatus" *) output [15:0]cfg_dstatus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand" *) output [15:0]cfg_dcommand;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lstatus" *) output [15:0]cfg_lstatus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lcommand" *) output [15:0]cfg_lcommand;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand2" *) output [15:0]cfg_dcommand2;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pcie_link_state" *) output [2:0]cfg_pcie_link_state;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_en" *) output cfg_pmcsr_pme_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_powerstate" *) output [1:0]cfg_pmcsr_powerstate;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_status" *) output cfg_pmcsr_pme_status;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status received_func_lvl_rst" *) output cfg_received_func_lvl_rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_DATA" *) input [31:0]cfg_mgmt_di;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt BYTE_EN" *) input [3:0]cfg_mgmt_byte_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt ADDR" *) input [9:0]cfg_mgmt_dwaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_EN" *) input cfg_mgmt_wr_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_EN" *) input cfg_mgmt_rd_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READONLY" *) input cfg_mgmt_wr_readonly;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ecrc" *) input cfg_err_ecrc;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ur" *) input cfg_err_ur;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_timeout" *) input cfg_err_cpl_timeout;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_unexpect" *) input cfg_err_cpl_unexpect;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_abort" *) input cfg_err_cpl_abort;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err posted" *) input cfg_err_posted;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cor" *) input cfg_err_cor;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err atomic_egress_blocked" *) input cfg_err_atomic_egress_blocked;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_cor" *) input cfg_err_internal_cor;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err malformed" *) input cfg_err_malformed;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err mc_blocked" *) input cfg_err_mc_blocked;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err poisoned" *) input cfg_err_poisoned;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err norecovery" *) input cfg_err_norecovery;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err tlp_cpl_header" *) input [47:0]cfg_err_tlp_cpl_header;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_rdy" *) output cfg_err_cpl_rdy;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err locked" *) input cfg_err_locked;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err acs" *) input cfg_err_acs;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_uncor" *) input cfg_err_internal_uncor;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control trn_pending" *) input cfg_trn_pending;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l0s" *) input cfg_pm_halt_aspm_l0s;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l1" *) input cfg_pm_halt_aspm_l1;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state_en" *) input cfg_pm_force_state_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state" *) input [1:0]cfg_pm_force_state;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control dsn" *) input [63:0]cfg_dsn;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt interrupt" *) input cfg_interrupt;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt rdy" *) output cfg_interrupt_rdy;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt assert" *) input cfg_interrupt_assert;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt write_data" *) input [7:0]cfg_interrupt_di;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt read_data" *) output [7:0]cfg_interrupt_do;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt mmenable" *) output [2:0]cfg_interrupt_mmenable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msienable" *) output cfg_interrupt_msienable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixenable" *) output cfg_interrupt_msixenable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixfm" *) output cfg_interrupt_msixfm;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt stat" *) input cfg_interrupt_stat;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt pciecap_interrupt_msgnum" *) input [4:0]cfg_pciecap_interrupt_msgnum;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status turnoff" *) output cfg_to_turnoff;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control turnoff_ok" *) input cfg_turnoff_ok;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bus_number" *) output [7:0]cfg_bus_number;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status device_number" *) output [4:0]cfg_device_number;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status function_number" *) output [2:0]cfg_function_number;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_wake" *) input cfg_pm_wake;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_send_pme_to" *) input cfg_pm_send_pme_to;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_bus_number" *) input [7:0]cfg_ds_bus_number;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_device_number" *) input [4:0]cfg_ds_device_number;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_function_number" *) input [2:0]cfg_ds_function_number;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt TYPE1_CFG_REG_ACCESS" *) input cfg_mgmt_wr_rw1c_as_rw;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received" *) output cfg_msg_received;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd data" *) output [15:0]cfg_msg_data;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bridge_serr_en" *) output cfg_bridge_serr_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status slot_control_electromech_il_ctl_pulse" *) output cfg_slot_control_electromech_il_ctl_pulse;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_corr_err_en" *) output cfg_root_control_syserr_corr_err_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_non_fatal_err_en" *) output cfg_root_control_syserr_non_fatal_err_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_fatal_err_en" *) output cfg_root_control_syserr_fatal_err_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_pme_int_en" *) output cfg_root_control_pme_int_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_reporting_en" *) output cfg_aer_rooterr_corr_err_reporting_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_reporting_en" *) output cfg_aer_rooterr_non_fatal_err_reporting_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_reporting_en" *) output cfg_aer_rooterr_fatal_err_reporting_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_received" *) output cfg_aer_rooterr_corr_err_received;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_received" *) output cfg_aer_rooterr_non_fatal_err_received;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_received" *) output cfg_aer_rooterr_fatal_err_received;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_cor" *) output cfg_msg_received_err_cor;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_non_fatal" *) output cfg_msg_received_err_non_fatal;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd err_fatal" *) output cfg_msg_received_err_fatal;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_pm_as_nak" *) output cfg_msg_received_pm_as_nak;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pm_pme" *) output cfg_msg_received_pm_pme;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd pme_to_ack" *) output cfg_msg_received_pme_to_ack;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_a" *) output cfg_msg_received_assert_int_a;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_b" *) output cfg_msg_received_assert_int_b;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_c" *) output cfg_msg_received_assert_int_c;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd assert_int_d" *) output cfg_msg_received_assert_int_d;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_a" *) output cfg_msg_received_deassert_int_a;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_b" *) output cfg_msg_received_deassert_int_b;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_c" *) output cfg_msg_received_deassert_int_c;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd deassert_int_d" *) output cfg_msg_received_deassert_int_d;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0 pcie2_cfg_msg_rcvd received_setslotpowerlimit" *) output cfg_msg_received_setslotpowerlimit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_change" *) input [1:0]pl_directed_link_change;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_width" *) input [1:0]pl_directed_link_width;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_speed" *) input pl_directed_link_speed;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_auton" *) input pl_directed_link_auton;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl upstream_prefer_deemph" *) input pl_upstream_prefer_deemph;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_rate" *) output pl_sel_lnk_rate;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_width" *) output [1:0]pl_sel_lnk_width;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl ltssm_state" *) output [5:0]pl_ltssm_state;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl lane_reversal_mode" *) output [1:0]pl_lane_reversal_mode;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl phy_lnk_up" *) output pl_phy_lnk_up;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl tx_pm_state" *) output [2:0]pl_tx_pm_state;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl rx_pm_state" *) output [1:0]pl_rx_pm_state;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_upcfg_cap" *) output pl_link_upcfg_cap;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_gen2_cap" *) output pl_link_gen2_cap;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_partner_gen2_supported" *) output pl_link_partner_gen2_supported;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl initial_link_width" *) output [2:0]pl_initial_link_width;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_change_done" *) output pl_directed_change_done;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl received_hot_rst" *) output pl_received_hot_rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl transmit_hot_rst" *) input pl_transmit_hot_rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl downstream_deemph_source" *) input pl_downstream_deemph_source;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog" *) input [127:0]cfg_err_aer_headerlog;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_interrupt_msgnum" *) input [4:0]cfg_aer_interrupt_msgnum;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog_set" *) output cfg_err_aer_headerlog_set;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_check_en" *) output cfg_aer_ecrc_check_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_gen_en" *) output cfg_aer_ecrc_gen_en;
  (* X_INTERFACE_INFO = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status vc_tcvc_map" *) output [6:0]cfg_vc_tcvc_map;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.sys_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.sys_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input sys_clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.sys_rst_n RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.sys_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input sys_rst_n;

  wire \<const0> ;
  wire [4:0]cfg_aer_interrupt_msgnum;
  wire [7:0]cfg_bus_number;
  wire [2:2]\^cfg_command ;
  wire [14:5]\^cfg_dcommand ;
  wire [4:0]cfg_device_number;
  wire [63:0]cfg_dsn;
  wire [127:0]cfg_err_aer_headerlog;
  wire [47:0]cfg_err_tlp_cpl_header;
  wire [2:0]cfg_function_number;
  wire cfg_interrupt;
  wire cfg_interrupt_assert;
  wire [7:0]cfg_interrupt_di;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire cfg_interrupt_rdy;
  wire [3:0]cfg_mgmt_byte_en;
  wire [31:0]cfg_mgmt_di;
  wire [31:0]cfg_mgmt_do;
  wire [9:0]cfg_mgmt_dwaddr;
  wire cfg_mgmt_rd_en;
  wire cfg_mgmt_rd_wr_done;
  wire cfg_mgmt_wr_en;
  wire cfg_mgmt_wr_readonly;
  wire [4:0]cfg_pciecap_interrupt_msgnum;
  wire [1:0]cfg_pm_force_state;
  wire cfg_to_turnoff;
  wire cfg_turnoff_ok;
  wire [7:0]fc_nph;
  wire [2:0]fc_sel;
  wire [63:0]m_axis_rx_tdata;
  wire [7:4]\^m_axis_rx_tkeep ;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [21:0]\^m_axis_rx_tuser ;
  wire m_axis_rx_tvalid;
  wire [1:0]pci_exp_rxn;
  wire [1:0]pci_exp_rxp;
  wire [1:0]pci_exp_txn;
  wire [1:0]pci_exp_txp;
  wire pl_directed_link_auton;
  wire [1:0]pl_directed_link_change;
  wire pl_directed_link_speed;
  wire [1:0]pl_directed_link_width;
  wire pl_phy_lnk_up;
  wire pl_upstream_prefer_deemph;
  wire rx_np_ok;
  wire rx_np_req;
  wire [63:0]s_axis_tx_tdata;
  wire [7:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tready;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire sys_clk;
  wire sys_rst_n;
  wire tx_cfg_gnt;
  wire user_clk_out;
  wire user_lnk_up;
  wire user_reset_out;
  wire NLW_inst_cfg_aer_ecrc_check_en_UNCONNECTED;
  wire NLW_inst_cfg_aer_ecrc_gen_en_UNCONNECTED;
  wire NLW_inst_cfg_aer_rooterr_corr_err_received_UNCONNECTED;
  wire NLW_inst_cfg_aer_rooterr_corr_err_reporting_en_UNCONNECTED;
  wire NLW_inst_cfg_aer_rooterr_fatal_err_received_UNCONNECTED;
  wire NLW_inst_cfg_aer_rooterr_fatal_err_reporting_en_UNCONNECTED;
  wire NLW_inst_cfg_aer_rooterr_non_fatal_err_received_UNCONNECTED;
  wire NLW_inst_cfg_aer_rooterr_non_fatal_err_reporting_en_UNCONNECTED;
  wire NLW_inst_cfg_bridge_serr_en_UNCONNECTED;
  wire NLW_inst_cfg_err_aer_headerlog_set_UNCONNECTED;
  wire NLW_inst_cfg_err_cpl_rdy_UNCONNECTED;
  wire NLW_inst_cfg_interrupt_msixenable_UNCONNECTED;
  wire NLW_inst_cfg_interrupt_msixfm_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_assert_int_a_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_assert_int_b_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_assert_int_c_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_assert_int_d_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_deassert_int_a_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_deassert_int_b_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_deassert_int_c_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_deassert_int_d_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_err_cor_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_err_fatal_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_err_non_fatal_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_pm_as_nak_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_pm_pme_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_pme_to_ack_UNCONNECTED;
  wire NLW_inst_cfg_msg_received_setslotpowerlimit_UNCONNECTED;
  wire NLW_inst_cfg_pmcsr_pme_en_UNCONNECTED;
  wire NLW_inst_cfg_pmcsr_pme_status_UNCONNECTED;
  wire NLW_inst_cfg_received_func_lvl_rst_UNCONNECTED;
  wire NLW_inst_cfg_root_control_pme_int_en_UNCONNECTED;
  wire NLW_inst_cfg_root_control_syserr_corr_err_en_UNCONNECTED;
  wire NLW_inst_cfg_root_control_syserr_fatal_err_en_UNCONNECTED;
  wire NLW_inst_cfg_root_control_syserr_non_fatal_err_en_UNCONNECTED;
  wire NLW_inst_cfg_slot_control_electromech_il_ctl_pulse_UNCONNECTED;
  wire NLW_inst_ext_ch_gt_drpclk_UNCONNECTED;
  wire NLW_inst_int_dclk_out_UNCONNECTED;
  wire NLW_inst_int_mmcm_lock_out_UNCONNECTED;
  wire NLW_inst_int_oobclk_out_UNCONNECTED;
  wire NLW_inst_int_pclk_out_slave_UNCONNECTED;
  wire NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED;
  wire NLW_inst_int_userclk1_out_UNCONNECTED;
  wire NLW_inst_int_userclk2_out_UNCONNECTED;
  wire NLW_inst_pcie_drp_rdy_UNCONNECTED;
  wire NLW_inst_pipe_gen3_out_UNCONNECTED;
  wire NLW_inst_pipe_qrst_idle_UNCONNECTED;
  wire NLW_inst_pipe_rate_idle_UNCONNECTED;
  wire NLW_inst_pipe_rst_idle_UNCONNECTED;
  wire NLW_inst_pipe_txoutclk_out_UNCONNECTED;
  wire NLW_inst_pl_directed_change_done_UNCONNECTED;
  wire NLW_inst_pl_link_gen2_cap_UNCONNECTED;
  wire NLW_inst_pl_link_partner_gen2_supported_UNCONNECTED;
  wire NLW_inst_pl_link_upcfg_cap_UNCONNECTED;
  wire NLW_inst_pl_received_hot_rst_UNCONNECTED;
  wire NLW_inst_pl_sel_lnk_rate_UNCONNECTED;
  wire NLW_inst_qpll_drp_clk_UNCONNECTED;
  wire NLW_inst_qpll_drp_gen3_UNCONNECTED;
  wire NLW_inst_qpll_drp_ovrd_UNCONNECTED;
  wire NLW_inst_qpll_drp_rst_n_UNCONNECTED;
  wire NLW_inst_qpll_drp_start_UNCONNECTED;
  wire NLW_inst_qpll_qplld_UNCONNECTED;
  wire NLW_inst_startup_cfgclk_UNCONNECTED;
  wire NLW_inst_startup_cfgmclk_UNCONNECTED;
  wire NLW_inst_startup_eos_UNCONNECTED;
  wire NLW_inst_startup_preq_UNCONNECTED;
  wire NLW_inst_tx_cfg_req_UNCONNECTED;
  wire NLW_inst_tx_err_drop_UNCONNECTED;
  wire NLW_inst_user_app_rdy_UNCONNECTED;
  wire [15:0]NLW_inst_cfg_command_UNCONNECTED;
  wire [15:0]NLW_inst_cfg_dcommand_UNCONNECTED;
  wire [15:0]NLW_inst_cfg_dcommand2_UNCONNECTED;
  wire [15:0]NLW_inst_cfg_dstatus_UNCONNECTED;
  wire [7:0]NLW_inst_cfg_interrupt_do_UNCONNECTED;
  wire [15:0]NLW_inst_cfg_lcommand_UNCONNECTED;
  wire [15:0]NLW_inst_cfg_lstatus_UNCONNECTED;
  wire [15:0]NLW_inst_cfg_msg_data_UNCONNECTED;
  wire [2:0]NLW_inst_cfg_pcie_link_state_UNCONNECTED;
  wire [1:0]NLW_inst_cfg_pmcsr_powerstate_UNCONNECTED;
  wire [15:0]NLW_inst_cfg_status_UNCONNECTED;
  wire [6:0]NLW_inst_cfg_vc_tcvc_map_UNCONNECTED;
  wire [11:0]NLW_inst_common_commands_out_UNCONNECTED;
  wire [31:0]NLW_inst_ext_ch_gt_drpdo_UNCONNECTED;
  wire [1:0]NLW_inst_ext_ch_gt_drprdy_UNCONNECTED;
  wire [11:0]NLW_inst_fc_cpld_UNCONNECTED;
  wire [7:0]NLW_inst_fc_cplh_UNCONNECTED;
  wire [11:0]NLW_inst_fc_npd_UNCONNECTED;
  wire [11:0]NLW_inst_fc_pd_UNCONNECTED;
  wire [7:0]NLW_inst_fc_ph_UNCONNECTED;
  wire [1:0]NLW_inst_gt_ch_drp_rdy_UNCONNECTED;
  wire [31:0]NLW_inst_icap_o_UNCONNECTED;
  wire [1:0]NLW_inst_int_qplllock_out_UNCONNECTED;
  wire [1:0]NLW_inst_int_qplloutclk_out_UNCONNECTED;
  wire [1:0]NLW_inst_int_qplloutrefclk_out_UNCONNECTED;
  wire [1:0]NLW_inst_int_rxoutclk_out_UNCONNECTED;
  wire [3:0]NLW_inst_m_axis_rx_tkeep_UNCONNECTED;
  wire [20:9]NLW_inst_m_axis_rx_tuser_UNCONNECTED;
  wire [15:0]NLW_inst_pcie_drp_do_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_cpll_lock_UNCONNECTED;
  wire [31:0]NLW_inst_pipe_debug_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_0_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_1_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_2_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_3_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_4_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_5_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_6_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_7_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_8_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_debug_9_UNCONNECTED;
  wire [29:0]NLW_inst_pipe_dmonitorout_UNCONNECTED;
  wire [13:0]NLW_inst_pipe_drp_fsm_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_eyescandataerror_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_pclk_sel_out_UNCONNECTED;
  wire [0:0]NLW_inst_pipe_qpll_lock_UNCONNECTED;
  wire [11:0]NLW_inst_pipe_qrst_fsm_UNCONNECTED;
  wire [9:0]NLW_inst_pipe_rate_fsm_UNCONNECTED;
  wire [4:0]NLW_inst_pipe_rst_fsm_UNCONNECTED;
  wire [5:0]NLW_inst_pipe_rxbufstatus_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxcommadet_UNCONNECTED;
  wire [15:0]NLW_inst_pipe_rxdisperr_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxdlysresetdone_UNCONNECTED;
  wire [15:0]NLW_inst_pipe_rxnotintable_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxoutclk_out_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxphaligndone_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxpmaresetdone_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxprbserr_UNCONNECTED;
  wire [5:0]NLW_inst_pipe_rxstatus_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_rxsyncdone_UNCONNECTED;
  wire [13:0]NLW_inst_pipe_sync_fsm_rx_UNCONNECTED;
  wire [11:0]NLW_inst_pipe_sync_fsm_tx_UNCONNECTED;
  wire [24:0]NLW_inst_pipe_tx_0_sigs_UNCONNECTED;
  wire [24:0]NLW_inst_pipe_tx_1_sigs_UNCONNECTED;
  wire [24:0]NLW_inst_pipe_tx_2_sigs_UNCONNECTED;
  wire [24:0]NLW_inst_pipe_tx_3_sigs_UNCONNECTED;
  wire [24:0]NLW_inst_pipe_tx_4_sigs_UNCONNECTED;
  wire [24:0]NLW_inst_pipe_tx_5_sigs_UNCONNECTED;
  wire [24:0]NLW_inst_pipe_tx_6_sigs_UNCONNECTED;
  wire [24:0]NLW_inst_pipe_tx_7_sigs_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_txdlysresetdone_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_txphaligndone_UNCONNECTED;
  wire [1:0]NLW_inst_pipe_txphinitdone_UNCONNECTED;
  wire [2:0]NLW_inst_pl_initial_link_width_UNCONNECTED;
  wire [1:0]NLW_inst_pl_lane_reversal_mode_UNCONNECTED;
  wire [5:0]NLW_inst_pl_ltssm_state_UNCONNECTED;
  wire [1:0]NLW_inst_pl_rx_pm_state_UNCONNECTED;
  wire [1:0]NLW_inst_pl_sel_lnk_width_UNCONNECTED;
  wire [2:0]NLW_inst_pl_tx_pm_state_UNCONNECTED;
  wire [1:0]NLW_inst_qpll_qpllreset_UNCONNECTED;
  wire [5:0]NLW_inst_tx_buf_av_UNCONNECTED;

  assign cfg_aer_ecrc_check_en = \<const0> ;
  assign cfg_aer_ecrc_gen_en = \<const0> ;
  assign cfg_aer_rooterr_corr_err_received = \<const0> ;
  assign cfg_aer_rooterr_corr_err_reporting_en = \<const0> ;
  assign cfg_aer_rooterr_fatal_err_received = \<const0> ;
  assign cfg_aer_rooterr_fatal_err_reporting_en = \<const0> ;
  assign cfg_aer_rooterr_non_fatal_err_received = \<const0> ;
  assign cfg_aer_rooterr_non_fatal_err_reporting_en = \<const0> ;
  assign cfg_bridge_serr_en = \<const0> ;
  assign cfg_command[15] = \<const0> ;
  assign cfg_command[14] = \<const0> ;
  assign cfg_command[13] = \<const0> ;
  assign cfg_command[12] = \<const0> ;
  assign cfg_command[11] = \<const0> ;
  assign cfg_command[10] = \<const0> ;
  assign cfg_command[9] = \<const0> ;
  assign cfg_command[8] = \<const0> ;
  assign cfg_command[7] = \<const0> ;
  assign cfg_command[6] = \<const0> ;
  assign cfg_command[5] = \<const0> ;
  assign cfg_command[4] = \<const0> ;
  assign cfg_command[3] = \<const0> ;
  assign cfg_command[2] = \^cfg_command [2];
  assign cfg_command[1] = \<const0> ;
  assign cfg_command[0] = \<const0> ;
  assign cfg_dcommand[15] = \<const0> ;
  assign cfg_dcommand[14:12] = \^cfg_dcommand [14:12];
  assign cfg_dcommand[11] = \<const0> ;
  assign cfg_dcommand[10] = \<const0> ;
  assign cfg_dcommand[9] = \<const0> ;
  assign cfg_dcommand[8] = \<const0> ;
  assign cfg_dcommand[7:5] = \^cfg_dcommand [7:5];
  assign cfg_dcommand[4] = \<const0> ;
  assign cfg_dcommand[3] = \<const0> ;
  assign cfg_dcommand[2] = \<const0> ;
  assign cfg_dcommand[1] = \<const0> ;
  assign cfg_dcommand[0] = \<const0> ;
  assign cfg_dcommand2[15] = \<const0> ;
  assign cfg_dcommand2[14] = \<const0> ;
  assign cfg_dcommand2[13] = \<const0> ;
  assign cfg_dcommand2[12] = \<const0> ;
  assign cfg_dcommand2[11] = \<const0> ;
  assign cfg_dcommand2[10] = \<const0> ;
  assign cfg_dcommand2[9] = \<const0> ;
  assign cfg_dcommand2[8] = \<const0> ;
  assign cfg_dcommand2[7] = \<const0> ;
  assign cfg_dcommand2[6] = \<const0> ;
  assign cfg_dcommand2[5] = \<const0> ;
  assign cfg_dcommand2[4] = \<const0> ;
  assign cfg_dcommand2[3] = \<const0> ;
  assign cfg_dcommand2[2] = \<const0> ;
  assign cfg_dcommand2[1] = \<const0> ;
  assign cfg_dcommand2[0] = \<const0> ;
  assign cfg_dstatus[15] = \<const0> ;
  assign cfg_dstatus[14] = \<const0> ;
  assign cfg_dstatus[13] = \<const0> ;
  assign cfg_dstatus[12] = \<const0> ;
  assign cfg_dstatus[11] = \<const0> ;
  assign cfg_dstatus[10] = \<const0> ;
  assign cfg_dstatus[9] = \<const0> ;
  assign cfg_dstatus[8] = \<const0> ;
  assign cfg_dstatus[7] = \<const0> ;
  assign cfg_dstatus[6] = \<const0> ;
  assign cfg_dstatus[5] = \<const0> ;
  assign cfg_dstatus[4] = \<const0> ;
  assign cfg_dstatus[3] = \<const0> ;
  assign cfg_dstatus[2] = \<const0> ;
  assign cfg_dstatus[1] = \<const0> ;
  assign cfg_dstatus[0] = \<const0> ;
  assign cfg_err_aer_headerlog_set = \<const0> ;
  assign cfg_err_cpl_rdy = \<const0> ;
  assign cfg_interrupt_do[7] = \<const0> ;
  assign cfg_interrupt_do[6] = \<const0> ;
  assign cfg_interrupt_do[5] = \<const0> ;
  assign cfg_interrupt_do[4] = \<const0> ;
  assign cfg_interrupt_do[3] = \<const0> ;
  assign cfg_interrupt_do[2] = \<const0> ;
  assign cfg_interrupt_do[1] = \<const0> ;
  assign cfg_interrupt_do[0] = \<const0> ;
  assign cfg_interrupt_msixenable = \<const0> ;
  assign cfg_interrupt_msixfm = \<const0> ;
  assign cfg_lcommand[15] = \<const0> ;
  assign cfg_lcommand[14] = \<const0> ;
  assign cfg_lcommand[13] = \<const0> ;
  assign cfg_lcommand[12] = \<const0> ;
  assign cfg_lcommand[11] = \<const0> ;
  assign cfg_lcommand[10] = \<const0> ;
  assign cfg_lcommand[9] = \<const0> ;
  assign cfg_lcommand[8] = \<const0> ;
  assign cfg_lcommand[7] = \<const0> ;
  assign cfg_lcommand[6] = \<const0> ;
  assign cfg_lcommand[5] = \<const0> ;
  assign cfg_lcommand[4] = \<const0> ;
  assign cfg_lcommand[3] = \<const0> ;
  assign cfg_lcommand[2] = \<const0> ;
  assign cfg_lcommand[1] = \<const0> ;
  assign cfg_lcommand[0] = \<const0> ;
  assign cfg_lstatus[15] = \<const0> ;
  assign cfg_lstatus[14] = \<const0> ;
  assign cfg_lstatus[13] = \<const0> ;
  assign cfg_lstatus[12] = \<const0> ;
  assign cfg_lstatus[11] = \<const0> ;
  assign cfg_lstatus[10] = \<const0> ;
  assign cfg_lstatus[9] = \<const0> ;
  assign cfg_lstatus[8] = \<const0> ;
  assign cfg_lstatus[7] = \<const0> ;
  assign cfg_lstatus[6] = \<const0> ;
  assign cfg_lstatus[5] = \<const0> ;
  assign cfg_lstatus[4] = \<const0> ;
  assign cfg_lstatus[3] = \<const0> ;
  assign cfg_lstatus[2] = \<const0> ;
  assign cfg_lstatus[1] = \<const0> ;
  assign cfg_lstatus[0] = \<const0> ;
  assign cfg_msg_data[15] = \<const0> ;
  assign cfg_msg_data[14] = \<const0> ;
  assign cfg_msg_data[13] = \<const0> ;
  assign cfg_msg_data[12] = \<const0> ;
  assign cfg_msg_data[11] = \<const0> ;
  assign cfg_msg_data[10] = \<const0> ;
  assign cfg_msg_data[9] = \<const0> ;
  assign cfg_msg_data[8] = \<const0> ;
  assign cfg_msg_data[7] = \<const0> ;
  assign cfg_msg_data[6] = \<const0> ;
  assign cfg_msg_data[5] = \<const0> ;
  assign cfg_msg_data[4] = \<const0> ;
  assign cfg_msg_data[3] = \<const0> ;
  assign cfg_msg_data[2] = \<const0> ;
  assign cfg_msg_data[1] = \<const0> ;
  assign cfg_msg_data[0] = \<const0> ;
  assign cfg_msg_received = \<const0> ;
  assign cfg_msg_received_assert_int_a = \<const0> ;
  assign cfg_msg_received_assert_int_b = \<const0> ;
  assign cfg_msg_received_assert_int_c = \<const0> ;
  assign cfg_msg_received_assert_int_d = \<const0> ;
  assign cfg_msg_received_deassert_int_a = \<const0> ;
  assign cfg_msg_received_deassert_int_b = \<const0> ;
  assign cfg_msg_received_deassert_int_c = \<const0> ;
  assign cfg_msg_received_deassert_int_d = \<const0> ;
  assign cfg_msg_received_err_cor = \<const0> ;
  assign cfg_msg_received_err_fatal = \<const0> ;
  assign cfg_msg_received_err_non_fatal = \<const0> ;
  assign cfg_msg_received_pm_as_nak = \<const0> ;
  assign cfg_msg_received_pm_pme = \<const0> ;
  assign cfg_msg_received_pme_to_ack = \<const0> ;
  assign cfg_msg_received_setslotpowerlimit = \<const0> ;
  assign cfg_pcie_link_state[2] = \<const0> ;
  assign cfg_pcie_link_state[1] = \<const0> ;
  assign cfg_pcie_link_state[0] = \<const0> ;
  assign cfg_pmcsr_pme_en = \<const0> ;
  assign cfg_pmcsr_pme_status = \<const0> ;
  assign cfg_pmcsr_powerstate[1] = \<const0> ;
  assign cfg_pmcsr_powerstate[0] = \<const0> ;
  assign cfg_received_func_lvl_rst = \<const0> ;
  assign cfg_root_control_pme_int_en = \<const0> ;
  assign cfg_root_control_syserr_corr_err_en = \<const0> ;
  assign cfg_root_control_syserr_fatal_err_en = \<const0> ;
  assign cfg_root_control_syserr_non_fatal_err_en = \<const0> ;
  assign cfg_slot_control_electromech_il_ctl_pulse = \<const0> ;
  assign cfg_status[15] = \<const0> ;
  assign cfg_status[14] = \<const0> ;
  assign cfg_status[13] = \<const0> ;
  assign cfg_status[12] = \<const0> ;
  assign cfg_status[11] = \<const0> ;
  assign cfg_status[10] = \<const0> ;
  assign cfg_status[9] = \<const0> ;
  assign cfg_status[8] = \<const0> ;
  assign cfg_status[7] = \<const0> ;
  assign cfg_status[6] = \<const0> ;
  assign cfg_status[5] = \<const0> ;
  assign cfg_status[4] = \<const0> ;
  assign cfg_status[3] = \<const0> ;
  assign cfg_status[2] = \<const0> ;
  assign cfg_status[1] = \<const0> ;
  assign cfg_status[0] = \<const0> ;
  assign cfg_vc_tcvc_map[6] = \<const0> ;
  assign cfg_vc_tcvc_map[5] = \<const0> ;
  assign cfg_vc_tcvc_map[4] = \<const0> ;
  assign cfg_vc_tcvc_map[3] = \<const0> ;
  assign cfg_vc_tcvc_map[2] = \<const0> ;
  assign cfg_vc_tcvc_map[1] = \<const0> ;
  assign cfg_vc_tcvc_map[0] = \<const0> ;
  assign fc_cpld[11] = \<const0> ;
  assign fc_cpld[10] = \<const0> ;
  assign fc_cpld[9] = \<const0> ;
  assign fc_cpld[8] = \<const0> ;
  assign fc_cpld[7] = \<const0> ;
  assign fc_cpld[6] = \<const0> ;
  assign fc_cpld[5] = \<const0> ;
  assign fc_cpld[4] = \<const0> ;
  assign fc_cpld[3] = \<const0> ;
  assign fc_cpld[2] = \<const0> ;
  assign fc_cpld[1] = \<const0> ;
  assign fc_cpld[0] = \<const0> ;
  assign fc_cplh[7] = \<const0> ;
  assign fc_cplh[6] = \<const0> ;
  assign fc_cplh[5] = \<const0> ;
  assign fc_cplh[4] = \<const0> ;
  assign fc_cplh[3] = \<const0> ;
  assign fc_cplh[2] = \<const0> ;
  assign fc_cplh[1] = \<const0> ;
  assign fc_cplh[0] = \<const0> ;
  assign fc_npd[11] = \<const0> ;
  assign fc_npd[10] = \<const0> ;
  assign fc_npd[9] = \<const0> ;
  assign fc_npd[8] = \<const0> ;
  assign fc_npd[7] = \<const0> ;
  assign fc_npd[6] = \<const0> ;
  assign fc_npd[5] = \<const0> ;
  assign fc_npd[4] = \<const0> ;
  assign fc_npd[3] = \<const0> ;
  assign fc_npd[2] = \<const0> ;
  assign fc_npd[1] = \<const0> ;
  assign fc_npd[0] = \<const0> ;
  assign fc_pd[11] = \<const0> ;
  assign fc_pd[10] = \<const0> ;
  assign fc_pd[9] = \<const0> ;
  assign fc_pd[8] = \<const0> ;
  assign fc_pd[7] = \<const0> ;
  assign fc_pd[6] = \<const0> ;
  assign fc_pd[5] = \<const0> ;
  assign fc_pd[4] = \<const0> ;
  assign fc_pd[3] = \<const0> ;
  assign fc_pd[2] = \<const0> ;
  assign fc_pd[1] = \<const0> ;
  assign fc_pd[0] = \<const0> ;
  assign fc_ph[7] = \<const0> ;
  assign fc_ph[6] = \<const0> ;
  assign fc_ph[5] = \<const0> ;
  assign fc_ph[4] = \<const0> ;
  assign fc_ph[3] = \<const0> ;
  assign fc_ph[2] = \<const0> ;
  assign fc_ph[1] = \<const0> ;
  assign fc_ph[0] = \<const0> ;
  assign m_axis_rx_tkeep[7:4] = \^m_axis_rx_tkeep [7:4];
  assign m_axis_rx_tkeep[3] = \<const0> ;
  assign m_axis_rx_tkeep[2] = \<const0> ;
  assign m_axis_rx_tkeep[1] = \<const0> ;
  assign m_axis_rx_tkeep[0] = \<const0> ;
  assign m_axis_rx_tuser[21] = \^m_axis_rx_tuser [21];
  assign m_axis_rx_tuser[20] = \<const0> ;
  assign m_axis_rx_tuser[19:17] = \^m_axis_rx_tuser [19:17];
  assign m_axis_rx_tuser[16] = \<const0> ;
  assign m_axis_rx_tuser[15] = \<const0> ;
  assign m_axis_rx_tuser[14] = \^m_axis_rx_tuser [14];
  assign m_axis_rx_tuser[13] = \<const0> ;
  assign m_axis_rx_tuser[12] = \<const0> ;
  assign m_axis_rx_tuser[11] = \<const0> ;
  assign m_axis_rx_tuser[10] = \<const0> ;
  assign m_axis_rx_tuser[9] = \<const0> ;
  assign m_axis_rx_tuser[8:0] = \^m_axis_rx_tuser [8:0];
  assign pl_directed_change_done = \<const0> ;
  assign pl_initial_link_width[2] = \<const0> ;
  assign pl_initial_link_width[1] = \<const0> ;
  assign pl_initial_link_width[0] = \<const0> ;
  assign pl_lane_reversal_mode[1] = \<const0> ;
  assign pl_lane_reversal_mode[0] = \<const0> ;
  assign pl_link_gen2_cap = \<const0> ;
  assign pl_link_partner_gen2_supported = \<const0> ;
  assign pl_link_upcfg_cap = \<const0> ;
  assign pl_ltssm_state[5] = \<const0> ;
  assign pl_ltssm_state[4] = \<const0> ;
  assign pl_ltssm_state[3] = \<const0> ;
  assign pl_ltssm_state[2] = \<const0> ;
  assign pl_ltssm_state[1] = \<const0> ;
  assign pl_ltssm_state[0] = \<const0> ;
  assign pl_received_hot_rst = \<const0> ;
  assign pl_rx_pm_state[1] = \<const0> ;
  assign pl_rx_pm_state[0] = \<const0> ;
  assign pl_sel_lnk_rate = \<const0> ;
  assign pl_sel_lnk_width[1] = \<const0> ;
  assign pl_sel_lnk_width[0] = \<const0> ;
  assign pl_tx_pm_state[2] = \<const0> ;
  assign pl_tx_pm_state[1] = \<const0> ;
  assign pl_tx_pm_state[0] = \<const0> ;
  assign tx_buf_av[5] = \<const0> ;
  assign tx_buf_av[4] = \<const0> ;
  assign tx_buf_av[3] = \<const0> ;
  assign tx_buf_av[2] = \<const0> ;
  assign tx_buf_av[1] = \<const0> ;
  assign tx_buf_av[0] = \<const0> ;
  assign tx_cfg_req = \<const0> ;
  assign tx_err_drop = \<const0> ;
  assign user_app_rdy = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* CFG_CTL_IF = "TRUE" *) 
  (* CFG_FC_IF = "TRUE" *) 
  (* CFG_MGMT_IF = "TRUE" *) 
  (* CFG_STATUS_IF = "TRUE" *) 
  (* CLASS_CODE = "070001" *) 
  (* C_DATA_WIDTH = "64" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* ENABLE_JTAG_DBG = "FALSE" *) 
  (* ERR_REPORTING_IF = "TRUE" *) 
  (* EXT_CH_GT_DRP = "FALSE" *) 
  (* EXT_PIPE_INTERFACE = "FALSE" *) 
  (* EXT_STARTUP_PRIMITIVE = "FALSE" *) 
  (* KEEP_WIDTH = "8" *) 
  (* LINK_CAP_MAX_LINK_WIDTH = "2" *) 
  (* PCIE_ASYNC_EN = "FALSE" *) 
  (* PCIE_EXT_CLK = "FALSE" *) 
  (* PCIE_EXT_GT_COMMON = "FALSE" *) 
  (* PCIE_ID_IF = "FALSE" *) 
  (* PIPE_SIM = "FALSE" *) 
  (* PL_INTERFACE = "TRUE" *) 
  (* RCV_MSG_IF = "TRUE" *) 
  (* REDUCE_OOB_FREQ = "FALSE" *) 
  (* SHARED_LOGIC_IN_CORE = "FALSE" *) 
  (* TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE" *) 
  (* bar_0 = "FFFF0000" *) 
  (* bar_1 = "FFF00000" *) 
  (* bar_2 = "00000000" *) 
  (* bar_3 = "00000000" *) 
  (* bar_4 = "00000000" *) 
  (* bar_5 = "00000000" *) 
  (* bram_lat = "0" *) 
  (* c_aer_base_ptr = "000" *) 
  (* c_aer_cap_ecrc_check_capable = "FALSE" *) 
  (* c_aer_cap_ecrc_gen_capable = "FALSE" *) 
  (* c_aer_cap_multiheader = "FALSE" *) 
  (* c_aer_cap_nextptr = "000" *) 
  (* c_aer_cap_on = "FALSE" *) 
  (* c_aer_cap_optional_err_support = "000000" *) 
  (* c_aer_cap_permit_rooterr_update = "FALSE" *) 
  (* c_buf_opt_bma = "TRUE" *) 
  (* c_component_name = "xdma_0_pcie2_ip" *) 
  (* c_cpl_inf = "TRUE" *) 
  (* c_cpl_infinite = "TRUE" *) 
  (* c_cpl_timeout_disable_sup = "FALSE" *) 
  (* c_cpl_timeout_range = "0010" *) 
  (* c_cpl_timeout_ranges_sup = "2" *) 
  (* c_d1_support = "FALSE" *) 
  (* c_d2_support = "FALSE" *) 
  (* c_de_emph = "FALSE" *) 
  (* c_dev_cap2_ari_forwarding_supported = "FALSE" *) 
  (* c_dev_cap2_atomicop32_completer_supported = "FALSE" *) 
  (* c_dev_cap2_atomicop64_completer_supported = "FALSE" *) 
  (* c_dev_cap2_atomicop_routing_supported = "FALSE" *) 
  (* c_dev_cap2_cas128_completer_supported = "FALSE" *) 
  (* c_dev_cap2_tph_completer_supported = "00" *) 
  (* c_dev_control_ext_tag_default = "FALSE" *) 
  (* c_dev_port_type = "0" *) 
  (* c_dis_lane_reverse = "TRUE" *) 
  (* c_disable_rx_poisoned_resp = "FALSE" *) 
  (* c_disable_scrambling = "FALSE" *) 
  (* c_disable_tx_aspm_l0s = "FALSE" *) 
  (* c_dll_lnk_actv_cap = "FALSE" *) 
  (* c_dsi_bool = "FALSE" *) 
  (* c_dsn_base_ptr = "100" *) 
  (* c_dsn_cap_enabled = "TRUE" *) 
  (* c_dsn_next_ptr = "000" *) 
  (* c_enable_msg_route = "00000000000" *) 
  (* c_ep_l0s_accpt_lat = "0" *) 
  (* c_ep_l1_accpt_lat = "7" *) 
  (* c_ext_pci_cfg_space_addr = "3FF" *) 
  (* c_external_clocking = "TRUE" *) 
  (* c_fc_cpld = "461" *) 
  (* c_fc_cplh = "36" *) 
  (* c_fc_npd = "24" *) 
  (* c_fc_nph = "12" *) 
  (* c_fc_pd = "437" *) 
  (* c_fc_ph = "32" *) 
  (* c_gen1 = "1'b1" *) 
  (* c_header_type = "00" *) 
  (* c_hw_auton_spd_disable = "FALSE" *) 
  (* c_int_width = "64" *) 
  (* c_last_cfg_dw = "10C" *) 
  (* c_link_cap_aspm_optionality = "FALSE" *) 
  (* c_ll_ack_timeout = "0000" *) 
  (* c_ll_ack_timeout_enable = "FALSE" *) 
  (* c_ll_ack_timeout_function = "0" *) 
  (* c_ll_replay_timeout = "0000" *) 
  (* c_ll_replay_timeout_enable = "FALSE" *) 
  (* c_ll_replay_timeout_func = "1" *) 
  (* c_lnk_bndwdt_notif = "FALSE" *) 
  (* c_msi = "0" *) 
  (* c_msi_64b_addr = "TRUE" *) 
  (* c_msi_cap_on = "TRUE" *) 
  (* c_msi_mult_msg_extn = "0" *) 
  (* c_msi_per_vctr_mask_cap = "FALSE" *) 
  (* c_msix_cap_on = "FALSE" *) 
  (* c_msix_next_ptr = "00" *) 
  (* c_msix_pba_bir = "0" *) 
  (* c_msix_pba_offset = "0" *) 
  (* c_msix_table_bir = "0" *) 
  (* c_msix_table_offset = "0" *) 
  (* c_msix_table_size = "000" *) 
  (* c_pci_cfg_space_addr = "3F" *) 
  (* c_pcie_blk_locn = "0" *) 
  (* c_pcie_cap_next_ptr = "00" *) 
  (* c_pcie_cap_slot_implemented = "FALSE" *) 
  (* c_pcie_dbg_ports = "FALSE" *) 
  (* c_pcie_fast_config = "0" *) 
  (* c_perf_level_high = "TRUE" *) 
  (* c_phantom_functions = "0" *) 
  (* c_pm_cap_next_ptr = "48" *) 
  (* c_pme_support = "0F" *) 
  (* c_rbar_base_ptr = "000" *) 
  (* c_rbar_cap_control_encodedbar0 = "00" *) 
  (* c_rbar_cap_control_encodedbar1 = "00" *) 
  (* c_rbar_cap_control_encodedbar2 = "00" *) 
  (* c_rbar_cap_control_encodedbar3 = "00" *) 
  (* c_rbar_cap_control_encodedbar4 = "00" *) 
  (* c_rbar_cap_control_encodedbar5 = "00" *) 
  (* c_rbar_cap_index0 = "0" *) 
  (* c_rbar_cap_index1 = "0" *) 
  (* c_rbar_cap_index2 = "0" *) 
  (* c_rbar_cap_index3 = "0" *) 
  (* c_rbar_cap_index4 = "0" *) 
  (* c_rbar_cap_index5 = "0" *) 
  (* c_rbar_cap_nextptr = "000" *) 
  (* c_rbar_cap_on = "FALSE" *) 
  (* c_rbar_cap_sup0 = "00001" *) 
  (* c_rbar_cap_sup1 = "00001" *) 
  (* c_rbar_cap_sup2 = "00001" *) 
  (* c_rbar_cap_sup3 = "00001" *) 
  (* c_rbar_cap_sup4 = "00001" *) 
  (* c_rbar_cap_sup5 = "00001" *) 
  (* c_rbar_num = "0" *) 
  (* c_rcb = "0" *) 
  (* c_recrc_check = "0" *) 
  (* c_recrc_check_trim = "FALSE" *) 
  (* c_rev_gt_order = "FALSE" *) 
  (* c_root_cap_crs = "FALSE" *) 
  (* c_rx_raddr_lat = "0" *) 
  (* c_rx_ram_limit = "7FF" *) 
  (* c_rx_rdata_lat = "2" *) 
  (* c_rx_write_lat = "0" *) 
  (* c_silicon_rev = "2" *) 
  (* c_slot_cap_attn_butn = "FALSE" *) 
  (* c_slot_cap_attn_ind = "FALSE" *) 
  (* c_slot_cap_elec_interlock = "FALSE" *) 
  (* c_slot_cap_hotplug_cap = "FALSE" *) 
  (* c_slot_cap_hotplug_surprise = "FALSE" *) 
  (* c_slot_cap_mrl = "FALSE" *) 
  (* c_slot_cap_no_cmd_comp_sup = "FALSE" *) 
  (* c_slot_cap_physical_slot_num = "0" *) 
  (* c_slot_cap_pwr_ctrl = "FALSE" *) 
  (* c_slot_cap_pwr_ind = "FALSE" *) 
  (* c_slot_cap_pwr_limit_scale = "0" *) 
  (* c_slot_cap_pwr_limit_value = "0" *) 
  (* c_surprise_dn_err_cap = "FALSE" *) 
  (* c_trgt_lnk_spd = "2" *) 
  (* c_trn_np_fc = "TRUE" *) 
  (* c_tx_last_tlp = "29" *) 
  (* c_tx_raddr_lat = "0" *) 
  (* c_tx_rdata_lat = "2" *) 
  (* c_tx_write_lat = "0" *) 
  (* c_upconfig_capable = "TRUE" *) 
  (* c_upstream_facing = "TRUE" *) 
  (* c_ur_atomic = "FALSE" *) 
  (* c_ur_inv_req = "TRUE" *) 
  (* c_ur_prs_response = "TRUE" *) 
  (* c_vc_base_ptr = "000" *) 
  (* c_vc_cap_enabled = "FALSE" *) 
  (* c_vc_cap_reject_snoop = "FALSE" *) 
  (* c_vc_next_ptr = "000" *) 
  (* c_vsec_base_ptr = "000" *) 
  (* c_vsec_cap_enabled = "FALSE" *) 
  (* c_vsec_next_ptr = "000" *) 
  (* c_xlnx_ref_board = "NONE" *) 
  (* cap_ver = "2" *) 
  (* cardbus_cis_ptr = "00000000" *) 
  (* cmps = "2" *) 
  (* con_scl_fctr_d0_state = "0" *) 
  (* con_scl_fctr_d1_state = "0" *) 
  (* con_scl_fctr_d2_state = "0" *) 
  (* con_scl_fctr_d3_state = "0" *) 
  (* cost_table = "1" *) 
  (* d1_sup = "0" *) 
  (* d2_sup = "0" *) 
  (* dev_id = "7022" *) 
  (* dev_port_type = "0000" *) 
  (* dis_scl_fctr_d0_state = "0" *) 
  (* dis_scl_fctr_d1_state = "0" *) 
  (* dis_scl_fctr_d2_state = "0" *) 
  (* dis_scl_fctr_d3_state = "0" *) 
  (* dsi = "0" *) 
  (* ep_l0s_accpt_lat = "000" *) 
  (* ep_l1_accpt_lat = "111" *) 
  (* ext_tag_fld_sup = "TRUE" *) 
  (* int_pin = "1" *) 
  (* intx = "TRUE" *) 
  (* max_lnk_spd = "2" *) 
  (* max_lnk_wdt = "000010" *) 
  (* mps = "010" *) 
  (* no_soft_rst = "TRUE" *) 
  (* pci_exp_int_freq = "2" *) 
  (* pci_exp_ref_freq = "0" *) 
  (* phantm_func_sup = "00" *) 
  (* pme_sup = "0F" *) 
  (* pwr_con_d0_state = "00" *) 
  (* pwr_con_d1_state = "00" *) 
  (* pwr_con_d2_state = "00" *) 
  (* pwr_con_d3_state = "00" *) 
  (* pwr_dis_d0_state = "00" *) 
  (* pwr_dis_d1_state = "00" *) 
  (* pwr_dis_d2_state = "00" *) 
  (* pwr_dis_d3_state = "00" *) 
  (* rev_id = "00" *) 
  (* slot_clk = "TRUE" *) 
  (* subsys_id = "0007" *) 
  (* subsys_ven_id = "10EE" *) 
  (* ven_id = "10EE" *) 
  (* xrom_bar = "00000000" *) 
  xdma_0_pcie2_ip_pcie2_top inst
       (.cfg_aer_ecrc_check_en(NLW_inst_cfg_aer_ecrc_check_en_UNCONNECTED),
        .cfg_aer_ecrc_gen_en(NLW_inst_cfg_aer_ecrc_gen_en_UNCONNECTED),
        .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
        .cfg_aer_rooterr_corr_err_received(NLW_inst_cfg_aer_rooterr_corr_err_received_UNCONNECTED),
        .cfg_aer_rooterr_corr_err_reporting_en(NLW_inst_cfg_aer_rooterr_corr_err_reporting_en_UNCONNECTED),
        .cfg_aer_rooterr_fatal_err_received(NLW_inst_cfg_aer_rooterr_fatal_err_received_UNCONNECTED),
        .cfg_aer_rooterr_fatal_err_reporting_en(NLW_inst_cfg_aer_rooterr_fatal_err_reporting_en_UNCONNECTED),
        .cfg_aer_rooterr_non_fatal_err_received(NLW_inst_cfg_aer_rooterr_non_fatal_err_received_UNCONNECTED),
        .cfg_aer_rooterr_non_fatal_err_reporting_en(NLW_inst_cfg_aer_rooterr_non_fatal_err_reporting_en_UNCONNECTED),
        .cfg_bridge_serr_en(NLW_inst_cfg_bridge_serr_en_UNCONNECTED),
        .cfg_bus_number(cfg_bus_number),
        .cfg_command({NLW_inst_cfg_command_UNCONNECTED[15:3],\^cfg_command ,NLW_inst_cfg_command_UNCONNECTED[1:0]}),
        .cfg_dcommand({NLW_inst_cfg_dcommand_UNCONNECTED[15],\^cfg_dcommand ,NLW_inst_cfg_dcommand_UNCONNECTED[4:0]}),
        .cfg_dcommand2(NLW_inst_cfg_dcommand2_UNCONNECTED[15:0]),
        .cfg_dev_id_pf0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}),
        .cfg_device_number(cfg_device_number),
        .cfg_ds_bus_number({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_ds_device_number({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_ds_function_number({1'b0,1'b0,1'b0}),
        .cfg_dsn(cfg_dsn),
        .cfg_dstatus(NLW_inst_cfg_dstatus_UNCONNECTED[15:0]),
        .cfg_err_acs(1'b0),
        .cfg_err_aer_headerlog(cfg_err_aer_headerlog),
        .cfg_err_aer_headerlog_set(NLW_inst_cfg_err_aer_headerlog_set_UNCONNECTED),
        .cfg_err_atomic_egress_blocked(1'b0),
        .cfg_err_cor(1'b0),
        .cfg_err_cpl_abort(1'b0),
        .cfg_err_cpl_rdy(NLW_inst_cfg_err_cpl_rdy_UNCONNECTED),
        .cfg_err_cpl_timeout(1'b0),
        .cfg_err_cpl_unexpect(1'b0),
        .cfg_err_ecrc(1'b0),
        .cfg_err_internal_cor(1'b0),
        .cfg_err_internal_uncor(1'b0),
        .cfg_err_locked(1'b0),
        .cfg_err_malformed(1'b0),
        .cfg_err_mc_blocked(1'b0),
        .cfg_err_norecovery(1'b0),
        .cfg_err_poisoned(1'b0),
        .cfg_err_posted(1'b0),
        .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
        .cfg_err_ur(1'b0),
        .cfg_function_number(cfg_function_number),
        .cfg_interrupt(cfg_interrupt),
        .cfg_interrupt_assert(cfg_interrupt_assert),
        .cfg_interrupt_di(cfg_interrupt_di),
        .cfg_interrupt_do(NLW_inst_cfg_interrupt_do_UNCONNECTED[7:0]),
        .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
        .cfg_interrupt_msienable(cfg_interrupt_msienable),
        .cfg_interrupt_msixenable(NLW_inst_cfg_interrupt_msixenable_UNCONNECTED),
        .cfg_interrupt_msixfm(NLW_inst_cfg_interrupt_msixfm_UNCONNECTED),
        .cfg_interrupt_rdy(cfg_interrupt_rdy),
        .cfg_interrupt_stat(1'b0),
        .cfg_lcommand(NLW_inst_cfg_lcommand_UNCONNECTED[15:0]),
        .cfg_lstatus(NLW_inst_cfg_lstatus_UNCONNECTED[15:0]),
        .cfg_mgmt_byte_en(cfg_mgmt_byte_en),
        .cfg_mgmt_di(cfg_mgmt_di),
        .cfg_mgmt_do(cfg_mgmt_do),
        .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
        .cfg_mgmt_rd_en(cfg_mgmt_rd_en),
        .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
        .cfg_mgmt_wr_en(cfg_mgmt_wr_en),
        .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
        .cfg_mgmt_wr_rw1c_as_rw(1'b0),
        .cfg_msg_data(NLW_inst_cfg_msg_data_UNCONNECTED[15:0]),
        .cfg_msg_received(NLW_inst_cfg_msg_received_UNCONNECTED),
        .cfg_msg_received_assert_int_a(NLW_inst_cfg_msg_received_assert_int_a_UNCONNECTED),
        .cfg_msg_received_assert_int_b(NLW_inst_cfg_msg_received_assert_int_b_UNCONNECTED),
        .cfg_msg_received_assert_int_c(NLW_inst_cfg_msg_received_assert_int_c_UNCONNECTED),
        .cfg_msg_received_assert_int_d(NLW_inst_cfg_msg_received_assert_int_d_UNCONNECTED),
        .cfg_msg_received_deassert_int_a(NLW_inst_cfg_msg_received_deassert_int_a_UNCONNECTED),
        .cfg_msg_received_deassert_int_b(NLW_inst_cfg_msg_received_deassert_int_b_UNCONNECTED),
        .cfg_msg_received_deassert_int_c(NLW_inst_cfg_msg_received_deassert_int_c_UNCONNECTED),
        .cfg_msg_received_deassert_int_d(NLW_inst_cfg_msg_received_deassert_int_d_UNCONNECTED),
        .cfg_msg_received_err_cor(NLW_inst_cfg_msg_received_err_cor_UNCONNECTED),
        .cfg_msg_received_err_fatal(NLW_inst_cfg_msg_received_err_fatal_UNCONNECTED),
        .cfg_msg_received_err_non_fatal(NLW_inst_cfg_msg_received_err_non_fatal_UNCONNECTED),
        .cfg_msg_received_pm_as_nak(NLW_inst_cfg_msg_received_pm_as_nak_UNCONNECTED),
        .cfg_msg_received_pm_pme(NLW_inst_cfg_msg_received_pm_pme_UNCONNECTED),
        .cfg_msg_received_pme_to_ack(NLW_inst_cfg_msg_received_pme_to_ack_UNCONNECTED),
        .cfg_msg_received_setslotpowerlimit(NLW_inst_cfg_msg_received_setslotpowerlimit_UNCONNECTED),
        .cfg_pcie_link_state(NLW_inst_cfg_pcie_link_state_UNCONNECTED[2:0]),
        .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
        .cfg_pm_force_state(cfg_pm_force_state),
        .cfg_pm_force_state_en(1'b0),
        .cfg_pm_halt_aspm_l0s(1'b0),
        .cfg_pm_halt_aspm_l1(1'b0),
        .cfg_pm_send_pme_to(1'b0),
        .cfg_pm_wake(1'b0),
        .cfg_pmcsr_pme_en(NLW_inst_cfg_pmcsr_pme_en_UNCONNECTED),
        .cfg_pmcsr_pme_status(NLW_inst_cfg_pmcsr_pme_status_UNCONNECTED),
        .cfg_pmcsr_powerstate(NLW_inst_cfg_pmcsr_powerstate_UNCONNECTED[1:0]),
        .cfg_received_func_lvl_rst(NLW_inst_cfg_received_func_lvl_rst_UNCONNECTED),
        .cfg_rev_id_pf0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_root_control_pme_int_en(NLW_inst_cfg_root_control_pme_int_en_UNCONNECTED),
        .cfg_root_control_syserr_corr_err_en(NLW_inst_cfg_root_control_syserr_corr_err_en_UNCONNECTED),
        .cfg_root_control_syserr_fatal_err_en(NLW_inst_cfg_root_control_syserr_fatal_err_en_UNCONNECTED),
        .cfg_root_control_syserr_non_fatal_err_en(NLW_inst_cfg_root_control_syserr_non_fatal_err_en_UNCONNECTED),
        .cfg_slot_control_electromech_il_ctl_pulse(NLW_inst_cfg_slot_control_electromech_il_ctl_pulse_UNCONNECTED),
        .cfg_status(NLW_inst_cfg_status_UNCONNECTED[15:0]),
        .cfg_subsys_id_pf0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}),
        .cfg_subsys_ven_id({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b1,1'b1,1'b1,1'b0}),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_trn_pending(1'b0),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .cfg_vc_tcvc_map(NLW_inst_cfg_vc_tcvc_map_UNCONNECTED[6:0]),
        .cfg_ven_id({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b1,1'b1,1'b1,1'b0}),
        .common_commands_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .common_commands_out(NLW_inst_common_commands_out_UNCONNECTED[11:0]),
        .ext_ch_gt_drpaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ext_ch_gt_drpclk(NLW_inst_ext_ch_gt_drpclk_UNCONNECTED),
        .ext_ch_gt_drpdi({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ext_ch_gt_drpdo(NLW_inst_ext_ch_gt_drpdo_UNCONNECTED[31:0]),
        .ext_ch_gt_drpen({1'b0,1'b0}),
        .ext_ch_gt_drprdy(NLW_inst_ext_ch_gt_drprdy_UNCONNECTED[1:0]),
        .ext_ch_gt_drpwe({1'b0,1'b0}),
        .fc_cpld(NLW_inst_fc_cpld_UNCONNECTED[11:0]),
        .fc_cplh(NLW_inst_fc_cplh_UNCONNECTED[7:0]),
        .fc_npd(NLW_inst_fc_npd_UNCONNECTED[11:0]),
        .fc_nph(fc_nph),
        .fc_pd(NLW_inst_fc_pd_UNCONNECTED[11:0]),
        .fc_ph(NLW_inst_fc_ph_UNCONNECTED[7:0]),
        .fc_sel(fc_sel),
        .gt_ch_drp_rdy(NLW_inst_gt_ch_drp_rdy_UNCONNECTED[1:0]),
        .icap_clk(1'b0),
        .icap_csib(1'b0),
        .icap_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .icap_o(NLW_inst_icap_o_UNCONNECTED[31:0]),
        .icap_rdwrb(1'b0),
        .int_dclk_out(NLW_inst_int_dclk_out_UNCONNECTED),
        .int_mmcm_lock_out(NLW_inst_int_mmcm_lock_out_UNCONNECTED),
        .int_oobclk_out(NLW_inst_int_oobclk_out_UNCONNECTED),
        .int_pclk_out_slave(NLW_inst_int_pclk_out_slave_UNCONNECTED),
        .int_pclk_sel_slave({1'b0,1'b0}),
        .int_pipe_rxusrclk_out(NLW_inst_int_pipe_rxusrclk_out_UNCONNECTED),
        .int_qplllock_out(NLW_inst_int_qplllock_out_UNCONNECTED[1:0]),
        .int_qplloutclk_out(NLW_inst_int_qplloutclk_out_UNCONNECTED[1:0]),
        .int_qplloutrefclk_out(NLW_inst_int_qplloutrefclk_out_UNCONNECTED[1:0]),
        .int_rxoutclk_out(NLW_inst_int_rxoutclk_out_UNCONNECTED[1:0]),
        .int_userclk1_out(NLW_inst_int_userclk1_out_UNCONNECTED),
        .int_userclk2_out(NLW_inst_int_userclk2_out_UNCONNECTED),
        .m_axis_rx_tdata(m_axis_rx_tdata),
        .m_axis_rx_tkeep({\^m_axis_rx_tkeep ,NLW_inst_m_axis_rx_tkeep_UNCONNECTED[3:0]}),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(\^m_axis_rx_tuser ),
        .m_axis_rx_tvalid(m_axis_rx_tvalid),
        .pci_exp_rxn(pci_exp_rxn),
        .pci_exp_rxp(pci_exp_rxp),
        .pci_exp_txn(pci_exp_txn),
        .pci_exp_txp(pci_exp_txp),
        .pcie_drp_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pcie_drp_clk(1'b1),
        .pcie_drp_di({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pcie_drp_do(NLW_inst_pcie_drp_do_UNCONNECTED[15:0]),
        .pcie_drp_en(1'b0),
        .pcie_drp_rdy(NLW_inst_pcie_drp_rdy_UNCONNECTED),
        .pcie_drp_we(1'b0),
        .pipe_cpll_lock(NLW_inst_pipe_cpll_lock_UNCONNECTED[1:0]),
        .pipe_dclk_in(1'b0),
        .pipe_debug(NLW_inst_pipe_debug_UNCONNECTED[31:0]),
        .pipe_debug_0(NLW_inst_pipe_debug_0_UNCONNECTED[1:0]),
        .pipe_debug_1(NLW_inst_pipe_debug_1_UNCONNECTED[1:0]),
        .pipe_debug_2(NLW_inst_pipe_debug_2_UNCONNECTED[1:0]),
        .pipe_debug_3(NLW_inst_pipe_debug_3_UNCONNECTED[1:0]),
        .pipe_debug_4(NLW_inst_pipe_debug_4_UNCONNECTED[1:0]),
        .pipe_debug_5(NLW_inst_pipe_debug_5_UNCONNECTED[1:0]),
        .pipe_debug_6(NLW_inst_pipe_debug_6_UNCONNECTED[1:0]),
        .pipe_debug_7(NLW_inst_pipe_debug_7_UNCONNECTED[1:0]),
        .pipe_debug_8(NLW_inst_pipe_debug_8_UNCONNECTED[1:0]),
        .pipe_debug_9(NLW_inst_pipe_debug_9_UNCONNECTED[1:0]),
        .pipe_dmonitorout(NLW_inst_pipe_dmonitorout_UNCONNECTED[29:0]),
        .pipe_drp_fsm(NLW_inst_pipe_drp_fsm_UNCONNECTED[13:0]),
        .pipe_eyescandataerror(NLW_inst_pipe_eyescandataerror_UNCONNECTED[1:0]),
        .pipe_gen3_out(NLW_inst_pipe_gen3_out_UNCONNECTED),
        .pipe_loopback({1'b0,1'b0,1'b0}),
        .pipe_mmcm_lock_in(1'b1),
        .pipe_mmcm_rst_n(1'b1),
        .pipe_oobclk_in(1'b0),
        .pipe_pclk_in(1'b0),
        .pipe_pclk_sel_out(NLW_inst_pipe_pclk_sel_out_UNCONNECTED[1:0]),
        .pipe_qpll_lock(NLW_inst_pipe_qpll_lock_UNCONNECTED[0]),
        .pipe_qrst_fsm(NLW_inst_pipe_qrst_fsm_UNCONNECTED[11:0]),
        .pipe_qrst_idle(NLW_inst_pipe_qrst_idle_UNCONNECTED),
        .pipe_rate_fsm(NLW_inst_pipe_rate_fsm_UNCONNECTED[9:0]),
        .pipe_rate_idle(NLW_inst_pipe_rate_idle_UNCONNECTED),
        .pipe_rst_fsm(NLW_inst_pipe_rst_fsm_UNCONNECTED[4:0]),
        .pipe_rst_idle(NLW_inst_pipe_rst_idle_UNCONNECTED),
        .pipe_rx_0_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_1_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_2_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_3_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_4_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_5_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_6_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_7_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rxbufstatus(NLW_inst_pipe_rxbufstatus_UNCONNECTED[5:0]),
        .pipe_rxcommadet(NLW_inst_pipe_rxcommadet_UNCONNECTED[1:0]),
        .pipe_rxdisperr(NLW_inst_pipe_rxdisperr_UNCONNECTED[15:0]),
        .pipe_rxdlysresetdone(NLW_inst_pipe_rxdlysresetdone_UNCONNECTED[1:0]),
        .pipe_rxnotintable(NLW_inst_pipe_rxnotintable_UNCONNECTED[15:0]),
        .pipe_rxoutclk_in({1'b0,1'b0}),
        .pipe_rxoutclk_out(NLW_inst_pipe_rxoutclk_out_UNCONNECTED[1:0]),
        .pipe_rxphaligndone(NLW_inst_pipe_rxphaligndone_UNCONNECTED[1:0]),
        .pipe_rxpmaresetdone(NLW_inst_pipe_rxpmaresetdone_UNCONNECTED[1:0]),
        .pipe_rxprbscntreset(1'b0),
        .pipe_rxprbserr(NLW_inst_pipe_rxprbserr_UNCONNECTED[1:0]),
        .pipe_rxprbssel({1'b0,1'b0,1'b0}),
        .pipe_rxstatus(NLW_inst_pipe_rxstatus_UNCONNECTED[5:0]),
        .pipe_rxsyncdone(NLW_inst_pipe_rxsyncdone_UNCONNECTED[1:0]),
        .pipe_rxusrclk_in(1'b0),
        .pipe_sync_fsm_rx(NLW_inst_pipe_sync_fsm_rx_UNCONNECTED[13:0]),
        .pipe_sync_fsm_tx(NLW_inst_pipe_sync_fsm_tx_UNCONNECTED[11:0]),
        .pipe_tx_0_sigs(NLW_inst_pipe_tx_0_sigs_UNCONNECTED[24:0]),
        .pipe_tx_1_sigs(NLW_inst_pipe_tx_1_sigs_UNCONNECTED[24:0]),
        .pipe_tx_2_sigs(NLW_inst_pipe_tx_2_sigs_UNCONNECTED[24:0]),
        .pipe_tx_3_sigs(NLW_inst_pipe_tx_3_sigs_UNCONNECTED[24:0]),
        .pipe_tx_4_sigs(NLW_inst_pipe_tx_4_sigs_UNCONNECTED[24:0]),
        .pipe_tx_5_sigs(NLW_inst_pipe_tx_5_sigs_UNCONNECTED[24:0]),
        .pipe_tx_6_sigs(NLW_inst_pipe_tx_6_sigs_UNCONNECTED[24:0]),
        .pipe_tx_7_sigs(NLW_inst_pipe_tx_7_sigs_UNCONNECTED[24:0]),
        .pipe_txdlysresetdone(NLW_inst_pipe_txdlysresetdone_UNCONNECTED[1:0]),
        .pipe_txinhibit({1'b0,1'b0}),
        .pipe_txoutclk_out(NLW_inst_pipe_txoutclk_out_UNCONNECTED),
        .pipe_txphaligndone(NLW_inst_pipe_txphaligndone_UNCONNECTED[1:0]),
        .pipe_txphinitdone(NLW_inst_pipe_txphinitdone_UNCONNECTED[1:0]),
        .pipe_txprbsforceerr(1'b0),
        .pipe_txprbssel({1'b0,1'b0,1'b0}),
        .pipe_userclk1_in(1'b1),
        .pipe_userclk2_in(1'b0),
        .pl_directed_change_done(NLW_inst_pl_directed_change_done_UNCONNECTED),
        .pl_directed_link_auton(pl_directed_link_auton),
        .pl_directed_link_change(pl_directed_link_change),
        .pl_directed_link_speed(pl_directed_link_speed),
        .pl_directed_link_width(pl_directed_link_width),
        .pl_downstream_deemph_source(1'b0),
        .pl_initial_link_width(NLW_inst_pl_initial_link_width_UNCONNECTED[2:0]),
        .pl_lane_reversal_mode(NLW_inst_pl_lane_reversal_mode_UNCONNECTED[1:0]),
        .pl_link_gen2_cap(NLW_inst_pl_link_gen2_cap_UNCONNECTED),
        .pl_link_partner_gen2_supported(NLW_inst_pl_link_partner_gen2_supported_UNCONNECTED),
        .pl_link_upcfg_cap(NLW_inst_pl_link_upcfg_cap_UNCONNECTED),
        .pl_ltssm_state(NLW_inst_pl_ltssm_state_UNCONNECTED[5:0]),
        .pl_phy_lnk_up(pl_phy_lnk_up),
        .pl_received_hot_rst(NLW_inst_pl_received_hot_rst_UNCONNECTED),
        .pl_rx_pm_state(NLW_inst_pl_rx_pm_state_UNCONNECTED[1:0]),
        .pl_sel_lnk_rate(NLW_inst_pl_sel_lnk_rate_UNCONNECTED),
        .pl_sel_lnk_width(NLW_inst_pl_sel_lnk_width_UNCONNECTED[1:0]),
        .pl_transmit_hot_rst(1'b0),
        .pl_tx_pm_state(NLW_inst_pl_tx_pm_state_UNCONNECTED[2:0]),
        .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
        .qpll_drp_clk(NLW_inst_qpll_drp_clk_UNCONNECTED),
        .qpll_drp_crscode({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .qpll_drp_done({1'b0,1'b0}),
        .qpll_drp_fsm({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .qpll_drp_gen3(NLW_inst_qpll_drp_gen3_UNCONNECTED),
        .qpll_drp_ovrd(NLW_inst_qpll_drp_ovrd_UNCONNECTED),
        .qpll_drp_reset({1'b0,1'b0}),
        .qpll_drp_rst_n(NLW_inst_qpll_drp_rst_n_UNCONNECTED),
        .qpll_drp_start(NLW_inst_qpll_drp_start_UNCONNECTED),
        .qpll_qplld(NLW_inst_qpll_qplld_UNCONNECTED),
        .qpll_qplllock({1'b0,1'b0}),
        .qpll_qplloutclk({1'b0,1'b0}),
        .qpll_qplloutrefclk({1'b0,1'b0}),
        .qpll_qpllreset(NLW_inst_qpll_qpllreset_UNCONNECTED[1:0]),
        .rx_np_ok(rx_np_ok),
        .rx_np_req(rx_np_req),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep({s_axis_tx_tkeep[7],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tready(s_axis_tx_tready),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .startup_cfgclk(NLW_inst_startup_cfgclk_UNCONNECTED),
        .startup_cfgmclk(NLW_inst_startup_cfgmclk_UNCONNECTED),
        .startup_clk(1'b0),
        .startup_eos(NLW_inst_startup_eos_UNCONNECTED),
        .startup_eos_in(1'b0),
        .startup_gsr(1'b0),
        .startup_gts(1'b0),
        .startup_keyclearb(1'b1),
        .startup_pack(1'b0),
        .startup_preq(NLW_inst_startup_preq_UNCONNECTED),
        .startup_usrcclko(1'b1),
        .startup_usrcclkts(1'b0),
        .startup_usrdoneo(1'b0),
        .startup_usrdonets(1'b1),
        .sys_clk(sys_clk),
        .sys_rst_n(sys_rst_n),
        .tx_buf_av(NLW_inst_tx_buf_av_UNCONNECTED[5:0]),
        .tx_cfg_gnt(tx_cfg_gnt),
        .tx_cfg_req(NLW_inst_tx_cfg_req_UNCONNECTED),
        .tx_err_drop(NLW_inst_tx_err_drop_UNCONNECTED),
        .user_app_rdy(NLW_inst_user_app_rdy_UNCONNECTED),
        .user_clk_out(user_clk_out),
        .user_lnk_up(user_lnk_up),
        .user_reset_out(user_reset_out));
endmodule

module xdma_0_pcie2_ip_axi_basic_rx
   (E,
    trn_rsrc_dsc_d,
    m_axis_rx_tvalid_reg,
    m_axis_rx_tkeep,
    m_axis_rx_tlast,
    trn_in_packet,
    reg_dsc_detect_reg,
    m_axis_rx_tuser,
    Q,
    \trn_rbar_hit_prev_reg[0] ,
    CLK,
    trn_rrem,
    trn_rsrc_dsc,
    rsrc_rdy_filtered,
    trn_reof,
    trn_rsrc_dsc_prev0,
    trn_rsof,
    trn_recrc_err,
    trn_rerrfwd,
    trn_in_packet_reg,
    m_axis_rx_tready,
    dsc_detect,
    trn_rd,
    trn_rbar_hit);
  output [0:0]E;
  output trn_rsrc_dsc_d;
  output m_axis_rx_tvalid_reg;
  output [0:0]m_axis_rx_tkeep;
  output m_axis_rx_tlast;
  output trn_in_packet;
  output reg_dsc_detect_reg;
  output [12:0]m_axis_rx_tuser;
  output [63:0]Q;
  input \trn_rbar_hit_prev_reg[0] ;
  input CLK;
  input [0:0]trn_rrem;
  input trn_rsrc_dsc;
  input rsrc_rdy_filtered;
  input trn_reof;
  input trn_rsrc_dsc_prev0;
  input trn_rsof;
  input trn_recrc_err;
  input trn_rerrfwd;
  input trn_in_packet_reg;
  input m_axis_rx_tready;
  input dsc_detect;
  input [63:0]trn_rd;
  input [6:0]trn_rbar_hit;

  wire CLK;
  wire [0:0]E;
  wire [63:0]Q;
  wire dsc_detect;
  wire [0:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [12:0]m_axis_rx_tuser;
  wire m_axis_rx_tvalid_reg;
  wire [10:0]new_pkt_len;
  wire null_mux_sel;
  wire reg_dsc_detect_reg;
  wire rsrc_rdy_filtered;
  wire rx_null_gen_inst_n_0;
  wire rx_null_gen_inst_n_1;
  wire rx_null_gen_inst_n_2;
  wire rx_null_gen_inst_n_3;
  wire rx_null_gen_inst_n_4;
  wire rx_null_gen_inst_n_5;
  wire rx_null_gen_inst_n_6;
  wire rx_null_gen_inst_n_7;
  wire rx_null_gen_inst_n_8;
  wire rx_pipeline_inst_n_73;
  wire rx_pipeline_inst_n_74;
  wire rx_pipeline_inst_n_8;
  wire trn_in_packet;
  wire trn_in_packet_reg;
  wire [6:0]trn_rbar_hit;
  wire \trn_rbar_hit_prev_reg[0] ;
  wire [63:0]trn_rd;
  wire trn_recrc_err;
  wire trn_reof;
  wire trn_rerrfwd;
  wire [0:0]trn_rrem;
  wire trn_rsof;
  wire trn_rsrc_dsc;
  wire trn_rsrc_dsc_d;
  wire trn_rsrc_dsc_prev0;

  xdma_0_pcie2_ip_axi_basic_rx_null_gen rx_null_gen_inst
       (.CLK(CLK),
        .D({rx_null_gen_inst_n_0,rx_null_gen_inst_n_1}),
        .Q({Q[30:29],Q[15],Q[1:0]}),
        .S({rx_null_gen_inst_n_7,rx_null_gen_inst_n_8}),
        .cur_state_reg_0(\trn_rbar_hit_prev_reg[0] ),
        .cur_state_reg_1(m_axis_rx_tvalid_reg),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser[12]),
        .\m_axis_rx_tuser_reg[19] (rx_pipeline_inst_n_74),
        .\m_axis_rx_tuser_reg[21] (rx_pipeline_inst_n_73),
        .new_pkt_len(new_pkt_len),
        .null_mux_sel(null_mux_sel),
        .null_mux_sel_reg(rx_null_gen_inst_n_5),
        .null_mux_sel_reg_0(rx_null_gen_inst_n_6),
        .null_mux_sel_reg_1(rx_pipeline_inst_n_8),
        .\reg_pkt_len_counter_reg[0]_0 (rx_null_gen_inst_n_4),
        .\reg_pkt_len_counter_reg[3]_0 (rx_null_gen_inst_n_3),
        .\reg_tkeep[4]_i_7_0 (rx_null_gen_inst_n_2));
  xdma_0_pcie2_ip_axi_basic_rx_pipeline rx_pipeline_inst
       (.CLK(CLK),
        .D({rx_null_gen_inst_n_0,rx_null_gen_inst_n_1}),
        .E(E),
        .Q(Q),
        .S({rx_null_gen_inst_n_7,rx_null_gen_inst_n_8}),
        .dsc_detect(dsc_detect),
        .m_axis_rx_tkeep(m_axis_rx_tkeep),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser),
        .m_axis_rx_tvalid_reg_0(m_axis_rx_tvalid_reg),
        .new_pkt_len(new_pkt_len),
        .null_mux_sel(null_mux_sel),
        .null_mux_sel_reg_0(rx_null_gen_inst_n_5),
        .pcie_block_i(rx_pipeline_inst_n_73),
        .pcie_block_i_0(rx_pipeline_inst_n_74),
        .reg_dsc_detect_reg_0(reg_dsc_detect_reg),
        .\reg_tkeep_reg[4]_0 (rx_null_gen_inst_n_3),
        .reg_tlast_reg_0(rx_null_gen_inst_n_6),
        .rsrc_rdy_filtered(rsrc_rdy_filtered),
        .trn_in_packet(trn_in_packet),
        .trn_in_packet_reg_0(trn_in_packet_reg),
        .trn_rbar_hit(trn_rbar_hit),
        .\trn_rbar_hit_prev_reg[0]_0 (\trn_rbar_hit_prev_reg[0] ),
        .trn_rd(trn_rd),
        .trn_rdst_rdy_reg_0(rx_null_gen_inst_n_2),
        .trn_rdst_rdy_reg_1(rx_null_gen_inst_n_4),
        .trn_recrc_err(trn_recrc_err),
        .trn_reof(trn_reof),
        .trn_rerrfwd(trn_rerrfwd),
        .trn_rrem(trn_rrem),
        .trn_rsof(trn_rsof),
        .trn_rsrc_dsc(trn_rsrc_dsc),
        .trn_rsrc_dsc_d(trn_rsrc_dsc_d),
        .trn_rsrc_dsc_prev0(trn_rsrc_dsc_prev0),
        .user_reset_out_reg(rx_pipeline_inst_n_8));
endmodule

module xdma_0_pcie2_ip_axi_basic_rx_null_gen
   (D,
    \reg_tkeep[4]_i_7_0 ,
    \reg_pkt_len_counter_reg[3]_0 ,
    \reg_pkt_len_counter_reg[0]_0 ,
    null_mux_sel_reg,
    null_mux_sel_reg_0,
    S,
    cur_state_reg_0,
    CLK,
    null_mux_sel,
    \m_axis_rx_tuser_reg[19] ,
    new_pkt_len,
    m_axis_rx_tready,
    null_mux_sel_reg_1,
    cur_state_reg_1,
    m_axis_rx_tuser,
    \m_axis_rx_tuser_reg[21] ,
    Q);
  output [1:0]D;
  output \reg_tkeep[4]_i_7_0 ;
  output \reg_pkt_len_counter_reg[3]_0 ;
  output \reg_pkt_len_counter_reg[0]_0 ;
  output null_mux_sel_reg;
  output null_mux_sel_reg_0;
  output [1:0]S;
  input cur_state_reg_0;
  input CLK;
  input null_mux_sel;
  input \m_axis_rx_tuser_reg[19] ;
  input [10:0]new_pkt_len;
  input m_axis_rx_tready;
  input null_mux_sel_reg_1;
  input cur_state_reg_1;
  input [0:0]m_axis_rx_tuser;
  input \m_axis_rx_tuser_reg[21] ;
  input [4:0]Q;

  wire CLK;
  wire [1:0]D;
  wire [4:0]Q;
  wire [1:0]S;
  wire cur_state;
  wire cur_state_reg_0;
  wire cur_state_reg_1;
  wire m_axis_rx_tready;
  wire [0:0]m_axis_rx_tuser;
  wire \m_axis_rx_tuser_reg[19] ;
  wire \m_axis_rx_tuser_reg[21] ;
  wire [10:0]new_pkt_len;
  wire next_state;
  wire null_mux_sel;
  wire null_mux_sel_reg;
  wire null_mux_sel_reg_0;
  wire null_mux_sel_reg_1;
  wire [11:1]pkt_len_counter;
  wire [1:0]pkt_len_counter_0;
  wire pkt_len_counter_dec__0_carry__0_i_1_n_0;
  wire pkt_len_counter_dec__0_carry__0_i_2_n_0;
  wire pkt_len_counter_dec__0_carry__0_i_3_n_0;
  wire pkt_len_counter_dec__0_carry__0_i_4_n_0;
  wire pkt_len_counter_dec__0_carry__0_n_0;
  wire pkt_len_counter_dec__0_carry__0_n_1;
  wire pkt_len_counter_dec__0_carry__0_n_2;
  wire pkt_len_counter_dec__0_carry__0_n_3;
  wire pkt_len_counter_dec__0_carry__1_i_1_n_0;
  wire pkt_len_counter_dec__0_carry__1_i_2_n_0;
  wire pkt_len_counter_dec__0_carry__1_i_3_n_0;
  wire pkt_len_counter_dec__0_carry__1_n_2;
  wire pkt_len_counter_dec__0_carry__1_n_3;
  wire pkt_len_counter_dec__0_carry_i_1_n_0;
  wire pkt_len_counter_dec__0_carry_i_2_n_0;
  wire pkt_len_counter_dec__0_carry_i_3_n_0;
  wire pkt_len_counter_dec__0_carry_i_4_n_0;
  wire pkt_len_counter_dec__0_carry_i_5_n_0;
  wire pkt_len_counter_dec__0_carry_n_0;
  wire pkt_len_counter_dec__0_carry_n_1;
  wire pkt_len_counter_dec__0_carry_n_2;
  wire pkt_len_counter_dec__0_carry_n_3;
  wire [11:0]reg_pkt_len_counter;
  wire \reg_pkt_len_counter[11]_i_2_n_0 ;
  wire \reg_pkt_len_counter[11]_i_3_n_0 ;
  wire \reg_pkt_len_counter[11]_i_4_n_0 ;
  wire \reg_pkt_len_counter_reg[0]_0 ;
  wire \reg_pkt_len_counter_reg[3]_0 ;
  wire \reg_tkeep[4]_i_4_n_0 ;
  wire \reg_tkeep[4]_i_5_n_0 ;
  wire \reg_tkeep[4]_i_6_n_0 ;
  wire \reg_tkeep[4]_i_7_0 ;
  wire \reg_tkeep[4]_i_7_n_0 ;
  wire [11:2]sel0;
  wire [3:2]NLW_pkt_len_counter_dec__0_carry__1_CO_UNCONNECTED;
  wire [3:3]NLW_pkt_len_counter_dec__0_carry__1_O_UNCONNECTED;

  LUT5 #(
    .INIT(32'hAAAAAAEA)) 
    cur_state_i_1
       (.I0(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I1(m_axis_rx_tready),
        .I2(cur_state_reg_1),
        .I3(cur_state),
        .I4(m_axis_rx_tuser),
        .O(next_state));
  FDRE cur_state_reg
       (.C(CLK),
        .CE(1'b1),
        .D(next_state),
        .Q(cur_state),
        .R(cur_state_reg_0));
  LUT6 #(
    .INIT(64'h5555555500000400)) 
    \m_axis_rx_tuser[19]_i_1 
       (.I0(cur_state_reg_0),
        .I1(\reg_tkeep[4]_i_7_0 ),
        .I2(\reg_pkt_len_counter_reg[3]_0 ),
        .I3(null_mux_sel),
        .I4(pkt_len_counter_0[0]),
        .I5(\m_axis_rx_tuser_reg[19] ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h00000000FF80FF08)) 
    \m_axis_rx_tuser[21]_i_2 
       (.I0(\reg_tkeep[4]_i_7_0 ),
        .I1(null_mux_sel),
        .I2(\reg_pkt_len_counter_reg[3]_0 ),
        .I3(\m_axis_rx_tuser_reg[21] ),
        .I4(pkt_len_counter_0[0]),
        .I5(cur_state_reg_0),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h0000000077F7FFFF)) 
    null_mux_sel_i_1
       (.I0(\reg_tkeep[4]_i_7_0 ),
        .I1(null_mux_sel),
        .I2(pkt_len_counter_0[0]),
        .I3(\reg_pkt_len_counter_reg[3]_0 ),
        .I4(m_axis_rx_tready),
        .I5(null_mux_sel_reg_1),
        .O(null_mux_sel_reg));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 pkt_len_counter_dec__0_carry
       (.CI(1'b0),
        .CO({pkt_len_counter_dec__0_carry_n_0,pkt_len_counter_dec__0_carry_n_1,pkt_len_counter_dec__0_carry_n_2,pkt_len_counter_dec__0_carry_n_3}),
        .CYINIT(1'b0),
        .DI({reg_pkt_len_counter[3:2],pkt_len_counter_dec__0_carry_i_1_n_0,1'b0}),
        .O(pkt_len_counter[4:1]),
        .S({pkt_len_counter_dec__0_carry_i_2_n_0,pkt_len_counter_dec__0_carry_i_3_n_0,pkt_len_counter_dec__0_carry_i_4_n_0,pkt_len_counter_dec__0_carry_i_5_n_0}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 pkt_len_counter_dec__0_carry__0
       (.CI(pkt_len_counter_dec__0_carry_n_0),
        .CO({pkt_len_counter_dec__0_carry__0_n_0,pkt_len_counter_dec__0_carry__0_n_1,pkt_len_counter_dec__0_carry__0_n_2,pkt_len_counter_dec__0_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI(reg_pkt_len_counter[7:4]),
        .O(pkt_len_counter[8:5]),
        .S({pkt_len_counter_dec__0_carry__0_i_1_n_0,pkt_len_counter_dec__0_carry__0_i_2_n_0,pkt_len_counter_dec__0_carry__0_i_3_n_0,pkt_len_counter_dec__0_carry__0_i_4_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    pkt_len_counter_dec__0_carry__0_i_1
       (.I0(reg_pkt_len_counter[7]),
        .I1(reg_pkt_len_counter[8]),
        .O(pkt_len_counter_dec__0_carry__0_i_1_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    pkt_len_counter_dec__0_carry__0_i_2
       (.I0(reg_pkt_len_counter[6]),
        .I1(reg_pkt_len_counter[7]),
        .O(pkt_len_counter_dec__0_carry__0_i_2_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    pkt_len_counter_dec__0_carry__0_i_3
       (.I0(reg_pkt_len_counter[5]),
        .I1(reg_pkt_len_counter[6]),
        .O(pkt_len_counter_dec__0_carry__0_i_3_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    pkt_len_counter_dec__0_carry__0_i_4
       (.I0(reg_pkt_len_counter[4]),
        .I1(reg_pkt_len_counter[5]),
        .O(pkt_len_counter_dec__0_carry__0_i_4_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 pkt_len_counter_dec__0_carry__1
       (.CI(pkt_len_counter_dec__0_carry__0_n_0),
        .CO({NLW_pkt_len_counter_dec__0_carry__1_CO_UNCONNECTED[3:2],pkt_len_counter_dec__0_carry__1_n_2,pkt_len_counter_dec__0_carry__1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,reg_pkt_len_counter[9:8]}),
        .O({NLW_pkt_len_counter_dec__0_carry__1_O_UNCONNECTED[3],pkt_len_counter[11:9]}),
        .S({1'b0,pkt_len_counter_dec__0_carry__1_i_1_n_0,pkt_len_counter_dec__0_carry__1_i_2_n_0,pkt_len_counter_dec__0_carry__1_i_3_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    pkt_len_counter_dec__0_carry__1_i_1
       (.I0(reg_pkt_len_counter[10]),
        .I1(reg_pkt_len_counter[11]),
        .O(pkt_len_counter_dec__0_carry__1_i_1_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    pkt_len_counter_dec__0_carry__1_i_2
       (.I0(reg_pkt_len_counter[9]),
        .I1(reg_pkt_len_counter[10]),
        .O(pkt_len_counter_dec__0_carry__1_i_2_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    pkt_len_counter_dec__0_carry__1_i_3
       (.I0(reg_pkt_len_counter[8]),
        .I1(reg_pkt_len_counter[9]),
        .O(pkt_len_counter_dec__0_carry__1_i_3_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    pkt_len_counter_dec__0_carry_i_1
       (.I0(reg_pkt_len_counter[1]),
        .I1(m_axis_rx_tready),
        .O(pkt_len_counter_dec__0_carry_i_1_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    pkt_len_counter_dec__0_carry_i_2
       (.I0(reg_pkt_len_counter[3]),
        .I1(reg_pkt_len_counter[4]),
        .O(pkt_len_counter_dec__0_carry_i_2_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    pkt_len_counter_dec__0_carry_i_3
       (.I0(reg_pkt_len_counter[2]),
        .I1(reg_pkt_len_counter[3]),
        .O(pkt_len_counter_dec__0_carry_i_3_n_0));
  LUT3 #(
    .INIT(8'hD2)) 
    pkt_len_counter_dec__0_carry_i_4
       (.I0(m_axis_rx_tready),
        .I1(reg_pkt_len_counter[1]),
        .I2(reg_pkt_len_counter[2]),
        .O(pkt_len_counter_dec__0_carry_i_4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    pkt_len_counter_dec__0_carry_i_5
       (.I0(reg_pkt_len_counter[1]),
        .I1(m_axis_rx_tready),
        .O(pkt_len_counter_dec__0_carry_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1857" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[0]_i_1 
       (.I0(reg_pkt_len_counter[0]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[0]),
        .O(pkt_len_counter_0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1854" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[10]_i_1 
       (.I0(pkt_len_counter[10]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[10]),
        .O(sel0[10]));
  (* SOFT_HLUTNM = "soft_lutpair1854" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \reg_pkt_len_counter[11]_i_1 
       (.I0(pkt_len_counter[11]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .O(sel0[11]));
  LUT6 #(
    .INIT(64'hAAAAAAA8AAAAAAAA)) 
    \reg_pkt_len_counter[11]_i_2 
       (.I0(cur_state),
        .I1(reg_pkt_len_counter[3]),
        .I2(reg_pkt_len_counter[8]),
        .I3(reg_pkt_len_counter[7]),
        .I4(\reg_pkt_len_counter[11]_i_3_n_0 ),
        .I5(\reg_pkt_len_counter[11]_i_4_n_0 ),
        .O(\reg_pkt_len_counter[11]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFFEF)) 
    \reg_pkt_len_counter[11]_i_3 
       (.I0(reg_pkt_len_counter[5]),
        .I1(reg_pkt_len_counter[4]),
        .I2(m_axis_rx_tready),
        .I3(reg_pkt_len_counter[9]),
        .O(\reg_pkt_len_counter[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000007)) 
    \reg_pkt_len_counter[11]_i_4 
       (.I0(reg_pkt_len_counter[0]),
        .I1(reg_pkt_len_counter[1]),
        .I2(reg_pkt_len_counter[2]),
        .I3(reg_pkt_len_counter[6]),
        .I4(reg_pkt_len_counter[10]),
        .I5(reg_pkt_len_counter[11]),
        .O(\reg_pkt_len_counter[11]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \reg_pkt_len_counter[1]_i_1 
       (.I0(new_pkt_len[1]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(pkt_len_counter[1]),
        .O(pkt_len_counter_0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1853" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[2]_i_1 
       (.I0(pkt_len_counter[2]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[2]),
        .O(sel0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1856" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[3]_i_1 
       (.I0(pkt_len_counter[3]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[3]),
        .O(sel0[3]));
  LUT4 #(
    .INIT(16'h1EEE)) 
    \reg_pkt_len_counter[3]_i_7 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[4]),
        .O(S[1]));
  LUT4 #(
    .INIT(16'h6999)) 
    \reg_pkt_len_counter[3]_i_8 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(Q[4]),
        .I3(Q[0]),
        .O(S[0]));
  (* SOFT_HLUTNM = "soft_lutpair1852" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[4]_i_1 
       (.I0(pkt_len_counter[4]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[4]),
        .O(sel0[4]));
  (* SOFT_HLUTNM = "soft_lutpair1856" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[5]_i_1 
       (.I0(pkt_len_counter[5]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[5]),
        .O(sel0[5]));
  (* SOFT_HLUTNM = "soft_lutpair1851" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[6]_i_1 
       (.I0(pkt_len_counter[6]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[6]),
        .O(sel0[6]));
  (* SOFT_HLUTNM = "soft_lutpair1855" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[7]_i_1 
       (.I0(pkt_len_counter[7]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[7]),
        .O(sel0[7]));
  (* SOFT_HLUTNM = "soft_lutpair1850" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[8]_i_1 
       (.I0(pkt_len_counter[8]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[8]),
        .O(sel0[8]));
  (* SOFT_HLUTNM = "soft_lutpair1855" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[9]_i_1 
       (.I0(pkt_len_counter[9]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[9]),
        .O(sel0[9]));
  FDRE \reg_pkt_len_counter_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pkt_len_counter_0[0]),
        .Q(reg_pkt_len_counter[0]),
        .R(cur_state_reg_0));
  FDRE \reg_pkt_len_counter_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(sel0[10]),
        .Q(reg_pkt_len_counter[10]),
        .R(cur_state_reg_0));
  FDRE \reg_pkt_len_counter_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(sel0[11]),
        .Q(reg_pkt_len_counter[11]),
        .R(cur_state_reg_0));
  FDRE \reg_pkt_len_counter_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pkt_len_counter_0[1]),
        .Q(reg_pkt_len_counter[1]),
        .R(cur_state_reg_0));
  FDRE \reg_pkt_len_counter_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(sel0[2]),
        .Q(reg_pkt_len_counter[2]),
        .R(cur_state_reg_0));
  FDRE \reg_pkt_len_counter_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(sel0[3]),
        .Q(reg_pkt_len_counter[3]),
        .R(cur_state_reg_0));
  FDRE \reg_pkt_len_counter_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(sel0[4]),
        .Q(reg_pkt_len_counter[4]),
        .R(cur_state_reg_0));
  FDRE \reg_pkt_len_counter_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(sel0[5]),
        .Q(reg_pkt_len_counter[5]),
        .R(cur_state_reg_0));
  FDRE \reg_pkt_len_counter_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(sel0[6]),
        .Q(reg_pkt_len_counter[6]),
        .R(cur_state_reg_0));
  FDRE \reg_pkt_len_counter_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(sel0[7]),
        .Q(reg_pkt_len_counter[7]),
        .R(cur_state_reg_0));
  FDRE \reg_pkt_len_counter_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(sel0[8]),
        .Q(reg_pkt_len_counter[8]),
        .R(cur_state_reg_0));
  FDRE \reg_pkt_len_counter_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(sel0[9]),
        .Q(reg_pkt_len_counter[9]),
        .R(cur_state_reg_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \reg_tkeep[4]_i_2 
       (.I0(sel0[11]),
        .I1(sel0[10]),
        .I2(\reg_tkeep[4]_i_4_n_0 ),
        .I3(\reg_tkeep[4]_i_5_n_0 ),
        .I4(\reg_tkeep[4]_i_6_n_0 ),
        .I5(\reg_tkeep[4]_i_7_n_0 ),
        .O(\reg_tkeep[4]_i_7_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1857" *) 
  LUT3 #(
    .INIT(8'h47)) 
    \reg_tkeep[4]_i_3 
       (.I0(pkt_len_counter[1]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[1]),
        .O(\reg_pkt_len_counter_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1850" *) 
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    \reg_tkeep[4]_i_4 
       (.I0(new_pkt_len[8]),
        .I1(pkt_len_counter[8]),
        .I2(new_pkt_len[9]),
        .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I4(pkt_len_counter[9]),
        .O(\reg_tkeep[4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1851" *) 
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    \reg_tkeep[4]_i_5 
       (.I0(new_pkt_len[6]),
        .I1(pkt_len_counter[6]),
        .I2(new_pkt_len[7]),
        .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I4(pkt_len_counter[7]),
        .O(\reg_tkeep[4]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1852" *) 
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    \reg_tkeep[4]_i_6 
       (.I0(new_pkt_len[4]),
        .I1(pkt_len_counter[4]),
        .I2(new_pkt_len[5]),
        .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I4(pkt_len_counter[5]),
        .O(\reg_tkeep[4]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1853" *) 
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    \reg_tkeep[4]_i_7 
       (.I0(new_pkt_len[2]),
        .I1(pkt_len_counter[2]),
        .I2(new_pkt_len[3]),
        .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I4(pkt_len_counter[3]),
        .O(\reg_tkeep[4]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFB000)) 
    reg_tlast_i_1
       (.I0(\reg_pkt_len_counter_reg[3]_0 ),
        .I1(pkt_len_counter_0[0]),
        .I2(null_mux_sel),
        .I3(\reg_tkeep[4]_i_7_0 ),
        .I4(\m_axis_rx_tuser_reg[21] ),
        .O(null_mux_sel_reg_0));
  LUT6 #(
    .INIT(64'hB8308800FFFFFFFF)) 
    trn_rdst_rdy_i_3
       (.I0(pkt_len_counter[1]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(new_pkt_len[1]),
        .I3(reg_pkt_len_counter[0]),
        .I4(new_pkt_len[0]),
        .I5(null_mux_sel),
        .O(\reg_pkt_len_counter_reg[0]_0 ));
endmodule

module xdma_0_pcie2_ip_axi_basic_rx_pipeline
   (E,
    trn_rsrc_dsc_d,
    m_axis_rx_tvalid_reg_0,
    m_axis_rx_tkeep,
    m_axis_rx_tlast,
    null_mux_sel,
    trn_in_packet,
    reg_dsc_detect_reg_0,
    user_reset_out_reg,
    Q,
    pcie_block_i,
    pcie_block_i_0,
    new_pkt_len,
    m_axis_rx_tuser,
    \trn_rbar_hit_prev_reg[0]_0 ,
    CLK,
    trn_rrem,
    trn_rsrc_dsc,
    rsrc_rdy_filtered,
    trn_reof,
    reg_tlast_reg_0,
    trn_rsrc_dsc_prev0,
    trn_rsof,
    trn_recrc_err,
    trn_rerrfwd,
    null_mux_sel_reg_0,
    trn_in_packet_reg_0,
    m_axis_rx_tready,
    dsc_detect,
    trn_rdst_rdy_reg_0,
    trn_rdst_rdy_reg_1,
    \reg_tkeep_reg[4]_0 ,
    trn_rd,
    trn_rbar_hit,
    S,
    D);
  output [0:0]E;
  output trn_rsrc_dsc_d;
  output m_axis_rx_tvalid_reg_0;
  output [0:0]m_axis_rx_tkeep;
  output m_axis_rx_tlast;
  output null_mux_sel;
  output trn_in_packet;
  output reg_dsc_detect_reg_0;
  output user_reset_out_reg;
  output [63:0]Q;
  output pcie_block_i;
  output pcie_block_i_0;
  output [10:0]new_pkt_len;
  output [12:0]m_axis_rx_tuser;
  input \trn_rbar_hit_prev_reg[0]_0 ;
  input CLK;
  input [0:0]trn_rrem;
  input trn_rsrc_dsc;
  input rsrc_rdy_filtered;
  input trn_reof;
  input reg_tlast_reg_0;
  input trn_rsrc_dsc_prev0;
  input trn_rsof;
  input trn_recrc_err;
  input trn_rerrfwd;
  input null_mux_sel_reg_0;
  input trn_in_packet_reg_0;
  input m_axis_rx_tready;
  input dsc_detect;
  input trn_rdst_rdy_reg_0;
  input trn_rdst_rdy_reg_1;
  input \reg_tkeep_reg[4]_0 ;
  input [63:0]trn_rd;
  input [6:0]trn_rbar_hit;
  input [1:0]S;
  input [1:0]D;

  wire CLK;
  wire [1:0]D;
  wire [0:0]E;
  wire [63:0]Q;
  wire [1:0]S;
  wire data_hold;
  wire data_prev;
  wire dsc_detect;
  wire \m_axis_rx_tdata[63]_i_1_n_0 ;
  wire [0:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [12:0]m_axis_rx_tuser;
  wire \m_axis_rx_tuser[0]_i_1_n_0 ;
  wire \m_axis_rx_tuser[14]_i_1_n_0 ;
  wire \m_axis_rx_tuser[14]_i_2_n_0 ;
  wire \m_axis_rx_tuser[18]_i_1_n_0 ;
  wire \m_axis_rx_tuser[1]_i_1_n_0 ;
  wire \m_axis_rx_tuser[21]_i_1_n_0 ;
  wire \m_axis_rx_tuser[2]_i_1_n_0 ;
  wire \m_axis_rx_tuser[3]_i_1_n_0 ;
  wire \m_axis_rx_tuser[4]_i_1_n_0 ;
  wire \m_axis_rx_tuser[5]_i_1_n_0 ;
  wire \m_axis_rx_tuser[6]_i_1_n_0 ;
  wire \m_axis_rx_tuser[7]_i_1_n_0 ;
  wire \m_axis_rx_tuser[8]_i_1_n_0 ;
  wire m_axis_rx_tvalid_i_1_n_0;
  wire m_axis_rx_tvalid_reg_0;
  wire [10:0]new_pkt_len;
  wire null_mux_sel;
  wire null_mux_sel_reg_0;
  wire [63:0]p_1_in;
  wire [1:0]packet_overhead;
  wire pcie_block_i;
  wire pcie_block_i_0;
  wire reg_dsc_detect_i_1_n_0;
  wire reg_dsc_detect_reg_0;
  wire \reg_pkt_len_counter[10]_i_3_n_0 ;
  wire \reg_pkt_len_counter[10]_i_4_n_0 ;
  wire \reg_pkt_len_counter[3]_i_5_n_0 ;
  wire \reg_pkt_len_counter[3]_i_6_n_0 ;
  wire \reg_pkt_len_counter[7]_i_3_n_0 ;
  wire \reg_pkt_len_counter[7]_i_4_n_0 ;
  wire \reg_pkt_len_counter[7]_i_5_n_0 ;
  wire \reg_pkt_len_counter[7]_i_6_n_0 ;
  wire \reg_pkt_len_counter_reg[10]_i_2_n_3 ;
  wire \reg_pkt_len_counter_reg[3]_i_2_n_0 ;
  wire \reg_pkt_len_counter_reg[3]_i_2_n_1 ;
  wire \reg_pkt_len_counter_reg[3]_i_2_n_2 ;
  wire \reg_pkt_len_counter_reg[3]_i_2_n_3 ;
  wire \reg_pkt_len_counter_reg[7]_i_2_n_0 ;
  wire \reg_pkt_len_counter_reg[7]_i_2_n_1 ;
  wire \reg_pkt_len_counter_reg[7]_i_2_n_2 ;
  wire \reg_pkt_len_counter_reg[7]_i_2_n_3 ;
  wire [7:7]reg_tkeep;
  wire \reg_tkeep_reg[4]_0 ;
  wire reg_tlast_reg_0;
  wire rsrc_rdy_filtered;
  wire trn_in_packet;
  wire trn_in_packet_reg_0;
  wire [6:0]trn_rbar_hit;
  wire [6:0]trn_rbar_hit_prev;
  wire \trn_rbar_hit_prev_reg[0]_0 ;
  wire [63:0]trn_rd;
  wire [63:0]trn_rd_prev;
  wire trn_rdst_rdy_i_1_n_0;
  wire trn_rdst_rdy_i_2_n_0;
  wire trn_rdst_rdy_reg_0;
  wire trn_rdst_rdy_reg_1;
  wire trn_recrc_err;
  wire trn_recrc_err_prev;
  wire trn_reof;
  wire trn_reof_prev;
  wire trn_rerrfwd;
  wire trn_rerrfwd_prev;
  wire [0:0]trn_rrem;
  wire trn_rrem_prev;
  wire trn_rsof;
  wire trn_rsof_prev;
  wire trn_rsrc_dsc;
  wire trn_rsrc_dsc_d;
  wire trn_rsrc_dsc_prev;
  wire trn_rsrc_dsc_prev0;
  wire trn_rsrc_rdy_prev;
  wire user_reset_out_reg;
  wire [3:1]\NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED ;
  wire [3:2]\NLW_reg_pkt_len_counter_reg[10]_i_2_O_UNCONNECTED ;

  LUT2 #(
    .INIT(4'h2)) 
    data_prev_i_1
       (.I0(m_axis_rx_tvalid_reg_0),
        .I1(m_axis_rx_tready),
        .O(data_hold));
  FDRE data_prev_reg
       (.C(CLK),
        .CE(1'b1),
        .D(data_hold),
        .Q(data_prev),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1886" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[0]_i_1 
       (.I0(trn_rd_prev[0]),
        .I1(data_prev),
        .I2(trn_rd[32]),
        .O(p_1_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair1889" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[10]_i_1 
       (.I0(trn_rd_prev[10]),
        .I1(data_prev),
        .I2(trn_rd[42]),
        .O(p_1_in[10]));
  (* SOFT_HLUTNM = "soft_lutpair1887" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[11]_i_1 
       (.I0(trn_rd_prev[11]),
        .I1(data_prev),
        .I2(trn_rd[43]),
        .O(p_1_in[11]));
  (* SOFT_HLUTNM = "soft_lutpair1883" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[12]_i_1 
       (.I0(trn_rd_prev[12]),
        .I1(data_prev),
        .I2(trn_rd[44]),
        .O(p_1_in[12]));
  (* SOFT_HLUTNM = "soft_lutpair1882" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[13]_i_1 
       (.I0(trn_rd_prev[13]),
        .I1(data_prev),
        .I2(trn_rd[45]),
        .O(p_1_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair1892" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[14]_i_1 
       (.I0(trn_rd_prev[14]),
        .I1(data_prev),
        .I2(trn_rd[46]),
        .O(p_1_in[14]));
  (* SOFT_HLUTNM = "soft_lutpair1884" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[15]_i_1 
       (.I0(trn_rd_prev[15]),
        .I1(data_prev),
        .I2(trn_rd[47]),
        .O(p_1_in[15]));
  (* SOFT_HLUTNM = "soft_lutpair1881" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[16]_i_1 
       (.I0(trn_rd_prev[16]),
        .I1(data_prev),
        .I2(trn_rd[48]),
        .O(p_1_in[16]));
  (* SOFT_HLUTNM = "soft_lutpair1877" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[17]_i_1 
       (.I0(trn_rd_prev[17]),
        .I1(data_prev),
        .I2(trn_rd[49]),
        .O(p_1_in[17]));
  (* SOFT_HLUTNM = "soft_lutpair1875" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[18]_i_1 
       (.I0(trn_rd_prev[18]),
        .I1(data_prev),
        .I2(trn_rd[50]),
        .O(p_1_in[18]));
  (* SOFT_HLUTNM = "soft_lutpair1889" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[19]_i_1 
       (.I0(trn_rd_prev[19]),
        .I1(data_prev),
        .I2(trn_rd[51]),
        .O(p_1_in[19]));
  (* SOFT_HLUTNM = "soft_lutpair1892" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[1]_i_1 
       (.I0(trn_rd_prev[1]),
        .I1(data_prev),
        .I2(trn_rd[33]),
        .O(p_1_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair1885" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[20]_i_1 
       (.I0(trn_rd_prev[20]),
        .I1(data_prev),
        .I2(trn_rd[52]),
        .O(p_1_in[20]));
  (* SOFT_HLUTNM = "soft_lutpair1879" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[21]_i_1 
       (.I0(trn_rd_prev[21]),
        .I1(data_prev),
        .I2(trn_rd[53]),
        .O(p_1_in[21]));
  (* SOFT_HLUTNM = "soft_lutpair1888" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[22]_i_1 
       (.I0(trn_rd_prev[22]),
        .I1(data_prev),
        .I2(trn_rd[54]),
        .O(p_1_in[22]));
  (* SOFT_HLUTNM = "soft_lutpair1890" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[23]_i_1 
       (.I0(trn_rd_prev[23]),
        .I1(data_prev),
        .I2(trn_rd[55]),
        .O(p_1_in[23]));
  (* SOFT_HLUTNM = "soft_lutpair1885" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[24]_i_1 
       (.I0(trn_rd_prev[24]),
        .I1(data_prev),
        .I2(trn_rd[56]),
        .O(p_1_in[24]));
  (* SOFT_HLUTNM = "soft_lutpair1873" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[25]_i_1 
       (.I0(trn_rd_prev[25]),
        .I1(data_prev),
        .I2(trn_rd[57]),
        .O(p_1_in[25]));
  (* SOFT_HLUTNM = "soft_lutpair1872" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[26]_i_1 
       (.I0(trn_rd_prev[26]),
        .I1(data_prev),
        .I2(trn_rd[58]),
        .O(p_1_in[26]));
  (* SOFT_HLUTNM = "soft_lutpair1874" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[27]_i_1 
       (.I0(trn_rd_prev[27]),
        .I1(data_prev),
        .I2(trn_rd[59]),
        .O(p_1_in[27]));
  (* SOFT_HLUTNM = "soft_lutpair1880" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[28]_i_1 
       (.I0(trn_rd_prev[28]),
        .I1(data_prev),
        .I2(trn_rd[60]),
        .O(p_1_in[28]));
  (* SOFT_HLUTNM = "soft_lutpair1871" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[29]_i_1 
       (.I0(trn_rd_prev[29]),
        .I1(data_prev),
        .I2(trn_rd[61]),
        .O(p_1_in[29]));
  (* SOFT_HLUTNM = "soft_lutpair1883" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[2]_i_1 
       (.I0(trn_rd_prev[2]),
        .I1(data_prev),
        .I2(trn_rd[34]),
        .O(p_1_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair1871" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[30]_i_1 
       (.I0(trn_rd_prev[30]),
        .I1(data_prev),
        .I2(trn_rd[62]),
        .O(p_1_in[30]));
  (* SOFT_HLUTNM = "soft_lutpair1864" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[31]_i_1 
       (.I0(trn_rd_prev[31]),
        .I1(data_prev),
        .I2(trn_rd[63]),
        .O(p_1_in[31]));
  (* SOFT_HLUTNM = "soft_lutpair1869" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[32]_i_1 
       (.I0(trn_rd_prev[32]),
        .I1(data_prev),
        .I2(trn_rd[0]),
        .O(p_1_in[32]));
  (* SOFT_HLUTNM = "soft_lutpair1861" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[33]_i_1 
       (.I0(trn_rd_prev[33]),
        .I1(data_prev),
        .I2(trn_rd[1]),
        .O(p_1_in[33]));
  (* SOFT_HLUTNM = "soft_lutpair1868" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[34]_i_1 
       (.I0(trn_rd_prev[34]),
        .I1(data_prev),
        .I2(trn_rd[2]),
        .O(p_1_in[34]));
  (* SOFT_HLUTNM = "soft_lutpair1862" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[35]_i_1 
       (.I0(trn_rd_prev[35]),
        .I1(data_prev),
        .I2(trn_rd[3]),
        .O(p_1_in[35]));
  (* SOFT_HLUTNM = "soft_lutpair1870" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[36]_i_1 
       (.I0(trn_rd_prev[36]),
        .I1(data_prev),
        .I2(trn_rd[4]),
        .O(p_1_in[36]));
  (* SOFT_HLUTNM = "soft_lutpair1862" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[37]_i_1 
       (.I0(trn_rd_prev[37]),
        .I1(data_prev),
        .I2(trn_rd[5]),
        .O(p_1_in[37]));
  (* SOFT_HLUTNM = "soft_lutpair1869" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[38]_i_1 
       (.I0(trn_rd_prev[38]),
        .I1(data_prev),
        .I2(trn_rd[6]),
        .O(p_1_in[38]));
  (* SOFT_HLUTNM = "soft_lutpair1866" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[39]_i_1 
       (.I0(trn_rd_prev[39]),
        .I1(data_prev),
        .I2(trn_rd[7]),
        .O(p_1_in[39]));
  (* SOFT_HLUTNM = "soft_lutpair1891" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[3]_i_1 
       (.I0(trn_rd_prev[3]),
        .I1(data_prev),
        .I2(trn_rd[35]),
        .O(p_1_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair1867" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[40]_i_1 
       (.I0(trn_rd_prev[40]),
        .I1(data_prev),
        .I2(trn_rd[8]),
        .O(p_1_in[40]));
  (* SOFT_HLUTNM = "soft_lutpair1866" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[41]_i_1 
       (.I0(trn_rd_prev[41]),
        .I1(data_prev),
        .I2(trn_rd[9]),
        .O(p_1_in[41]));
  (* SOFT_HLUTNM = "soft_lutpair1864" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[42]_i_1 
       (.I0(trn_rd_prev[42]),
        .I1(data_prev),
        .I2(trn_rd[10]),
        .O(p_1_in[42]));
  (* SOFT_HLUTNM = "soft_lutpair1867" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[43]_i_1 
       (.I0(trn_rd_prev[43]),
        .I1(data_prev),
        .I2(trn_rd[11]),
        .O(p_1_in[43]));
  (* SOFT_HLUTNM = "soft_lutpair1872" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[44]_i_1 
       (.I0(trn_rd_prev[44]),
        .I1(data_prev),
        .I2(trn_rd[12]),
        .O(p_1_in[44]));
  (* SOFT_HLUTNM = "soft_lutpair1870" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[45]_i_1 
       (.I0(trn_rd_prev[45]),
        .I1(data_prev),
        .I2(trn_rd[13]),
        .O(p_1_in[45]));
  (* SOFT_HLUTNM = "soft_lutpair1863" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[46]_i_1 
       (.I0(trn_rd_prev[46]),
        .I1(data_prev),
        .I2(trn_rd[14]),
        .O(p_1_in[46]));
  (* SOFT_HLUTNM = "soft_lutpair1875" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[47]_i_1 
       (.I0(trn_rd_prev[47]),
        .I1(data_prev),
        .I2(trn_rd[15]),
        .O(p_1_in[47]));
  (* SOFT_HLUTNM = "soft_lutpair1863" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[48]_i_1 
       (.I0(trn_rd_prev[48]),
        .I1(data_prev),
        .I2(trn_rd[16]),
        .O(p_1_in[48]));
  (* SOFT_HLUTNM = "soft_lutpair1878" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[49]_i_1 
       (.I0(trn_rd_prev[49]),
        .I1(data_prev),
        .I2(trn_rd[17]),
        .O(p_1_in[49]));
  (* SOFT_HLUTNM = "soft_lutpair1891" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[4]_i_1 
       (.I0(trn_rd_prev[4]),
        .I1(data_prev),
        .I2(trn_rd[36]),
        .O(p_1_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair1876" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[50]_i_1 
       (.I0(trn_rd_prev[50]),
        .I1(data_prev),
        .I2(trn_rd[18]),
        .O(p_1_in[50]));
  (* SOFT_HLUTNM = "soft_lutpair1874" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[51]_i_1 
       (.I0(trn_rd_prev[51]),
        .I1(data_prev),
        .I2(trn_rd[19]),
        .O(p_1_in[51]));
  (* SOFT_HLUTNM = "soft_lutpair1861" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[52]_i_1 
       (.I0(trn_rd_prev[52]),
        .I1(data_prev),
        .I2(trn_rd[20]),
        .O(p_1_in[52]));
  (* SOFT_HLUTNM = "soft_lutpair1868" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[53]_i_1 
       (.I0(trn_rd_prev[53]),
        .I1(data_prev),
        .I2(trn_rd[21]),
        .O(p_1_in[53]));
  (* SOFT_HLUTNM = "soft_lutpair1865" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[54]_i_1 
       (.I0(trn_rd_prev[54]),
        .I1(data_prev),
        .I2(trn_rd[22]),
        .O(p_1_in[54]));
  (* SOFT_HLUTNM = "soft_lutpair1865" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[55]_i_1 
       (.I0(trn_rd_prev[55]),
        .I1(data_prev),
        .I2(trn_rd[23]),
        .O(p_1_in[55]));
  (* SOFT_HLUTNM = "soft_lutpair1882" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[56]_i_1 
       (.I0(trn_rd_prev[56]),
        .I1(data_prev),
        .I2(trn_rd[24]),
        .O(p_1_in[56]));
  (* SOFT_HLUTNM = "soft_lutpair1879" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[57]_i_1 
       (.I0(trn_rd_prev[57]),
        .I1(data_prev),
        .I2(trn_rd[25]),
        .O(p_1_in[57]));
  (* SOFT_HLUTNM = "soft_lutpair1881" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[58]_i_1 
       (.I0(trn_rd_prev[58]),
        .I1(data_prev),
        .I2(trn_rd[26]),
        .O(p_1_in[58]));
  (* SOFT_HLUTNM = "soft_lutpair1873" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[59]_i_1 
       (.I0(trn_rd_prev[59]),
        .I1(data_prev),
        .I2(trn_rd[27]),
        .O(p_1_in[59]));
  (* SOFT_HLUTNM = "soft_lutpair1880" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[5]_i_1 
       (.I0(trn_rd_prev[5]),
        .I1(data_prev),
        .I2(trn_rd[37]),
        .O(p_1_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair1876" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[60]_i_1 
       (.I0(trn_rd_prev[60]),
        .I1(data_prev),
        .I2(trn_rd[28]),
        .O(p_1_in[60]));
  (* SOFT_HLUTNM = "soft_lutpair1886" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[61]_i_1 
       (.I0(trn_rd_prev[61]),
        .I1(data_prev),
        .I2(trn_rd[29]),
        .O(p_1_in[61]));
  (* SOFT_HLUTNM = "soft_lutpair1877" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[62]_i_1 
       (.I0(trn_rd_prev[62]),
        .I1(data_prev),
        .I2(trn_rd[30]),
        .O(p_1_in[62]));
  LUT2 #(
    .INIT(4'hB)) 
    \m_axis_rx_tdata[63]_i_1 
       (.I0(m_axis_rx_tready),
        .I1(m_axis_rx_tvalid_reg_0),
        .O(\m_axis_rx_tdata[63]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1890" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[63]_i_2 
       (.I0(trn_rd_prev[63]),
        .I1(data_prev),
        .I2(trn_rd[31]),
        .O(p_1_in[63]));
  (* SOFT_HLUTNM = "soft_lutpair1878" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[6]_i_1 
       (.I0(trn_rd_prev[6]),
        .I1(data_prev),
        .I2(trn_rd[38]),
        .O(p_1_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair1888" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[7]_i_1 
       (.I0(trn_rd_prev[7]),
        .I1(data_prev),
        .I2(trn_rd[39]),
        .O(p_1_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair1887" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[8]_i_1 
       (.I0(trn_rd_prev[8]),
        .I1(data_prev),
        .I2(trn_rd[40]),
        .O(p_1_in[8]));
  (* SOFT_HLUTNM = "soft_lutpair1884" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata[9]_i_1 
       (.I0(trn_rd_prev[9]),
        .I1(data_prev),
        .I2(trn_rd[41]),
        .O(p_1_in[9]));
  FDRE \m_axis_rx_tdata_reg[0] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[0]),
        .Q(Q[0]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[10] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[10]),
        .Q(Q[10]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[11] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[11]),
        .Q(Q[11]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[12] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[12]),
        .Q(Q[12]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[13] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[13]),
        .Q(Q[13]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[14] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[14]),
        .Q(Q[14]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[15] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[15]),
        .Q(Q[15]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[16] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[16]),
        .Q(Q[16]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[17] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[17]),
        .Q(Q[17]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[18] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[18]),
        .Q(Q[18]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[19] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[19]),
        .Q(Q[19]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[1] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(Q[1]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[20] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[20]),
        .Q(Q[20]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[21] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[21]),
        .Q(Q[21]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[22] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[22]),
        .Q(Q[22]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[23] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[23]),
        .Q(Q[23]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[24] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[24]),
        .Q(Q[24]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[25] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[25]),
        .Q(Q[25]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[26] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[26]),
        .Q(Q[26]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[27] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[27]),
        .Q(Q[27]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[28] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[28]),
        .Q(Q[28]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[29] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[29]),
        .Q(Q[29]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[2] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(Q[2]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[30] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[30]),
        .Q(Q[30]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[31] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[31]),
        .Q(Q[31]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[32] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[32]),
        .Q(Q[32]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[33] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[33]),
        .Q(Q[33]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[34] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[34]),
        .Q(Q[34]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[35] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[35]),
        .Q(Q[35]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[36] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[36]),
        .Q(Q[36]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[37] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[37]),
        .Q(Q[37]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[38] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[38]),
        .Q(Q[38]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[39] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[39]),
        .Q(Q[39]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[3] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(Q[3]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[40] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[40]),
        .Q(Q[40]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[41] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[41]),
        .Q(Q[41]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[42] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[42]),
        .Q(Q[42]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[43] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[43]),
        .Q(Q[43]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[44] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[44]),
        .Q(Q[44]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[45] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[45]),
        .Q(Q[45]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[46] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[46]),
        .Q(Q[46]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[47] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[47]),
        .Q(Q[47]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[48] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[48]),
        .Q(Q[48]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[49] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[49]),
        .Q(Q[49]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[4] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[4]),
        .Q(Q[4]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[50] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[50]),
        .Q(Q[50]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[51] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[51]),
        .Q(Q[51]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[52] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[52]),
        .Q(Q[52]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[53] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[53]),
        .Q(Q[53]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[54] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[54]),
        .Q(Q[54]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[55] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[55]),
        .Q(Q[55]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[56] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[56]),
        .Q(Q[56]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[57] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[57]),
        .Q(Q[57]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[58] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[58]),
        .Q(Q[58]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[59] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[59]),
        .Q(Q[59]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[5] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[5]),
        .Q(Q[5]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[60] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[60]),
        .Q(Q[60]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[61] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[61]),
        .Q(Q[61]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[62] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[62]),
        .Q(Q[62]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[63] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[63]),
        .Q(Q[63]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[6] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[6]),
        .Q(Q[6]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[7] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[7]),
        .Q(Q[7]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[8] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[8]),
        .Q(Q[8]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \m_axis_rx_tdata_reg[9] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(p_1_in[9]),
        .Q(Q[9]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h000000E2)) 
    \m_axis_rx_tuser[0]_i_1 
       (.I0(trn_recrc_err),
        .I1(data_prev),
        .I2(trn_recrc_err_prev),
        .I3(\trn_rbar_hit_prev_reg[0]_0 ),
        .I4(null_mux_sel),
        .O(\m_axis_rx_tuser[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000004F40404)) 
    \m_axis_rx_tuser[14]_i_1 
       (.I0(trn_rsrc_dsc),
        .I1(trn_rsof),
        .I2(data_prev),
        .I3(trn_rsrc_dsc_prev),
        .I4(trn_rsof_prev),
        .I5(\m_axis_rx_tuser[14]_i_2_n_0 ),
        .O(\m_axis_rx_tuser[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1858" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \m_axis_rx_tuser[14]_i_2 
       (.I0(\trn_rbar_hit_prev_reg[0]_0 ),
        .I1(null_mux_sel),
        .O(\m_axis_rx_tuser[14]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1859" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \m_axis_rx_tuser[18]_i_1 
       (.I0(\trn_rbar_hit_prev_reg[0]_0 ),
        .O(\m_axis_rx_tuser[18]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \m_axis_rx_tuser[19]_i_2 
       (.I0(trn_rrem),
        .I1(data_prev),
        .I2(trn_rrem_prev),
        .I3(null_mux_sel),
        .O(pcie_block_i_0));
  LUT5 #(
    .INIT(32'h000000B8)) 
    \m_axis_rx_tuser[1]_i_1 
       (.I0(trn_rerrfwd_prev),
        .I1(data_prev),
        .I2(trn_rerrfwd),
        .I3(\trn_rbar_hit_prev_reg[0]_0 ),
        .I4(null_mux_sel),
        .O(\m_axis_rx_tuser[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hEF)) 
    \m_axis_rx_tuser[21]_i_1 
       (.I0(\trn_rbar_hit_prev_reg[0]_0 ),
        .I1(m_axis_rx_tready),
        .I2(m_axis_rx_tvalid_reg_0),
        .O(\m_axis_rx_tuser[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1859" *) 
  LUT5 #(
    .INIT(32'h000000B8)) 
    \m_axis_rx_tuser[2]_i_1 
       (.I0(trn_rbar_hit_prev[0]),
        .I1(data_prev),
        .I2(trn_rbar_hit[0]),
        .I3(\trn_rbar_hit_prev_reg[0]_0 ),
        .I4(null_mux_sel),
        .O(\m_axis_rx_tuser[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h000000E2)) 
    \m_axis_rx_tuser[3]_i_1 
       (.I0(trn_rbar_hit[1]),
        .I1(data_prev),
        .I2(trn_rbar_hit_prev[1]),
        .I3(\trn_rbar_hit_prev_reg[0]_0 ),
        .I4(null_mux_sel),
        .O(\m_axis_rx_tuser[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h000000E2)) 
    \m_axis_rx_tuser[4]_i_1 
       (.I0(trn_rbar_hit[2]),
        .I1(data_prev),
        .I2(trn_rbar_hit_prev[2]),
        .I3(\trn_rbar_hit_prev_reg[0]_0 ),
        .I4(null_mux_sel),
        .O(\m_axis_rx_tuser[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h000000B8)) 
    \m_axis_rx_tuser[5]_i_1 
       (.I0(trn_rbar_hit_prev[3]),
        .I1(data_prev),
        .I2(trn_rbar_hit[3]),
        .I3(\trn_rbar_hit_prev_reg[0]_0 ),
        .I4(null_mux_sel),
        .O(\m_axis_rx_tuser[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h000000B8)) 
    \m_axis_rx_tuser[6]_i_1 
       (.I0(trn_rbar_hit_prev[4]),
        .I1(data_prev),
        .I2(trn_rbar_hit[4]),
        .I3(\trn_rbar_hit_prev_reg[0]_0 ),
        .I4(null_mux_sel),
        .O(\m_axis_rx_tuser[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1858" *) 
  LUT5 #(
    .INIT(32'h000000E2)) 
    \m_axis_rx_tuser[7]_i_1 
       (.I0(trn_rbar_hit[5]),
        .I1(data_prev),
        .I2(trn_rbar_hit_prev[5]),
        .I3(\trn_rbar_hit_prev_reg[0]_0 ),
        .I4(null_mux_sel),
        .O(\m_axis_rx_tuser[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h000000E2)) 
    \m_axis_rx_tuser[8]_i_1 
       (.I0(trn_rbar_hit[6]),
        .I1(data_prev),
        .I2(trn_rbar_hit_prev[6]),
        .I3(\trn_rbar_hit_prev_reg[0]_0 ),
        .I4(null_mux_sel),
        .O(\m_axis_rx_tuser[8]_i_1_n_0 ));
  FDRE \m_axis_rx_tuser_reg[0] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser[0]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[0]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[14] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser[14]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[9]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[18] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser[18]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[10]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[19] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(D[0]),
        .Q(m_axis_rx_tuser[11]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[1] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser[1]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[1]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[21] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(D[1]),
        .Q(m_axis_rx_tuser[12]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[2] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser[2]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[2]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[3] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser[3]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[3]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[4] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser[4]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[4]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[5] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser[5]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[5]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[6] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser[6]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[6]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[7] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser[7]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[7]),
        .R(1'b0));
  FDRE \m_axis_rx_tuser_reg[8] 
       (.C(CLK),
        .CE(\m_axis_rx_tuser[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser[8]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[8]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFECE)) 
    m_axis_rx_tvalid_i_1
       (.I0(rsrc_rdy_filtered),
        .I1(null_mux_sel),
        .I2(data_prev),
        .I3(trn_rsrc_rdy_prev),
        .I4(reg_dsc_detect_reg_0),
        .I5(dsc_detect),
        .O(m_axis_rx_tvalid_i_1_n_0));
  FDRE m_axis_rx_tvalid_reg
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tvalid_i_1_n_0),
        .Q(m_axis_rx_tvalid_reg_0),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hABAAABAAABAABBBB)) 
    null_mux_sel_i_2
       (.I0(\trn_rbar_hit_prev_reg[0]_0 ),
        .I1(null_mux_sel),
        .I2(m_axis_rx_tready),
        .I3(m_axis_rx_tvalid_reg_0),
        .I4(dsc_detect),
        .I5(reg_dsc_detect_reg_0),
        .O(user_reset_out_reg));
  FDRE null_mux_sel_reg
       (.C(CLK),
        .CE(1'b1),
        .D(null_mux_sel_reg_0),
        .Q(null_mux_sel),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1860" *) 
  LUT3 #(
    .INIT(8'hDC)) 
    reg_dsc_detect_i_1
       (.I0(null_mux_sel),
        .I1(dsc_detect),
        .I2(reg_dsc_detect_reg_0),
        .O(reg_dsc_detect_i_1_n_0));
  FDRE reg_dsc_detect_reg
       (.C(CLK),
        .CE(1'b1),
        .D(reg_dsc_detect_i_1_n_0),
        .Q(reg_dsc_detect_reg_0),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \reg_pkt_len_counter[10]_i_3 
       (.I0(Q[30]),
        .I1(Q[9]),
        .O(\reg_pkt_len_counter[10]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \reg_pkt_len_counter[10]_i_4 
       (.I0(Q[30]),
        .I1(Q[8]),
        .O(\reg_pkt_len_counter[10]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \reg_pkt_len_counter[3]_i_3 
       (.I0(Q[29]),
        .I1(Q[15]),
        .O(packet_overhead[1]));
  LUT2 #(
    .INIT(4'h9)) 
    \reg_pkt_len_counter[3]_i_4 
       (.I0(Q[15]),
        .I1(Q[29]),
        .O(packet_overhead[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \reg_pkt_len_counter[3]_i_5 
       (.I0(Q[30]),
        .I1(Q[3]),
        .O(\reg_pkt_len_counter[3]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \reg_pkt_len_counter[3]_i_6 
       (.I0(Q[30]),
        .I1(Q[2]),
        .O(\reg_pkt_len_counter[3]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \reg_pkt_len_counter[7]_i_3 
       (.I0(Q[30]),
        .I1(Q[7]),
        .O(\reg_pkt_len_counter[7]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \reg_pkt_len_counter[7]_i_4 
       (.I0(Q[30]),
        .I1(Q[6]),
        .O(\reg_pkt_len_counter[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \reg_pkt_len_counter[7]_i_5 
       (.I0(Q[30]),
        .I1(Q[5]),
        .O(\reg_pkt_len_counter[7]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \reg_pkt_len_counter[7]_i_6 
       (.I0(Q[30]),
        .I1(Q[4]),
        .O(\reg_pkt_len_counter[7]_i_6_n_0 ));
  CARRY4 \reg_pkt_len_counter_reg[10]_i_2 
       (.CI(\reg_pkt_len_counter_reg[7]_i_2_n_0 ),
        .CO({\NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED [3],new_pkt_len[10],\NLW_reg_pkt_len_counter_reg[10]_i_2_CO_UNCONNECTED [1],\reg_pkt_len_counter_reg[10]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_reg_pkt_len_counter_reg[10]_i_2_O_UNCONNECTED [3:2],new_pkt_len[9:8]}),
        .S({1'b0,1'b1,\reg_pkt_len_counter[10]_i_3_n_0 ,\reg_pkt_len_counter[10]_i_4_n_0 }));
  CARRY4 \reg_pkt_len_counter_reg[3]_i_2 
       (.CI(1'b0),
        .CO({\reg_pkt_len_counter_reg[3]_i_2_n_0 ,\reg_pkt_len_counter_reg[3]_i_2_n_1 ,\reg_pkt_len_counter_reg[3]_i_2_n_2 ,\reg_pkt_len_counter_reg[3]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,packet_overhead}),
        .O(new_pkt_len[3:0]),
        .S({\reg_pkt_len_counter[3]_i_5_n_0 ,\reg_pkt_len_counter[3]_i_6_n_0 ,S}));
  CARRY4 \reg_pkt_len_counter_reg[7]_i_2 
       (.CI(\reg_pkt_len_counter_reg[3]_i_2_n_0 ),
        .CO({\reg_pkt_len_counter_reg[7]_i_2_n_0 ,\reg_pkt_len_counter_reg[7]_i_2_n_1 ,\reg_pkt_len_counter_reg[7]_i_2_n_2 ,\reg_pkt_len_counter_reg[7]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(new_pkt_len[7:4]),
        .S({\reg_pkt_len_counter[7]_i_3_n_0 ,\reg_pkt_len_counter[7]_i_4_n_0 ,\reg_pkt_len_counter[7]_i_5_n_0 ,\reg_pkt_len_counter[7]_i_6_n_0 }));
  LUT6 #(
    .INIT(64'h7F7F7F7070707F70)) 
    \reg_tkeep[4]_i_1 
       (.I0(trn_rdst_rdy_reg_0),
        .I1(\reg_tkeep_reg[4]_0 ),
        .I2(null_mux_sel),
        .I3(trn_rrem),
        .I4(data_prev),
        .I5(trn_rrem_prev),
        .O(reg_tkeep));
  FDSE \reg_tkeep_reg[4] 
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(reg_tkeep),
        .Q(m_axis_rx_tkeep),
        .S(\trn_rbar_hit_prev_reg[0]_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    reg_tlast_i_2
       (.I0(trn_reof),
        .I1(data_prev),
        .I2(trn_reof_prev),
        .I3(null_mux_sel),
        .O(pcie_block_i));
  FDRE reg_tlast_reg
       (.C(CLK),
        .CE(\m_axis_rx_tdata[63]_i_1_n_0 ),
        .D(reg_tlast_reg_0),
        .Q(m_axis_rx_tlast),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE trn_in_packet_reg
       (.C(CLK),
        .CE(1'b1),
        .D(trn_in_packet_reg_0),
        .Q(trn_in_packet),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rbar_hit_prev_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(trn_rbar_hit[0]),
        .Q(trn_rbar_hit_prev[0]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rbar_hit_prev_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(trn_rbar_hit[1]),
        .Q(trn_rbar_hit_prev[1]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rbar_hit_prev_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(trn_rbar_hit[2]),
        .Q(trn_rbar_hit_prev[2]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rbar_hit_prev_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(trn_rbar_hit[3]),
        .Q(trn_rbar_hit_prev[3]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rbar_hit_prev_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(trn_rbar_hit[4]),
        .Q(trn_rbar_hit_prev[4]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rbar_hit_prev_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(trn_rbar_hit[5]),
        .Q(trn_rbar_hit_prev[5]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rbar_hit_prev_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(trn_rbar_hit[6]),
        .Q(trn_rbar_hit_prev[6]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[32]),
        .Q(trn_rd_prev[0]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[10] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[42]),
        .Q(trn_rd_prev[10]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[11] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[43]),
        .Q(trn_rd_prev[11]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[12] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[44]),
        .Q(trn_rd_prev[12]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[13] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[45]),
        .Q(trn_rd_prev[13]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[14] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[46]),
        .Q(trn_rd_prev[14]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[15] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[47]),
        .Q(trn_rd_prev[15]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[16] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[48]),
        .Q(trn_rd_prev[16]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[17] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[49]),
        .Q(trn_rd_prev[17]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[18] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[50]),
        .Q(trn_rd_prev[18]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[19] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[51]),
        .Q(trn_rd_prev[19]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[33]),
        .Q(trn_rd_prev[1]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[20] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[52]),
        .Q(trn_rd_prev[20]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[21] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[53]),
        .Q(trn_rd_prev[21]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[22] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[54]),
        .Q(trn_rd_prev[22]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[23] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[55]),
        .Q(trn_rd_prev[23]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[24] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[56]),
        .Q(trn_rd_prev[24]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[25] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[57]),
        .Q(trn_rd_prev[25]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[26] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[58]),
        .Q(trn_rd_prev[26]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[27] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[59]),
        .Q(trn_rd_prev[27]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[28] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[60]),
        .Q(trn_rd_prev[28]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[29] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[61]),
        .Q(trn_rd_prev[29]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[34]),
        .Q(trn_rd_prev[2]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[30] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[62]),
        .Q(trn_rd_prev[30]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[31] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[63]),
        .Q(trn_rd_prev[31]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[32] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[0]),
        .Q(trn_rd_prev[32]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[33] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[1]),
        .Q(trn_rd_prev[33]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[34] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[2]),
        .Q(trn_rd_prev[34]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[35] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[3]),
        .Q(trn_rd_prev[35]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[36] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[4]),
        .Q(trn_rd_prev[36]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[37] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[5]),
        .Q(trn_rd_prev[37]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[38] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[6]),
        .Q(trn_rd_prev[38]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[39] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[7]),
        .Q(trn_rd_prev[39]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[35]),
        .Q(trn_rd_prev[3]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[40] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[8]),
        .Q(trn_rd_prev[40]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[41] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[9]),
        .Q(trn_rd_prev[41]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[42] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[10]),
        .Q(trn_rd_prev[42]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[43] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[11]),
        .Q(trn_rd_prev[43]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[44] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[12]),
        .Q(trn_rd_prev[44]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[45] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[13]),
        .Q(trn_rd_prev[45]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[46] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[14]),
        .Q(trn_rd_prev[46]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[47] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[15]),
        .Q(trn_rd_prev[47]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[48] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[16]),
        .Q(trn_rd_prev[48]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[49] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[17]),
        .Q(trn_rd_prev[49]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[36]),
        .Q(trn_rd_prev[4]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[50] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[18]),
        .Q(trn_rd_prev[50]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[51] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[19]),
        .Q(trn_rd_prev[51]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[52] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[20]),
        .Q(trn_rd_prev[52]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[53] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[21]),
        .Q(trn_rd_prev[53]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[54] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[22]),
        .Q(trn_rd_prev[54]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[55] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[23]),
        .Q(trn_rd_prev[55]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[56] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[24]),
        .Q(trn_rd_prev[56]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[57] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[25]),
        .Q(trn_rd_prev[57]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[58] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[26]),
        .Q(trn_rd_prev[58]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[59] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[27]),
        .Q(trn_rd_prev[59]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[37]),
        .Q(trn_rd_prev[5]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[60] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[28]),
        .Q(trn_rd_prev[60]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[61] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[29]),
        .Q(trn_rd_prev[61]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[62] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[30]),
        .Q(trn_rd_prev[62]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[63] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[31]),
        .Q(trn_rd_prev[63]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[38]),
        .Q(trn_rd_prev[6]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[39]),
        .Q(trn_rd_prev[7]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[40]),
        .Q(trn_rd_prev[8]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rd_prev_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(trn_rd[41]),
        .Q(trn_rd_prev[9]),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h3030FF3050505050)) 
    trn_rdst_rdy_i_1
       (.I0(m_axis_rx_tvalid_reg_0),
        .I1(null_mux_sel),
        .I2(trn_rdst_rdy_i_2_n_0),
        .I3(trn_rdst_rdy_reg_0),
        .I4(trn_rdst_rdy_reg_1),
        .I5(m_axis_rx_tready),
        .O(trn_rdst_rdy_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1860" *) 
  LUT2 #(
    .INIT(4'h1)) 
    trn_rdst_rdy_i_2
       (.I0(reg_dsc_detect_reg_0),
        .I1(dsc_detect),
        .O(trn_rdst_rdy_i_2_n_0));
  FDRE trn_rdst_rdy_reg
       (.C(CLK),
        .CE(1'b1),
        .D(trn_rdst_rdy_i_1_n_0),
        .Q(E),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE trn_recrc_err_prev_reg
       (.C(CLK),
        .CE(E),
        .D(trn_recrc_err),
        .Q(trn_recrc_err_prev),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE trn_reof_prev_reg
       (.C(CLK),
        .CE(E),
        .D(trn_reof),
        .Q(trn_reof_prev),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE trn_rerrfwd_prev_reg
       (.C(CLK),
        .CE(E),
        .D(trn_rerrfwd),
        .Q(trn_rerrfwd_prev),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE \trn_rrem_prev_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(trn_rrem),
        .Q(trn_rrem_prev),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE trn_rsof_prev_reg
       (.C(CLK),
        .CE(E),
        .D(trn_rsof),
        .Q(trn_rsof_prev),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE trn_rsrc_dsc_d_reg
       (.C(CLK),
        .CE(1'b1),
        .D(trn_rsrc_dsc),
        .Q(trn_rsrc_dsc_d),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE trn_rsrc_dsc_prev_reg
       (.C(CLK),
        .CE(E),
        .D(trn_rsrc_dsc_prev0),
        .Q(trn_rsrc_dsc_prev),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
  FDRE trn_rsrc_rdy_prev_reg
       (.C(CLK),
        .CE(E),
        .D(rsrc_rdy_filtered),
        .Q(trn_rsrc_rdy_prev),
        .R(\trn_rbar_hit_prev_reg[0]_0 ));
endmodule

module xdma_0_pcie2_ip_axi_basic_top
   (E,
    trn_rsrc_dsc_d,
    m_axis_rx_tvalid_reg,
    m_axis_rx_tkeep,
    m_axis_rx_tlast,
    reg_tcfg_gnt,
    tready_thrtl_reg,
    trn_teof,
    trn_tsrc_rdy,
    trn_trem,
    trn_in_packet,
    reg_dsc_detect,
    ppm_L1_thrtl,
    lnk_up_thrtl,
    m_axis_rx_tuser,
    ppm_L1_trig,
    cfg_pm_turnoff_ok_n,
    trn_tcfg_gnt,
    trn_tsof,
    Q,
    \throttle_ctl_pipeline.reg_tdata_reg[63] ,
    \throttle_ctl_pipeline.reg_tuser_reg[3] ,
    \throttle_ctl_pipeline.reg_tkeep_reg[7] ,
    CLK,
    trn_rrem,
    trn_rsrc_dsc,
    rsrc_rdy_filtered,
    trn_reof,
    trn_rsrc_dsc_prev0,
    trn_rsof,
    trn_recrc_err,
    trn_rerrfwd,
    tx_cfg_gnt,
    trn_tcfg_req,
    trn_tdst_rdy,
    tbuf_av_min_trig,
    cfg_turnoff_ok,
    s_axis_tx_tlast,
    s_axis_tx_tvalid,
    s_axis_tx_tkeep,
    trn_in_packet_reg,
    ppm_L1_thrtl_reg,
    lnk_up_thrtl_reg,
    m_axis_rx_tready,
    dsc_detect,
    out,
    tcfg_req_trig,
    tready_thrtl_i_5,
    cfg_pcie_link_state,
    s_axis_tx_tdata,
    s_axis_tx_tuser,
    trn_tbuf_av,
    trn_rd,
    trn_rbar_hit,
    cfg_to_turnoff);
  output [0:0]E;
  output trn_rsrc_dsc_d;
  output m_axis_rx_tvalid_reg;
  output [0:0]m_axis_rx_tkeep;
  output m_axis_rx_tlast;
  output reg_tcfg_gnt;
  output tready_thrtl_reg;
  output trn_teof;
  output trn_tsrc_rdy;
  output [0:0]trn_trem;
  output trn_in_packet;
  output reg_dsc_detect;
  output ppm_L1_thrtl;
  output lnk_up_thrtl;
  output [12:0]m_axis_rx_tuser;
  output ppm_L1_trig;
  output cfg_pm_turnoff_ok_n;
  output trn_tcfg_gnt;
  output trn_tsof;
  output [63:0]Q;
  output [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ;
  output [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ;
  input \throttle_ctl_pipeline.reg_tkeep_reg[7] ;
  input CLK;
  input [0:0]trn_rrem;
  input trn_rsrc_dsc;
  input rsrc_rdy_filtered;
  input trn_reof;
  input trn_rsrc_dsc_prev0;
  input trn_rsof;
  input trn_recrc_err;
  input trn_rerrfwd;
  input tx_cfg_gnt;
  input trn_tcfg_req;
  input trn_tdst_rdy;
  input tbuf_av_min_trig;
  input cfg_turnoff_ok;
  input s_axis_tx_tlast;
  input s_axis_tx_tvalid;
  input [0:0]s_axis_tx_tkeep;
  input trn_in_packet_reg;
  input ppm_L1_thrtl_reg;
  input lnk_up_thrtl_reg;
  input m_axis_rx_tready;
  input dsc_detect;
  input out;
  input tcfg_req_trig;
  input tready_thrtl_i_5;
  input [2:0]cfg_pcie_link_state;
  input [63:0]s_axis_tx_tdata;
  input [3:0]s_axis_tx_tuser;
  input [5:0]trn_tbuf_av;
  input [63:0]trn_rd;
  input [6:0]trn_rbar_hit;
  input cfg_to_turnoff;

  wire CLK;
  wire [0:0]E;
  wire [63:0]Q;
  wire [2:0]cfg_pcie_link_state;
  wire cfg_pm_turnoff_ok_n;
  wire cfg_to_turnoff;
  wire cfg_turnoff_ok;
  wire dsc_detect;
  wire lnk_up_thrtl;
  wire lnk_up_thrtl_reg;
  wire [0:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [12:0]m_axis_rx_tuser;
  wire m_axis_rx_tvalid_reg;
  wire out;
  wire ppm_L1_thrtl;
  wire ppm_L1_thrtl_reg;
  wire ppm_L1_trig;
  wire reg_dsc_detect;
  wire reg_tcfg_gnt;
  wire rsrc_rdy_filtered;
  wire [63:0]s_axis_tx_tdata;
  wire [0:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire tbuf_av_min_trig;
  wire tcfg_req_trig;
  wire [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ;
  wire \throttle_ctl_pipeline.reg_tkeep_reg[7] ;
  wire [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ;
  wire tready_thrtl_i_5;
  wire tready_thrtl_reg;
  wire trn_in_packet;
  wire trn_in_packet_reg;
  wire [6:0]trn_rbar_hit;
  wire [63:0]trn_rd;
  wire trn_recrc_err;
  wire trn_reof;
  wire trn_rerrfwd;
  wire [0:0]trn_rrem;
  wire trn_rsof;
  wire trn_rsrc_dsc;
  wire trn_rsrc_dsc_d;
  wire trn_rsrc_dsc_prev0;
  wire [5:0]trn_tbuf_av;
  wire trn_tcfg_gnt;
  wire trn_tcfg_req;
  wire trn_tdst_rdy;
  wire trn_teof;
  wire [0:0]trn_trem;
  wire trn_tsof;
  wire trn_tsrc_rdy;
  wire tx_cfg_gnt;

  xdma_0_pcie2_ip_axi_basic_rx rx_inst
       (.CLK(CLK),
        .E(E),
        .Q(Q),
        .dsc_detect(dsc_detect),
        .m_axis_rx_tkeep(m_axis_rx_tkeep),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser),
        .m_axis_rx_tvalid_reg(m_axis_rx_tvalid_reg),
        .reg_dsc_detect_reg(reg_dsc_detect),
        .rsrc_rdy_filtered(rsrc_rdy_filtered),
        .trn_in_packet(trn_in_packet),
        .trn_in_packet_reg(trn_in_packet_reg),
        .trn_rbar_hit(trn_rbar_hit),
        .\trn_rbar_hit_prev_reg[0] (\throttle_ctl_pipeline.reg_tkeep_reg[7] ),
        .trn_rd(trn_rd),
        .trn_recrc_err(trn_recrc_err),
        .trn_reof(trn_reof),
        .trn_rerrfwd(trn_rerrfwd),
        .trn_rrem(trn_rrem),
        .trn_rsof(trn_rsof),
        .trn_rsrc_dsc(trn_rsrc_dsc),
        .trn_rsrc_dsc_d(trn_rsrc_dsc_d),
        .trn_rsrc_dsc_prev0(trn_rsrc_dsc_prev0));
  xdma_0_pcie2_ip_axi_basic_tx tx_inst
       (.CLK(CLK),
        .cfg_pcie_link_state(cfg_pcie_link_state),
        .cfg_pm_turnoff_ok_n(cfg_pm_turnoff_ok_n),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .lnk_up_thrtl(lnk_up_thrtl),
        .lnk_up_thrtl_reg(lnk_up_thrtl_reg),
        .out(out),
        .ppm_L1_thrtl(ppm_L1_thrtl),
        .ppm_L1_thrtl_reg(ppm_L1_thrtl_reg),
        .ppm_L1_trig(ppm_L1_trig),
        .reg_tcfg_gnt(reg_tcfg_gnt),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep(s_axis_tx_tkeep),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .tbuf_av_min_trig(tbuf_av_min_trig),
        .tcfg_req_trig(tcfg_req_trig),
        .\throttle_ctl_pipeline.reg_tdata_reg[63] (\throttle_ctl_pipeline.reg_tdata_reg[63] ),
        .\throttle_ctl_pipeline.reg_tkeep_reg[7] (\throttle_ctl_pipeline.reg_tkeep_reg[7] ),
        .\throttle_ctl_pipeline.reg_tuser_reg[3] (\throttle_ctl_pipeline.reg_tuser_reg[3] ),
        .tready_thrtl_i_5(tready_thrtl_i_5),
        .tready_thrtl_reg(tready_thrtl_reg),
        .trn_tbuf_av(trn_tbuf_av),
        .trn_tcfg_gnt(trn_tcfg_gnt),
        .trn_tcfg_req(trn_tcfg_req),
        .trn_tdst_rdy(trn_tdst_rdy),
        .trn_teof(trn_teof),
        .trn_trem(trn_trem),
        .trn_tsof(trn_tsof),
        .trn_tsrc_rdy(trn_tsrc_rdy),
        .tx_cfg_gnt(tx_cfg_gnt));
endmodule

module xdma_0_pcie2_ip_axi_basic_tx
   (reg_tcfg_gnt,
    tready_thrtl_reg,
    trn_teof,
    trn_tsrc_rdy,
    trn_trem,
    ppm_L1_thrtl,
    lnk_up_thrtl,
    ppm_L1_trig,
    cfg_pm_turnoff_ok_n,
    trn_tcfg_gnt,
    trn_tsof,
    \throttle_ctl_pipeline.reg_tdata_reg[63] ,
    \throttle_ctl_pipeline.reg_tuser_reg[3] ,
    \throttle_ctl_pipeline.reg_tkeep_reg[7] ,
    tx_cfg_gnt,
    CLK,
    trn_tcfg_req,
    trn_tdst_rdy,
    tbuf_av_min_trig,
    cfg_turnoff_ok,
    s_axis_tx_tlast,
    s_axis_tx_tvalid,
    s_axis_tx_tkeep,
    ppm_L1_thrtl_reg,
    lnk_up_thrtl_reg,
    out,
    tcfg_req_trig,
    tready_thrtl_i_5,
    cfg_pcie_link_state,
    s_axis_tx_tdata,
    s_axis_tx_tuser,
    trn_tbuf_av,
    cfg_to_turnoff);
  output reg_tcfg_gnt;
  output tready_thrtl_reg;
  output trn_teof;
  output trn_tsrc_rdy;
  output [0:0]trn_trem;
  output ppm_L1_thrtl;
  output lnk_up_thrtl;
  output ppm_L1_trig;
  output cfg_pm_turnoff_ok_n;
  output trn_tcfg_gnt;
  output trn_tsof;
  output [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ;
  output [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ;
  input \throttle_ctl_pipeline.reg_tkeep_reg[7] ;
  input tx_cfg_gnt;
  input CLK;
  input trn_tcfg_req;
  input trn_tdst_rdy;
  input tbuf_av_min_trig;
  input cfg_turnoff_ok;
  input s_axis_tx_tlast;
  input s_axis_tx_tvalid;
  input [0:0]s_axis_tx_tkeep;
  input ppm_L1_thrtl_reg;
  input lnk_up_thrtl_reg;
  input out;
  input tcfg_req_trig;
  input tready_thrtl_i_5;
  input [2:0]cfg_pcie_link_state;
  input [63:0]s_axis_tx_tdata;
  input [3:0]s_axis_tx_tuser;
  input [5:0]trn_tbuf_av;
  input cfg_to_turnoff;

  wire CLK;
  wire axi_in_packet;
  wire [2:0]cfg_pcie_link_state;
  wire cfg_pm_turnoff_ok_n;
  wire cfg_to_turnoff;
  wire cfg_turnoff_ok;
  wire lnk_up_thrtl;
  wire lnk_up_thrtl_reg;
  wire out;
  wire ppm_L1_thrtl;
  wire ppm_L1_thrtl_reg;
  wire ppm_L1_trig;
  wire reg_disable_trn;
  wire reg_tcfg_gnt;
  wire reg_tsrc_rdy0;
  wire [63:0]s_axis_tx_tdata;
  wire [0:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire tbuf_av_min_trig;
  wire tcfg_req_trig;
  wire [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63] ;
  wire \throttle_ctl_pipeline.reg_tkeep_reg[7] ;
  wire [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3] ;
  wire \thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4 ;
  wire tready_thrtl_i_5;
  wire tready_thrtl_reg;
  wire [5:0]trn_tbuf_av;
  wire trn_tcfg_gnt;
  wire trn_tcfg_req;
  wire trn_tdst_rdy;
  wire trn_teof;
  wire [0:0]trn_trem;
  wire trn_tsof;
  wire trn_tsrc_rdy;
  wire tx_cfg_gnt;

  xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl \thrtl_ctl_enabled.tx_thrl_ctl_inst 
       (.CLK(CLK),
        .axi_in_packet(axi_in_packet),
        .cfg_pcie_link_state(cfg_pcie_link_state),
        .cfg_pm_turnoff_ok_n(cfg_pm_turnoff_ok_n),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .lnk_up_thrtl(lnk_up_thrtl),
        .lnk_up_thrtl_reg_0(lnk_up_thrtl_reg),
        .out(out),
        .ppm_L1_thrtl(ppm_L1_thrtl),
        .ppm_L1_thrtl_reg_0(ppm_L1_thrtl_reg),
        .ppm_L1_trig(ppm_L1_trig),
        .reg_disable_trn(reg_disable_trn),
        .reg_tcfg_gnt(reg_tcfg_gnt),
        .reg_tsrc_rdy0(reg_tsrc_rdy0),
        .s_axis_tx_tdata({s_axis_tx_tdata[30:29],s_axis_tx_tdata[15],s_axis_tx_tdata[0]}),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tuser(s_axis_tx_tuser[0]),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .tbuf_av_min_trig(tbuf_av_min_trig),
        .\tbuf_gap_cnt_reg[0]_0 (\throttle_ctl_pipeline.reg_tkeep_reg[7] ),
        .tcfg_req_trig(tcfg_req_trig),
        .tready_thrtl_i_5_0(tready_thrtl_i_5),
        .tready_thrtl_reg_0(tready_thrtl_reg),
        .tready_thrtl_reg_1(\thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4 ),
        .trn_tbuf_av(trn_tbuf_av),
        .trn_tcfg_gnt(trn_tcfg_gnt),
        .trn_tcfg_req(trn_tcfg_req),
        .trn_tdst_rdy(trn_tdst_rdy),
        .tx_cfg_gnt(tx_cfg_gnt));
  xdma_0_pcie2_ip_axi_basic_tx_pipeline tx_pipeline_inst
       (.CLK(CLK),
        .axi_in_packet(axi_in_packet),
        .axi_in_packet_reg_0(\thrtl_ctl_enabled.tx_thrl_ctl_inst_n_4 ),
        .out(out),
        .reg_disable_trn(reg_disable_trn),
        .reg_tsrc_rdy0(reg_tsrc_rdy0),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep(s_axis_tx_tkeep),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .\throttle_ctl_pipeline.reg_tdata_reg[63]_0 (\throttle_ctl_pipeline.reg_tdata_reg[63] ),
        .\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 (\throttle_ctl_pipeline.reg_tkeep_reg[7] ),
        .\throttle_ctl_pipeline.reg_tuser_reg[3]_0 (\throttle_ctl_pipeline.reg_tuser_reg[3] ),
        .\thrtl_ctl_trn_flush.reg_disable_trn_reg_0 (tready_thrtl_reg),
        .trn_tdst_rdy(trn_tdst_rdy),
        .trn_teof(trn_teof),
        .trn_trem(trn_trem),
        .trn_tsof(trn_tsof),
        .trn_tsrc_rdy(trn_tsrc_rdy));
endmodule

module xdma_0_pcie2_ip_axi_basic_tx_pipeline
   (trn_teof,
    trn_tsrc_rdy,
    trn_trem,
    axi_in_packet,
    reg_disable_trn,
    trn_tsof,
    \throttle_ctl_pipeline.reg_tdata_reg[63]_0 ,
    \throttle_ctl_pipeline.reg_tuser_reg[3]_0 ,
    \throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ,
    s_axis_tx_tlast,
    CLK,
    reg_tsrc_rdy0,
    s_axis_tx_tvalid,
    s_axis_tx_tkeep,
    axi_in_packet_reg_0,
    out,
    \thrtl_ctl_trn_flush.reg_disable_trn_reg_0 ,
    trn_tdst_rdy,
    s_axis_tx_tdata,
    s_axis_tx_tuser);
  output trn_teof;
  output trn_tsrc_rdy;
  output [0:0]trn_trem;
  output axi_in_packet;
  output reg_disable_trn;
  output trn_tsof;
  output [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63]_0 ;
  output [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3]_0 ;
  input \throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ;
  input s_axis_tx_tlast;
  input CLK;
  input reg_tsrc_rdy0;
  input s_axis_tx_tvalid;
  input [0:0]s_axis_tx_tkeep;
  input axi_in_packet_reg_0;
  input out;
  input \thrtl_ctl_trn_flush.reg_disable_trn_reg_0 ;
  input trn_tdst_rdy;
  input [63:0]s_axis_tx_tdata;
  input [3:0]s_axis_tx_tuser;

  wire CLK;
  wire axi_in_packet;
  wire axi_in_packet_reg_0;
  wire out;
  wire reg_disable_trn;
  wire reg_tsrc_rdy0;
  wire reg_tvalid;
  wire [63:0]s_axis_tx_tdata;
  wire [0:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire [63:0]\throttle_ctl_pipeline.reg_tdata_reg[63]_0 ;
  wire \throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ;
  wire [3:0]\throttle_ctl_pipeline.reg_tuser_reg[3]_0 ;
  wire \thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0 ;
  wire \thrtl_ctl_trn_flush.reg_disable_trn_reg_0 ;
  wire trn_in_packet;
  wire trn_in_packet_i_1__0_n_0;
  wire trn_tdst_rdy;
  wire trn_teof;
  wire [0:0]trn_trem;
  wire trn_tsof;
  wire trn_tsrc_rdy;

  FDRE axi_in_packet_reg
       (.C(CLK),
        .CE(1'b1),
        .D(axi_in_packet_reg_0),
        .Q(axi_in_packet),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    pcie_block_i_i_9
       (.I0(reg_tvalid),
        .I1(trn_in_packet),
        .O(trn_tsof));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[0]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [0]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[10]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [10]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[11]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [11]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[12]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [12]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[13]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [13]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[14]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [14]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[15]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [15]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[16]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [16]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[17]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [17]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[18]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [18]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[19]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [19]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[1]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [1]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[20]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [20]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[21]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [21]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[22]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [22]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[23]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [23]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[24]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [24]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[25]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [25]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[26]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [26]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[27]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [27]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[28]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [28]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[29]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [29]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[2]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [2]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[30]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [30]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[31]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [31]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[32]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [32]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[33]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [33]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[34]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [34]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[35]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [35]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[36]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [36]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[37]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [37]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[38]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [38]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[39]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [39]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[3]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [3]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[40]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [40]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[41]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [41]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[42]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [42]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[43]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [43]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[44]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [44]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[45]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [45]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[46]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [46]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[47]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [47]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[48]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [48]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[49]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [49]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[4]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [4]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[50]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [50]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[51]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [51]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[52]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [52]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[53]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [53]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[54]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [54]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[55]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [55]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[56]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [56]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[57]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [57]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[58]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [58]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[59]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [59]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[5]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [5]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[60]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [60]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[61]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [61]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[62]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [62]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[63]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [63]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[6]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [6]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[7]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [7]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[8]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [8]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tdata_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tdata[9]),
        .Q(\throttle_ctl_pipeline.reg_tdata_reg[63]_0 [9]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tkeep_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tkeep),
        .Q(trn_trem),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tlast_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tlast),
        .Q(trn_teof),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tsrc_rdy_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(reg_tsrc_rdy0),
        .Q(trn_tsrc_rdy),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tuser_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tuser[0]),
        .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [0]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tuser_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tuser[1]),
        .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [1]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tuser_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tuser[2]),
        .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [2]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tuser_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tuser[3]),
        .Q(\throttle_ctl_pipeline.reg_tuser_reg[3]_0 [3]),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  FDRE \throttle_ctl_pipeline.reg_tvalid_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(s_axis_tx_tvalid),
        .Q(reg_tvalid),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  LUT6 #(
    .INIT(64'h0FFFFFFF04444444)) 
    \thrtl_ctl_trn_flush.reg_disable_trn_i_1 
       (.I0(out),
        .I1(axi_in_packet),
        .I2(\thrtl_ctl_trn_flush.reg_disable_trn_reg_0 ),
        .I3(s_axis_tx_tvalid),
        .I4(s_axis_tx_tlast),
        .I5(reg_disable_trn),
        .O(\thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0 ));
  FDRE \thrtl_ctl_trn_flush.reg_disable_trn_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\thrtl_ctl_trn_flush.reg_disable_trn_i_1_n_0 ),
        .Q(reg_disable_trn),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
  LUT6 #(
    .INIT(64'h0000F088F000F000)) 
    trn_in_packet_i_1__0
       (.I0(trn_tdst_rdy),
        .I1(reg_tvalid),
        .I2(out),
        .I3(trn_in_packet),
        .I4(trn_teof),
        .I5(trn_tsrc_rdy),
        .O(trn_in_packet_i_1__0_n_0));
  FDRE trn_in_packet_reg
       (.C(CLK),
        .CE(1'b1),
        .D(trn_in_packet_i_1__0_n_0),
        .Q(trn_in_packet),
        .R(\throttle_ctl_pipeline.reg_tkeep_reg[7]_0 ));
endmodule

module xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl
   (reg_tcfg_gnt,
    tready_thrtl_reg_0,
    ppm_L1_thrtl,
    lnk_up_thrtl,
    tready_thrtl_reg_1,
    ppm_L1_trig,
    cfg_pm_turnoff_ok_n,
    trn_tcfg_gnt,
    reg_tsrc_rdy0,
    \tbuf_gap_cnt_reg[0]_0 ,
    tx_cfg_gnt,
    CLK,
    trn_tcfg_req,
    trn_tdst_rdy,
    tbuf_av_min_trig,
    cfg_turnoff_ok,
    ppm_L1_thrtl_reg_0,
    lnk_up_thrtl_reg_0,
    s_axis_tx_tlast,
    s_axis_tx_tvalid,
    axi_in_packet,
    out,
    tcfg_req_trig,
    tready_thrtl_i_5_0,
    cfg_pcie_link_state,
    s_axis_tx_tdata,
    s_axis_tx_tuser,
    reg_disable_trn,
    trn_tbuf_av,
    cfg_to_turnoff);
  output reg_tcfg_gnt;
  output tready_thrtl_reg_0;
  output ppm_L1_thrtl;
  output lnk_up_thrtl;
  output tready_thrtl_reg_1;
  output ppm_L1_trig;
  output cfg_pm_turnoff_ok_n;
  output trn_tcfg_gnt;
  output reg_tsrc_rdy0;
  input \tbuf_gap_cnt_reg[0]_0 ;
  input tx_cfg_gnt;
  input CLK;
  input trn_tcfg_req;
  input trn_tdst_rdy;
  input tbuf_av_min_trig;
  input cfg_turnoff_ok;
  input ppm_L1_thrtl_reg_0;
  input lnk_up_thrtl_reg_0;
  input s_axis_tx_tlast;
  input s_axis_tx_tvalid;
  input axi_in_packet;
  input out;
  input tcfg_req_trig;
  input tready_thrtl_i_5_0;
  input [2:0]cfg_pcie_link_state;
  input [3:0]s_axis_tx_tdata;
  input [0:0]s_axis_tx_tuser;
  input reg_disable_trn;
  input [5:0]trn_tbuf_av;
  input cfg_to_turnoff;

  wire CLK;
  wire \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ;
  wire \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0 ;
  wire axi_in_packet;
  wire [2:0]cfg_pcie_link_state;
  wire [2:0]cfg_pcie_link_state_d;
  wire cfg_pm_turnoff_ok_n;
  wire cfg_to_turnoff;
  wire cfg_turnoff_ok;
  wire cfg_turnoff_ok_pending;
  wire cfg_turnoff_ok_pending_i_1_n_0;
  wire cur_state;
  wire cur_state_i_2_n_0;
  wire \ecrc_pause_enabled.reg_tx_ecrc_pkt ;
  wire \ecrc_pause_enabled.reg_tx_ecrc_pkt021_out ;
  wire \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0 ;
  wire lnk_up_thrtl;
  wire lnk_up_thrtl_reg_0;
  wire next_state;
  wire out;
  wire p_2_in;
  wire pcie_block_i_i_14_n_0;
  wire ppm_L1_thrtl;
  wire ppm_L1_thrtl_reg_0;
  wire ppm_L1_trig;
  wire ppm_L23_thrtl;
  wire ppm_L23_thrtl_i_1_n_0;
  wire ppm_L23_trig;
  wire reg_axi_in_pkt;
  wire reg_axi_in_pkt_i_1_n_0;
  wire reg_disable_trn;
  wire reg_tcfg_gnt;
  wire reg_tsrc_rdy0;
  wire reg_turnoff_ok;
  wire [3:0]s_axis_tx_tdata;
  wire s_axis_tx_tlast;
  wire [0:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire [5:0]tbuf_av_d;
  wire tbuf_av_gap_thrtl;
  wire tbuf_av_gap_thrtl_i_1_n_0;
  wire tbuf_av_gap_trig;
  wire tbuf_av_min_thrtl;
  wire tbuf_av_min_trig;
  wire \tbuf_gap_cnt[0]_i_1_n_0 ;
  wire \tbuf_gap_cnt_reg[0]_0 ;
  wire \tbuf_gap_cnt_reg_n_0_[0] ;
  wire tcfg_gnt_pending;
  wire tcfg_gnt_pending_i_1_n_0;
  wire [1:0]tcfg_req_cnt;
  wire \tcfg_req_cnt[0]_i_1_n_0 ;
  wire \tcfg_req_cnt[1]_i_1_n_0 ;
  wire tcfg_req_thrtl;
  wire tcfg_req_thrtl_i_1_n_0;
  wire tcfg_req_trig;
  wire tready_thrtl0;
  wire tready_thrtl_i_10_n_0;
  wire tready_thrtl_i_12_n_0;
  wire tready_thrtl_i_2_n_0;
  wire tready_thrtl_i_3_n_0;
  wire tready_thrtl_i_4_n_0;
  wire tready_thrtl_i_5_0;
  wire tready_thrtl_i_6_n_0;
  wire tready_thrtl_i_7_n_0;
  wire tready_thrtl_reg_0;
  wire tready_thrtl_reg_1;
  wire [5:0]trn_tbuf_av;
  wire trn_tcfg_gnt;
  wire trn_tcfg_req;
  wire trn_tcfg_req_d;
  wire trn_tdst_rdy;
  wire trn_tdst_rdy_d;
  wire tx_cfg_gnt;

  FDRE \L23_thrtl_ep.reg_turnoff_ok_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(cfg_turnoff_ok),
        .Q(reg_turnoff_ok),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1898" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1 
       (.I0(cfg_to_turnoff),
        .I1(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ),
        .O(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0 ));
  FDRE \L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff_i_1_n_0 ),
        .Q(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  LUT4 #(
    .INIT(16'h7F40)) 
    axi_in_packet_i_1
       (.I0(s_axis_tx_tlast),
        .I1(s_axis_tx_tvalid),
        .I2(tready_thrtl_reg_0),
        .I3(axi_in_packet),
        .O(tready_thrtl_reg_1));
  FDRE \cfg_pcie_link_state_d_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(cfg_pcie_link_state[0]),
        .Q(cfg_pcie_link_state_d[0]),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDRE \cfg_pcie_link_state_d_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(cfg_pcie_link_state[1]),
        .Q(cfg_pcie_link_state_d[1]),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDRE \cfg_pcie_link_state_d_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(cfg_pcie_link_state[2]),
        .Q(cfg_pcie_link_state_d[2]),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1895" *) 
  LUT5 #(
    .INIT(32'h75553000)) 
    cfg_turnoff_ok_pending_i_1
       (.I0(cfg_pm_turnoff_ok_n),
        .I1(ppm_L23_thrtl),
        .I2(reg_turnoff_ok),
        .I3(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ),
        .I4(cfg_turnoff_ok_pending),
        .O(cfg_turnoff_ok_pending_i_1_n_0));
  FDRE cfg_turnoff_ok_pending_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cfg_turnoff_ok_pending_i_1_n_0),
        .Q(cfg_turnoff_ok_pending),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h5455445554555555)) 
    cur_state_i_1__0
       (.I0(cur_state_i_2_n_0),
        .I1(cur_state),
        .I2(s_axis_tx_tlast),
        .I3(tready_thrtl_reg_0),
        .I4(s_axis_tx_tvalid),
        .I5(reg_axi_in_pkt),
        .O(next_state));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    cur_state_i_2
       (.I0(ppm_L1_thrtl),
        .I1(lnk_up_thrtl),
        .I2(tcfg_req_thrtl),
        .I3(ppm_L23_thrtl),
        .I4(tbuf_av_gap_thrtl),
        .I5(tbuf_av_min_thrtl),
        .O(cur_state_i_2_n_0));
  FDSE cur_state_reg
       (.C(CLK),
        .CE(1'b1),
        .D(next_state),
        .Q(cur_state),
        .S(\tbuf_gap_cnt_reg[0]_0 ));
  LUT5 #(
    .INIT(32'hBFFFAAAA)) 
    \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1 
       (.I0(\ecrc_pause_enabled.reg_tx_ecrc_pkt021_out ),
        .I1(tready_thrtl_reg_0),
        .I2(s_axis_tx_tvalid),
        .I3(s_axis_tx_tlast),
        .I4(\ecrc_pause_enabled.reg_tx_ecrc_pkt ),
        .O(\ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1894" *) 
  LUT5 #(
    .INIT(32'h00001444)) 
    \ecrc_pause_enabled.reg_tx_ecrc_pkt_i_2 
       (.I0(tready_thrtl_i_7_n_0),
        .I1(s_axis_tx_tdata[2]),
        .I2(s_axis_tx_tdata[3]),
        .I3(s_axis_tx_tdata[0]),
        .I4(s_axis_tx_tlast),
        .O(\ecrc_pause_enabled.reg_tx_ecrc_pkt021_out ));
  FDRE \ecrc_pause_enabled.reg_tx_ecrc_pkt_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\ecrc_pause_enabled.reg_tx_ecrc_pkt_i_1_n_0 ),
        .Q(\ecrc_pause_enabled.reg_tx_ecrc_pkt ),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDSE lnk_up_thrtl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(lnk_up_thrtl_reg_0),
        .Q(lnk_up_thrtl),
        .S(\tbuf_gap_cnt_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1893" *) 
  LUT5 #(
    .INIT(32'hFFFF20E0)) 
    pcie_block_i_i_14
       (.I0(reg_axi_in_pkt),
        .I1(s_axis_tx_tvalid),
        .I2(tready_thrtl_reg_0),
        .I3(s_axis_tx_tlast),
        .I4(cur_state_i_2_n_0),
        .O(pcie_block_i_i_14_n_0));
  LUT6 #(
    .INIT(64'h20202020A0AFA0A0)) 
    pcie_block_i_i_6
       (.I0(cfg_turnoff_ok_pending),
        .I1(tcfg_gnt_pending),
        .I2(cur_state),
        .I3(pcie_block_i_i_14_n_0),
        .I4(ppm_L23_thrtl),
        .I5(tcfg_req_thrtl),
        .O(cfg_pm_turnoff_ok_n));
  (* SOFT_HLUTNM = "soft_lutpair1897" *) 
  LUT4 #(
    .INIT(16'hA202)) 
    pcie_block_i_i_8
       (.I0(tcfg_req_thrtl),
        .I1(pcie_block_i_i_14_n_0),
        .I2(cur_state),
        .I3(tcfg_gnt_pending),
        .O(trn_tcfg_gnt));
  LUT6 #(
    .INIT(64'h0000010000000000)) 
    ppm_L1_thrtl_i_2
       (.I0(cfg_pcie_link_state_d[1]),
        .I1(cfg_pcie_link_state_d[2]),
        .I2(cfg_pcie_link_state_d[0]),
        .I3(cfg_pcie_link_state[0]),
        .I4(cfg_pcie_link_state[1]),
        .I5(cfg_pcie_link_state[2]),
        .O(ppm_L1_trig));
  FDRE ppm_L1_thrtl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ppm_L1_thrtl_reg_0),
        .Q(ppm_L1_thrtl),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1895" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    ppm_L23_thrtl_i_1
       (.I0(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ),
        .I1(reg_turnoff_ok),
        .I2(ppm_L23_thrtl),
        .O(ppm_L23_thrtl_i_1_n_0));
  FDRE ppm_L23_thrtl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ppm_L23_thrtl_i_1_n_0),
        .Q(ppm_L23_thrtl),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h00005F40)) 
    reg_axi_in_pkt_i_1
       (.I0(s_axis_tx_tlast),
        .I1(tready_thrtl_reg_0),
        .I2(s_axis_tx_tvalid),
        .I3(reg_axi_in_pkt),
        .I4(\tbuf_gap_cnt_reg[0]_0 ),
        .O(reg_axi_in_pkt_i_1_n_0));
  FDRE reg_axi_in_pkt_reg
       (.C(CLK),
        .CE(1'b1),
        .D(reg_axi_in_pkt_i_1_n_0),
        .Q(reg_axi_in_pkt),
        .R(1'b0));
  FDRE reg_tcfg_gnt_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tx_cfg_gnt),
        .Q(reg_tcfg_gnt),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDRE \tbuf_av_d_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(trn_tbuf_av[0]),
        .Q(tbuf_av_d[0]),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDRE \tbuf_av_d_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(trn_tbuf_av[1]),
        .Q(tbuf_av_d[1]),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDRE \tbuf_av_d_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(trn_tbuf_av[2]),
        .Q(tbuf_av_d[2]),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDRE \tbuf_av_d_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(trn_tbuf_av[3]),
        .Q(tbuf_av_d[3]),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDRE \tbuf_av_d_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(trn_tbuf_av[4]),
        .Q(tbuf_av_d[4]),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDRE \tbuf_av_d_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(trn_tbuf_av[5]),
        .Q(tbuf_av_d[5]),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  LUT3 #(
    .INIT(8'hEA)) 
    tbuf_av_gap_thrtl_i_1
       (.I0(tbuf_av_gap_trig),
        .I1(\tbuf_gap_cnt_reg_n_0_[0] ),
        .I2(tbuf_av_gap_thrtl),
        .O(tbuf_av_gap_thrtl_i_1_n_0));
  FDRE tbuf_av_gap_thrtl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tbuf_av_gap_thrtl_i_1_n_0),
        .Q(tbuf_av_gap_thrtl),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDRE tbuf_av_min_thrtl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tbuf_av_min_trig),
        .Q(tbuf_av_min_thrtl),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1897" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \tbuf_gap_cnt[0]_i_1 
       (.I0(tbuf_av_gap_thrtl),
        .I1(cur_state),
        .O(\tbuf_gap_cnt[0]_i_1_n_0 ));
  FDRE \tbuf_gap_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\tbuf_gap_cnt[0]_i_1_n_0 ),
        .Q(\tbuf_gap_cnt_reg_n_0_[0] ),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h44F44444F4F4F4F4)) 
    tcfg_gnt_pending_i_1
       (.I0(trn_tcfg_req_d),
        .I1(trn_tcfg_req),
        .I2(tcfg_gnt_pending),
        .I3(cur_state),
        .I4(pcie_block_i_i_14_n_0),
        .I5(tcfg_req_thrtl),
        .O(tcfg_gnt_pending_i_1_n_0));
  FDRE tcfg_gnt_pending_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tcfg_gnt_pending_i_1_n_0),
        .Q(tcfg_gnt_pending),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h0000000000000D00)) 
    \tcfg_req_cnt[0]_i_1 
       (.I0(trn_tcfg_req),
        .I1(trn_tcfg_req_d),
        .I2(tcfg_gnt_pending),
        .I3(tcfg_req_cnt[1]),
        .I4(tcfg_req_cnt[0]),
        .I5(\tbuf_gap_cnt_reg[0]_0 ),
        .O(\tcfg_req_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1896" *) 
  LUT5 #(
    .INIT(32'hFFFF88F8)) 
    \tcfg_req_cnt[1]_i_1 
       (.I0(tcfg_req_cnt[0]),
        .I1(tcfg_req_cnt[1]),
        .I2(trn_tcfg_req),
        .I3(trn_tcfg_req_d),
        .I4(tcfg_gnt_pending),
        .O(\tcfg_req_cnt[1]_i_1_n_0 ));
  FDRE \tcfg_req_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\tcfg_req_cnt[0]_i_1_n_0 ),
        .Q(tcfg_req_cnt[0]),
        .R(1'b0));
  FDRE \tcfg_req_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\tcfg_req_cnt[1]_i_1_n_0 ),
        .Q(tcfg_req_cnt[1]),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFF8FF88888888)) 
    tcfg_req_thrtl_i_1
       (.I0(reg_tcfg_gnt),
        .I1(trn_tcfg_req),
        .I2(trn_tdst_rdy_d),
        .I3(trn_tdst_rdy),
        .I4(p_2_in),
        .I5(tcfg_req_thrtl),
        .O(tcfg_req_thrtl_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1896" *) 
  LUT2 #(
    .INIT(4'hE)) 
    tcfg_req_thrtl_i_2
       (.I0(tcfg_req_cnt[1]),
        .I1(tcfg_req_cnt[0]),
        .O(p_2_in));
  FDRE tcfg_req_thrtl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tcfg_req_thrtl_i_1_n_0),
        .Q(tcfg_req_thrtl),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \throttle_ctl_pipeline.reg_tsrc_rdy_i_1 
       (.I0(tready_thrtl_reg_0),
        .I1(s_axis_tx_tvalid),
        .I2(out),
        .I3(reg_disable_trn),
        .O(reg_tsrc_rdy0));
  LUT6 #(
    .INIT(64'hF1F1F1F10000F100)) 
    tready_thrtl_i_1
       (.I0(\ecrc_pause_enabled.reg_tx_ecrc_pkt ),
        .I1(tready_thrtl_i_2_n_0),
        .I2(tready_thrtl_i_3_n_0),
        .I3(tready_thrtl_i_4_n_0),
        .I4(tbuf_av_gap_trig),
        .I5(tready_thrtl_i_6_n_0),
        .O(tready_thrtl0));
  LUT6 #(
    .INIT(64'h00002000AAAAAAAA)) 
    tready_thrtl_i_10
       (.I0(tready_thrtl_i_5_0),
        .I1(tbuf_av_d[4]),
        .I2(tbuf_av_d[0]),
        .I3(tbuf_av_d[1]),
        .I4(tready_thrtl_i_12_n_0),
        .I5(tready_thrtl_i_3_n_0),
        .O(tready_thrtl_i_10_n_0));
  LUT4 #(
    .INIT(16'hFFEF)) 
    tready_thrtl_i_12
       (.I0(tbuf_av_d[5]),
        .I1(tbuf_av_d[2]),
        .I2(trn_tbuf_av[1]),
        .I3(tbuf_av_d[3]),
        .O(tready_thrtl_i_12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1894" *) 
  LUT4 #(
    .INIT(16'h0078)) 
    tready_thrtl_i_2
       (.I0(s_axis_tx_tdata[0]),
        .I1(s_axis_tx_tdata[3]),
        .I2(s_axis_tx_tdata[2]),
        .I3(tready_thrtl_i_7_n_0),
        .O(tready_thrtl_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1893" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    tready_thrtl_i_3
       (.I0(s_axis_tx_tlast),
        .I1(s_axis_tx_tvalid),
        .I2(tready_thrtl_reg_0),
        .O(tready_thrtl_i_3_n_0));
  LUT6 #(
    .INIT(64'h0000000000040000)) 
    tready_thrtl_i_4
       (.I0(ppm_L23_trig),
        .I1(out),
        .I2(tcfg_req_trig),
        .I3(ppm_L1_trig),
        .I4(cur_state_i_2_n_0),
        .I5(tbuf_av_min_trig),
        .O(tready_thrtl_i_4_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00100000)) 
    tready_thrtl_i_5
       (.I0(tcfg_req_cnt[0]),
        .I1(tcfg_req_cnt[1]),
        .I2(trn_tdst_rdy),
        .I3(trn_tdst_rdy_d),
        .I4(tcfg_req_thrtl),
        .I5(tready_thrtl_i_10_n_0),
        .O(tbuf_av_gap_trig));
  LUT5 #(
    .INIT(32'h000020E0)) 
    tready_thrtl_i_6
       (.I0(reg_axi_in_pkt),
        .I1(s_axis_tx_tvalid),
        .I2(tready_thrtl_reg_0),
        .I3(s_axis_tx_tlast),
        .I4(cur_state),
        .O(tready_thrtl_i_6_n_0));
  LUT5 #(
    .INIT(32'hFFFFDFFF)) 
    tready_thrtl_i_7
       (.I0(s_axis_tx_tuser),
        .I1(s_axis_tx_tdata[1]),
        .I2(s_axis_tx_tvalid),
        .I3(tready_thrtl_reg_0),
        .I4(reg_axi_in_pkt),
        .O(tready_thrtl_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1898" *) 
  LUT2 #(
    .INIT(4'h8)) 
    tready_thrtl_i_8
       (.I0(reg_turnoff_ok),
        .I1(\L23_thrtl_ep.x7_L23_thrtl_ep.reg_to_turnoff ),
        .O(ppm_L23_trig));
  FDRE tready_thrtl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tready_thrtl0),
        .Q(tready_thrtl_reg_0),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDRE trn_tcfg_req_d_reg
       (.C(CLK),
        .CE(1'b1),
        .D(trn_tcfg_req),
        .Q(trn_tcfg_req_d),
        .R(\tbuf_gap_cnt_reg[0]_0 ));
  FDSE trn_tdst_rdy_d_reg
       (.C(CLK),
        .CE(1'b1),
        .D(trn_tdst_rdy),
        .Q(trn_tdst_rdy_d),
        .S(\tbuf_gap_cnt_reg[0]_0 ));
endmodule

module xdma_0_pcie2_ip_core_top
   (pl_phy_lnk_up,
    user_reset_out,
    m_axis_rx_tvalid,
    s_axis_tx_tready,
    int_userclk1_out,
    cfg_command,
    cfg_interrupt_msienable,
    cfg_to_turnoff,
    cfg_dcommand,
    cfg_interrupt_mmenable,
    cfg_mgmt_do,
    fc_nph,
    pci_exp_txn,
    pci_exp_txp,
    user_lnk_up,
    m_axis_rx_tdata,
    m_axis_rx_tkeep,
    m_axis_rx_tlast,
    m_axis_rx_tuser,
    cfg_bus_number,
    cfg_device_number,
    cfg_function_number,
    cfg_mgmt_rd_wr_done,
    cfg_interrupt_rdy,
    m_axis_rx_tready,
    s_axis_tx_tlast,
    s_axis_tx_tvalid,
    pl_directed_link_auton,
    pl_directed_link_speed,
    pl_upstream_prefer_deemph,
    rx_np_ok,
    rx_np_req,
    cfg_err_aer_headerlog,
    cfg_pm_force_state,
    pl_directed_link_change,
    pl_directed_link_width,
    fc_sel,
    cfg_mgmt_di,
    cfg_err_tlp_cpl_header,
    cfg_aer_interrupt_msgnum,
    cfg_pciecap_interrupt_msgnum,
    cfg_dsn,
    cfg_interrupt_di,
    cfg_mgmt_dwaddr,
    sys_clk,
    pci_exp_rxn,
    pci_exp_rxp,
    int_pclk_sel_slave,
    tx_cfg_gnt,
    cfg_turnoff_ok,
    s_axis_tx_tdata,
    s_axis_tx_tuser,
    s_axis_tx_tkeep,
    cfg_mgmt_byte_en,
    sys_rst_n,
    cfg_mgmt_wr_readonly,
    cfg_mgmt_wr_en,
    cfg_mgmt_rd_en,
    cfg_interrupt,
    cfg_interrupt_assert);
  output pl_phy_lnk_up;
  output user_reset_out;
  output m_axis_rx_tvalid;
  output s_axis_tx_tready;
  output int_userclk1_out;
  output [0:0]cfg_command;
  output cfg_interrupt_msienable;
  output cfg_to_turnoff;
  output [5:0]cfg_dcommand;
  output [2:0]cfg_interrupt_mmenable;
  output [31:0]cfg_mgmt_do;
  output [7:0]fc_nph;
  output [1:0]pci_exp_txn;
  output [1:0]pci_exp_txp;
  output user_lnk_up;
  output [63:0]m_axis_rx_tdata;
  output [0:0]m_axis_rx_tkeep;
  output m_axis_rx_tlast;
  output [12:0]m_axis_rx_tuser;
  output [7:0]cfg_bus_number;
  output [4:0]cfg_device_number;
  output [2:0]cfg_function_number;
  output cfg_mgmt_rd_wr_done;
  output cfg_interrupt_rdy;
  input m_axis_rx_tready;
  input s_axis_tx_tlast;
  input s_axis_tx_tvalid;
  input pl_directed_link_auton;
  input pl_directed_link_speed;
  input pl_upstream_prefer_deemph;
  input rx_np_ok;
  input rx_np_req;
  input [127:0]cfg_err_aer_headerlog;
  input [1:0]cfg_pm_force_state;
  input [1:0]pl_directed_link_change;
  input [1:0]pl_directed_link_width;
  input [2:0]fc_sel;
  input [31:0]cfg_mgmt_di;
  input [47:0]cfg_err_tlp_cpl_header;
  input [4:0]cfg_aer_interrupt_msgnum;
  input [4:0]cfg_pciecap_interrupt_msgnum;
  input [63:0]cfg_dsn;
  input [7:0]cfg_interrupt_di;
  input [9:0]cfg_mgmt_dwaddr;
  input sys_clk;
  input [1:0]pci_exp_rxn;
  input [1:0]pci_exp_rxp;
  input [1:0]int_pclk_sel_slave;
  input tx_cfg_gnt;
  input cfg_turnoff_ok;
  input [63:0]s_axis_tx_tdata;
  input [3:0]s_axis_tx_tuser;
  input [0:0]s_axis_tx_tkeep;
  input [3:0]cfg_mgmt_byte_en;
  input sys_rst_n;
  input cfg_mgmt_wr_readonly;
  input cfg_mgmt_wr_en;
  input cfg_mgmt_rd_en;
  input cfg_interrupt;
  input cfg_interrupt_assert;

  wire \_inferred__0/store_ltssm_inferred_i_2_n_0 ;
  wire \_inferred__0/store_ltssm_inferred_i_3_n_0 ;
  wire bridge_reset_int;
  wire [4:0]cfg_aer_interrupt_msgnum;
  wire [7:0]cfg_bus_number;
  wire [0:0]cfg_command;
  wire [5:0]cfg_dcommand;
  wire [4:0]cfg_device_number;
  wire [63:0]cfg_dsn;
  wire [127:0]cfg_err_aer_headerlog;
  wire [47:0]cfg_err_tlp_cpl_header;
  wire [2:0]cfg_function_number;
  wire cfg_interrupt;
  wire cfg_interrupt_assert;
  wire [7:0]cfg_interrupt_di;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire cfg_interrupt_rdy;
  wire [3:0]cfg_mgmt_byte_en;
  wire [31:0]cfg_mgmt_di;
  wire [31:0]cfg_mgmt_do;
  wire [9:0]cfg_mgmt_dwaddr;
  wire cfg_mgmt_rd_en;
  wire cfg_mgmt_rd_wr_done;
  wire cfg_mgmt_wr_en;
  wire cfg_mgmt_wr_readonly;
  wire [4:0]cfg_pciecap_interrupt_msgnum;
  wire [1:0]cfg_pm_force_state;
  wire cfg_to_turnoff;
  wire cfg_turnoff_ok;
  wire [7:0]fc_nph;
  wire [2:0]fc_sel;
  wire gt_rx_phy_status_q;
  wire gt_rxelecidle_q;
  wire gt_top_i_n_0;
  wire gt_top_i_n_12;
  wire gt_top_i_n_13;
  wire gt_top_i_n_16;
  wire gt_top_i_n_49;
  wire gt_top_i_n_50;
  wire gt_top_i_n_51;
  wire gt_top_i_n_52;
  wire gt_top_i_n_53;
  wire gt_top_i_n_54;
  wire gt_top_i_n_8;
  wire [1:0]int_pclk_sel_slave;
  wire int_userclk1_out;
  wire \ltssm_reg1_reg[0]_srl2_n_0 ;
  wire \ltssm_reg1_reg[1]_srl2_n_0 ;
  wire \ltssm_reg1_reg[2]_srl2_n_0 ;
  wire \ltssm_reg1_reg[3]_srl2_n_0 ;
  wire \ltssm_reg1_reg[4]_srl2_n_0 ;
  wire \ltssm_reg1_reg[5]_srl2_n_0 ;
  wire [5:0]ltssm_reg2;
  wire [63:0]m_axis_rx_tdata;
  wire [0:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [12:0]m_axis_rx_tuser;
  wire m_axis_rx_tvalid;
  wire [1:0]pci_exp_rxn;
  wire [1:0]pci_exp_rxp;
  wire [1:0]pci_exp_txn;
  wire [1:0]pci_exp_txp;
  wire pcie_block_i_i_10_n_0;
  wire pcie_block_i_i_11_n_0;
  wire pcie_block_i_i_12_n_0;
  wire pcie_block_i_i_13_n_0;
  wire pcie_top_i_n_13;
  wire pcie_top_i_n_199;
  wire pcie_top_i_n_200;
  wire pcie_top_i_n_201;
  wire pcie_top_i_n_202;
  wire pcie_top_i_n_203;
  wire pcie_top_i_n_204;
  wire phy_rdy_n;
  wire pipe_rx0_chanisaligned_gt;
  wire [1:0]pipe_rx0_char_is_k_gt;
  wire [15:0]pipe_rx0_data_gt;
  wire pipe_rx0_polarity_gt;
  wire pipe_rx0_valid_gt;
  wire pipe_rx1_chanisaligned_gt;
  wire [1:0]pipe_rx1_char_is_k_gt;
  wire [15:0]pipe_rx1_data_gt;
  wire pipe_rx1_polarity_gt;
  wire pipe_rx1_valid_gt;
  wire [1:0]pipe_tx0_char_is_k_gt;
  wire pipe_tx0_compliance_gt;
  wire [15:0]pipe_tx0_data_gt;
  wire pipe_tx0_elec_idle_gt;
  wire [1:0]pipe_tx0_powerdown_gt;
  wire [1:0]pipe_tx1_char_is_k_gt;
  wire pipe_tx1_compliance_gt;
  wire [15:0]pipe_tx1_data_gt;
  wire pipe_tx1_elec_idle_gt;
  wire [1:0]pipe_tx1_powerdown_gt;
  wire pipe_tx_deemph_gt;
  wire [2:0]pipe_tx_margin_gt;
  wire pipe_tx_rate_gt;
  wire pipe_tx_rcvr_det_gt;
  wire pl_directed_link_auton;
  wire [1:0]pl_directed_link_change;
  wire pl_directed_link_speed;
  wire [1:0]pl_directed_link_width;
  wire pl_phy_lnk_up;
  wire pl_phy_lnk_up_sync;
  wire pl_phy_lnk_up_wire;
  wire pl_received_hot_rst_q_reg_n_0;
  wire pl_received_hot_rst_sync;
  wire pl_received_hot_rst_wire;
  wire pl_upstream_prefer_deemph;
  wire rx_np_ok;
  wire rx_np_req;
  wire [63:0]s_axis_tx_tdata;
  wire [0:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tready;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  (* DONT_TOUCH *) wire store_ltssm;
  wire sys_clk;
  wire sys_or_hot_rst;
  wire sys_rst_n;
  wire trn_lnk_up;
  wire tx_cfg_gnt;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire user_lnk_up_int;
  (* async_reg = "true" *) wire user_lnk_up_mux;
  wire user_reset_out;

  assign user_lnk_up = user_lnk_up_int;
  LUT2 #(
    .INIT(4'hE)) 
    \_inferred__0/store_ltssm_inferred_i_1 
       (.I0(\_inferred__0/store_ltssm_inferred_i_2_n_0 ),
        .I1(\_inferred__0/store_ltssm_inferred_i_3_n_0 ),
        .O(store_ltssm));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \_inferred__0/store_ltssm_inferred_i_2 
       (.I0(ltssm_reg2[0]),
        .I1(pcie_top_i_n_204),
        .I2(pcie_top_i_n_202),
        .I3(ltssm_reg2[2]),
        .I4(pcie_top_i_n_203),
        .I5(ltssm_reg2[1]),
        .O(\_inferred__0/store_ltssm_inferred_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \_inferred__0/store_ltssm_inferred_i_3 
       (.I0(ltssm_reg2[3]),
        .I1(pcie_top_i_n_201),
        .I2(pcie_top_i_n_199),
        .I3(ltssm_reg2[5]),
        .I4(pcie_top_i_n_200),
        .I5(ltssm_reg2[4]),
        .O(\_inferred__0/store_ltssm_inferred_i_3_n_0 ));
  xdma_0_pcie2_ip_gt_top gt_top_i
       (.CLK(int_userclk1_out),
        .D(pipe_tx_rate_gt),
        .Q(pipe_tx0_powerdown_gt),
        .TXCHARDISPMODE(pipe_tx0_compliance_gt),
        .gt_rx_phy_status_q(gt_rx_phy_status_q),
        .gt_rx_phy_status_q_reg(gt_top_i_n_12),
        .\gt_rx_status_q_reg[2] ({gt_top_i_n_49,gt_top_i_n_50,gt_top_i_n_51}),
        .\gt_rx_status_q_reg[2]_0 ({gt_top_i_n_52,gt_top_i_n_53,gt_top_i_n_54}),
        .\gt_rxcharisk_q_reg[1] (pipe_rx0_char_is_k_gt),
        .\gt_rxcharisk_q_reg[1]_0 (pipe_rx1_char_is_k_gt),
        .\gt_rxdata_q_reg[15] (pipe_rx0_data_gt),
        .\gt_rxdata_q_reg[15]_0 (pipe_rx1_data_gt),
        .gt_rxelecidle_q(gt_rxelecidle_q),
        .gt_rxelecidle_q_reg(gt_top_i_n_13),
        .\gtp_channel.gtpe2_channel_i (pipe_tx_margin_gt),
        .\gtp_channel.gtpe2_channel_i_0 (pipe_tx0_data_gt),
        .\gtp_channel.gtpe2_channel_i_1 (pipe_tx0_char_is_k_gt),
        .\gtp_channel.gtpe2_channel_i_2 (pipe_tx1_powerdown_gt),
        .\gtp_channel.gtpe2_channel_i_3 (pipe_tx1_data_gt),
        .\gtp_channel.gtpe2_channel_i_4 (pipe_tx1_char_is_k_gt),
        .int_pclk_sel_slave(int_pclk_sel_slave),
        .pci_exp_rxn(pci_exp_rxn),
        .pci_exp_rxp(pci_exp_rxp),
        .pci_exp_txn(pci_exp_txn),
        .pci_exp_txp(pci_exp_txp),
        .\pclk_i1_bufgctrl.pclk_i1 (gt_top_i_n_0),
        .phy_rdy_n(phy_rdy_n),
        .phy_rdy_n_int_reg_0(gt_top_i_n_16),
        .pipe_rx0_chanisaligned_gt(pipe_rx0_chanisaligned_gt),
        .pipe_rx0_polarity_gt(pipe_rx0_polarity_gt),
        .pipe_rx0_valid_gt(pipe_rx0_valid_gt),
        .pipe_rx1_chanisaligned_gt(pipe_rx1_chanisaligned_gt),
        .pipe_rx1_polarity_gt(pipe_rx1_polarity_gt),
        .pipe_rx1_valid_gt(pipe_rx1_valid_gt),
        .pipe_tx0_elec_idle_gt(pipe_tx0_elec_idle_gt),
        .pipe_tx1_elec_idle_gt(pipe_tx1_elec_idle_gt),
        .pipe_tx_deemph_gt(pipe_tx_deemph_gt),
        .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt),
        .pl_ltssm_state({pcie_top_i_n_199,pcie_top_i_n_200,pcie_top_i_n_201,pcie_top_i_n_202,pcie_top_i_n_203,pcie_top_i_n_204}),
        .sys_clk(sys_clk),
        .sys_rst_n(sys_rst_n),
        .sys_rst_n_0(gt_top_i_n_8),
        .txcompliance_reg1_reg(pipe_tx1_compliance_gt));
  SRL16E #(
    .INIT(16'h0000)) 
    \ltssm_reg1_reg[0]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(gt_top_i_n_0),
        .D(pcie_top_i_n_204),
        .Q(\ltssm_reg1_reg[0]_srl2_n_0 ));
  SRL16E #(
    .INIT(16'h0000)) 
    \ltssm_reg1_reg[1]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(gt_top_i_n_0),
        .D(pcie_top_i_n_203),
        .Q(\ltssm_reg1_reg[1]_srl2_n_0 ));
  SRL16E #(
    .INIT(16'h0000)) 
    \ltssm_reg1_reg[2]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(gt_top_i_n_0),
        .D(pcie_top_i_n_202),
        .Q(\ltssm_reg1_reg[2]_srl2_n_0 ));
  SRL16E #(
    .INIT(16'h0000)) 
    \ltssm_reg1_reg[3]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(gt_top_i_n_0),
        .D(pcie_top_i_n_201),
        .Q(\ltssm_reg1_reg[3]_srl2_n_0 ));
  SRL16E #(
    .INIT(16'h0000)) 
    \ltssm_reg1_reg[4]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(gt_top_i_n_0),
        .D(pcie_top_i_n_200),
        .Q(\ltssm_reg1_reg[4]_srl2_n_0 ));
  SRL16E #(
    .INIT(16'h0000)) 
    \ltssm_reg1_reg[5]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(gt_top_i_n_0),
        .D(pcie_top_i_n_199),
        .Q(\ltssm_reg1_reg[5]_srl2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ltssm_reg2_reg[0] 
       (.C(gt_top_i_n_0),
        .CE(1'b1),
        .D(\ltssm_reg1_reg[0]_srl2_n_0 ),
        .Q(ltssm_reg2[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ltssm_reg2_reg[1] 
       (.C(gt_top_i_n_0),
        .CE(1'b1),
        .D(\ltssm_reg1_reg[1]_srl2_n_0 ),
        .Q(ltssm_reg2[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ltssm_reg2_reg[2] 
       (.C(gt_top_i_n_0),
        .CE(1'b1),
        .D(\ltssm_reg1_reg[2]_srl2_n_0 ),
        .Q(ltssm_reg2[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ltssm_reg2_reg[3] 
       (.C(gt_top_i_n_0),
        .CE(1'b1),
        .D(\ltssm_reg1_reg[3]_srl2_n_0 ),
        .Q(ltssm_reg2[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ltssm_reg2_reg[4] 
       (.C(gt_top_i_n_0),
        .CE(1'b1),
        .D(\ltssm_reg1_reg[4]_srl2_n_0 ),
        .Q(ltssm_reg2[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ltssm_reg2_reg[5] 
       (.C(gt_top_i_n_0),
        .CE(1'b1),
        .D(\ltssm_reg1_reg[5]_srl2_n_0 ),
        .Q(ltssm_reg2[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_10
       (.I0(cfg_mgmt_byte_en[3]),
        .O(pcie_block_i_i_10_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_11
       (.I0(cfg_mgmt_byte_en[2]),
        .O(pcie_block_i_i_11_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_12
       (.I0(cfg_mgmt_byte_en[1]),
        .O(pcie_block_i_i_12_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_13
       (.I0(cfg_mgmt_byte_en[0]),
        .O(pcie_block_i_i_13_n_0));
  xdma_0_pcie2_ip_pcie_top pcie_top_i
       (.CLK(int_userclk1_out),
        .D(pipe_tx_rate_gt),
        .Q(pipe_tx0_char_is_k_gt),
        .SR(phy_rdy_n),
        .TXCHARDISPMODE(pipe_tx0_compliance_gt),
        .bridge_reset_int(bridge_reset_int),
        .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
        .cfg_bus_number(cfg_bus_number),
        .cfg_command(cfg_command),
        .cfg_dcommand(cfg_dcommand),
        .cfg_device_number(cfg_device_number),
        .cfg_dsn(cfg_dsn),
        .cfg_err_aer_headerlog(cfg_err_aer_headerlog),
        .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
        .cfg_function_number(cfg_function_number),
        .cfg_interrupt(cfg_interrupt),
        .cfg_interrupt_assert(cfg_interrupt_assert),
        .cfg_interrupt_di(cfg_interrupt_di),
        .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
        .cfg_interrupt_msienable(cfg_interrupt_msienable),
        .cfg_interrupt_rdy(cfg_interrupt_rdy),
        .cfg_mgmt_byte_en_n({pcie_block_i_i_10_n_0,pcie_block_i_i_11_n_0,pcie_block_i_i_12_n_0,pcie_block_i_i_13_n_0}),
        .cfg_mgmt_di(cfg_mgmt_di),
        .cfg_mgmt_do(cfg_mgmt_do),
        .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
        .cfg_mgmt_rd_en(cfg_mgmt_rd_en),
        .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
        .cfg_mgmt_wr_en(cfg_mgmt_wr_en),
        .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
        .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
        .cfg_pm_force_state(cfg_pm_force_state),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .fc_nph(fc_nph),
        .fc_sel(fc_sel),
        .gt_rx_phy_status_q(gt_rx_phy_status_q),
        .gt_rxelecidle_q(gt_rxelecidle_q),
        .m_axis_rx_tdata(m_axis_rx_tdata),
        .m_axis_rx_tkeep(m_axis_rx_tkeep),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser),
        .m_axis_rx_tvalid_reg(m_axis_rx_tvalid),
        .out(user_lnk_up_int),
        .pipe_rx0_chanisaligned_gt(pipe_rx0_chanisaligned_gt),
        .pipe_rx0_polarity_gt(pipe_rx0_polarity_gt),
        .pipe_rx0_valid_gt(pipe_rx0_valid_gt),
        .pipe_rx1_chanisaligned_gt(pipe_rx1_chanisaligned_gt),
        .pipe_rx1_polarity_gt(pipe_rx1_polarity_gt),
        .pipe_rx1_valid_gt(pipe_rx1_valid_gt),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (pipe_rx1_char_is_k_gt),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (pipe_rx0_char_is_k_gt),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (pipe_rx1_data_gt),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (pipe_rx0_data_gt),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg (gt_top_i_n_13),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg (gt_top_i_n_12),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] ({gt_top_i_n_49,gt_top_i_n_50,gt_top_i_n_51}),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ({gt_top_i_n_52,gt_top_i_n_53,gt_top_i_n_54}),
        .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] (pipe_tx1_char_is_k_gt),
        .\pipe_stages_1.pipe_tx_compliance_q_reg (pipe_tx1_compliance_gt),
        .\pipe_stages_1.pipe_tx_data_q_reg[15] (pipe_tx0_data_gt),
        .\pipe_stages_1.pipe_tx_data_q_reg[15]_0 (pipe_tx1_data_gt),
        .\pipe_stages_1.pipe_tx_deemph_q_reg (gt_top_i_n_0),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2] (pipe_tx_margin_gt),
        .\pipe_stages_1.pipe_tx_powerdown_q_reg[1] (pipe_tx0_powerdown_gt),
        .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 (pipe_tx1_powerdown_gt),
        .pipe_tx0_elec_idle_gt(pipe_tx0_elec_idle_gt),
        .pipe_tx1_elec_idle_gt(pipe_tx1_elec_idle_gt),
        .pipe_tx_deemph_gt(pipe_tx_deemph_gt),
        .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt),
        .pl_directed_link_auton(pl_directed_link_auton),
        .pl_directed_link_change(pl_directed_link_change),
        .pl_directed_link_speed(pl_directed_link_speed),
        .pl_directed_link_width(pl_directed_link_width),
        .pl_ltssm_state({pcie_top_i_n_199,pcie_top_i_n_200,pcie_top_i_n_201,pcie_top_i_n_202,pcie_top_i_n_203,pcie_top_i_n_204}),
        .pl_phy_lnk_up(pl_phy_lnk_up),
        .pl_received_hot_rst(pl_received_hot_rst_wire),
        .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
        .rx_np_ok(rx_np_ok),
        .rx_np_req(rx_np_req),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep(s_axis_tx_tkeep),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .src_in(pl_phy_lnk_up_wire),
        .sys_rst_n(gt_top_i_n_16),
        .\throttle_ctl_pipeline.reg_tkeep_reg[7] (user_reset_out),
        .tready_thrtl_reg(s_axis_tx_tready),
        .trn_lnk_up(trn_lnk_up),
        .tx_cfg_gnt(tx_cfg_gnt),
        .user_reset_int_reg(pcie_top_i_n_13));
  (* DEST_SYNC_FF = "2" *) 
  (* INIT_SYNC_FF = "0" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* SRC_INPUT_REG = "0" *) 
  (* VERSION = "0" *) 
  (* XPM_CDC = "SINGLE" *) 
  (* XPM_MODULE = "TRUE" *) 
  xdma_0_xpm_cdc_single__parameterized0__2 phy_lnk_up_cdc
       (.dest_clk(int_userclk1_out),
        .dest_out(pl_phy_lnk_up_sync),
        .src_clk(1'b0),
        .src_in(pl_phy_lnk_up_wire));
  FDRE pl_phy_lnk_up_q_reg
       (.C(int_userclk1_out),
        .CE(1'b1),
        .D(pl_phy_lnk_up_sync),
        .Q(pl_phy_lnk_up),
        .R(gt_top_i_n_8));
  (* DEST_SYNC_FF = "2" *) 
  (* INIT_SYNC_FF = "0" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* SRC_INPUT_REG = "0" *) 
  (* VERSION = "0" *) 
  (* XPM_CDC = "SINGLE" *) 
  (* XPM_MODULE = "TRUE" *) 
  xdma_0_xpm_cdc_single__parameterized0 pl_received_hot_rst_cdc
       (.dest_clk(int_userclk1_out),
        .dest_out(pl_received_hot_rst_sync),
        .src_clk(1'b0),
        .src_in(pl_received_hot_rst_wire));
  FDRE pl_received_hot_rst_q_reg
       (.C(int_userclk1_out),
        .CE(1'b1),
        .D(pl_received_hot_rst_sync),
        .Q(pl_received_hot_rst_q_reg_n_0),
        .R(gt_top_i_n_8));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE user_lnk_up_int_reg
       (.C(int_userclk1_out),
        .CE(1'b1),
        .D(trn_lnk_up),
        .Q(user_lnk_up_int),
        .R(gt_top_i_n_8));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE user_lnk_up_mux_reg
       (.C(int_userclk1_out),
        .CE(1'b1),
        .D(user_lnk_up_int),
        .Q(user_lnk_up_mux),
        .R(gt_top_i_n_8));
  FDPE user_reset_int_reg
       (.C(int_userclk1_out),
        .CE(1'b1),
        .D(pcie_top_i_n_13),
        .PRE(sys_or_hot_rst),
        .Q(bridge_reset_int));
  LUT2 #(
    .INIT(4'hB)) 
    user_reset_out_i_1
       (.I0(pl_received_hot_rst_q_reg_n_0),
        .I1(sys_rst_n),
        .O(sys_or_hot_rst));
  FDPE user_reset_out_reg
       (.C(int_userclk1_out),
        .CE(1'b1),
        .D(bridge_reset_int),
        .PRE(sys_or_hot_rst),
        .Q(user_reset_out));
endmodule

module xdma_0_pcie2_ip_gt_common
   (cpllrst,
    QRST_QPLLLOCK,
    \gtp_common.gtpe2_common_i ,
    \gtp_common.gtpe2_common_i_0 ,
    QRST_DRP_DONE,
    gt_cpllpdrefclk,
    CLK,
    sys_clk,
    PLL0RESET0,
    rst_dclk_reset,
    QRST_DRP_START);
  output cpllrst;
  output [0:0]QRST_QPLLLOCK;
  output \gtp_common.gtpe2_common_i ;
  output \gtp_common.gtpe2_common_i_0 ;
  output [0:0]QRST_DRP_DONE;
  input gt_cpllpdrefclk;
  input CLK;
  input sys_clk;
  input PLL0RESET0;
  input rst_dclk_reset;
  input QRST_DRP_START;

  wire CLK;
  wire PLL0RESET0;
  wire [0:0]QRST_DRP_DONE;
  wire QRST_DRP_START;
  wire [0:0]QRST_QPLLLOCK;
  wire cpllrst;
  wire gt_cpllpdrefclk;
  wire \gtp_common.gtpe2_common_i ;
  wire \gtp_common.gtpe2_common_i_0 ;
  wire [7:0]qpll_drp_addr;
  wire [15:0]qpll_drp_di;
  wire [15:0]qpll_drp_do;
  wire qpll_drp_en;
  wire qpll_drp_rdy;
  wire qpll_drp_we;
  wire rst_dclk_reset;
  wire sys_clk;

  xdma_0_pcie2_ip_qpll_drp qpll_drp_i
       (.CLK(CLK),
        .D(qpll_drp_do),
        .Q({qpll_drp_addr[7],qpll_drp_addr[5],qpll_drp_addr[2:0]}),
        .QRST_DRP_DONE(QRST_DRP_DONE),
        .QRST_DRP_START(QRST_DRP_START),
        .QRST_QPLLLOCK(QRST_QPLLLOCK),
        .\di_reg[15]_0 (qpll_drp_di),
        .qpll_drp_en(qpll_drp_en),
        .qpll_drp_rdy(qpll_drp_rdy),
        .qpll_drp_we(qpll_drp_we),
        .rst_dclk_reset(rst_dclk_reset));
  xdma_0_pcie2_ip_qpll_wrapper qpll_wrapper_i
       (.CLK(CLK),
        .D(qpll_drp_do),
        .PLL0RESET0(PLL0RESET0),
        .Q({qpll_drp_addr[7],qpll_drp_addr[5],qpll_drp_addr[2:0]}),
        .QRST_QPLLLOCK(QRST_QPLLLOCK),
        .cpllrst(cpllrst),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .\gtp_common.gtpe2_common_i_0 (\gtp_common.gtpe2_common_i ),
        .\gtp_common.gtpe2_common_i_1 (\gtp_common.gtpe2_common_i_0 ),
        .\gtp_common.gtpe2_common_i_2 (qpll_drp_di),
        .qpll_drp_en(qpll_drp_en),
        .qpll_drp_rdy(qpll_drp_rdy),
        .qpll_drp_we(qpll_drp_we),
        .sys_clk(sys_clk));
endmodule

module xdma_0_pcie2_ip_gt_rx_valid_filter_7x
   (gt_rxvalid_q_reg_0,
    gt_rx_phy_status_q,
    gt_rxelecidle_q,
    \gt_rxdata_q_reg[15]_0 ,
    \gt_rxcharisk_q_reg[1]_0 ,
    \gt_rx_status_q_reg[2]_0 ,
    SR,
    CLK,
    gt_rx_phy_status_wire_filter,
    SYNC_RXELECIDLE,
    gt_rxvalid_q_reg_1,
    gt_rxvalid_q_reg_2,
    D,
    \gt_rxdata_q_reg[15]_1 ,
    \gt_rx_status_q_reg[2]_1 );
  output gt_rxvalid_q_reg_0;
  output gt_rx_phy_status_q;
  output gt_rxelecidle_q;
  output [15:0]\gt_rxdata_q_reg[15]_0 ;
  output [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  output [2:0]\gt_rx_status_q_reg[2]_0 ;
  input [0:0]SR;
  input CLK;
  input [0:0]gt_rx_phy_status_wire_filter;
  input SYNC_RXELECIDLE;
  input gt_rxvalid_q_reg_1;
  input gt_rxvalid_q_reg_2;
  input [1:0]D;
  input [15:0]\gt_rxdata_q_reg[15]_1 ;
  input [2:0]\gt_rx_status_q_reg[2]_1 ;

  wire CLK;
  wire [1:0]D;
  wire [0:0]SR;
  wire SYNC_RXELECIDLE;
  wire gt_rx_phy_status_q;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2]_0 ;
  wire [2:0]\gt_rx_status_q_reg[2]_1 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  wire \gt_rxcharisk_q_reg_n_0_[0] ;
  wire [15:0]\gt_rxdata_q_reg[15]_0 ;
  wire [15:0]\gt_rxdata_q_reg[15]_1 ;
  wire gt_rxelecidle_q;
  wire gt_rxvalid_q__0;
  wire gt_rxvalid_q_i_2_n_0;
  wire gt_rxvalid_q_i_4_n_0;
  wire gt_rxvalid_q_n_0;
  wire gt_rxvalid_q_reg_0;
  wire gt_rxvalid_q_reg_1;
  wire gt_rxvalid_q_reg_2;
  wire p_1_in;
  wire [4:0]p_1_in__0;
  wire \reg_state_eios_det[0]_i_2_n_0 ;
  wire \reg_state_eios_det[2]_i_2_n_0 ;
  wire \reg_state_eios_det[2]_i_3_n_0 ;
  wire \reg_state_eios_det[2]_i_4_n_0 ;
  wire \reg_state_eios_det[2]_i_5_n_0 ;
  wire \reg_state_eios_det[3]_i_2__0_n_0 ;
  wire \reg_state_eios_det[3]_i_3_n_0 ;
  wire \reg_state_eios_det[4]_i_1_n_0 ;
  wire \reg_state_eios_det[4]_i_3_n_0 ;
  wire \reg_state_eios_det[4]_i_4_n_0 ;
  wire reg_symbol_after_eios;
  wire [4:0]state_eios_det;
  wire symbol_after_eios;

  FDRE gt_rx_phy_status_q_reg
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_wire_filter),
        .Q(gt_rx_phy_status_q),
        .R(SR));
  FDRE \gt_rx_status_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2]_1 [0]),
        .Q(\gt_rx_status_q_reg[2]_0 [0]),
        .R(SR));
  FDRE \gt_rx_status_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2]_1 [1]),
        .Q(\gt_rx_status_q_reg[2]_0 [1]),
        .R(SR));
  FDRE \gt_rx_status_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2]_1 [2]),
        .Q(\gt_rx_status_q_reg[2]_0 [2]),
        .R(SR));
  FDRE \gt_rxcharisk_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
        .R(SR));
  FDRE \gt_rxcharisk_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(p_1_in),
        .R(SR));
  FDRE \gt_rxdata_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [0]),
        .Q(\gt_rxdata_q_reg[15]_0 [0]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [10]),
        .Q(\gt_rxdata_q_reg[15]_0 [10]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [11]),
        .Q(\gt_rxdata_q_reg[15]_0 [11]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [12]),
        .Q(\gt_rxdata_q_reg[15]_0 [12]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [13]),
        .Q(\gt_rxdata_q_reg[15]_0 [13]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [14]),
        .Q(\gt_rxdata_q_reg[15]_0 [14]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [15]),
        .Q(\gt_rxdata_q_reg[15]_0 [15]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [1]),
        .Q(\gt_rxdata_q_reg[15]_0 [1]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [2]),
        .Q(\gt_rxdata_q_reg[15]_0 [2]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [3]),
        .Q(\gt_rxdata_q_reg[15]_0 [3]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [4]),
        .Q(\gt_rxdata_q_reg[15]_0 [4]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [5]),
        .Q(\gt_rxdata_q_reg[15]_0 [5]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [6]),
        .Q(\gt_rxdata_q_reg[15]_0 [6]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [7]),
        .Q(\gt_rxdata_q_reg[15]_0 [7]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [8]),
        .Q(\gt_rxdata_q_reg[15]_0 [8]),
        .R(SR));
  FDRE \gt_rxdata_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [9]),
        .Q(\gt_rxdata_q_reg[15]_0 [9]),
        .R(SR));
  FDRE gt_rxelecidle_q_reg
       (.C(CLK),
        .CE(1'b1),
        .D(SYNC_RXELECIDLE),
        .Q(gt_rxelecidle_q),
        .R(SR));
  LUT5 #(
    .INIT(32'h00010116)) 
    gt_rxvalid_q
       (.I0(state_eios_det[0]),
        .I1(state_eios_det[1]),
        .I2(state_eios_det[2]),
        .I3(state_eios_det[3]),
        .I4(state_eios_det[4]),
        .O(gt_rxvalid_q_n_0));
  LUT6 #(
    .INIT(64'h000000000000FFFB)) 
    gt_rxvalid_q_i_1
       (.I0(gt_rxvalid_q_i_2_n_0),
        .I1(gt_rxvalid_q_n_0),
        .I2(state_eios_det[0]),
        .I3(\reg_state_eios_det[0]_i_2_n_0 ),
        .I4(gt_rxvalid_q_reg_1),
        .I5(gt_rxvalid_q_i_4_n_0),
        .O(gt_rxvalid_q__0));
  (* SOFT_HLUTNM = "soft_lutpair1750" *) 
  LUT2 #(
    .INIT(4'h2)) 
    gt_rxvalid_q_i_2
       (.I0(state_eios_det[1]),
        .I1(\reg_state_eios_det[4]_i_3_n_0 ),
        .O(gt_rxvalid_q_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    gt_rxvalid_q_i_4
       (.I0(gt_rxvalid_q_reg_2),
        .I1(state_eios_det[0]),
        .I2(state_eios_det[4]),
        .I3(state_eios_det[2]),
        .I4(state_eios_det[1]),
        .I5(state_eios_det[3]),
        .O(gt_rxvalid_q_i_4_n_0));
  FDRE gt_rxvalid_q_reg
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rxvalid_q__0),
        .Q(gt_rxvalid_q_reg_0),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair1751" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1 
       (.I0(gt_rxvalid_q_reg_0),
        .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\gt_rxcharisk_q_reg[1]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1751" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1 
       (.I0(p_1_in),
        .I1(gt_rxvalid_q_reg_0),
        .I2(symbol_after_eios),
        .O(\gt_rxcharisk_q_reg[1]_0 [1]));
  LUT6 #(
    .INIT(64'hFFFFFFFF8080FF80)) 
    \reg_state_eios_det[0]_i_1__0 
       (.I0(state_eios_det[0]),
        .I1(\reg_state_eios_det[2]_i_2_n_0 ),
        .I2(\reg_state_eios_det[2]_i_3_n_0 ),
        .I3(state_eios_det[1]),
        .I4(\reg_state_eios_det[4]_i_3_n_0 ),
        .I5(\reg_state_eios_det[0]_i_2_n_0 ),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1748" *) 
  LUT5 #(
    .INIT(32'hFFFF88FA)) 
    \reg_state_eios_det[0]_i_2 
       (.I0(state_eios_det[2]),
        .I1(\reg_state_eios_det[3]_i_3_n_0 ),
        .I2(state_eios_det[3]),
        .I3(\reg_state_eios_det[4]_i_3_n_0 ),
        .I4(state_eios_det[4]),
        .O(\reg_state_eios_det[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1749" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \reg_state_eios_det[1]_i_1 
       (.I0(state_eios_det[0]),
        .I1(\reg_state_eios_det[2]_i_2_n_0 ),
        .O(p_1_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1749" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \reg_state_eios_det[2]_i_1__0 
       (.I0(state_eios_det[0]),
        .I1(\reg_state_eios_det[2]_i_2_n_0 ),
        .I2(\reg_state_eios_det[2]_i_3_n_0 ),
        .O(p_1_in__0[2]));
  LUT6 #(
    .INIT(64'hEFFFFFFFFFFFFFFF)) 
    \reg_state_eios_det[2]_i_2 
       (.I0(\reg_state_eios_det[3]_i_3_n_0 ),
        .I1(\reg_state_eios_det[2]_i_4_n_0 ),
        .I2(\gt_rxdata_q_reg[15]_0 [3]),
        .I3(\gt_rxdata_q_reg[15]_0 [5]),
        .I4(\gt_rxdata_q_reg[15]_0 [2]),
        .I5(\gt_rxdata_q_reg[15]_0 [4]),
        .O(\reg_state_eios_det[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFBFFFFF)) 
    \reg_state_eios_det[2]_i_3 
       (.I0(\gt_rxdata_q_reg[15]_0 [8]),
        .I1(\gt_rxdata_q_reg[15]_0 [11]),
        .I2(\gt_rxdata_q_reg[15]_0 [10]),
        .I3(\reg_state_eios_det[2]_i_5_n_0 ),
        .I4(\gt_rxdata_q_reg[15]_0 [15]),
        .I5(\gt_rxdata_q_reg[15]_0 [14]),
        .O(\reg_state_eios_det[2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFDFF)) 
    \reg_state_eios_det[2]_i_4 
       (.I0(\gt_rxcharisk_q_reg_n_0_[0] ),
        .I1(\gt_rxdata_q_reg[15]_0 [0]),
        .I2(\gt_rxdata_q_reg[15]_0 [6]),
        .I3(\gt_rxdata_q_reg[15]_0 [7]),
        .I4(\gt_rxdata_q_reg[15]_0 [1]),
        .O(\reg_state_eios_det[2]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hFF7F)) 
    \reg_state_eios_det[2]_i_5 
       (.I0(p_1_in),
        .I1(\gt_rxdata_q_reg[15]_0 [13]),
        .I2(\gt_rxdata_q_reg[15]_0 [12]),
        .I3(\gt_rxdata_q_reg[15]_0 [9]),
        .O(\reg_state_eios_det[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \reg_state_eios_det[3]_i_1 
       (.I0(state_eios_det[2]),
        .I1(\reg_state_eios_det[3]_i_2__0_n_0 ),
        .O(p_1_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1748" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \reg_state_eios_det[3]_i_2__0 
       (.I0(\reg_state_eios_det[3]_i_3_n_0 ),
        .I1(\reg_state_eios_det[4]_i_3_n_0 ),
        .O(\reg_state_eios_det[3]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFBFFFFF)) 
    \reg_state_eios_det[3]_i_3 
       (.I0(\gt_rxdata_q_reg[15]_0 [8]),
        .I1(\gt_rxdata_q_reg[15]_0 [11]),
        .I2(\gt_rxdata_q_reg[15]_0 [10]),
        .I3(\reg_state_eios_det[2]_i_5_n_0 ),
        .I4(\gt_rxdata_q_reg[15]_0 [14]),
        .I5(\gt_rxdata_q_reg[15]_0 [15]),
        .O(\reg_state_eios_det[3]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00010116)) 
    \reg_state_eios_det[4]_i_1 
       (.I0(state_eios_det[2]),
        .I1(state_eios_det[4]),
        .I2(state_eios_det[3]),
        .I3(state_eios_det[0]),
        .I4(state_eios_det[1]),
        .O(\reg_state_eios_det[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1750" *) 
  LUT3 #(
    .INIT(8'hC8)) 
    \reg_state_eios_det[4]_i_2 
       (.I0(state_eios_det[3]),
        .I1(\reg_state_eios_det[4]_i_3_n_0 ),
        .I2(state_eios_det[1]),
        .O(p_1_in__0[4]));
  LUT6 #(
    .INIT(64'h0000000000000200)) 
    \reg_state_eios_det[4]_i_3 
       (.I0(\gt_rxcharisk_q_reg_n_0_[0] ),
        .I1(\gt_rxdata_q_reg[15]_0 [1]),
        .I2(\gt_rxdata_q_reg[15]_0 [7]),
        .I3(\gt_rxdata_q_reg[15]_0 [6]),
        .I4(\gt_rxdata_q_reg[15]_0 [0]),
        .I5(\reg_state_eios_det[4]_i_4_n_0 ),
        .O(\reg_state_eios_det[4]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \reg_state_eios_det[4]_i_4 
       (.I0(\gt_rxdata_q_reg[15]_0 [3]),
        .I1(\gt_rxdata_q_reg[15]_0 [5]),
        .I2(\gt_rxdata_q_reg[15]_0 [2]),
        .I3(\gt_rxdata_q_reg[15]_0 [4]),
        .O(\reg_state_eios_det[4]_i_4_n_0 ));
  (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) 
  FDSE \reg_state_eios_det_reg[0] 
       (.C(CLK),
        .CE(\reg_state_eios_det[4]_i_1_n_0 ),
        .D(p_1_in__0[0]),
        .Q(state_eios_det[0]),
        .S(SR));
  (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) 
  FDRE \reg_state_eios_det_reg[1] 
       (.C(CLK),
        .CE(\reg_state_eios_det[4]_i_1_n_0 ),
        .D(p_1_in__0[1]),
        .Q(state_eios_det[1]),
        .R(SR));
  (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) 
  FDRE \reg_state_eios_det_reg[2] 
       (.C(CLK),
        .CE(\reg_state_eios_det[4]_i_1_n_0 ),
        .D(p_1_in__0[2]),
        .Q(state_eios_det[2]),
        .R(SR));
  (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) 
  FDRE \reg_state_eios_det_reg[3] 
       (.C(CLK),
        .CE(\reg_state_eios_det[4]_i_1_n_0 ),
        .D(p_1_in__0[3]),
        .Q(state_eios_det[3]),
        .R(SR));
  (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) 
  FDRE \reg_state_eios_det_reg[4] 
       (.C(CLK),
        .CE(\reg_state_eios_det[4]_i_1_n_0 ),
        .D(p_1_in__0[4]),
        .Q(state_eios_det[4]),
        .R(SR));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    reg_symbol_after_eios_i_1
       (.I0(state_eios_det[2]),
        .I1(\reg_state_eios_det[3]_i_2__0_n_0 ),
        .I2(state_eios_det[3]),
        .I3(state_eios_det[4]),
        .I4(state_eios_det[0]),
        .I5(state_eios_det[1]),
        .O(reg_symbol_after_eios));
  FDRE reg_symbol_after_eios_reg
       (.C(CLK),
        .CE(1'b1),
        .D(reg_symbol_after_eios),
        .Q(symbol_after_eios),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_gt_rx_valid_filter_7x" *) 
module xdma_0_pcie2_ip_gt_rx_valid_filter_7x_30
   (gt_rxvalid_q_reg_0,
    gt_rx_phy_status_q_reg_0,
    gt_rxelecidle_q_reg_0,
    \pl_ltssm_state_q_reg[5] ,
    \gt_rxdata_q_reg[15]_0 ,
    \gt_rxcharisk_q_reg[1]_0 ,
    \gt_rx_status_q_reg[2]_0 ,
    SS,
    CLK,
    gt_rx_phy_status_wire_filter,
    SYNC_RXELECIDLE,
    gt_rxvalid_q_reg_1,
    Q,
    D,
    \gt_rxdata_q_reg[15]_1 ,
    \gt_rx_status_q_reg[2]_1 );
  output gt_rxvalid_q_reg_0;
  output gt_rx_phy_status_q_reg_0;
  output gt_rxelecidle_q_reg_0;
  output \pl_ltssm_state_q_reg[5] ;
  output [15:0]\gt_rxdata_q_reg[15]_0 ;
  output [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  output [2:0]\gt_rx_status_q_reg[2]_0 ;
  input [0:0]SS;
  input CLK;
  input [0:0]gt_rx_phy_status_wire_filter;
  input SYNC_RXELECIDLE;
  input gt_rxvalid_q_reg_1;
  input [5:0]Q;
  input [1:0]D;
  input [15:0]\gt_rxdata_q_reg[15]_1 ;
  input [2:0]\gt_rx_status_q_reg[2]_1 ;

  wire CLK;
  wire [1:0]D;
  wire [5:0]Q;
  wire [0:0]SS;
  wire SYNC_RXELECIDLE;
  wire gt_rx_phy_status_q_reg_0;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2]_0 ;
  wire [2:0]\gt_rx_status_q_reg[2]_1 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  wire \gt_rxcharisk_q_reg_n_0_[0] ;
  wire [15:0]\gt_rxdata_q_reg[15]_0 ;
  wire [15:0]\gt_rxdata_q_reg[15]_1 ;
  wire gt_rxelecidle_q_reg_0;
  wire gt_rxvalid_q__0;
  wire gt_rxvalid_q_i_2__0_n_0;
  wire gt_rxvalid_q_i_4__0_n_0;
  wire gt_rxvalid_q_n_0;
  wire gt_rxvalid_q_reg_0;
  wire gt_rxvalid_q_reg_1;
  wire p_1_in;
  wire [4:0]p_1_in__0;
  wire \pl_ltssm_state_q_reg[5] ;
  wire \reg_state_eios_det[0]_i_2__0_n_0 ;
  wire \reg_state_eios_det[1]_i_2_n_0 ;
  wire \reg_state_eios_det[1]_i_3_n_0 ;
  wire \reg_state_eios_det[2]_i_2__0_n_0 ;
  wire \reg_state_eios_det[2]_i_3__0_n_0 ;
  wire \reg_state_eios_det[3]_i_2_n_0 ;
  wire \reg_state_eios_det[3]_i_3__0_n_0 ;
  wire \reg_state_eios_det[4]_i_1__0_n_0 ;
  wire \reg_state_eios_det[4]_i_3__0_n_0 ;
  wire \reg_state_eios_det[4]_i_4__0_n_0 ;
  wire reg_symbol_after_eios;
  wire [4:0]state_eios_det;
  wire symbol_after_eios;

  FDRE gt_rx_phy_status_q_reg
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_wire_filter),
        .Q(gt_rx_phy_status_q_reg_0),
        .R(SS));
  LUT6 #(
    .INIT(64'h0100000000000000)) 
    \gt_rx_status_q[2]_i_2 
       (.I0(Q[5]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[2]),
        .I4(Q[1]),
        .I5(Q[4]),
        .O(\pl_ltssm_state_q_reg[5] ));
  FDRE \gt_rx_status_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2]_1 [0]),
        .Q(\gt_rx_status_q_reg[2]_0 [0]),
        .R(SS));
  FDRE \gt_rx_status_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2]_1 [1]),
        .Q(\gt_rx_status_q_reg[2]_0 [1]),
        .R(SS));
  FDRE \gt_rx_status_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2]_1 [2]),
        .Q(\gt_rx_status_q_reg[2]_0 [2]),
        .R(SS));
  FDRE \gt_rxcharisk_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
        .R(SS));
  FDRE \gt_rxcharisk_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(p_1_in),
        .R(SS));
  FDRE \gt_rxdata_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [0]),
        .Q(\gt_rxdata_q_reg[15]_0 [0]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [10]),
        .Q(\gt_rxdata_q_reg[15]_0 [10]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [11]),
        .Q(\gt_rxdata_q_reg[15]_0 [11]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [12]),
        .Q(\gt_rxdata_q_reg[15]_0 [12]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [13]),
        .Q(\gt_rxdata_q_reg[15]_0 [13]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [14]),
        .Q(\gt_rxdata_q_reg[15]_0 [14]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [15]),
        .Q(\gt_rxdata_q_reg[15]_0 [15]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [1]),
        .Q(\gt_rxdata_q_reg[15]_0 [1]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [2]),
        .Q(\gt_rxdata_q_reg[15]_0 [2]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [3]),
        .Q(\gt_rxdata_q_reg[15]_0 [3]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [4]),
        .Q(\gt_rxdata_q_reg[15]_0 [4]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [5]),
        .Q(\gt_rxdata_q_reg[15]_0 [5]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [6]),
        .Q(\gt_rxdata_q_reg[15]_0 [6]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [7]),
        .Q(\gt_rxdata_q_reg[15]_0 [7]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [8]),
        .Q(\gt_rxdata_q_reg[15]_0 [8]),
        .R(SS));
  FDRE \gt_rxdata_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15]_1 [9]),
        .Q(\gt_rxdata_q_reg[15]_0 [9]),
        .R(SS));
  FDRE gt_rxelecidle_q_reg
       (.C(CLK),
        .CE(1'b1),
        .D(SYNC_RXELECIDLE),
        .Q(gt_rxelecidle_q_reg_0),
        .R(SS));
  LUT5 #(
    .INIT(32'h00010116)) 
    gt_rxvalid_q
       (.I0(state_eios_det[0]),
        .I1(state_eios_det[1]),
        .I2(state_eios_det[2]),
        .I3(state_eios_det[3]),
        .I4(state_eios_det[4]),
        .O(gt_rxvalid_q_n_0));
  LUT6 #(
    .INIT(64'h000000000000FFFB)) 
    gt_rxvalid_q_i_1__0
       (.I0(gt_rxvalid_q_i_2__0_n_0),
        .I1(gt_rxvalid_q_n_0),
        .I2(state_eios_det[0]),
        .I3(\reg_state_eios_det[0]_i_2__0_n_0 ),
        .I4(gt_rxvalid_q_reg_1),
        .I5(gt_rxvalid_q_i_4__0_n_0),
        .O(gt_rxvalid_q__0));
  (* SOFT_HLUTNM = "soft_lutpair1753" *) 
  LUT2 #(
    .INIT(4'h2)) 
    gt_rxvalid_q_i_2__0
       (.I0(state_eios_det[1]),
        .I1(\reg_state_eios_det[4]_i_3__0_n_0 ),
        .O(gt_rxvalid_q_i_2__0_n_0));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    gt_rxvalid_q_i_4__0
       (.I0(\pl_ltssm_state_q_reg[5] ),
        .I1(state_eios_det[0]),
        .I2(state_eios_det[4]),
        .I3(state_eios_det[2]),
        .I4(state_eios_det[1]),
        .I5(state_eios_det[3]),
        .O(gt_rxvalid_q_i_4__0_n_0));
  FDRE gt_rxvalid_q_reg
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rxvalid_q__0),
        .Q(gt_rxvalid_q_reg_0),
        .R(SS));
  (* SOFT_HLUTNM = "soft_lutpair1754" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__0 
       (.I0(gt_rxvalid_q_reg_0),
        .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\gt_rxcharisk_q_reg[1]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1754" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__0 
       (.I0(p_1_in),
        .I1(gt_rxvalid_q_reg_0),
        .I2(symbol_after_eios),
        .O(\gt_rxcharisk_q_reg[1]_0 [1]));
  LUT6 #(
    .INIT(64'hEAAAEAAAFFFFEAAA)) 
    \reg_state_eios_det[0]_i_1 
       (.I0(\reg_state_eios_det[0]_i_2__0_n_0 ),
        .I1(\reg_state_eios_det[2]_i_2__0_n_0 ),
        .I2(\reg_state_eios_det[1]_i_2_n_0 ),
        .I3(state_eios_det[0]),
        .I4(state_eios_det[1]),
        .I5(\reg_state_eios_det[4]_i_3__0_n_0 ),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1752" *) 
  LUT5 #(
    .INIT(32'hFFFF88FA)) 
    \reg_state_eios_det[0]_i_2__0 
       (.I0(state_eios_det[2]),
        .I1(\reg_state_eios_det[3]_i_3__0_n_0 ),
        .I2(state_eios_det[3]),
        .I3(\reg_state_eios_det[4]_i_3__0_n_0 ),
        .I4(state_eios_det[4]),
        .O(\reg_state_eios_det[0]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1755" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \reg_state_eios_det[1]_i_1__0 
       (.I0(state_eios_det[0]),
        .I1(\reg_state_eios_det[1]_i_2_n_0 ),
        .O(p_1_in__0[1]));
  LUT6 #(
    .INIT(64'hEFFFFFFFFFFFFFFF)) 
    \reg_state_eios_det[1]_i_2 
       (.I0(\reg_state_eios_det[3]_i_3__0_n_0 ),
        .I1(\reg_state_eios_det[1]_i_3_n_0 ),
        .I2(\gt_rxdata_q_reg[15]_0 [3]),
        .I3(\gt_rxdata_q_reg[15]_0 [5]),
        .I4(\gt_rxdata_q_reg[15]_0 [2]),
        .I5(\gt_rxdata_q_reg[15]_0 [4]),
        .O(\reg_state_eios_det[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFDFF)) 
    \reg_state_eios_det[1]_i_3 
       (.I0(\gt_rxcharisk_q_reg_n_0_[0] ),
        .I1(\gt_rxdata_q_reg[15]_0 [0]),
        .I2(\gt_rxdata_q_reg[15]_0 [6]),
        .I3(\gt_rxdata_q_reg[15]_0 [7]),
        .I4(\gt_rxdata_q_reg[15]_0 [1]),
        .O(\reg_state_eios_det[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1755" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \reg_state_eios_det[2]_i_1 
       (.I0(state_eios_det[0]),
        .I1(\reg_state_eios_det[2]_i_2__0_n_0 ),
        .O(p_1_in__0[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFEFFFFFFF)) 
    \reg_state_eios_det[2]_i_2__0 
       (.I0(\reg_state_eios_det[2]_i_3__0_n_0 ),
        .I1(\gt_rxdata_q_reg[15]_0 [8]),
        .I2(\gt_rxdata_q_reg[15]_0 [11]),
        .I3(\gt_rxdata_q_reg[15]_0 [10]),
        .I4(\gt_rxdata_q_reg[15]_0 [15]),
        .I5(\gt_rxdata_q_reg[15]_0 [14]),
        .O(\reg_state_eios_det[2]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'hFF7F)) 
    \reg_state_eios_det[2]_i_3__0 
       (.I0(p_1_in),
        .I1(\gt_rxdata_q_reg[15]_0 [13]),
        .I2(\gt_rxdata_q_reg[15]_0 [12]),
        .I3(\gt_rxdata_q_reg[15]_0 [9]),
        .O(\reg_state_eios_det[2]_i_3__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \reg_state_eios_det[3]_i_1__0 
       (.I0(state_eios_det[2]),
        .I1(\reg_state_eios_det[3]_i_2_n_0 ),
        .O(p_1_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1752" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \reg_state_eios_det[3]_i_2 
       (.I0(\reg_state_eios_det[3]_i_3__0_n_0 ),
        .I1(\reg_state_eios_det[4]_i_3__0_n_0 ),
        .O(\reg_state_eios_det[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEFFFFFFF)) 
    \reg_state_eios_det[3]_i_3__0 
       (.I0(\reg_state_eios_det[2]_i_3__0_n_0 ),
        .I1(\gt_rxdata_q_reg[15]_0 [8]),
        .I2(\gt_rxdata_q_reg[15]_0 [11]),
        .I3(\gt_rxdata_q_reg[15]_0 [10]),
        .I4(\gt_rxdata_q_reg[15]_0 [14]),
        .I5(\gt_rxdata_q_reg[15]_0 [15]),
        .O(\reg_state_eios_det[3]_i_3__0_n_0 ));
  LUT5 #(
    .INIT(32'h00010116)) 
    \reg_state_eios_det[4]_i_1__0 
       (.I0(state_eios_det[2]),
        .I1(state_eios_det[4]),
        .I2(state_eios_det[3]),
        .I3(state_eios_det[0]),
        .I4(state_eios_det[1]),
        .O(\reg_state_eios_det[4]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1753" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \reg_state_eios_det[4]_i_2__0 
       (.I0(\reg_state_eios_det[4]_i_3__0_n_0 ),
        .I1(state_eios_det[3]),
        .I2(state_eios_det[1]),
        .O(p_1_in__0[4]));
  LUT6 #(
    .INIT(64'h0000001000000000)) 
    \reg_state_eios_det[4]_i_3__0 
       (.I0(\reg_state_eios_det[4]_i_4__0_n_0 ),
        .I1(\gt_rxdata_q_reg[15]_0 [7]),
        .I2(\gt_rxdata_q_reg[15]_0 [6]),
        .I3(\gt_rxdata_q_reg[15]_0 [1]),
        .I4(\gt_rxdata_q_reg[15]_0 [0]),
        .I5(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\reg_state_eios_det[4]_i_3__0_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \reg_state_eios_det[4]_i_4__0 
       (.I0(\gt_rxdata_q_reg[15]_0 [3]),
        .I1(\gt_rxdata_q_reg[15]_0 [5]),
        .I2(\gt_rxdata_q_reg[15]_0 [2]),
        .I3(\gt_rxdata_q_reg[15]_0 [4]),
        .O(\reg_state_eios_det[4]_i_4__0_n_0 ));
  (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) 
  FDSE \reg_state_eios_det_reg[0] 
       (.C(CLK),
        .CE(\reg_state_eios_det[4]_i_1__0_n_0 ),
        .D(p_1_in__0[0]),
        .Q(state_eios_det[0]),
        .S(SS));
  (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) 
  FDRE \reg_state_eios_det_reg[1] 
       (.C(CLK),
        .CE(\reg_state_eios_det[4]_i_1__0_n_0 ),
        .D(p_1_in__0[1]),
        .Q(state_eios_det[1]),
        .R(SS));
  (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) 
  FDRE \reg_state_eios_det_reg[2] 
       (.C(CLK),
        .CE(\reg_state_eios_det[4]_i_1__0_n_0 ),
        .D(p_1_in__0[2]),
        .Q(state_eios_det[2]),
        .R(SS));
  (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) 
  FDRE \reg_state_eios_det_reg[3] 
       (.C(CLK),
        .CE(\reg_state_eios_det[4]_i_1__0_n_0 ),
        .D(p_1_in__0[3]),
        .Q(state_eios_det[3]),
        .R(SS));
  (* FSM_ENCODED_STATES = "EIOS_DET_NO_STR0:00010,EIOS_DET_STR0:00100,EIOS_DET_STR1:01000,EIOS_DET_IDL:00001,EIOS_DET_DONE:10000" *) 
  FDRE \reg_state_eios_det_reg[4] 
       (.C(CLK),
        .CE(\reg_state_eios_det[4]_i_1__0_n_0 ),
        .D(p_1_in__0[4]),
        .Q(state_eios_det[4]),
        .R(SS));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    reg_symbol_after_eios_i_1__0
       (.I0(state_eios_det[2]),
        .I1(\reg_state_eios_det[3]_i_2_n_0 ),
        .I2(state_eios_det[3]),
        .I3(state_eios_det[4]),
        .I4(state_eios_det[0]),
        .I5(state_eios_det[1]),
        .O(reg_symbol_after_eios));
  FDRE reg_symbol_after_eios_reg
       (.C(CLK),
        .CE(1'b1),
        .D(reg_symbol_after_eios),
        .Q(symbol_after_eios),
        .R(SS));
endmodule

module xdma_0_pcie2_ip_gt_top
   (\pclk_i1_bufgctrl.pclk_i1 ,
    CLK,
    pci_exp_txn,
    pci_exp_txp,
    pipe_rx0_chanisaligned_gt,
    pipe_rx1_chanisaligned_gt,
    sys_rst_n_0,
    pipe_rx0_valid_gt,
    phy_rdy_n,
    pipe_rx1_valid_gt,
    gt_rx_phy_status_q_reg,
    gt_rxelecidle_q_reg,
    gt_rx_phy_status_q,
    gt_rxelecidle_q,
    phy_rdy_n_int_reg_0,
    \gt_rxdata_q_reg[15] ,
    \gt_rxdata_q_reg[15]_0 ,
    \gt_rx_status_q_reg[2] ,
    \gt_rx_status_q_reg[2]_0 ,
    \gt_rxcharisk_q_reg[1] ,
    \gt_rxcharisk_q_reg[1]_0 ,
    sys_clk,
    pipe_tx0_elec_idle_gt,
    TXCHARDISPMODE,
    pci_exp_rxn,
    pci_exp_rxp,
    pipe_rx0_polarity_gt,
    pipe_tx_deemph_gt,
    pipe_tx_rcvr_det_gt,
    Q,
    \gtp_channel.gtpe2_channel_i ,
    \gtp_channel.gtpe2_channel_i_0 ,
    \gtp_channel.gtpe2_channel_i_1 ,
    pipe_tx1_elec_idle_gt,
    txcompliance_reg1_reg,
    pipe_rx1_polarity_gt,
    \gtp_channel.gtpe2_channel_i_2 ,
    \gtp_channel.gtpe2_channel_i_3 ,
    \gtp_channel.gtpe2_channel_i_4 ,
    sys_rst_n,
    D,
    int_pclk_sel_slave,
    pl_ltssm_state);
  output \pclk_i1_bufgctrl.pclk_i1 ;
  output CLK;
  output [1:0]pci_exp_txn;
  output [1:0]pci_exp_txp;
  output pipe_rx0_chanisaligned_gt;
  output pipe_rx1_chanisaligned_gt;
  output sys_rst_n_0;
  output pipe_rx0_valid_gt;
  output phy_rdy_n;
  output pipe_rx1_valid_gt;
  output gt_rx_phy_status_q_reg;
  output gt_rxelecidle_q_reg;
  output gt_rx_phy_status_q;
  output gt_rxelecidle_q;
  output phy_rdy_n_int_reg_0;
  output [15:0]\gt_rxdata_q_reg[15] ;
  output [15:0]\gt_rxdata_q_reg[15]_0 ;
  output [2:0]\gt_rx_status_q_reg[2] ;
  output [2:0]\gt_rx_status_q_reg[2]_0 ;
  output [1:0]\gt_rxcharisk_q_reg[1] ;
  output [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  input sys_clk;
  input pipe_tx0_elec_idle_gt;
  input [0:0]TXCHARDISPMODE;
  input [1:0]pci_exp_rxn;
  input [1:0]pci_exp_rxp;
  input pipe_rx0_polarity_gt;
  input pipe_tx_deemph_gt;
  input pipe_tx_rcvr_det_gt;
  input [1:0]Q;
  input [2:0]\gtp_channel.gtpe2_channel_i ;
  input [15:0]\gtp_channel.gtpe2_channel_i_0 ;
  input [1:0]\gtp_channel.gtpe2_channel_i_1 ;
  input pipe_tx1_elec_idle_gt;
  input [0:0]txcompliance_reg1_reg;
  input pipe_rx1_polarity_gt;
  input [1:0]\gtp_channel.gtpe2_channel_i_2 ;
  input [15:0]\gtp_channel.gtpe2_channel_i_3 ;
  input [1:0]\gtp_channel.gtpe2_channel_i_4 ;
  input sys_rst_n;
  input [0:0]D;
  input [1:0]int_pclk_sel_slave;
  input [5:0]pl_ltssm_state;

  wire CLK;
  wire [0:0]D;
  wire [1:0]Q;
  wire [0:0]TXCHARDISPMODE;
  wire [5:0]gt_rx_data_k_wire_filter;
  wire [47:0]gt_rx_data_wire_filter;
  wire [1:0]gt_rx_elec_idle_wire_filter;
  wire gt_rx_phy_status_q;
  wire gt_rx_phy_status_q_reg;
  wire [1:0]gt_rx_phy_status_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [2:0]\gt_rx_status_q_reg[2]_0 ;
  wire \gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst_n_3 ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire [15:0]\gt_rxdata_q_reg[15]_0 ;
  wire gt_rxelecidle_q;
  wire gt_rxelecidle_q_reg;
  wire [2:0]\gtp_channel.gtpe2_channel_i ;
  wire [15:0]\gtp_channel.gtpe2_channel_i_0 ;
  wire [1:0]\gtp_channel.gtpe2_channel_i_1 ;
  wire [1:0]\gtp_channel.gtpe2_channel_i_2 ;
  wire [15:0]\gtp_channel.gtpe2_channel_i_3 ;
  wire [1:0]\gtp_channel.gtpe2_channel_i_4 ;
  wire [1:0]int_pclk_sel_slave;
  wire [1:0]pci_exp_rxn;
  wire [1:0]pci_exp_rxp;
  wire [1:0]pci_exp_txn;
  wire [1:0]pci_exp_txp;
  wire \pclk_i1_bufgctrl.pclk_i1 ;
  wire phy_rdy_n;
  wire phy_rdy_n_int_reg_0;
  wire pipe_rx0_chanisaligned_gt;
  wire pipe_rx0_polarity_gt;
  wire pipe_rx0_valid_gt;
  wire pipe_rx1_chanisaligned_gt;
  wire pipe_rx1_polarity_gt;
  wire pipe_rx1_valid_gt;
  wire pipe_tx0_elec_idle_gt;
  wire pipe_tx1_elec_idle_gt;
  wire pipe_tx_deemph_gt;
  wire pipe_tx_rcvr_det_gt;
  wire pipe_wrapper_i_n_47;
  wire pipe_wrapper_i_n_48;
  wire pipe_wrapper_i_n_49;
  wire pipe_wrapper_i_n_50;
  wire pipe_wrapper_i_n_51;
  wire pipe_wrapper_i_n_52;
  wire pipe_wrapper_i_n_53;
  wire pipe_wrapper_i_n_54;
  wire pipe_wrapper_i_n_55;
  wire pipe_wrapper_i_n_56;
  wire [5:0]pl_ltssm_state;
  wire [5:0]pl_ltssm_state_q;
  wire reg_clock_locked;
  wire sys_clk;
  wire sys_rst_n;
  wire sys_rst_n_0;
  wire [0:0]txcompliance_reg1_reg;

  xdma_0_pcie2_ip_gt_rx_valid_filter_7x \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst 
       (.CLK(\pclk_i1_bufgctrl.pclk_i1 ),
        .D(gt_rx_data_k_wire_filter[1:0]),
        .SR(phy_rdy_n),
        .SYNC_RXELECIDLE(gt_rx_elec_idle_wire_filter[0]),
        .gt_rx_phy_status_q(gt_rx_phy_status_q),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[0]),
        .\gt_rx_status_q_reg[2]_0 (\gt_rx_status_q_reg[2]_0 ),
        .\gt_rx_status_q_reg[2]_1 ({pipe_wrapper_i_n_52,pipe_wrapper_i_n_53,pipe_wrapper_i_n_54}),
        .\gt_rxcharisk_q_reg[1]_0 (\gt_rxcharisk_q_reg[1] ),
        .\gt_rxdata_q_reg[15]_0 (\gt_rxdata_q_reg[15] ),
        .\gt_rxdata_q_reg[15]_1 (gt_rx_data_wire_filter[15:0]),
        .gt_rxelecidle_q(gt_rxelecidle_q),
        .gt_rxvalid_q_reg_0(pipe_rx0_valid_gt),
        .gt_rxvalid_q_reg_1(pipe_wrapper_i_n_48),
        .gt_rxvalid_q_reg_2(\gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst_n_3 ));
  xdma_0_pcie2_ip_gt_rx_valid_filter_7x_30 \gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst 
       (.CLK(\pclk_i1_bufgctrl.pclk_i1 ),
        .D(gt_rx_data_k_wire_filter[5:4]),
        .Q(pl_ltssm_state_q),
        .SS(phy_rdy_n),
        .SYNC_RXELECIDLE(gt_rx_elec_idle_wire_filter[1]),
        .gt_rx_phy_status_q_reg_0(gt_rx_phy_status_q_reg),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[1]),
        .\gt_rx_status_q_reg[2]_0 (\gt_rx_status_q_reg[2] ),
        .\gt_rx_status_q_reg[2]_1 ({pipe_wrapper_i_n_49,pipe_wrapper_i_n_50,pipe_wrapper_i_n_51}),
        .\gt_rxcharisk_q_reg[1]_0 (\gt_rxcharisk_q_reg[1]_0 ),
        .\gt_rxdata_q_reg[15]_0 (\gt_rxdata_q_reg[15]_0 ),
        .\gt_rxdata_q_reg[15]_1 (gt_rx_data_wire_filter[47:32]),
        .gt_rxelecidle_q_reg_0(gt_rxelecidle_q_reg),
        .gt_rxvalid_q_reg_0(pipe_rx1_valid_gt),
        .gt_rxvalid_q_reg_1(pipe_wrapper_i_n_55),
        .\pl_ltssm_state_q_reg[5] (\gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst_n_3 ));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_7
       (.I0(phy_rdy_n),
        .O(phy_rdy_n_int_reg_0));
  FDRE phy_rdy_n_int_reg
       (.C(\pclk_i1_bufgctrl.pclk_i1 ),
        .CE(1'b1),
        .D(pipe_wrapper_i_n_56),
        .Q(phy_rdy_n),
        .R(1'b0));
  xdma_0_pcie2_ip_pipe_wrapper pipe_wrapper_i
       (.CLK(\pclk_i1_bufgctrl.pclk_i1 ),
        .D(D),
        .Q(Q),
        .TXCHARDISPMODE(TXCHARDISPMODE),
        .gt_rx_data_k_wire_filter({gt_rx_data_k_wire_filter[5:4],gt_rx_data_k_wire_filter[1:0]}),
        .gt_rx_data_wire_filter({gt_rx_data_wire_filter[47:32],gt_rx_data_wire_filter[15:0]}),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter),
        .\gt_rx_status_q_reg[0] (pipe_rx0_valid_gt),
        .\gt_rx_status_q_reg[0]_0 (pipe_rx1_valid_gt),
        .\gt_rx_status_q_reg[2] (\gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst_n_3 ),
        .\gtp_channel.gtpe2_channel_i (pipe_wrapper_i_n_48),
        .\gtp_channel.gtpe2_channel_i_0 ({pipe_wrapper_i_n_49,pipe_wrapper_i_n_50,pipe_wrapper_i_n_51}),
        .\gtp_channel.gtpe2_channel_i_1 ({pipe_wrapper_i_n_52,pipe_wrapper_i_n_53,pipe_wrapper_i_n_54}),
        .\gtp_channel.gtpe2_channel_i_2 (pipe_wrapper_i_n_55),
        .\gtp_channel.gtpe2_channel_i_3 (\gtp_channel.gtpe2_channel_i ),
        .\gtp_channel.gtpe2_channel_i_4 (\gtp_channel.gtpe2_channel_i_0 ),
        .\gtp_channel.gtpe2_channel_i_5 (\gtp_channel.gtpe2_channel_i_1 ),
        .\gtp_channel.gtpe2_channel_i_6 (\gtp_channel.gtpe2_channel_i_2 ),
        .\gtp_channel.gtpe2_channel_i_7 (\gtp_channel.gtpe2_channel_i_3 ),
        .\gtp_channel.gtpe2_channel_i_8 (\gtp_channel.gtpe2_channel_i_4 ),
        .int_pclk_sel_slave(int_pclk_sel_slave),
        .mmcm_i(pipe_wrapper_i_n_47),
        .pci_exp_rxn(pci_exp_rxn),
        .pci_exp_rxp(pci_exp_rxp),
        .pci_exp_txn(pci_exp_txn),
        .pci_exp_txp(pci_exp_txp),
        .pipe_rx0_chanisaligned_gt(pipe_rx0_chanisaligned_gt),
        .pipe_rx0_polarity_gt(pipe_rx0_polarity_gt),
        .pipe_rx1_chanisaligned_gt(pipe_rx1_chanisaligned_gt),
        .pipe_rx1_polarity_gt(pipe_rx1_polarity_gt),
        .pipe_tx0_elec_idle_gt(pipe_tx0_elec_idle_gt),
        .pipe_tx1_elec_idle_gt(pipe_tx1_elec_idle_gt),
        .pipe_tx_deemph_gt(pipe_tx_deemph_gt),
        .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt),
        .reg_clock_locked(reg_clock_locked),
        .rst_idle_reg2_reg(pipe_wrapper_i_n_56),
        .sys_clk(sys_clk),
        .sys_rst_n(sys_rst_n),
        .sys_rst_n_0(sys_rst_n_0),
        .txcompliance_reg1_reg(txcompliance_reg1_reg),
        .\userclk1_i1.usrclk1_i1 (CLK));
  FDCE \pl_ltssm_state_q_reg[0] 
       (.C(\pclk_i1_bufgctrl.pclk_i1 ),
        .CE(1'b1),
        .CLR(pipe_wrapper_i_n_47),
        .D(pl_ltssm_state[0]),
        .Q(pl_ltssm_state_q[0]));
  FDCE \pl_ltssm_state_q_reg[1] 
       (.C(\pclk_i1_bufgctrl.pclk_i1 ),
        .CE(1'b1),
        .CLR(pipe_wrapper_i_n_47),
        .D(pl_ltssm_state[1]),
        .Q(pl_ltssm_state_q[1]));
  FDCE \pl_ltssm_state_q_reg[2] 
       (.C(\pclk_i1_bufgctrl.pclk_i1 ),
        .CE(1'b1),
        .CLR(pipe_wrapper_i_n_47),
        .D(pl_ltssm_state[2]),
        .Q(pl_ltssm_state_q[2]));
  FDCE \pl_ltssm_state_q_reg[3] 
       (.C(\pclk_i1_bufgctrl.pclk_i1 ),
        .CE(1'b1),
        .CLR(pipe_wrapper_i_n_47),
        .D(pl_ltssm_state[3]),
        .Q(pl_ltssm_state_q[3]));
  FDCE \pl_ltssm_state_q_reg[4] 
       (.C(\pclk_i1_bufgctrl.pclk_i1 ),
        .CE(1'b1),
        .CLR(pipe_wrapper_i_n_47),
        .D(pl_ltssm_state[4]),
        .Q(pl_ltssm_state_q[4]));
  FDCE \pl_ltssm_state_q_reg[5] 
       (.C(\pclk_i1_bufgctrl.pclk_i1 ),
        .CE(1'b1),
        .CLR(pipe_wrapper_i_n_47),
        .D(pl_ltssm_state[5]),
        .Q(pl_ltssm_state_q[5]));
  FDCE reg_clock_locked_reg
       (.C(\pclk_i1_bufgctrl.pclk_i1 ),
        .CE(1'b1),
        .CLR(pipe_wrapper_i_n_47),
        .D(1'b1),
        .Q(reg_clock_locked));
endmodule

module xdma_0_pcie2_ip_gt_wrapper
   (\gtp_channel.gtpe2_channel_i_0 ,
    pci_exp_txn,
    pci_exp_txp,
    \gtp_channel.gtpe2_channel_i_1 ,
    gt_rxcdrlock_0,
    pipe_rx0_chanisaligned_gt,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXPHALIGNDONE_M,
    \gtp_channel.gtpe2_channel_i_2 ,
    gt_rxratedone_0,
    gt_rxresetdone_0,
    SYNC_RXSYNCDONE,
    gt_rxsyncout_0,
    gt_rxvalid_0,
    \gtp_channel.gtpe2_channel_i_3 ,
    \gtp_channel.gtpe2_channel_i_4 ,
    \gtp_channel.gtpe2_channel_i_5 ,
    gt_txratedone_0,
    gt_txresetdone_0,
    SYNC_TXSYNCDONE,
    gt_txsyncout_0,
    D,
    RXSTATUS,
    gt_rx_data_wire_filter,
    gt_rx_data_k_wire_filter,
    RXCHBONDO,
    SYNC_TXDLYSRESETDONE,
    SYNC_RXDLYSRESETDONE,
    \gtp_channel.gtpe2_channel_i_6 ,
    CLK,
    \gtp_channel.gtpe2_channel_i_7 ,
    \gtp_channel.gtpe2_channel_i_8 ,
    user_eyescanreset_0,
    pci_exp_rxn,
    pci_exp_rxp,
    rst_gtreset,
    \gtp_channel.gtpe2_channel_i_9 ,
    \gtp_channel.gtpe2_channel_i_10 ,
    user_resetovrd_0,
    user_rxbufreset_0,
    user_rxcdrfreqreset_0,
    user_rxcdrreset_0,
    user_rxpcsreset_0,
    user_rxpmareset_0,
    pipe_rx0_polarity_gt,
    rxsyncallin,
    rst_userrdy,
    \gtp_channel.gtpe2_channel_i_11 ,
    user_oobclk_0,
    pipe_tx_deemph_gt,
    pipe_tx_rcvr_det_gt,
    sync_txdlyen_0,
    Q,
    pipe_tx0_elec_idle_gt,
    SYNC_TXPHALIGNDONE,
    DRPDI,
    \gtp_channel.gtpe2_channel_i_12 ,
    RXRATE,
    \gtp_channel.gtpe2_channel_i_13 ,
    \gtp_channel.gtpe2_channel_i_14 ,
    TXCHARDISPMODE,
    \gtp_channel.gtpe2_channel_i_15 ,
    TXPOSTCURSOR,
    TXPRECURSOR,
    TXMAINCURSOR,
    DRPADDR,
    txdlysresetdone_reg1_reg,
    rxdlysresetdone_reg1_reg,
    \gt_rx_status_q_reg[0] ,
    \gt_rx_status_q_reg[2] );
  output \gtp_channel.gtpe2_channel_i_0 ;
  output [0:0]pci_exp_txn;
  output [0:0]pci_exp_txp;
  output [0:0]\gtp_channel.gtpe2_channel_i_1 ;
  output gt_rxcdrlock_0;
  output pipe_rx0_chanisaligned_gt;
  output [0:0]gt_rx_elec_idle_wire_filter;
  output SYNC_RXPHALIGNDONE_M;
  output [0:0]\gtp_channel.gtpe2_channel_i_2 ;
  output gt_rxratedone_0;
  output gt_rxresetdone_0;
  output SYNC_RXSYNCDONE;
  output gt_rxsyncout_0;
  output gt_rxvalid_0;
  output \gtp_channel.gtpe2_channel_i_3 ;
  output \gtp_channel.gtpe2_channel_i_4 ;
  output \gtp_channel.gtpe2_channel_i_5 ;
  output gt_txratedone_0;
  output gt_txresetdone_0;
  output SYNC_TXSYNCDONE;
  output gt_txsyncout_0;
  output [15:0]D;
  output [0:0]RXSTATUS;
  output [15:0]gt_rx_data_wire_filter;
  output [1:0]gt_rx_data_k_wire_filter;
  output [3:0]RXCHBONDO;
  output SYNC_TXDLYSRESETDONE;
  output SYNC_RXDLYSRESETDONE;
  output [2:0]\gtp_channel.gtpe2_channel_i_6 ;
  input CLK;
  input \gtp_channel.gtpe2_channel_i_7 ;
  input \gtp_channel.gtpe2_channel_i_8 ;
  input user_eyescanreset_0;
  input [0:0]pci_exp_rxn;
  input [0:0]pci_exp_rxp;
  input rst_gtreset;
  input \gtp_channel.gtpe2_channel_i_9 ;
  input \gtp_channel.gtpe2_channel_i_10 ;
  input user_resetovrd_0;
  input user_rxbufreset_0;
  input user_rxcdrfreqreset_0;
  input user_rxcdrreset_0;
  input user_rxpcsreset_0;
  input user_rxpmareset_0;
  input pipe_rx0_polarity_gt;
  input rxsyncallin;
  input rst_userrdy;
  input \gtp_channel.gtpe2_channel_i_11 ;
  input user_oobclk_0;
  input pipe_tx_deemph_gt;
  input pipe_tx_rcvr_det_gt;
  input sync_txdlyen_0;
  input [2:0]Q;
  input pipe_tx0_elec_idle_gt;
  input SYNC_TXPHALIGNDONE;
  input [15:0]DRPDI;
  input [1:0]\gtp_channel.gtpe2_channel_i_12 ;
  input [0:0]RXRATE;
  input [2:0]\gtp_channel.gtpe2_channel_i_13 ;
  input [15:0]\gtp_channel.gtpe2_channel_i_14 ;
  input [0:0]TXCHARDISPMODE;
  input [1:0]\gtp_channel.gtpe2_channel_i_15 ;
  input [4:0]TXPOSTCURSOR;
  input [4:0]TXPRECURSOR;
  input [6:0]TXMAINCURSOR;
  input [0:0]DRPADDR;
  input txdlysresetdone_reg1_reg;
  input rxdlysresetdone_reg1_reg;
  input \gt_rx_status_q_reg[0] ;
  input \gt_rx_status_q_reg[2] ;

  wire CLK;
  wire [15:0]D;
  wire [0:0]DRPADDR;
  wire [15:0]DRPDI;
  wire [2:0]Q;
  wire [3:0]RXCHBONDO;
  wire [0:0]RXRATE;
  wire [0:0]RXSTATUS;
  wire SYNC_RXDLYSRESETDONE;
  wire SYNC_RXPHALIGNDONE_M;
  wire SYNC_RXSYNCDONE;
  wire SYNC_TXDLYSRESETDONE;
  wire SYNC_TXPHALIGNDONE;
  wire SYNC_TXSYNCDONE;
  wire [0:0]TXCHARDISPMODE;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire [1:0]gt_rx_data_k_wire_filter;
  wire [15:0]gt_rx_data_wire_filter;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire \gt_rx_status_q_reg[0] ;
  wire \gt_rx_status_q_reg[2] ;
  wire gt_rxcdrlock_0;
  wire gt_rxratedone_0;
  wire gt_rxresetdone_0;
  wire gt_rxsyncout_0;
  wire gt_rxvalid_0;
  wire gt_txratedone_0;
  wire gt_txresetdone_0;
  wire gt_txsyncout_0;
  wire \gtp_channel.gtpe2_channel_i_0 ;
  wire [0:0]\gtp_channel.gtpe2_channel_i_1 ;
  wire \gtp_channel.gtpe2_channel_i_10 ;
  wire \gtp_channel.gtpe2_channel_i_11 ;
  wire [1:0]\gtp_channel.gtpe2_channel_i_12 ;
  wire [2:0]\gtp_channel.gtpe2_channel_i_13 ;
  wire [15:0]\gtp_channel.gtpe2_channel_i_14 ;
  wire [1:0]\gtp_channel.gtpe2_channel_i_15 ;
  wire [0:0]\gtp_channel.gtpe2_channel_i_2 ;
  wire \gtp_channel.gtpe2_channel_i_3 ;
  wire \gtp_channel.gtpe2_channel_i_4 ;
  wire \gtp_channel.gtpe2_channel_i_5 ;
  wire [2:0]\gtp_channel.gtpe2_channel_i_6 ;
  wire \gtp_channel.gtpe2_channel_i_7 ;
  wire \gtp_channel.gtpe2_channel_i_8 ;
  wire \gtp_channel.gtpe2_channel_i_9 ;
  wire \gtp_channel.gtpe2_channel_i_n_1 ;
  wire \gtp_channel.gtpe2_channel_i_n_103 ;
  wire \gtp_channel.gtpe2_channel_i_n_104 ;
  wire \gtp_channel.gtpe2_channel_i_n_105 ;
  wire \gtp_channel.gtpe2_channel_i_n_110 ;
  wire \gtp_channel.gtpe2_channel_i_n_111 ;
  wire \gtp_channel.gtpe2_channel_i_n_112 ;
  wire \gtp_channel.gtpe2_channel_i_n_113 ;
  wire \gtp_channel.gtpe2_channel_i_n_114 ;
  wire \gtp_channel.gtpe2_channel_i_n_115 ;
  wire \gtp_channel.gtpe2_channel_i_n_116 ;
  wire \gtp_channel.gtpe2_channel_i_n_117 ;
  wire \gtp_channel.gtpe2_channel_i_n_118 ;
  wire \gtp_channel.gtpe2_channel_i_n_119 ;
  wire \gtp_channel.gtpe2_channel_i_n_120 ;
  wire \gtp_channel.gtpe2_channel_i_n_121 ;
  wire \gtp_channel.gtpe2_channel_i_n_122 ;
  wire \gtp_channel.gtpe2_channel_i_n_123 ;
  wire \gtp_channel.gtpe2_channel_i_n_124 ;
  wire \gtp_channel.gtpe2_channel_i_n_125 ;
  wire \gtp_channel.gtpe2_channel_i_n_126 ;
  wire \gtp_channel.gtpe2_channel_i_n_127 ;
  wire \gtp_channel.gtpe2_channel_i_n_14 ;
  wire \gtp_channel.gtpe2_channel_i_n_144 ;
  wire \gtp_channel.gtpe2_channel_i_n_145 ;
  wire \gtp_channel.gtpe2_channel_i_n_146 ;
  wire \gtp_channel.gtpe2_channel_i_n_147 ;
  wire \gtp_channel.gtpe2_channel_i_n_148 ;
  wire \gtp_channel.gtpe2_channel_i_n_149 ;
  wire \gtp_channel.gtpe2_channel_i_n_156 ;
  wire \gtp_channel.gtpe2_channel_i_n_157 ;
  wire \gtp_channel.gtpe2_channel_i_n_158 ;
  wire \gtp_channel.gtpe2_channel_i_n_159 ;
  wire \gtp_channel.gtpe2_channel_i_n_160 ;
  wire \gtp_channel.gtpe2_channel_i_n_161 ;
  wire \gtp_channel.gtpe2_channel_i_n_162 ;
  wire \gtp_channel.gtpe2_channel_i_n_163 ;
  wire \gtp_channel.gtpe2_channel_i_n_17 ;
  wire \gtp_channel.gtpe2_channel_i_n_24 ;
  wire \gtp_channel.gtpe2_channel_i_n_29 ;
  wire \gtp_channel.gtpe2_channel_i_n_36 ;
  wire \gtp_channel.gtpe2_channel_i_n_48 ;
  wire \gtp_channel.gtpe2_channel_i_n_49 ;
  wire \gtp_channel.gtpe2_channel_i_n_50 ;
  wire \gtp_channel.gtpe2_channel_i_n_51 ;
  wire \gtp_channel.gtpe2_channel_i_n_52 ;
  wire \gtp_channel.gtpe2_channel_i_n_53 ;
  wire \gtp_channel.gtpe2_channel_i_n_54 ;
  wire \gtp_channel.gtpe2_channel_i_n_55 ;
  wire \gtp_channel.gtpe2_channel_i_n_56 ;
  wire \gtp_channel.gtpe2_channel_i_n_57 ;
  wire \gtp_channel.gtpe2_channel_i_n_58 ;
  wire \gtp_channel.gtpe2_channel_i_n_59 ;
  wire \gtp_channel.gtpe2_channel_i_n_60 ;
  wire \gtp_channel.gtpe2_channel_i_n_61 ;
  wire \gtp_channel.gtpe2_channel_i_n_62 ;
  wire \gtp_channel.gtpe2_channel_i_n_7 ;
  wire \gtp_channel.gtpe2_channel_i_n_8 ;
  wire [0:0]pci_exp_rxn;
  wire [0:0]pci_exp_rxp;
  wire [0:0]pci_exp_txn;
  wire [0:0]pci_exp_txp;
  wire pipe_rx0_chanisaligned_gt;
  wire pipe_rx0_polarity_gt;
  wire pipe_tx0_elec_idle_gt;
  wire pipe_tx_deemph_gt;
  wire pipe_tx_rcvr_det_gt;
  wire rst_gtreset;
  wire rst_userrdy;
  wire rxdlysresetdone_reg1_reg;
  wire rxsyncallin;
  wire sync_txdlyen_0;
  wire txdlysresetdone_reg1_reg;
  wire user_eyescanreset_0;
  wire user_oobclk_0;
  wire user_resetovrd_0;
  wire user_rxbufreset_0;
  wire user_rxcdrfreqreset_0;
  wire user_rxcdrreset_0;
  wire user_rxpcsreset_0;
  wire user_rxpmareset_0;
  wire \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT0_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT1_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXCOMINITDET_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXCOMSASDET_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXHEADERVALID_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOSINTDONE_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTARTED_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBEDONE_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBESTARTED_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_TXCOMFINISH_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_TXPMARESETDONE_UNCONNECTED ;
  wire [15:0]\NLW_gtp_channel.gtpe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
  wire [1:0]\NLW_gtp_channel.gtpe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
  wire [1:0]\NLW_gtp_channel.gtpe2_channel_i_RXDATAVALID_UNCONNECTED ;
  wire [2:0]\NLW_gtp_channel.gtpe2_channel_i_RXHEADER_UNCONNECTED ;
  wire [4:0]\NLW_gtp_channel.gtpe2_channel_i_RXPHMONITOR_UNCONNECTED ;
  wire [4:0]\NLW_gtp_channel.gtpe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
  wire [1:0]\NLW_gtp_channel.gtpe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
  wire [1:0]\NLW_gtp_channel.gtpe2_channel_i_TXBUFSTATUS_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair1762" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \gt_rx_status_q[0]_i_1__0 
       (.I0(\gtp_channel.gtpe2_channel_i_n_111 ),
        .I1(\gt_rx_status_q_reg[0] ),
        .I2(\gt_rx_status_q_reg[2] ),
        .O(\gtp_channel.gtpe2_channel_i_6 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1762" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \gt_rx_status_q[1]_i_1__0 
       (.I0(\gtp_channel.gtpe2_channel_i_n_110 ),
        .I1(\gt_rx_status_q_reg[0] ),
        .I2(\gt_rx_status_q_reg[2] ),
        .O(\gtp_channel.gtpe2_channel_i_6 [1]));
  LUT3 #(
    .INIT(8'h8A)) 
    \gt_rx_status_q[2]_i_1__0 
       (.I0(RXSTATUS),
        .I1(\gt_rx_status_q_reg[0] ),
        .I2(\gt_rx_status_q_reg[2] ),
        .O(\gtp_channel.gtpe2_channel_i_6 [2]));
  (* box_type = "PRIMITIVE" *) 
  GTPE2_CHANNEL #(
    .ACJTAG_DEBUG_MODE(1'b0),
    .ACJTAG_MODE(1'b0),
    .ACJTAG_RESET(1'b0),
    .ADAPT_CFG0(20'b00000000000000000000),
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(1),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CFOK_CFG(43'b1001001000000000000000001000000111010000000),
    .CFOK_CFG2(7'b0100000),
    .CFOK_CFG3(7'b0100000),
    .CFOK_CFG4(1'b0),
    .CFOK_CFG5(2'b00),
    .CFOK_CFG6(4'b0000),
    .CHAN_BOND_KEEP_ALIGN("TRUE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0001001010),
    .CHAN_BOND_SEQ_1_2(10'b0001001010),
    .CHAN_BOND_SEQ_1_3(10'b0001001010),
    .CHAN_BOND_SEQ_1_4(10'b0110111100),
    .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_1(10'b0001000101),
    .CHAN_BOND_SEQ_2_2(10'b0001000101),
    .CHAN_BOND_SEQ_2_3(10'b0001000101),
    .CHAN_BOND_SEQ_2_4(10'b0110111100),
    .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_USE("TRUE"),
    .CHAN_BOND_SEQ_LEN(4),
    .CLK_COMMON_SWING(1'b0),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("TRUE"),
    .CLK_COR_MAX_LAT(20),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0100011100),
    .CLK_COR_SEQ_1_2(10'b0000000000),
    .CLK_COR_SEQ_1_3(10'b0000000000),
    .CLK_COR_SEQ_1_4(10'b0000000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0000000000),
    .CLK_COR_SEQ_2_2(10'b0000000000),
    .CLK_COR_SEQ_2_3(10'b0000000000),
    .CLK_COR_SEQ_2_4(10'b0000000000),
    .CLK_COR_SEQ_2_ENABLE(4'b0000),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000B01),
    .ES_CLK_PHASE_SEL(1'b0),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("FALSE"),
    .ES_HORZ_OFFSET(12'h010),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("TRUE"),
    .GEARBOX_MODE(3'b000),
    .IS_CLKRSVD0_INVERTED(1'b0),
    .IS_CLKRSVD1_INVERTED(1'b0),
    .IS_DMONITORCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_SIGVALIDCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .LOOPBACK_CFG(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("TRUE"),
    .PCS_RSVD_ATTR(48'h000000000100),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h09),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_LOOPBACK_CFG(1'b0),
    .PMA_RSV(32'h00000333),
    .PMA_RSV2(32'h00002040),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(4'b0000),
    .PMA_RSV5(1'b0),
    .PMA_RSV6(1'b0),
    .PMA_RSV7(1'b0),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b0100),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("TRUE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(83'h0000107FE406001041010),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b1),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPMRESET_TIME(7'b0001111),
    .RXLPM_BIAS_STARTUP_DISABLE(1'b0),
    .RXLPM_CFG(4'b0110),
    .RXLPM_CFG1(1'b0),
    .RXLPM_CM_CFG(1'b0),
    .RXLPM_GC_CFG(9'b111100010),
    .RXLPM_GC_CFG2(3'b001),
    .RXLPM_HF_CFG(14'b00001111110000),
    .RXLPM_HF_CFG2(5'b01010),
    .RXLPM_HF_CFG3(4'b0000),
    .RXLPM_HOLD_DURING_EIDLE(1'b1),
    .RXLPM_INCM_CFG(1'b1),
    .RXLPM_IPCM_CFG(1'b0),
    .RXLPM_LF_CFG(18'b000000001111110000),
    .RXLPM_LF_CFG2(5'b01010),
    .RXLPM_OSINT_CFG(3'b100),
    .RXOOB_CFG(7'b0000110),
    .RXOOB_CLK_CFG("FABRIC"),
    .RXOSCALRESET_TIME(5'b00011),
    .RXOSCALRESET_TIMEOUT(5'b00000),
    .RXOUT_DIV(2),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h004020),
    .RXPH_CFG(24'h000000),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPI_CFG0(3'b000),
    .RXPI_CFG1(1'b1),
    .RXPI_CFG2(1'b1),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("PMA"),
    .RXSYNC_MULTILANE(1'b1),
    .RXSYNC_OVRD(1'b1),
    .RXSYNC_SKIP_DA(1'b0),
    .RX_BIAS_CFG(16'b0000111100110011),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(4),
    .RX_CLKMUX_EN(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(4'b1010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(14'b00000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(10),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b1111),
    .SATA_BURST_VAL(3'b100),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SATA_PLL_CFG("VCO_3000MHZ"),
    .SHOW_REALIGN_COMMA("FALSE"),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
    .SIM_VERSION("1.0"),
    .TERM_RCAL_CFG(15'b100001000010000),
    .TERM_RCAL_OVRD(3'b000),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("FALSE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOOB_CFG(1'b1),
    .TXOUT_DIV(2),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPI_CFG0(2'b00),
    .TXPI_CFG1(2'b00),
    .TXPI_CFG2(2'b00),
    .TXPI_CFG3(1'b0),
    .TXPI_CFG4(1'b0),
    .TXPI_CFG5(3'b000),
    .TXPI_GREY_SEL(1'b0),
    .TXPI_INVSTROBE_SEL(1'b0),
    .TXPI_PPMCLK_SEL("TXUSRCLK2"),
    .TXPI_PPM_CFG(8'b00000000),
    .TXPI_SYNFREQ_PPM(3'b000),
    .TXPMARESET_TIME(5'b00011),
    .TXSYNC_MULTILANE(1'b1),
    .TXSYNC_OVRD(1'b1),
    .TXSYNC_SKIP_DA(1'b0),
    .TX_CLK25_DIV(4),
    .TX_CLKMUX_EN(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(6'b010100),
    .TX_DEEMPH1(6'b001011),
    .TX_DRIVE_MODE("PIPE"),
    .TX_EIDLE_ASSERT_DELAY(3'b010),
    .TX_EIDLE_DEASSERT_DELAY(3'b010),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001111),
    .TX_MARGIN_FULL_1(7'b1001110),
    .TX_MARGIN_FULL_2(7'b1001101),
    .TX_MARGIN_FULL_3(7'b1001100),
    .TX_MARGIN_FULL_4(7'b1000011),
    .TX_MARGIN_LOW_0(7'b1000101),
    .TX_MARGIN_LOW_1(7'b1000110),
    .TX_MARGIN_LOW_2(7'b1000011),
    .TX_MARGIN_LOW_3(7'b1000010),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_PREDRIVER_MODE(1'b0),
    .TX_RXDETECT_CFG(14'h0064),
    .TX_RXDETECT_REF(3'b011),
    .TX_XCLK_SEL("TXUSR"),
    .UCODEER_CLR(1'b0),
    .USE_PCS_CLK_PHASE_SEL(1'b0)) 
    \gtp_channel.gtpe2_channel_i 
       (.CFGRESET(1'b0),
        .CLKRSVD0(1'b0),
        .CLKRSVD1(1'b0),
        .DMONFIFORESET(1'b0),
        .DMONITORCLK(1'b0),
        .DMONITOROUT({\gtp_channel.gtpe2_channel_i_n_48 ,\gtp_channel.gtpe2_channel_i_n_49 ,\gtp_channel.gtpe2_channel_i_n_50 ,\gtp_channel.gtpe2_channel_i_n_51 ,\gtp_channel.gtpe2_channel_i_n_52 ,\gtp_channel.gtpe2_channel_i_n_53 ,\gtp_channel.gtpe2_channel_i_n_54 ,\gtp_channel.gtpe2_channel_i_n_55 ,\gtp_channel.gtpe2_channel_i_n_56 ,\gtp_channel.gtpe2_channel_i_n_57 ,\gtp_channel.gtpe2_channel_i_n_58 ,\gtp_channel.gtpe2_channel_i_n_59 ,\gtp_channel.gtpe2_channel_i_n_60 ,\gtp_channel.gtpe2_channel_i_n_61 ,\gtp_channel.gtpe2_channel_i_n_62 }),
        .DRPADDR({1'b0,1'b0,1'b0,1'b0,DRPADDR,1'b0,1'b0,1'b0,DRPADDR}),
        .DRPCLK(CLK),
        .DRPDI(DRPDI),
        .DRPDO(D),
        .DRPEN(\gtp_channel.gtpe2_channel_i_7 ),
        .DRPRDY(\gtp_channel.gtpe2_channel_i_0 ),
        .DRPWE(\gtp_channel.gtpe2_channel_i_8 ),
        .EYESCANDATAERROR(\gtp_channel.gtpe2_channel_i_n_1 ),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(user_eyescanreset_0),
        .EYESCANTRIGGER(1'b0),
        .GTPRXN(pci_exp_rxn),
        .GTPRXP(pci_exp_rxp),
        .GTPTXN(pci_exp_txn),
        .GTPTXP(pci_exp_txp),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(rst_gtreset),
        .GTTXRESET(rst_gtreset),
        .LOOPBACK({1'b0,1'b0,1'b0}),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(\NLW_gtp_channel.gtpe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
        .PHYSTATUS(\gtp_channel.gtpe2_channel_i_1 ),
        .PLL0CLK(\gtp_channel.gtpe2_channel_i_9 ),
        .PLL0REFCLK(\gtp_channel.gtpe2_channel_i_10 ),
        .PLL1CLK(1'b0),
        .PLL1REFCLK(1'b0),
        .PMARSVDIN0(1'b0),
        .PMARSVDIN1(1'b0),
        .PMARSVDIN2(1'b0),
        .PMARSVDIN3(1'b0),
        .PMARSVDIN4(1'b0),
        .PMARSVDOUT0(\NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT0_UNCONNECTED ),
        .PMARSVDOUT1(\NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT1_UNCONNECTED ),
        .RESETOVRD(user_resetovrd_0),
        .RX8B10BEN(1'b1),
        .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXBUFRESET(user_rxbufreset_0),
        .RXBUFSTATUS({\gtp_channel.gtpe2_channel_i_n_103 ,\gtp_channel.gtpe2_channel_i_n_104 ,\gtp_channel.gtpe2_channel_i_n_105 }),
        .RXBYTEISALIGNED(\gtp_channel.gtpe2_channel_i_n_7 ),
        .RXBYTEREALIGN(\gtp_channel.gtpe2_channel_i_n_8 ),
        .RXCDRFREQRESET(user_rxcdrfreqreset_0),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(gt_rxcdrlock_0),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(user_rxcdrreset_0),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(\NLW_gtp_channel.gtpe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
        .RXCHANISALIGNED(pipe_rx0_chanisaligned_gt),
        .RXCHANREALIGN(\NLW_gtp_channel.gtpe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
        .RXCHARISCOMMA({\gtp_channel.gtpe2_channel_i_n_144 ,\gtp_channel.gtpe2_channel_i_n_145 ,\gtp_channel.gtpe2_channel_i_n_146 ,\gtp_channel.gtpe2_channel_i_n_147 }),
        .RXCHARISK({\gtp_channel.gtpe2_channel_i_n_148 ,\gtp_channel.gtpe2_channel_i_n_149 ,gt_rx_data_k_wire_filter}),
        .RXCHBONDEN(1'b1),
        .RXCHBONDI({1'b0,1'b0,1'b0,1'b0}),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b1}),
        .RXCHBONDMASTER(1'b1),
        .RXCHBONDO(RXCHBONDO),
        .RXCHBONDSLAVE(1'b0),
        .RXCLKCORCNT(\NLW_gtp_channel.gtpe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
        .RXCOMINITDET(\NLW_gtp_channel.gtpe2_channel_i_RXCOMINITDET_UNCONNECTED ),
        .RXCOMMADET(\gtp_channel.gtpe2_channel_i_n_14 ),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(\NLW_gtp_channel.gtpe2_channel_i_RXCOMSASDET_UNCONNECTED ),
        .RXCOMWAKEDET(\NLW_gtp_channel.gtpe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
        .RXDATA({\gtp_channel.gtpe2_channel_i_n_112 ,\gtp_channel.gtpe2_channel_i_n_113 ,\gtp_channel.gtpe2_channel_i_n_114 ,\gtp_channel.gtpe2_channel_i_n_115 ,\gtp_channel.gtpe2_channel_i_n_116 ,\gtp_channel.gtpe2_channel_i_n_117 ,\gtp_channel.gtpe2_channel_i_n_118 ,\gtp_channel.gtpe2_channel_i_n_119 ,\gtp_channel.gtpe2_channel_i_n_120 ,\gtp_channel.gtpe2_channel_i_n_121 ,\gtp_channel.gtpe2_channel_i_n_122 ,\gtp_channel.gtpe2_channel_i_n_123 ,\gtp_channel.gtpe2_channel_i_n_124 ,\gtp_channel.gtpe2_channel_i_n_125 ,\gtp_channel.gtpe2_channel_i_n_126 ,\gtp_channel.gtpe2_channel_i_n_127 ,gt_rx_data_wire_filter}),
        .RXDATAVALID(\NLW_gtp_channel.gtpe2_channel_i_RXDATAVALID_UNCONNECTED [1:0]),
        .RXDDIEN(1'b0),
        .RXDFEXYDEN(1'b0),
        .RXDISPERR({\gtp_channel.gtpe2_channel_i_n_156 ,\gtp_channel.gtpe2_channel_i_n_157 ,\gtp_channel.gtpe2_channel_i_n_158 ,\gtp_channel.gtpe2_channel_i_n_159 }),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(1'b0),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(1'b0),
        .RXDLYSRESETDONE(\gtp_channel.gtpe2_channel_i_n_17 ),
        .RXELECIDLE(gt_rx_elec_idle_wire_filter),
        .RXELECIDLEMODE({1'b0,1'b0}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(\NLW_gtp_channel.gtpe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
        .RXHEADERVALID(\NLW_gtp_channel.gtpe2_channel_i_RXHEADERVALID_UNCONNECTED ),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFOVRDEN(1'b0),
        .RXLPMOSINTNTRLEN(1'b0),
        .RXLPMRESET(1'b0),
        .RXMCOMMAALIGNEN(1'b1),
        .RXNOTINTABLE({\gtp_channel.gtpe2_channel_i_n_160 ,\gtp_channel.gtpe2_channel_i_n_161 ,\gtp_channel.gtpe2_channel_i_n_162 ,\gtp_channel.gtpe2_channel_i_n_163 }),
        .RXOOBRESET(1'b0),
        .RXOSCALRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSINTCFG({1'b0,1'b0,1'b1,1'b0}),
        .RXOSINTDONE(\NLW_gtp_channel.gtpe2_channel_i_RXOSINTDONE_UNCONNECTED ),
        .RXOSINTEN(1'b1),
        .RXOSINTHOLD(1'b0),
        .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
        .RXOSINTNTRLEN(1'b0),
        .RXOSINTOVRDEN(1'b0),
        .RXOSINTPD(1'b0),
        .RXOSINTSTARTED(\NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTARTED_UNCONNECTED ),
        .RXOSINTSTROBE(1'b0),
        .RXOSINTSTROBEDONE(\NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBEDONE_UNCONNECTED ),
        .RXOSINTSTROBESTARTED(\NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBESTARTED_UNCONNECTED ),
        .RXOSINTTESTOVRDEN(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(\gtp_channel.gtpe2_channel_i_n_24 ),
        .RXOUTCLKFABRIC(\NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
        .RXOUTCLKPCS(\NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
        .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .RXPCOMMAALIGNEN(1'b1),
        .RXPCSRESET(user_rxpcsreset_0),
        .RXPD(\gtp_channel.gtpe2_channel_i_12 ),
        .RXPHALIGN(1'b0),
        .RXPHALIGNDONE(SYNC_RXPHALIGNDONE_M),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(\NLW_gtp_channel.gtpe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(\NLW_gtp_channel.gtpe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
        .RXPMARESET(user_rxpmareset_0),
        .RXPMARESETDONE(\gtp_channel.gtpe2_channel_i_2 ),
        .RXPOLARITY(pipe_rx0_polarity_gt),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(\gtp_channel.gtpe2_channel_i_n_29 ),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXRATE({1'b0,1'b0,RXRATE}),
        .RXRATEDONE(gt_rxratedone_0),
        .RXRATEMODE(1'b0),
        .RXRESETDONE(gt_rxresetdone_0),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(\NLW_gtp_channel.gtpe2_channel_i_RXSTARTOFSEQ_UNCONNECTED [1:0]),
        .RXSTATUS({RXSTATUS,\gtp_channel.gtpe2_channel_i_n_110 ,\gtp_channel.gtpe2_channel_i_n_111 }),
        .RXSYNCALLIN(rxsyncallin),
        .RXSYNCDONE(SYNC_RXSYNCDONE),
        .RXSYNCIN(gt_rxsyncout_0),
        .RXSYNCMODE(1'b1),
        .RXSYNCOUT(gt_rxsyncout_0),
        .RXSYSCLKSEL({1'b0,1'b0}),
        .RXUSERRDY(rst_userrdy),
        .RXUSRCLK(\gtp_channel.gtpe2_channel_i_11 ),
        .RXUSRCLK2(\gtp_channel.gtpe2_channel_i_11 ),
        .RXVALID(gt_rxvalid_0),
        .SETERRSTATUS(1'b0),
        .SIGVALIDCLK(user_oobclk_0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(1'b1),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(\NLW_gtp_channel.gtpe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,TXCHARDISPMODE}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,\gtp_channel.gtpe2_channel_i_15 }),
        .TXCOMFINISH(\NLW_gtp_channel.gtpe2_channel_i_TXCOMFINISH_UNCONNECTED ),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gtp_channel.gtpe2_channel_i_14 }),
        .TXDEEMPH(pipe_tx_deemph_gt),
        .TXDETECTRX(pipe_tx_rcvr_det_gt),
        .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b0),
        .TXDLYEN(sync_txdlyen_0),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(Q[0]),
        .TXDLYSRESETDONE(\gtp_channel.gtpe2_channel_i_n_36 ),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(pipe_tx0_elec_idle_gt),
        .TXGEARBOXREADY(\NLW_gtp_channel.gtpe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(1'b0),
        .TXMAINCURSOR(TXMAINCURSOR),
        .TXMARGIN(\gtp_channel.gtpe2_channel_i_13 ),
        .TXOUTCLK(\gtp_channel.gtpe2_channel_i_3 ),
        .TXOUTCLKFABRIC(\NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
        .TXOUTCLKPCS(\NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
        .TXOUTCLKSEL({1'b0,1'b1,1'b1}),
        .TXPCSRESET(1'b0),
        .TXPD(\gtp_channel.gtpe2_channel_i_12 ),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(Q[2]),
        .TXPHALIGNDONE(\gtp_channel.gtpe2_channel_i_4 ),
        .TXPHALIGNEN(1'b1),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(Q[1]),
        .TXPHINITDONE(\gtp_channel.gtpe2_channel_i_5 ),
        .TXPHOVRDEN(1'b0),
        .TXPIPPMEN(1'b0),
        .TXPIPPMOVRDEN(1'b0),
        .TXPIPPMPD(1'b0),
        .TXPIPPMSEL(1'b0),
        .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPISOPD(1'b0),
        .TXPMARESET(1'b0),
        .TXPMARESETDONE(\NLW_gtp_channel.gtpe2_channel_i_TXPMARESETDONE_UNCONNECTED ),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR(TXPOSTCURSOR),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR(TXPRECURSOR),
        .TXPRECURSORINV(1'b0),
        .TXRATE({1'b0,1'b0,RXRATE}),
        .TXRATEDONE(gt_txratedone_0),
        .TXRATEMODE(1'b0),
        .TXRESETDONE(gt_txresetdone_0),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYNCALLIN(SYNC_TXPHALIGNDONE),
        .TXSYNCDONE(SYNC_TXSYNCDONE),
        .TXSYNCIN(gt_txsyncout_0),
        .TXSYNCMODE(1'b1),
        .TXSYNCOUT(gt_txsyncout_0),
        .TXSYSCLKSEL({1'b0,1'b0}),
        .TXUSERRDY(rst_userrdy),
        .TXUSRCLK(\gtp_channel.gtpe2_channel_i_11 ),
        .TXUSRCLK2(\gtp_channel.gtpe2_channel_i_11 ));
  LUT2 #(
    .INIT(4'h8)) 
    rxdlysresetdone_reg1_i_1
       (.I0(\gtp_channel.gtpe2_channel_i_n_17 ),
        .I1(rxdlysresetdone_reg1_reg),
        .O(SYNC_RXDLYSRESETDONE));
  LUT2 #(
    .INIT(4'h8)) 
    txdlysresetdone_reg1_i_1
       (.I0(\gtp_channel.gtpe2_channel_i_n_36 ),
        .I1(txdlysresetdone_reg1_reg),
        .O(SYNC_TXDLYSRESETDONE));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_gt_wrapper" *) 
module xdma_0_pcie2_ip_gt_wrapper_31
   (\gtp_channel.gtpe2_channel_i_0 ,
    pci_exp_txn,
    pci_exp_txp,
    \gtp_channel.gtpe2_channel_i_1 ,
    gt_rxcdrlock_1,
    pipe_rx1_chanisaligned_gt,
    \gtp_channel.gtpe2_channel_i_2 ,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXPHALIGNDONE_S,
    \gtp_channel.gtpe2_channel_i_3 ,
    gt_rxratedone_1,
    gt_rxresetdone_1,
    SYNC_RXSYNCDONE,
    gt_rxvalid_1,
    \gtp_channel.gtpe2_channel_i_4 ,
    \gtp_channel.gtpe2_channel_i_5 ,
    \gtp_channel.gtpe2_channel_i_6 ,
    gt_txratedone_1,
    gt_txresetdone_1,
    SYNC_TXSYNCDONE,
    D,
    RXSTATUS,
    gt_rx_data_wire_filter,
    gt_rx_data_k_wire_filter,
    \gtp_channel.gtpe2_channel_i_7 ,
    CLK,
    \gtp_channel.gtpe2_channel_i_8 ,
    \gtp_channel.gtpe2_channel_i_9 ,
    user_eyescanreset_1,
    pci_exp_rxn,
    pci_exp_rxp,
    rst_gtreset,
    \gtp_channel.gtpe2_channel_i_10 ,
    \gtp_channel.gtpe2_channel_i_11 ,
    user_resetovrd_1,
    user_rxbufreset_1,
    user_rxcdrfreqreset_1,
    user_rxcdrreset_1,
    user_rxpcsreset_1,
    user_rxpmareset_1,
    pipe_rx1_polarity_gt,
    rxsyncallin,
    gt_rxsyncout_0,
    rst_userrdy,
    \gtp_channel.gtpe2_channel_i_12 ,
    user_oobclk_1,
    pipe_tx_deemph_gt,
    pipe_tx_rcvr_det_gt,
    Q,
    pipe_tx1_elec_idle_gt,
    SYNC_TXPHALIGNDONE,
    gt_txsyncout_0,
    DRPDI,
    \gtp_channel.gtpe2_channel_i_13 ,
    RXRATE,
    \gtp_channel.gtpe2_channel_i_14 ,
    \gtp_channel.gtpe2_channel_i_15 ,
    RXCHBONDO,
    \gtp_channel.gtpe2_channel_i_16 ,
    \gtp_channel.gtpe2_channel_i_17 ,
    TXPOSTCURSOR,
    TXPRECURSOR,
    TXMAINCURSOR,
    DRPADDR,
    \gt_rx_status_q_reg[0] ,
    \gt_rx_status_q_reg[2] );
  output \gtp_channel.gtpe2_channel_i_0 ;
  output [0:0]pci_exp_txn;
  output [0:0]pci_exp_txp;
  output [0:0]\gtp_channel.gtpe2_channel_i_1 ;
  output gt_rxcdrlock_1;
  output pipe_rx1_chanisaligned_gt;
  output \gtp_channel.gtpe2_channel_i_2 ;
  output [0:0]gt_rx_elec_idle_wire_filter;
  output SYNC_RXPHALIGNDONE_S;
  output [0:0]\gtp_channel.gtpe2_channel_i_3 ;
  output gt_rxratedone_1;
  output gt_rxresetdone_1;
  output SYNC_RXSYNCDONE;
  output gt_rxvalid_1;
  output \gtp_channel.gtpe2_channel_i_4 ;
  output \gtp_channel.gtpe2_channel_i_5 ;
  output \gtp_channel.gtpe2_channel_i_6 ;
  output gt_txratedone_1;
  output gt_txresetdone_1;
  output SYNC_TXSYNCDONE;
  output [15:0]D;
  output [0:0]RXSTATUS;
  output [15:0]gt_rx_data_wire_filter;
  output [1:0]gt_rx_data_k_wire_filter;
  output [2:0]\gtp_channel.gtpe2_channel_i_7 ;
  input CLK;
  input \gtp_channel.gtpe2_channel_i_8 ;
  input \gtp_channel.gtpe2_channel_i_9 ;
  input user_eyescanreset_1;
  input [0:0]pci_exp_rxn;
  input [0:0]pci_exp_rxp;
  input rst_gtreset;
  input \gtp_channel.gtpe2_channel_i_10 ;
  input \gtp_channel.gtpe2_channel_i_11 ;
  input user_resetovrd_1;
  input user_rxbufreset_1;
  input user_rxcdrfreqreset_1;
  input user_rxcdrreset_1;
  input user_rxpcsreset_1;
  input user_rxpmareset_1;
  input pipe_rx1_polarity_gt;
  input rxsyncallin;
  input gt_rxsyncout_0;
  input rst_userrdy;
  input \gtp_channel.gtpe2_channel_i_12 ;
  input user_oobclk_1;
  input pipe_tx_deemph_gt;
  input pipe_tx_rcvr_det_gt;
  input [2:0]Q;
  input pipe_tx1_elec_idle_gt;
  input SYNC_TXPHALIGNDONE;
  input gt_txsyncout_0;
  input [15:0]DRPDI;
  input [1:0]\gtp_channel.gtpe2_channel_i_13 ;
  input [0:0]RXRATE;
  input [2:0]\gtp_channel.gtpe2_channel_i_14 ;
  input [15:0]\gtp_channel.gtpe2_channel_i_15 ;
  input [3:0]RXCHBONDO;
  input [0:0]\gtp_channel.gtpe2_channel_i_16 ;
  input [1:0]\gtp_channel.gtpe2_channel_i_17 ;
  input [4:0]TXPOSTCURSOR;
  input [4:0]TXPRECURSOR;
  input [6:0]TXMAINCURSOR;
  input [0:0]DRPADDR;
  input \gt_rx_status_q_reg[0] ;
  input \gt_rx_status_q_reg[2] ;

  wire CLK;
  wire [15:0]D;
  wire [0:0]DRPADDR;
  wire [15:0]DRPDI;
  wire [2:0]Q;
  wire [3:0]RXCHBONDO;
  wire [0:0]RXRATE;
  wire [0:0]RXSTATUS;
  wire SYNC_RXPHALIGNDONE_S;
  wire SYNC_RXSYNCDONE;
  wire SYNC_TXPHALIGNDONE;
  wire SYNC_TXSYNCDONE;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire [1:0]gt_rx_data_k_wire_filter;
  wire [15:0]gt_rx_data_wire_filter;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire \gt_rx_status_q_reg[0] ;
  wire \gt_rx_status_q_reg[2] ;
  wire gt_rxcdrlock_1;
  wire gt_rxratedone_1;
  wire gt_rxresetdone_1;
  wire gt_rxsyncout_0;
  wire gt_rxvalid_1;
  wire gt_txratedone_1;
  wire gt_txresetdone_1;
  wire gt_txsyncout_0;
  wire \gtp_channel.gtpe2_channel_i_0 ;
  wire [0:0]\gtp_channel.gtpe2_channel_i_1 ;
  wire \gtp_channel.gtpe2_channel_i_10 ;
  wire \gtp_channel.gtpe2_channel_i_11 ;
  wire \gtp_channel.gtpe2_channel_i_12 ;
  wire [1:0]\gtp_channel.gtpe2_channel_i_13 ;
  wire [2:0]\gtp_channel.gtpe2_channel_i_14 ;
  wire [15:0]\gtp_channel.gtpe2_channel_i_15 ;
  wire [0:0]\gtp_channel.gtpe2_channel_i_16 ;
  wire [1:0]\gtp_channel.gtpe2_channel_i_17 ;
  wire \gtp_channel.gtpe2_channel_i_2 ;
  wire [0:0]\gtp_channel.gtpe2_channel_i_3 ;
  wire \gtp_channel.gtpe2_channel_i_4 ;
  wire \gtp_channel.gtpe2_channel_i_5 ;
  wire \gtp_channel.gtpe2_channel_i_6 ;
  wire [2:0]\gtp_channel.gtpe2_channel_i_7 ;
  wire \gtp_channel.gtpe2_channel_i_8 ;
  wire \gtp_channel.gtpe2_channel_i_9 ;
  wire \gtp_channel.gtpe2_channel_i_n_1 ;
  wire \gtp_channel.gtpe2_channel_i_n_103 ;
  wire \gtp_channel.gtpe2_channel_i_n_104 ;
  wire \gtp_channel.gtpe2_channel_i_n_105 ;
  wire \gtp_channel.gtpe2_channel_i_n_110 ;
  wire \gtp_channel.gtpe2_channel_i_n_111 ;
  wire \gtp_channel.gtpe2_channel_i_n_112 ;
  wire \gtp_channel.gtpe2_channel_i_n_113 ;
  wire \gtp_channel.gtpe2_channel_i_n_114 ;
  wire \gtp_channel.gtpe2_channel_i_n_115 ;
  wire \gtp_channel.gtpe2_channel_i_n_116 ;
  wire \gtp_channel.gtpe2_channel_i_n_117 ;
  wire \gtp_channel.gtpe2_channel_i_n_118 ;
  wire \gtp_channel.gtpe2_channel_i_n_119 ;
  wire \gtp_channel.gtpe2_channel_i_n_120 ;
  wire \gtp_channel.gtpe2_channel_i_n_121 ;
  wire \gtp_channel.gtpe2_channel_i_n_122 ;
  wire \gtp_channel.gtpe2_channel_i_n_123 ;
  wire \gtp_channel.gtpe2_channel_i_n_124 ;
  wire \gtp_channel.gtpe2_channel_i_n_125 ;
  wire \gtp_channel.gtpe2_channel_i_n_126 ;
  wire \gtp_channel.gtpe2_channel_i_n_127 ;
  wire \gtp_channel.gtpe2_channel_i_n_14 ;
  wire \gtp_channel.gtpe2_channel_i_n_144 ;
  wire \gtp_channel.gtpe2_channel_i_n_145 ;
  wire \gtp_channel.gtpe2_channel_i_n_146 ;
  wire \gtp_channel.gtpe2_channel_i_n_147 ;
  wire \gtp_channel.gtpe2_channel_i_n_148 ;
  wire \gtp_channel.gtpe2_channel_i_n_149 ;
  wire \gtp_channel.gtpe2_channel_i_n_152 ;
  wire \gtp_channel.gtpe2_channel_i_n_153 ;
  wire \gtp_channel.gtpe2_channel_i_n_154 ;
  wire \gtp_channel.gtpe2_channel_i_n_155 ;
  wire \gtp_channel.gtpe2_channel_i_n_156 ;
  wire \gtp_channel.gtpe2_channel_i_n_157 ;
  wire \gtp_channel.gtpe2_channel_i_n_158 ;
  wire \gtp_channel.gtpe2_channel_i_n_159 ;
  wire \gtp_channel.gtpe2_channel_i_n_160 ;
  wire \gtp_channel.gtpe2_channel_i_n_161 ;
  wire \gtp_channel.gtpe2_channel_i_n_162 ;
  wire \gtp_channel.gtpe2_channel_i_n_163 ;
  wire \gtp_channel.gtpe2_channel_i_n_24 ;
  wire \gtp_channel.gtpe2_channel_i_n_29 ;
  wire \gtp_channel.gtpe2_channel_i_n_33 ;
  wire \gtp_channel.gtpe2_channel_i_n_38 ;
  wire \gtp_channel.gtpe2_channel_i_n_47 ;
  wire \gtp_channel.gtpe2_channel_i_n_48 ;
  wire \gtp_channel.gtpe2_channel_i_n_49 ;
  wire \gtp_channel.gtpe2_channel_i_n_50 ;
  wire \gtp_channel.gtpe2_channel_i_n_51 ;
  wire \gtp_channel.gtpe2_channel_i_n_52 ;
  wire \gtp_channel.gtpe2_channel_i_n_53 ;
  wire \gtp_channel.gtpe2_channel_i_n_54 ;
  wire \gtp_channel.gtpe2_channel_i_n_55 ;
  wire \gtp_channel.gtpe2_channel_i_n_56 ;
  wire \gtp_channel.gtpe2_channel_i_n_57 ;
  wire \gtp_channel.gtpe2_channel_i_n_58 ;
  wire \gtp_channel.gtpe2_channel_i_n_59 ;
  wire \gtp_channel.gtpe2_channel_i_n_60 ;
  wire \gtp_channel.gtpe2_channel_i_n_61 ;
  wire \gtp_channel.gtpe2_channel_i_n_62 ;
  wire \gtp_channel.gtpe2_channel_i_n_7 ;
  wire \gtp_channel.gtpe2_channel_i_n_8 ;
  wire [0:0]pci_exp_rxn;
  wire [0:0]pci_exp_rxp;
  wire [0:0]pci_exp_txn;
  wire [0:0]pci_exp_txp;
  wire pipe_rx1_chanisaligned_gt;
  wire pipe_rx1_polarity_gt;
  wire pipe_tx1_elec_idle_gt;
  wire pipe_tx_deemph_gt;
  wire pipe_tx_rcvr_det_gt;
  wire rst_gtreset;
  wire rst_userrdy;
  wire rxsyncallin;
  wire user_eyescanreset_1;
  wire user_oobclk_1;
  wire user_resetovrd_1;
  wire user_rxbufreset_1;
  wire user_rxcdrfreqreset_1;
  wire user_rxcdrreset_1;
  wire user_rxpcsreset_1;
  wire user_rxpmareset_1;
  wire \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT0_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT1_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXCOMINITDET_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXCOMSASDET_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXHEADERVALID_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOSINTDONE_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTARTED_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBEDONE_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBESTARTED_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_TXCOMFINISH_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtp_channel.gtpe2_channel_i_TXPMARESETDONE_UNCONNECTED ;
  wire [15:0]\NLW_gtp_channel.gtpe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
  wire [1:0]\NLW_gtp_channel.gtpe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
  wire [1:0]\NLW_gtp_channel.gtpe2_channel_i_RXDATAVALID_UNCONNECTED ;
  wire [2:0]\NLW_gtp_channel.gtpe2_channel_i_RXHEADER_UNCONNECTED ;
  wire [4:0]\NLW_gtp_channel.gtpe2_channel_i_RXPHMONITOR_UNCONNECTED ;
  wire [4:0]\NLW_gtp_channel.gtpe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
  wire [1:0]\NLW_gtp_channel.gtpe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
  wire [1:0]\NLW_gtp_channel.gtpe2_channel_i_TXBUFSTATUS_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair1810" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \gt_rx_status_q[0]_i_1 
       (.I0(\gtp_channel.gtpe2_channel_i_n_111 ),
        .I1(\gt_rx_status_q_reg[0] ),
        .I2(\gt_rx_status_q_reg[2] ),
        .O(\gtp_channel.gtpe2_channel_i_7 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1810" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \gt_rx_status_q[1]_i_1 
       (.I0(\gtp_channel.gtpe2_channel_i_n_110 ),
        .I1(\gt_rx_status_q_reg[0] ),
        .I2(\gt_rx_status_q_reg[2] ),
        .O(\gtp_channel.gtpe2_channel_i_7 [1]));
  LUT3 #(
    .INIT(8'h8A)) 
    \gt_rx_status_q[2]_i_1 
       (.I0(RXSTATUS),
        .I1(\gt_rx_status_q_reg[0] ),
        .I2(\gt_rx_status_q_reg[2] ),
        .O(\gtp_channel.gtpe2_channel_i_7 [2]));
  (* box_type = "PRIMITIVE" *) 
  GTPE2_CHANNEL #(
    .ACJTAG_DEBUG_MODE(1'b0),
    .ACJTAG_MODE(1'b0),
    .ACJTAG_RESET(1'b0),
    .ADAPT_CFG0(20'b00000000000000000000),
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(1),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CFOK_CFG(43'b1001001000000000000000001000000111010000000),
    .CFOK_CFG2(7'b0100000),
    .CFOK_CFG3(7'b0100000),
    .CFOK_CFG4(1'b0),
    .CFOK_CFG5(2'b00),
    .CFOK_CFG6(4'b0000),
    .CHAN_BOND_KEEP_ALIGN("TRUE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0001001010),
    .CHAN_BOND_SEQ_1_2(10'b0001001010),
    .CHAN_BOND_SEQ_1_3(10'b0001001010),
    .CHAN_BOND_SEQ_1_4(10'b0110111100),
    .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_1(10'b0001000101),
    .CHAN_BOND_SEQ_2_2(10'b0001000101),
    .CHAN_BOND_SEQ_2_3(10'b0001000101),
    .CHAN_BOND_SEQ_2_4(10'b0110111100),
    .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_USE("TRUE"),
    .CHAN_BOND_SEQ_LEN(4),
    .CLK_COMMON_SWING(1'b0),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("TRUE"),
    .CLK_COR_MAX_LAT(20),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0100011100),
    .CLK_COR_SEQ_1_2(10'b0000000000),
    .CLK_COR_SEQ_1_3(10'b0000000000),
    .CLK_COR_SEQ_1_4(10'b0000000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0000000000),
    .CLK_COR_SEQ_2_2(10'b0000000000),
    .CLK_COR_SEQ_2_3(10'b0000000000),
    .CLK_COR_SEQ_2_4(10'b0000000000),
    .CLK_COR_SEQ_2_ENABLE(4'b0000),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000B01),
    .ES_CLK_PHASE_SEL(1'b0),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("FALSE"),
    .ES_HORZ_OFFSET(12'h010),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("TRUE"),
    .GEARBOX_MODE(3'b000),
    .IS_CLKRSVD0_INVERTED(1'b0),
    .IS_CLKRSVD1_INVERTED(1'b0),
    .IS_DMONITORCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_SIGVALIDCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .LOOPBACK_CFG(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("TRUE"),
    .PCS_RSVD_ATTR(48'h000000000100),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h09),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_LOOPBACK_CFG(1'b0),
    .PMA_RSV(32'h00000333),
    .PMA_RSV2(32'h00002040),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(4'b0000),
    .PMA_RSV5(1'b0),
    .PMA_RSV6(1'b0),
    .PMA_RSV7(1'b0),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b0100),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("TRUE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(83'h0000107FE406001041010),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b1),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPMRESET_TIME(7'b0001111),
    .RXLPM_BIAS_STARTUP_DISABLE(1'b0),
    .RXLPM_CFG(4'b0110),
    .RXLPM_CFG1(1'b0),
    .RXLPM_CM_CFG(1'b0),
    .RXLPM_GC_CFG(9'b111100010),
    .RXLPM_GC_CFG2(3'b001),
    .RXLPM_HF_CFG(14'b00001111110000),
    .RXLPM_HF_CFG2(5'b01010),
    .RXLPM_HF_CFG3(4'b0000),
    .RXLPM_HOLD_DURING_EIDLE(1'b1),
    .RXLPM_INCM_CFG(1'b1),
    .RXLPM_IPCM_CFG(1'b0),
    .RXLPM_LF_CFG(18'b000000001111110000),
    .RXLPM_LF_CFG2(5'b01010),
    .RXLPM_OSINT_CFG(3'b100),
    .RXOOB_CFG(7'b0000110),
    .RXOOB_CLK_CFG("FABRIC"),
    .RXOSCALRESET_TIME(5'b00011),
    .RXOSCALRESET_TIMEOUT(5'b00000),
    .RXOUT_DIV(2),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h004020),
    .RXPH_CFG(24'h000000),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPI_CFG0(3'b000),
    .RXPI_CFG1(1'b1),
    .RXPI_CFG2(1'b1),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("PMA"),
    .RXSYNC_MULTILANE(1'b1),
    .RXSYNC_OVRD(1'b1),
    .RXSYNC_SKIP_DA(1'b0),
    .RX_BIAS_CFG(16'b0000111100110011),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(4),
    .RX_CLKMUX_EN(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(4'b1010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(14'b00000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(10),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b1111),
    .SATA_BURST_VAL(3'b100),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SATA_PLL_CFG("VCO_3000MHZ"),
    .SHOW_REALIGN_COMMA("FALSE"),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
    .SIM_VERSION("1.0"),
    .TERM_RCAL_CFG(15'b100001000010000),
    .TERM_RCAL_OVRD(3'b000),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("FALSE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOOB_CFG(1'b1),
    .TXOUT_DIV(2),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPI_CFG0(2'b00),
    .TXPI_CFG1(2'b00),
    .TXPI_CFG2(2'b00),
    .TXPI_CFG3(1'b0),
    .TXPI_CFG4(1'b0),
    .TXPI_CFG5(3'b000),
    .TXPI_GREY_SEL(1'b0),
    .TXPI_INVSTROBE_SEL(1'b0),
    .TXPI_PPMCLK_SEL("TXUSRCLK2"),
    .TXPI_PPM_CFG(8'b00000000),
    .TXPI_SYNFREQ_PPM(3'b000),
    .TXPMARESET_TIME(5'b00011),
    .TXSYNC_MULTILANE(1'b1),
    .TXSYNC_OVRD(1'b1),
    .TXSYNC_SKIP_DA(1'b0),
    .TX_CLK25_DIV(4),
    .TX_CLKMUX_EN(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(6'b010100),
    .TX_DEEMPH1(6'b001011),
    .TX_DRIVE_MODE("PIPE"),
    .TX_EIDLE_ASSERT_DELAY(3'b010),
    .TX_EIDLE_DEASSERT_DELAY(3'b010),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001111),
    .TX_MARGIN_FULL_1(7'b1001110),
    .TX_MARGIN_FULL_2(7'b1001101),
    .TX_MARGIN_FULL_3(7'b1001100),
    .TX_MARGIN_FULL_4(7'b1000011),
    .TX_MARGIN_LOW_0(7'b1000101),
    .TX_MARGIN_LOW_1(7'b1000110),
    .TX_MARGIN_LOW_2(7'b1000011),
    .TX_MARGIN_LOW_3(7'b1000010),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_PREDRIVER_MODE(1'b0),
    .TX_RXDETECT_CFG(14'h0064),
    .TX_RXDETECT_REF(3'b011),
    .TX_XCLK_SEL("TXUSR"),
    .UCODEER_CLR(1'b0),
    .USE_PCS_CLK_PHASE_SEL(1'b0)) 
    \gtp_channel.gtpe2_channel_i 
       (.CFGRESET(1'b0),
        .CLKRSVD0(1'b0),
        .CLKRSVD1(1'b0),
        .DMONFIFORESET(1'b0),
        .DMONITORCLK(1'b0),
        .DMONITOROUT({\gtp_channel.gtpe2_channel_i_n_48 ,\gtp_channel.gtpe2_channel_i_n_49 ,\gtp_channel.gtpe2_channel_i_n_50 ,\gtp_channel.gtpe2_channel_i_n_51 ,\gtp_channel.gtpe2_channel_i_n_52 ,\gtp_channel.gtpe2_channel_i_n_53 ,\gtp_channel.gtpe2_channel_i_n_54 ,\gtp_channel.gtpe2_channel_i_n_55 ,\gtp_channel.gtpe2_channel_i_n_56 ,\gtp_channel.gtpe2_channel_i_n_57 ,\gtp_channel.gtpe2_channel_i_n_58 ,\gtp_channel.gtpe2_channel_i_n_59 ,\gtp_channel.gtpe2_channel_i_n_60 ,\gtp_channel.gtpe2_channel_i_n_61 ,\gtp_channel.gtpe2_channel_i_n_62 }),
        .DRPADDR({1'b0,1'b0,1'b0,1'b0,DRPADDR,1'b0,1'b0,1'b0,DRPADDR}),
        .DRPCLK(CLK),
        .DRPDI(DRPDI),
        .DRPDO(D),
        .DRPEN(\gtp_channel.gtpe2_channel_i_8 ),
        .DRPRDY(\gtp_channel.gtpe2_channel_i_0 ),
        .DRPWE(\gtp_channel.gtpe2_channel_i_9 ),
        .EYESCANDATAERROR(\gtp_channel.gtpe2_channel_i_n_1 ),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(user_eyescanreset_1),
        .EYESCANTRIGGER(1'b0),
        .GTPRXN(pci_exp_rxn),
        .GTPRXP(pci_exp_rxp),
        .GTPTXN(pci_exp_txn),
        .GTPTXP(pci_exp_txp),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(rst_gtreset),
        .GTTXRESET(rst_gtreset),
        .LOOPBACK({1'b0,1'b0,1'b0}),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(\NLW_gtp_channel.gtpe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
        .PHYSTATUS(\gtp_channel.gtpe2_channel_i_1 ),
        .PLL0CLK(\gtp_channel.gtpe2_channel_i_10 ),
        .PLL0REFCLK(\gtp_channel.gtpe2_channel_i_11 ),
        .PLL1CLK(1'b0),
        .PLL1REFCLK(1'b0),
        .PMARSVDIN0(1'b0),
        .PMARSVDIN1(1'b0),
        .PMARSVDIN2(1'b0),
        .PMARSVDIN3(1'b0),
        .PMARSVDIN4(1'b0),
        .PMARSVDOUT0(\NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT0_UNCONNECTED ),
        .PMARSVDOUT1(\NLW_gtp_channel.gtpe2_channel_i_PMARSVDOUT1_UNCONNECTED ),
        .RESETOVRD(user_resetovrd_1),
        .RX8B10BEN(1'b1),
        .RXADAPTSELTEST({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXBUFRESET(user_rxbufreset_1),
        .RXBUFSTATUS({\gtp_channel.gtpe2_channel_i_n_103 ,\gtp_channel.gtpe2_channel_i_n_104 ,\gtp_channel.gtpe2_channel_i_n_105 }),
        .RXBYTEISALIGNED(\gtp_channel.gtpe2_channel_i_n_7 ),
        .RXBYTEREALIGN(\gtp_channel.gtpe2_channel_i_n_8 ),
        .RXCDRFREQRESET(user_rxcdrfreqreset_1),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(gt_rxcdrlock_1),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(user_rxcdrreset_1),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(\NLW_gtp_channel.gtpe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
        .RXCHANISALIGNED(pipe_rx1_chanisaligned_gt),
        .RXCHANREALIGN(\NLW_gtp_channel.gtpe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
        .RXCHARISCOMMA({\gtp_channel.gtpe2_channel_i_n_144 ,\gtp_channel.gtpe2_channel_i_n_145 ,\gtp_channel.gtpe2_channel_i_n_146 ,\gtp_channel.gtpe2_channel_i_n_147 }),
        .RXCHARISK({\gtp_channel.gtpe2_channel_i_n_148 ,\gtp_channel.gtpe2_channel_i_n_149 ,gt_rx_data_k_wire_filter}),
        .RXCHBONDEN(1'b1),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({\gtp_channel.gtpe2_channel_i_n_152 ,\gtp_channel.gtpe2_channel_i_n_153 ,\gtp_channel.gtpe2_channel_i_n_154 ,\gtp_channel.gtpe2_channel_i_n_155 }),
        .RXCHBONDSLAVE(1'b1),
        .RXCLKCORCNT(\NLW_gtp_channel.gtpe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
        .RXCOMINITDET(\NLW_gtp_channel.gtpe2_channel_i_RXCOMINITDET_UNCONNECTED ),
        .RXCOMMADET(\gtp_channel.gtpe2_channel_i_n_14 ),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(\NLW_gtp_channel.gtpe2_channel_i_RXCOMSASDET_UNCONNECTED ),
        .RXCOMWAKEDET(\NLW_gtp_channel.gtpe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
        .RXDATA({\gtp_channel.gtpe2_channel_i_n_112 ,\gtp_channel.gtpe2_channel_i_n_113 ,\gtp_channel.gtpe2_channel_i_n_114 ,\gtp_channel.gtpe2_channel_i_n_115 ,\gtp_channel.gtpe2_channel_i_n_116 ,\gtp_channel.gtpe2_channel_i_n_117 ,\gtp_channel.gtpe2_channel_i_n_118 ,\gtp_channel.gtpe2_channel_i_n_119 ,\gtp_channel.gtpe2_channel_i_n_120 ,\gtp_channel.gtpe2_channel_i_n_121 ,\gtp_channel.gtpe2_channel_i_n_122 ,\gtp_channel.gtpe2_channel_i_n_123 ,\gtp_channel.gtpe2_channel_i_n_124 ,\gtp_channel.gtpe2_channel_i_n_125 ,\gtp_channel.gtpe2_channel_i_n_126 ,\gtp_channel.gtpe2_channel_i_n_127 ,gt_rx_data_wire_filter}),
        .RXDATAVALID(\NLW_gtp_channel.gtpe2_channel_i_RXDATAVALID_UNCONNECTED [1:0]),
        .RXDDIEN(1'b0),
        .RXDFEXYDEN(1'b0),
        .RXDISPERR({\gtp_channel.gtpe2_channel_i_n_156 ,\gtp_channel.gtpe2_channel_i_n_157 ,\gtp_channel.gtpe2_channel_i_n_158 ,\gtp_channel.gtpe2_channel_i_n_159 }),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(1'b0),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(1'b0),
        .RXDLYSRESETDONE(\gtp_channel.gtpe2_channel_i_2 ),
        .RXELECIDLE(gt_rx_elec_idle_wire_filter),
        .RXELECIDLEMODE({1'b0,1'b0}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(\NLW_gtp_channel.gtpe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
        .RXHEADERVALID(\NLW_gtp_channel.gtpe2_channel_i_RXHEADERVALID_UNCONNECTED ),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFOVRDEN(1'b0),
        .RXLPMOSINTNTRLEN(1'b0),
        .RXLPMRESET(1'b0),
        .RXMCOMMAALIGNEN(1'b1),
        .RXNOTINTABLE({\gtp_channel.gtpe2_channel_i_n_160 ,\gtp_channel.gtpe2_channel_i_n_161 ,\gtp_channel.gtpe2_channel_i_n_162 ,\gtp_channel.gtpe2_channel_i_n_163 }),
        .RXOOBRESET(1'b0),
        .RXOSCALRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSINTCFG({1'b0,1'b0,1'b1,1'b0}),
        .RXOSINTDONE(\NLW_gtp_channel.gtpe2_channel_i_RXOSINTDONE_UNCONNECTED ),
        .RXOSINTEN(1'b1),
        .RXOSINTHOLD(1'b0),
        .RXOSINTID0({1'b0,1'b0,1'b0,1'b0}),
        .RXOSINTNTRLEN(1'b0),
        .RXOSINTOVRDEN(1'b0),
        .RXOSINTPD(1'b0),
        .RXOSINTSTARTED(\NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTARTED_UNCONNECTED ),
        .RXOSINTSTROBE(1'b0),
        .RXOSINTSTROBEDONE(\NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBEDONE_UNCONNECTED ),
        .RXOSINTSTROBESTARTED(\NLW_gtp_channel.gtpe2_channel_i_RXOSINTSTROBESTARTED_UNCONNECTED ),
        .RXOSINTTESTOVRDEN(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(\gtp_channel.gtpe2_channel_i_n_24 ),
        .RXOUTCLKFABRIC(\NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
        .RXOUTCLKPCS(\NLW_gtp_channel.gtpe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
        .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .RXPCOMMAALIGNEN(1'b1),
        .RXPCSRESET(user_rxpcsreset_1),
        .RXPD(\gtp_channel.gtpe2_channel_i_13 ),
        .RXPHALIGN(1'b0),
        .RXPHALIGNDONE(SYNC_RXPHALIGNDONE_S),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(\NLW_gtp_channel.gtpe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(\NLW_gtp_channel.gtpe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
        .RXPMARESET(user_rxpmareset_1),
        .RXPMARESETDONE(\gtp_channel.gtpe2_channel_i_3 ),
        .RXPOLARITY(pipe_rx1_polarity_gt),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(\gtp_channel.gtpe2_channel_i_n_29 ),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXRATE({1'b0,1'b0,RXRATE}),
        .RXRATEDONE(gt_rxratedone_1),
        .RXRATEMODE(1'b0),
        .RXRESETDONE(gt_rxresetdone_1),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(\NLW_gtp_channel.gtpe2_channel_i_RXSTARTOFSEQ_UNCONNECTED [1:0]),
        .RXSTATUS({RXSTATUS,\gtp_channel.gtpe2_channel_i_n_110 ,\gtp_channel.gtpe2_channel_i_n_111 }),
        .RXSYNCALLIN(rxsyncallin),
        .RXSYNCDONE(SYNC_RXSYNCDONE),
        .RXSYNCIN(gt_rxsyncout_0),
        .RXSYNCMODE(1'b0),
        .RXSYNCOUT(\gtp_channel.gtpe2_channel_i_n_33 ),
        .RXSYSCLKSEL({1'b0,1'b0}),
        .RXUSERRDY(rst_userrdy),
        .RXUSRCLK(\gtp_channel.gtpe2_channel_i_12 ),
        .RXUSRCLK2(\gtp_channel.gtpe2_channel_i_12 ),
        .RXVALID(gt_rxvalid_1),
        .SETERRSTATUS(1'b0),
        .SIGVALIDCLK(user_oobclk_1),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(1'b1),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(\NLW_gtp_channel.gtpe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,\gtp_channel.gtpe2_channel_i_16 }),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,\gtp_channel.gtpe2_channel_i_17 }),
        .TXCOMFINISH(\NLW_gtp_channel.gtpe2_channel_i_TXCOMFINISH_UNCONNECTED ),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gtp_channel.gtpe2_channel_i_15 }),
        .TXDEEMPH(pipe_tx_deemph_gt),
        .TXDETECTRX(pipe_tx_rcvr_det_gt),
        .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b0),
        .TXDLYEN(1'b0),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(Q[0]),
        .TXDLYSRESETDONE(\gtp_channel.gtpe2_channel_i_4 ),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(pipe_tx1_elec_idle_gt),
        .TXGEARBOXREADY(\NLW_gtp_channel.gtpe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(1'b0),
        .TXMAINCURSOR(TXMAINCURSOR),
        .TXMARGIN(\gtp_channel.gtpe2_channel_i_14 ),
        .TXOUTCLK(\gtp_channel.gtpe2_channel_i_n_38 ),
        .TXOUTCLKFABRIC(\NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
        .TXOUTCLKPCS(\NLW_gtp_channel.gtpe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
        .TXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD(\gtp_channel.gtpe2_channel_i_13 ),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(Q[2]),
        .TXPHALIGNDONE(\gtp_channel.gtpe2_channel_i_5 ),
        .TXPHALIGNEN(1'b1),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(Q[1]),
        .TXPHINITDONE(\gtp_channel.gtpe2_channel_i_6 ),
        .TXPHOVRDEN(1'b0),
        .TXPIPPMEN(1'b0),
        .TXPIPPMOVRDEN(1'b0),
        .TXPIPPMPD(1'b0),
        .TXPIPPMSEL(1'b0),
        .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXPISOPD(1'b0),
        .TXPMARESET(1'b0),
        .TXPMARESETDONE(\NLW_gtp_channel.gtpe2_channel_i_TXPMARESETDONE_UNCONNECTED ),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR(TXPOSTCURSOR),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR(TXPRECURSOR),
        .TXPRECURSORINV(1'b0),
        .TXRATE({1'b0,1'b0,RXRATE}),
        .TXRATEDONE(gt_txratedone_1),
        .TXRATEMODE(1'b0),
        .TXRESETDONE(gt_txresetdone_1),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYNCALLIN(SYNC_TXPHALIGNDONE),
        .TXSYNCDONE(SYNC_TXSYNCDONE),
        .TXSYNCIN(gt_txsyncout_0),
        .TXSYNCMODE(1'b0),
        .TXSYNCOUT(\gtp_channel.gtpe2_channel_i_n_47 ),
        .TXSYSCLKSEL({1'b0,1'b0}),
        .TXUSERRDY(rst_userrdy),
        .TXUSRCLK(\gtp_channel.gtpe2_channel_i_12 ),
        .TXUSRCLK2(\gtp_channel.gtpe2_channel_i_12 ));
endmodule

module xdma_0_pcie2_ip_gtp_cpllpd_ovrd
   (cpllpd,
    cpllrst,
    gt_cpllpdrefclk);
  output cpllpd;
  output cpllrst;
  input gt_cpllpdrefclk;

  wire cpllpd;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire cpllrst;
  wire gt_cpllpdrefclk;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;

  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(cpllpd),
        .R(1'b0));
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllrst),
        .R(1'b0));
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
endmodule

module xdma_0_pcie2_ip_gtp_pipe_drp
   (done_reg_0,
    \fsm_reg[1]_0 ,
    DRPDI,
    DRPADDR,
    \fsm_reg[1]_1 ,
    rst_dclk_reset,
    DRP_START00_out,
    CLK,
    rdy_reg1_reg_0,
    DRP_X160,
    D);
  output [0:0]done_reg_0;
  output \fsm_reg[1]_0 ;
  output [15:0]DRPDI;
  output [0:0]DRPADDR;
  output \fsm_reg[1]_1 ;
  input rst_dclk_reset;
  input DRP_START00_out;
  input CLK;
  input rdy_reg1_reg_0;
  input DRP_X160;
  input [15:0]D;

  wire CLK;
  wire [15:0]D;
  wire [0:0]DRPADDR;
  wire [15:0]DRPDI;
  wire DRP_START00_out;
  wire DRP_X160;
  wire \addr_reg[4]_i_1_n_0 ;
  wire \di_reg[15]_i_1_n_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg2;
  wire done_i_1_n_0;
  wire [0:0]done_reg_0;
  wire [4:4]drp_addr_0;
  wire [15:0]drp_di_0;
  wire [2:0]fsm;
  wire \fsm[0]_i_2_n_0 ;
  wire \fsm[0]_i_3_n_0 ;
  wire \fsm_reg[1]_0 ;
  wire \fsm_reg[1]_1 ;
  wire \fsm_reg_n_0_[0] ;
  wire \fsm_reg_n_0_[1] ;
  wire \fsm_reg_n_0_[2] ;
  wire [4:0]index;
  wire \index[4]_i_1_n_0 ;
  wire \index[4]_i_3_n_0 ;
  wire \index[4]_i_4_n_0 ;
  wire load_cnt;
  wire \load_cnt[0]_i_1_n_0 ;
  wire [11:11]p_1_in;
  wire [4:0]p_2_in;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg1;
  wire rdy_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg2;
  wire rst_dclk_reset;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg2;

  (* SOFT_HLUTNM = "soft_lutpair1765" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \addr_reg[4]_i_1 
       (.I0(index[3]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(index[1]),
        .O(\addr_reg[4]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\addr_reg[4]_i_1_n_0 ),
        .Q(drp_addr_0),
        .R(rst_dclk_reset));
  LUT1 #(
    .INIT(2'h1)) 
    \di_reg[11]_i_1 
       (.I0(x16_reg2),
        .O(p_1_in));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \di_reg[15]_i_1 
       (.I0(rst_dclk_reset),
        .I1(index[4]),
        .I2(index[3]),
        .I3(index[1]),
        .I4(index[0]),
        .I5(index[2]),
        .O(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[0]),
        .Q(drp_di_0[0]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[10]),
        .Q(drp_di_0[10]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_1_in),
        .Q(drp_di_0[11]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[12]),
        .Q(drp_di_0[12]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[13]),
        .Q(drp_di_0[13]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[14]),
        .Q(drp_di_0[14]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[15]),
        .Q(drp_di_0[15]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[1]),
        .Q(drp_di_0[1]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[2]),
        .Q(drp_di_0[2]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[3]),
        .Q(drp_di_0[3]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[4]),
        .Q(drp_di_0[4]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[5]),
        .Q(drp_di_0[5]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[6]),
        .Q(drp_di_0[6]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[7]),
        .Q(drp_di_0[7]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[8]),
        .Q(drp_di_0[8]),
        .R(\di_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[9]),
        .Q(drp_di_0[9]),
        .R(\di_reg[15]_i_1_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(do_reg1[0]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[10]),
        .Q(do_reg1[10]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[11]),
        .Q(do_reg1[11]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[12]),
        .Q(do_reg1[12]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[13]),
        .Q(do_reg1[13]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[14]),
        .Q(do_reg1[14]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[15]),
        .Q(do_reg1[15]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(do_reg1[1]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(do_reg1[2]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(do_reg1[3]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[4]),
        .Q(do_reg1[4]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[5]),
        .Q(do_reg1[5]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[6]),
        .Q(do_reg1[6]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[7]),
        .Q(do_reg1[7]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[8]),
        .Q(do_reg1[8]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[9]),
        .Q(do_reg1[9]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(rst_dclk_reset));
  LUT5 #(
    .INIT(32'hC001CC01)) 
    done_i_1
       (.I0(start_reg2),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[1] ),
        .I4(\index[4]_i_4_n_0 ),
        .O(done_i_1_n_0));
  FDSE #(
    .INIT(1'b0)) 
    done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(done_i_1_n_0),
        .Q(done_reg_0),
        .S(rst_dclk_reset));
  LUT6 #(
    .INIT(64'h0B3BFFFF0B3B0000)) 
    \fsm[0]_i_1 
       (.I0(\fsm[0]_i_2_n_0 ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(rdy_reg2),
        .I4(\fsm_reg_n_0_[2] ),
        .I5(\fsm[0]_i_3_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair1763" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \fsm[0]_i_2 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[4]),
        .O(\fsm[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h47FF47CC)) 
    \fsm[0]_i_3 
       (.I0(rdy_reg2),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(load_cnt),
        .I3(\fsm_reg_n_0_[0] ),
        .I4(start_reg2),
        .O(\fsm[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h1D501850)) 
    \fsm[1]_i_1 
       (.I0(\fsm_reg_n_0_[2] ),
        .I1(rdy_reg2),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[0] ),
        .I4(load_cnt),
        .O(fsm[1]));
  LUT4 #(
    .INIT(16'h6222)) 
    \fsm[2]_i_1 
       (.I0(\fsm_reg_n_0_[2] ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(rdy_reg2),
        .I3(\fsm_reg_n_0_[0] ),
        .O(fsm[2]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(\fsm_reg_n_0_[0] ),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(\fsm_reg_n_0_[1] ),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(\fsm_reg_n_0_[2] ),
        .R(rst_dclk_reset));
  (* SOFT_HLUTNM = "soft_lutpair1766" *) 
  LUT3 #(
    .INIT(8'h12)) 
    \gtp_channel.gtpe2_channel_i_i_1 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\fsm_reg_n_0_[2] ),
        .O(\fsm_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1771" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_10 
       (.I0(drp_di_0[9]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[9]));
  (* SOFT_HLUTNM = "soft_lutpair1770" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_11 
       (.I0(drp_di_0[8]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[8]));
  (* SOFT_HLUTNM = "soft_lutpair1770" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_12 
       (.I0(drp_di_0[7]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[7]));
  (* SOFT_HLUTNM = "soft_lutpair1769" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_13 
       (.I0(drp_di_0[6]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[6]));
  (* SOFT_HLUTNM = "soft_lutpair1769" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_14 
       (.I0(drp_di_0[5]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[5]));
  (* SOFT_HLUTNM = "soft_lutpair1768" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_15 
       (.I0(drp_di_0[4]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[4]));
  (* SOFT_HLUTNM = "soft_lutpair1768" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_16 
       (.I0(drp_di_0[3]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[3]));
  (* SOFT_HLUTNM = "soft_lutpair1767" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_17 
       (.I0(drp_di_0[2]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[2]));
  (* SOFT_HLUTNM = "soft_lutpair1767" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_18 
       (.I0(drp_di_0[1]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[1]));
  (* SOFT_HLUTNM = "soft_lutpair1766" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_19 
       (.I0(drp_di_0[0]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[0]));
  (* SOFT_HLUTNM = "soft_lutpair1775" *) 
  LUT3 #(
    .INIT(8'h10)) 
    \gtp_channel.gtpe2_channel_i_i_2 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\fsm_reg_n_0_[2] ),
        .O(\fsm_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1774" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_37__0 
       (.I0(drp_addr_0),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPADDR));
  (* SOFT_HLUTNM = "soft_lutpair1774" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_4__0 
       (.I0(drp_di_0[15]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[15]));
  (* SOFT_HLUTNM = "soft_lutpair1773" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_5__0 
       (.I0(drp_di_0[14]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[14]));
  (* SOFT_HLUTNM = "soft_lutpair1773" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_6 
       (.I0(drp_di_0[13]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[13]));
  (* SOFT_HLUTNM = "soft_lutpair1772" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_7 
       (.I0(drp_di_0[12]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[12]));
  (* SOFT_HLUTNM = "soft_lutpair1772" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_8 
       (.I0(drp_di_0[11]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[11]));
  (* SOFT_HLUTNM = "soft_lutpair1771" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_9 
       (.I0(drp_di_0[10]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[10]));
  (* SOFT_HLUTNM = "soft_lutpair1764" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    \index[0]_i_1 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\index[4]_i_4_n_0 ),
        .I2(index[0]),
        .I3(\fsm_reg_n_0_[2] ),
        .O(p_2_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair1764" *) 
  LUT5 #(
    .INIT(32'h14000000)) 
    \index[1]_i_1 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(index[1]),
        .I2(index[0]),
        .I3(\index[4]_i_4_n_0 ),
        .I4(\fsm_reg_n_0_[2] ),
        .O(p_2_in[1]));
  LUT6 #(
    .INIT(64'h1444000000000000)) 
    \index[2]_i_1 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(index[2]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(\index[4]_i_4_n_0 ),
        .I5(\fsm_reg_n_0_[2] ),
        .O(p_2_in[2]));
  LUT5 #(
    .INIT(32'h14000000)) 
    \index[3]_i_1 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(index[3]),
        .I2(\index[4]_i_3_n_0 ),
        .I3(\index[4]_i_4_n_0 ),
        .I4(\fsm_reg_n_0_[2] ),
        .O(p_2_in[3]));
  LUT3 #(
    .INIT(8'hA1)) 
    \index[4]_i_1 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\fsm_reg_n_0_[2] ),
        .O(\index[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1444000000000000)) 
    \index[4]_i_2 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(index[4]),
        .I2(index[3]),
        .I3(\index[4]_i_3_n_0 ),
        .I4(\index[4]_i_4_n_0 ),
        .I5(\fsm_reg_n_0_[2] ),
        .O(p_2_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair1765" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \index[4]_i_3 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .O(\index[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1763" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \index[4]_i_4 
       (.I0(index[3]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[4]),
        .I4(index[2]),
        .O(\index[4]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(CLK),
        .CE(\index[4]_i_1_n_0 ),
        .D(p_2_in[0]),
        .Q(index[0]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(CLK),
        .CE(\index[4]_i_1_n_0 ),
        .D(p_2_in[1]),
        .Q(index[1]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(CLK),
        .CE(\index[4]_i_1_n_0 ),
        .D(p_2_in[2]),
        .Q(index[2]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[3] 
       (.C(CLK),
        .CE(\index[4]_i_1_n_0 ),
        .D(p_2_in[3]),
        .Q(index[3]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[4] 
       (.C(CLK),
        .CE(\index[4]_i_1_n_0 ),
        .D(p_2_in[4]),
        .Q(index[4]),
        .R(rst_dclk_reset));
  (* SOFT_HLUTNM = "soft_lutpair1775" *) 
  LUT3 #(
    .INIT(8'h10)) 
    \load_cnt[0]_i_1 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[0] ),
        .O(\load_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1_n_0 ),
        .Q(load_cnt),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rdy_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdy_reg1_reg_0),
        .Q(rdy_reg1),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rdy_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE start_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(DRP_START00_out),
        .Q(start_reg1),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE start_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE x16_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(DRP_X160),
        .Q(x16_reg1),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE x16_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(x16_reg1),
        .Q(x16_reg2),
        .R(rst_dclk_reset));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_gtp_pipe_drp" *) 
module xdma_0_pcie2_ip_gtp_pipe_drp_32
   (done_reg_0,
    \fsm_reg[1]_0 ,
    DRPADDR,
    \fsm_reg[1]_1 ,
    DRPDI,
    rst_dclk_reset,
    DRP_START0,
    CLK,
    rdy_reg1_reg_0,
    DRP_X1602_out,
    D);
  output [0:0]done_reg_0;
  output \fsm_reg[1]_0 ;
  output [0:0]DRPADDR;
  output \fsm_reg[1]_1 ;
  output [15:0]DRPDI;
  input rst_dclk_reset;
  input DRP_START0;
  input CLK;
  input rdy_reg1_reg_0;
  input DRP_X1602_out;
  input [15:0]D;

  wire CLK;
  wire [15:0]D;
  wire [0:0]DRPADDR;
  wire [15:0]DRPDI;
  wire DRP_START0;
  wire DRP_X1602_out;
  wire \addr_reg[4]_i_1__0_n_0 ;
  wire \di_reg[15]_i_1__0_n_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg2;
  wire done_i_1__0_n_0;
  wire [0:0]done_reg_0;
  wire [4:4]drp_addr_9;
  wire [15:0]drp_di_16;
  wire [2:0]fsm;
  wire \fsm[0]_i_2__0_n_0 ;
  wire \fsm[0]_i_3__0_n_0 ;
  wire \fsm_reg[1]_0 ;
  wire \fsm_reg[1]_1 ;
  wire \fsm_reg_n_0_[0] ;
  wire \fsm_reg_n_0_[1] ;
  wire \fsm_reg_n_0_[2] ;
  wire [4:0]index;
  wire \index[4]_i_1__0_n_0 ;
  wire \index[4]_i_3__0_n_0 ;
  wire \index[4]_i_4__0_n_0 ;
  wire load_cnt;
  wire \load_cnt[0]_i_1__0_n_0 ;
  wire [11:11]p_1_in;
  wire [4:0]p_2_in;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg1;
  wire rdy_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg2;
  wire rst_dclk_reset;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire x16_reg2;

  (* SOFT_HLUTNM = "soft_lutpair1813" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \addr_reg[4]_i_1__0 
       (.I0(index[3]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(index[1]),
        .O(\addr_reg[4]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\addr_reg[4]_i_1__0_n_0 ),
        .Q(drp_addr_9),
        .R(rst_dclk_reset));
  LUT1 #(
    .INIT(2'h1)) 
    \di_reg[11]_i_1__0 
       (.I0(x16_reg2),
        .O(p_1_in));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \di_reg[15]_i_1__0 
       (.I0(rst_dclk_reset),
        .I1(index[4]),
        .I2(index[3]),
        .I3(index[1]),
        .I4(index[0]),
        .I5(index[2]),
        .O(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[0]),
        .Q(drp_di_16[0]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[10]),
        .Q(drp_di_16[10]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_1_in),
        .Q(drp_di_16[11]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[12]),
        .Q(drp_di_16[12]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[13]),
        .Q(drp_di_16[13]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[14]),
        .Q(drp_di_16[14]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[15]),
        .Q(drp_di_16[15]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[1]),
        .Q(drp_di_16[1]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[2]),
        .Q(drp_di_16[2]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[3]),
        .Q(drp_di_16[3]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[4]),
        .Q(drp_di_16[4]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[5]),
        .Q(drp_di_16[5]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[6]),
        .Q(drp_di_16[6]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[7]),
        .Q(drp_di_16[7]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[8]),
        .Q(drp_di_16[8]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg2[9]),
        .Q(drp_di_16[9]),
        .R(\di_reg[15]_i_1__0_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(do_reg1[0]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[10]),
        .Q(do_reg1[10]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[11]),
        .Q(do_reg1[11]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[12]),
        .Q(do_reg1[12]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[13]),
        .Q(do_reg1[13]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[14]),
        .Q(do_reg1[14]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[15]),
        .Q(do_reg1[15]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(do_reg1[1]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(do_reg1[2]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(do_reg1[3]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[4]),
        .Q(do_reg1[4]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[5]),
        .Q(do_reg1[5]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[6]),
        .Q(do_reg1[6]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[7]),
        .Q(do_reg1[7]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[8]),
        .Q(do_reg1[8]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[9]),
        .Q(do_reg1[9]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(rst_dclk_reset));
  LUT5 #(
    .INIT(32'hC001CC01)) 
    done_i_1__0
       (.I0(start_reg2),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[1] ),
        .I4(\index[4]_i_4__0_n_0 ),
        .O(done_i_1__0_n_0));
  FDSE #(
    .INIT(1'b0)) 
    done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(done_i_1__0_n_0),
        .Q(done_reg_0),
        .S(rst_dclk_reset));
  LUT6 #(
    .INIT(64'h0B3BFFFF0B3B0000)) 
    \fsm[0]_i_1__0 
       (.I0(\fsm[0]_i_2__0_n_0 ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(rdy_reg2),
        .I4(\fsm_reg_n_0_[2] ),
        .I5(\fsm[0]_i_3__0_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair1811" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \fsm[0]_i_2__0 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[4]),
        .O(\fsm[0]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h47FF47CC)) 
    \fsm[0]_i_3__0 
       (.I0(rdy_reg2),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(load_cnt),
        .I3(\fsm_reg_n_0_[0] ),
        .I4(start_reg2),
        .O(\fsm[0]_i_3__0_n_0 ));
  LUT5 #(
    .INIT(32'h1D501850)) 
    \fsm[1]_i_1__0 
       (.I0(\fsm_reg_n_0_[2] ),
        .I1(rdy_reg2),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[0] ),
        .I4(load_cnt),
        .O(fsm[1]));
  LUT4 #(
    .INIT(16'h6222)) 
    \fsm[2]_i_1__0 
       (.I0(\fsm_reg_n_0_[2] ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(rdy_reg2),
        .I3(\fsm_reg_n_0_[0] ),
        .O(fsm[2]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(\fsm_reg_n_0_[0] ),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(\fsm_reg_n_0_[1] ),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(\fsm_reg_n_0_[2] ),
        .R(rst_dclk_reset));
  (* SOFT_HLUTNM = "soft_lutpair1821" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_10__0 
       (.I0(drp_di_16[11]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[11]));
  (* SOFT_HLUTNM = "soft_lutpair1820" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_11__0 
       (.I0(drp_di_16[10]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[10]));
  (* SOFT_HLUTNM = "soft_lutpair1820" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_12__0 
       (.I0(drp_di_16[9]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[9]));
  (* SOFT_HLUTNM = "soft_lutpair1819" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_13__0 
       (.I0(drp_di_16[8]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[8]));
  (* SOFT_HLUTNM = "soft_lutpair1819" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_14__0 
       (.I0(drp_di_16[7]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[7]));
  (* SOFT_HLUTNM = "soft_lutpair1818" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_15__0 
       (.I0(drp_di_16[6]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[6]));
  (* SOFT_HLUTNM = "soft_lutpair1818" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_16__0 
       (.I0(drp_di_16[5]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[5]));
  (* SOFT_HLUTNM = "soft_lutpair1817" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_17__0 
       (.I0(drp_di_16[4]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[4]));
  (* SOFT_HLUTNM = "soft_lutpair1817" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_18__0 
       (.I0(drp_di_16[3]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[3]));
  (* SOFT_HLUTNM = "soft_lutpair1816" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_19__0 
       (.I0(drp_di_16[2]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[2]));
  (* SOFT_HLUTNM = "soft_lutpair1814" *) 
  LUT3 #(
    .INIT(8'h12)) 
    \gtp_channel.gtpe2_channel_i_i_1__0 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\fsm_reg_n_0_[2] ),
        .O(\fsm_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1816" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_20__0 
       (.I0(drp_di_16[1]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[1]));
  (* SOFT_HLUTNM = "soft_lutpair1815" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_21__0 
       (.I0(drp_di_16[0]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[0]));
  (* SOFT_HLUTNM = "soft_lutpair1815" *) 
  LUT3 #(
    .INIT(8'h10)) 
    \gtp_channel.gtpe2_channel_i_i_2__0 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\fsm_reg_n_0_[2] ),
        .O(\fsm_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1814" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_39 
       (.I0(drp_addr_9),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPADDR));
  (* SOFT_HLUTNM = "soft_lutpair1823" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_6__0 
       (.I0(drp_di_16[15]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[15]));
  (* SOFT_HLUTNM = "soft_lutpair1822" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_7__0 
       (.I0(drp_di_16[14]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[14]));
  (* SOFT_HLUTNM = "soft_lutpair1822" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_8__0 
       (.I0(drp_di_16[13]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[13]));
  (* SOFT_HLUTNM = "soft_lutpair1821" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \gtp_channel.gtpe2_channel_i_i_9__0 
       (.I0(drp_di_16[12]),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_reg_n_0_[2] ),
        .O(DRPDI[12]));
  (* SOFT_HLUTNM = "soft_lutpair1812" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    \index[0]_i_1__0 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\index[4]_i_4__0_n_0 ),
        .I2(index[0]),
        .I3(\fsm_reg_n_0_[2] ),
        .O(p_2_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair1812" *) 
  LUT5 #(
    .INIT(32'h14000000)) 
    \index[1]_i_1__0 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(index[1]),
        .I2(index[0]),
        .I3(\index[4]_i_4__0_n_0 ),
        .I4(\fsm_reg_n_0_[2] ),
        .O(p_2_in[1]));
  LUT6 #(
    .INIT(64'h1444000000000000)) 
    \index[2]_i_1__0 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(index[2]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(\index[4]_i_4__0_n_0 ),
        .I5(\fsm_reg_n_0_[2] ),
        .O(p_2_in[2]));
  LUT5 #(
    .INIT(32'h14000000)) 
    \index[3]_i_1__0 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(index[3]),
        .I2(\index[4]_i_3__0_n_0 ),
        .I3(\index[4]_i_4__0_n_0 ),
        .I4(\fsm_reg_n_0_[2] ),
        .O(p_2_in[3]));
  LUT3 #(
    .INIT(8'hA1)) 
    \index[4]_i_1__0 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\fsm_reg_n_0_[2] ),
        .O(\index[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h1444000000000000)) 
    \index[4]_i_2__0 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(index[4]),
        .I2(index[3]),
        .I3(\index[4]_i_3__0_n_0 ),
        .I4(\index[4]_i_4__0_n_0 ),
        .I5(\fsm_reg_n_0_[2] ),
        .O(p_2_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair1813" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \index[4]_i_3__0 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .O(\index[4]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1811" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \index[4]_i_4__0 
       (.I0(index[3]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[4]),
        .I4(index[2]),
        .O(\index[4]_i_4__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(CLK),
        .CE(\index[4]_i_1__0_n_0 ),
        .D(p_2_in[0]),
        .Q(index[0]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(CLK),
        .CE(\index[4]_i_1__0_n_0 ),
        .D(p_2_in[1]),
        .Q(index[1]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(CLK),
        .CE(\index[4]_i_1__0_n_0 ),
        .D(p_2_in[2]),
        .Q(index[2]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[3] 
       (.C(CLK),
        .CE(\index[4]_i_1__0_n_0 ),
        .D(p_2_in[3]),
        .Q(index[3]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[4] 
       (.C(CLK),
        .CE(\index[4]_i_1__0_n_0 ),
        .D(p_2_in[4]),
        .Q(index[4]),
        .R(rst_dclk_reset));
  (* SOFT_HLUTNM = "soft_lutpair1823" *) 
  LUT3 #(
    .INIT(8'h10)) 
    \load_cnt[0]_i_1__0 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[0] ),
        .O(\load_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1__0_n_0 ),
        .Q(load_cnt),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rdy_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdy_reg1_reg_0),
        .Q(rdy_reg1),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rdy_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE start_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(DRP_START0),
        .Q(start_reg1),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE start_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE x16_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(DRP_X1602_out),
        .Q(x16_reg1),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE x16_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(x16_reg1),
        .Q(x16_reg2),
        .R(rst_dclk_reset));
endmodule

module xdma_0_pcie2_ip_gtp_pipe_rate
   (pclk_sel_reg_0,
    Q,
    DRP_X160,
    DRP_START00_out,
    RXRATE,
    rst_cpllreset,
    drp_done_reg1_reg_0,
    \txdata_wait_cnt_reg[0]_0 ,
    rxpmaresetdone_reg1_reg_0,
    gt_txratedone_0,
    phystatus_reg1_reg_0,
    gt_rxratedone_0,
    txsync_done_reg1_reg_0,
    rst_drp_x16,
    rst_drp_start,
    D);
  output pclk_sel_reg_0;
  output [2:0]Q;
  output DRP_X160;
  output DRP_START00_out;
  output [0:0]RXRATE;
  input rst_cpllreset;
  input [0:0]drp_done_reg1_reg_0;
  input \txdata_wait_cnt_reg[0]_0 ;
  input [0:0]rxpmaresetdone_reg1_reg_0;
  input gt_txratedone_0;
  input [0:0]phystatus_reg1_reg_0;
  input gt_rxratedone_0;
  input [0:0]txsync_done_reg1_reg_0;
  input rst_drp_x16;
  input rst_drp_start;
  input [0:0]D;

  wire [0:0]D;
  wire DRP_START00_out;
  wire DRP_X160;
  wire \FSM_onehot_fsm[0]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[10]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[11]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[12]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[1]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm[5]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[6]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[7]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[8]_i_1_n_0 ;
  wire \FSM_onehot_fsm[8]_i_2_n_0 ;
  wire \FSM_onehot_fsm[9]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm_reg_n_0_[0] ;
  wire \FSM_onehot_fsm_reg_n_0_[11] ;
  wire \FSM_onehot_fsm_reg_n_0_[12] ;
  wire \FSM_onehot_fsm_reg_n_0_[6] ;
  wire \FSM_onehot_fsm_reg_n_0_[8] ;
  wire [2:0]Q;
  wire [0:0]RXRATE;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg1;
  wire [0:0]drp_done_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg2;
  wire gt_rxratedone_0;
  wire gt_txratedone_0;
  wire p_0_in1_in;
  wire [3:0]p_0_in__0;
  wire p_2_in;
  wire p_3_in;
  wire pclk_sel;
  wire pclk_sel_i_1_n_0;
  wire pclk_sel_reg_0;
  wire phystatus_i_1_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg1;
  wire [0:0]phystatus_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg2;
  wire phystatus_reg_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg2;
  wire rate_out;
  wire \rate_out[0]_i_1_n_0 ;
  wire ratedone_i_1_n_0;
  wire ratedone_i_2_n_0;
  wire ratedone_reg_n_0;
  wire rst_cpllreset;
  wire rst_drp_start;
  wire rst_drp_x16;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg1;
  wire [0:0]rxpmaresetdone_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg2;
  wire rxratedone_i_1_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg2;
  wire rxratedone_reg_n_0;
  wire [3:0]txdata_wait_cnt_reg;
  wire \txdata_wait_cnt_reg[0]_0 ;
  wire txratedone_i_1_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg2;
  wire txratedone_reg_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg1;
  wire [0:0]txsync_done_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg2;

  LUT3 #(
    .INIT(8'hEA)) 
    \FSM_onehot_fsm[0]_i_1__0 
       (.I0(pclk_sel),
        .I1(drp_done_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[0] ),
        .O(\FSM_onehot_fsm[0]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h54)) 
    \FSM_onehot_fsm[10]_i_1__0 
       (.I0(drp_done_reg2),
        .I1(p_3_in),
        .I2(p_2_in),
        .O(\FSM_onehot_fsm[10]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \FSM_onehot_fsm[11]_i_1__0 
       (.I0(ratedone_reg_n_0),
        .I1(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I2(p_3_in),
        .I3(drp_done_reg2),
        .O(\FSM_onehot_fsm[11]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hEA)) 
    \FSM_onehot_fsm[12]_i_1__0 
       (.I0(rate_out),
        .I1(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I2(rxpmaresetdone_reg2),
        .O(\FSM_onehot_fsm[12]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h54)) 
    \FSM_onehot_fsm[1]_i_1__2 
       (.I0(drp_done_reg2),
        .I1(p_0_in1_in),
        .I2(\FSM_onehot_fsm_reg_n_0_[0] ),
        .O(\FSM_onehot_fsm[1]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_fsm[2]_i_1__0 
       (.I0(p_0_in1_in),
        .I1(drp_done_reg2),
        .O(\FSM_onehot_fsm[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1778" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \FSM_onehot_fsm[3]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I1(txdata_wait_cnt_reg[1]),
        .I2(txdata_wait_cnt_reg[0]),
        .I3(txdata_wait_cnt_reg[2]),
        .I4(txdata_wait_cnt_reg[3]),
        .O(\FSM_onehot_fsm[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEBAAAAEBAAAAAAAA)) 
    \FSM_onehot_fsm[4]_i_1__2 
       (.I0(Q[1]),
        .I1(rate_in_reg1[1]),
        .I2(rate_in_reg2[1]),
        .I3(rate_in_reg1[0]),
        .I4(rate_in_reg2[0]),
        .I5(Q[0]),
        .O(\FSM_onehot_fsm[4]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_fsm[5]_i_1__0 
       (.I0(txsync_done_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm[5]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h0E)) 
    \FSM_onehot_fsm[6]_i_1__0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[6] ),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .O(\FSM_onehot_fsm[6]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \FSM_onehot_fsm[7]_i_1__0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I1(ratedone_reg_n_0),
        .I2(Q[2]),
        .I3(txsync_done_reg2),
        .O(\FSM_onehot_fsm[7]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hBEFFFFBEAAAAAAAA)) 
    \FSM_onehot_fsm[8]_i_1 
       (.I0(\FSM_onehot_fsm[8]_i_2_n_0 ),
        .I1(rate_in_reg1[1]),
        .I2(rate_in_reg2[1]),
        .I3(rate_in_reg1[0]),
        .I4(rate_in_reg2[0]),
        .I5(Q[0]),
        .O(\FSM_onehot_fsm[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1776" *) 
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    \FSM_onehot_fsm[8]_i_2 
       (.I0(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I1(txdata_wait_cnt_reg[1]),
        .I2(txdata_wait_cnt_reg[0]),
        .I3(txdata_wait_cnt_reg[2]),
        .I4(txdata_wait_cnt_reg[3]),
        .O(\FSM_onehot_fsm[8]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \FSM_onehot_fsm[9]_i_1__0 
       (.I0(rxpmaresetdone_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I2(drp_done_reg2),
        .I3(p_2_in),
        .O(\FSM_onehot_fsm[9]_i_1__0_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[0]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[10] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[10]_i_1__0_n_0 ),
        .Q(p_3_in),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[11] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[11]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[11] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[12] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[12]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[12] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__2_n_0 ),
        .Q(p_0_in1_in),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__0_n_0 ),
        .Q(rate_out),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1_n_0 ),
        .Q(pclk_sel),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__2_n_0 ),
        .Q(Q[0]),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[5] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[5]_i_1__0_n_0 ),
        .Q(Q[1]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[6] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[6]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[6] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[7] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[7]_i_1__0_n_0 ),
        .Q(Q[2]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[8] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[8]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[8] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[9] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[9]_i_1__0_n_0 ),
        .Q(p_2_in),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE drp_done_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(drp_done_reg1_reg_0),
        .Q(drp_done_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE drp_done_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(drp_done_reg1),
        .Q(drp_done_reg2),
        .R(rst_cpllreset));
  LUT4 #(
    .INIT(16'h2F20)) 
    pclk_sel_i_1
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(pclk_sel),
        .I3(pclk_sel_reg_0),
        .O(pclk_sel_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(pclk_sel_i_1_n_0),
        .Q(pclk_sel_reg_0),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'hFFFFFFFCAAAAAAA8)) 
    phystatus_i_1
       (.I0(phystatus_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I3(p_2_in),
        .I4(p_3_in),
        .I5(phystatus_reg_n_0),
        .O(phystatus_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    phystatus_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(phystatus_i_1_n_0),
        .Q(phystatus_reg_n_0),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE phystatus_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(phystatus_reg1_reg_0),
        .Q(phystatus_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE phystatus_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(phystatus_reg1),
        .Q(phystatus_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_in_reg1_reg[0] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(D),
        .Q(rate_in_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_in_reg1_reg[1] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_in_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_in_reg2_reg[0] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rate_in_reg1[0]),
        .Q(rate_in_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_in_reg2_reg[1] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rate_in_reg1[1]),
        .Q(rate_in_reg2[1]),
        .R(rst_cpllreset));
  LUT4 #(
    .INIT(16'h2F20)) 
    \rate_out[0]_i_1 
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(rate_out),
        .I3(RXRATE),
        .O(\rate_out[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[0] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\rate_out[0]_i_1_n_0 ),
        .Q(RXRATE),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h55554000)) 
    ratedone_i_1
       (.I0(ratedone_i_2_n_0),
        .I1(txratedone_reg_n_0),
        .I2(phystatus_reg_n_0),
        .I3(rxratedone_reg_n_0),
        .I4(ratedone_reg_n_0),
        .O(ratedone_i_1_n_0));
  LUT4 #(
    .INIT(16'h0001)) 
    ratedone_i_2
       (.I0(p_3_in),
        .I1(p_2_in),
        .I2(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[12] ),
        .O(ratedone_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ratedone_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(ratedone_i_1_n_0),
        .Q(ratedone_reg_n_0),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxpmaresetdone_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1_reg_0),
        .Q(rxpmaresetdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxpmaresetdone_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1),
        .Q(rxpmaresetdone_reg2),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'hFFFFFFFCAAAAAAA8)) 
    rxratedone_i_1
       (.I0(rxratedone_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I3(p_2_in),
        .I4(p_3_in),
        .I5(rxratedone_reg_n_0),
        .O(rxratedone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxratedone_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rxratedone_i_1_n_0),
        .Q(rxratedone_reg_n_0),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxratedone_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(gt_rxratedone_0),
        .Q(rxratedone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxratedone_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rxratedone_reg1),
        .Q(rxratedone_reg2),
        .R(rst_cpllreset));
  (* SOFT_HLUTNM = "soft_lutpair1779" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    start_reg1_i_1
       (.I0(rst_drp_start),
        .I1(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I2(p_2_in),
        .O(DRP_START00_out));
  (* SOFT_HLUTNM = "soft_lutpair1777" *) 
  LUT5 #(
    .INIT(32'h80AA00AA)) 
    \txdata_wait_cnt[0]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I1(txdata_wait_cnt_reg[3]),
        .I2(txdata_wait_cnt_reg[2]),
        .I3(txdata_wait_cnt_reg[0]),
        .I4(txdata_wait_cnt_reg[1]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1777" *) 
  LUT5 #(
    .INIT(32'hE0606060)) 
    \txdata_wait_cnt[1]_i_1 
       (.I0(txdata_wait_cnt_reg[0]),
        .I1(txdata_wait_cnt_reg[1]),
        .I2(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I3(txdata_wait_cnt_reg[2]),
        .I4(txdata_wait_cnt_reg[3]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1776" *) 
  LUT5 #(
    .INIT(32'hEA006A00)) 
    \txdata_wait_cnt[2]_i_1 
       (.I0(txdata_wait_cnt_reg[2]),
        .I1(txdata_wait_cnt_reg[1]),
        .I2(txdata_wait_cnt_reg[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I4(txdata_wait_cnt_reg[3]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1778" *) 
  LUT5 #(
    .INIT(32'hA8888888)) 
    \txdata_wait_cnt[3]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I1(txdata_wait_cnt_reg[3]),
        .I2(txdata_wait_cnt_reg[1]),
        .I3(txdata_wait_cnt_reg[0]),
        .I4(txdata_wait_cnt_reg[2]),
        .O(p_0_in__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[0] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(txdata_wait_cnt_reg[0]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[1] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(txdata_wait_cnt_reg[1]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[2] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(txdata_wait_cnt_reg[2]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[3] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(txdata_wait_cnt_reg[3]),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'hFFFFFFFCAAAAAAA8)) 
    txratedone_i_1
       (.I0(txratedone_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I3(p_2_in),
        .I4(p_3_in),
        .I5(txratedone_reg_n_0),
        .O(txratedone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txratedone_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(txratedone_i_1_n_0),
        .Q(txratedone_reg_n_0),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txratedone_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(gt_txratedone_0),
        .Q(txratedone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txratedone_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(txratedone_reg1),
        .Q(txratedone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsync_done_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(txsync_done_reg1_reg_0),
        .Q(txsync_done_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsync_done_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(txsync_done_reg1),
        .Q(txsync_done_reg2),
        .R(rst_cpllreset));
  (* SOFT_HLUTNM = "soft_lutpair1779" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    x16_reg1_i_1
       (.I0(rst_drp_x16),
        .I1(p_0_in1_in),
        .I2(\FSM_onehot_fsm_reg_n_0_[0] ),
        .O(DRP_X160));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_gtp_pipe_rate" *) 
module xdma_0_pcie2_ip_gtp_pipe_rate_33
   (pclk_sel_reg_0,
    Q,
    DRP_X1602_out,
    DRP_START0,
    RXRATE,
    rst_cpllreset,
    drp_done_reg1_reg_0,
    \txdata_wait_cnt_reg[0]_0 ,
    rxpmaresetdone_reg1_reg_0,
    gt_txratedone_1,
    phystatus_reg1_reg_0,
    gt_rxratedone_1,
    txsync_done_reg1_reg_0,
    rst_drp_x16,
    rst_drp_start,
    D);
  output pclk_sel_reg_0;
  output [2:0]Q;
  output DRP_X1602_out;
  output DRP_START0;
  output [0:0]RXRATE;
  input rst_cpllreset;
  input [0:0]drp_done_reg1_reg_0;
  input \txdata_wait_cnt_reg[0]_0 ;
  input [0:0]rxpmaresetdone_reg1_reg_0;
  input gt_txratedone_1;
  input [0:0]phystatus_reg1_reg_0;
  input gt_rxratedone_1;
  input [0:0]txsync_done_reg1_reg_0;
  input rst_drp_x16;
  input rst_drp_start;
  input [0:0]D;

  wire [0:0]D;
  wire DRP_START0;
  wire DRP_X1602_out;
  wire \FSM_onehot_fsm[0]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[10]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[11]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[12]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[1]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm[5]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[6]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[7]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[8]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[8]_i_2__0_n_0 ;
  wire \FSM_onehot_fsm[9]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm_reg_n_0_[0] ;
  wire \FSM_onehot_fsm_reg_n_0_[11] ;
  wire \FSM_onehot_fsm_reg_n_0_[12] ;
  wire \FSM_onehot_fsm_reg_n_0_[6] ;
  wire \FSM_onehot_fsm_reg_n_0_[8] ;
  wire [2:0]Q;
  wire [0:0]RXRATE;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg1;
  wire [0:0]drp_done_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg2;
  wire gt_rxratedone_1;
  wire gt_txratedone_1;
  wire p_0_in1_in;
  wire [3:0]p_0_in__3;
  wire p_2_in;
  wire p_3_in;
  wire pclk_sel;
  wire pclk_sel_i_1__0_n_0;
  wire pclk_sel_reg_0;
  wire phystatus_i_1__0_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg1;
  wire [0:0]phystatus_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire phystatus_reg2;
  wire phystatus_reg_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_in_reg2;
  wire rate_out;
  wire \rate_out[0]_i_1__0_n_0 ;
  wire ratedone_i_1__0_n_0;
  wire ratedone_i_2__0_n_0;
  wire ratedone_reg_n_0;
  wire rst_cpllreset;
  wire rst_drp_start;
  wire rst_drp_x16;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg1;
  wire [0:0]rxpmaresetdone_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxpmaresetdone_reg2;
  wire rxratedone_i_1__0_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxratedone_reg2;
  wire rxratedone_reg_n_0;
  wire [3:0]txdata_wait_cnt_reg;
  wire \txdata_wait_cnt_reg[0]_0 ;
  wire txratedone_i_1__0_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txratedone_reg2;
  wire txratedone_reg_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg1;
  wire [0:0]txsync_done_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_done_reg2;

  LUT3 #(
    .INIT(8'hEA)) 
    \FSM_onehot_fsm[0]_i_1__1 
       (.I0(pclk_sel),
        .I1(drp_done_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[0] ),
        .O(\FSM_onehot_fsm[0]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h54)) 
    \FSM_onehot_fsm[10]_i_1__1 
       (.I0(drp_done_reg2),
        .I1(p_3_in),
        .I2(p_2_in),
        .O(\FSM_onehot_fsm[10]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \FSM_onehot_fsm[11]_i_1__1 
       (.I0(ratedone_reg_n_0),
        .I1(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I2(p_3_in),
        .I3(drp_done_reg2),
        .O(\FSM_onehot_fsm[11]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hEA)) 
    \FSM_onehot_fsm[12]_i_1__1 
       (.I0(rate_out),
        .I1(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I2(rxpmaresetdone_reg2),
        .O(\FSM_onehot_fsm[12]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h54)) 
    \FSM_onehot_fsm[1]_i_1__3 
       (.I0(drp_done_reg2),
        .I1(p_0_in1_in),
        .I2(\FSM_onehot_fsm_reg_n_0_[0] ),
        .O(\FSM_onehot_fsm[1]_i_1__3_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_fsm[2]_i_1__2 
       (.I0(p_0_in1_in),
        .I1(drp_done_reg2),
        .O(\FSM_onehot_fsm[2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1826" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \FSM_onehot_fsm[3]_i_1__0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I1(txdata_wait_cnt_reg[1]),
        .I2(txdata_wait_cnt_reg[0]),
        .I3(txdata_wait_cnt_reg[2]),
        .I4(txdata_wait_cnt_reg[3]),
        .O(\FSM_onehot_fsm[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hEBAAAAEBAAAAAAAA)) 
    \FSM_onehot_fsm[4]_i_1__3 
       (.I0(Q[1]),
        .I1(rate_in_reg1[1]),
        .I2(rate_in_reg2[1]),
        .I3(rate_in_reg1[0]),
        .I4(rate_in_reg2[0]),
        .I5(Q[0]),
        .O(\FSM_onehot_fsm[4]_i_1__3_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_fsm[5]_i_1__1 
       (.I0(txsync_done_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm[5]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h0E)) 
    \FSM_onehot_fsm[6]_i_1__1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[6] ),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .O(\FSM_onehot_fsm[6]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \FSM_onehot_fsm[7]_i_1__1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I1(ratedone_reg_n_0),
        .I2(Q[2]),
        .I3(txsync_done_reg2),
        .O(\FSM_onehot_fsm[7]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hBEFFFFBEAAAAAAAA)) 
    \FSM_onehot_fsm[8]_i_1__0 
       (.I0(\FSM_onehot_fsm[8]_i_2__0_n_0 ),
        .I1(rate_in_reg1[1]),
        .I2(rate_in_reg2[1]),
        .I3(rate_in_reg1[0]),
        .I4(rate_in_reg2[0]),
        .I5(Q[0]),
        .O(\FSM_onehot_fsm[8]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1824" *) 
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    \FSM_onehot_fsm[8]_i_2__0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I1(txdata_wait_cnt_reg[1]),
        .I2(txdata_wait_cnt_reg[0]),
        .I3(txdata_wait_cnt_reg[2]),
        .I4(txdata_wait_cnt_reg[3]),
        .O(\FSM_onehot_fsm[8]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \FSM_onehot_fsm[9]_i_1__1 
       (.I0(rxpmaresetdone_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I2(drp_done_reg2),
        .I3(p_2_in),
        .O(\FSM_onehot_fsm[9]_i_1__1_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[0]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[10] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[10]_i_1__1_n_0 ),
        .Q(p_3_in),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[11] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[11]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[11] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[12] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[12]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[12] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__3_n_0 ),
        .Q(p_0_in1_in),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__2_n_0 ),
        .Q(rate_out),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__0_n_0 ),
        .Q(pclk_sel),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__3_n_0 ),
        .Q(Q[0]),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[5] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[5]_i_1__1_n_0 ),
        .Q(Q[1]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[6] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[6]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[6] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[7] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[7]_i_1__1_n_0 ),
        .Q(Q[2]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[8] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[8]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[8] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_DRP_X16_DONE:0000000000010,FSM_DRP_X16_START:0000000000001,FSM_PCLK_SEL:0000000001000,FSM_TXSYNC_DONE:0000001000000,FSM_DONE:0000000100000,FSM_TXSYNC_START:0000010000000,FSM_TXDATA_WAIT:0000100000000,FSM_IDLE:0000000010000,FSM_RATE_DONE:0100000000000,FSM_DRP_X20_START:0001000000000,FSM_DRP_X20_DONE:0010000000000,FSM_RXPMARESETDONE:1000000000000,FSM_RATE_SEL:0000000000100" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[9] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[9]_i_1__1_n_0 ),
        .Q(p_2_in),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE drp_done_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(drp_done_reg1_reg_0),
        .Q(drp_done_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE drp_done_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(drp_done_reg1),
        .Q(drp_done_reg2),
        .R(rst_cpllreset));
  LUT4 #(
    .INIT(16'h2F20)) 
    pclk_sel_i_1__0
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(pclk_sel),
        .I3(pclk_sel_reg_0),
        .O(pclk_sel_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(pclk_sel_i_1__0_n_0),
        .Q(pclk_sel_reg_0),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'hFFFFFFFCAAAAAAA8)) 
    phystatus_i_1__0
       (.I0(phystatus_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I3(p_2_in),
        .I4(p_3_in),
        .I5(phystatus_reg_n_0),
        .O(phystatus_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    phystatus_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(phystatus_i_1__0_n_0),
        .Q(phystatus_reg_n_0),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE phystatus_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(phystatus_reg1_reg_0),
        .Q(phystatus_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE phystatus_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(phystatus_reg1),
        .Q(phystatus_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_in_reg1_reg[0] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(D),
        .Q(rate_in_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_in_reg1_reg[1] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_in_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_in_reg2_reg[0] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rate_in_reg1[0]),
        .Q(rate_in_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_in_reg2_reg[1] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rate_in_reg1[1]),
        .Q(rate_in_reg2[1]),
        .R(rst_cpllreset));
  LUT4 #(
    .INIT(16'h2F20)) 
    \rate_out[0]_i_1__0 
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(rate_out),
        .I3(RXRATE),
        .O(\rate_out[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[0] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(\rate_out[0]_i_1__0_n_0 ),
        .Q(RXRATE),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h55554000)) 
    ratedone_i_1__0
       (.I0(ratedone_i_2__0_n_0),
        .I1(txratedone_reg_n_0),
        .I2(phystatus_reg_n_0),
        .I3(rxratedone_reg_n_0),
        .I4(ratedone_reg_n_0),
        .O(ratedone_i_1__0_n_0));
  LUT4 #(
    .INIT(16'h0001)) 
    ratedone_i_2__0
       (.I0(p_3_in),
        .I1(p_2_in),
        .I2(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[12] ),
        .O(ratedone_i_2__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ratedone_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(ratedone_i_1__0_n_0),
        .Q(ratedone_reg_n_0),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxpmaresetdone_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1_reg_0),
        .Q(rxpmaresetdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxpmaresetdone_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1),
        .Q(rxpmaresetdone_reg2),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'hFFFFFFFCAAAAAAA8)) 
    rxratedone_i_1__0
       (.I0(rxratedone_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I3(p_2_in),
        .I4(p_3_in),
        .I5(rxratedone_reg_n_0),
        .O(rxratedone_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxratedone_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rxratedone_i_1__0_n_0),
        .Q(rxratedone_reg_n_0),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxratedone_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(gt_rxratedone_1),
        .Q(rxratedone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxratedone_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(rxratedone_reg1),
        .Q(rxratedone_reg2),
        .R(rst_cpllreset));
  (* SOFT_HLUTNM = "soft_lutpair1827" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    start_reg1_i_1__0
       (.I0(rst_drp_start),
        .I1(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I2(p_2_in),
        .O(DRP_START0));
  (* SOFT_HLUTNM = "soft_lutpair1825" *) 
  LUT5 #(
    .INIT(32'h80AA00AA)) 
    \txdata_wait_cnt[0]_i_1__0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I1(txdata_wait_cnt_reg[3]),
        .I2(txdata_wait_cnt_reg[2]),
        .I3(txdata_wait_cnt_reg[0]),
        .I4(txdata_wait_cnt_reg[1]),
        .O(p_0_in__3[0]));
  (* SOFT_HLUTNM = "soft_lutpair1825" *) 
  LUT5 #(
    .INIT(32'hE0606060)) 
    \txdata_wait_cnt[1]_i_1__0 
       (.I0(txdata_wait_cnt_reg[0]),
        .I1(txdata_wait_cnt_reg[1]),
        .I2(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I3(txdata_wait_cnt_reg[2]),
        .I4(txdata_wait_cnt_reg[3]),
        .O(p_0_in__3[1]));
  (* SOFT_HLUTNM = "soft_lutpair1824" *) 
  LUT5 #(
    .INIT(32'hEA006A00)) 
    \txdata_wait_cnt[2]_i_1__0 
       (.I0(txdata_wait_cnt_reg[2]),
        .I1(txdata_wait_cnt_reg[1]),
        .I2(txdata_wait_cnt_reg[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I4(txdata_wait_cnt_reg[3]),
        .O(p_0_in__3[2]));
  (* SOFT_HLUTNM = "soft_lutpair1826" *) 
  LUT5 #(
    .INIT(32'hA8888888)) 
    \txdata_wait_cnt[3]_i_1__0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I1(txdata_wait_cnt_reg[3]),
        .I2(txdata_wait_cnt_reg[1]),
        .I3(txdata_wait_cnt_reg[0]),
        .I4(txdata_wait_cnt_reg[2]),
        .O(p_0_in__3[3]));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[0] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(p_0_in__3[0]),
        .Q(txdata_wait_cnt_reg[0]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[1] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(p_0_in__3[1]),
        .Q(txdata_wait_cnt_reg[1]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[2] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(p_0_in__3[2]),
        .Q(txdata_wait_cnt_reg[2]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[3] 
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(p_0_in__3[3]),
        .Q(txdata_wait_cnt_reg[3]),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'hFFFFFFFCAAAAAAA8)) 
    txratedone_i_1__0
       (.I0(txratedone_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[11] ),
        .I3(p_2_in),
        .I4(p_3_in),
        .I5(txratedone_reg_n_0),
        .O(txratedone_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txratedone_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(txratedone_i_1__0_n_0),
        .Q(txratedone_reg_n_0),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txratedone_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(gt_txratedone_1),
        .Q(txratedone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txratedone_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(txratedone_reg1),
        .Q(txratedone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsync_done_reg1_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(txsync_done_reg1_reg_0),
        .Q(txsync_done_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsync_done_reg2_reg
       (.C(\txdata_wait_cnt_reg[0]_0 ),
        .CE(1'b1),
        .D(txsync_done_reg1),
        .Q(txsync_done_reg2),
        .R(rst_cpllreset));
  (* SOFT_HLUTNM = "soft_lutpair1827" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    x16_reg1_i_1__0
       (.I0(rst_drp_x16),
        .I1(p_0_in1_in),
        .I2(\FSM_onehot_fsm_reg_n_0_[0] ),
        .O(DRP_X1602_out));
endmodule

module xdma_0_pcie2_ip_gtp_pipe_reset
   (SR,
    rst_drp_start,
    rst_drp_x16,
    rst_cpllreset,
    rxusrclk_rst_reg2_reg_0,
    rst_dclk_reset,
    rst_gtreset,
    rst_userrdy,
    PLL0RESET0,
    SYNC_TXSYNC_START,
    \FSM_onehot_fsm_reg[11]_0 ,
    \FSM_onehot_fsm_reg[1]_0 ,
    SYNC_MMCM_LOCK,
    \cfg_wait_cnt_reg[5]_0 ,
    QRST_QPLLLOCK,
    CLK,
    out,
    cpllrst,
    Q,
    txsync_start_reg1_reg,
    D,
    \drp_done_reg1_reg[1]_0 ,
    \rxpmaresetdone_reg1_reg[1]_0 ,
    \phystatus_reg1_reg[1]_0 ,
    \txsync_done_reg1_reg[1]_0 ,
    \rxcdrlock_reg1_reg[1]_0 );
  output [0:0]SR;
  output rst_drp_start;
  output rst_drp_x16;
  output rst_cpllreset;
  output [0:0]rxusrclk_rst_reg2_reg_0;
  output rst_dclk_reset;
  output rst_gtreset;
  output rst_userrdy;
  output PLL0RESET0;
  output SYNC_TXSYNC_START;
  output \FSM_onehot_fsm_reg[11]_0 ;
  output [0:0]\FSM_onehot_fsm_reg[1]_0 ;
  input SYNC_MMCM_LOCK;
  input \cfg_wait_cnt_reg[5]_0 ;
  input [0:0]QRST_QPLLLOCK;
  input CLK;
  input out;
  input cpllrst;
  input [1:0]Q;
  input [1:0]txsync_start_reg1_reg;
  input [1:0]D;
  input [1:0]\drp_done_reg1_reg[1]_0 ;
  input [1:0]\rxpmaresetdone_reg1_reg[1]_0 ;
  input [1:0]\phystatus_reg1_reg[1]_0 ;
  input [1:0]\txsync_done_reg1_reg[1]_0 ;
  input [1:0]\rxcdrlock_reg1_reg[1]_0 ;

  wire CLK;
  wire [1:0]D;
  wire \FSM_onehot_fsm[0]_i_1_n_0 ;
  wire \FSM_onehot_fsm[10]_i_1_n_0 ;
  wire \FSM_onehot_fsm[11]_i_1_n_0 ;
  wire \FSM_onehot_fsm[12]_i_1_n_0 ;
  wire \FSM_onehot_fsm[12]_i_2_n_0 ;
  wire \FSM_onehot_fsm[13]_i_1_n_0 ;
  wire \FSM_onehot_fsm[13]_i_2_n_0 ;
  wire \FSM_onehot_fsm[14]_i_2_n_0 ;
  wire \FSM_onehot_fsm[1]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[5]_i_1_n_0 ;
  wire \FSM_onehot_fsm[6]_i_1_n_0 ;
  wire \FSM_onehot_fsm[7]_i_1_n_0 ;
  wire \FSM_onehot_fsm[8]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[9]_i_1_n_0 ;
  wire \FSM_onehot_fsm[9]_i_2_n_0 ;
  wire \FSM_onehot_fsm_reg[11]_0 ;
  wire [0:0]\FSM_onehot_fsm_reg[1]_0 ;
  wire \FSM_onehot_fsm_reg_n_0_[10] ;
  wire \FSM_onehot_fsm_reg_n_0_[12] ;
  wire \FSM_onehot_fsm_reg_n_0_[13] ;
  wire \FSM_onehot_fsm_reg_n_0_[2] ;
  wire \FSM_onehot_fsm_reg_n_0_[3] ;
  wire \FSM_onehot_fsm_reg_n_0_[5] ;
  wire \FSM_onehot_fsm_reg_n_0_[6] ;
  wire \FSM_onehot_fsm_reg_n_0_[7] ;
  wire \FSM_onehot_fsm_reg_n_0_[8] ;
  wire \FSM_onehot_fsm_reg_n_0_[9] ;
  wire PLL0RESET0;
  wire [1:0]Q;
  wire [0:0]QRST_QPLLLOCK;
  wire RST_DRP_START0;
  wire RST_DRP_X160;
  wire [0:0]SR;
  wire SYNC_MMCM_LOCK;
  wire SYNC_TXSYNC_START;
  wire \cfg_wait_cnt[5]_i_2_n_0 ;
  wire [5:0]cfg_wait_cnt_reg;
  wire \cfg_wait_cnt_reg[5]_0 ;
  wire cpllrst;
  wire dclk_rst_reg1;
  wire dclk_rst_reg1__0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]drp_done_reg1;
  wire [1:0]\drp_done_reg1_reg[1]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]drp_done_reg2;
  wire gtreset_i_1_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2;
  wire out;
  wire [5:0]p_0_in;
  wire p_0_in0_in;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]phystatus_reg1;
  wire [1:0]\phystatus_reg1_reg[1]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]phystatus_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire plllock_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire plllock_reg2;
  wire pllreset_i_1_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_idle_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_idle_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]resetdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]resetdone_reg2;
  wire rst_cpllreset;
  wire rst_dclk_reset;
  wire rst_drp_start;
  wire rst_drp_x16;
  wire rst_gtreset;
  wire rst_txsync_start;
  wire rst_userrdy;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxcdrlock_reg1;
  wire [1:0]\rxcdrlock_reg1_reg[1]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxcdrlock_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxpmaresetdone_reg1;
  wire [1:0]\rxpmaresetdone_reg1_reg[1]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxpmaresetdone_reg2;
  wire rxusrclk_rst_reg1;
  wire [0:0]rxusrclk_rst_reg2_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txsync_done_reg1;
  wire [1:0]\txsync_done_reg1_reg[1]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txsync_done_reg2;
  wire [1:0]txsync_start_reg1_reg;
  wire userrdy;
  wire userrdy_i_1_n_0;

  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_fsm[0]_i_1 
       (.I0(dclk_rst_reg1),
        .I1(\FSM_onehot_fsm[12]_i_2_n_0 ),
        .O(\FSM_onehot_fsm[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2B2A)) 
    \FSM_onehot_fsm[10]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[10] ),
        .I1(drp_done_reg2[1]),
        .I2(drp_done_reg2[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[9] ),
        .O(\FSM_onehot_fsm[10]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF88888)) 
    \FSM_onehot_fsm[11]_i_1 
       (.I0(\FSM_onehot_fsm[13]_i_2_n_0 ),
        .I1(\FSM_onehot_fsm_reg_n_0_[13] ),
        .I2(txsync_done_reg2[1]),
        .I3(txsync_done_reg2[0]),
        .I4(rst_txsync_start),
        .O(\FSM_onehot_fsm[11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFF444444444)) 
    \FSM_onehot_fsm[12]_i_1 
       (.I0(\FSM_onehot_fsm[12]_i_2_n_0 ),
        .I1(dclk_rst_reg1),
        .I2(resetdone_reg2[0]),
        .I3(resetdone_reg2[1]),
        .I4(plllock_reg2),
        .I5(\FSM_onehot_fsm_reg_n_0_[12] ),
        .O(\FSM_onehot_fsm[12]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[12]_i_2 
       (.I0(cfg_wait_cnt_reg[4]),
        .I1(cfg_wait_cnt_reg[3]),
        .I2(cfg_wait_cnt_reg[5]),
        .I3(cfg_wait_cnt_reg[0]),
        .I4(cfg_wait_cnt_reg[1]),
        .I5(cfg_wait_cnt_reg[2]),
        .O(\FSM_onehot_fsm[12]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F88)) 
    \FSM_onehot_fsm[13]_i_1 
       (.I0(userrdy),
        .I1(mmcm_lock_reg2),
        .I2(\FSM_onehot_fsm[13]_i_2_n_0 ),
        .I3(\FSM_onehot_fsm_reg_n_0_[13] ),
        .O(\FSM_onehot_fsm[13]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \FSM_onehot_fsm[13]_i_2 
       (.I0(phystatus_reg2[1]),
        .I1(resetdone_reg2[1]),
        .I2(resetdone_reg2[0]),
        .I3(phystatus_reg2[0]),
        .O(\FSM_onehot_fsm[13]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \FSM_onehot_fsm[14]_i_1 
       (.I0(out),
        .O(SR));
  LUT5 #(
    .INIT(32'hF4444444)) 
    \FSM_onehot_fsm[14]_i_2 
       (.I0(mmcm_lock_reg2),
        .I1(userrdy),
        .I2(drp_done_reg2[1]),
        .I3(drp_done_reg2[0]),
        .I4(\FSM_onehot_fsm_reg_n_0_[5] ),
        .O(\FSM_onehot_fsm[14]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hEAAA)) 
    \FSM_onehot_fsm[1]_i_1__1 
       (.I0(\FSM_onehot_fsm_reg[1]_0 ),
        .I1(txsync_done_reg2[1]),
        .I2(txsync_done_reg2[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[7] ),
        .O(\FSM_onehot_fsm[1]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hBFAA)) 
    \FSM_onehot_fsm[2]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[6] ),
        .I1(rxpmaresetdone_reg2[1]),
        .I2(rxpmaresetdone_reg2[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hE8A8)) 
    \FSM_onehot_fsm[3]_i_1__1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I1(rxpmaresetdone_reg2[1]),
        .I2(rxpmaresetdone_reg2[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hE0E0E0FFE0E0E0E0)) 
    \FSM_onehot_fsm[4]_i_1__1 
       (.I0(drp_done_reg2[1]),
        .I1(drp_done_reg2[0]),
        .I2(p_0_in0_in),
        .I3(rxpmaresetdone_reg2[1]),
        .I4(rxpmaresetdone_reg2[0]),
        .I5(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[4]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2B2A)) 
    \FSM_onehot_fsm[5]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[5] ),
        .I1(drp_done_reg2[1]),
        .I2(drp_done_reg2[0]),
        .I3(p_0_in0_in),
        .O(\FSM_onehot_fsm[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_fsm[6]_i_1 
       (.I0(plllock_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[8] ),
        .O(\FSM_onehot_fsm[6]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h3F02)) 
    \FSM_onehot_fsm[7]_i_1 
       (.I0(rst_txsync_start),
        .I1(txsync_done_reg2[1]),
        .I2(txsync_done_reg2[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[7] ),
        .O(\FSM_onehot_fsm[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h80FF8080)) 
    \FSM_onehot_fsm[8]_i_1__1 
       (.I0(drp_done_reg2[1]),
        .I1(drp_done_reg2[0]),
        .I2(\FSM_onehot_fsm_reg_n_0_[10] ),
        .I3(plllock_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[8] ),
        .O(\FSM_onehot_fsm[8]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0100FFFF01000100)) 
    \FSM_onehot_fsm[9]_i_1 
       (.I0(resetdone_reg2[0]),
        .I1(resetdone_reg2[1]),
        .I2(plllock_reg2),
        .I3(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I4(\FSM_onehot_fsm[9]_i_2_n_0 ),
        .I5(\FSM_onehot_fsm_reg_n_0_[9] ),
        .O(\FSM_onehot_fsm[9]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_onehot_fsm[9]_i_2 
       (.I0(drp_done_reg2[1]),
        .I1(drp_done_reg2[0]),
        .O(\FSM_onehot_fsm[9]_i_2_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[0]_i_1_n_0 ),
        .Q(dclk_rst_reg1),
        .S(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[10] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[10]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[10] ),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[11] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[11]_i_1_n_0 ),
        .Q(rst_txsync_start),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[12] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[12]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[12] ),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[13] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[13]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[13] ),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[14] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[14]_i_2_n_0 ),
        .Q(userrdy),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg[1]_0 ),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[2] ),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__1_n_0 ),
        .Q(p_0_in0_in),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[5] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[5]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[5] ),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[6] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[6]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[6] ),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[7] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[7]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[7] ),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[8] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[8]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[8] ),
        .R(SR));
  (* FSM_ENCODED_STATES = "FSM_IDLE:000000000000010,FSM_DRP_X20_START:000000000010000,FSM_RXPMARESETDONE_1:000000000000100,FSM_RXPMARESETDONE_2:000000000001000,FSM_GTRESET:000000001000000,FSM_TXSYNC_DONE:000000010000000,FSM_PLLLOCK:000000100000000,FSM_DRP_X16_START:000001000000000,FSM_DRP_X16_DONE:000010000000000,FSM_TXSYNC_START:000100000000000,FSM_PLLRESET:001000000000000,FSM_MMCM_LOCK:100000000000000,FSM_RESETDONE:010000000000000,FSM_DRP_X20_DONE:000000000100000,FSM_CFG_WAIT:000000000000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[9] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[9]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[9] ),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair1760" *) 
  LUT2 #(
    .INIT(4'hE)) 
    RST_DRP_START_i_1
       (.I0(p_0_in0_in),
        .I1(\FSM_onehot_fsm_reg_n_0_[9] ),
        .O(RST_DRP_START0));
  FDRE RST_DRP_START_reg
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(RST_DRP_START0),
        .Q(rst_drp_start),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair1760" *) 
  LUT2 #(
    .INIT(4'hE)) 
    RST_DRP_X16_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[9] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[10] ),
        .O(RST_DRP_X160));
  FDRE RST_DRP_X16_reg
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(RST_DRP_X160),
        .Q(rst_drp_x16),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair1758" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    \cfg_wait_cnt[0]_i_1 
       (.I0(dclk_rst_reg1),
        .I1(\FSM_onehot_fsm[12]_i_2_n_0 ),
        .I2(cfg_wait_cnt_reg[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair1756" *) 
  LUT4 #(
    .INIT(16'h28AA)) 
    \cfg_wait_cnt[1]_i_1 
       (.I0(dclk_rst_reg1),
        .I1(cfg_wait_cnt_reg[0]),
        .I2(cfg_wait_cnt_reg[1]),
        .I3(\FSM_onehot_fsm[12]_i_2_n_0 ),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair1756" *) 
  LUT5 #(
    .INIT(32'h2888AAAA)) 
    \cfg_wait_cnt[2]_i_1 
       (.I0(dclk_rst_reg1),
        .I1(cfg_wait_cnt_reg[2]),
        .I2(cfg_wait_cnt_reg[1]),
        .I3(cfg_wait_cnt_reg[0]),
        .I4(\FSM_onehot_fsm[12]_i_2_n_0 ),
        .O(p_0_in[2]));
  LUT6 #(
    .INIT(64'h28888888AAAAAAAA)) 
    \cfg_wait_cnt[3]_i_1 
       (.I0(dclk_rst_reg1),
        .I1(cfg_wait_cnt_reg[3]),
        .I2(cfg_wait_cnt_reg[0]),
        .I3(cfg_wait_cnt_reg[1]),
        .I4(cfg_wait_cnt_reg[2]),
        .I5(\FSM_onehot_fsm[12]_i_2_n_0 ),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair1757" *) 
  LUT5 #(
    .INIT(32'hEA006A00)) 
    \cfg_wait_cnt[4]_i_1 
       (.I0(cfg_wait_cnt_reg[4]),
        .I1(\cfg_wait_cnt[5]_i_2_n_0 ),
        .I2(cfg_wait_cnt_reg[3]),
        .I3(dclk_rst_reg1),
        .I4(cfg_wait_cnt_reg[5]),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair1757" *) 
  LUT5 #(
    .INIT(32'hA8888888)) 
    \cfg_wait_cnt[5]_i_1 
       (.I0(dclk_rst_reg1),
        .I1(cfg_wait_cnt_reg[5]),
        .I2(\cfg_wait_cnt[5]_i_2_n_0 ),
        .I3(cfg_wait_cnt_reg[3]),
        .I4(cfg_wait_cnt_reg[4]),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair1758" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \cfg_wait_cnt[5]_i_2 
       (.I0(cfg_wait_cnt_reg[2]),
        .I1(cfg_wait_cnt_reg[1]),
        .I2(cfg_wait_cnt_reg[0]),
        .O(\cfg_wait_cnt[5]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cfg_wait_cnt_reg[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cfg_wait_cnt_reg[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[2] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cfg_wait_cnt_reg[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[3] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cfg_wait_cnt_reg[3]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[4] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(cfg_wait_cnt_reg[4]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[5] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(p_0_in[5]),
        .Q(cfg_wait_cnt_reg[5]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    dclk_rst_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dclk_rst_reg1),
        .Q(dclk_rst_reg1__0),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    dclk_rst_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dclk_rst_reg1__0),
        .Q(rst_dclk_reset),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \drp_done_reg1_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\drp_done_reg1_reg[1]_0 [0]),
        .Q(drp_done_reg1[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \drp_done_reg1_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\drp_done_reg1_reg[1]_0 [1]),
        .Q(drp_done_reg1[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \drp_done_reg2_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(drp_done_reg1[0]),
        .Q(drp_done_reg2[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \drp_done_reg2_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(drp_done_reg1[1]),
        .Q(drp_done_reg2[1]),
        .R(SR));
  LUT2 #(
    .INIT(4'hE)) 
    \gtp_common.gtpe2_common_i_i_3 
       (.I0(rst_cpllreset),
        .I1(cpllrst),
        .O(PLL0RESET0));
  (* SOFT_HLUTNM = "soft_lutpair1759" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    gtreset_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[6] ),
        .I2(rst_gtreset),
        .O(gtreset_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gtreset_reg
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(gtreset_i_1_n_0),
        .Q(rst_gtreset),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(SYNC_MMCM_LOCK),
        .Q(mmcm_lock_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \phystatus_reg1_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\phystatus_reg1_reg[1]_0 [0]),
        .Q(phystatus_reg1[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \phystatus_reg1_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\phystatus_reg1_reg[1]_0 [1]),
        .Q(phystatus_reg1[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \phystatus_reg2_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(phystatus_reg1[0]),
        .Q(phystatus_reg2[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \phystatus_reg2_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(phystatus_reg1[1]),
        .Q(phystatus_reg2[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE plllock_reg1_reg
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(QRST_QPLLLOCK),
        .Q(plllock_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE plllock_reg2_reg
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(plllock_reg1),
        .Q(plllock_reg2),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair1759" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    pllreset_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I2(rst_cpllreset),
        .O(pllreset_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pllreset_reg
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(pllreset_i_1_n_0),
        .Q(rst_cpllreset),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_idle_reg1_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(Q[0]),
        .Q(rate_idle_reg1[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_idle_reg1_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(txsync_start_reg1_reg[0]),
        .Q(rate_idle_reg1[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_idle_reg2_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(rate_idle_reg1[0]),
        .Q(rate_idle_reg2[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_idle_reg2_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(rate_idle_reg1[1]),
        .Q(rate_idle_reg2[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \resetdone_reg1_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(resetdone_reg1[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \resetdone_reg1_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(resetdone_reg1[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \resetdone_reg2_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(resetdone_reg1[0]),
        .Q(resetdone_reg2[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \resetdone_reg2_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(resetdone_reg1[1]),
        .Q(resetdone_reg2[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxcdrlock_reg1_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\rxcdrlock_reg1_reg[1]_0 [0]),
        .Q(rxcdrlock_reg1[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxcdrlock_reg1_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\rxcdrlock_reg1_reg[1]_0 [1]),
        .Q(rxcdrlock_reg1[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxcdrlock_reg2_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(rxcdrlock_reg1[0]),
        .Q(rxcdrlock_reg2[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxcdrlock_reg2_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(rxcdrlock_reg1[1]),
        .Q(rxcdrlock_reg2[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxpmaresetdone_reg1_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\rxpmaresetdone_reg1_reg[1]_0 [0]),
        .Q(rxpmaresetdone_reg1[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxpmaresetdone_reg1_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\rxpmaresetdone_reg1_reg[1]_0 [1]),
        .Q(rxpmaresetdone_reg1[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxpmaresetdone_reg2_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1[0]),
        .Q(rxpmaresetdone_reg2[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxpmaresetdone_reg2_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1[1]),
        .Q(rxpmaresetdone_reg2[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    rxusrclk_rst_reg1_reg
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(rst_cpllreset),
        .Q(rxusrclk_rst_reg1),
        .R(1'b0));
  FDSE #(
    .INIT(1'b0)) 
    rxusrclk_rst_reg2_reg
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(rxusrclk_rst_reg1),
        .Q(rxusrclk_rst_reg2_reg_0),
        .S(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txsync_done_reg1_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\txsync_done_reg1_reg[1]_0 [0]),
        .Q(txsync_done_reg1[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txsync_done_reg1_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(\txsync_done_reg1_reg[1]_0 [1]),
        .Q(txsync_done_reg1[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txsync_done_reg2_reg[0] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(txsync_done_reg1[0]),
        .Q(txsync_done_reg2[0]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txsync_done_reg2_reg[1] 
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(txsync_done_reg1[1]),
        .Q(txsync_done_reg2[1]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair1761" *) 
  LUT2 #(
    .INIT(4'hE)) 
    txsync_start_reg1_i_1
       (.I0(rst_txsync_start),
        .I1(Q[1]),
        .O(SYNC_TXSYNC_START));
  (* SOFT_HLUTNM = "soft_lutpair1761" *) 
  LUT2 #(
    .INIT(4'hE)) 
    txsync_start_reg1_i_1__0
       (.I0(rst_txsync_start),
        .I1(txsync_start_reg1_reg[1]),
        .O(\FSM_onehot_fsm_reg[11]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    userrdy_i_1
       (.I0(mmcm_lock_reg2),
        .I1(userrdy),
        .I2(rst_userrdy),
        .O(userrdy_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    userrdy_reg
       (.C(\cfg_wait_cnt_reg[5]_0 ),
        .CE(1'b1),
        .D(userrdy_i_1_n_0),
        .Q(rst_userrdy),
        .R(SR));
endmodule

(* CFG_CTL_IF = "TRUE" *) (* CFG_FC_IF = "TRUE" *) (* CFG_MGMT_IF = "TRUE" *) 
(* CFG_STATUS_IF = "TRUE" *) (* C_DATA_WIDTH = "64" *) (* DEV_PORT_TYPE = "0" *) 
(* DowngradeIPIdentifiedWarnings = "yes" *) (* ENABLE_JTAG_DBG = "FALSE" *) (* ERR_REPORTING_IF = "TRUE" *) 
(* EXT_CH_GT_DRP = "FALSE" *) (* EXT_PIPE_INTERFACE = "FALSE" *) (* EXT_STARTUP_PRIMITIVE = "FALSE" *) 
(* KEEP_WIDTH = "8" *) (* LINK_CAP_MAX_LINK_WIDTH = "2" *) (* PCIE_ASYNC_EN = "FALSE" *) 
(* PCIE_EXT_CLK = "FALSE" *) (* PCIE_EXT_GT_COMMON = "FALSE" *) (* PCIE_ID_IF = "FALSE" *) 
(* PIPE_SIM = "FALSE" *) (* PL_INTERFACE = "TRUE" *) (* RCV_MSG_IF = "TRUE" *) 
(* REDUCE_OOB_FREQ = "FALSE" *) (* SHARED_LOGIC_IN_CORE = "FALSE" *) (* TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE" *) 
(* bar_0 = "FFFF0000" *) (* bar_1 = "FFF00000" *) (* bar_2 = "00000000" *) 
(* bar_3 = "00000000" *) (* bar_4 = "00000000" *) (* bar_5 = "00000000" *) 
(* bram_lat = "0" *) (* c_aer_base_ptr = "000" *) (* c_aer_cap_ecrc_check_capable = "FALSE" *) 
(* c_aer_cap_ecrc_gen_capable = "FALSE" *) (* c_aer_cap_multiheader = "FALSE" *) (* c_aer_cap_nextptr = "000" *) 
(* c_aer_cap_on = "FALSE" *) (* c_aer_cap_optional_err_support = "000000" *) (* c_aer_cap_permit_rooterr_update = "FALSE" *) 
(* c_buf_opt_bma = "TRUE" *) (* c_component_name = "xdma_0_pcie2_ip" *) (* c_cpl_inf = "TRUE" *) 
(* c_cpl_infinite = "TRUE" *) (* c_cpl_timeout_disable_sup = "FALSE" *) (* c_cpl_timeout_range = "0010" *) 
(* c_cpl_timeout_ranges_sup = "2" *) (* c_d1_support = "FALSE" *) (* c_d2_support = "FALSE" *) 
(* c_de_emph = "FALSE" *) (* c_dev_cap2_ari_forwarding_supported = "FALSE" *) (* c_dev_cap2_atomicop32_completer_supported = "FALSE" *) 
(* c_dev_cap2_atomicop64_completer_supported = "FALSE" *) (* c_dev_cap2_atomicop_routing_supported = "FALSE" *) (* c_dev_cap2_cas128_completer_supported = "FALSE" *) 
(* c_dev_cap2_tph_completer_supported = "00" *) (* c_dev_control_ext_tag_default = "FALSE" *) (* c_dev_port_type = "0" *) 
(* c_dis_lane_reverse = "TRUE" *) (* c_disable_rx_poisoned_resp = "FALSE" *) (* c_disable_scrambling = "FALSE" *) 
(* c_disable_tx_aspm_l0s = "FALSE" *) (* c_dll_lnk_actv_cap = "FALSE" *) (* c_dsi_bool = "FALSE" *) 
(* c_dsn_base_ptr = "100" *) (* c_dsn_cap_enabled = "TRUE" *) (* c_dsn_next_ptr = "000" *) 
(* c_enable_msg_route = "00000000000" *) (* c_ep_l0s_accpt_lat = "0" *) (* c_ep_l1_accpt_lat = "7" *) 
(* c_ext_pci_cfg_space_addr = "3FF" *) (* c_external_clocking = "TRUE" *) (* c_fc_cpld = "461" *) 
(* c_fc_cplh = "36" *) (* c_fc_npd = "24" *) (* c_fc_nph = "12" *) 
(* c_fc_pd = "437" *) (* c_fc_ph = "32" *) (* c_gen1 = "1'b1" *) 
(* c_header_type = "00" *) (* c_hw_auton_spd_disable = "FALSE" *) (* c_int_width = "64" *) 
(* c_last_cfg_dw = "10C" *) (* c_link_cap_aspm_optionality = "FALSE" *) (* c_ll_ack_timeout = "0000" *) 
(* c_ll_ack_timeout_enable = "FALSE" *) (* c_ll_ack_timeout_function = "0" *) (* c_ll_replay_timeout = "0000" *) 
(* c_ll_replay_timeout_enable = "FALSE" *) (* c_ll_replay_timeout_func = "1" *) (* c_lnk_bndwdt_notif = "FALSE" *) 
(* c_msi = "0" *) (* c_msi_64b_addr = "TRUE" *) (* c_msi_cap_on = "TRUE" *) 
(* c_msi_mult_msg_extn = "0" *) (* c_msi_per_vctr_mask_cap = "FALSE" *) (* c_msix_cap_on = "FALSE" *) 
(* c_msix_next_ptr = "00" *) (* c_msix_pba_bir = "0" *) (* c_msix_pba_offset = "0" *) 
(* c_msix_table_bir = "0" *) (* c_msix_table_offset = "0" *) (* c_msix_table_size = "000" *) 
(* c_pci_cfg_space_addr = "3F" *) (* c_pcie_blk_locn = "0" *) (* c_pcie_cap_next_ptr = "00" *) 
(* c_pcie_cap_slot_implemented = "FALSE" *) (* c_pcie_dbg_ports = "FALSE" *) (* c_pcie_fast_config = "0" *) 
(* c_perf_level_high = "TRUE" *) (* c_phantom_functions = "0" *) (* c_pm_cap_next_ptr = "48" *) 
(* c_pme_support = "0F" *) (* c_rbar_base_ptr = "000" *) (* c_rbar_cap_control_encodedbar0 = "00" *) 
(* c_rbar_cap_control_encodedbar1 = "00" *) (* c_rbar_cap_control_encodedbar2 = "00" *) (* c_rbar_cap_control_encodedbar3 = "00" *) 
(* c_rbar_cap_control_encodedbar4 = "00" *) (* c_rbar_cap_control_encodedbar5 = "00" *) (* c_rbar_cap_index0 = "0" *) 
(* c_rbar_cap_index1 = "0" *) (* c_rbar_cap_index2 = "0" *) (* c_rbar_cap_index3 = "0" *) 
(* c_rbar_cap_index4 = "0" *) (* c_rbar_cap_index5 = "0" *) (* c_rbar_cap_nextptr = "000" *) 
(* c_rbar_cap_on = "FALSE" *) (* c_rbar_cap_sup0 = "00001" *) (* c_rbar_cap_sup1 = "00001" *) 
(* c_rbar_cap_sup2 = "00001" *) (* c_rbar_cap_sup3 = "00001" *) (* c_rbar_cap_sup4 = "00001" *) 
(* c_rbar_cap_sup5 = "00001" *) (* c_rbar_num = "0" *) (* c_rcb = "0" *) 
(* c_recrc_check = "0" *) (* c_recrc_check_trim = "FALSE" *) (* c_rev_gt_order = "FALSE" *) 
(* c_root_cap_crs = "FALSE" *) (* c_rx_raddr_lat = "0" *) (* c_rx_ram_limit = "7FF" *) 
(* c_rx_rdata_lat = "2" *) (* c_rx_write_lat = "0" *) (* c_silicon_rev = "2" *) 
(* c_slot_cap_attn_butn = "FALSE" *) (* c_slot_cap_attn_ind = "FALSE" *) (* c_slot_cap_elec_interlock = "FALSE" *) 
(* c_slot_cap_hotplug_cap = "FALSE" *) (* c_slot_cap_hotplug_surprise = "FALSE" *) (* c_slot_cap_mrl = "FALSE" *) 
(* c_slot_cap_no_cmd_comp_sup = "FALSE" *) (* c_slot_cap_physical_slot_num = "0" *) (* c_slot_cap_pwr_ctrl = "FALSE" *) 
(* c_slot_cap_pwr_ind = "FALSE" *) (* c_slot_cap_pwr_limit_scale = "0" *) (* c_slot_cap_pwr_limit_value = "0" *) 
(* c_surprise_dn_err_cap = "FALSE" *) (* c_trgt_lnk_spd = "2" *) (* c_trn_np_fc = "TRUE" *) 
(* c_tx_last_tlp = "29" *) (* c_tx_raddr_lat = "0" *) (* c_tx_rdata_lat = "2" *) 
(* c_tx_write_lat = "0" *) (* c_upconfig_capable = "TRUE" *) (* c_upstream_facing = "TRUE" *) 
(* c_ur_atomic = "FALSE" *) (* c_ur_inv_req = "TRUE" *) (* c_ur_prs_response = "TRUE" *) 
(* c_vc_base_ptr = "000" *) (* c_vc_cap_enabled = "FALSE" *) (* c_vc_cap_reject_snoop = "FALSE" *) 
(* c_vc_next_ptr = "000" *) (* c_vsec_base_ptr = "000" *) (* c_vsec_cap_enabled = "FALSE" *) 
(* c_vsec_next_ptr = "000" *) (* c_xlnx_ref_board = "NONE" *) (* cap_ver = "2" *) 
(* cardbus_cis_ptr = "00000000" *) (* class_code = "070001" *) (* cmps = "2" *) 
(* con_scl_fctr_d0_state = "0" *) (* con_scl_fctr_d1_state = "0" *) (* con_scl_fctr_d2_state = "0" *) 
(* con_scl_fctr_d3_state = "0" *) (* cost_table = "1" *) (* d1_sup = "0" *) 
(* d2_sup = "0" *) (* dev_id = "7022" *) (* dis_scl_fctr_d0_state = "0" *) 
(* dis_scl_fctr_d1_state = "0" *) (* dis_scl_fctr_d2_state = "0" *) (* dis_scl_fctr_d3_state = "0" *) 
(* dsi = "0" *) (* ep_l0s_accpt_lat = "000" *) (* ep_l1_accpt_lat = "111" *) 
(* ext_tag_fld_sup = "TRUE" *) (* int_pin = "1" *) (* intx = "TRUE" *) 
(* max_lnk_spd = "2" *) (* max_lnk_wdt = "000010" *) (* mps = "010" *) 
(* no_soft_rst = "TRUE" *) (* pci_exp_int_freq = "2" *) (* pci_exp_ref_freq = "0" *) 
(* phantm_func_sup = "00" *) (* pme_sup = "0F" *) (* pwr_con_d0_state = "00" *) 
(* pwr_con_d1_state = "00" *) (* pwr_con_d2_state = "00" *) (* pwr_con_d3_state = "00" *) 
(* pwr_dis_d0_state = "00" *) (* pwr_dis_d1_state = "00" *) (* pwr_dis_d2_state = "00" *) 
(* pwr_dis_d3_state = "00" *) (* rev_id = "00" *) (* slot_clk = "TRUE" *) 
(* subsys_id = "0007" *) (* subsys_ven_id = "10EE" *) (* ven_id = "10EE" *) 
(* xrom_bar = "00000000" *) 
module xdma_0_pcie2_ip_pcie2_top
   (pci_exp_txn,
    pci_exp_txp,
    pci_exp_rxn,
    pci_exp_rxp,
    int_pclk_out_slave,
    int_pipe_rxusrclk_out,
    int_rxoutclk_out,
    int_dclk_out,
    int_userclk1_out,
    int_userclk2_out,
    int_oobclk_out,
    int_mmcm_lock_out,
    int_qplllock_out,
    int_qplloutclk_out,
    int_qplloutrefclk_out,
    int_pclk_sel_slave,
    pipe_pclk_in,
    pipe_rxusrclk_in,
    pipe_rxoutclk_in,
    pipe_dclk_in,
    pipe_userclk1_in,
    pipe_userclk2_in,
    pipe_oobclk_in,
    pipe_mmcm_lock_in,
    pipe_txoutclk_out,
    pipe_rxoutclk_out,
    pipe_pclk_sel_out,
    pipe_gen3_out,
    qpll_drp_crscode,
    qpll_drp_fsm,
    qpll_drp_done,
    qpll_drp_reset,
    qpll_qplllock,
    qpll_qplloutclk,
    qpll_qplloutrefclk,
    qpll_qplld,
    qpll_qpllreset,
    qpll_drp_clk,
    qpll_drp_rst_n,
    qpll_drp_ovrd,
    qpll_drp_gen3,
    qpll_drp_start,
    user_clk_out,
    user_reset_out,
    user_lnk_up,
    user_app_rdy,
    tx_buf_av,
    tx_err_drop,
    tx_cfg_req,
    s_axis_tx_tdata,
    s_axis_tx_tvalid,
    s_axis_tx_tready,
    s_axis_tx_tkeep,
    s_axis_tx_tlast,
    s_axis_tx_tuser,
    tx_cfg_gnt,
    m_axis_rx_tdata,
    m_axis_rx_tvalid,
    m_axis_rx_tready,
    m_axis_rx_tkeep,
    m_axis_rx_tlast,
    m_axis_rx_tuser,
    rx_np_ok,
    rx_np_req,
    fc_cpld,
    fc_cplh,
    fc_npd,
    fc_nph,
    fc_pd,
    fc_ph,
    fc_sel,
    cfg_mgmt_do,
    cfg_mgmt_rd_wr_done,
    cfg_status,
    cfg_command,
    cfg_dstatus,
    cfg_dcommand,
    cfg_lstatus,
    cfg_lcommand,
    cfg_dcommand2,
    cfg_pcie_link_state,
    cfg_pmcsr_pme_en,
    cfg_pmcsr_powerstate,
    cfg_pmcsr_pme_status,
    cfg_received_func_lvl_rst,
    cfg_mgmt_di,
    cfg_mgmt_byte_en,
    cfg_mgmt_dwaddr,
    cfg_mgmt_wr_en,
    cfg_mgmt_rd_en,
    cfg_mgmt_wr_readonly,
    cfg_err_ecrc,
    cfg_err_ur,
    cfg_err_cpl_timeout,
    cfg_err_cpl_unexpect,
    cfg_err_cpl_abort,
    cfg_err_posted,
    cfg_err_cor,
    cfg_err_atomic_egress_blocked,
    cfg_err_internal_cor,
    cfg_err_malformed,
    cfg_err_mc_blocked,
    cfg_err_poisoned,
    cfg_err_norecovery,
    cfg_err_tlp_cpl_header,
    cfg_err_cpl_rdy,
    cfg_err_locked,
    cfg_err_acs,
    cfg_err_internal_uncor,
    cfg_trn_pending,
    cfg_pm_halt_aspm_l0s,
    cfg_pm_halt_aspm_l1,
    cfg_pm_force_state_en,
    cfg_pm_force_state,
    cfg_dsn,
    cfg_msg_received,
    cfg_msg_data,
    cfg_interrupt,
    cfg_interrupt_rdy,
    cfg_interrupt_assert,
    cfg_interrupt_di,
    cfg_interrupt_do,
    cfg_interrupt_mmenable,
    cfg_interrupt_msienable,
    cfg_interrupt_msixenable,
    cfg_interrupt_msixfm,
    cfg_interrupt_stat,
    cfg_pciecap_interrupt_msgnum,
    cfg_to_turnoff,
    cfg_turnoff_ok,
    cfg_bus_number,
    cfg_device_number,
    cfg_function_number,
    cfg_pm_wake,
    cfg_msg_received_pm_as_nak,
    cfg_msg_received_setslotpowerlimit,
    cfg_pm_send_pme_to,
    cfg_ds_bus_number,
    cfg_ds_device_number,
    cfg_ds_function_number,
    cfg_mgmt_wr_rw1c_as_rw,
    cfg_bridge_serr_en,
    cfg_slot_control_electromech_il_ctl_pulse,
    cfg_root_control_syserr_corr_err_en,
    cfg_root_control_syserr_non_fatal_err_en,
    cfg_root_control_syserr_fatal_err_en,
    cfg_root_control_pme_int_en,
    cfg_aer_rooterr_corr_err_reporting_en,
    cfg_aer_rooterr_non_fatal_err_reporting_en,
    cfg_aer_rooterr_fatal_err_reporting_en,
    cfg_aer_rooterr_corr_err_received,
    cfg_aer_rooterr_non_fatal_err_received,
    cfg_aer_rooterr_fatal_err_received,
    cfg_msg_received_err_cor,
    cfg_msg_received_err_non_fatal,
    cfg_msg_received_err_fatal,
    cfg_msg_received_pm_pme,
    cfg_msg_received_pme_to_ack,
    cfg_msg_received_assert_int_a,
    cfg_msg_received_assert_int_b,
    cfg_msg_received_assert_int_c,
    cfg_msg_received_assert_int_d,
    cfg_msg_received_deassert_int_a,
    cfg_msg_received_deassert_int_b,
    cfg_msg_received_deassert_int_c,
    cfg_msg_received_deassert_int_d,
    pl_directed_link_change,
    pl_directed_link_width,
    pl_directed_link_speed,
    pl_directed_link_auton,
    pl_upstream_prefer_deemph,
    pl_sel_lnk_rate,
    pl_sel_lnk_width,
    pl_ltssm_state,
    pl_lane_reversal_mode,
    pl_phy_lnk_up,
    pl_tx_pm_state,
    pl_rx_pm_state,
    pl_link_upcfg_cap,
    pl_link_gen2_cap,
    pl_link_partner_gen2_supported,
    pl_initial_link_width,
    pl_directed_change_done,
    pl_received_hot_rst,
    pl_transmit_hot_rst,
    pl_downstream_deemph_source,
    cfg_err_aer_headerlog,
    cfg_aer_interrupt_msgnum,
    cfg_err_aer_headerlog_set,
    cfg_aer_ecrc_check_en,
    cfg_aer_ecrc_gen_en,
    cfg_vc_tcvc_map,
    pcie_drp_clk,
    pcie_drp_en,
    pcie_drp_we,
    pcie_drp_addr,
    pcie_drp_di,
    pcie_drp_rdy,
    pcie_drp_do,
    startup_eos_in,
    startup_cfgclk,
    startup_cfgmclk,
    startup_eos,
    startup_preq,
    startup_clk,
    startup_gsr,
    startup_gts,
    startup_keyclearb,
    startup_pack,
    startup_usrcclko,
    startup_usrcclkts,
    startup_usrdoneo,
    startup_usrdonets,
    icap_clk,
    icap_csib,
    icap_rdwrb,
    icap_i,
    icap_o,
    pipe_txprbssel,
    pipe_rxprbssel,
    pipe_txprbsforceerr,
    pipe_rxprbscntreset,
    pipe_loopback,
    pipe_rxprbserr,
    pipe_txinhibit,
    pipe_rst_fsm,
    pipe_qrst_fsm,
    pipe_rate_fsm,
    pipe_sync_fsm_tx,
    pipe_sync_fsm_rx,
    pipe_drp_fsm,
    pipe_rst_idle,
    pipe_qrst_idle,
    pipe_rate_idle,
    pipe_eyescandataerror,
    pipe_rxstatus,
    pipe_dmonitorout,
    pipe_cpll_lock,
    pipe_qpll_lock,
    pipe_rxpmaresetdone,
    pipe_rxbufstatus,
    pipe_txphaligndone,
    pipe_txphinitdone,
    pipe_txdlysresetdone,
    pipe_rxphaligndone,
    pipe_rxdlysresetdone,
    pipe_rxsyncdone,
    pipe_rxdisperr,
    pipe_rxnotintable,
    pipe_rxcommadet,
    gt_ch_drp_rdy,
    pipe_debug_0,
    pipe_debug_1,
    pipe_debug_2,
    pipe_debug_3,
    pipe_debug_4,
    pipe_debug_5,
    pipe_debug_6,
    pipe_debug_7,
    pipe_debug_8,
    pipe_debug_9,
    pipe_debug,
    ext_ch_gt_drpclk,
    ext_ch_gt_drpaddr,
    ext_ch_gt_drpen,
    ext_ch_gt_drpdi,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdo,
    ext_ch_gt_drprdy,
    common_commands_in,
    pipe_rx_0_sigs,
    pipe_rx_1_sigs,
    pipe_rx_2_sigs,
    pipe_rx_3_sigs,
    pipe_rx_4_sigs,
    pipe_rx_5_sigs,
    pipe_rx_6_sigs,
    pipe_rx_7_sigs,
    common_commands_out,
    pipe_tx_0_sigs,
    pipe_tx_1_sigs,
    pipe_tx_2_sigs,
    pipe_tx_3_sigs,
    pipe_tx_4_sigs,
    pipe_tx_5_sigs,
    pipe_tx_6_sigs,
    pipe_tx_7_sigs,
    cfg_dev_id_pf0,
    cfg_ven_id,
    cfg_rev_id_pf0,
    cfg_subsys_id_pf0,
    cfg_subsys_ven_id,
    pipe_mmcm_rst_n,
    sys_clk,
    sys_rst_n);
  output [1:0]pci_exp_txn;
  output [1:0]pci_exp_txp;
  input [1:0]pci_exp_rxn;
  input [1:0]pci_exp_rxp;
  output int_pclk_out_slave;
  output int_pipe_rxusrclk_out;
  output [1:0]int_rxoutclk_out;
  output int_dclk_out;
  output int_userclk1_out;
  output int_userclk2_out;
  output int_oobclk_out;
  output int_mmcm_lock_out;
  output [1:0]int_qplllock_out;
  output [1:0]int_qplloutclk_out;
  output [1:0]int_qplloutrefclk_out;
  input [1:0]int_pclk_sel_slave;
  input pipe_pclk_in;
  input pipe_rxusrclk_in;
  input [1:0]pipe_rxoutclk_in;
  input pipe_dclk_in;
  input pipe_userclk1_in;
  input pipe_userclk2_in;
  input pipe_oobclk_in;
  input pipe_mmcm_lock_in;
  output pipe_txoutclk_out;
  output [1:0]pipe_rxoutclk_out;
  output [1:0]pipe_pclk_sel_out;
  output pipe_gen3_out;
  input [11:0]qpll_drp_crscode;
  input [17:0]qpll_drp_fsm;
  input [1:0]qpll_drp_done;
  input [1:0]qpll_drp_reset;
  input [1:0]qpll_qplllock;
  input [1:0]qpll_qplloutclk;
  input [1:0]qpll_qplloutrefclk;
  output qpll_qplld;
  output [1:0]qpll_qpllreset;
  output qpll_drp_clk;
  output qpll_drp_rst_n;
  output qpll_drp_ovrd;
  output qpll_drp_gen3;
  output qpll_drp_start;
  output user_clk_out;
  output user_reset_out;
  output user_lnk_up;
  output user_app_rdy;
  output [5:0]tx_buf_av;
  output tx_err_drop;
  output tx_cfg_req;
  input [63:0]s_axis_tx_tdata;
  input s_axis_tx_tvalid;
  output s_axis_tx_tready;
  input [7:0]s_axis_tx_tkeep;
  input s_axis_tx_tlast;
  input [3:0]s_axis_tx_tuser;
  input tx_cfg_gnt;
  output [63:0]m_axis_rx_tdata;
  output m_axis_rx_tvalid;
  input m_axis_rx_tready;
  output [7:0]m_axis_rx_tkeep;
  output m_axis_rx_tlast;
  output [21:0]m_axis_rx_tuser;
  input rx_np_ok;
  input rx_np_req;
  output [11:0]fc_cpld;
  output [7:0]fc_cplh;
  output [11:0]fc_npd;
  output [7:0]fc_nph;
  output [11:0]fc_pd;
  output [7:0]fc_ph;
  input [2:0]fc_sel;
  output [31:0]cfg_mgmt_do;
  output cfg_mgmt_rd_wr_done;
  output [15:0]cfg_status;
  output [15:0]cfg_command;
  output [15:0]cfg_dstatus;
  output [15:0]cfg_dcommand;
  output [15:0]cfg_lstatus;
  output [15:0]cfg_lcommand;
  output [15:0]cfg_dcommand2;
  output [2:0]cfg_pcie_link_state;
  output cfg_pmcsr_pme_en;
  output [1:0]cfg_pmcsr_powerstate;
  output cfg_pmcsr_pme_status;
  output cfg_received_func_lvl_rst;
  input [31:0]cfg_mgmt_di;
  input [3:0]cfg_mgmt_byte_en;
  input [9:0]cfg_mgmt_dwaddr;
  input cfg_mgmt_wr_en;
  input cfg_mgmt_rd_en;
  input cfg_mgmt_wr_readonly;
  input cfg_err_ecrc;
  input cfg_err_ur;
  input cfg_err_cpl_timeout;
  input cfg_err_cpl_unexpect;
  input cfg_err_cpl_abort;
  input cfg_err_posted;
  input cfg_err_cor;
  input cfg_err_atomic_egress_blocked;
  input cfg_err_internal_cor;
  input cfg_err_malformed;
  input cfg_err_mc_blocked;
  input cfg_err_poisoned;
  input cfg_err_norecovery;
  input [47:0]cfg_err_tlp_cpl_header;
  output cfg_err_cpl_rdy;
  input cfg_err_locked;
  input cfg_err_acs;
  input cfg_err_internal_uncor;
  input cfg_trn_pending;
  input cfg_pm_halt_aspm_l0s;
  input cfg_pm_halt_aspm_l1;
  input cfg_pm_force_state_en;
  input [1:0]cfg_pm_force_state;
  input [63:0]cfg_dsn;
  output cfg_msg_received;
  output [15:0]cfg_msg_data;
  input cfg_interrupt;
  output cfg_interrupt_rdy;
  input cfg_interrupt_assert;
  input [7:0]cfg_interrupt_di;
  output [7:0]cfg_interrupt_do;
  output [2:0]cfg_interrupt_mmenable;
  output cfg_interrupt_msienable;
  output cfg_interrupt_msixenable;
  output cfg_interrupt_msixfm;
  input cfg_interrupt_stat;
  input [4:0]cfg_pciecap_interrupt_msgnum;
  output cfg_to_turnoff;
  input cfg_turnoff_ok;
  output [7:0]cfg_bus_number;
  output [4:0]cfg_device_number;
  output [2:0]cfg_function_number;
  input cfg_pm_wake;
  output cfg_msg_received_pm_as_nak;
  output cfg_msg_received_setslotpowerlimit;
  input cfg_pm_send_pme_to;
  input [7:0]cfg_ds_bus_number;
  input [4:0]cfg_ds_device_number;
  input [2:0]cfg_ds_function_number;
  input cfg_mgmt_wr_rw1c_as_rw;
  output cfg_bridge_serr_en;
  output cfg_slot_control_electromech_il_ctl_pulse;
  output cfg_root_control_syserr_corr_err_en;
  output cfg_root_control_syserr_non_fatal_err_en;
  output cfg_root_control_syserr_fatal_err_en;
  output cfg_root_control_pme_int_en;
  output cfg_aer_rooterr_corr_err_reporting_en;
  output cfg_aer_rooterr_non_fatal_err_reporting_en;
  output cfg_aer_rooterr_fatal_err_reporting_en;
  output cfg_aer_rooterr_corr_err_received;
  output cfg_aer_rooterr_non_fatal_err_received;
  output cfg_aer_rooterr_fatal_err_received;
  output cfg_msg_received_err_cor;
  output cfg_msg_received_err_non_fatal;
  output cfg_msg_received_err_fatal;
  output cfg_msg_received_pm_pme;
  output cfg_msg_received_pme_to_ack;
  output cfg_msg_received_assert_int_a;
  output cfg_msg_received_assert_int_b;
  output cfg_msg_received_assert_int_c;
  output cfg_msg_received_assert_int_d;
  output cfg_msg_received_deassert_int_a;
  output cfg_msg_received_deassert_int_b;
  output cfg_msg_received_deassert_int_c;
  output cfg_msg_received_deassert_int_d;
  input [1:0]pl_directed_link_change;
  input [1:0]pl_directed_link_width;
  input pl_directed_link_speed;
  input pl_directed_link_auton;
  input pl_upstream_prefer_deemph;
  output pl_sel_lnk_rate;
  output [1:0]pl_sel_lnk_width;
  output [5:0]pl_ltssm_state;
  output [1:0]pl_lane_reversal_mode;
  output pl_phy_lnk_up;
  output [2:0]pl_tx_pm_state;
  output [1:0]pl_rx_pm_state;
  output pl_link_upcfg_cap;
  output pl_link_gen2_cap;
  output pl_link_partner_gen2_supported;
  output [2:0]pl_initial_link_width;
  output pl_directed_change_done;
  output pl_received_hot_rst;
  input pl_transmit_hot_rst;
  input pl_downstream_deemph_source;
  input [127:0]cfg_err_aer_headerlog;
  input [4:0]cfg_aer_interrupt_msgnum;
  output cfg_err_aer_headerlog_set;
  output cfg_aer_ecrc_check_en;
  output cfg_aer_ecrc_gen_en;
  output [6:0]cfg_vc_tcvc_map;
  input pcie_drp_clk;
  input pcie_drp_en;
  input pcie_drp_we;
  input [8:0]pcie_drp_addr;
  input [15:0]pcie_drp_di;
  output pcie_drp_rdy;
  output [15:0]pcie_drp_do;
  input startup_eos_in;
  output startup_cfgclk;
  output startup_cfgmclk;
  output startup_eos;
  output startup_preq;
  input startup_clk;
  input startup_gsr;
  input startup_gts;
  input startup_keyclearb;
  input startup_pack;
  input startup_usrcclko;
  input startup_usrcclkts;
  input startup_usrdoneo;
  input startup_usrdonets;
  input icap_clk;
  input icap_csib;
  input icap_rdwrb;
  input [31:0]icap_i;
  output [31:0]icap_o;
  input [2:0]pipe_txprbssel;
  input [2:0]pipe_rxprbssel;
  input pipe_txprbsforceerr;
  input pipe_rxprbscntreset;
  input [2:0]pipe_loopback;
  output [1:0]pipe_rxprbserr;
  input [1:0]pipe_txinhibit;
  output [4:0]pipe_rst_fsm;
  output [11:0]pipe_qrst_fsm;
  output [9:0]pipe_rate_fsm;
  output [11:0]pipe_sync_fsm_tx;
  output [13:0]pipe_sync_fsm_rx;
  output [13:0]pipe_drp_fsm;
  output pipe_rst_idle;
  output pipe_qrst_idle;
  output pipe_rate_idle;
  output [1:0]pipe_eyescandataerror;
  output [5:0]pipe_rxstatus;
  output [29:0]pipe_dmonitorout;
  output [1:0]pipe_cpll_lock;
  output [0:0]pipe_qpll_lock;
  output [1:0]pipe_rxpmaresetdone;
  output [5:0]pipe_rxbufstatus;
  output [1:0]pipe_txphaligndone;
  output [1:0]pipe_txphinitdone;
  output [1:0]pipe_txdlysresetdone;
  output [1:0]pipe_rxphaligndone;
  output [1:0]pipe_rxdlysresetdone;
  output [1:0]pipe_rxsyncdone;
  output [15:0]pipe_rxdisperr;
  output [15:0]pipe_rxnotintable;
  output [1:0]pipe_rxcommadet;
  output [1:0]gt_ch_drp_rdy;
  output [1:0]pipe_debug_0;
  output [1:0]pipe_debug_1;
  output [1:0]pipe_debug_2;
  output [1:0]pipe_debug_3;
  output [1:0]pipe_debug_4;
  output [1:0]pipe_debug_5;
  output [1:0]pipe_debug_6;
  output [1:0]pipe_debug_7;
  output [1:0]pipe_debug_8;
  output [1:0]pipe_debug_9;
  output [31:0]pipe_debug;
  output ext_ch_gt_drpclk;
  input [17:0]ext_ch_gt_drpaddr;
  input [1:0]ext_ch_gt_drpen;
  input [31:0]ext_ch_gt_drpdi;
  input [1:0]ext_ch_gt_drpwe;
  output [31:0]ext_ch_gt_drpdo;
  output [1:0]ext_ch_gt_drprdy;
  input [11:0]common_commands_in;
  input [24:0]pipe_rx_0_sigs;
  input [24:0]pipe_rx_1_sigs;
  input [24:0]pipe_rx_2_sigs;
  input [24:0]pipe_rx_3_sigs;
  input [24:0]pipe_rx_4_sigs;
  input [24:0]pipe_rx_5_sigs;
  input [24:0]pipe_rx_6_sigs;
  input [24:0]pipe_rx_7_sigs;
  output [11:0]common_commands_out;
  output [24:0]pipe_tx_0_sigs;
  output [24:0]pipe_tx_1_sigs;
  output [24:0]pipe_tx_2_sigs;
  output [24:0]pipe_tx_3_sigs;
  output [24:0]pipe_tx_4_sigs;
  output [24:0]pipe_tx_5_sigs;
  output [24:0]pipe_tx_6_sigs;
  output [24:0]pipe_tx_7_sigs;
  input [15:0]cfg_dev_id_pf0;
  input [15:0]cfg_ven_id;
  input [7:0]cfg_rev_id_pf0;
  input [15:0]cfg_subsys_id_pf0;
  input [15:0]cfg_subsys_ven_id;
  input pipe_mmcm_rst_n;
  input sys_clk;
  input sys_rst_n;

  wire \<const0> ;
  wire [4:0]cfg_aer_interrupt_msgnum;
  wire [7:0]cfg_bus_number;
  wire [2:2]\^cfg_command ;
  wire [14:5]\^cfg_dcommand ;
  wire [4:0]cfg_device_number;
  wire [63:0]cfg_dsn;
  wire [127:0]cfg_err_aer_headerlog;
  wire [47:0]cfg_err_tlp_cpl_header;
  wire [2:0]cfg_function_number;
  wire cfg_interrupt;
  wire cfg_interrupt_assert;
  wire [7:0]cfg_interrupt_di;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire cfg_interrupt_rdy;
  wire [3:0]cfg_mgmt_byte_en;
  wire [31:0]cfg_mgmt_di;
  wire [31:0]cfg_mgmt_do;
  wire [9:0]cfg_mgmt_dwaddr;
  wire cfg_mgmt_rd_en;
  wire cfg_mgmt_rd_wr_done;
  wire cfg_mgmt_wr_en;
  wire cfg_mgmt_wr_readonly;
  wire [4:0]cfg_pciecap_interrupt_msgnum;
  wire [1:0]cfg_pm_force_state;
  wire cfg_to_turnoff;
  wire cfg_turnoff_ok;
  wire [7:0]fc_nph;
  wire [2:0]fc_sel;
  wire [1:0]int_pclk_sel_slave;
  wire [63:0]m_axis_rx_tdata;
  wire [5:5]\^m_axis_rx_tkeep ;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [21:0]\^m_axis_rx_tuser ;
  wire m_axis_rx_tvalid;
  wire [1:0]pci_exp_rxn;
  wire [1:0]pci_exp_rxp;
  wire [1:0]pci_exp_txn;
  wire [1:0]pci_exp_txp;
  wire pl_directed_link_auton;
  wire [1:0]pl_directed_link_change;
  wire pl_directed_link_speed;
  wire [1:0]pl_directed_link_width;
  wire pl_phy_lnk_up;
  wire pl_upstream_prefer_deemph;
  wire rx_np_ok;
  wire rx_np_req;
  wire [63:0]s_axis_tx_tdata;
  wire [7:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tready;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire sys_clk;
  wire sys_rst_n;
  wire tx_cfg_gnt;
  wire user_clk_out;
  wire user_lnk_up;
  wire user_reset_out;

  assign cfg_aer_ecrc_check_en = \<const0> ;
  assign cfg_aer_ecrc_gen_en = \<const0> ;
  assign cfg_aer_rooterr_corr_err_received = \<const0> ;
  assign cfg_aer_rooterr_corr_err_reporting_en = \<const0> ;
  assign cfg_aer_rooterr_fatal_err_received = \<const0> ;
  assign cfg_aer_rooterr_fatal_err_reporting_en = \<const0> ;
  assign cfg_aer_rooterr_non_fatal_err_received = \<const0> ;
  assign cfg_aer_rooterr_non_fatal_err_reporting_en = \<const0> ;
  assign cfg_bridge_serr_en = \<const0> ;
  assign cfg_command[15] = \<const0> ;
  assign cfg_command[14] = \<const0> ;
  assign cfg_command[13] = \<const0> ;
  assign cfg_command[12] = \<const0> ;
  assign cfg_command[11] = \<const0> ;
  assign cfg_command[10] = \<const0> ;
  assign cfg_command[9] = \<const0> ;
  assign cfg_command[8] = \<const0> ;
  assign cfg_command[7] = \<const0> ;
  assign cfg_command[6] = \<const0> ;
  assign cfg_command[5] = \<const0> ;
  assign cfg_command[4] = \<const0> ;
  assign cfg_command[3] = \<const0> ;
  assign cfg_command[2] = \^cfg_command [2];
  assign cfg_command[1] = \<const0> ;
  assign cfg_command[0] = \<const0> ;
  assign cfg_dcommand[15] = \<const0> ;
  assign cfg_dcommand[14:12] = \^cfg_dcommand [14:12];
  assign cfg_dcommand[11] = \<const0> ;
  assign cfg_dcommand[10] = \<const0> ;
  assign cfg_dcommand[9] = \<const0> ;
  assign cfg_dcommand[8] = \<const0> ;
  assign cfg_dcommand[7:5] = \^cfg_dcommand [7:5];
  assign cfg_dcommand[4] = \<const0> ;
  assign cfg_dcommand[3] = \<const0> ;
  assign cfg_dcommand[2] = \<const0> ;
  assign cfg_dcommand[1] = \<const0> ;
  assign cfg_dcommand[0] = \<const0> ;
  assign cfg_dcommand2[15] = \<const0> ;
  assign cfg_dcommand2[14] = \<const0> ;
  assign cfg_dcommand2[13] = \<const0> ;
  assign cfg_dcommand2[12] = \<const0> ;
  assign cfg_dcommand2[11] = \<const0> ;
  assign cfg_dcommand2[10] = \<const0> ;
  assign cfg_dcommand2[9] = \<const0> ;
  assign cfg_dcommand2[8] = \<const0> ;
  assign cfg_dcommand2[7] = \<const0> ;
  assign cfg_dcommand2[6] = \<const0> ;
  assign cfg_dcommand2[5] = \<const0> ;
  assign cfg_dcommand2[4] = \<const0> ;
  assign cfg_dcommand2[3] = \<const0> ;
  assign cfg_dcommand2[2] = \<const0> ;
  assign cfg_dcommand2[1] = \<const0> ;
  assign cfg_dcommand2[0] = \<const0> ;
  assign cfg_dstatus[15] = \<const0> ;
  assign cfg_dstatus[14] = \<const0> ;
  assign cfg_dstatus[13] = \<const0> ;
  assign cfg_dstatus[12] = \<const0> ;
  assign cfg_dstatus[11] = \<const0> ;
  assign cfg_dstatus[10] = \<const0> ;
  assign cfg_dstatus[9] = \<const0> ;
  assign cfg_dstatus[8] = \<const0> ;
  assign cfg_dstatus[7] = \<const0> ;
  assign cfg_dstatus[6] = \<const0> ;
  assign cfg_dstatus[5] = \<const0> ;
  assign cfg_dstatus[4] = \<const0> ;
  assign cfg_dstatus[3] = \<const0> ;
  assign cfg_dstatus[2] = \<const0> ;
  assign cfg_dstatus[1] = \<const0> ;
  assign cfg_dstatus[0] = \<const0> ;
  assign cfg_err_aer_headerlog_set = \<const0> ;
  assign cfg_err_cpl_rdy = \<const0> ;
  assign cfg_interrupt_do[7] = \<const0> ;
  assign cfg_interrupt_do[6] = \<const0> ;
  assign cfg_interrupt_do[5] = \<const0> ;
  assign cfg_interrupt_do[4] = \<const0> ;
  assign cfg_interrupt_do[3] = \<const0> ;
  assign cfg_interrupt_do[2] = \<const0> ;
  assign cfg_interrupt_do[1] = \<const0> ;
  assign cfg_interrupt_do[0] = \<const0> ;
  assign cfg_interrupt_msixenable = \<const0> ;
  assign cfg_interrupt_msixfm = \<const0> ;
  assign cfg_lcommand[15] = \<const0> ;
  assign cfg_lcommand[14] = \<const0> ;
  assign cfg_lcommand[13] = \<const0> ;
  assign cfg_lcommand[12] = \<const0> ;
  assign cfg_lcommand[11] = \<const0> ;
  assign cfg_lcommand[10] = \<const0> ;
  assign cfg_lcommand[9] = \<const0> ;
  assign cfg_lcommand[8] = \<const0> ;
  assign cfg_lcommand[7] = \<const0> ;
  assign cfg_lcommand[6] = \<const0> ;
  assign cfg_lcommand[5] = \<const0> ;
  assign cfg_lcommand[4] = \<const0> ;
  assign cfg_lcommand[3] = \<const0> ;
  assign cfg_lcommand[2] = \<const0> ;
  assign cfg_lcommand[1] = \<const0> ;
  assign cfg_lcommand[0] = \<const0> ;
  assign cfg_lstatus[15] = \<const0> ;
  assign cfg_lstatus[14] = \<const0> ;
  assign cfg_lstatus[13] = \<const0> ;
  assign cfg_lstatus[12] = \<const0> ;
  assign cfg_lstatus[11] = \<const0> ;
  assign cfg_lstatus[10] = \<const0> ;
  assign cfg_lstatus[9] = \<const0> ;
  assign cfg_lstatus[8] = \<const0> ;
  assign cfg_lstatus[7] = \<const0> ;
  assign cfg_lstatus[6] = \<const0> ;
  assign cfg_lstatus[5] = \<const0> ;
  assign cfg_lstatus[4] = \<const0> ;
  assign cfg_lstatus[3] = \<const0> ;
  assign cfg_lstatus[2] = \<const0> ;
  assign cfg_lstatus[1] = \<const0> ;
  assign cfg_lstatus[0] = \<const0> ;
  assign cfg_msg_data[15] = \<const0> ;
  assign cfg_msg_data[14] = \<const0> ;
  assign cfg_msg_data[13] = \<const0> ;
  assign cfg_msg_data[12] = \<const0> ;
  assign cfg_msg_data[11] = \<const0> ;
  assign cfg_msg_data[10] = \<const0> ;
  assign cfg_msg_data[9] = \<const0> ;
  assign cfg_msg_data[8] = \<const0> ;
  assign cfg_msg_data[7] = \<const0> ;
  assign cfg_msg_data[6] = \<const0> ;
  assign cfg_msg_data[5] = \<const0> ;
  assign cfg_msg_data[4] = \<const0> ;
  assign cfg_msg_data[3] = \<const0> ;
  assign cfg_msg_data[2] = \<const0> ;
  assign cfg_msg_data[1] = \<const0> ;
  assign cfg_msg_data[0] = \<const0> ;
  assign cfg_msg_received = \<const0> ;
  assign cfg_msg_received_assert_int_a = \<const0> ;
  assign cfg_msg_received_assert_int_b = \<const0> ;
  assign cfg_msg_received_assert_int_c = \<const0> ;
  assign cfg_msg_received_assert_int_d = \<const0> ;
  assign cfg_msg_received_deassert_int_a = \<const0> ;
  assign cfg_msg_received_deassert_int_b = \<const0> ;
  assign cfg_msg_received_deassert_int_c = \<const0> ;
  assign cfg_msg_received_deassert_int_d = \<const0> ;
  assign cfg_msg_received_err_cor = \<const0> ;
  assign cfg_msg_received_err_fatal = \<const0> ;
  assign cfg_msg_received_err_non_fatal = \<const0> ;
  assign cfg_msg_received_pm_as_nak = \<const0> ;
  assign cfg_msg_received_pm_pme = \<const0> ;
  assign cfg_msg_received_pme_to_ack = \<const0> ;
  assign cfg_msg_received_setslotpowerlimit = \<const0> ;
  assign cfg_pcie_link_state[2] = \<const0> ;
  assign cfg_pcie_link_state[1] = \<const0> ;
  assign cfg_pcie_link_state[0] = \<const0> ;
  assign cfg_pmcsr_pme_en = \<const0> ;
  assign cfg_pmcsr_pme_status = \<const0> ;
  assign cfg_pmcsr_powerstate[1] = \<const0> ;
  assign cfg_pmcsr_powerstate[0] = \<const0> ;
  assign cfg_received_func_lvl_rst = \<const0> ;
  assign cfg_root_control_pme_int_en = \<const0> ;
  assign cfg_root_control_syserr_corr_err_en = \<const0> ;
  assign cfg_root_control_syserr_fatal_err_en = \<const0> ;
  assign cfg_root_control_syserr_non_fatal_err_en = \<const0> ;
  assign cfg_slot_control_electromech_il_ctl_pulse = \<const0> ;
  assign cfg_status[15] = \<const0> ;
  assign cfg_status[14] = \<const0> ;
  assign cfg_status[13] = \<const0> ;
  assign cfg_status[12] = \<const0> ;
  assign cfg_status[11] = \<const0> ;
  assign cfg_status[10] = \<const0> ;
  assign cfg_status[9] = \<const0> ;
  assign cfg_status[8] = \<const0> ;
  assign cfg_status[7] = \<const0> ;
  assign cfg_status[6] = \<const0> ;
  assign cfg_status[5] = \<const0> ;
  assign cfg_status[4] = \<const0> ;
  assign cfg_status[3] = \<const0> ;
  assign cfg_status[2] = \<const0> ;
  assign cfg_status[1] = \<const0> ;
  assign cfg_status[0] = \<const0> ;
  assign cfg_vc_tcvc_map[6] = \<const0> ;
  assign cfg_vc_tcvc_map[5] = \<const0> ;
  assign cfg_vc_tcvc_map[4] = \<const0> ;
  assign cfg_vc_tcvc_map[3] = \<const0> ;
  assign cfg_vc_tcvc_map[2] = \<const0> ;
  assign cfg_vc_tcvc_map[1] = \<const0> ;
  assign cfg_vc_tcvc_map[0] = \<const0> ;
  assign common_commands_out[11] = \<const0> ;
  assign common_commands_out[10] = \<const0> ;
  assign common_commands_out[9] = \<const0> ;
  assign common_commands_out[8] = \<const0> ;
  assign common_commands_out[7] = \<const0> ;
  assign common_commands_out[6] = \<const0> ;
  assign common_commands_out[5] = \<const0> ;
  assign common_commands_out[4] = \<const0> ;
  assign common_commands_out[3] = \<const0> ;
  assign common_commands_out[2] = \<const0> ;
  assign common_commands_out[1] = \<const0> ;
  assign common_commands_out[0] = \<const0> ;
  assign ext_ch_gt_drpclk = \<const0> ;
  assign ext_ch_gt_drpdo[31] = \<const0> ;
  assign ext_ch_gt_drpdo[30] = \<const0> ;
  assign ext_ch_gt_drpdo[29] = \<const0> ;
  assign ext_ch_gt_drpdo[28] = \<const0> ;
  assign ext_ch_gt_drpdo[27] = \<const0> ;
  assign ext_ch_gt_drpdo[26] = \<const0> ;
  assign ext_ch_gt_drpdo[25] = \<const0> ;
  assign ext_ch_gt_drpdo[24] = \<const0> ;
  assign ext_ch_gt_drpdo[23] = \<const0> ;
  assign ext_ch_gt_drpdo[22] = \<const0> ;
  assign ext_ch_gt_drpdo[21] = \<const0> ;
  assign ext_ch_gt_drpdo[20] = \<const0> ;
  assign ext_ch_gt_drpdo[19] = \<const0> ;
  assign ext_ch_gt_drpdo[18] = \<const0> ;
  assign ext_ch_gt_drpdo[17] = \<const0> ;
  assign ext_ch_gt_drpdo[16] = \<const0> ;
  assign ext_ch_gt_drpdo[15] = \<const0> ;
  assign ext_ch_gt_drpdo[14] = \<const0> ;
  assign ext_ch_gt_drpdo[13] = \<const0> ;
  assign ext_ch_gt_drpdo[12] = \<const0> ;
  assign ext_ch_gt_drpdo[11] = \<const0> ;
  assign ext_ch_gt_drpdo[10] = \<const0> ;
  assign ext_ch_gt_drpdo[9] = \<const0> ;
  assign ext_ch_gt_drpdo[8] = \<const0> ;
  assign ext_ch_gt_drpdo[7] = \<const0> ;
  assign ext_ch_gt_drpdo[6] = \<const0> ;
  assign ext_ch_gt_drpdo[5] = \<const0> ;
  assign ext_ch_gt_drpdo[4] = \<const0> ;
  assign ext_ch_gt_drpdo[3] = \<const0> ;
  assign ext_ch_gt_drpdo[2] = \<const0> ;
  assign ext_ch_gt_drpdo[1] = \<const0> ;
  assign ext_ch_gt_drpdo[0] = \<const0> ;
  assign ext_ch_gt_drprdy[1] = \<const0> ;
  assign ext_ch_gt_drprdy[0] = \<const0> ;
  assign fc_cpld[11] = \<const0> ;
  assign fc_cpld[10] = \<const0> ;
  assign fc_cpld[9] = \<const0> ;
  assign fc_cpld[8] = \<const0> ;
  assign fc_cpld[7] = \<const0> ;
  assign fc_cpld[6] = \<const0> ;
  assign fc_cpld[5] = \<const0> ;
  assign fc_cpld[4] = \<const0> ;
  assign fc_cpld[3] = \<const0> ;
  assign fc_cpld[2] = \<const0> ;
  assign fc_cpld[1] = \<const0> ;
  assign fc_cpld[0] = \<const0> ;
  assign fc_cplh[7] = \<const0> ;
  assign fc_cplh[6] = \<const0> ;
  assign fc_cplh[5] = \<const0> ;
  assign fc_cplh[4] = \<const0> ;
  assign fc_cplh[3] = \<const0> ;
  assign fc_cplh[2] = \<const0> ;
  assign fc_cplh[1] = \<const0> ;
  assign fc_cplh[0] = \<const0> ;
  assign fc_npd[11] = \<const0> ;
  assign fc_npd[10] = \<const0> ;
  assign fc_npd[9] = \<const0> ;
  assign fc_npd[8] = \<const0> ;
  assign fc_npd[7] = \<const0> ;
  assign fc_npd[6] = \<const0> ;
  assign fc_npd[5] = \<const0> ;
  assign fc_npd[4] = \<const0> ;
  assign fc_npd[3] = \<const0> ;
  assign fc_npd[2] = \<const0> ;
  assign fc_npd[1] = \<const0> ;
  assign fc_npd[0] = \<const0> ;
  assign fc_pd[11] = \<const0> ;
  assign fc_pd[10] = \<const0> ;
  assign fc_pd[9] = \<const0> ;
  assign fc_pd[8] = \<const0> ;
  assign fc_pd[7] = \<const0> ;
  assign fc_pd[6] = \<const0> ;
  assign fc_pd[5] = \<const0> ;
  assign fc_pd[4] = \<const0> ;
  assign fc_pd[3] = \<const0> ;
  assign fc_pd[2] = \<const0> ;
  assign fc_pd[1] = \<const0> ;
  assign fc_pd[0] = \<const0> ;
  assign fc_ph[7] = \<const0> ;
  assign fc_ph[6] = \<const0> ;
  assign fc_ph[5] = \<const0> ;
  assign fc_ph[4] = \<const0> ;
  assign fc_ph[3] = \<const0> ;
  assign fc_ph[2] = \<const0> ;
  assign fc_ph[1] = \<const0> ;
  assign fc_ph[0] = \<const0> ;
  assign gt_ch_drp_rdy[1] = \<const0> ;
  assign gt_ch_drp_rdy[0] = \<const0> ;
  assign icap_o[31] = \<const0> ;
  assign icap_o[30] = \<const0> ;
  assign icap_o[29] = \<const0> ;
  assign icap_o[28] = \<const0> ;
  assign icap_o[27] = \<const0> ;
  assign icap_o[26] = \<const0> ;
  assign icap_o[25] = \<const0> ;
  assign icap_o[24] = \<const0> ;
  assign icap_o[23] = \<const0> ;
  assign icap_o[22] = \<const0> ;
  assign icap_o[21] = \<const0> ;
  assign icap_o[20] = \<const0> ;
  assign icap_o[19] = \<const0> ;
  assign icap_o[18] = \<const0> ;
  assign icap_o[17] = \<const0> ;
  assign icap_o[16] = \<const0> ;
  assign icap_o[15] = \<const0> ;
  assign icap_o[14] = \<const0> ;
  assign icap_o[13] = \<const0> ;
  assign icap_o[12] = \<const0> ;
  assign icap_o[11] = \<const0> ;
  assign icap_o[10] = \<const0> ;
  assign icap_o[9] = \<const0> ;
  assign icap_o[8] = \<const0> ;
  assign icap_o[7] = \<const0> ;
  assign icap_o[6] = \<const0> ;
  assign icap_o[5] = \<const0> ;
  assign icap_o[4] = \<const0> ;
  assign icap_o[3] = \<const0> ;
  assign icap_o[2] = \<const0> ;
  assign icap_o[1] = \<const0> ;
  assign icap_o[0] = \<const0> ;
  assign int_dclk_out = \<const0> ;
  assign int_mmcm_lock_out = \<const0> ;
  assign int_oobclk_out = \<const0> ;
  assign int_pclk_out_slave = \<const0> ;
  assign int_pipe_rxusrclk_out = \<const0> ;
  assign int_qplllock_out[1] = \<const0> ;
  assign int_qplllock_out[0] = \<const0> ;
  assign int_qplloutclk_out[1] = \<const0> ;
  assign int_qplloutclk_out[0] = \<const0> ;
  assign int_qplloutrefclk_out[1] = \<const0> ;
  assign int_qplloutrefclk_out[0] = \<const0> ;
  assign int_rxoutclk_out[1] = \<const0> ;
  assign int_rxoutclk_out[0] = \<const0> ;
  assign int_userclk1_out = \<const0> ;
  assign int_userclk2_out = \<const0> ;
  assign m_axis_rx_tkeep[7] = \^m_axis_rx_tkeep [5];
  assign m_axis_rx_tkeep[6] = \^m_axis_rx_tkeep [5];
  assign m_axis_rx_tkeep[5] = \^m_axis_rx_tkeep [5];
  assign m_axis_rx_tkeep[4] = \^m_axis_rx_tkeep [5];
  assign m_axis_rx_tkeep[3] = \<const0> ;
  assign m_axis_rx_tkeep[2] = \<const0> ;
  assign m_axis_rx_tkeep[1] = \<const0> ;
  assign m_axis_rx_tkeep[0] = \<const0> ;
  assign m_axis_rx_tuser[21] = \^m_axis_rx_tuser [21];
  assign m_axis_rx_tuser[20] = \<const0> ;
  assign m_axis_rx_tuser[19] = \^m_axis_rx_tuser [19];
  assign m_axis_rx_tuser[18] = \^m_axis_rx_tuser [17];
  assign m_axis_rx_tuser[17] = \^m_axis_rx_tuser [17];
  assign m_axis_rx_tuser[16] = \<const0> ;
  assign m_axis_rx_tuser[15] = \<const0> ;
  assign m_axis_rx_tuser[14] = \^m_axis_rx_tuser [14];
  assign m_axis_rx_tuser[13] = \<const0> ;
  assign m_axis_rx_tuser[12] = \<const0> ;
  assign m_axis_rx_tuser[11] = \<const0> ;
  assign m_axis_rx_tuser[10] = \<const0> ;
  assign m_axis_rx_tuser[9] = \<const0> ;
  assign m_axis_rx_tuser[8:0] = \^m_axis_rx_tuser [8:0];
  assign pcie_drp_do[15] = \<const0> ;
  assign pcie_drp_do[14] = \<const0> ;
  assign pcie_drp_do[13] = \<const0> ;
  assign pcie_drp_do[12] = \<const0> ;
  assign pcie_drp_do[11] = \<const0> ;
  assign pcie_drp_do[10] = \<const0> ;
  assign pcie_drp_do[9] = \<const0> ;
  assign pcie_drp_do[8] = \<const0> ;
  assign pcie_drp_do[7] = \<const0> ;
  assign pcie_drp_do[6] = \<const0> ;
  assign pcie_drp_do[5] = \<const0> ;
  assign pcie_drp_do[4] = \<const0> ;
  assign pcie_drp_do[3] = \<const0> ;
  assign pcie_drp_do[2] = \<const0> ;
  assign pcie_drp_do[1] = \<const0> ;
  assign pcie_drp_do[0] = \<const0> ;
  assign pcie_drp_rdy = \<const0> ;
  assign pipe_cpll_lock[1] = \<const0> ;
  assign pipe_cpll_lock[0] = \<const0> ;
  assign pipe_debug[31] = \<const0> ;
  assign pipe_debug[30] = \<const0> ;
  assign pipe_debug[29] = \<const0> ;
  assign pipe_debug[28] = \<const0> ;
  assign pipe_debug[27] = \<const0> ;
  assign pipe_debug[26] = \<const0> ;
  assign pipe_debug[25] = \<const0> ;
  assign pipe_debug[24] = \<const0> ;
  assign pipe_debug[23] = \<const0> ;
  assign pipe_debug[22] = \<const0> ;
  assign pipe_debug[21] = \<const0> ;
  assign pipe_debug[20] = \<const0> ;
  assign pipe_debug[19] = \<const0> ;
  assign pipe_debug[18] = \<const0> ;
  assign pipe_debug[17] = \<const0> ;
  assign pipe_debug[16] = \<const0> ;
  assign pipe_debug[15] = \<const0> ;
  assign pipe_debug[14] = \<const0> ;
  assign pipe_debug[13] = \<const0> ;
  assign pipe_debug[12] = \<const0> ;
  assign pipe_debug[11] = \<const0> ;
  assign pipe_debug[10] = \<const0> ;
  assign pipe_debug[9] = \<const0> ;
  assign pipe_debug[8] = \<const0> ;
  assign pipe_debug[7] = \<const0> ;
  assign pipe_debug[6] = \<const0> ;
  assign pipe_debug[5] = \<const0> ;
  assign pipe_debug[4] = \<const0> ;
  assign pipe_debug[3] = \<const0> ;
  assign pipe_debug[2] = \<const0> ;
  assign pipe_debug[1] = \<const0> ;
  assign pipe_debug[0] = \<const0> ;
  assign pipe_debug_0[1] = \<const0> ;
  assign pipe_debug_0[0] = \<const0> ;
  assign pipe_debug_1[1] = \<const0> ;
  assign pipe_debug_1[0] = \<const0> ;
  assign pipe_debug_2[1] = \<const0> ;
  assign pipe_debug_2[0] = \<const0> ;
  assign pipe_debug_3[1] = \<const0> ;
  assign pipe_debug_3[0] = \<const0> ;
  assign pipe_debug_4[1] = \<const0> ;
  assign pipe_debug_4[0] = \<const0> ;
  assign pipe_debug_5[1] = \<const0> ;
  assign pipe_debug_5[0] = \<const0> ;
  assign pipe_debug_6[1] = \<const0> ;
  assign pipe_debug_6[0] = \<const0> ;
  assign pipe_debug_7[1] = \<const0> ;
  assign pipe_debug_7[0] = \<const0> ;
  assign pipe_debug_8[1] = \<const0> ;
  assign pipe_debug_8[0] = \<const0> ;
  assign pipe_debug_9[1] = \<const0> ;
  assign pipe_debug_9[0] = \<const0> ;
  assign pipe_dmonitorout[29] = \<const0> ;
  assign pipe_dmonitorout[28] = \<const0> ;
  assign pipe_dmonitorout[27] = \<const0> ;
  assign pipe_dmonitorout[26] = \<const0> ;
  assign pipe_dmonitorout[25] = \<const0> ;
  assign pipe_dmonitorout[24] = \<const0> ;
  assign pipe_dmonitorout[23] = \<const0> ;
  assign pipe_dmonitorout[22] = \<const0> ;
  assign pipe_dmonitorout[21] = \<const0> ;
  assign pipe_dmonitorout[20] = \<const0> ;
  assign pipe_dmonitorout[19] = \<const0> ;
  assign pipe_dmonitorout[18] = \<const0> ;
  assign pipe_dmonitorout[17] = \<const0> ;
  assign pipe_dmonitorout[16] = \<const0> ;
  assign pipe_dmonitorout[15] = \<const0> ;
  assign pipe_dmonitorout[14] = \<const0> ;
  assign pipe_dmonitorout[13] = \<const0> ;
  assign pipe_dmonitorout[12] = \<const0> ;
  assign pipe_dmonitorout[11] = \<const0> ;
  assign pipe_dmonitorout[10] = \<const0> ;
  assign pipe_dmonitorout[9] = \<const0> ;
  assign pipe_dmonitorout[8] = \<const0> ;
  assign pipe_dmonitorout[7] = \<const0> ;
  assign pipe_dmonitorout[6] = \<const0> ;
  assign pipe_dmonitorout[5] = \<const0> ;
  assign pipe_dmonitorout[4] = \<const0> ;
  assign pipe_dmonitorout[3] = \<const0> ;
  assign pipe_dmonitorout[2] = \<const0> ;
  assign pipe_dmonitorout[1] = \<const0> ;
  assign pipe_dmonitorout[0] = \<const0> ;
  assign pipe_drp_fsm[13] = \<const0> ;
  assign pipe_drp_fsm[12] = \<const0> ;
  assign pipe_drp_fsm[11] = \<const0> ;
  assign pipe_drp_fsm[10] = \<const0> ;
  assign pipe_drp_fsm[9] = \<const0> ;
  assign pipe_drp_fsm[8] = \<const0> ;
  assign pipe_drp_fsm[7] = \<const0> ;
  assign pipe_drp_fsm[6] = \<const0> ;
  assign pipe_drp_fsm[5] = \<const0> ;
  assign pipe_drp_fsm[4] = \<const0> ;
  assign pipe_drp_fsm[3] = \<const0> ;
  assign pipe_drp_fsm[2] = \<const0> ;
  assign pipe_drp_fsm[1] = \<const0> ;
  assign pipe_drp_fsm[0] = \<const0> ;
  assign pipe_eyescandataerror[1] = \<const0> ;
  assign pipe_eyescandataerror[0] = \<const0> ;
  assign pipe_gen3_out = \<const0> ;
  assign pipe_pclk_sel_out[1] = \<const0> ;
  assign pipe_pclk_sel_out[0] = \<const0> ;
  assign pipe_qpll_lock[0] = \<const0> ;
  assign pipe_qrst_fsm[11] = \<const0> ;
  assign pipe_qrst_fsm[10] = \<const0> ;
  assign pipe_qrst_fsm[9] = \<const0> ;
  assign pipe_qrst_fsm[8] = \<const0> ;
  assign pipe_qrst_fsm[7] = \<const0> ;
  assign pipe_qrst_fsm[6] = \<const0> ;
  assign pipe_qrst_fsm[5] = \<const0> ;
  assign pipe_qrst_fsm[4] = \<const0> ;
  assign pipe_qrst_fsm[3] = \<const0> ;
  assign pipe_qrst_fsm[2] = \<const0> ;
  assign pipe_qrst_fsm[1] = \<const0> ;
  assign pipe_qrst_fsm[0] = \<const0> ;
  assign pipe_qrst_idle = \<const0> ;
  assign pipe_rate_fsm[9] = \<const0> ;
  assign pipe_rate_fsm[8] = \<const0> ;
  assign pipe_rate_fsm[7] = \<const0> ;
  assign pipe_rate_fsm[6] = \<const0> ;
  assign pipe_rate_fsm[5] = \<const0> ;
  assign pipe_rate_fsm[4] = \<const0> ;
  assign pipe_rate_fsm[3] = \<const0> ;
  assign pipe_rate_fsm[2] = \<const0> ;
  assign pipe_rate_fsm[1] = \<const0> ;
  assign pipe_rate_fsm[0] = \<const0> ;
  assign pipe_rate_idle = \<const0> ;
  assign pipe_rst_fsm[4] = \<const0> ;
  assign pipe_rst_fsm[3] = \<const0> ;
  assign pipe_rst_fsm[2] = \<const0> ;
  assign pipe_rst_fsm[1] = \<const0> ;
  assign pipe_rst_fsm[0] = \<const0> ;
  assign pipe_rst_idle = \<const0> ;
  assign pipe_rxbufstatus[5] = \<const0> ;
  assign pipe_rxbufstatus[4] = \<const0> ;
  assign pipe_rxbufstatus[3] = \<const0> ;
  assign pipe_rxbufstatus[2] = \<const0> ;
  assign pipe_rxbufstatus[1] = \<const0> ;
  assign pipe_rxbufstatus[0] = \<const0> ;
  assign pipe_rxcommadet[1] = \<const0> ;
  assign pipe_rxcommadet[0] = \<const0> ;
  assign pipe_rxdisperr[15] = \<const0> ;
  assign pipe_rxdisperr[14] = \<const0> ;
  assign pipe_rxdisperr[13] = \<const0> ;
  assign pipe_rxdisperr[12] = \<const0> ;
  assign pipe_rxdisperr[11] = \<const0> ;
  assign pipe_rxdisperr[10] = \<const0> ;
  assign pipe_rxdisperr[9] = \<const0> ;
  assign pipe_rxdisperr[8] = \<const0> ;
  assign pipe_rxdisperr[7] = \<const0> ;
  assign pipe_rxdisperr[6] = \<const0> ;
  assign pipe_rxdisperr[5] = \<const0> ;
  assign pipe_rxdisperr[4] = \<const0> ;
  assign pipe_rxdisperr[3] = \<const0> ;
  assign pipe_rxdisperr[2] = \<const0> ;
  assign pipe_rxdisperr[1] = \<const0> ;
  assign pipe_rxdisperr[0] = \<const0> ;
  assign pipe_rxdlysresetdone[1] = \<const0> ;
  assign pipe_rxdlysresetdone[0] = \<const0> ;
  assign pipe_rxnotintable[15] = \<const0> ;
  assign pipe_rxnotintable[14] = \<const0> ;
  assign pipe_rxnotintable[13] = \<const0> ;
  assign pipe_rxnotintable[12] = \<const0> ;
  assign pipe_rxnotintable[11] = \<const0> ;
  assign pipe_rxnotintable[10] = \<const0> ;
  assign pipe_rxnotintable[9] = \<const0> ;
  assign pipe_rxnotintable[8] = \<const0> ;
  assign pipe_rxnotintable[7] = \<const0> ;
  assign pipe_rxnotintable[6] = \<const0> ;
  assign pipe_rxnotintable[5] = \<const0> ;
  assign pipe_rxnotintable[4] = \<const0> ;
  assign pipe_rxnotintable[3] = \<const0> ;
  assign pipe_rxnotintable[2] = \<const0> ;
  assign pipe_rxnotintable[1] = \<const0> ;
  assign pipe_rxnotintable[0] = \<const0> ;
  assign pipe_rxoutclk_out[1] = \<const0> ;
  assign pipe_rxoutclk_out[0] = \<const0> ;
  assign pipe_rxphaligndone[1] = \<const0> ;
  assign pipe_rxphaligndone[0] = \<const0> ;
  assign pipe_rxpmaresetdone[1] = \<const0> ;
  assign pipe_rxpmaresetdone[0] = \<const0> ;
  assign pipe_rxprbserr[1] = \<const0> ;
  assign pipe_rxprbserr[0] = \<const0> ;
  assign pipe_rxstatus[5] = \<const0> ;
  assign pipe_rxstatus[4] = \<const0> ;
  assign pipe_rxstatus[3] = \<const0> ;
  assign pipe_rxstatus[2] = \<const0> ;
  assign pipe_rxstatus[1] = \<const0> ;
  assign pipe_rxstatus[0] = \<const0> ;
  assign pipe_rxsyncdone[1] = \<const0> ;
  assign pipe_rxsyncdone[0] = \<const0> ;
  assign pipe_sync_fsm_rx[13] = \<const0> ;
  assign pipe_sync_fsm_rx[12] = \<const0> ;
  assign pipe_sync_fsm_rx[11] = \<const0> ;
  assign pipe_sync_fsm_rx[10] = \<const0> ;
  assign pipe_sync_fsm_rx[9] = \<const0> ;
  assign pipe_sync_fsm_rx[8] = \<const0> ;
  assign pipe_sync_fsm_rx[7] = \<const0> ;
  assign pipe_sync_fsm_rx[6] = \<const0> ;
  assign pipe_sync_fsm_rx[5] = \<const0> ;
  assign pipe_sync_fsm_rx[4] = \<const0> ;
  assign pipe_sync_fsm_rx[3] = \<const0> ;
  assign pipe_sync_fsm_rx[2] = \<const0> ;
  assign pipe_sync_fsm_rx[1] = \<const0> ;
  assign pipe_sync_fsm_rx[0] = \<const0> ;
  assign pipe_sync_fsm_tx[11] = \<const0> ;
  assign pipe_sync_fsm_tx[10] = \<const0> ;
  assign pipe_sync_fsm_tx[9] = \<const0> ;
  assign pipe_sync_fsm_tx[8] = \<const0> ;
  assign pipe_sync_fsm_tx[7] = \<const0> ;
  assign pipe_sync_fsm_tx[6] = \<const0> ;
  assign pipe_sync_fsm_tx[5] = \<const0> ;
  assign pipe_sync_fsm_tx[4] = \<const0> ;
  assign pipe_sync_fsm_tx[3] = \<const0> ;
  assign pipe_sync_fsm_tx[2] = \<const0> ;
  assign pipe_sync_fsm_tx[1] = \<const0> ;
  assign pipe_sync_fsm_tx[0] = \<const0> ;
  assign pipe_tx_0_sigs[24] = \<const0> ;
  assign pipe_tx_0_sigs[23] = \<const0> ;
  assign pipe_tx_0_sigs[22] = \<const0> ;
  assign pipe_tx_0_sigs[21] = \<const0> ;
  assign pipe_tx_0_sigs[20] = \<const0> ;
  assign pipe_tx_0_sigs[19] = \<const0> ;
  assign pipe_tx_0_sigs[18] = \<const0> ;
  assign pipe_tx_0_sigs[17] = \<const0> ;
  assign pipe_tx_0_sigs[16] = \<const0> ;
  assign pipe_tx_0_sigs[15] = \<const0> ;
  assign pipe_tx_0_sigs[14] = \<const0> ;
  assign pipe_tx_0_sigs[13] = \<const0> ;
  assign pipe_tx_0_sigs[12] = \<const0> ;
  assign pipe_tx_0_sigs[11] = \<const0> ;
  assign pipe_tx_0_sigs[10] = \<const0> ;
  assign pipe_tx_0_sigs[9] = \<const0> ;
  assign pipe_tx_0_sigs[8] = \<const0> ;
  assign pipe_tx_0_sigs[7] = \<const0> ;
  assign pipe_tx_0_sigs[6] = \<const0> ;
  assign pipe_tx_0_sigs[5] = \<const0> ;
  assign pipe_tx_0_sigs[4] = \<const0> ;
  assign pipe_tx_0_sigs[3] = \<const0> ;
  assign pipe_tx_0_sigs[2] = \<const0> ;
  assign pipe_tx_0_sigs[1] = \<const0> ;
  assign pipe_tx_0_sigs[0] = \<const0> ;
  assign pipe_tx_1_sigs[24] = \<const0> ;
  assign pipe_tx_1_sigs[23] = \<const0> ;
  assign pipe_tx_1_sigs[22] = \<const0> ;
  assign pipe_tx_1_sigs[21] = \<const0> ;
  assign pipe_tx_1_sigs[20] = \<const0> ;
  assign pipe_tx_1_sigs[19] = \<const0> ;
  assign pipe_tx_1_sigs[18] = \<const0> ;
  assign pipe_tx_1_sigs[17] = \<const0> ;
  assign pipe_tx_1_sigs[16] = \<const0> ;
  assign pipe_tx_1_sigs[15] = \<const0> ;
  assign pipe_tx_1_sigs[14] = \<const0> ;
  assign pipe_tx_1_sigs[13] = \<const0> ;
  assign pipe_tx_1_sigs[12] = \<const0> ;
  assign pipe_tx_1_sigs[11] = \<const0> ;
  assign pipe_tx_1_sigs[10] = \<const0> ;
  assign pipe_tx_1_sigs[9] = \<const0> ;
  assign pipe_tx_1_sigs[8] = \<const0> ;
  assign pipe_tx_1_sigs[7] = \<const0> ;
  assign pipe_tx_1_sigs[6] = \<const0> ;
  assign pipe_tx_1_sigs[5] = \<const0> ;
  assign pipe_tx_1_sigs[4] = \<const0> ;
  assign pipe_tx_1_sigs[3] = \<const0> ;
  assign pipe_tx_1_sigs[2] = \<const0> ;
  assign pipe_tx_1_sigs[1] = \<const0> ;
  assign pipe_tx_1_sigs[0] = \<const0> ;
  assign pipe_tx_2_sigs[24] = \<const0> ;
  assign pipe_tx_2_sigs[23] = \<const0> ;
  assign pipe_tx_2_sigs[22] = \<const0> ;
  assign pipe_tx_2_sigs[21] = \<const0> ;
  assign pipe_tx_2_sigs[20] = \<const0> ;
  assign pipe_tx_2_sigs[19] = \<const0> ;
  assign pipe_tx_2_sigs[18] = \<const0> ;
  assign pipe_tx_2_sigs[17] = \<const0> ;
  assign pipe_tx_2_sigs[16] = \<const0> ;
  assign pipe_tx_2_sigs[15] = \<const0> ;
  assign pipe_tx_2_sigs[14] = \<const0> ;
  assign pipe_tx_2_sigs[13] = \<const0> ;
  assign pipe_tx_2_sigs[12] = \<const0> ;
  assign pipe_tx_2_sigs[11] = \<const0> ;
  assign pipe_tx_2_sigs[10] = \<const0> ;
  assign pipe_tx_2_sigs[9] = \<const0> ;
  assign pipe_tx_2_sigs[8] = \<const0> ;
  assign pipe_tx_2_sigs[7] = \<const0> ;
  assign pipe_tx_2_sigs[6] = \<const0> ;
  assign pipe_tx_2_sigs[5] = \<const0> ;
  assign pipe_tx_2_sigs[4] = \<const0> ;
  assign pipe_tx_2_sigs[3] = \<const0> ;
  assign pipe_tx_2_sigs[2] = \<const0> ;
  assign pipe_tx_2_sigs[1] = \<const0> ;
  assign pipe_tx_2_sigs[0] = \<const0> ;
  assign pipe_tx_3_sigs[24] = \<const0> ;
  assign pipe_tx_3_sigs[23] = \<const0> ;
  assign pipe_tx_3_sigs[22] = \<const0> ;
  assign pipe_tx_3_sigs[21] = \<const0> ;
  assign pipe_tx_3_sigs[20] = \<const0> ;
  assign pipe_tx_3_sigs[19] = \<const0> ;
  assign pipe_tx_3_sigs[18] = \<const0> ;
  assign pipe_tx_3_sigs[17] = \<const0> ;
  assign pipe_tx_3_sigs[16] = \<const0> ;
  assign pipe_tx_3_sigs[15] = \<const0> ;
  assign pipe_tx_3_sigs[14] = \<const0> ;
  assign pipe_tx_3_sigs[13] = \<const0> ;
  assign pipe_tx_3_sigs[12] = \<const0> ;
  assign pipe_tx_3_sigs[11] = \<const0> ;
  assign pipe_tx_3_sigs[10] = \<const0> ;
  assign pipe_tx_3_sigs[9] = \<const0> ;
  assign pipe_tx_3_sigs[8] = \<const0> ;
  assign pipe_tx_3_sigs[7] = \<const0> ;
  assign pipe_tx_3_sigs[6] = \<const0> ;
  assign pipe_tx_3_sigs[5] = \<const0> ;
  assign pipe_tx_3_sigs[4] = \<const0> ;
  assign pipe_tx_3_sigs[3] = \<const0> ;
  assign pipe_tx_3_sigs[2] = \<const0> ;
  assign pipe_tx_3_sigs[1] = \<const0> ;
  assign pipe_tx_3_sigs[0] = \<const0> ;
  assign pipe_tx_4_sigs[24] = \<const0> ;
  assign pipe_tx_4_sigs[23] = \<const0> ;
  assign pipe_tx_4_sigs[22] = \<const0> ;
  assign pipe_tx_4_sigs[21] = \<const0> ;
  assign pipe_tx_4_sigs[20] = \<const0> ;
  assign pipe_tx_4_sigs[19] = \<const0> ;
  assign pipe_tx_4_sigs[18] = \<const0> ;
  assign pipe_tx_4_sigs[17] = \<const0> ;
  assign pipe_tx_4_sigs[16] = \<const0> ;
  assign pipe_tx_4_sigs[15] = \<const0> ;
  assign pipe_tx_4_sigs[14] = \<const0> ;
  assign pipe_tx_4_sigs[13] = \<const0> ;
  assign pipe_tx_4_sigs[12] = \<const0> ;
  assign pipe_tx_4_sigs[11] = \<const0> ;
  assign pipe_tx_4_sigs[10] = \<const0> ;
  assign pipe_tx_4_sigs[9] = \<const0> ;
  assign pipe_tx_4_sigs[8] = \<const0> ;
  assign pipe_tx_4_sigs[7] = \<const0> ;
  assign pipe_tx_4_sigs[6] = \<const0> ;
  assign pipe_tx_4_sigs[5] = \<const0> ;
  assign pipe_tx_4_sigs[4] = \<const0> ;
  assign pipe_tx_4_sigs[3] = \<const0> ;
  assign pipe_tx_4_sigs[2] = \<const0> ;
  assign pipe_tx_4_sigs[1] = \<const0> ;
  assign pipe_tx_4_sigs[0] = \<const0> ;
  assign pipe_tx_5_sigs[24] = \<const0> ;
  assign pipe_tx_5_sigs[23] = \<const0> ;
  assign pipe_tx_5_sigs[22] = \<const0> ;
  assign pipe_tx_5_sigs[21] = \<const0> ;
  assign pipe_tx_5_sigs[20] = \<const0> ;
  assign pipe_tx_5_sigs[19] = \<const0> ;
  assign pipe_tx_5_sigs[18] = \<const0> ;
  assign pipe_tx_5_sigs[17] = \<const0> ;
  assign pipe_tx_5_sigs[16] = \<const0> ;
  assign pipe_tx_5_sigs[15] = \<const0> ;
  assign pipe_tx_5_sigs[14] = \<const0> ;
  assign pipe_tx_5_sigs[13] = \<const0> ;
  assign pipe_tx_5_sigs[12] = \<const0> ;
  assign pipe_tx_5_sigs[11] = \<const0> ;
  assign pipe_tx_5_sigs[10] = \<const0> ;
  assign pipe_tx_5_sigs[9] = \<const0> ;
  assign pipe_tx_5_sigs[8] = \<const0> ;
  assign pipe_tx_5_sigs[7] = \<const0> ;
  assign pipe_tx_5_sigs[6] = \<const0> ;
  assign pipe_tx_5_sigs[5] = \<const0> ;
  assign pipe_tx_5_sigs[4] = \<const0> ;
  assign pipe_tx_5_sigs[3] = \<const0> ;
  assign pipe_tx_5_sigs[2] = \<const0> ;
  assign pipe_tx_5_sigs[1] = \<const0> ;
  assign pipe_tx_5_sigs[0] = \<const0> ;
  assign pipe_tx_6_sigs[24] = \<const0> ;
  assign pipe_tx_6_sigs[23] = \<const0> ;
  assign pipe_tx_6_sigs[22] = \<const0> ;
  assign pipe_tx_6_sigs[21] = \<const0> ;
  assign pipe_tx_6_sigs[20] = \<const0> ;
  assign pipe_tx_6_sigs[19] = \<const0> ;
  assign pipe_tx_6_sigs[18] = \<const0> ;
  assign pipe_tx_6_sigs[17] = \<const0> ;
  assign pipe_tx_6_sigs[16] = \<const0> ;
  assign pipe_tx_6_sigs[15] = \<const0> ;
  assign pipe_tx_6_sigs[14] = \<const0> ;
  assign pipe_tx_6_sigs[13] = \<const0> ;
  assign pipe_tx_6_sigs[12] = \<const0> ;
  assign pipe_tx_6_sigs[11] = \<const0> ;
  assign pipe_tx_6_sigs[10] = \<const0> ;
  assign pipe_tx_6_sigs[9] = \<const0> ;
  assign pipe_tx_6_sigs[8] = \<const0> ;
  assign pipe_tx_6_sigs[7] = \<const0> ;
  assign pipe_tx_6_sigs[6] = \<const0> ;
  assign pipe_tx_6_sigs[5] = \<const0> ;
  assign pipe_tx_6_sigs[4] = \<const0> ;
  assign pipe_tx_6_sigs[3] = \<const0> ;
  assign pipe_tx_6_sigs[2] = \<const0> ;
  assign pipe_tx_6_sigs[1] = \<const0> ;
  assign pipe_tx_6_sigs[0] = \<const0> ;
  assign pipe_tx_7_sigs[24] = \<const0> ;
  assign pipe_tx_7_sigs[23] = \<const0> ;
  assign pipe_tx_7_sigs[22] = \<const0> ;
  assign pipe_tx_7_sigs[21] = \<const0> ;
  assign pipe_tx_7_sigs[20] = \<const0> ;
  assign pipe_tx_7_sigs[19] = \<const0> ;
  assign pipe_tx_7_sigs[18] = \<const0> ;
  assign pipe_tx_7_sigs[17] = \<const0> ;
  assign pipe_tx_7_sigs[16] = \<const0> ;
  assign pipe_tx_7_sigs[15] = \<const0> ;
  assign pipe_tx_7_sigs[14] = \<const0> ;
  assign pipe_tx_7_sigs[13] = \<const0> ;
  assign pipe_tx_7_sigs[12] = \<const0> ;
  assign pipe_tx_7_sigs[11] = \<const0> ;
  assign pipe_tx_7_sigs[10] = \<const0> ;
  assign pipe_tx_7_sigs[9] = \<const0> ;
  assign pipe_tx_7_sigs[8] = \<const0> ;
  assign pipe_tx_7_sigs[7] = \<const0> ;
  assign pipe_tx_7_sigs[6] = \<const0> ;
  assign pipe_tx_7_sigs[5] = \<const0> ;
  assign pipe_tx_7_sigs[4] = \<const0> ;
  assign pipe_tx_7_sigs[3] = \<const0> ;
  assign pipe_tx_7_sigs[2] = \<const0> ;
  assign pipe_tx_7_sigs[1] = \<const0> ;
  assign pipe_tx_7_sigs[0] = \<const0> ;
  assign pipe_txdlysresetdone[1] = \<const0> ;
  assign pipe_txdlysresetdone[0] = \<const0> ;
  assign pipe_txoutclk_out = \<const0> ;
  assign pipe_txphaligndone[1] = \<const0> ;
  assign pipe_txphaligndone[0] = \<const0> ;
  assign pipe_txphinitdone[1] = \<const0> ;
  assign pipe_txphinitdone[0] = \<const0> ;
  assign pl_directed_change_done = \<const0> ;
  assign pl_initial_link_width[2] = \<const0> ;
  assign pl_initial_link_width[1] = \<const0> ;
  assign pl_initial_link_width[0] = \<const0> ;
  assign pl_lane_reversal_mode[1] = \<const0> ;
  assign pl_lane_reversal_mode[0] = \<const0> ;
  assign pl_link_gen2_cap = \<const0> ;
  assign pl_link_partner_gen2_supported = \<const0> ;
  assign pl_link_upcfg_cap = \<const0> ;
  assign pl_ltssm_state[5] = \<const0> ;
  assign pl_ltssm_state[4] = \<const0> ;
  assign pl_ltssm_state[3] = \<const0> ;
  assign pl_ltssm_state[2] = \<const0> ;
  assign pl_ltssm_state[1] = \<const0> ;
  assign pl_ltssm_state[0] = \<const0> ;
  assign pl_received_hot_rst = \<const0> ;
  assign pl_rx_pm_state[1] = \<const0> ;
  assign pl_rx_pm_state[0] = \<const0> ;
  assign pl_sel_lnk_rate = \<const0> ;
  assign pl_sel_lnk_width[1] = \<const0> ;
  assign pl_sel_lnk_width[0] = \<const0> ;
  assign pl_tx_pm_state[2] = \<const0> ;
  assign pl_tx_pm_state[1] = \<const0> ;
  assign pl_tx_pm_state[0] = \<const0> ;
  assign qpll_drp_clk = \<const0> ;
  assign qpll_drp_gen3 = \<const0> ;
  assign qpll_drp_ovrd = \<const0> ;
  assign qpll_drp_rst_n = \<const0> ;
  assign qpll_drp_start = \<const0> ;
  assign qpll_qplld = \<const0> ;
  assign qpll_qpllreset[1] = \<const0> ;
  assign qpll_qpllreset[0] = \<const0> ;
  assign startup_cfgclk = \<const0> ;
  assign startup_cfgmclk = \<const0> ;
  assign startup_eos = \<const0> ;
  assign startup_preq = \<const0> ;
  assign tx_buf_av[5] = \<const0> ;
  assign tx_buf_av[4] = \<const0> ;
  assign tx_buf_av[3] = \<const0> ;
  assign tx_buf_av[2] = \<const0> ;
  assign tx_buf_av[1] = \<const0> ;
  assign tx_buf_av[0] = \<const0> ;
  assign tx_cfg_req = \<const0> ;
  assign tx_err_drop = \<const0> ;
  assign user_app_rdy = \<const0> ;
  GND GND
       (.G(\<const0> ));
  xdma_0_pcie2_ip_core_top inst
       (.cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
        .cfg_bus_number(cfg_bus_number),
        .cfg_command(\^cfg_command ),
        .cfg_dcommand({\^cfg_dcommand [14:12],\^cfg_dcommand [7:5]}),
        .cfg_device_number(cfg_device_number),
        .cfg_dsn(cfg_dsn),
        .cfg_err_aer_headerlog(cfg_err_aer_headerlog),
        .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
        .cfg_function_number(cfg_function_number),
        .cfg_interrupt(cfg_interrupt),
        .cfg_interrupt_assert(cfg_interrupt_assert),
        .cfg_interrupt_di(cfg_interrupt_di),
        .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
        .cfg_interrupt_msienable(cfg_interrupt_msienable),
        .cfg_interrupt_rdy(cfg_interrupt_rdy),
        .cfg_mgmt_byte_en(cfg_mgmt_byte_en),
        .cfg_mgmt_di(cfg_mgmt_di),
        .cfg_mgmt_do(cfg_mgmt_do),
        .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
        .cfg_mgmt_rd_en(cfg_mgmt_rd_en),
        .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
        .cfg_mgmt_wr_en(cfg_mgmt_wr_en),
        .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
        .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
        .cfg_pm_force_state(cfg_pm_force_state),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .fc_nph(fc_nph),
        .fc_sel(fc_sel),
        .int_pclk_sel_slave(int_pclk_sel_slave),
        .int_userclk1_out(user_clk_out),
        .m_axis_rx_tdata(m_axis_rx_tdata),
        .m_axis_rx_tkeep(\^m_axis_rx_tkeep ),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser({\^m_axis_rx_tuser [21],\^m_axis_rx_tuser [19],\^m_axis_rx_tuser [17],\^m_axis_rx_tuser [14],\^m_axis_rx_tuser [8:0]}),
        .m_axis_rx_tvalid(m_axis_rx_tvalid),
        .pci_exp_rxn(pci_exp_rxn),
        .pci_exp_rxp(pci_exp_rxp),
        .pci_exp_txn(pci_exp_txn),
        .pci_exp_txp(pci_exp_txp),
        .pl_directed_link_auton(pl_directed_link_auton),
        .pl_directed_link_change(pl_directed_link_change),
        .pl_directed_link_speed(pl_directed_link_speed),
        .pl_directed_link_width(pl_directed_link_width),
        .pl_phy_lnk_up(pl_phy_lnk_up),
        .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
        .rx_np_ok(rx_np_ok),
        .rx_np_req(rx_np_req),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep(s_axis_tx_tkeep[7]),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tready(s_axis_tx_tready),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .sys_clk(sys_clk),
        .sys_rst_n(sys_rst_n),
        .tx_cfg_gnt(tx_cfg_gnt),
        .user_lnk_up(user_lnk_up),
        .user_reset_out(user_reset_out));
endmodule

module xdma_0_pcie2_ip_pcie_7x
   (user_reset_int_reg,
    src_in,
    cfg_mgmt_rd_wr_done,
    cfg_interrupt_rdy,
    E,
    trn_in_packet_reg,
    trn_reof,
    trn_rsof,
    trn_rsrc_dsc,
    pcie_block_i_0,
    cfg_pcie_link_state,
    dsc_detect,
    rsrc_rdy_filtered,
    trn_rsrc_dsc_prev0,
    tcfg_req_trig,
    trn_tcfg_req,
    pcie_block_i_1,
    trn_tbuf_av,
    tbuf_av_min_trig,
    pcie_block_i_2,
    trn_tdst_rdy,
    cfg_command,
    cfg_interrupt_msienable,
    cfg_to_turnoff,
    pipe_rx0_polarity,
    pipe_rx1_polarity,
    pipe_tx0_compliance,
    pipe_tx0_elec_idle,
    pipe_tx1_compliance,
    pipe_tx1_elec_idle,
    pipe_tx_deemph,
    pipe_tx_rate,
    pipe_tx_rcvr_det,
    pl_received_hot_rst,
    trn_lnk_up,
    trn_recrc_err,
    trn_rerrfwd,
    pcie_block_i_3,
    cfg_msg_data,
    pipe_tx0_data,
    pipe_tx1_data,
    pipe_tx0_char_is_k,
    pipe_tx0_powerdown,
    pipe_tx1_char_is_k,
    pipe_tx1_powerdown,
    pcie_block_i_4,
    cfg_dcommand,
    cfg_interrupt_mmenable,
    pipe_tx_margin,
    cfg_mgmt_do,
    pl_ltssm_state,
    fc_nph,
    trn_rbar_hit,
    bridge_reset_int,
    pl_phy_lnk_up,
    cfg_mgmt_wr_readonly,
    cfg_mgmt_wr_en,
    cfg_mgmt_rd_en,
    cfg_interrupt,
    cfg_interrupt_assert,
    trn_in_packet,
    trn_rdst_rdy,
    ppm_L1_trig,
    ppm_L1_thrtl,
    trn_rsrc_dsc_d,
    reg_dsc_detect,
    reg_tcfg_gnt,
    lnk_up_thrtl,
    out,
    CLK,
    cfg_pm_turnoff_ok_n,
    pcie_block_i_5,
    pipe_rx0_chanisaligned,
    pipe_rx0_elec_idle,
    pipe_rx0_phy_status,
    pipe_rx0_valid,
    pipe_rx1_chanisaligned,
    pipe_rx1_elec_idle,
    pipe_rx1_phy_status,
    pipe_rx1_valid,
    pl_directed_link_auton,
    pl_directed_link_speed,
    pl_upstream_prefer_deemph,
    sys_rst_n,
    rx_np_ok,
    rx_np_req,
    trn_tcfg_gnt,
    pcie_block_i_6,
    trn_teof,
    trn_tsof,
    trn_tsrc_rdy,
    cfg_err_aer_headerlog,
    trn_td,
    Q,
    pcie_block_i_7,
    cfg_pm_force_state,
    pcie_block_i_8,
    pcie_block_i_9,
    pl_directed_link_change,
    pl_directed_link_width,
    trn_trem,
    pcie_block_i_10,
    pcie_block_i_11,
    fc_sel,
    cfg_mgmt_di,
    cfg_mgmt_byte_en_n,
    cfg_err_tlp_cpl_header,
    cfg_aer_interrupt_msgnum,
    cfg_pciecap_interrupt_msgnum,
    cfg_dsn,
    cfg_interrupt_di,
    cfg_mgmt_dwaddr);
  output user_reset_int_reg;
  output src_in;
  output cfg_mgmt_rd_wr_done;
  output cfg_interrupt_rdy;
  output [0:0]E;
  output trn_in_packet_reg;
  output trn_reof;
  output trn_rsof;
  output trn_rsrc_dsc;
  output pcie_block_i_0;
  output [2:0]cfg_pcie_link_state;
  output dsc_detect;
  output rsrc_rdy_filtered;
  output trn_rsrc_dsc_prev0;
  output tcfg_req_trig;
  output trn_tcfg_req;
  output pcie_block_i_1;
  output [5:0]trn_tbuf_av;
  output tbuf_av_min_trig;
  output pcie_block_i_2;
  output trn_tdst_rdy;
  output [0:0]cfg_command;
  output cfg_interrupt_msienable;
  output cfg_to_turnoff;
  output pipe_rx0_polarity;
  output pipe_rx1_polarity;
  output pipe_tx0_compliance;
  output pipe_tx0_elec_idle;
  output pipe_tx1_compliance;
  output pipe_tx1_elec_idle;
  output pipe_tx_deemph;
  output pipe_tx_rate;
  output pipe_tx_rcvr_det;
  output pl_received_hot_rst;
  output trn_lnk_up;
  output trn_recrc_err;
  output trn_rerrfwd;
  output [63:0]pcie_block_i_3;
  output [15:0]cfg_msg_data;
  output [15:0]pipe_tx0_data;
  output [15:0]pipe_tx1_data;
  output [1:0]pipe_tx0_char_is_k;
  output [1:0]pipe_tx0_powerdown;
  output [1:0]pipe_tx1_char_is_k;
  output [1:0]pipe_tx1_powerdown;
  output [0:0]pcie_block_i_4;
  output [5:0]cfg_dcommand;
  output [2:0]cfg_interrupt_mmenable;
  output [2:0]pipe_tx_margin;
  output [31:0]cfg_mgmt_do;
  output [5:0]pl_ltssm_state;
  output [7:0]fc_nph;
  output [6:0]trn_rbar_hit;
  input bridge_reset_int;
  input pl_phy_lnk_up;
  input cfg_mgmt_wr_readonly;
  input cfg_mgmt_wr_en;
  input cfg_mgmt_rd_en;
  input cfg_interrupt;
  input cfg_interrupt_assert;
  input trn_in_packet;
  input trn_rdst_rdy;
  input ppm_L1_trig;
  input ppm_L1_thrtl;
  input trn_rsrc_dsc_d;
  input reg_dsc_detect;
  input reg_tcfg_gnt;
  input lnk_up_thrtl;
  input out;
  input CLK;
  input cfg_pm_turnoff_ok_n;
  input pcie_block_i_5;
  input pipe_rx0_chanisaligned;
  input pipe_rx0_elec_idle;
  input pipe_rx0_phy_status;
  input pipe_rx0_valid;
  input pipe_rx1_chanisaligned;
  input pipe_rx1_elec_idle;
  input pipe_rx1_phy_status;
  input pipe_rx1_valid;
  input pl_directed_link_auton;
  input pl_directed_link_speed;
  input pl_upstream_prefer_deemph;
  input sys_rst_n;
  input rx_np_ok;
  input rx_np_req;
  input trn_tcfg_gnt;
  input [3:0]pcie_block_i_6;
  input trn_teof;
  input trn_tsof;
  input trn_tsrc_rdy;
  input [127:0]cfg_err_aer_headerlog;
  input [63:0]trn_td;
  input [15:0]Q;
  input [15:0]pcie_block_i_7;
  input [1:0]cfg_pm_force_state;
  input [1:0]pcie_block_i_8;
  input [1:0]pcie_block_i_9;
  input [1:0]pl_directed_link_change;
  input [1:0]pl_directed_link_width;
  input [0:0]trn_trem;
  input [2:0]pcie_block_i_10;
  input [2:0]pcie_block_i_11;
  input [2:0]fc_sel;
  input [31:0]cfg_mgmt_di;
  input [3:0]cfg_mgmt_byte_en_n;
  input [47:0]cfg_err_tlp_cpl_header;
  input [4:0]cfg_aer_interrupt_msgnum;
  input [4:0]cfg_pciecap_interrupt_msgnum;
  input [63:0]cfg_dsn;
  input [7:0]cfg_interrupt_di;
  input [9:0]cfg_mgmt_dwaddr;

  wire CLK;
  wire [0:0]E;
  wire [15:0]Q;
  wire bridge_reset_int;
  wire [4:0]cfg_aer_interrupt_msgnum;
  wire [0:0]cfg_command;
  wire [5:0]cfg_dcommand;
  wire [63:0]cfg_dsn;
  wire [127:0]cfg_err_aer_headerlog;
  wire cfg_err_aer_headerlog_set_n;
  wire cfg_err_cpl_rdy_n;
  wire [47:0]cfg_err_tlp_cpl_header;
  wire cfg_interrupt;
  wire cfg_interrupt_assert;
  wire [7:0]cfg_interrupt_di;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire cfg_interrupt_rdy;
  wire cfg_interrupt_rdy_n;
  wire [3:0]cfg_mgmt_byte_en_n;
  wire [31:0]cfg_mgmt_di;
  wire [31:0]cfg_mgmt_do;
  wire [9:0]cfg_mgmt_dwaddr;
  wire cfg_mgmt_rd_en;
  wire cfg_mgmt_rd_wr_done;
  wire cfg_mgmt_rd_wr_done_n;
  wire cfg_mgmt_wr_en;
  wire cfg_mgmt_wr_readonly;
  wire [15:0]cfg_msg_data;
  wire [2:0]cfg_pcie_link_state;
  wire [4:0]cfg_pciecap_interrupt_msgnum;
  wire [1:0]cfg_pm_force_state;
  wire cfg_pm_turnoff_ok_n;
  wire cfg_received_func_lvl_rst_n;
  wire cfg_to_turnoff;
  wire dsc_detect;
  wire [7:0]fc_nph;
  wire [2:0]fc_sel;
  wire lnk_up_thrtl;
  wire [12:0]mim_rx_raddr;
  wire [67:0]mim_rx_rdata;
  wire mim_rx_ren;
  wire [12:0]mim_rx_waddr;
  wire [67:0]mim_rx_wdata;
  wire mim_rx_wen;
  wire [12:0]mim_tx_raddr;
  wire [68:0]mim_tx_rdata;
  wire mim_tx_ren;
  wire [12:0]mim_tx_waddr;
  wire [68:0]mim_tx_wdata;
  wire mim_tx_wen;
  wire out;
  wire pcie_block_i_0;
  wire pcie_block_i_1;
  wire [2:0]pcie_block_i_10;
  wire [2:0]pcie_block_i_11;
  wire pcie_block_i_2;
  wire [63:0]pcie_block_i_3;
  wire [0:0]pcie_block_i_4;
  wire pcie_block_i_5;
  wire [3:0]pcie_block_i_6;
  wire [15:0]pcie_block_i_7;
  wire [1:0]pcie_block_i_8;
  wire [1:0]pcie_block_i_9;
  wire pcie_block_i_i_1_n_0;
  wire pcie_block_i_i_2_n_0;
  wire pcie_block_i_i_3_n_0;
  wire pcie_block_i_i_4_n_0;
  wire pcie_block_i_i_5_n_0;
  wire pcie_block_i_n_0;
  wire pcie_block_i_n_1;
  wire pcie_block_i_n_10;
  wire pcie_block_i_n_100;
  wire pcie_block_i_n_101;
  wire pcie_block_i_n_102;
  wire pcie_block_i_n_103;
  wire pcie_block_i_n_104;
  wire pcie_block_i_n_105;
  wire pcie_block_i_n_106;
  wire pcie_block_i_n_107;
  wire pcie_block_i_n_108;
  wire pcie_block_i_n_1097;
  wire pcie_block_i_n_1098;
  wire pcie_block_i_n_1099;
  wire pcie_block_i_n_11;
  wire pcie_block_i_n_1100;
  wire pcie_block_i_n_1101;
  wire pcie_block_i_n_1102;
  wire pcie_block_i_n_1103;
  wire pcie_block_i_n_1104;
  wire pcie_block_i_n_1105;
  wire pcie_block_i_n_1106;
  wire pcie_block_i_n_1107;
  wire pcie_block_i_n_1108;
  wire pcie_block_i_n_1109;
  wire pcie_block_i_n_1110;
  wire pcie_block_i_n_1111;
  wire pcie_block_i_n_1112;
  wire pcie_block_i_n_1113;
  wire pcie_block_i_n_1114;
  wire pcie_block_i_n_1115;
  wire pcie_block_i_n_1116;
  wire pcie_block_i_n_1117;
  wire pcie_block_i_n_1118;
  wire pcie_block_i_n_1119;
  wire pcie_block_i_n_1120;
  wire pcie_block_i_n_1121;
  wire pcie_block_i_n_1122;
  wire pcie_block_i_n_1123;
  wire pcie_block_i_n_1124;
  wire pcie_block_i_n_1125;
  wire pcie_block_i_n_1126;
  wire pcie_block_i_n_1135;
  wire pcie_block_i_n_1136;
  wire pcie_block_i_n_1137;
  wire pcie_block_i_n_1138;
  wire pcie_block_i_n_1139;
  wire pcie_block_i_n_1140;
  wire pcie_block_i_n_1141;
  wire pcie_block_i_n_1142;
  wire pcie_block_i_n_1143;
  wire pcie_block_i_n_12;
  wire pcie_block_i_n_13;
  wire pcie_block_i_n_14;
  wire pcie_block_i_n_140;
  wire pcie_block_i_n_141;
  wire pcie_block_i_n_142;
  wire pcie_block_i_n_143;
  wire pcie_block_i_n_144;
  wire pcie_block_i_n_145;
  wire pcie_block_i_n_146;
  wire pcie_block_i_n_147;
  wire pcie_block_i_n_148;
  wire pcie_block_i_n_149;
  wire pcie_block_i_n_15;
  wire pcie_block_i_n_150;
  wire pcie_block_i_n_153;
  wire pcie_block_i_n_155;
  wire pcie_block_i_n_156;
  wire pcie_block_i_n_157;
  wire pcie_block_i_n_158;
  wire pcie_block_i_n_159;
  wire pcie_block_i_n_16;
  wire pcie_block_i_n_160;
  wire pcie_block_i_n_169;
  wire pcie_block_i_n_17;
  wire pcie_block_i_n_170;
  wire pcie_block_i_n_172;
  wire pcie_block_i_n_173;
  wire pcie_block_i_n_174;
  wire pcie_block_i_n_175;
  wire pcie_block_i_n_176;
  wire pcie_block_i_n_177;
  wire pcie_block_i_n_178;
  wire pcie_block_i_n_179;
  wire pcie_block_i_n_18;
  wire pcie_block_i_n_180;
  wire pcie_block_i_n_181;
  wire pcie_block_i_n_182;
  wire pcie_block_i_n_183;
  wire pcie_block_i_n_184;
  wire pcie_block_i_n_185;
  wire pcie_block_i_n_186;
  wire pcie_block_i_n_187;
  wire pcie_block_i_n_188;
  wire pcie_block_i_n_189;
  wire pcie_block_i_n_19;
  wire pcie_block_i_n_190;
  wire pcie_block_i_n_191;
  wire pcie_block_i_n_192;
  wire pcie_block_i_n_193;
  wire pcie_block_i_n_194;
  wire pcie_block_i_n_195;
  wire pcie_block_i_n_196;
  wire pcie_block_i_n_197;
  wire pcie_block_i_n_198;
  wire pcie_block_i_n_199;
  wire pcie_block_i_n_2;
  wire pcie_block_i_n_20;
  wire pcie_block_i_n_200;
  wire pcie_block_i_n_201;
  wire pcie_block_i_n_202;
  wire pcie_block_i_n_203;
  wire pcie_block_i_n_204;
  wire pcie_block_i_n_205;
  wire pcie_block_i_n_206;
  wire pcie_block_i_n_207;
  wire pcie_block_i_n_208;
  wire pcie_block_i_n_209;
  wire pcie_block_i_n_21;
  wire pcie_block_i_n_210;
  wire pcie_block_i_n_211;
  wire pcie_block_i_n_212;
  wire pcie_block_i_n_213;
  wire pcie_block_i_n_214;
  wire pcie_block_i_n_215;
  wire pcie_block_i_n_216;
  wire pcie_block_i_n_217;
  wire pcie_block_i_n_218;
  wire pcie_block_i_n_219;
  wire pcie_block_i_n_22;
  wire pcie_block_i_n_220;
  wire pcie_block_i_n_221;
  wire pcie_block_i_n_222;
  wire pcie_block_i_n_223;
  wire pcie_block_i_n_224;
  wire pcie_block_i_n_225;
  wire pcie_block_i_n_226;
  wire pcie_block_i_n_227;
  wire pcie_block_i_n_228;
  wire pcie_block_i_n_229;
  wire pcie_block_i_n_23;
  wire pcie_block_i_n_230;
  wire pcie_block_i_n_231;
  wire pcie_block_i_n_24;
  wire pcie_block_i_n_25;
  wire pcie_block_i_n_26;
  wire pcie_block_i_n_27;
  wire pcie_block_i_n_28;
  wire pcie_block_i_n_29;
  wire pcie_block_i_n_3;
  wire pcie_block_i_n_30;
  wire pcie_block_i_n_31;
  wire pcie_block_i_n_32;
  wire pcie_block_i_n_33;
  wire pcie_block_i_n_34;
  wire pcie_block_i_n_38;
  wire pcie_block_i_n_39;
  wire pcie_block_i_n_4;
  wire pcie_block_i_n_41;
  wire pcie_block_i_n_42;
  wire pcie_block_i_n_428;
  wire pcie_block_i_n_429;
  wire pcie_block_i_n_43;
  wire pcie_block_i_n_430;
  wire pcie_block_i_n_431;
  wire pcie_block_i_n_432;
  wire pcie_block_i_n_433;
  wire pcie_block_i_n_434;
  wire pcie_block_i_n_435;
  wire pcie_block_i_n_436;
  wire pcie_block_i_n_437;
  wire pcie_block_i_n_438;
  wire pcie_block_i_n_439;
  wire pcie_block_i_n_44;
  wire pcie_block_i_n_440;
  wire pcie_block_i_n_441;
  wire pcie_block_i_n_442;
  wire pcie_block_i_n_443;
  wire pcie_block_i_n_45;
  wire pcie_block_i_n_46;
  wire pcie_block_i_n_47;
  wire pcie_block_i_n_48;
  wire pcie_block_i_n_49;
  wire pcie_block_i_n_5;
  wire pcie_block_i_n_50;
  wire pcie_block_i_n_51;
  wire pcie_block_i_n_52;
  wire pcie_block_i_n_53;
  wire pcie_block_i_n_55;
  wire pcie_block_i_n_56;
  wire pcie_block_i_n_57;
  wire pcie_block_i_n_572;
  wire pcie_block_i_n_573;
  wire pcie_block_i_n_574;
  wire pcie_block_i_n_575;
  wire pcie_block_i_n_576;
  wire pcie_block_i_n_577;
  wire pcie_block_i_n_58;
  wire pcie_block_i_n_59;
  wire pcie_block_i_n_6;
  wire pcie_block_i_n_60;
  wire pcie_block_i_n_61;
  wire pcie_block_i_n_610;
  wire pcie_block_i_n_611;
  wire pcie_block_i_n_612;
  wire pcie_block_i_n_613;
  wire pcie_block_i_n_614;
  wire pcie_block_i_n_615;
  wire pcie_block_i_n_616;
  wire pcie_block_i_n_617;
  wire pcie_block_i_n_618;
  wire pcie_block_i_n_619;
  wire pcie_block_i_n_62;
  wire pcie_block_i_n_63;
  wire pcie_block_i_n_637;
  wire pcie_block_i_n_638;
  wire pcie_block_i_n_639;
  wire pcie_block_i_n_64;
  wire pcie_block_i_n_640;
  wire pcie_block_i_n_641;
  wire pcie_block_i_n_642;
  wire pcie_block_i_n_65;
  wire pcie_block_i_n_66;
  wire pcie_block_i_n_67;
  wire pcie_block_i_n_675;
  wire pcie_block_i_n_676;
  wire pcie_block_i_n_677;
  wire pcie_block_i_n_678;
  wire pcie_block_i_n_679;
  wire pcie_block_i_n_680;
  wire pcie_block_i_n_681;
  wire pcie_block_i_n_682;
  wire pcie_block_i_n_687;
  wire pcie_block_i_n_688;
  wire pcie_block_i_n_689;
  wire pcie_block_i_n_69;
  wire pcie_block_i_n_690;
  wire pcie_block_i_n_691;
  wire pcie_block_i_n_7;
  wire pcie_block_i_n_70;
  wire pcie_block_i_n_704;
  wire pcie_block_i_n_705;
  wire pcie_block_i_n_706;
  wire pcie_block_i_n_707;
  wire pcie_block_i_n_708;
  wire pcie_block_i_n_709;
  wire pcie_block_i_n_71;
  wire pcie_block_i_n_710;
  wire pcie_block_i_n_711;
  wire pcie_block_i_n_712;
  wire pcie_block_i_n_713;
  wire pcie_block_i_n_714;
  wire pcie_block_i_n_715;
  wire pcie_block_i_n_716;
  wire pcie_block_i_n_717;
  wire pcie_block_i_n_718;
  wire pcie_block_i_n_719;
  wire pcie_block_i_n_72;
  wire pcie_block_i_n_720;
  wire pcie_block_i_n_721;
  wire pcie_block_i_n_722;
  wire pcie_block_i_n_723;
  wire pcie_block_i_n_724;
  wire pcie_block_i_n_725;
  wire pcie_block_i_n_726;
  wire pcie_block_i_n_727;
  wire pcie_block_i_n_728;
  wire pcie_block_i_n_729;
  wire pcie_block_i_n_73;
  wire pcie_block_i_n_730;
  wire pcie_block_i_n_731;
  wire pcie_block_i_n_732;
  wire pcie_block_i_n_733;
  wire pcie_block_i_n_734;
  wire pcie_block_i_n_735;
  wire pcie_block_i_n_736;
  wire pcie_block_i_n_737;
  wire pcie_block_i_n_738;
  wire pcie_block_i_n_739;
  wire pcie_block_i_n_74;
  wire pcie_block_i_n_740;
  wire pcie_block_i_n_741;
  wire pcie_block_i_n_742;
  wire pcie_block_i_n_743;
  wire pcie_block_i_n_744;
  wire pcie_block_i_n_745;
  wire pcie_block_i_n_746;
  wire pcie_block_i_n_747;
  wire pcie_block_i_n_748;
  wire pcie_block_i_n_749;
  wire pcie_block_i_n_75;
  wire pcie_block_i_n_750;
  wire pcie_block_i_n_751;
  wire pcie_block_i_n_752;
  wire pcie_block_i_n_753;
  wire pcie_block_i_n_754;
  wire pcie_block_i_n_755;
  wire pcie_block_i_n_756;
  wire pcie_block_i_n_757;
  wire pcie_block_i_n_758;
  wire pcie_block_i_n_759;
  wire pcie_block_i_n_76;
  wire pcie_block_i_n_760;
  wire pcie_block_i_n_761;
  wire pcie_block_i_n_762;
  wire pcie_block_i_n_763;
  wire pcie_block_i_n_764;
  wire pcie_block_i_n_765;
  wire pcie_block_i_n_766;
  wire pcie_block_i_n_767;
  wire pcie_block_i_n_768;
  wire pcie_block_i_n_769;
  wire pcie_block_i_n_77;
  wire pcie_block_i_n_770;
  wire pcie_block_i_n_771;
  wire pcie_block_i_n_772;
  wire pcie_block_i_n_773;
  wire pcie_block_i_n_774;
  wire pcie_block_i_n_775;
  wire pcie_block_i_n_776;
  wire pcie_block_i_n_777;
  wire pcie_block_i_n_778;
  wire pcie_block_i_n_779;
  wire pcie_block_i_n_78;
  wire pcie_block_i_n_780;
  wire pcie_block_i_n_781;
  wire pcie_block_i_n_782;
  wire pcie_block_i_n_783;
  wire pcie_block_i_n_784;
  wire pcie_block_i_n_785;
  wire pcie_block_i_n_786;
  wire pcie_block_i_n_787;
  wire pcie_block_i_n_788;
  wire pcie_block_i_n_789;
  wire pcie_block_i_n_79;
  wire pcie_block_i_n_790;
  wire pcie_block_i_n_791;
  wire pcie_block_i_n_792;
  wire pcie_block_i_n_793;
  wire pcie_block_i_n_794;
  wire pcie_block_i_n_795;
  wire pcie_block_i_n_796;
  wire pcie_block_i_n_797;
  wire pcie_block_i_n_798;
  wire pcie_block_i_n_799;
  wire pcie_block_i_n_8;
  wire pcie_block_i_n_80;
  wire pcie_block_i_n_800;
  wire pcie_block_i_n_801;
  wire pcie_block_i_n_802;
  wire pcie_block_i_n_803;
  wire pcie_block_i_n_804;
  wire pcie_block_i_n_805;
  wire pcie_block_i_n_806;
  wire pcie_block_i_n_807;
  wire pcie_block_i_n_808;
  wire pcie_block_i_n_809;
  wire pcie_block_i_n_81;
  wire pcie_block_i_n_810;
  wire pcie_block_i_n_811;
  wire pcie_block_i_n_812;
  wire pcie_block_i_n_813;
  wire pcie_block_i_n_814;
  wire pcie_block_i_n_815;
  wire pcie_block_i_n_816;
  wire pcie_block_i_n_817;
  wire pcie_block_i_n_818;
  wire pcie_block_i_n_819;
  wire pcie_block_i_n_82;
  wire pcie_block_i_n_820;
  wire pcie_block_i_n_821;
  wire pcie_block_i_n_822;
  wire pcie_block_i_n_823;
  wire pcie_block_i_n_824;
  wire pcie_block_i_n_825;
  wire pcie_block_i_n_826;
  wire pcie_block_i_n_827;
  wire pcie_block_i_n_828;
  wire pcie_block_i_n_829;
  wire pcie_block_i_n_83;
  wire pcie_block_i_n_830;
  wire pcie_block_i_n_831;
  wire pcie_block_i_n_832;
  wire pcie_block_i_n_833;
  wire pcie_block_i_n_834;
  wire pcie_block_i_n_835;
  wire pcie_block_i_n_836;
  wire pcie_block_i_n_837;
  wire pcie_block_i_n_838;
  wire pcie_block_i_n_839;
  wire pcie_block_i_n_84;
  wire pcie_block_i_n_840;
  wire pcie_block_i_n_841;
  wire pcie_block_i_n_842;
  wire pcie_block_i_n_843;
  wire pcie_block_i_n_844;
  wire pcie_block_i_n_845;
  wire pcie_block_i_n_846;
  wire pcie_block_i_n_847;
  wire pcie_block_i_n_848;
  wire pcie_block_i_n_849;
  wire pcie_block_i_n_85;
  wire pcie_block_i_n_850;
  wire pcie_block_i_n_851;
  wire pcie_block_i_n_852;
  wire pcie_block_i_n_853;
  wire pcie_block_i_n_854;
  wire pcie_block_i_n_855;
  wire pcie_block_i_n_856;
  wire pcie_block_i_n_857;
  wire pcie_block_i_n_858;
  wire pcie_block_i_n_859;
  wire pcie_block_i_n_86;
  wire pcie_block_i_n_860;
  wire pcie_block_i_n_861;
  wire pcie_block_i_n_862;
  wire pcie_block_i_n_863;
  wire pcie_block_i_n_864;
  wire pcie_block_i_n_865;
  wire pcie_block_i_n_866;
  wire pcie_block_i_n_867;
  wire pcie_block_i_n_868;
  wire pcie_block_i_n_869;
  wire pcie_block_i_n_87;
  wire pcie_block_i_n_870;
  wire pcie_block_i_n_871;
  wire pcie_block_i_n_872;
  wire pcie_block_i_n_873;
  wire pcie_block_i_n_874;
  wire pcie_block_i_n_875;
  wire pcie_block_i_n_876;
  wire pcie_block_i_n_877;
  wire pcie_block_i_n_878;
  wire pcie_block_i_n_879;
  wire pcie_block_i_n_88;
  wire pcie_block_i_n_880;
  wire pcie_block_i_n_881;
  wire pcie_block_i_n_882;
  wire pcie_block_i_n_883;
  wire pcie_block_i_n_884;
  wire pcie_block_i_n_885;
  wire pcie_block_i_n_886;
  wire pcie_block_i_n_887;
  wire pcie_block_i_n_888;
  wire pcie_block_i_n_889;
  wire pcie_block_i_n_89;
  wire pcie_block_i_n_890;
  wire pcie_block_i_n_891;
  wire pcie_block_i_n_892;
  wire pcie_block_i_n_893;
  wire pcie_block_i_n_894;
  wire pcie_block_i_n_895;
  wire pcie_block_i_n_896;
  wire pcie_block_i_n_897;
  wire pcie_block_i_n_898;
  wire pcie_block_i_n_899;
  wire pcie_block_i_n_90;
  wire pcie_block_i_n_900;
  wire pcie_block_i_n_901;
  wire pcie_block_i_n_902;
  wire pcie_block_i_n_903;
  wire pcie_block_i_n_904;
  wire pcie_block_i_n_905;
  wire pcie_block_i_n_906;
  wire pcie_block_i_n_907;
  wire pcie_block_i_n_908;
  wire pcie_block_i_n_909;
  wire pcie_block_i_n_91;
  wire pcie_block_i_n_910;
  wire pcie_block_i_n_911;
  wire pcie_block_i_n_912;
  wire pcie_block_i_n_913;
  wire pcie_block_i_n_914;
  wire pcie_block_i_n_915;
  wire pcie_block_i_n_916;
  wire pcie_block_i_n_917;
  wire pcie_block_i_n_918;
  wire pcie_block_i_n_919;
  wire pcie_block_i_n_92;
  wire pcie_block_i_n_920;
  wire pcie_block_i_n_921;
  wire pcie_block_i_n_922;
  wire pcie_block_i_n_923;
  wire pcie_block_i_n_924;
  wire pcie_block_i_n_925;
  wire pcie_block_i_n_926;
  wire pcie_block_i_n_927;
  wire pcie_block_i_n_928;
  wire pcie_block_i_n_929;
  wire pcie_block_i_n_93;
  wire pcie_block_i_n_930;
  wire pcie_block_i_n_931;
  wire pcie_block_i_n_932;
  wire pcie_block_i_n_933;
  wire pcie_block_i_n_934;
  wire pcie_block_i_n_935;
  wire pcie_block_i_n_936;
  wire pcie_block_i_n_937;
  wire pcie_block_i_n_938;
  wire pcie_block_i_n_939;
  wire pcie_block_i_n_94;
  wire pcie_block_i_n_940;
  wire pcie_block_i_n_941;
  wire pcie_block_i_n_942;
  wire pcie_block_i_n_943;
  wire pcie_block_i_n_944;
  wire pcie_block_i_n_945;
  wire pcie_block_i_n_946;
  wire pcie_block_i_n_947;
  wire pcie_block_i_n_948;
  wire pcie_block_i_n_949;
  wire pcie_block_i_n_95;
  wire pcie_block_i_n_950;
  wire pcie_block_i_n_951;
  wire pcie_block_i_n_952;
  wire pcie_block_i_n_953;
  wire pcie_block_i_n_954;
  wire pcie_block_i_n_955;
  wire pcie_block_i_n_956;
  wire pcie_block_i_n_957;
  wire pcie_block_i_n_958;
  wire pcie_block_i_n_959;
  wire pcie_block_i_n_96;
  wire pcie_block_i_n_97;
  wire pcie_block_i_n_98;
  wire pcie_block_i_n_99;
  wire pipe_rx0_chanisaligned;
  wire pipe_rx0_elec_idle;
  wire pipe_rx0_phy_status;
  wire pipe_rx0_polarity;
  wire pipe_rx0_valid;
  wire pipe_rx1_chanisaligned;
  wire pipe_rx1_elec_idle;
  wire pipe_rx1_phy_status;
  wire pipe_rx1_polarity;
  wire pipe_rx1_valid;
  wire pipe_rx2_polarity;
  wire pipe_rx3_polarity;
  wire pipe_rx4_polarity;
  wire pipe_rx5_polarity;
  wire pipe_rx6_polarity;
  wire pipe_rx7_polarity;
  wire [1:0]pipe_tx0_char_is_k;
  wire pipe_tx0_compliance;
  wire [15:0]pipe_tx0_data;
  wire pipe_tx0_elec_idle;
  wire [1:0]pipe_tx0_powerdown;
  wire [1:0]pipe_tx1_char_is_k;
  wire pipe_tx1_compliance;
  wire [15:0]pipe_tx1_data;
  wire pipe_tx1_elec_idle;
  wire [1:0]pipe_tx1_powerdown;
  wire [1:0]pipe_tx2_char_is_k;
  wire pipe_tx2_compliance;
  wire [15:0]pipe_tx2_data;
  wire pipe_tx2_elec_idle;
  wire [1:0]pipe_tx2_powerdown;
  wire [1:0]pipe_tx3_char_is_k;
  wire pipe_tx3_compliance;
  wire [15:0]pipe_tx3_data;
  wire pipe_tx3_elec_idle;
  wire [1:0]pipe_tx3_powerdown;
  wire [1:0]pipe_tx4_char_is_k;
  wire pipe_tx4_compliance;
  wire [15:0]pipe_tx4_data;
  wire pipe_tx4_elec_idle;
  wire [1:0]pipe_tx4_powerdown;
  wire [1:0]pipe_tx5_char_is_k;
  wire pipe_tx5_compliance;
  wire [15:0]pipe_tx5_data;
  wire pipe_tx5_elec_idle;
  wire [1:0]pipe_tx5_powerdown;
  wire [1:0]pipe_tx6_char_is_k;
  wire pipe_tx6_compliance;
  wire [15:0]pipe_tx6_data;
  wire pipe_tx6_elec_idle;
  wire [1:0]pipe_tx6_powerdown;
  wire [1:0]pipe_tx7_char_is_k;
  wire pipe_tx7_compliance;
  wire [15:0]pipe_tx7_data;
  wire pipe_tx7_elec_idle;
  wire [1:0]pipe_tx7_powerdown;
  wire pipe_tx_deemph;
  wire [2:0]pipe_tx_margin;
  wire pipe_tx_rate;
  wire pipe_tx_rcvr_det;
  wire pl_directed_link_auton;
  wire [1:0]pl_directed_link_change;
  wire pl_directed_link_speed;
  wire [1:0]pl_directed_link_width;
  wire [5:0]pl_ltssm_state;
  wire pl_phy_lnk_up;
  wire pl_phy_lnk_up_n;
  wire pl_received_hot_rst;
  wire pl_upstream_prefer_deemph;
  wire ppm_L1_thrtl;
  wire ppm_L1_trig;
  wire reg_dsc_detect;
  wire reg_tcfg_gnt;
  wire rsrc_rdy_filtered;
  wire rx_np_ok;
  wire rx_np_req;
  wire src_in;
  wire sys_rst_n;
  wire tbuf_av_min_trig;
  wire tcfg_req_trig;
  wire trn_in_packet;
  wire trn_in_packet_reg;
  wire trn_lnk_up;
  wire [6:0]trn_rbar_hit;
  wire [127:64]trn_rd;
  wire trn_rdst_rdy;
  wire trn_recrc_err;
  wire trn_reof;
  wire trn_rerrfwd;
  wire [1:1]trn_rrem;
  wire trn_rsof;
  wire trn_rsrc_dsc;
  wire trn_rsrc_dsc_d;
  wire trn_rsrc_dsc_prev0;
  wire trn_rsrc_rdy;
  wire [5:0]trn_tbuf_av;
  wire trn_tcfg_gnt;
  wire trn_tcfg_req;
  wire [63:0]trn_td;
  wire trn_tdst_rdy;
  wire trn_teof;
  wire [0:0]trn_trem;
  wire trn_tsof;
  wire trn_tsrc_rdy;
  wire user_reset_int_reg;
  wire user_rst_n;
  wire [3:1]NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED;

  LUT1 #(
    .INIT(2'h1)) 
    \cfg_bus_number_d[7]_i_2 
       (.I0(pcie_block_i_n_55),
        .O(E));
  LUT1 #(
    .INIT(2'h1)) 
    cfg_interrupt_rdy_INST_0
       (.I0(cfg_interrupt_rdy_n),
        .O(cfg_interrupt_rdy));
  LUT1 #(
    .INIT(2'h1)) 
    cfg_mgmt_rd_wr_done_INST_0
       (.I0(cfg_mgmt_rd_wr_done_n),
        .O(cfg_mgmt_rd_wr_done));
  LUT3 #(
    .INIT(8'h4F)) 
    lnk_up_thrtl_i_1
       (.I0(trn_tdst_rdy),
        .I1(lnk_up_thrtl),
        .I2(out),
        .O(pcie_block_i_2));
  LUT6 #(
    .INIT(64'h0000000027000000)) 
    m_axis_rx_tvalid_i_2
       (.I0(trn_reof),
        .I1(trn_rdst_rdy),
        .I2(trn_rsof),
        .I3(trn_rsrc_dsc),
        .I4(trn_in_packet),
        .I5(trn_rsrc_dsc_d),
        .O(dsc_detect));
  (* box_type = "PRIMITIVE" *) 
  PCIE_2_1 #(
    .AER_BASE_PTR(12'h000),
    .AER_CAP_ECRC_CHECK_CAPABLE("FALSE"),
    .AER_CAP_ECRC_GEN_CAPABLE("FALSE"),
    .AER_CAP_ID(16'h0001),
    .AER_CAP_MULTIHEADER("FALSE"),
    .AER_CAP_NEXTPTR(12'h000),
    .AER_CAP_ON("FALSE"),
    .AER_CAP_OPTIONAL_ERR_SUPPORT(24'h000000),
    .AER_CAP_PERMIT_ROOTERR_UPDATE("FALSE"),
    .AER_CAP_VERSION(4'h1),
    .ALLOW_X8_GEN2("FALSE"),
    .BAR0(32'hFFFF0000),
    .BAR1(32'hFFF00000),
    .BAR2(32'h00000000),
    .BAR3(32'h00000000),
    .BAR4(32'h00000000),
    .BAR5(32'h00000000),
    .CAPABILITIES_PTR(8'h40),
    .CARDBUS_CIS_POINTER(32'h00000000),
    .CFG_ECRC_ERR_CPLSTAT(0),
    .CLASS_CODE(24'h070001),
    .CMD_INTX_IMPLEMENTED("TRUE"),
    .CPL_TIMEOUT_DISABLE_SUPPORTED("FALSE"),
    .CPL_TIMEOUT_RANGES_SUPPORTED(4'h2),
    .CRM_MODULE_RSTS(7'h00),
    .DEV_CAP2_ARI_FORWARDING_SUPPORTED("FALSE"),
    .DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED("FALSE"),
    .DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED("FALSE"),
    .DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED("FALSE"),
    .DEV_CAP2_CAS128_COMPLETER_SUPPORTED("FALSE"),
    .DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED("FALSE"),
    .DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED("FALSE"),
    .DEV_CAP2_LTR_MECHANISM_SUPPORTED("FALSE"),
    .DEV_CAP2_MAX_ENDEND_TLP_PREFIXES(2'h0),
    .DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING("FALSE"),
    .DEV_CAP2_TPH_COMPLETER_SUPPORTED(2'h0),
    .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE("TRUE"),
    .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE("TRUE"),
    .DEV_CAP_ENDPOINT_L0S_LATENCY(0),
    .DEV_CAP_ENDPOINT_L1_LATENCY(7),
    .DEV_CAP_EXT_TAG_SUPPORTED("TRUE"),
    .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE("FALSE"),
    .DEV_CAP_MAX_PAYLOAD_SUPPORTED(2),
    .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT(0),
    .DEV_CAP_ROLE_BASED_ERROR("TRUE"),
    .DEV_CAP_RSVD_14_12(0),
    .DEV_CAP_RSVD_17_16(0),
    .DEV_CAP_RSVD_31_29(0),
    .DEV_CONTROL_AUX_POWER_SUPPORTED("FALSE"),
    .DEV_CONTROL_EXT_TAG_DEFAULT("FALSE"),
    .DISABLE_ASPM_L1_TIMER("FALSE"),
    .DISABLE_BAR_FILTERING("FALSE"),
    .DISABLE_ERR_MSG("FALSE"),
    .DISABLE_ID_CHECK("FALSE"),
    .DISABLE_LANE_REVERSAL("TRUE"),
    .DISABLE_LOCKED_FILTER("FALSE"),
    .DISABLE_PPM_FILTER("FALSE"),
    .DISABLE_RX_POISONED_RESP("FALSE"),
    .DISABLE_RX_TC_FILTER("FALSE"),
    .DISABLE_SCRAMBLING("FALSE"),
    .DNSTREAM_LINK_NUM(8'h00),
    .DSN_BASE_PTR(12'h100),
    .DSN_CAP_ID(16'h0003),
    .DSN_CAP_NEXTPTR(12'h000),
    .DSN_CAP_ON("TRUE"),
    .DSN_CAP_VERSION(4'h1),
    .ENABLE_MSG_ROUTE(11'h000),
    .ENABLE_RX_TD_ECRC_TRIM("FALSE"),
    .ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED("FALSE"),
    .ENTER_RVRY_EI_L0("TRUE"),
    .EXIT_LOOPBACK_ON_EI("TRUE"),
    .EXPANSION_ROM(32'h00000000),
    .EXT_CFG_CAP_PTR(6'h3F),
    .EXT_CFG_XP_CAP_PTR(10'h3FF),
    .HEADER_TYPE(8'h00),
    .INFER_EI(5'h00),
    .INTERRUPT_PIN(8'h01),
    .INTERRUPT_STAT_AUTO("TRUE"),
    .IS_SWITCH("FALSE"),
    .LAST_CONFIG_DWORD(10'h3FF),
    .LINK_CAP_ASPM_OPTIONALITY("FALSE"),
    .LINK_CAP_ASPM_SUPPORT(1),
    .LINK_CAP_CLOCK_POWER_MANAGEMENT("FALSE"),
    .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP("FALSE"),
    .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1(7),
    .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2(7),
    .LINK_CAP_L0S_EXIT_LATENCY_GEN1(7),
    .LINK_CAP_L0S_EXIT_LATENCY_GEN2(7),
    .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1(7),
    .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2(7),
    .LINK_CAP_L1_EXIT_LATENCY_GEN1(7),
    .LINK_CAP_L1_EXIT_LATENCY_GEN2(7),
    .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP("FALSE"),
    .LINK_CAP_MAX_LINK_SPEED(4'h2),
    .LINK_CAP_MAX_LINK_WIDTH(6'h02),
    .LINK_CAP_RSVD_23(0),
    .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE("FALSE"),
    .LINK_CONTROL_RCB(0),
    .LINK_CTRL2_DEEMPHASIS("FALSE"),
    .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE("FALSE"),
    .LINK_CTRL2_TARGET_LINK_SPEED(4'h2),
    .LINK_STATUS_SLOT_CLOCK_CONFIG("TRUE"),
    .LL_ACK_TIMEOUT(15'h0000),
    .LL_ACK_TIMEOUT_EN("FALSE"),
    .LL_ACK_TIMEOUT_FUNC(0),
    .LL_REPLAY_TIMEOUT(15'h0000),
    .LL_REPLAY_TIMEOUT_EN("FALSE"),
    .LL_REPLAY_TIMEOUT_FUNC(1),
    .LTSSM_MAX_LINK_WIDTH(6'h02),
    .MPS_FORCE("FALSE"),
    .MSIX_BASE_PTR(8'h9C),
    .MSIX_CAP_ID(8'h11),
    .MSIX_CAP_NEXTPTR(8'h00),
    .MSIX_CAP_ON("FALSE"),
    .MSIX_CAP_PBA_BIR(0),
    .MSIX_CAP_PBA_OFFSET(29'h00000000),
    .MSIX_CAP_TABLE_BIR(0),
    .MSIX_CAP_TABLE_OFFSET(29'h00000000),
    .MSIX_CAP_TABLE_SIZE(11'h000),
    .MSI_BASE_PTR(8'h48),
    .MSI_CAP_64_BIT_ADDR_CAPABLE("TRUE"),
    .MSI_CAP_ID(8'h05),
    .MSI_CAP_MULTIMSGCAP(0),
    .MSI_CAP_MULTIMSG_EXTENSION(0),
    .MSI_CAP_NEXTPTR(8'h60),
    .MSI_CAP_ON("TRUE"),
    .MSI_CAP_PER_VECTOR_MASKING_CAPABLE("FALSE"),
    .N_FTS_COMCLK_GEN1(255),
    .N_FTS_COMCLK_GEN2(255),
    .N_FTS_GEN1(255),
    .N_FTS_GEN2(255),
    .PCIE_BASE_PTR(8'h60),
    .PCIE_CAP_CAPABILITY_ID(8'h10),
    .PCIE_CAP_CAPABILITY_VERSION(4'h2),
    .PCIE_CAP_DEVICE_PORT_TYPE(4'h0),
    .PCIE_CAP_NEXTPTR(8'h00),
    .PCIE_CAP_ON("TRUE"),
    .PCIE_CAP_RSVD_15_14(0),
    .PCIE_CAP_SLOT_IMPLEMENTED("FALSE"),
    .PCIE_REVISION(2),
    .PL_AUTO_CONFIG(0),
    .PL_FAST_TRAIN("TRUE"),
    .PM_ASPML0S_TIMEOUT(15'h0000),
    .PM_ASPML0S_TIMEOUT_EN("FALSE"),
    .PM_ASPML0S_TIMEOUT_FUNC(0),
    .PM_ASPM_FASTEXIT("FALSE"),
    .PM_BASE_PTR(8'h40),
    .PM_CAP_AUXCURRENT(0),
    .PM_CAP_D1SUPPORT("FALSE"),
    .PM_CAP_D2SUPPORT("FALSE"),
    .PM_CAP_DSI("FALSE"),
    .PM_CAP_ID(8'h01),
    .PM_CAP_NEXTPTR(8'h48),
    .PM_CAP_ON("TRUE"),
    .PM_CAP_PMESUPPORT(5'h0F),
    .PM_CAP_PME_CLOCK("FALSE"),
    .PM_CAP_RSVD_04(0),
    .PM_CAP_VERSION(3),
    .PM_CSR_B2B3("FALSE"),
    .PM_CSR_BPCCEN("FALSE"),
    .PM_CSR_NOSOFTRST("TRUE"),
    .PM_DATA0(8'h00),
    .PM_DATA1(8'h00),
    .PM_DATA2(8'h00),
    .PM_DATA3(8'h00),
    .PM_DATA4(8'h00),
    .PM_DATA5(8'h00),
    .PM_DATA6(8'h00),
    .PM_DATA7(8'h00),
    .PM_DATA_SCALE0(2'h0),
    .PM_DATA_SCALE1(2'h0),
    .PM_DATA_SCALE2(2'h0),
    .PM_DATA_SCALE3(2'h0),
    .PM_DATA_SCALE4(2'h0),
    .PM_DATA_SCALE5(2'h0),
    .PM_DATA_SCALE6(2'h0),
    .PM_DATA_SCALE7(2'h0),
    .PM_MF("FALSE"),
    .RBAR_BASE_PTR(12'h000),
    .RBAR_CAP_CONTROL_ENCODEDBAR0(5'h00),
    .RBAR_CAP_CONTROL_ENCODEDBAR1(5'h00),
    .RBAR_CAP_CONTROL_ENCODEDBAR2(5'h00),
    .RBAR_CAP_CONTROL_ENCODEDBAR3(5'h00),
    .RBAR_CAP_CONTROL_ENCODEDBAR4(5'h00),
    .RBAR_CAP_CONTROL_ENCODEDBAR5(5'h00),
    .RBAR_CAP_ID(16'h0015),
    .RBAR_CAP_INDEX0(3'h0),
    .RBAR_CAP_INDEX1(3'h0),
    .RBAR_CAP_INDEX2(3'h0),
    .RBAR_CAP_INDEX3(3'h0),
    .RBAR_CAP_INDEX4(3'h0),
    .RBAR_CAP_INDEX5(3'h0),
    .RBAR_CAP_NEXTPTR(12'h000),
    .RBAR_CAP_ON("FALSE"),
    .RBAR_CAP_SUP0(32'h00000001),
    .RBAR_CAP_SUP1(32'h00000001),
    .RBAR_CAP_SUP2(32'h00000001),
    .RBAR_CAP_SUP3(32'h00000001),
    .RBAR_CAP_SUP4(32'h00000001),
    .RBAR_CAP_SUP5(32'h00000001),
    .RBAR_CAP_VERSION(4'h1),
    .RBAR_NUM(3'h0),
    .RECRC_CHK(0),
    .RECRC_CHK_TRIM("FALSE"),
    .ROOT_CAP_CRS_SW_VISIBILITY("FALSE"),
    .RP_AUTO_SPD(2'h1),
    .RP_AUTO_SPD_LOOPCNT(5'h1F),
    .SELECT_DLL_IF("FALSE"),
    .SIM_VERSION("1.0"),
    .SLOT_CAP_ATT_BUTTON_PRESENT("FALSE"),
    .SLOT_CAP_ATT_INDICATOR_PRESENT("FALSE"),
    .SLOT_CAP_ELEC_INTERLOCK_PRESENT("FALSE"),
    .SLOT_CAP_HOTPLUG_CAPABLE("FALSE"),
    .SLOT_CAP_HOTPLUG_SURPRISE("FALSE"),
    .SLOT_CAP_MRL_SENSOR_PRESENT("FALSE"),
    .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT("FALSE"),
    .SLOT_CAP_PHYSICAL_SLOT_NUM(13'h0000),
    .SLOT_CAP_POWER_CONTROLLER_PRESENT("FALSE"),
    .SLOT_CAP_POWER_INDICATOR_PRESENT("FALSE"),
    .SLOT_CAP_SLOT_POWER_LIMIT_SCALE(0),
    .SLOT_CAP_SLOT_POWER_LIMIT_VALUE(8'h00),
    .SPARE_BIT0(0),
    .SPARE_BIT1(0),
    .SPARE_BIT2(0),
    .SPARE_BIT3(0),
    .SPARE_BIT4(0),
    .SPARE_BIT5(0),
    .SPARE_BIT6(0),
    .SPARE_BIT7(0),
    .SPARE_BIT8(0),
    .SPARE_BYTE0(8'h00),
    .SPARE_BYTE1(8'h00),
    .SPARE_BYTE2(8'h00),
    .SPARE_BYTE3(8'h00),
    .SPARE_WORD0(32'h00000000),
    .SPARE_WORD1(32'h00000000),
    .SPARE_WORD2(32'h00000000),
    .SPARE_WORD3(32'h00000000),
    .SSL_MESSAGE_AUTO("FALSE"),
    .TECRC_EP_INV("FALSE"),
    .TL_RBYPASS("FALSE"),
    .TL_RX_RAM_RADDR_LATENCY(0),
    .TL_RX_RAM_RDATA_LATENCY(2),
    .TL_RX_RAM_WRITE_LATENCY(0),
    .TL_TFC_DISABLE("FALSE"),
    .TL_TX_CHECKS_DISABLE("FALSE"),
    .TL_TX_RAM_RADDR_LATENCY(0),
    .TL_TX_RAM_RDATA_LATENCY(2),
    .TL_TX_RAM_WRITE_LATENCY(0),
    .TRN_DW("FALSE"),
    .TRN_NP_FC("TRUE"),
    .UPCONFIG_CAPABLE("TRUE"),
    .UPSTREAM_FACING("TRUE"),
    .UR_ATOMIC("FALSE"),
    .UR_CFG1("TRUE"),
    .UR_INV_REQ("TRUE"),
    .UR_PRS_RESPONSE("TRUE"),
    .USER_CLK2_DIV2("FALSE"),
    .USER_CLK_FREQ(2),
    .USE_RID_PINS("FALSE"),
    .VC0_CPL_INFINITE("TRUE"),
    .VC0_RX_RAM_LIMIT(13'h07FF),
    .VC0_TOTAL_CREDITS_CD(461),
    .VC0_TOTAL_CREDITS_CH(36),
    .VC0_TOTAL_CREDITS_NPD(24),
    .VC0_TOTAL_CREDITS_NPH(12),
    .VC0_TOTAL_CREDITS_PD(437),
    .VC0_TOTAL_CREDITS_PH(32),
    .VC0_TX_LASTPACKET(29),
    .VC_BASE_PTR(12'h000),
    .VC_CAP_ID(16'h0002),
    .VC_CAP_NEXTPTR(12'h000),
    .VC_CAP_ON("FALSE"),
    .VC_CAP_REJECT_SNOOP_TRANSACTIONS("FALSE"),
    .VC_CAP_VERSION(4'h1),
    .VSEC_BASE_PTR(12'h000),
    .VSEC_CAP_HDR_ID(16'h1234),
    .VSEC_CAP_HDR_LENGTH(12'h018),
    .VSEC_CAP_HDR_REVISION(4'h1),
    .VSEC_CAP_ID(16'h000B),
    .VSEC_CAP_IS_LINK_VISIBLE("TRUE"),
    .VSEC_CAP_NEXTPTR(12'h000),
    .VSEC_CAP_ON("FALSE"),
    .VSEC_CAP_VERSION(4'h1)) 
    pcie_block_i
       (.CFGAERECRCCHECKEN(pcie_block_i_n_0),
        .CFGAERECRCGENEN(pcie_block_i_n_1),
        .CFGAERINTERRUPTMSGNUM(cfg_aer_interrupt_msgnum),
        .CFGAERROOTERRCORRERRRECEIVED(pcie_block_i_n_2),
        .CFGAERROOTERRCORRERRREPORTINGEN(pcie_block_i_n_3),
        .CFGAERROOTERRFATALERRRECEIVED(pcie_block_i_n_4),
        .CFGAERROOTERRFATALERRREPORTINGEN(pcie_block_i_n_5),
        .CFGAERROOTERRNONFATALERRRECEIVED(pcie_block_i_n_6),
        .CFGAERROOTERRNONFATALERRREPORTINGEN(pcie_block_i_n_7),
        .CFGBRIDGESERREN(pcie_block_i_n_8),
        .CFGCOMMANDBUSMASTERENABLE(cfg_command),
        .CFGCOMMANDINTERRUPTDISABLE(pcie_block_i_n_10),
        .CFGCOMMANDIOENABLE(pcie_block_i_n_11),
        .CFGCOMMANDMEMENABLE(pcie_block_i_n_12),
        .CFGCOMMANDSERREN(pcie_block_i_n_13),
        .CFGDEVCONTROL2ARIFORWARDEN(pcie_block_i_n_14),
        .CFGDEVCONTROL2ATOMICEGRESSBLOCK(pcie_block_i_n_15),
        .CFGDEVCONTROL2ATOMICREQUESTEREN(pcie_block_i_n_16),
        .CFGDEVCONTROL2CPLTIMEOUTDIS(pcie_block_i_n_17),
        .CFGDEVCONTROL2CPLTIMEOUTVAL({pcie_block_i_n_675,pcie_block_i_n_676,pcie_block_i_n_677,pcie_block_i_n_678}),
        .CFGDEVCONTROL2IDOCPLEN(pcie_block_i_n_18),
        .CFGDEVCONTROL2IDOREQEN(pcie_block_i_n_19),
        .CFGDEVCONTROL2LTREN(pcie_block_i_n_20),
        .CFGDEVCONTROL2TLPPREFIXBLOCK(pcie_block_i_n_21),
        .CFGDEVCONTROLAUXPOWEREN(pcie_block_i_n_22),
        .CFGDEVCONTROLCORRERRREPORTINGEN(pcie_block_i_n_23),
        .CFGDEVCONTROLENABLERO(pcie_block_i_n_24),
        .CFGDEVCONTROLEXTTAGEN(pcie_block_i_n_25),
        .CFGDEVCONTROLFATALERRREPORTINGEN(pcie_block_i_n_26),
        .CFGDEVCONTROLMAXPAYLOAD(cfg_dcommand[2:0]),
        .CFGDEVCONTROLMAXREADREQ(cfg_dcommand[5:3]),
        .CFGDEVCONTROLNONFATALREPORTINGEN(pcie_block_i_n_27),
        .CFGDEVCONTROLNOSNOOPEN(pcie_block_i_n_28),
        .CFGDEVCONTROLPHANTOMEN(pcie_block_i_n_29),
        .CFGDEVCONTROLURERRREPORTINGEN(pcie_block_i_n_30),
        .CFGDEVID({1'b0,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b1,1'b0}),
        .CFGDEVSTATUSCORRERRDETECTED(pcie_block_i_n_31),
        .CFGDEVSTATUSFATALERRDETECTED(pcie_block_i_n_32),
        .CFGDEVSTATUSNONFATALERRDETECTED(pcie_block_i_n_33),
        .CFGDEVSTATUSURDETECTED(pcie_block_i_n_34),
        .CFGDSBUSNUMBER({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CFGDSDEVICENUMBER({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CFGDSFUNCTIONNUMBER({1'b0,1'b0,1'b0}),
        .CFGDSN(cfg_dsn),
        .CFGERRACSN(1'b1),
        .CFGERRAERHEADERLOG(cfg_err_aer_headerlog),
        .CFGERRAERHEADERLOGSETN(cfg_err_aer_headerlog_set_n),
        .CFGERRATOMICEGRESSBLOCKEDN(1'b1),
        .CFGERRCORN(1'b1),
        .CFGERRCPLABORTN(1'b1),
        .CFGERRCPLRDYN(cfg_err_cpl_rdy_n),
        .CFGERRCPLTIMEOUTN(1'b1),
        .CFGERRCPLUNEXPECTN(1'b1),
        .CFGERRECRCN(1'b1),
        .CFGERRINTERNALCORN(1'b1),
        .CFGERRINTERNALUNCORN(1'b1),
        .CFGERRLOCKEDN(1'b1),
        .CFGERRMALFORMEDN(1'b1),
        .CFGERRMCBLOCKEDN(1'b1),
        .CFGERRNORECOVERYN(1'b1),
        .CFGERRPOISONEDN(1'b1),
        .CFGERRPOSTEDN(1'b1),
        .CFGERRTLPCPLHEADER(cfg_err_tlp_cpl_header),
        .CFGERRURN(1'b1),
        .CFGFORCECOMMONCLOCKOFF(1'b0),
        .CFGFORCEEXTENDEDSYNCON(1'b0),
        .CFGFORCEMPS({1'b0,1'b0,1'b0}),
        .CFGINTERRUPTASSERTN(pcie_block_i_i_1_n_0),
        .CFGINTERRUPTDI(cfg_interrupt_di),
        .CFGINTERRUPTDO({pcie_block_i_n_1111,pcie_block_i_n_1112,pcie_block_i_n_1113,pcie_block_i_n_1114,pcie_block_i_n_1115,pcie_block_i_n_1116,pcie_block_i_n_1117,pcie_block_i_n_1118}),
        .CFGINTERRUPTMMENABLE(cfg_interrupt_mmenable),
        .CFGINTERRUPTMSIENABLE(cfg_interrupt_msienable),
        .CFGINTERRUPTMSIXENABLE(pcie_block_i_n_38),
        .CFGINTERRUPTMSIXFM(pcie_block_i_n_39),
        .CFGINTERRUPTN(pcie_block_i_i_2_n_0),
        .CFGINTERRUPTRDYN(cfg_interrupt_rdy_n),
        .CFGINTERRUPTSTATN(1'b1),
        .CFGLINKCONTROLASPMCONTROL({pcie_block_i_n_572,pcie_block_i_n_573}),
        .CFGLINKCONTROLAUTOBANDWIDTHINTEN(pcie_block_i_n_41),
        .CFGLINKCONTROLBANDWIDTHINTEN(pcie_block_i_n_42),
        .CFGLINKCONTROLCLOCKPMEN(pcie_block_i_n_43),
        .CFGLINKCONTROLCOMMONCLOCK(pcie_block_i_n_44),
        .CFGLINKCONTROLEXTENDEDSYNC(pcie_block_i_n_45),
        .CFGLINKCONTROLHWAUTOWIDTHDIS(pcie_block_i_n_46),
        .CFGLINKCONTROLLINKDISABLE(pcie_block_i_n_47),
        .CFGLINKCONTROLRCB(pcie_block_i_n_48),
        .CFGLINKCONTROLRETRAINLINK(pcie_block_i_n_49),
        .CFGLINKSTATUSAUTOBANDWIDTHSTATUS(pcie_block_i_n_50),
        .CFGLINKSTATUSBANDWIDTHSTATUS(pcie_block_i_n_51),
        .CFGLINKSTATUSCURRENTSPEED({pcie_block_i_n_574,pcie_block_i_n_575}),
        .CFGLINKSTATUSDLLACTIVE(pcie_block_i_n_52),
        .CFGLINKSTATUSLINKTRAINING(pcie_block_i_n_53),
        .CFGLINKSTATUSNEGOTIATEDWIDTH({pcie_block_i_n_679,pcie_block_i_n_680,pcie_block_i_n_681,pcie_block_i_n_682}),
        .CFGMGMTBYTEENN(cfg_mgmt_byte_en_n),
        .CFGMGMTDI(cfg_mgmt_di),
        .CFGMGMTDO(cfg_mgmt_do),
        .CFGMGMTDWADDR(cfg_mgmt_dwaddr),
        .CFGMGMTRDENN(pcie_block_i_i_3_n_0),
        .CFGMGMTRDWRDONEN(cfg_mgmt_rd_wr_done_n),
        .CFGMGMTWRENN(pcie_block_i_i_4_n_0),
        .CFGMGMTWRREADONLYN(pcie_block_i_i_5_n_0),
        .CFGMGMTWRRW1CASRWN(1'b1),
        .CFGMSGDATA(cfg_msg_data),
        .CFGMSGRECEIVED(pcie_block_i_n_55),
        .CFGMSGRECEIVEDASSERTINTA(pcie_block_i_n_56),
        .CFGMSGRECEIVEDASSERTINTB(pcie_block_i_n_57),
        .CFGMSGRECEIVEDASSERTINTC(pcie_block_i_n_58),
        .CFGMSGRECEIVEDASSERTINTD(pcie_block_i_n_59),
        .CFGMSGRECEIVEDDEASSERTINTA(pcie_block_i_n_60),
        .CFGMSGRECEIVEDDEASSERTINTB(pcie_block_i_n_61),
        .CFGMSGRECEIVEDDEASSERTINTC(pcie_block_i_n_62),
        .CFGMSGRECEIVEDDEASSERTINTD(pcie_block_i_n_63),
        .CFGMSGRECEIVEDERRCOR(pcie_block_i_n_64),
        .CFGMSGRECEIVEDERRFATAL(pcie_block_i_n_65),
        .CFGMSGRECEIVEDERRNONFATAL(pcie_block_i_n_66),
        .CFGMSGRECEIVEDPMASNAK(pcie_block_i_n_67),
        .CFGMSGRECEIVEDPMETO(cfg_to_turnoff),
        .CFGMSGRECEIVEDPMETOACK(pcie_block_i_n_69),
        .CFGMSGRECEIVEDPMPME(pcie_block_i_n_70),
        .CFGMSGRECEIVEDSETSLOTPOWERLIMIT(pcie_block_i_n_71),
        .CFGMSGRECEIVEDUNLOCK(pcie_block_i_n_72),
        .CFGPCIECAPINTERRUPTMSGNUM(cfg_pciecap_interrupt_msgnum),
        .CFGPCIELINKSTATE(cfg_pcie_link_state),
        .CFGPMCSRPMEEN(pcie_block_i_n_73),
        .CFGPMCSRPMESTATUS(pcie_block_i_n_74),
        .CFGPMCSRPOWERSTATE({pcie_block_i_n_576,pcie_block_i_n_577}),
        .CFGPMFORCESTATE(cfg_pm_force_state),
        .CFGPMFORCESTATEENN(1'b1),
        .CFGPMHALTASPML0SN(1'b1),
        .CFGPMHALTASPML1N(1'b1),
        .CFGPMRCVASREQL1N(pcie_block_i_n_75),
        .CFGPMRCVENTERL1N(pcie_block_i_n_76),
        .CFGPMRCVENTERL23N(pcie_block_i_n_77),
        .CFGPMRCVREQACKN(pcie_block_i_n_78),
        .CFGPMSENDPMETON(1'b1),
        .CFGPMTURNOFFOKN(cfg_pm_turnoff_ok_n),
        .CFGPMWAKEN(1'b1),
        .CFGPORTNUMBER({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CFGREVID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CFGROOTCONTROLPMEINTEN(pcie_block_i_n_79),
        .CFGROOTCONTROLSYSERRCORRERREN(pcie_block_i_n_80),
        .CFGROOTCONTROLSYSERRFATALERREN(pcie_block_i_n_81),
        .CFGROOTCONTROLSYSERRNONFATALERREN(pcie_block_i_n_82),
        .CFGSLOTCONTROLELECTROMECHILCTLPULSE(pcie_block_i_n_83),
        .CFGSUBSYSID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}),
        .CFGSUBSYSVENDID({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b1,1'b1,1'b1,1'b0}),
        .CFGTRANSACTION(pcie_block_i_n_84),
        .CFGTRANSACTIONADDR({pcie_block_i_n_1097,pcie_block_i_n_1098,pcie_block_i_n_1099,pcie_block_i_n_1100,pcie_block_i_n_1101,pcie_block_i_n_1102,pcie_block_i_n_1103}),
        .CFGTRANSACTIONTYPE(pcie_block_i_n_85),
        .CFGTRNPENDINGN(1'b1),
        .CFGVCTCVCMAP({pcie_block_i_n_1104,pcie_block_i_n_1105,pcie_block_i_n_1106,pcie_block_i_n_1107,pcie_block_i_n_1108,pcie_block_i_n_1109,pcie_block_i_n_1110}),
        .CFGVENDID({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b1,1'b1,1'b1,1'b0}),
        .CMRSTN(1'b1),
        .CMSTICKYRSTN(1'b1),
        .DBGMODE({1'b0,1'b0}),
        .DBGSCLRA(pcie_block_i_n_86),
        .DBGSCLRB(pcie_block_i_n_87),
        .DBGSCLRC(pcie_block_i_n_88),
        .DBGSCLRD(pcie_block_i_n_89),
        .DBGSCLRE(pcie_block_i_n_90),
        .DBGSCLRF(pcie_block_i_n_91),
        .DBGSCLRG(pcie_block_i_n_92),
        .DBGSCLRH(pcie_block_i_n_93),
        .DBGSCLRI(pcie_block_i_n_94),
        .DBGSCLRJ(pcie_block_i_n_95),
        .DBGSCLRK(pcie_block_i_n_96),
        .DBGSUBMODE(1'b0),
        .DBGVECA({pcie_block_i_n_704,pcie_block_i_n_705,pcie_block_i_n_706,pcie_block_i_n_707,pcie_block_i_n_708,pcie_block_i_n_709,pcie_block_i_n_710,pcie_block_i_n_711,pcie_block_i_n_712,pcie_block_i_n_713,pcie_block_i_n_714,pcie_block_i_n_715,pcie_block_i_n_716,pcie_block_i_n_717,pcie_block_i_n_718,pcie_block_i_n_719,pcie_block_i_n_720,pcie_block_i_n_721,pcie_block_i_n_722,pcie_block_i_n_723,pcie_block_i_n_724,pcie_block_i_n_725,pcie_block_i_n_726,pcie_block_i_n_727,pcie_block_i_n_728,pcie_block_i_n_729,pcie_block_i_n_730,pcie_block_i_n_731,pcie_block_i_n_732,pcie_block_i_n_733,pcie_block_i_n_734,pcie_block_i_n_735,pcie_block_i_n_736,pcie_block_i_n_737,pcie_block_i_n_738,pcie_block_i_n_739,pcie_block_i_n_740,pcie_block_i_n_741,pcie_block_i_n_742,pcie_block_i_n_743,pcie_block_i_n_744,pcie_block_i_n_745,pcie_block_i_n_746,pcie_block_i_n_747,pcie_block_i_n_748,pcie_block_i_n_749,pcie_block_i_n_750,pcie_block_i_n_751,pcie_block_i_n_752,pcie_block_i_n_753,pcie_block_i_n_754,pcie_block_i_n_755,pcie_block_i_n_756,pcie_block_i_n_757,pcie_block_i_n_758,pcie_block_i_n_759,pcie_block_i_n_760,pcie_block_i_n_761,pcie_block_i_n_762,pcie_block_i_n_763,pcie_block_i_n_764,pcie_block_i_n_765,pcie_block_i_n_766,pcie_block_i_n_767}),
        .DBGVECB({pcie_block_i_n_768,pcie_block_i_n_769,pcie_block_i_n_770,pcie_block_i_n_771,pcie_block_i_n_772,pcie_block_i_n_773,pcie_block_i_n_774,pcie_block_i_n_775,pcie_block_i_n_776,pcie_block_i_n_777,pcie_block_i_n_778,pcie_block_i_n_779,pcie_block_i_n_780,pcie_block_i_n_781,pcie_block_i_n_782,pcie_block_i_n_783,pcie_block_i_n_784,pcie_block_i_n_785,pcie_block_i_n_786,pcie_block_i_n_787,pcie_block_i_n_788,pcie_block_i_n_789,pcie_block_i_n_790,pcie_block_i_n_791,pcie_block_i_n_792,pcie_block_i_n_793,pcie_block_i_n_794,pcie_block_i_n_795,pcie_block_i_n_796,pcie_block_i_n_797,pcie_block_i_n_798,pcie_block_i_n_799,pcie_block_i_n_800,pcie_block_i_n_801,pcie_block_i_n_802,pcie_block_i_n_803,pcie_block_i_n_804,pcie_block_i_n_805,pcie_block_i_n_806,pcie_block_i_n_807,pcie_block_i_n_808,pcie_block_i_n_809,pcie_block_i_n_810,pcie_block_i_n_811,pcie_block_i_n_812,pcie_block_i_n_813,pcie_block_i_n_814,pcie_block_i_n_815,pcie_block_i_n_816,pcie_block_i_n_817,pcie_block_i_n_818,pcie_block_i_n_819,pcie_block_i_n_820,pcie_block_i_n_821,pcie_block_i_n_822,pcie_block_i_n_823,pcie_block_i_n_824,pcie_block_i_n_825,pcie_block_i_n_826,pcie_block_i_n_827,pcie_block_i_n_828,pcie_block_i_n_829,pcie_block_i_n_830,pcie_block_i_n_831}),
        .DBGVECC({pcie_block_i_n_172,pcie_block_i_n_173,pcie_block_i_n_174,pcie_block_i_n_175,pcie_block_i_n_176,pcie_block_i_n_177,pcie_block_i_n_178,pcie_block_i_n_179,pcie_block_i_n_180,pcie_block_i_n_181,pcie_block_i_n_182,pcie_block_i_n_183}),
        .DLRSTN(1'b1),
        .DRPADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DRPCLK(1'b1),
        .DRPDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DRPDO({pcie_block_i_n_428,pcie_block_i_n_429,pcie_block_i_n_430,pcie_block_i_n_431,pcie_block_i_n_432,pcie_block_i_n_433,pcie_block_i_n_434,pcie_block_i_n_435,pcie_block_i_n_436,pcie_block_i_n_437,pcie_block_i_n_438,pcie_block_i_n_439,pcie_block_i_n_440,pcie_block_i_n_441,pcie_block_i_n_442,pcie_block_i_n_443}),
        .DRPEN(1'b0),
        .DRPRDY(pcie_block_i_n_97),
        .DRPWE(1'b0),
        .FUNCLVLRSTN(1'b1),
        .LL2BADDLLPERR(pcie_block_i_n_98),
        .LL2BADTLPERR(pcie_block_i_n_99),
        .LL2LINKSTATUS({pcie_block_i_n_687,pcie_block_i_n_688,pcie_block_i_n_689,pcie_block_i_n_690,pcie_block_i_n_691}),
        .LL2PROTOCOLERR(pcie_block_i_n_100),
        .LL2RECEIVERERR(pcie_block_i_n_101),
        .LL2REPLAYROERR(pcie_block_i_n_102),
        .LL2REPLAYTOERR(pcie_block_i_n_103),
        .LL2SENDASREQL1(1'b0),
        .LL2SENDENTERL1(1'b0),
        .LL2SENDENTERL23(1'b0),
        .LL2SENDPMACK(1'b0),
        .LL2SUSPENDNOW(1'b0),
        .LL2SUSPENDOK(pcie_block_i_n_104),
        .LL2TFCINIT1SEQ(pcie_block_i_n_105),
        .LL2TFCINIT2SEQ(pcie_block_i_n_106),
        .LL2TLPRCV(1'b0),
        .LL2TXIDLE(pcie_block_i_n_107),
        .LNKCLKEN(pcie_block_i_n_108),
        .MIMRXRADDR(mim_rx_raddr),
        .MIMRXRDATA(mim_rx_rdata),
        .MIMRXREN(mim_rx_ren),
        .MIMRXWADDR(mim_rx_waddr),
        .MIMRXWDATA(mim_rx_wdata),
        .MIMRXWEN(mim_rx_wen),
        .MIMTXRADDR(mim_tx_raddr),
        .MIMTXRDATA(mim_tx_rdata),
        .MIMTXREN(mim_tx_ren),
        .MIMTXWADDR(mim_tx_waddr),
        .MIMTXWDATA(mim_tx_wdata),
        .MIMTXWEN(mim_tx_wen),
        .PIPECLK(pcie_block_i_5),
        .PIPERX0CHANISALIGNED(pipe_rx0_chanisaligned),
        .PIPERX0CHARISK(pcie_block_i_8),
        .PIPERX0DATA(Q),
        .PIPERX0ELECIDLE(pipe_rx0_elec_idle),
        .PIPERX0PHYSTATUS(pipe_rx0_phy_status),
        .PIPERX0POLARITY(pipe_rx0_polarity),
        .PIPERX0STATUS(pcie_block_i_10),
        .PIPERX0VALID(pipe_rx0_valid),
        .PIPERX1CHANISALIGNED(pipe_rx1_chanisaligned),
        .PIPERX1CHARISK(pcie_block_i_9),
        .PIPERX1DATA(pcie_block_i_7),
        .PIPERX1ELECIDLE(pipe_rx1_elec_idle),
        .PIPERX1PHYSTATUS(pipe_rx1_phy_status),
        .PIPERX1POLARITY(pipe_rx1_polarity),
        .PIPERX1STATUS(pcie_block_i_11),
        .PIPERX1VALID(pipe_rx1_valid),
        .PIPERX2CHANISALIGNED(1'b0),
        .PIPERX2CHARISK({1'b0,1'b0}),
        .PIPERX2DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PIPERX2ELECIDLE(1'b1),
        .PIPERX2PHYSTATUS(1'b0),
        .PIPERX2POLARITY(pipe_rx2_polarity),
        .PIPERX2STATUS({1'b0,1'b0,1'b0}),
        .PIPERX2VALID(1'b0),
        .PIPERX3CHANISALIGNED(1'b0),
        .PIPERX3CHARISK({1'b0,1'b0}),
        .PIPERX3DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PIPERX3ELECIDLE(1'b1),
        .PIPERX3PHYSTATUS(1'b0),
        .PIPERX3POLARITY(pipe_rx3_polarity),
        .PIPERX3STATUS({1'b0,1'b0,1'b0}),
        .PIPERX3VALID(1'b0),
        .PIPERX4CHANISALIGNED(1'b0),
        .PIPERX4CHARISK({1'b0,1'b0}),
        .PIPERX4DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PIPERX4ELECIDLE(1'b1),
        .PIPERX4PHYSTATUS(1'b0),
        .PIPERX4POLARITY(pipe_rx4_polarity),
        .PIPERX4STATUS({1'b0,1'b0,1'b0}),
        .PIPERX4VALID(1'b0),
        .PIPERX5CHANISALIGNED(1'b0),
        .PIPERX5CHARISK({1'b0,1'b0}),
        .PIPERX5DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PIPERX5ELECIDLE(1'b1),
        .PIPERX5PHYSTATUS(1'b0),
        .PIPERX5POLARITY(pipe_rx5_polarity),
        .PIPERX5STATUS({1'b0,1'b0,1'b0}),
        .PIPERX5VALID(1'b0),
        .PIPERX6CHANISALIGNED(1'b0),
        .PIPERX6CHARISK({1'b0,1'b0}),
        .PIPERX6DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PIPERX6ELECIDLE(1'b1),
        .PIPERX6PHYSTATUS(1'b0),
        .PIPERX6POLARITY(pipe_rx6_polarity),
        .PIPERX6STATUS({1'b0,1'b0,1'b0}),
        .PIPERX6VALID(1'b0),
        .PIPERX7CHANISALIGNED(1'b0),
        .PIPERX7CHARISK({1'b0,1'b0}),
        .PIPERX7DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PIPERX7ELECIDLE(1'b1),
        .PIPERX7PHYSTATUS(1'b0),
        .PIPERX7POLARITY(pipe_rx7_polarity),
        .PIPERX7STATUS({1'b0,1'b0,1'b0}),
        .PIPERX7VALID(1'b0),
        .PIPETX0CHARISK(pipe_tx0_char_is_k),
        .PIPETX0COMPLIANCE(pipe_tx0_compliance),
        .PIPETX0DATA(pipe_tx0_data),
        .PIPETX0ELECIDLE(pipe_tx0_elec_idle),
        .PIPETX0POWERDOWN(pipe_tx0_powerdown),
        .PIPETX1CHARISK(pipe_tx1_char_is_k),
        .PIPETX1COMPLIANCE(pipe_tx1_compliance),
        .PIPETX1DATA(pipe_tx1_data),
        .PIPETX1ELECIDLE(pipe_tx1_elec_idle),
        .PIPETX1POWERDOWN(pipe_tx1_powerdown),
        .PIPETX2CHARISK(pipe_tx2_char_is_k),
        .PIPETX2COMPLIANCE(pipe_tx2_compliance),
        .PIPETX2DATA(pipe_tx2_data),
        .PIPETX2ELECIDLE(pipe_tx2_elec_idle),
        .PIPETX2POWERDOWN(pipe_tx2_powerdown),
        .PIPETX3CHARISK(pipe_tx3_char_is_k),
        .PIPETX3COMPLIANCE(pipe_tx3_compliance),
        .PIPETX3DATA(pipe_tx3_data),
        .PIPETX3ELECIDLE(pipe_tx3_elec_idle),
        .PIPETX3POWERDOWN(pipe_tx3_powerdown),
        .PIPETX4CHARISK(pipe_tx4_char_is_k),
        .PIPETX4COMPLIANCE(pipe_tx4_compliance),
        .PIPETX4DATA(pipe_tx4_data),
        .PIPETX4ELECIDLE(pipe_tx4_elec_idle),
        .PIPETX4POWERDOWN(pipe_tx4_powerdown),
        .PIPETX5CHARISK(pipe_tx5_char_is_k),
        .PIPETX5COMPLIANCE(pipe_tx5_compliance),
        .PIPETX5DATA(pipe_tx5_data),
        .PIPETX5ELECIDLE(pipe_tx5_elec_idle),
        .PIPETX5POWERDOWN(pipe_tx5_powerdown),
        .PIPETX6CHARISK(pipe_tx6_char_is_k),
        .PIPETX6COMPLIANCE(pipe_tx6_compliance),
        .PIPETX6DATA(pipe_tx6_data),
        .PIPETX6ELECIDLE(pipe_tx6_elec_idle),
        .PIPETX6POWERDOWN(pipe_tx6_powerdown),
        .PIPETX7CHARISK(pipe_tx7_char_is_k),
        .PIPETX7COMPLIANCE(pipe_tx7_compliance),
        .PIPETX7DATA(pipe_tx7_data),
        .PIPETX7ELECIDLE(pipe_tx7_elec_idle),
        .PIPETX7POWERDOWN(pipe_tx7_powerdown),
        .PIPETXDEEMPH(pipe_tx_deemph),
        .PIPETXMARGIN(pipe_tx_margin),
        .PIPETXRATE(pipe_tx_rate),
        .PIPETXRCVRDET(pipe_tx_rcvr_det),
        .PIPETXRESET(pcie_block_i_n_140),
        .PL2DIRECTEDLSTATE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PL2L0REQ(pcie_block_i_n_141),
        .PL2LINKUP(pcie_block_i_n_142),
        .PL2RECEIVERERR(pcie_block_i_n_143),
        .PL2RECOVERY(pcie_block_i_n_144),
        .PL2RXELECIDLE(pcie_block_i_n_145),
        .PL2RXPMSTATE({pcie_block_i_n_610,pcie_block_i_n_611}),
        .PL2SUSPENDOK(pcie_block_i_n_146),
        .PLDBGMODE({1'b0,1'b0,1'b0}),
        .PLDBGVEC({pcie_block_i_n_184,pcie_block_i_n_185,pcie_block_i_n_186,pcie_block_i_n_187,pcie_block_i_n_188,pcie_block_i_n_189,pcie_block_i_n_190,pcie_block_i_n_191,pcie_block_i_n_192,pcie_block_i_n_193,pcie_block_i_n_194,pcie_block_i_n_195}),
        .PLDIRECTEDCHANGEDONE(pcie_block_i_n_147),
        .PLDIRECTEDLINKAUTON(pl_directed_link_auton),
        .PLDIRECTEDLINKCHANGE(pl_directed_link_change),
        .PLDIRECTEDLINKSPEED(pl_directed_link_speed),
        .PLDIRECTEDLINKWIDTH(pl_directed_link_width),
        .PLDIRECTEDLTSSMNEW({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PLDIRECTEDLTSSMNEWVLD(1'b0),
        .PLDIRECTEDLTSSMSTALL(1'b0),
        .PLDOWNSTREAMDEEMPHSOURCE(1'b0),
        .PLINITIALLINKWIDTH({pcie_block_i_n_637,pcie_block_i_n_638,pcie_block_i_n_639}),
        .PLLANEREVERSALMODE({pcie_block_i_n_612,pcie_block_i_n_613}),
        .PLLINKGEN2CAP(pcie_block_i_n_148),
        .PLLINKPARTNERGEN2SUPPORTED(pcie_block_i_n_149),
        .PLLINKUPCFGCAP(pcie_block_i_n_150),
        .PLLTSSMSTATE(pl_ltssm_state),
        .PLPHYLNKUPN(pl_phy_lnk_up_n),
        .PLRECEIVEDHOTRST(pl_received_hot_rst),
        .PLRSTN(1'b1),
        .PLRXPMSTATE({pcie_block_i_n_614,pcie_block_i_n_615}),
        .PLSELLNKRATE(pcie_block_i_n_153),
        .PLSELLNKWIDTH({pcie_block_i_n_616,pcie_block_i_n_617}),
        .PLTRANSMITHOTRST(1'b0),
        .PLTXPMSTATE({pcie_block_i_n_640,pcie_block_i_n_641,pcie_block_i_n_642}),
        .PLUPSTREAMPREFERDEEMPH(pl_upstream_prefer_deemph),
        .RECEIVEDFUNCLVLRSTN(cfg_received_func_lvl_rst_n),
        .SYSRSTN(sys_rst_n),
        .TL2ASPMSUSPENDCREDITCHECK(1'b0),
        .TL2ASPMSUSPENDCREDITCHECKOK(pcie_block_i_n_155),
        .TL2ASPMSUSPENDREQ(pcie_block_i_n_156),
        .TL2ERRFCPE(pcie_block_i_n_157),
        .TL2ERRHDR({pcie_block_i_n_832,pcie_block_i_n_833,pcie_block_i_n_834,pcie_block_i_n_835,pcie_block_i_n_836,pcie_block_i_n_837,pcie_block_i_n_838,pcie_block_i_n_839,pcie_block_i_n_840,pcie_block_i_n_841,pcie_block_i_n_842,pcie_block_i_n_843,pcie_block_i_n_844,pcie_block_i_n_845,pcie_block_i_n_846,pcie_block_i_n_847,pcie_block_i_n_848,pcie_block_i_n_849,pcie_block_i_n_850,pcie_block_i_n_851,pcie_block_i_n_852,pcie_block_i_n_853,pcie_block_i_n_854,pcie_block_i_n_855,pcie_block_i_n_856,pcie_block_i_n_857,pcie_block_i_n_858,pcie_block_i_n_859,pcie_block_i_n_860,pcie_block_i_n_861,pcie_block_i_n_862,pcie_block_i_n_863,pcie_block_i_n_864,pcie_block_i_n_865,pcie_block_i_n_866,pcie_block_i_n_867,pcie_block_i_n_868,pcie_block_i_n_869,pcie_block_i_n_870,pcie_block_i_n_871,pcie_block_i_n_872,pcie_block_i_n_873,pcie_block_i_n_874,pcie_block_i_n_875,pcie_block_i_n_876,pcie_block_i_n_877,pcie_block_i_n_878,pcie_block_i_n_879,pcie_block_i_n_880,pcie_block_i_n_881,pcie_block_i_n_882,pcie_block_i_n_883,pcie_block_i_n_884,pcie_block_i_n_885,pcie_block_i_n_886,pcie_block_i_n_887,pcie_block_i_n_888,pcie_block_i_n_889,pcie_block_i_n_890,pcie_block_i_n_891,pcie_block_i_n_892,pcie_block_i_n_893,pcie_block_i_n_894,pcie_block_i_n_895}),
        .TL2ERRMALFORMED(pcie_block_i_n_158),
        .TL2ERRRXOVERFLOW(pcie_block_i_n_159),
        .TL2PPMSUSPENDOK(pcie_block_i_n_160),
        .TL2PPMSUSPENDREQ(1'b0),
        .TLRSTN(1'b1),
        .TRNFCCPLD({pcie_block_i_n_196,pcie_block_i_n_197,pcie_block_i_n_198,pcie_block_i_n_199,pcie_block_i_n_200,pcie_block_i_n_201,pcie_block_i_n_202,pcie_block_i_n_203,pcie_block_i_n_204,pcie_block_i_n_205,pcie_block_i_n_206,pcie_block_i_n_207}),
        .TRNFCCPLH({pcie_block_i_n_1119,pcie_block_i_n_1120,pcie_block_i_n_1121,pcie_block_i_n_1122,pcie_block_i_n_1123,pcie_block_i_n_1124,pcie_block_i_n_1125,pcie_block_i_n_1126}),
        .TRNFCNPD({pcie_block_i_n_208,pcie_block_i_n_209,pcie_block_i_n_210,pcie_block_i_n_211,pcie_block_i_n_212,pcie_block_i_n_213,pcie_block_i_n_214,pcie_block_i_n_215,pcie_block_i_n_216,pcie_block_i_n_217,pcie_block_i_n_218,pcie_block_i_n_219}),
        .TRNFCNPH(fc_nph),
        .TRNFCPD({pcie_block_i_n_220,pcie_block_i_n_221,pcie_block_i_n_222,pcie_block_i_n_223,pcie_block_i_n_224,pcie_block_i_n_225,pcie_block_i_n_226,pcie_block_i_n_227,pcie_block_i_n_228,pcie_block_i_n_229,pcie_block_i_n_230,pcie_block_i_n_231}),
        .TRNFCPH({pcie_block_i_n_1135,pcie_block_i_n_1136,pcie_block_i_n_1137,pcie_block_i_n_1138,pcie_block_i_n_1139,pcie_block_i_n_1140,pcie_block_i_n_1141,pcie_block_i_n_1142}),
        .TRNFCSEL(fc_sel),
        .TRNLNKUP(trn_lnk_up),
        .TRNRBARHIT({pcie_block_i_n_1143,trn_rbar_hit}),
        .TRNRD({trn_rd,pcie_block_i_3}),
        .TRNRDLLPDATA({pcie_block_i_n_896,pcie_block_i_n_897,pcie_block_i_n_898,pcie_block_i_n_899,pcie_block_i_n_900,pcie_block_i_n_901,pcie_block_i_n_902,pcie_block_i_n_903,pcie_block_i_n_904,pcie_block_i_n_905,pcie_block_i_n_906,pcie_block_i_n_907,pcie_block_i_n_908,pcie_block_i_n_909,pcie_block_i_n_910,pcie_block_i_n_911,pcie_block_i_n_912,pcie_block_i_n_913,pcie_block_i_n_914,pcie_block_i_n_915,pcie_block_i_n_916,pcie_block_i_n_917,pcie_block_i_n_918,pcie_block_i_n_919,pcie_block_i_n_920,pcie_block_i_n_921,pcie_block_i_n_922,pcie_block_i_n_923,pcie_block_i_n_924,pcie_block_i_n_925,pcie_block_i_n_926,pcie_block_i_n_927,pcie_block_i_n_928,pcie_block_i_n_929,pcie_block_i_n_930,pcie_block_i_n_931,pcie_block_i_n_932,pcie_block_i_n_933,pcie_block_i_n_934,pcie_block_i_n_935,pcie_block_i_n_936,pcie_block_i_n_937,pcie_block_i_n_938,pcie_block_i_n_939,pcie_block_i_n_940,pcie_block_i_n_941,pcie_block_i_n_942,pcie_block_i_n_943,pcie_block_i_n_944,pcie_block_i_n_945,pcie_block_i_n_946,pcie_block_i_n_947,pcie_block_i_n_948,pcie_block_i_n_949,pcie_block_i_n_950,pcie_block_i_n_951,pcie_block_i_n_952,pcie_block_i_n_953,pcie_block_i_n_954,pcie_block_i_n_955,pcie_block_i_n_956,pcie_block_i_n_957,pcie_block_i_n_958,pcie_block_i_n_959}),
        .TRNRDLLPSRCRDY({pcie_block_i_n_618,pcie_block_i_n_619}),
        .TRNRDSTRDY(trn_rdst_rdy),
        .TRNRECRCERR(trn_recrc_err),
        .TRNREOF(trn_reof),
        .TRNRERRFWD(trn_rerrfwd),
        .TRNRFCPRET(1'b1),
        .TRNRNPOK(rx_np_ok),
        .TRNRNPREQ(rx_np_req),
        .TRNRREM({trn_rrem,pcie_block_i_4}),
        .TRNRSOF(trn_rsof),
        .TRNRSRCDSC(trn_rsrc_dsc),
        .TRNRSRCRDY(trn_rsrc_rdy),
        .TRNTBUFAV(trn_tbuf_av),
        .TRNTCFGGNT(trn_tcfg_gnt),
        .TRNTCFGREQ(trn_tcfg_req),
        .TRNTD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,trn_td}),
        .TRNTDLLPDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TRNTDLLPDSTRDY(pcie_block_i_n_169),
        .TRNTDLLPSRCRDY(1'b0),
        .TRNTDSTRDY({NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED[3:1],trn_tdst_rdy}),
        .TRNTECRCGEN(pcie_block_i_6[0]),
        .TRNTEOF(trn_teof),
        .TRNTERRDROP(pcie_block_i_n_170),
        .TRNTERRFWD(pcie_block_i_6[1]),
        .TRNTREM({1'b0,trn_trem}),
        .TRNTSOF(trn_tsof),
        .TRNTSRCDSC(pcie_block_i_6[3]),
        .TRNTSRCRDY(trn_tsrc_rdy),
        .TRNTSTR(pcie_block_i_6[2]),
        .USERCLK(CLK),
        .USERCLK2(CLK),
        .USERRSTN(user_rst_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_1
       (.I0(cfg_interrupt_assert),
        .O(pcie_block_i_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_2
       (.I0(cfg_interrupt),
        .O(pcie_block_i_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_3
       (.I0(cfg_mgmt_rd_en),
        .O(pcie_block_i_i_3_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_4
       (.I0(cfg_mgmt_wr_en),
        .O(pcie_block_i_i_4_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_5
       (.I0(cfg_mgmt_wr_readonly),
        .O(pcie_block_i_i_5_n_0));
  xdma_0_pcie2_ip_pcie_bram_top_7x pcie_bram_top
       (.CLK(CLK),
        .MIMRXRADDR(mim_rx_raddr[10:0]),
        .MIMRXWADDR(mim_rx_waddr[10:0]),
        .MIMTXRADDR(mim_tx_raddr[10:0]),
        .MIMTXWADDR(mim_tx_waddr[10:0]),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (mim_rx_rdata),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (mim_rx_wdata),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(mim_tx_rdata),
        .wdata(mim_tx_wdata));
  LUT1 #(
    .INIT(2'h1)) 
    phy_lnk_up_cdc_i_1
       (.I0(pl_phy_lnk_up_n),
        .O(src_in));
  LUT5 #(
    .INIT(32'hFFFEAAAA)) 
    ppm_L1_thrtl_i_1
       (.I0(ppm_L1_trig),
        .I1(cfg_pcie_link_state[0]),
        .I2(cfg_pcie_link_state[2]),
        .I3(cfg_pcie_link_state[1]),
        .I4(ppm_L1_thrtl),
        .O(pcie_block_i_0));
  LUT5 #(
    .INIT(32'h00000001)) 
    tbuf_av_min_thrtl_i_1
       (.I0(trn_tbuf_av[5]),
        .I1(trn_tbuf_av[4]),
        .I2(trn_tbuf_av[3]),
        .I3(trn_tbuf_av[2]),
        .I4(trn_tbuf_av[1]),
        .O(tbuf_av_min_trig));
  LUT6 #(
    .INIT(64'h0000000100010001)) 
    tready_thrtl_i_11
       (.I0(trn_tbuf_av[5]),
        .I1(trn_tbuf_av[4]),
        .I2(trn_tbuf_av[3]),
        .I3(trn_tbuf_av[2]),
        .I4(trn_tbuf_av[0]),
        .I5(trn_tbuf_av[1]),
        .O(pcie_block_i_1));
  LUT2 #(
    .INIT(4'h8)) 
    tready_thrtl_i_9
       (.I0(trn_tcfg_req),
        .I1(reg_tcfg_gnt),
        .O(tcfg_req_trig));
  LUT6 #(
    .INIT(64'h08000000AEAA2AAA)) 
    trn_in_packet_i_1
       (.I0(trn_in_packet),
        .I1(trn_rdst_rdy),
        .I2(trn_reof),
        .I3(trn_rsrc_rdy),
        .I4(trn_rsof),
        .I5(trn_rsrc_dsc),
        .O(trn_in_packet_reg));
  (* SOFT_HLUTNM = "soft_lutpair1899" *) 
  LUT2 #(
    .INIT(4'hE)) 
    trn_rsrc_dsc_prev_i_1
       (.I0(trn_rsrc_dsc),
        .I1(reg_dsc_detect),
        .O(trn_rsrc_dsc_prev0));
  (* SOFT_HLUTNM = "soft_lutpair1899" *) 
  LUT4 #(
    .INIT(16'hAA08)) 
    trn_rsrc_rdy_prev_i_1
       (.I0(trn_rsrc_rdy),
        .I1(trn_rsof),
        .I2(trn_rsrc_dsc),
        .I3(trn_in_packet),
        .O(rsrc_rdy_filtered));
  LUT3 #(
    .INIT(8'h2A)) 
    user_reset_int_i_1
       (.I0(bridge_reset_int),
        .I1(pl_phy_lnk_up),
        .I2(user_rst_n),
        .O(user_reset_int_reg));
endmodule

module xdma_0_pcie2_ip_pcie_bram_7x
   (rdata,
    CLK,
    mim_tx_wen,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input CLK;
  input mim_tx_wen;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire CLK;
  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [17:0]rdata;
  wire [17:0]wdata;

  xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_21 \use_tdp.ramb36 
       (.CLK(CLK),
        .MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata),
        .wdata(wdata));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pcie_bram_7x" *) 
module xdma_0_pcie2_ip_pcie_bram_7x_16
   (rdata,
    CLK,
    mim_tx_wen,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input CLK;
  input mim_tx_wen;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire CLK;
  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [17:0]rdata;
  wire [17:0]wdata;

  xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_20 \use_tdp.ramb36 
       (.CLK(CLK),
        .MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata),
        .wdata(wdata));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pcie_bram_7x" *) 
module xdma_0_pcie2_ip_pcie_bram_7x_17
   (rdata,
    CLK,
    mim_tx_wen,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input CLK;
  input mim_tx_wen;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire CLK;
  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [17:0]rdata;
  wire [17:0]wdata;

  xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_19 \use_tdp.ramb36 
       (.CLK(CLK),
        .MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata),
        .wdata(wdata));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pcie_bram_7x" *) 
module xdma_0_pcie2_ip_pcie_bram_7x_18
   (rdata,
    CLK,
    mim_tx_wen,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [14:0]rdata;
  input CLK;
  input mim_tx_wen;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [14:0]wdata;

  wire CLK;
  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [14:0]rdata;
  wire [14:0]wdata;

  xdma_0_xil_internal_svlib_BRAM_TDP_MACRO \use_tdp.ramb36 
       (.CLK(CLK),
        .MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata),
        .wdata(wdata));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pcie_bram_7x" *) 
module xdma_0_pcie2_ip_pcie_bram_7x_22
   (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ,
    CLK,
    mim_rx_wen,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 );
  output [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  input CLK;
  input mim_rx_wen;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;

  wire CLK;
  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  wire mim_rx_ren;
  wire mim_rx_wen;

  xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_29 \use_tdp.ramb36 
       (.CLK(CLK),
        .MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pcie_bram_7x" *) 
module xdma_0_pcie2_ip_pcie_bram_7x_23
   (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ,
    CLK,
    mim_rx_wen,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 );
  output [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  input CLK;
  input mim_rx_wen;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;

  wire CLK;
  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  wire mim_rx_ren;
  wire mim_rx_wen;

  xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_28 \use_tdp.ramb36 
       (.CLK(CLK),
        .MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pcie_bram_7x" *) 
module xdma_0_pcie2_ip_pcie_bram_7x_24
   (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ,
    CLK,
    mim_rx_wen,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 );
  output [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  input CLK;
  input mim_rx_wen;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;

  wire CLK;
  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  wire mim_rx_ren;
  wire mim_rx_wen;

  xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_27 \use_tdp.ramb36 
       (.CLK(CLK),
        .MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pcie_bram_7x" *) 
module xdma_0_pcie2_ip_pcie_bram_7x_25
   (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ,
    CLK,
    mim_rx_wen,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 );
  output [13:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  input CLK;
  input mim_rx_wen;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [13:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;

  wire CLK;
  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire [13:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  wire [13:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  wire mim_rx_ren;
  wire mim_rx_wen;

  xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_26 \use_tdp.ramb36 
       (.CLK(CLK),
        .MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen));
endmodule

module xdma_0_pcie2_ip_pcie_bram_top_7x
   (rdata,
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl ,
    CLK,
    mim_tx_wen,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata,
    mim_rx_wen,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 );
  output [68:0]rdata;
  output [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  input CLK;
  input mim_tx_wen;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [68:0]wdata;
  input mim_rx_wen;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;

  wire CLK;
  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  wire [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [68:0]rdata;
  wire [68:0]wdata;

  xdma_0_pcie2_ip_pcie_brams_7x pcie_brams_rx
       (.CLK(CLK),
        .MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen));
  xdma_0_pcie2_ip_pcie_brams_7x_15 pcie_brams_tx
       (.CLK(CLK),
        .MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata),
        .wdata(wdata));
endmodule

module xdma_0_pcie2_ip_pcie_brams_7x
   (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ,
    CLK,
    mim_rx_wen,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 );
  output [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  input CLK;
  input mim_rx_wen;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;

  wire CLK;
  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl ;
  wire [67:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  wire mim_rx_ren;
  wire mim_rx_wen;

  xdma_0_pcie2_ip_pcie_bram_7x_22 \brams[0].ram 
       (.CLK(CLK),
        .MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [17:0]),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [17:0]),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen));
  xdma_0_pcie2_ip_pcie_bram_7x_23 \brams[1].ram 
       (.CLK(CLK),
        .MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [35:18]),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [35:18]),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen));
  xdma_0_pcie2_ip_pcie_bram_7x_24 \brams[2].ram 
       (.CLK(CLK),
        .MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [53:36]),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [53:36]),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen));
  xdma_0_pcie2_ip_pcie_bram_7x_25 \brams[3].ram 
       (.CLK(CLK),
        .MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl [67:54]),
        .\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [67:54]),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pcie_brams_7x" *) 
module xdma_0_pcie2_ip_pcie_brams_7x_15
   (rdata,
    CLK,
    mim_tx_wen,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [68:0]rdata;
  input CLK;
  input mim_tx_wen;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [68:0]wdata;

  wire CLK;
  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [68:0]rdata;
  wire [68:0]wdata;

  xdma_0_pcie2_ip_pcie_bram_7x \brams[0].ram 
       (.CLK(CLK),
        .MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata[17:0]),
        .wdata(wdata[17:0]));
  xdma_0_pcie2_ip_pcie_bram_7x_16 \brams[1].ram 
       (.CLK(CLK),
        .MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata[35:18]),
        .wdata(wdata[35:18]));
  xdma_0_pcie2_ip_pcie_bram_7x_17 \brams[2].ram 
       (.CLK(CLK),
        .MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata[53:36]),
        .wdata(wdata[53:36]));
  xdma_0_pcie2_ip_pcie_bram_7x_18 \brams[3].ram 
       (.CLK(CLK),
        .MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata[68:54]),
        .wdata(wdata[68:54]));
endmodule

module xdma_0_pcie2_ip_pcie_pipe_lane
   (pipe_rx1_valid,
    pipe_rx1_chanisaligned,
    pipe_rx1_phy_status,
    pipe_rx1_elec_idle,
    pipe_rx1_polarity_gt,
    \pipe_stages_1.pipe_tx_compliance_q_reg_0 ,
    pipe_tx1_elec_idle_gt,
    Q,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0 ,
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ,
    \pipe_stages_1.pipe_tx_data_q_reg[15]_0 ,
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ,
    SR,
    pipe_rx1_valid_gt,
    \pipe_stages_1.pipe_rx_valid_q_reg_0 ,
    pipe_rx1_chanisaligned_gt,
    \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ,
    pipe_rx1_polarity,
    pipe_tx1_compliance,
    pipe_tx1_elec_idle,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_1 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_1 ,
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ,
    \pipe_stages_1.pipe_tx_data_q_reg[15]_1 ,
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 );
  output pipe_rx1_valid;
  output pipe_rx1_chanisaligned;
  output pipe_rx1_phy_status;
  output pipe_rx1_elec_idle;
  output pipe_rx1_polarity_gt;
  output [0:0]\pipe_stages_1.pipe_tx_compliance_q_reg_0 ;
  output pipe_tx1_elec_idle_gt;
  output [1:0]Q;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  output [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ;
  output [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ;
  output [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ;
  input [0:0]SR;
  input pipe_rx1_valid_gt;
  input \pipe_stages_1.pipe_rx_valid_q_reg_0 ;
  input pipe_rx1_chanisaligned_gt;
  input \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ;
  input \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ;
  input pipe_rx1_polarity;
  input pipe_tx1_compliance;
  input pipe_tx1_elec_idle;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ;
  input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ;
  input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_1 ;
  input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ;

  wire [1:0]Q;
  wire [0:0]SR;
  wire pipe_rx1_chanisaligned;
  wire pipe_rx1_chanisaligned_gt;
  wire pipe_rx1_elec_idle;
  wire pipe_rx1_phy_status;
  wire pipe_rx1_polarity;
  wire pipe_rx1_polarity_gt;
  wire pipe_rx1_valid;
  wire pipe_rx1_valid_gt;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ;
  wire \pipe_stages_1.pipe_rx_valid_q_reg_0 ;
  wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ;
  wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ;
  wire [0:0]\pipe_stages_1.pipe_tx_compliance_q_reg_0 ;
  wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ;
  wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_1 ;
  wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ;
  wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ;
  wire pipe_tx1_compliance;
  wire pipe_tx1_elec_idle;
  wire pipe_tx1_elec_idle_gt;

  FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_rx1_chanisaligned_gt),
        .Q(pipe_rx1_chanisaligned),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 [0]),
        .Q(Q[0]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 [1]),
        .Q(Q[1]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [0]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [0]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [10]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [10]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [11]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [11]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [12]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [12]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [13]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [13]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [14]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [14]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [15]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [15]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [1]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [1]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [2]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [2]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [3]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [3]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [4]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [4]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [5]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [5]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [6]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [6]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [7]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [7]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [8]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [8]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [9]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [9]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ),
        .Q(pipe_rx1_elec_idle),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_phy_status_q_reg_0 ),
        .Q(pipe_rx1_phy_status),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_polarity_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_rx1_polarity),
        .Q(pipe_rx1_polarity_gt),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [0]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [0]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [1]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [1]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [2]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [2]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_valid_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_rx1_valid_gt),
        .Q(pipe_rx1_valid),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 [0]),
        .Q(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [0]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 [1]),
        .Q(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [1]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_compliance_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_tx1_compliance),
        .Q(\pipe_stages_1.pipe_tx_compliance_q_reg_0 ),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [0]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [0]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [10]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [10]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [11]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [11]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [12]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [12]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [13]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [13]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [14]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [14]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [15]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [15]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [1]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [1]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [2]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [2]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [3]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [3]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [4]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [4]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [5]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [5]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [6]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [6]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [7]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [7]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [8]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [8]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [9]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [9]),
        .R(SR));
  FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_tx1_elec_idle),
        .Q(pipe_tx1_elec_idle_gt),
        .S(SR));
  FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 [0]),
        .Q(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [0]),
        .R(SR));
  FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 [1]),
        .Q(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [1]),
        .S(SR));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pcie_pipe_lane" *) 
module xdma_0_pcie2_ip_pcie_pipe_lane_14
   (pipe_rx0_polarity_gt,
    TXCHARDISPMODE,
    pipe_tx0_elec_idle_gt,
    pipe_rx0_valid,
    pipe_rx0_chanisaligned,
    pipe_rx0_phy_status,
    pipe_rx0_elec_idle,
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ,
    \pipe_stages_1.pipe_tx_data_q_reg[15]_0 ,
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0 ,
    SR,
    pipe_rx0_polarity,
    \pipe_stages_1.pipe_rx_valid_q_reg_0 ,
    pipe_tx0_compliance,
    pipe_tx0_elec_idle,
    pipe_rx0_valid_gt,
    pipe_rx0_chanisaligned_gt,
    gt_rx_phy_status_q,
    gt_rxelecidle_q,
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ,
    \pipe_stages_1.pipe_tx_data_q_reg[15]_1 ,
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_1 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_1 );
  output pipe_rx0_polarity_gt;
  output [0:0]TXCHARDISPMODE;
  output pipe_tx0_elec_idle_gt;
  output pipe_rx0_valid;
  output pipe_rx0_chanisaligned;
  output pipe_rx0_phy_status;
  output pipe_rx0_elec_idle;
  output [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ;
  output [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ;
  output [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  input [0:0]SR;
  input pipe_rx0_polarity;
  input \pipe_stages_1.pipe_rx_valid_q_reg_0 ;
  input pipe_tx0_compliance;
  input pipe_tx0_elec_idle;
  input pipe_rx0_valid_gt;
  input pipe_rx0_chanisaligned_gt;
  input gt_rx_phy_status_q;
  input gt_rxelecidle_q;
  input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ;
  input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_1 ;
  input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ;

  wire [0:0]SR;
  wire [0:0]TXCHARDISPMODE;
  wire gt_rx_phy_status_q;
  wire gt_rxelecidle_q;
  wire pipe_rx0_chanisaligned;
  wire pipe_rx0_chanisaligned_gt;
  wire pipe_rx0_elec_idle;
  wire pipe_rx0_phy_status;
  wire pipe_rx0_polarity;
  wire pipe_rx0_polarity_gt;
  wire pipe_rx0_valid;
  wire pipe_rx0_valid_gt;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ;
  wire \pipe_stages_1.pipe_rx_valid_q_reg_0 ;
  wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ;
  wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ;
  wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ;
  wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_1 ;
  wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ;
  wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ;
  wire pipe_tx0_compliance;
  wire pipe_tx0_elec_idle;
  wire pipe_tx0_elec_idle_gt;

  FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_rx0_chanisaligned_gt),
        .Q(pipe_rx0_chanisaligned),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 [0]),
        .Q(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 [0]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 [1]),
        .Q(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 [1]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [0]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [0]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [10]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [10]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [11]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [11]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [12]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [12]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [13]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [13]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [14]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [14]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [15]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [15]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [1]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [1]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [2]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [2]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [3]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [3]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [4]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [4]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [5]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [5]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [6]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [6]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [7]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [7]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [8]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [8]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 [9]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 [9]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(gt_rxelecidle_q),
        .Q(pipe_rx0_elec_idle),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(gt_rx_phy_status_q),
        .Q(pipe_rx0_phy_status),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_polarity_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_rx0_polarity),
        .Q(pipe_rx0_polarity_gt),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [0]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [0]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [1]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [1]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 [2]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 [2]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_rx_valid_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_rx0_valid_gt),
        .Q(pipe_rx0_valid),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 [0]),
        .Q(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [0]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 [1]),
        .Q(\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 [1]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_compliance_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_tx0_compliance),
        .Q(TXCHARDISPMODE),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [0]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [0]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [10]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [10]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [11]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [11]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [12]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [12]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [13]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [13]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [14]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [14]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [15]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [15]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [1]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [1]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [2]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [2]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [3]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [3]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [4]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [4]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [5]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [5]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [6]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [6]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [7]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [7]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [8]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [8]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_data_q_reg[15]_1 [9]),
        .Q(\pipe_stages_1.pipe_tx_data_q_reg[15]_0 [9]),
        .R(SR));
  FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_tx0_elec_idle),
        .Q(pipe_tx0_elec_idle_gt),
        .S(SR));
  FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 [0]),
        .Q(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [0]),
        .R(SR));
  FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] 
       (.C(\pipe_stages_1.pipe_rx_valid_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 [1]),
        .Q(\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 [1]),
        .S(SR));
endmodule

module xdma_0_pcie2_ip_pcie_pipe_misc
   (pipe_tx_rcvr_det_gt,
    D,
    pipe_tx_deemph_gt,
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ,
    SR,
    pipe_tx_rcvr_det,
    \pipe_stages_1.pipe_tx_deemph_q_reg_0 ,
    pipe_tx_rate,
    pipe_tx_deemph,
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_1 );
  output pipe_tx_rcvr_det_gt;
  output [0:0]D;
  output pipe_tx_deemph_gt;
  output [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ;
  input [0:0]SR;
  input pipe_tx_rcvr_det;
  input \pipe_stages_1.pipe_tx_deemph_q_reg_0 ;
  input pipe_tx_rate;
  input pipe_tx_deemph;
  input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 ;

  wire [0:0]D;
  wire [0:0]SR;
  wire \pipe_stages_1.pipe_tx_deemph_q_reg_0 ;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 ;
  wire pipe_tx_deemph;
  wire pipe_tx_deemph_gt;
  wire pipe_tx_rate;
  wire pipe_tx_rcvr_det;
  wire pipe_tx_rcvr_det_gt;

  FDSE \pipe_stages_1.pipe_tx_deemph_q_reg 
       (.C(\pipe_stages_1.pipe_tx_deemph_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_tx_deemph),
        .Q(pipe_tx_deemph_gt),
        .S(SR));
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[0] 
       (.C(\pipe_stages_1.pipe_tx_deemph_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 [0]),
        .Q(\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 [0]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[1] 
       (.C(\pipe_stages_1.pipe_tx_deemph_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 [1]),
        .Q(\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 [1]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[2] 
       (.C(\pipe_stages_1.pipe_tx_deemph_q_reg_0 ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 [2]),
        .Q(\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 [2]),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_rate_q_reg 
       (.C(\pipe_stages_1.pipe_tx_deemph_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_tx_rate),
        .Q(D),
        .R(SR));
  FDRE \pipe_stages_1.pipe_tx_rcvr_det_q_reg 
       (.C(\pipe_stages_1.pipe_tx_deemph_q_reg_0 ),
        .CE(1'b1),
        .D(pipe_tx_rcvr_det),
        .Q(pipe_tx_rcvr_det_gt),
        .R(SR));
endmodule

module xdma_0_pcie2_ip_pcie_pipe_pipeline
   (pipe_rx1_valid,
    pipe_rx1_chanisaligned,
    pipe_rx1_phy_status,
    pipe_rx1_elec_idle,
    pipe_rx0_polarity_gt,
    pipe_rx1_polarity_gt,
    TXCHARDISPMODE,
    \pipe_stages_1.pipe_tx_compliance_q_reg ,
    pipe_tx0_elec_idle_gt,
    pipe_tx1_elec_idle_gt,
    pipe_tx_rcvr_det_gt,
    D,
    pipe_tx_deemph_gt,
    pipe_rx0_valid,
    pipe_rx0_chanisaligned,
    pipe_rx0_phy_status,
    pipe_rx0_elec_idle,
    Q,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ,
    \pipe_stages_1.pipe_tx_data_q_reg[15] ,
    \pipe_stages_1.pipe_tx_data_q_reg[15]_0 ,
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1] ,
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ,
    \pipe_stages_1.pipe_tx_margin_q_reg[2] ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0 ,
    SR,
    pipe_rx1_valid_gt,
    \pipe_stages_1.pipe_tx_deemph_q_reg ,
    pipe_rx1_chanisaligned_gt,
    \pipe_stages_1.pipe_rx_phy_status_q_reg ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg ,
    pipe_rx0_polarity,
    pipe_rx1_polarity,
    pipe_tx0_compliance,
    pipe_tx1_compliance,
    pipe_tx0_elec_idle,
    pipe_tx1_elec_idle,
    pipe_tx_rcvr_det,
    pipe_tx_rate,
    pipe_tx_deemph,
    pipe_rx0_valid_gt,
    pipe_rx0_chanisaligned_gt,
    gt_rx_phy_status_q,
    gt_rxelecidle_q,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_1 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_1 ,
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ,
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2 ,
    \pipe_stages_1.pipe_tx_data_q_reg[15]_1 ,
    \pipe_stages_1.pipe_tx_data_q_reg[15]_2 ,
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ,
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2 ,
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_2 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_2 );
  output pipe_rx1_valid;
  output pipe_rx1_chanisaligned;
  output pipe_rx1_phy_status;
  output pipe_rx1_elec_idle;
  output pipe_rx0_polarity_gt;
  output pipe_rx1_polarity_gt;
  output [0:0]TXCHARDISPMODE;
  output [0:0]\pipe_stages_1.pipe_tx_compliance_q_reg ;
  output pipe_tx0_elec_idle_gt;
  output pipe_tx1_elec_idle_gt;
  output pipe_tx_rcvr_det_gt;
  output [0:0]D;
  output pipe_tx_deemph_gt;
  output pipe_rx0_valid;
  output pipe_rx0_chanisaligned;
  output pipe_rx0_phy_status;
  output pipe_rx0_elec_idle;
  output [1:0]Q;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  output [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] ;
  output [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ;
  output [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15] ;
  output [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ;
  output [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1] ;
  output [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ;
  output [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  input [0:0]SR;
  input pipe_rx1_valid_gt;
  input \pipe_stages_1.pipe_tx_deemph_q_reg ;
  input pipe_rx1_chanisaligned_gt;
  input \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  input \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  input pipe_rx0_polarity;
  input pipe_rx1_polarity;
  input pipe_tx0_compliance;
  input pipe_tx1_compliance;
  input pipe_tx0_elec_idle;
  input pipe_tx1_elec_idle;
  input pipe_tx_rcvr_det;
  input pipe_tx_rate;
  input pipe_tx_deemph;
  input pipe_rx0_valid_gt;
  input pipe_rx0_chanisaligned_gt;
  input gt_rx_phy_status_q;
  input gt_rxelecidle_q;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ;
  input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ;
  input [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2 ;
  input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_1 ;
  input [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_2 ;
  input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ;
  input [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2 ;
  input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ;

  wire [0:0]D;
  wire [1:0]Q;
  wire [0:0]SR;
  wire [0:0]TXCHARDISPMODE;
  wire gt_rx_phy_status_q;
  wire gt_rxelecidle_q;
  wire pipe_rx0_chanisaligned;
  wire pipe_rx0_chanisaligned_gt;
  wire pipe_rx0_elec_idle;
  wire pipe_rx0_phy_status;
  wire pipe_rx0_polarity;
  wire pipe_rx0_polarity_gt;
  wire pipe_rx0_valid;
  wire pipe_rx0_valid_gt;
  wire pipe_rx1_chanisaligned;
  wire pipe_rx1_chanisaligned_gt;
  wire pipe_rx1_elec_idle;
  wire pipe_rx1_phy_status;
  wire pipe_rx1_polarity;
  wire pipe_rx1_polarity_gt;
  wire pipe_rx1_valid;
  wire pipe_rx1_valid_gt;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ;
  wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] ;
  wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ;
  wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ;
  wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2 ;
  wire [0:0]\pipe_stages_1.pipe_tx_compliance_q_reg ;
  wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15] ;
  wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ;
  wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_1 ;
  wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_2 ;
  wire \pipe_stages_1.pipe_tx_deemph_q_reg ;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ;
  wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1] ;
  wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ;
  wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ;
  wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2 ;
  wire pipe_tx0_compliance;
  wire pipe_tx0_elec_idle;
  wire pipe_tx0_elec_idle_gt;
  wire pipe_tx1_compliance;
  wire pipe_tx1_elec_idle;
  wire pipe_tx1_elec_idle_gt;
  wire pipe_tx_deemph;
  wire pipe_tx_deemph_gt;
  wire pipe_tx_rate;
  wire pipe_tx_rcvr_det;
  wire pipe_tx_rcvr_det_gt;

  xdma_0_pcie2_ip_pcie_pipe_lane \pipe_2_lane.pipe_lane_1_i 
       (.Q(Q),
        .SR(SR),
        .pipe_rx1_chanisaligned(pipe_rx1_chanisaligned),
        .pipe_rx1_chanisaligned_gt(pipe_rx1_chanisaligned_gt),
        .pipe_rx1_elec_idle(pipe_rx1_elec_idle),
        .pipe_rx1_phy_status(pipe_rx1_phy_status),
        .pipe_rx1_polarity(pipe_rx1_polarity),
        .pipe_rx1_polarity_gt(pipe_rx1_polarity_gt),
        .pipe_rx1_valid(pipe_rx1_valid),
        .pipe_rx1_valid_gt(pipe_rx1_valid_gt),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (\pipe_stages_1.pipe_rx_data_q_reg[15] ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 (\pipe_stages_1.pipe_rx_elec_idle_q_reg ),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg_0 (\pipe_stages_1.pipe_rx_phy_status_q_reg ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 (\pipe_stages_1.pipe_rx_status_q_reg[2] ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 (\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ),
        .\pipe_stages_1.pipe_rx_valid_q_reg_0 (\pipe_stages_1.pipe_tx_deemph_q_reg ),
        .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 ),
        .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 (\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2 ),
        .\pipe_stages_1.pipe_tx_compliance_q_reg_0 (\pipe_stages_1.pipe_tx_compliance_q_reg ),
        .\pipe_stages_1.pipe_tx_data_q_reg[15]_0 (\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ),
        .\pipe_stages_1.pipe_tx_data_q_reg[15]_1 (\pipe_stages_1.pipe_tx_data_q_reg[15]_2 ),
        .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 (\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ),
        .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 (\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2 ),
        .pipe_tx1_compliance(pipe_tx1_compliance),
        .pipe_tx1_elec_idle(pipe_tx1_elec_idle),
        .pipe_tx1_elec_idle_gt(pipe_tx1_elec_idle_gt));
  xdma_0_pcie2_ip_pcie_pipe_lane_14 pipe_lane_0_i
       (.SR(SR),
        .TXCHARDISPMODE(TXCHARDISPMODE),
        .gt_rx_phy_status_q(gt_rx_phy_status_q),
        .gt_rxelecidle_q(gt_rxelecidle_q),
        .pipe_rx0_chanisaligned(pipe_rx0_chanisaligned),
        .pipe_rx0_chanisaligned_gt(pipe_rx0_chanisaligned_gt),
        .pipe_rx0_elec_idle(pipe_rx0_elec_idle),
        .pipe_rx0_phy_status(pipe_rx0_phy_status),
        .pipe_rx0_polarity(pipe_rx0_polarity),
        .pipe_rx0_polarity_gt(pipe_rx0_polarity_gt),
        .pipe_rx0_valid(pipe_rx0_valid),
        .pipe_rx0_valid_gt(pipe_rx0_valid_gt),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 (\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 (\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ),
        .\pipe_stages_1.pipe_rx_valid_q_reg_0 (\pipe_stages_1.pipe_tx_deemph_q_reg ),
        .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] ),
        .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 (\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 ),
        .\pipe_stages_1.pipe_tx_data_q_reg[15]_0 (\pipe_stages_1.pipe_tx_data_q_reg[15] ),
        .\pipe_stages_1.pipe_tx_data_q_reg[15]_1 (\pipe_stages_1.pipe_tx_data_q_reg[15]_1 ),
        .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 (\pipe_stages_1.pipe_tx_powerdown_q_reg[1] ),
        .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 (\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 ),
        .pipe_tx0_compliance(pipe_tx0_compliance),
        .pipe_tx0_elec_idle(pipe_tx0_elec_idle),
        .pipe_tx0_elec_idle_gt(pipe_tx0_elec_idle_gt));
  xdma_0_pcie2_ip_pcie_pipe_misc pipe_misc_i
       (.D(D),
        .SR(SR),
        .\pipe_stages_1.pipe_tx_deemph_q_reg_0 (\pipe_stages_1.pipe_tx_deemph_q_reg ),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 (\pipe_stages_1.pipe_tx_margin_q_reg[2] ),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2]_1 (\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 ),
        .pipe_tx_deemph(pipe_tx_deemph),
        .pipe_tx_deemph_gt(pipe_tx_deemph_gt),
        .pipe_tx_rate(pipe_tx_rate),
        .pipe_tx_rcvr_det(pipe_tx_rcvr_det),
        .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt));
endmodule

module xdma_0_pcie2_ip_pcie_top
   (m_axis_rx_tvalid_reg,
    m_axis_rx_tkeep,
    m_axis_rx_tlast,
    tready_thrtl_reg,
    pipe_rx0_polarity_gt,
    pipe_rx1_polarity_gt,
    TXCHARDISPMODE,
    \pipe_stages_1.pipe_tx_compliance_q_reg ,
    pipe_tx0_elec_idle_gt,
    pipe_tx1_elec_idle_gt,
    pipe_tx_rcvr_det_gt,
    D,
    pipe_tx_deemph_gt,
    user_reset_int_reg,
    src_in,
    cfg_mgmt_rd_wr_done,
    cfg_interrupt_rdy,
    m_axis_rx_tdata,
    m_axis_rx_tuser,
    cfg_to_turnoff,
    cfg_bus_number,
    cfg_device_number,
    cfg_function_number,
    Q,
    \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_tx_data_q_reg[15] ,
    \pipe_stages_1.pipe_tx_data_q_reg[15]_0 ,
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1] ,
    \pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ,
    \pipe_stages_1.pipe_tx_margin_q_reg[2] ,
    cfg_command,
    cfg_interrupt_msienable,
    pl_received_hot_rst,
    trn_lnk_up,
    cfg_dcommand,
    cfg_interrupt_mmenable,
    cfg_mgmt_do,
    pl_ltssm_state,
    fc_nph,
    \throttle_ctl_pipeline.reg_tkeep_reg[7] ,
    CLK,
    tx_cfg_gnt,
    cfg_turnoff_ok,
    s_axis_tx_tlast,
    s_axis_tx_tvalid,
    s_axis_tx_tkeep,
    SR,
    pipe_rx1_valid_gt,
    \pipe_stages_1.pipe_tx_deemph_q_reg ,
    pipe_rx1_chanisaligned_gt,
    \pipe_stages_1.pipe_rx_phy_status_q_reg ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg ,
    pipe_rx0_valid_gt,
    pipe_rx0_chanisaligned_gt,
    gt_rx_phy_status_q,
    gt_rxelecidle_q,
    bridge_reset_int,
    pl_phy_lnk_up,
    m_axis_rx_tready,
    cfg_mgmt_wr_readonly,
    cfg_mgmt_wr_en,
    cfg_mgmt_rd_en,
    cfg_interrupt,
    cfg_interrupt_assert,
    out,
    s_axis_tx_tdata,
    s_axis_tx_tuser,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0 ,
    pl_directed_link_auton,
    pl_directed_link_speed,
    pl_upstream_prefer_deemph,
    sys_rst_n,
    rx_np_ok,
    rx_np_req,
    cfg_err_aer_headerlog,
    cfg_pm_force_state,
    pl_directed_link_change,
    pl_directed_link_width,
    fc_sel,
    cfg_mgmt_di,
    cfg_mgmt_byte_en_n,
    cfg_err_tlp_cpl_header,
    cfg_aer_interrupt_msgnum,
    cfg_pciecap_interrupt_msgnum,
    cfg_dsn,
    cfg_interrupt_di,
    cfg_mgmt_dwaddr);
  output m_axis_rx_tvalid_reg;
  output [0:0]m_axis_rx_tkeep;
  output m_axis_rx_tlast;
  output tready_thrtl_reg;
  output pipe_rx0_polarity_gt;
  output pipe_rx1_polarity_gt;
  output [0:0]TXCHARDISPMODE;
  output [0:0]\pipe_stages_1.pipe_tx_compliance_q_reg ;
  output pipe_tx0_elec_idle_gt;
  output pipe_tx1_elec_idle_gt;
  output pipe_tx_rcvr_det_gt;
  output [0:0]D;
  output pipe_tx_deemph_gt;
  output user_reset_int_reg;
  output src_in;
  output cfg_mgmt_rd_wr_done;
  output cfg_interrupt_rdy;
  output [63:0]m_axis_rx_tdata;
  output [12:0]m_axis_rx_tuser;
  output cfg_to_turnoff;
  output [7:0]cfg_bus_number;
  output [4:0]cfg_device_number;
  output [2:0]cfg_function_number;
  output [1:0]Q;
  output [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] ;
  output [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15] ;
  output [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ;
  output [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1] ;
  output [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ;
  output [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  output [0:0]cfg_command;
  output cfg_interrupt_msienable;
  output pl_received_hot_rst;
  output trn_lnk_up;
  output [5:0]cfg_dcommand;
  output [2:0]cfg_interrupt_mmenable;
  output [31:0]cfg_mgmt_do;
  output [5:0]pl_ltssm_state;
  output [7:0]fc_nph;
  input \throttle_ctl_pipeline.reg_tkeep_reg[7] ;
  input CLK;
  input tx_cfg_gnt;
  input cfg_turnoff_ok;
  input s_axis_tx_tlast;
  input s_axis_tx_tvalid;
  input [0:0]s_axis_tx_tkeep;
  input [0:0]SR;
  input pipe_rx1_valid_gt;
  input \pipe_stages_1.pipe_tx_deemph_q_reg ;
  input pipe_rx1_chanisaligned_gt;
  input \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  input \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  input pipe_rx0_valid_gt;
  input pipe_rx0_chanisaligned_gt;
  input gt_rx_phy_status_q;
  input gt_rxelecidle_q;
  input bridge_reset_int;
  input pl_phy_lnk_up;
  input m_axis_rx_tready;
  input cfg_mgmt_wr_readonly;
  input cfg_mgmt_wr_en;
  input cfg_mgmt_rd_en;
  input cfg_interrupt;
  input cfg_interrupt_assert;
  input out;
  input [63:0]s_axis_tx_tdata;
  input [3:0]s_axis_tx_tuser;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  input pl_directed_link_auton;
  input pl_directed_link_speed;
  input pl_upstream_prefer_deemph;
  input sys_rst_n;
  input rx_np_ok;
  input rx_np_req;
  input [127:0]cfg_err_aer_headerlog;
  input [1:0]cfg_pm_force_state;
  input [1:0]pl_directed_link_change;
  input [1:0]pl_directed_link_width;
  input [2:0]fc_sel;
  input [31:0]cfg_mgmt_di;
  input [3:0]cfg_mgmt_byte_en_n;
  input [47:0]cfg_err_tlp_cpl_header;
  input [4:0]cfg_aer_interrupt_msgnum;
  input [4:0]cfg_pciecap_interrupt_msgnum;
  input [63:0]cfg_dsn;
  input [7:0]cfg_interrupt_di;
  input [9:0]cfg_mgmt_dwaddr;

  wire CLK;
  wire [0:0]D;
  wire [1:0]Q;
  wire [0:0]SR;
  wire [0:0]TXCHARDISPMODE;
  wire bridge_reset_int;
  wire [4:0]cfg_aer_interrupt_msgnum;
  wire [7:0]cfg_bus_number;
  wire [0:0]cfg_command;
  wire [5:0]cfg_dcommand;
  wire [4:0]cfg_device_number;
  wire [63:0]cfg_dsn;
  wire [127:0]cfg_err_aer_headerlog;
  wire [47:0]cfg_err_tlp_cpl_header;
  wire [2:0]cfg_function_number;
  wire cfg_interrupt;
  wire cfg_interrupt_assert;
  wire [7:0]cfg_interrupt_di;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire cfg_interrupt_rdy;
  wire [3:0]cfg_mgmt_byte_en_n;
  wire [31:0]cfg_mgmt_di;
  wire [31:0]cfg_mgmt_do;
  wire [9:0]cfg_mgmt_dwaddr;
  wire cfg_mgmt_rd_en;
  wire cfg_mgmt_rd_wr_done;
  wire cfg_mgmt_wr_en;
  wire cfg_mgmt_wr_readonly;
  wire [4:0]cfg_pciecap_interrupt_msgnum;
  wire [1:0]cfg_pm_force_state;
  wire cfg_to_turnoff;
  wire cfg_turnoff_ok;
  wire cfg_turnoff_ok_w;
  wire [7:0]fc_nph;
  wire [2:0]fc_sel;
  wire gt_rx_phy_status_q;
  wire gt_rxelecidle_q;
  wire [63:0]m_axis_rx_tdata;
  wire [0:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [12:0]m_axis_rx_tuser;
  wire m_axis_rx_tvalid_reg;
  wire out;
  wire pcie_7x_i_n_10;
  wire pcie_7x_i_n_108;
  wire pcie_7x_i_n_109;
  wire pcie_7x_i_n_11;
  wire pcie_7x_i_n_110;
  wire pcie_7x_i_n_111;
  wire pcie_7x_i_n_112;
  wire pcie_7x_i_n_113;
  wire pcie_7x_i_n_114;
  wire pcie_7x_i_n_115;
  wire pcie_7x_i_n_116;
  wire pcie_7x_i_n_117;
  wire pcie_7x_i_n_118;
  wire pcie_7x_i_n_119;
  wire pcie_7x_i_n_12;
  wire pcie_7x_i_n_120;
  wire pcie_7x_i_n_121;
  wire pcie_7x_i_n_122;
  wire pcie_7x_i_n_123;
  wire pcie_7x_i_n_17;
  wire pcie_7x_i_n_18;
  wire pcie_7x_i_n_19;
  wire pcie_7x_i_n_20;
  wire pcie_7x_i_n_21;
  wire pcie_7x_i_n_22;
  wire pcie_7x_i_n_23;
  wire pcie_7x_i_n_24;
  wire pcie_7x_i_n_26;
  wire pcie_7x_i_n_4;
  wire pcie_7x_i_n_5;
  wire pcie_7x_i_n_9;
  wire pipe_rx0_chanisaligned;
  wire pipe_rx0_chanisaligned_gt;
  wire [1:0]pipe_rx0_char_is_k;
  wire [15:0]pipe_rx0_data;
  wire pipe_rx0_elec_idle;
  wire pipe_rx0_phy_status;
  wire pipe_rx0_polarity;
  wire pipe_rx0_polarity_gt;
  wire [2:0]pipe_rx0_status;
  wire pipe_rx0_valid;
  wire pipe_rx0_valid_gt;
  wire pipe_rx1_chanisaligned;
  wire pipe_rx1_chanisaligned_gt;
  wire [1:0]pipe_rx1_char_is_k;
  wire [15:0]pipe_rx1_data;
  wire pipe_rx1_elec_idle;
  wire pipe_rx1_phy_status;
  wire pipe_rx1_polarity;
  wire pipe_rx1_polarity_gt;
  wire [2:0]pipe_rx1_status;
  wire pipe_rx1_valid;
  wire pipe_rx1_valid_gt;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  wire [1:0]\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] ;
  wire [0:0]\pipe_stages_1.pipe_tx_compliance_q_reg ;
  wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15] ;
  wire [15:0]\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ;
  wire \pipe_stages_1.pipe_tx_deemph_q_reg ;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1] ;
  wire [1:0]\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ;
  wire [1:0]pipe_tx0_char_is_k;
  wire pipe_tx0_compliance;
  wire [15:0]pipe_tx0_data;
  wire pipe_tx0_elec_idle;
  wire pipe_tx0_elec_idle_gt;
  wire [1:0]pipe_tx0_powerdown;
  wire [1:0]pipe_tx1_char_is_k;
  wire pipe_tx1_compliance;
  wire [15:0]pipe_tx1_data;
  wire pipe_tx1_elec_idle;
  wire pipe_tx1_elec_idle_gt;
  wire [1:0]pipe_tx1_powerdown;
  wire pipe_tx_deemph;
  wire pipe_tx_deemph_gt;
  wire [2:0]pipe_tx_margin;
  wire pipe_tx_rate;
  wire pipe_tx_rcvr_det;
  wire pipe_tx_rcvr_det_gt;
  wire pl_directed_link_auton;
  wire [1:0]pl_directed_link_change;
  wire pl_directed_link_speed;
  wire [1:0]pl_directed_link_width;
  wire [5:0]pl_ltssm_state;
  wire pl_phy_lnk_up;
  wire pl_received_hot_rst;
  wire pl_upstream_prefer_deemph;
  wire \rx_inst/rx_pipeline_inst/dsc_detect ;
  wire \rx_inst/rx_pipeline_inst/reg_dsc_detect ;
  wire \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered ;
  wire \rx_inst/rx_pipeline_inst/trn_in_packet ;
  wire \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d ;
  wire \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0 ;
  wire rx_np_ok;
  wire rx_np_req;
  wire [63:0]s_axis_tx_tdata;
  wire [0:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire src_in;
  wire sys_rst_n;
  wire \throttle_ctl_pipeline.reg_tkeep_reg[7] ;
  wire tready_thrtl_reg;
  wire trn_lnk_up;
  wire [6:0]trn_rbar_hit;
  wire [63:0]trn_rd;
  wire trn_rdst_rdy;
  wire trn_recrc_err;
  wire trn_reof;
  wire trn_rerrfwd;
  wire [0:0]trn_rrem;
  wire trn_rsof;
  wire trn_rsrc_dsc;
  wire trn_tcfg_gnt;
  wire [63:0]trn_td;
  wire trn_tdst_rdy;
  wire trn_tecrc_gen;
  wire trn_teof;
  wire trn_terrfwd;
  wire trn_trem;
  wire trn_tsof;
  wire trn_tsrc_dsc;
  wire trn_tsrc_rdy;
  wire trn_tstr;
  wire tx_cfg_gnt;
  wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl ;
  wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl ;
  wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig ;
  wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt ;
  wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig ;
  wire \tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig ;
  wire \tx_inst/tx_pipeline_inst/reg_disable_trn2 ;
  wire user_reset_int_reg;

  xdma_0_pcie2_ip_axi_basic_top axi_basic_top
       (.CLK(CLK),
        .E(trn_rdst_rdy),
        .Q(m_axis_rx_tdata),
        .cfg_pcie_link_state({pcie_7x_i_n_10,pcie_7x_i_n_11,pcie_7x_i_n_12}),
        .cfg_pm_turnoff_ok_n(cfg_turnoff_ok_w),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .dsc_detect(\rx_inst/rx_pipeline_inst/dsc_detect ),
        .lnk_up_thrtl(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl ),
        .lnk_up_thrtl_reg(pcie_7x_i_n_26),
        .m_axis_rx_tkeep(m_axis_rx_tkeep),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser),
        .m_axis_rx_tvalid_reg(m_axis_rx_tvalid_reg),
        .out(out),
        .ppm_L1_thrtl(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl ),
        .ppm_L1_thrtl_reg(pcie_7x_i_n_9),
        .ppm_L1_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig ),
        .reg_dsc_detect(\rx_inst/rx_pipeline_inst/reg_dsc_detect ),
        .reg_tcfg_gnt(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt ),
        .rsrc_rdy_filtered(\rx_inst/rx_pipeline_inst/rsrc_rdy_filtered ),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep(s_axis_tx_tkeep),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .tbuf_av_min_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig ),
        .tcfg_req_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig ),
        .\throttle_ctl_pipeline.reg_tdata_reg[63] ({trn_td[31:0],trn_td[63:32]}),
        .\throttle_ctl_pipeline.reg_tkeep_reg[7] (\throttle_ctl_pipeline.reg_tkeep_reg[7] ),
        .\throttle_ctl_pipeline.reg_tuser_reg[3] ({trn_tsrc_dsc,trn_tstr,trn_terrfwd,trn_tecrc_gen}),
        .tready_thrtl_i_5(pcie_7x_i_n_18),
        .tready_thrtl_reg(tready_thrtl_reg),
        .trn_in_packet(\rx_inst/rx_pipeline_inst/trn_in_packet ),
        .trn_in_packet_reg(pcie_7x_i_n_5),
        .trn_rbar_hit(trn_rbar_hit),
        .trn_rd(trn_rd),
        .trn_recrc_err(trn_recrc_err),
        .trn_reof(trn_reof),
        .trn_rerrfwd(trn_rerrfwd),
        .trn_rrem(trn_rrem),
        .trn_rsof(trn_rsof),
        .trn_rsrc_dsc(trn_rsrc_dsc),
        .trn_rsrc_dsc_d(\rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d ),
        .trn_rsrc_dsc_prev0(\rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0 ),
        .trn_tbuf_av({pcie_7x_i_n_19,pcie_7x_i_n_20,pcie_7x_i_n_21,pcie_7x_i_n_22,pcie_7x_i_n_23,pcie_7x_i_n_24}),
        .trn_tcfg_gnt(trn_tcfg_gnt),
        .trn_tcfg_req(pcie_7x_i_n_17),
        .trn_tdst_rdy(trn_tdst_rdy),
        .trn_teof(trn_teof),
        .trn_trem(trn_trem),
        .trn_tsof(trn_tsof),
        .trn_tsrc_rdy(trn_tsrc_rdy),
        .tx_cfg_gnt(tx_cfg_gnt));
  LUT1 #(
    .INIT(2'h1)) 
    \cfg_bus_number_d[7]_i_1 
       (.I0(out),
        .O(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_bus_number_d_reg[0] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_115),
        .Q(cfg_bus_number[0]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_bus_number_d_reg[1] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_114),
        .Q(cfg_bus_number[1]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_bus_number_d_reg[2] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_113),
        .Q(cfg_bus_number[2]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_bus_number_d_reg[3] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_112),
        .Q(cfg_bus_number[3]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_bus_number_d_reg[4] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_111),
        .Q(cfg_bus_number[4]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_bus_number_d_reg[5] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_110),
        .Q(cfg_bus_number[5]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_bus_number_d_reg[6] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_109),
        .Q(cfg_bus_number[6]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_bus_number_d_reg[7] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_108),
        .Q(cfg_bus_number[7]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_device_number_d_reg[0] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_120),
        .Q(cfg_device_number[0]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_device_number_d_reg[1] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_119),
        .Q(cfg_device_number[1]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_device_number_d_reg[2] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_118),
        .Q(cfg_device_number[2]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_device_number_d_reg[3] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_117),
        .Q(cfg_device_number[3]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_device_number_d_reg[4] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_116),
        .Q(cfg_device_number[4]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_function_number_d_reg[0] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_123),
        .Q(cfg_function_number[0]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_function_number_d_reg[1] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_122),
        .Q(cfg_function_number[1]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  FDRE \cfg_function_number_d_reg[2] 
       (.C(CLK),
        .CE(pcie_7x_i_n_4),
        .D(pcie_7x_i_n_121),
        .Q(cfg_function_number[2]),
        .R(\tx_inst/tx_pipeline_inst/reg_disable_trn2 ));
  xdma_0_pcie2_ip_pcie_7x pcie_7x_i
       (.CLK(CLK),
        .E(pcie_7x_i_n_4),
        .Q(pipe_rx0_data),
        .bridge_reset_int(bridge_reset_int),
        .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
        .cfg_command(cfg_command),
        .cfg_dcommand(cfg_dcommand),
        .cfg_dsn(cfg_dsn),
        .cfg_err_aer_headerlog(cfg_err_aer_headerlog),
        .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
        .cfg_interrupt(cfg_interrupt),
        .cfg_interrupt_assert(cfg_interrupt_assert),
        .cfg_interrupt_di(cfg_interrupt_di),
        .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
        .cfg_interrupt_msienable(cfg_interrupt_msienable),
        .cfg_interrupt_rdy(cfg_interrupt_rdy),
        .cfg_mgmt_byte_en_n(cfg_mgmt_byte_en_n),
        .cfg_mgmt_di(cfg_mgmt_di),
        .cfg_mgmt_do(cfg_mgmt_do),
        .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
        .cfg_mgmt_rd_en(cfg_mgmt_rd_en),
        .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
        .cfg_mgmt_wr_en(cfg_mgmt_wr_en),
        .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
        .cfg_msg_data({pcie_7x_i_n_108,pcie_7x_i_n_109,pcie_7x_i_n_110,pcie_7x_i_n_111,pcie_7x_i_n_112,pcie_7x_i_n_113,pcie_7x_i_n_114,pcie_7x_i_n_115,pcie_7x_i_n_116,pcie_7x_i_n_117,pcie_7x_i_n_118,pcie_7x_i_n_119,pcie_7x_i_n_120,pcie_7x_i_n_121,pcie_7x_i_n_122,pcie_7x_i_n_123}),
        .cfg_pcie_link_state({pcie_7x_i_n_10,pcie_7x_i_n_11,pcie_7x_i_n_12}),
        .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
        .cfg_pm_force_state(cfg_pm_force_state),
        .cfg_pm_turnoff_ok_n(cfg_turnoff_ok_w),
        .cfg_to_turnoff(cfg_to_turnoff),
        .dsc_detect(\rx_inst/rx_pipeline_inst/dsc_detect ),
        .fc_nph(fc_nph),
        .fc_sel(fc_sel),
        .lnk_up_thrtl(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/lnk_up_thrtl ),
        .out(out),
        .pcie_block_i_0(pcie_7x_i_n_9),
        .pcie_block_i_1(pcie_7x_i_n_18),
        .pcie_block_i_10(pipe_rx0_status),
        .pcie_block_i_11(pipe_rx1_status),
        .pcie_block_i_2(pcie_7x_i_n_26),
        .pcie_block_i_3(trn_rd),
        .pcie_block_i_4(trn_rrem),
        .pcie_block_i_5(\pipe_stages_1.pipe_tx_deemph_q_reg ),
        .pcie_block_i_6({trn_tsrc_dsc,trn_tstr,trn_terrfwd,trn_tecrc_gen}),
        .pcie_block_i_7(pipe_rx1_data),
        .pcie_block_i_8(pipe_rx0_char_is_k),
        .pcie_block_i_9(pipe_rx1_char_is_k),
        .pipe_rx0_chanisaligned(pipe_rx0_chanisaligned),
        .pipe_rx0_elec_idle(pipe_rx0_elec_idle),
        .pipe_rx0_phy_status(pipe_rx0_phy_status),
        .pipe_rx0_polarity(pipe_rx0_polarity),
        .pipe_rx0_valid(pipe_rx0_valid),
        .pipe_rx1_chanisaligned(pipe_rx1_chanisaligned),
        .pipe_rx1_elec_idle(pipe_rx1_elec_idle),
        .pipe_rx1_phy_status(pipe_rx1_phy_status),
        .pipe_rx1_polarity(pipe_rx1_polarity),
        .pipe_rx1_valid(pipe_rx1_valid),
        .pipe_tx0_char_is_k(pipe_tx0_char_is_k),
        .pipe_tx0_compliance(pipe_tx0_compliance),
        .pipe_tx0_data(pipe_tx0_data),
        .pipe_tx0_elec_idle(pipe_tx0_elec_idle),
        .pipe_tx0_powerdown(pipe_tx0_powerdown),
        .pipe_tx1_char_is_k(pipe_tx1_char_is_k),
        .pipe_tx1_compliance(pipe_tx1_compliance),
        .pipe_tx1_data(pipe_tx1_data),
        .pipe_tx1_elec_idle(pipe_tx1_elec_idle),
        .pipe_tx1_powerdown(pipe_tx1_powerdown),
        .pipe_tx_deemph(pipe_tx_deemph),
        .pipe_tx_margin(pipe_tx_margin),
        .pipe_tx_rate(pipe_tx_rate),
        .pipe_tx_rcvr_det(pipe_tx_rcvr_det),
        .pl_directed_link_auton(pl_directed_link_auton),
        .pl_directed_link_change(pl_directed_link_change),
        .pl_directed_link_speed(pl_directed_link_speed),
        .pl_directed_link_width(pl_directed_link_width),
        .pl_ltssm_state(pl_ltssm_state),
        .pl_phy_lnk_up(pl_phy_lnk_up),
        .pl_received_hot_rst(pl_received_hot_rst),
        .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
        .ppm_L1_thrtl(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_thrtl ),
        .ppm_L1_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/ppm_L1_trig ),
        .reg_dsc_detect(\rx_inst/rx_pipeline_inst/reg_dsc_detect ),
        .reg_tcfg_gnt(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/reg_tcfg_gnt ),
        .rsrc_rdy_filtered(\rx_inst/rx_pipeline_inst/rsrc_rdy_filtered ),
        .rx_np_ok(rx_np_ok),
        .rx_np_req(rx_np_req),
        .src_in(src_in),
        .sys_rst_n(sys_rst_n),
        .tbuf_av_min_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tbuf_av_min_trig ),
        .tcfg_req_trig(\tx_inst/thrtl_ctl_enabled.tx_thrl_ctl_inst/tcfg_req_trig ),
        .trn_in_packet(\rx_inst/rx_pipeline_inst/trn_in_packet ),
        .trn_in_packet_reg(pcie_7x_i_n_5),
        .trn_lnk_up(trn_lnk_up),
        .trn_rbar_hit(trn_rbar_hit),
        .trn_rdst_rdy(trn_rdst_rdy),
        .trn_recrc_err(trn_recrc_err),
        .trn_reof(trn_reof),
        .trn_rerrfwd(trn_rerrfwd),
        .trn_rsof(trn_rsof),
        .trn_rsrc_dsc(trn_rsrc_dsc),
        .trn_rsrc_dsc_d(\rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d ),
        .trn_rsrc_dsc_prev0(\rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0 ),
        .trn_tbuf_av({pcie_7x_i_n_19,pcie_7x_i_n_20,pcie_7x_i_n_21,pcie_7x_i_n_22,pcie_7x_i_n_23,pcie_7x_i_n_24}),
        .trn_tcfg_gnt(trn_tcfg_gnt),
        .trn_tcfg_req(pcie_7x_i_n_17),
        .trn_td(trn_td),
        .trn_tdst_rdy(trn_tdst_rdy),
        .trn_teof(trn_teof),
        .trn_trem(trn_trem),
        .trn_tsof(trn_tsof),
        .trn_tsrc_rdy(trn_tsrc_rdy),
        .user_reset_int_reg(user_reset_int_reg));
  xdma_0_pcie2_ip_pcie_pipe_pipeline pcie_pipe_pipeline_i
       (.D(D),
        .Q(pipe_rx1_char_is_k),
        .SR(SR),
        .TXCHARDISPMODE(TXCHARDISPMODE),
        .gt_rx_phy_status_q(gt_rx_phy_status_q),
        .gt_rxelecidle_q(gt_rxelecidle_q),
        .pipe_rx0_chanisaligned(pipe_rx0_chanisaligned),
        .pipe_rx0_chanisaligned_gt(pipe_rx0_chanisaligned_gt),
        .pipe_rx0_elec_idle(pipe_rx0_elec_idle),
        .pipe_rx0_phy_status(pipe_rx0_phy_status),
        .pipe_rx0_polarity(pipe_rx0_polarity),
        .pipe_rx0_polarity_gt(pipe_rx0_polarity_gt),
        .pipe_rx0_valid(pipe_rx0_valid),
        .pipe_rx0_valid_gt(pipe_rx0_valid_gt),
        .pipe_rx1_chanisaligned(pipe_rx1_chanisaligned),
        .pipe_rx1_chanisaligned_gt(pipe_rx1_chanisaligned_gt),
        .pipe_rx1_elec_idle(pipe_rx1_elec_idle),
        .pipe_rx1_phy_status(pipe_rx1_phy_status),
        .pipe_rx1_polarity(pipe_rx1_polarity),
        .pipe_rx1_polarity_gt(pipe_rx1_polarity_gt),
        .pipe_rx1_valid(pipe_rx1_valid),
        .pipe_rx1_valid_gt(pipe_rx1_valid_gt),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (pipe_rx0_char_is_k),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (pipe_rx1_data),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (pipe_rx0_data),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (\pipe_stages_1.pipe_rx_data_q_reg[15] ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_2 (\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg (\pipe_stages_1.pipe_rx_elec_idle_q_reg ),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg (\pipe_stages_1.pipe_rx_phy_status_q_reg ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] (pipe_rx1_status),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 (pipe_rx0_status),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 (\pipe_stages_1.pipe_rx_status_q_reg[2] ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_2 (\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ),
        .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] (Q),
        .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_0 (\pipe_stages_1.pipe_tx_char_is_k_q_reg[1] ),
        .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_1 (pipe_tx0_char_is_k),
        .\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]_2 (pipe_tx1_char_is_k),
        .\pipe_stages_1.pipe_tx_compliance_q_reg (\pipe_stages_1.pipe_tx_compliance_q_reg ),
        .\pipe_stages_1.pipe_tx_data_q_reg[15] (\pipe_stages_1.pipe_tx_data_q_reg[15] ),
        .\pipe_stages_1.pipe_tx_data_q_reg[15]_0 (\pipe_stages_1.pipe_tx_data_q_reg[15]_0 ),
        .\pipe_stages_1.pipe_tx_data_q_reg[15]_1 (pipe_tx0_data),
        .\pipe_stages_1.pipe_tx_data_q_reg[15]_2 (pipe_tx1_data),
        .\pipe_stages_1.pipe_tx_deemph_q_reg (\pipe_stages_1.pipe_tx_deemph_q_reg ),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2] (\pipe_stages_1.pipe_tx_margin_q_reg[2] ),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2]_0 (pipe_tx_margin),
        .\pipe_stages_1.pipe_tx_powerdown_q_reg[1] (\pipe_stages_1.pipe_tx_powerdown_q_reg[1] ),
        .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 (\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_0 ),
        .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_1 (pipe_tx0_powerdown),
        .\pipe_stages_1.pipe_tx_powerdown_q_reg[1]_2 (pipe_tx1_powerdown),
        .pipe_tx0_compliance(pipe_tx0_compliance),
        .pipe_tx0_elec_idle(pipe_tx0_elec_idle),
        .pipe_tx0_elec_idle_gt(pipe_tx0_elec_idle_gt),
        .pipe_tx1_compliance(pipe_tx1_compliance),
        .pipe_tx1_elec_idle(pipe_tx1_elec_idle),
        .pipe_tx1_elec_idle_gt(pipe_tx1_elec_idle_gt),
        .pipe_tx_deemph(pipe_tx_deemph),
        .pipe_tx_deemph_gt(pipe_tx_deemph_gt),
        .pipe_tx_rate(pipe_tx_rate),
        .pipe_tx_rcvr_det(pipe_tx_rcvr_det),
        .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt));
endmodule

module xdma_0_pcie2_ip_pipe_clock
   (\pclk_i1_bufgctrl.pclk_i1_0 ,
    CLK,
    \userclk1_i1.usrclk1_i1_0 ,
    SYNC_MMCM_LOCK,
    mmcm_i_0,
    \txoutclk_i.txoutclk_i_0 ,
    \pclk_sel_reg1_reg[1]_0 ,
    \pclk_sel_reg1_reg[0]_0 ,
    int_pclk_sel_slave);
  output \pclk_i1_bufgctrl.pclk_i1_0 ;
  output CLK;
  output \userclk1_i1.usrclk1_i1_0 ;
  output SYNC_MMCM_LOCK;
  output mmcm_i_0;
  input \txoutclk_i.txoutclk_i_0 ;
  input \pclk_sel_reg1_reg[1]_0 ;
  input \pclk_sel_reg1_reg[0]_0 ;
  input [1:0]int_pclk_sel_slave;

  wire CLK;
  wire S00;
  wire SYNC_MMCM_LOCK;
  wire clk_125mhz;
  wire clk_250mhz;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2;
  wire [1:0]int_pclk_sel_slave;
  wire mmcm_fb;
  wire mmcm_i_0;
  wire \pclk_i1_bufgctrl.pclk_i1_0 ;
  wire pclk_sel;
  wire pclk_sel_i_1__1_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]pclk_sel_reg1;
  wire \pclk_sel_reg1_reg[0]_0 ;
  wire \pclk_sel_reg1_reg[1]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]pclk_sel_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]pclk_sel_slave_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]pclk_sel_slave_reg2;
  wire refclk;
  wire \txoutclk_i.txoutclk_i_0 ;
  wire userclk1;
  wire \userclk1_i1.usrclk1_i1_0 ;
  wire NLW_mmcm_i_CLKFBOUTB_UNCONNECTED;
  wire NLW_mmcm_i_CLKFBSTOPPED_UNCONNECTED;
  wire NLW_mmcm_i_CLKINSTOPPED_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT0B_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT1B_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT2B_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT3_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT3B_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT4_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT5_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT6_UNCONNECTED;
  wire NLW_mmcm_i_DRDY_UNCONNECTED;
  wire NLW_mmcm_i_PSDONE_UNCONNECTED;
  wire [15:0]NLW_mmcm_i_DO_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  BUFG \dclk_i_bufg.dclk_i 
       (.I(clk_125mhz),
        .O(CLK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg1_reg
       (.C(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .CE(1'b1),
        .D(1'b0),
        .Q(gen3_reg1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg2_reg
       (.C(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(1'b0));
  (* box_type = "PRIMITIVE" *) 
  MMCME2_ADV #(
    .BANDWIDTH("OPTIMIZED"),
    .CLKFBOUT_MULT_F(10.000000),
    .CLKFBOUT_PHASE(0.000000),
    .CLKFBOUT_USE_FINE_PS("FALSE"),
    .CLKIN1_PERIOD(10.000000),
    .CLKIN2_PERIOD(0.000000),
    .CLKOUT0_DIVIDE_F(8.000000),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT0_USE_FINE_PS("FALSE"),
    .CLKOUT1_DIVIDE(4),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUT1_USE_FINE_PS("FALSE"),
    .CLKOUT2_DIVIDE(8),
    .CLKOUT2_DUTY_CYCLE(0.500000),
    .CLKOUT2_PHASE(0.000000),
    .CLKOUT2_USE_FINE_PS("FALSE"),
    .CLKOUT3_DIVIDE(8),
    .CLKOUT3_DUTY_CYCLE(0.500000),
    .CLKOUT3_PHASE(0.000000),
    .CLKOUT3_USE_FINE_PS("FALSE"),
    .CLKOUT4_CASCADE("FALSE"),
    .CLKOUT4_DIVIDE(20),
    .CLKOUT4_DUTY_CYCLE(0.500000),
    .CLKOUT4_PHASE(0.000000),
    .CLKOUT4_USE_FINE_PS("FALSE"),
    .CLKOUT5_DIVIDE(1),
    .CLKOUT5_DUTY_CYCLE(0.500000),
    .CLKOUT5_PHASE(0.000000),
    .CLKOUT5_USE_FINE_PS("FALSE"),
    .CLKOUT6_DIVIDE(1),
    .CLKOUT6_DUTY_CYCLE(0.500000),
    .CLKOUT6_PHASE(0.000000),
    .CLKOUT6_USE_FINE_PS("FALSE"),
    .COMPENSATION("INTERNAL"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKINSEL_INVERTED(1'b0),
    .IS_PSEN_INVERTED(1'b0),
    .IS_PSINCDEC_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER1(0.010000),
    .REF_JITTER2(0.010000),
    .SS_EN("FALSE"),
    .SS_MODE("CENTER_HIGH"),
    .SS_MOD_PERIOD(10000),
    .STARTUP_WAIT("FALSE")) 
    mmcm_i
       (.CLKFBIN(mmcm_fb),
        .CLKFBOUT(mmcm_fb),
        .CLKFBOUTB(NLW_mmcm_i_CLKFBOUTB_UNCONNECTED),
        .CLKFBSTOPPED(NLW_mmcm_i_CLKFBSTOPPED_UNCONNECTED),
        .CLKIN1(refclk),
        .CLKIN2(1'b0),
        .CLKINSEL(1'b1),
        .CLKINSTOPPED(NLW_mmcm_i_CLKINSTOPPED_UNCONNECTED),
        .CLKOUT0(clk_125mhz),
        .CLKOUT0B(NLW_mmcm_i_CLKOUT0B_UNCONNECTED),
        .CLKOUT1(clk_250mhz),
        .CLKOUT1B(NLW_mmcm_i_CLKOUT1B_UNCONNECTED),
        .CLKOUT2(userclk1),
        .CLKOUT2B(NLW_mmcm_i_CLKOUT2B_UNCONNECTED),
        .CLKOUT3(NLW_mmcm_i_CLKOUT3_UNCONNECTED),
        .CLKOUT3B(NLW_mmcm_i_CLKOUT3B_UNCONNECTED),
        .CLKOUT4(NLW_mmcm_i_CLKOUT4_UNCONNECTED),
        .CLKOUT5(NLW_mmcm_i_CLKOUT5_UNCONNECTED),
        .CLKOUT6(NLW_mmcm_i_CLKOUT6_UNCONNECTED),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(NLW_mmcm_i_DO_UNCONNECTED[15:0]),
        .DRDY(NLW_mmcm_i_DRDY_UNCONNECTED),
        .DWE(1'b0),
        .LOCKED(SYNC_MMCM_LOCK),
        .PSCLK(1'b0),
        .PSDONE(NLW_mmcm_i_PSDONE_UNCONNECTED),
        .PSEN(1'b0),
        .PSINCDEC(1'b0),
        .PWRDWN(1'b0),
        .RST(1'b0));
  (* box_type = "PRIMITIVE" *) 
  BUFGCTRL #(
    .CE_TYPE_CE0("SYNC"),
    .CE_TYPE_CE1("SYNC"),
    .INIT_OUT(0),
    .IS_CE0_INVERTED(1'b0),
    .IS_CE1_INVERTED(1'b0),
    .IS_I0_INVERTED(1'b0),
    .IS_I1_INVERTED(1'b0),
    .IS_IGNORE0_INVERTED(1'b0),
    .IS_IGNORE1_INVERTED(1'b0),
    .IS_S0_INVERTED(1'b0),
    .IS_S1_INVERTED(1'b0),
    .PRESELECT_I0("FALSE"),
    .PRESELECT_I1("FALSE"),
    .SIM_DEVICE("7SERIES"),
    .STARTUP_SYNC("FALSE")) 
    \pclk_i1_bufgctrl.pclk_i1 
       (.CE0(1'b1),
        .CE1(1'b1),
        .I0(clk_125mhz),
        .I1(clk_250mhz),
        .IGNORE0(1'b0),
        .IGNORE1(1'b0),
        .O(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .S0(S00),
        .S1(pclk_sel));
  LUT1 #(
    .INIT(2'h1)) 
    \pclk_i1_bufgctrl.pclk_i1_i_1 
       (.I0(pclk_sel),
        .O(S00));
  LUT3 #(
    .INIT(8'hE8)) 
    pclk_sel_i_1__1
       (.I0(pclk_sel_reg2[1]),
        .I1(pclk_sel_reg2[0]),
        .I2(pclk_sel),
        .O(pclk_sel_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .CE(1'b1),
        .D(pclk_sel_i_1__1_n_0),
        .Q(pclk_sel),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg1_reg[0] 
       (.C(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .CE(1'b1),
        .D(\pclk_sel_reg1_reg[0]_0 ),
        .Q(pclk_sel_reg1[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg1_reg[1] 
       (.C(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .CE(1'b1),
        .D(\pclk_sel_reg1_reg[1]_0 ),
        .Q(pclk_sel_reg1[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg2_reg[0] 
       (.C(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .CE(1'b1),
        .D(pclk_sel_reg1[0]),
        .Q(pclk_sel_reg2[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg2_reg[1] 
       (.C(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .CE(1'b1),
        .D(pclk_sel_reg1[1]),
        .Q(pclk_sel_reg2[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg1_reg[0] 
       (.C(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .CE(1'b1),
        .D(int_pclk_sel_slave[0]),
        .Q(pclk_sel_slave_reg1[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg1_reg[1] 
       (.C(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .CE(1'b1),
        .D(int_pclk_sel_slave[1]),
        .Q(pclk_sel_slave_reg1[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg2_reg[0] 
       (.C(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .CE(1'b1),
        .D(pclk_sel_slave_reg1[0]),
        .Q(pclk_sel_slave_reg2[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg2_reg[1] 
       (.C(\pclk_i1_bufgctrl.pclk_i1_0 ),
        .CE(1'b1),
        .D(pclk_sel_slave_reg1[1]),
        .Q(pclk_sel_slave_reg2[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    reg_clock_locked_i_1
       (.I0(SYNC_MMCM_LOCK),
        .O(mmcm_i_0));
  (* box_type = "PRIMITIVE" *) 
  BUFG \txoutclk_i.txoutclk_i 
       (.I(\txoutclk_i.txoutclk_i_0 ),
        .O(refclk));
  (* box_type = "PRIMITIVE" *) 
  BUFG \userclk1_i1.usrclk1_i1 
       (.I(userclk1),
        .O(\userclk1_i1.usrclk1_i1_0 ));
endmodule

module xdma_0_pcie2_ip_pipe_eq
   (eq_rxeq_adapt_done_0,
    TXPRECURSOR,
    TXMAINCURSOR,
    TXPOSTCURSOR,
    rst_cpllreset,
    \fs_reg2_reg[5] );
  output eq_rxeq_adapt_done_0;
  output [4:0]TXPRECURSOR;
  output [6:0]TXMAINCURSOR;
  output [4:0]TXPOSTCURSOR;
  input rst_cpllreset;
  input \fs_reg2_reg[5] ;

  wire \FSM_onehot_fsm_rx[1]_i_1_n_0 ;
  wire \FSM_onehot_fsm_rx[1]_i_2_n_0 ;
  wire \FSM_onehot_fsm_rx[3]_i_1_n_0 ;
  wire \FSM_onehot_fsm_rx[4]_i_1_n_0 ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[1] ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[2] ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[3] ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[4] ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[5] ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[6] ;
  wire \FSM_sequential_fsm_tx[1]_i_2_n_0 ;
  wire \FSM_sequential_fsm_tx[2]_i_2_n_0 ;
  wire \FSM_sequential_fsm_tx[2]_i_3_n_0 ;
  wire \FSM_sequential_fsm_tx[2]_i_4_n_0 ;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire eq_rxeq_adapt_done_0;
  wire \fs_reg2_reg[5] ;
  wire [2:0]fsm_tx;
  wire [2:0]fsm_tx__0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2;
  wire [11:0]in10;
  wire [17:0]p_0_out;
  wire rst_cpllreset;
  wire rxeq_adapt_done_i_2_n_0;
  wire rxeq_adapt_done_reg_i_2_n_0;
  wire rxeq_adapt_done_reg_reg_n_0;
  wire [2:0]rxeq_cnt;
  wire \rxeq_cnt_reg_n_0_[0] ;
  wire \rxeq_cnt_reg_n_0_[1] ;
  wire \rxeq_cnt_reg_n_0_[2] ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg2;
  wire [5:0]rxeq_fs;
  wire \rxeq_fs[5]_i_1_n_0 ;
  wire \rxeq_fs_reg_n_0_[0] ;
  wire \rxeq_fs_reg_n_0_[1] ;
  wire \rxeq_fs_reg_n_0_[2] ;
  wire \rxeq_fs_reg_n_0_[3] ;
  wire \rxeq_fs_reg_n_0_[4] ;
  wire \rxeq_fs_reg_n_0_[5] ;
  wire [5:0]rxeq_lf;
  wire \rxeq_lf[5]_i_1_n_0 ;
  wire \rxeq_lf_reg_n_0_[0] ;
  wire \rxeq_lf_reg_n_0_[1] ;
  wire \rxeq_lf_reg_n_0_[2] ;
  wire \rxeq_lf_reg_n_0_[3] ;
  wire \rxeq_lf_reg_n_0_[4] ;
  wire \rxeq_lf_reg_n_0_[5] ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg2;
  wire rxeq_new_txcoeff_req;
  wire rxeq_new_txcoeff_req_reg_n_0;
  wire \rxeq_preset[0]_i_1_n_0 ;
  wire \rxeq_preset[1]_i_1_n_0 ;
  wire \rxeq_preset[2]_i_1_n_0 ;
  wire \rxeq_preset[2]_i_2_n_0 ;
  wire \rxeq_preset[2]_i_3_n_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg2;
  wire \rxeq_preset_reg_n_0_[0] ;
  wire \rxeq_preset_reg_n_0_[1] ;
  wire \rxeq_preset_reg_n_0_[2] ;
  wire rxeq_preset_valid;
  wire rxeq_scan_i_n_0;
  wire rxeq_scan_i_n_1;
  wire rxeq_scan_i_n_2;
  wire rxeq_scan_i_n_3;
  wire rxeq_scan_i_n_4;
  wire [17:0]rxeq_txcoeff;
  wire \rxeq_txcoeff_reg_n_0_[0] ;
  wire \rxeq_txcoeff_reg_n_0_[1] ;
  wire \rxeq_txcoeff_reg_n_0_[2] ;
  wire \rxeq_txcoeff_reg_n_0_[3] ;
  wire \rxeq_txcoeff_reg_n_0_[4] ;
  wire \rxeq_txcoeff_reg_n_0_[5] ;
  wire [3:0]rxeq_txpreset;
  wire \rxeq_txpreset[3]_i_1_n_0 ;
  wire \rxeq_txpreset[3]_i_3_n_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg2;
  wire \rxeq_txpreset_reg_n_0_[0] ;
  wire \rxeq_txpreset_reg_n_0_[1] ;
  wire \rxeq_txpreset_reg_n_0_[2] ;
  wire \rxeq_txpreset_reg_n_0_[3] ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg2;
  wire \txeq_preset[17]_i_1_n_0 ;
  wire \txeq_preset[3]_i_1_n_0 ;
  wire \txeq_preset[7]_i_1_n_0 ;
  wire \txeq_preset[7]_i_2_n_0 ;
  wire txeq_preset_done;
  wire txeq_preset_done_i_1_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg2;
  wire \txeq_preset_reg_n_0_[0] ;
  wire \txeq_preset_reg_n_0_[10] ;
  wire \txeq_preset_reg_n_0_[11] ;
  wire \txeq_preset_reg_n_0_[12] ;
  wire \txeq_preset_reg_n_0_[13] ;
  wire \txeq_preset_reg_n_0_[14] ;
  wire \txeq_preset_reg_n_0_[15] ;
  wire \txeq_preset_reg_n_0_[16] ;
  wire \txeq_preset_reg_n_0_[17] ;
  wire \txeq_preset_reg_n_0_[1] ;
  wire \txeq_preset_reg_n_0_[2] ;
  wire \txeq_preset_reg_n_0_[3] ;
  wire \txeq_preset_reg_n_0_[7] ;
  wire \txeq_preset_reg_n_0_[8] ;
  wire \txeq_preset_reg_n_0_[9] ;
  wire txeq_txcoeff;
  wire \txeq_txcoeff[0]_i_1_n_0 ;
  wire \txeq_txcoeff[0]_i_2_n_0 ;
  wire \txeq_txcoeff[10]_i_1_n_0 ;
  wire \txeq_txcoeff[10]_i_2_n_0 ;
  wire \txeq_txcoeff[11]_i_1_n_0 ;
  wire \txeq_txcoeff[11]_i_2_n_0 ;
  wire \txeq_txcoeff[12]_i_1_n_0 ;
  wire \txeq_txcoeff[12]_i_2_n_0 ;
  wire \txeq_txcoeff[13]_i_1_n_0 ;
  wire \txeq_txcoeff[13]_i_2_n_0 ;
  wire \txeq_txcoeff[14]_i_1_n_0 ;
  wire \txeq_txcoeff[14]_i_2_n_0 ;
  wire \txeq_txcoeff[15]_i_1_n_0 ;
  wire \txeq_txcoeff[15]_i_2_n_0 ;
  wire \txeq_txcoeff[16]_i_1_n_0 ;
  wire \txeq_txcoeff[16]_i_2_n_0 ;
  wire \txeq_txcoeff[17]_i_1_n_0 ;
  wire \txeq_txcoeff[17]_i_2_n_0 ;
  wire \txeq_txcoeff[18]_i_2_n_0 ;
  wire \txeq_txcoeff[18]_i_3_n_0 ;
  wire \txeq_txcoeff[1]_i_1_n_0 ;
  wire \txeq_txcoeff[1]_i_2_n_0 ;
  wire \txeq_txcoeff[2]_i_1_n_0 ;
  wire \txeq_txcoeff[2]_i_2_n_0 ;
  wire \txeq_txcoeff[3]_i_1_n_0 ;
  wire \txeq_txcoeff[3]_i_2_n_0 ;
  wire \txeq_txcoeff[4]_i_1_n_0 ;
  wire \txeq_txcoeff[4]_i_2_n_0 ;
  wire \txeq_txcoeff[5]_i_1_n_0 ;
  wire \txeq_txcoeff[5]_i_2_n_0 ;
  wire \txeq_txcoeff[6]_i_1_n_0 ;
  wire \txeq_txcoeff[6]_i_2_n_0 ;
  wire \txeq_txcoeff[7]_i_1_n_0 ;
  wire \txeq_txcoeff[7]_i_2_n_0 ;
  wire \txeq_txcoeff[8]_i_1_n_0 ;
  wire \txeq_txcoeff[8]_i_2_n_0 ;
  wire \txeq_txcoeff[9]_i_1_n_0 ;
  wire \txeq_txcoeff[9]_i_2_n_0 ;
  wire [1:0]txeq_txcoeff_cnt;
  wire \txeq_txcoeff_cnt_reg_n_0_[0] ;
  wire \txeq_txcoeff_cnt_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[0] ;
  wire \txeq_txcoeff_reg_n_0_[10] ;
  wire \txeq_txcoeff_reg_n_0_[11] ;
  wire \txeq_txcoeff_reg_n_0_[12] ;
  wire \txeq_txcoeff_reg_n_0_[13] ;
  wire \txeq_txcoeff_reg_n_0_[14] ;
  wire \txeq_txcoeff_reg_n_0_[15] ;
  wire \txeq_txcoeff_reg_n_0_[16] ;
  wire \txeq_txcoeff_reg_n_0_[17] ;
  wire \txeq_txcoeff_reg_n_0_[18] ;
  wire \txeq_txcoeff_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[2] ;
  wire \txeq_txcoeff_reg_n_0_[3] ;
  wire \txeq_txcoeff_reg_n_0_[4] ;
  wire \txeq_txcoeff_reg_n_0_[5] ;
  wire \txeq_txcoeff_reg_n_0_[6] ;
  wire \txeq_txcoeff_reg_n_0_[7] ;
  wire \txeq_txcoeff_reg_n_0_[8] ;
  wire \txeq_txcoeff_reg_n_0_[9] ;

  LUT5 #(
    .INIT(32'hABABABAA)) 
    \FSM_onehot_fsm_rx[1]_i_1 
       (.I0(\FSM_onehot_fsm_rx[1]_i_2_n_0 ),
        .I1(rxeq_control_reg2[0]),
        .I2(rxeq_control_reg2[1]),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm_rx[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \FSM_onehot_fsm_rx[1]_i_2 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm_rx_reg_n_0_[5] ),
        .O(\FSM_onehot_fsm_rx[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF8FF88888888)) 
    \FSM_onehot_fsm_rx[3]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .I3(\rxeq_cnt_reg_n_0_[1] ),
        .I4(\rxeq_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_rx[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1784" *) 
  LUT5 #(
    .INIT(32'h2ABA2AAA)) 
    \FSM_onehot_fsm_rx[4]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\rxeq_cnt_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_rx[4]_i_1_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_rx[1]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_scan_i_n_4),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_rx[3]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[4] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_rx[4]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[5] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_scan_i_n_3),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[5] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[6] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_scan_i_n_2),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'hC04FC043C04FF04F)) 
    \FSM_sequential_fsm_tx[0]_i_1 
       (.I0(\FSM_sequential_fsm_tx[1]_i_2_n_0 ),
        .I1(fsm_tx[0]),
        .I2(fsm_tx[1]),
        .I3(fsm_tx[2]),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(fsm_tx__0[0]));
  LUT6 #(
    .INIT(64'h3F703F7C3F7C0F70)) 
    \FSM_sequential_fsm_tx[1]_i_1 
       (.I0(\FSM_sequential_fsm_tx[1]_i_2_n_0 ),
        .I1(fsm_tx[0]),
        .I2(fsm_tx[1]),
        .I3(fsm_tx[2]),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(fsm_tx__0[1]));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_fsm_tx[1]_i_2 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fsm_tx[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hA8A8A8A8A8AAA8A8)) 
    \FSM_sequential_fsm_tx[2]_i_1 
       (.I0(\FSM_sequential_fsm_tx[2]_i_2_n_0 ),
        .I1(\FSM_sequential_fsm_tx[2]_i_3_n_0 ),
        .I2(fsm_tx[2]),
        .I3(\FSM_sequential_fsm_tx[2]_i_4_n_0 ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(fsm_tx__0[2]));
  LUT5 #(
    .INIT(32'h7777FFF7)) 
    \FSM_sequential_fsm_tx[2]_i_2 
       (.I0(fsm_tx[1]),
        .I1(fsm_tx[2]),
        .I2(txeq_control_reg2[1]),
        .I3(txeq_control_reg2[0]),
        .I4(fsm_tx[0]),
        .O(\FSM_sequential_fsm_tx[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0F800080)) 
    \FSM_sequential_fsm_tx[2]_i_3 
       (.I0(txeq_control_reg2[1]),
        .I1(txeq_control_reg2[0]),
        .I2(fsm_tx[0]),
        .I3(fsm_tx[1]),
        .I4(txeq_preset_done),
        .O(\FSM_sequential_fsm_tx[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1782" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \FSM_sequential_fsm_tx[2]_i_4 
       (.I0(fsm_tx[0]),
        .I1(fsm_tx[1]),
        .O(\FSM_sequential_fsm_tx[2]_i_4_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_tx_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(fsm_tx__0[0]),
        .Q(fsm_tx[0]),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_tx_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(fsm_tx__0[1]),
        .Q(fsm_tx[1]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_tx_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(fsm_tx__0[2]),
        .Q(fsm_tx[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE gen3_reg1_reg
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(gen3_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE gen3_reg2_reg
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(rst_cpllreset));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_20 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .O(TXPOSTCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_21 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[16] ),
        .O(TXPOSTCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_22 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .O(TXPOSTCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_23 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .O(TXPOSTCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_24 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[13] ),
        .O(TXPOSTCURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_25 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[4] ),
        .O(TXPRECURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_26 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[3] ),
        .O(TXPRECURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_27 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[2] ),
        .O(TXPRECURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_28 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[1] ),
        .O(TXPRECURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_29 
       (.I0(\txeq_txcoeff_reg_n_0_[0] ),
        .I1(gen3_reg2),
        .O(TXPRECURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_30 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .O(TXMAINCURSOR[6]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_31 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .O(TXMAINCURSOR[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_32 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .O(TXMAINCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_33 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[9] ),
        .O(TXMAINCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_34 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[8] ),
        .O(TXMAINCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_35 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[7] ),
        .O(TXMAINCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_36 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[6] ),
        .O(TXMAINCURSOR[0]));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFFFFFF)) 
    rxeq_adapt_done_i_2
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[5] ),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I5(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .O(rxeq_adapt_done_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_scan_i_n_1),
        .Q(eq_rxeq_adapt_done_0),
        .R(rst_cpllreset));
  LUT3 #(
    .INIT(8'h08)) 
    rxeq_adapt_done_reg_i_2
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_control_reg2[0]),
        .I2(rxeq_control_reg2[1]),
        .O(rxeq_adapt_done_reg_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg_reg
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_scan_i_n_0),
        .Q(rxeq_adapt_done_reg_reg_n_0),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h8888FFF8)) 
    \rxeq_cnt[0]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I4(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[0]));
  (* SOFT_HLUTNM = "soft_lutpair1785" *) 
  LUT4 #(
    .INIT(16'h6660)) 
    \rxeq_cnt[1]_i_1 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(rxeq_cnt[1]));
  (* SOFT_HLUTNM = "soft_lutpair1784" *) 
  LUT5 #(
    .INIT(32'h78787800)) 
    \rxeq_cnt[2]_i_1 
       (.I0(\rxeq_cnt_reg_n_0_[0] ),
        .I1(\rxeq_cnt_reg_n_0_[1] ),
        .I2(\rxeq_cnt_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(rxeq_cnt[2]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_cnt[0]),
        .Q(\rxeq_cnt_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_cnt[1]),
        .Q(\rxeq_cnt_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_cnt[2]),
        .Q(\rxeq_cnt_reg_n_0_[2] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_control_reg1_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_control_reg1_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_control_reg2_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_control_reg1[0]),
        .Q(rxeq_control_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_control_reg2_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_control_reg1[1]),
        .Q(rxeq_control_reg2[1]),
        .R(rst_cpllreset));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[0]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[0]),
        .O(rxeq_fs[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[1]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[1]),
        .O(rxeq_fs[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[2]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[2]),
        .O(rxeq_fs[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[3]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[3]),
        .O(rxeq_fs[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[4]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[4]),
        .O(rxeq_fs[4]));
  LUT3 #(
    .INIT(8'hF8)) 
    \rxeq_fs[5]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_rx[1]_i_2_n_0 ),
        .O(\rxeq_fs[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[5]_i_2 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[5]),
        .O(rxeq_fs[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[0]),
        .Q(\rxeq_fs_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[1]),
        .Q(\rxeq_fs_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[2]),
        .Q(\rxeq_fs_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[3]),
        .Q(\rxeq_fs_reg_n_0_[3] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[4] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[4]),
        .Q(\rxeq_fs_reg_n_0_[4] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[5] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[5]),
        .Q(\rxeq_fs_reg_n_0_[5] ),
        .R(rst_cpllreset));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[0]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[0]),
        .O(rxeq_lf[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[1]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[1]),
        .O(rxeq_lf[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[2]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[2]),
        .O(rxeq_lf[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[3]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[3]),
        .O(rxeq_lf[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[4]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[4]),
        .O(rxeq_lf[4]));
  LUT5 #(
    .INIT(32'hEAAAAAAA)) 
    \rxeq_lf[5]_i_1 
       (.I0(\FSM_onehot_fsm_rx[1]_i_2_n_0 ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[0] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .O(\rxeq_lf[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[5]_i_2 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[5]),
        .O(rxeq_lf[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[0]),
        .Q(\rxeq_lf_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[1]),
        .Q(\rxeq_lf_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[2]),
        .Q(\rxeq_lf_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[3]),
        .Q(\rxeq_lf_reg_n_0_[3] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[4] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[4]),
        .Q(\rxeq_lf_reg_n_0_[4] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[5] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[5]),
        .Q(\rxeq_lf_reg_n_0_[5] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[4] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[5] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[0]),
        .Q(rxeq_lffs_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[1]),
        .Q(rxeq_lffs_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[2]),
        .Q(rxeq_lffs_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[3]),
        .Q(rxeq_lffs_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[4] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[4]),
        .Q(rxeq_lffs_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[5] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[5]),
        .Q(rxeq_lffs_reg2[5]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_new_txcoeff_req_reg
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_new_txcoeff_req),
        .Q(rxeq_new_txcoeff_req_reg_n_0),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'hA8FFA800)) 
    \rxeq_preset[0]_i_1 
       (.I0(rxeq_preset_reg2[0]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I3(\rxeq_preset[2]_i_2_n_0 ),
        .I4(\rxeq_preset_reg_n_0_[0] ),
        .O(\rxeq_preset[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hA8FFA800)) 
    \rxeq_preset[1]_i_1 
       (.I0(rxeq_preset_reg2[1]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I3(\rxeq_preset[2]_i_2_n_0 ),
        .I4(\rxeq_preset_reg_n_0_[1] ),
        .O(\rxeq_preset[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hA8FFA800)) 
    \rxeq_preset[2]_i_1 
       (.I0(rxeq_preset_reg2[2]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I3(\rxeq_preset[2]_i_2_n_0 ),
        .I4(\rxeq_preset_reg_n_0_[2] ),
        .O(\rxeq_preset[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0002)) 
    \rxeq_preset[2]_i_2 
       (.I0(\rxeq_preset[2]_i_3_n_0 ),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[5] ),
        .I4(rxeq_adapt_done_reg_i_2_n_0),
        .I5(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .O(\rxeq_preset[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1785" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \rxeq_preset[2]_i_3 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(\rxeq_preset[2]_i_3_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg1_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg1_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg1_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg2_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_preset_reg1[0]),
        .Q(rxeq_preset_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg2_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_preset_reg1[1]),
        .Q(rxeq_preset_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg2_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_preset_reg1[2]),
        .Q(rxeq_preset_reg2[2]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(\rxeq_preset[0]_i_1_n_0 ),
        .Q(\rxeq_preset_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(\rxeq_preset[1]_i_1_n_0 ),
        .Q(\rxeq_preset_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(\rxeq_preset[2]_i_1_n_0 ),
        .Q(\rxeq_preset_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_preset_valid_reg
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .Q(rxeq_preset_valid),
        .R(rst_cpllreset));
  xdma_0_pcie2_ip_rxeq_scan_37 rxeq_scan_i
       (.D({rxeq_scan_i_n_2,rxeq_scan_i_n_3,rxeq_scan_i_n_4}),
        .\FSM_onehot_fsm_rx_reg[5] ({\rxeq_cnt_reg_n_0_[2] ,\rxeq_cnt_reg_n_0_[1] ,\rxeq_cnt_reg_n_0_[0] }),
        .Q({\FSM_onehot_fsm_rx_reg_n_0_[6] ,\FSM_onehot_fsm_rx_reg_n_0_[5] ,\FSM_onehot_fsm_rx_reg_n_0_[4] ,\FSM_onehot_fsm_rx_reg_n_0_[2] ,\FSM_onehot_fsm_rx_reg_n_0_[1] }),
        .adapt_done_reg_0(rxeq_scan_i_n_0),
        .eq_rxeq_adapt_done_0(eq_rxeq_adapt_done_0),
        .\fs_reg1_reg[5]_0 ({\rxeq_fs_reg_n_0_[5] ,\rxeq_fs_reg_n_0_[4] ,\rxeq_fs_reg_n_0_[3] ,\rxeq_fs_reg_n_0_[2] ,\rxeq_fs_reg_n_0_[1] ,\rxeq_fs_reg_n_0_[0] }),
        .\fs_reg2_reg[5]_0 (\fs_reg2_reg[5] ),
        .\lf_reg1_reg[5]_0 ({\rxeq_lf_reg_n_0_[5] ,\rxeq_lf_reg_n_0_[4] ,\rxeq_lf_reg_n_0_[3] ,\rxeq_lf_reg_n_0_[2] ,\rxeq_lf_reg_n_0_[1] ,\rxeq_lf_reg_n_0_[0] }),
        .new_txcoeff_done_reg_0(rxeq_scan_i_n_1),
        .new_txcoeff_req_reg1_reg_0(rxeq_new_txcoeff_req_reg_n_0),
        .out(rxeq_control_reg2),
        .\preset_reg1_reg[2]_0 ({\rxeq_preset_reg_n_0_[2] ,\rxeq_preset_reg_n_0_[1] ,\rxeq_preset_reg_n_0_[0] }),
        .rst_cpllreset(rst_cpllreset),
        .rxeq_adapt_done_reg(rxeq_adapt_done_i_2_n_0),
        .rxeq_adapt_done_reg_reg(\FSM_onehot_fsm_rx[1]_i_2_n_0 ),
        .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_i_2_n_0),
        .rxeq_adapt_done_reg_reg_1(rxeq_adapt_done_reg_reg_n_0),
        .rxeq_new_txcoeff_req(rxeq_new_txcoeff_req),
        .rxeq_preset_valid(rxeq_preset_valid),
        .\txcoeff_reg1_reg[17]_0 ({in10,\rxeq_txcoeff_reg_n_0_[5] ,\rxeq_txcoeff_reg_n_0_[4] ,\rxeq_txcoeff_reg_n_0_[3] ,\rxeq_txcoeff_reg_n_0_[2] ,\rxeq_txcoeff_reg_n_0_[1] ,\rxeq_txcoeff_reg_n_0_[0] }),
        .\txpreset_reg1_reg[3]_0 ({\rxeq_txpreset_reg_n_0_[3] ,\rxeq_txpreset_reg_n_0_[2] ,\rxeq_txpreset_reg_n_0_[1] ,\rxeq_txpreset_reg_n_0_[0] }));
  (* SOFT_HLUTNM = "soft_lutpair1786" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[0]_i_1 
       (.I0(in10[0]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[0]));
  (* SOFT_HLUTNM = "soft_lutpair1791" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[10]_i_1 
       (.I0(in10[10]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[10]));
  (* SOFT_HLUTNM = "soft_lutpair1791" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[11]_i_1 
       (.I0(in10[11]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[11]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[12]_i_1 
       (.I0(txeq_deemph_reg2[0]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[12]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[13]_i_1 
       (.I0(txeq_deemph_reg2[1]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[13]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[14]_i_1 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[14]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[15]_i_1 
       (.I0(txeq_deemph_reg2[3]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[15]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[16]_i_1 
       (.I0(txeq_deemph_reg2[4]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[16]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[17]_i_1 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[17]));
  (* SOFT_HLUTNM = "soft_lutpair1786" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[1]_i_1 
       (.I0(in10[1]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[1]));
  (* SOFT_HLUTNM = "soft_lutpair1787" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[2]_i_1 
       (.I0(in10[2]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[2]));
  (* SOFT_HLUTNM = "soft_lutpair1787" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[3]_i_1 
       (.I0(in10[3]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[3]));
  (* SOFT_HLUTNM = "soft_lutpair1788" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[4]_i_1 
       (.I0(in10[4]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[4]));
  (* SOFT_HLUTNM = "soft_lutpair1788" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[5]_i_1 
       (.I0(in10[5]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[5]));
  (* SOFT_HLUTNM = "soft_lutpair1789" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[6]_i_1 
       (.I0(in10[6]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[6]));
  (* SOFT_HLUTNM = "soft_lutpair1789" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[7]_i_1 
       (.I0(in10[7]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[7]));
  (* SOFT_HLUTNM = "soft_lutpair1790" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[8]_i_1 
       (.I0(in10[8]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[8]));
  (* SOFT_HLUTNM = "soft_lutpair1790" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[9]_i_1 
       (.I0(in10[9]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[0]),
        .Q(\rxeq_txcoeff_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[10] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[10]),
        .Q(in10[4]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[11] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[11]),
        .Q(in10[5]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[12] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[12]),
        .Q(in10[6]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[13] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[13]),
        .Q(in10[7]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[14] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[14]),
        .Q(in10[8]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[15] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[15]),
        .Q(in10[9]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[16] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[16]),
        .Q(in10[10]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[17] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[17]),
        .Q(in10[11]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[1]),
        .Q(\rxeq_txcoeff_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[2]),
        .Q(\rxeq_txcoeff_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[3]),
        .Q(\rxeq_txcoeff_reg_n_0_[3] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[4] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[4]),
        .Q(\rxeq_txcoeff_reg_n_0_[4] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[5] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[5]),
        .Q(\rxeq_txcoeff_reg_n_0_[5] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[6] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[6]),
        .Q(in10[0]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[7] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[7]),
        .Q(in10[1]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[8] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[8]),
        .Q(in10[2]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[9] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[9]),
        .Q(in10[3]),
        .R(rst_cpllreset));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txpreset[0]_i_1 
       (.I0(rxeq_txpreset_reg2[0]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txpreset[0]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txpreset[1]_i_1 
       (.I0(rxeq_txpreset_reg2[1]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txpreset[1]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txpreset[2]_i_1 
       (.I0(rxeq_txpreset_reg2[2]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txpreset[2]));
  LUT5 #(
    .INIT(32'hFFFFF044)) 
    \rxeq_txpreset[3]_i_1 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .I1(\rxeq_txpreset[3]_i_3_n_0 ),
        .I2(rxeq_control_reg2[1]),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(\rxeq_txpreset[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txpreset[3]_i_2 
       (.I0(rxeq_txpreset_reg2[3]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txpreset[3]));
  LUT3 #(
    .INIT(8'h01)) 
    \rxeq_txpreset[3]_i_3 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[5] ),
        .O(\rxeq_txpreset[3]_i_3_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg1_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg1_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg1_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg1_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg2_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[0]),
        .Q(rxeq_txpreset_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg2_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[1]),
        .Q(rxeq_txpreset_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg2_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[2]),
        .Q(rxeq_txpreset_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg2_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[3]),
        .Q(rxeq_txpreset_reg2[3]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txpreset[0]),
        .Q(\rxeq_txpreset_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txpreset[1]),
        .Q(\rxeq_txpreset_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txpreset[2]),
        .Q(\rxeq_txpreset_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txpreset[3]),
        .Q(\rxeq_txpreset_reg_n_0_[3] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_user_en_reg1_reg
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_en_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_user_en_reg2_reg
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_en_reg1),
        .Q(rxeq_user_en_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_user_mode_reg1_reg
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_mode_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_user_mode_reg2_reg
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_mode_reg1),
        .Q(rxeq_user_mode_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[10] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[10]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[11] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[11]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[12] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[12]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[13] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[13]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[14] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[14]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[15] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[15]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[16] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[16]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[17] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[17]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[4] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[5] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[6] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[6]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[7] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[7]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[8] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[8]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[9] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[9]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[0]),
        .Q(rxeq_user_txcoeff_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[10] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[10]),
        .Q(rxeq_user_txcoeff_reg2[10]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[11] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[11]),
        .Q(rxeq_user_txcoeff_reg2[11]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[12] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[12]),
        .Q(rxeq_user_txcoeff_reg2[12]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[13] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[13]),
        .Q(rxeq_user_txcoeff_reg2[13]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[14] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[14]),
        .Q(rxeq_user_txcoeff_reg2[14]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[15] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[15]),
        .Q(rxeq_user_txcoeff_reg2[15]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[16] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[16]),
        .Q(rxeq_user_txcoeff_reg2[16]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[17] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[17]),
        .Q(rxeq_user_txcoeff_reg2[17]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[1]),
        .Q(rxeq_user_txcoeff_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[2]),
        .Q(rxeq_user_txcoeff_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[3]),
        .Q(rxeq_user_txcoeff_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[4] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[4]),
        .Q(rxeq_user_txcoeff_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[5] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[5]),
        .Q(rxeq_user_txcoeff_reg2[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[6] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[6]),
        .Q(rxeq_user_txcoeff_reg2[6]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[7] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[7]),
        .Q(rxeq_user_txcoeff_reg2[7]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[8] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[8]),
        .Q(rxeq_user_txcoeff_reg2[8]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[9] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[9]),
        .Q(rxeq_user_txcoeff_reg2[9]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_control_reg1_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_control_reg1_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_control_reg2_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_control_reg1[0]),
        .Q(txeq_control_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_control_reg2_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_control_reg1[1]),
        .Q(txeq_control_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \txeq_deemph_reg1_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[0]),
        .S(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg1_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg1_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg1_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg1_reg[4] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg1_reg[5] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \txeq_deemph_reg2_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[0]),
        .Q(txeq_deemph_reg2[0]),
        .S(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg2_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[1]),
        .Q(txeq_deemph_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg2_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[2]),
        .Q(txeq_deemph_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg2_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[3]),
        .Q(txeq_deemph_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg2_reg[4] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[4]),
        .Q(txeq_deemph_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg2_reg[5] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[5]),
        .Q(txeq_deemph_reg2[5]),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h00040000)) 
    \txeq_preset[0]_i_1 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .I2(rst_cpllreset),
        .I3(txeq_preset_reg2[2]),
        .I4(txeq_preset_reg2[0]),
        .O(p_0_out[0]));
  LUT5 #(
    .INIT(32'hAAEABBAF)) 
    \txeq_preset[10]_i_1 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[0]),
        .O(p_0_out[10]));
  LUT5 #(
    .INIT(32'hFFFF1811)) 
    \txeq_preset[11]_i_1 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(rst_cpllreset),
        .O(p_0_out[11]));
  LUT5 #(
    .INIT(32'h01111510)) 
    \txeq_preset[12]_i_1 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .I4(txeq_preset_reg2[1]),
        .O(p_0_out[12]));
  LUT5 #(
    .INIT(32'h01000010)) 
    \txeq_preset[13]_i_1 
       (.I0(txeq_preset_reg2[2]),
        .I1(rst_cpllreset),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[1]),
        .O(p_0_out[13]));
  LUT5 #(
    .INIT(32'h00100100)) 
    \txeq_preset[14]_i_1 
       (.I0(txeq_preset_reg2[2]),
        .I1(rst_cpllreset),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[0]),
        .O(p_0_out[14]));
  LUT4 #(
    .INIT(16'hF0F1)) 
    \txeq_preset[15]_i_1 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[1]),
        .I2(rst_cpllreset),
        .I3(txeq_preset_reg2[3]),
        .O(p_0_out[15]));
  LUT4 #(
    .INIT(16'h0006)) 
    \txeq_preset[16]_i_1 
       (.I0(txeq_preset_reg2[3]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[2]),
        .I3(rst_cpllreset),
        .O(p_0_out[16]));
  LUT4 #(
    .INIT(16'hAABA)) 
    \txeq_preset[17]_i_1 
       (.I0(rst_cpllreset),
        .I1(fsm_tx[0]),
        .I2(fsm_tx[1]),
        .I3(fsm_tx[2]),
        .O(\txeq_preset[17]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF1091)) 
    \txeq_preset[17]_i_2 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(rst_cpllreset),
        .O(p_0_out[17]));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[1]_i_1 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[2]),
        .I4(txeq_preset_reg2[0]),
        .O(p_0_out[1]));
  LUT4 #(
    .INIT(16'h4440)) 
    \txeq_preset[2]_i_1 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .O(p_0_out[2]));
  LUT5 #(
    .INIT(32'h00441140)) 
    \txeq_preset[3]_i_1 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[1]),
        .O(\txeq_preset[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000AAAA3C00AAAA)) 
    \txeq_preset[7]_i_1 
       (.I0(\txeq_preset_reg_n_0_[7] ),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[2]),
        .I3(\txeq_preset[7]_i_2_n_0 ),
        .I4(\txeq_preset[17]_i_1_n_0 ),
        .I5(rst_cpllreset),
        .O(\txeq_preset[7]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \txeq_preset[7]_i_2 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .O(\txeq_preset[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hAABEAFAF)) 
    \txeq_preset[8]_i_1 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[1]),
        .O(p_0_out[8]));
  LUT5 #(
    .INIT(32'hCFCCCCFD)) 
    \txeq_preset[9]_i_1 
       (.I0(txeq_preset_reg2[1]),
        .I1(rst_cpllreset),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[0]),
        .I4(txeq_preset_reg2[2]),
        .O(p_0_out[9]));
  LUT3 #(
    .INIT(8'h04)) 
    txeq_preset_done_i_1
       (.I0(fsm_tx[2]),
        .I1(fsm_tx[1]),
        .I2(fsm_tx[0]),
        .O(txeq_preset_done_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txeq_preset_done_reg
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_preset_done_i_1_n_0),
        .Q(txeq_preset_done),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg1_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg1_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg1_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg1_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg2_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_preset_reg1[0]),
        .Q(txeq_preset_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg2_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_preset_reg1[1]),
        .Q(txeq_preset_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg2_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_preset_reg1[2]),
        .Q(txeq_preset_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg2_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_preset_reg1[3]),
        .Q(txeq_preset_reg2[3]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[0]),
        .Q(\txeq_preset_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[10] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[10]),
        .Q(\txeq_preset_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[11] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[11]),
        .Q(\txeq_preset_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[12] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[12]),
        .Q(\txeq_preset_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[13] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[13]),
        .Q(\txeq_preset_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[14] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[14]),
        .Q(\txeq_preset_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[15] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[15]),
        .Q(\txeq_preset_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[16] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[16]),
        .Q(\txeq_preset_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[17] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[17]),
        .Q(\txeq_preset_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[1]),
        .Q(\txeq_preset_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[2]),
        .Q(\txeq_preset_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[3]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[7] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(\txeq_preset[7]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[8] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[8]),
        .Q(\txeq_preset_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[9] 
       (.C(\fs_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(p_0_out[9]),
        .Q(\txeq_preset_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1782" *) 
  LUT5 #(
    .INIT(32'h45404040)) 
    \txeq_txcoeff[0]_i_1 
       (.I0(fsm_tx[2]),
        .I1(\txeq_txcoeff[0]_i_2_n_0 ),
        .I2(fsm_tx[1]),
        .I3(fsm_tx[0]),
        .I4(\txeq_txcoeff_reg_n_0_[6] ),
        .O(\txeq_txcoeff[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[0]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[7] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[0] ),
        .O(\txeq_txcoeff[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[10]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[10]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[16] ),
        .O(\txeq_txcoeff[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[10]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[16] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[10] ),
        .O(\txeq_txcoeff[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[11]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[10] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[11]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[17] ),
        .O(\txeq_txcoeff[11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[11]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[18] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[17] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[11] ),
        .O(\txeq_txcoeff[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[12]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[11] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[12]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[18] ),
        .O(\txeq_txcoeff[12]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[12]_i_2 
       (.I0(txeq_deemph_reg2[0]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[18] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[12] ),
        .O(\txeq_txcoeff[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[13]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[12] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[13]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(txeq_deemph_reg2[0]),
        .O(\txeq_txcoeff[13]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[13]_i_2 
       (.I0(txeq_deemph_reg2[1]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(txeq_deemph_reg2[0]),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[13] ),
        .O(\txeq_txcoeff[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[14]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[14]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(txeq_deemph_reg2[1]),
        .O(\txeq_txcoeff[14]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[14]_i_2 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(txeq_deemph_reg2[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[14] ),
        .O(\txeq_txcoeff[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[15]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[14] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[15]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(txeq_deemph_reg2[2]),
        .O(\txeq_txcoeff[15]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[15]_i_2 
       (.I0(txeq_deemph_reg2[3]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(txeq_deemph_reg2[2]),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[15] ),
        .O(\txeq_txcoeff[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[16]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[15] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[16]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(txeq_deemph_reg2[3]),
        .O(\txeq_txcoeff[16]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[16]_i_2 
       (.I0(txeq_deemph_reg2[4]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(txeq_deemph_reg2[3]),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[16] ),
        .O(\txeq_txcoeff[16]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[17]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[17]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(txeq_deemph_reg2[4]),
        .O(\txeq_txcoeff[17]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[17]_i_2 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(txeq_deemph_reg2[4]),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[17] ),
        .O(\txeq_txcoeff[17]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFF040FFF)) 
    \txeq_txcoeff[18]_i_1 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(fsm_tx[2]),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .O(txeq_txcoeff));
  LUT6 #(
    .INIT(64'h440F440044004400)) 
    \txeq_txcoeff[18]_i_2 
       (.I0(fsm_tx[1]),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .I2(\txeq_txcoeff[18]_i_3_n_0 ),
        .I3(fsm_tx[2]),
        .I4(txeq_deemph_reg2[5]),
        .I5(fsm_tx[0]),
        .O(\txeq_txcoeff[18]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1783" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \txeq_txcoeff[18]_i_3 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(fsm_tx[1]),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .O(\txeq_txcoeff[18]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[1]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[0] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[1]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[7] ),
        .O(\txeq_txcoeff[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[1]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[7] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[1] ),
        .O(\txeq_txcoeff[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[2]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[1] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[2]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[8] ),
        .O(\txeq_txcoeff[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[2]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[8] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[2] ),
        .O(\txeq_txcoeff[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[3]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[2] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[3]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[9] ),
        .O(\txeq_txcoeff[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[3]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[10] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[9] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[3] ),
        .O(\txeq_txcoeff[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \txeq_txcoeff[4]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[3] ),
        .I1(fsm_tx[1]),
        .I2(fsm_tx[2]),
        .I3(\txeq_txcoeff[4]_i_2_n_0 ),
        .O(\txeq_txcoeff[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA0E0A0A0A020A0A0)) 
    \txeq_txcoeff[4]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[10] ),
        .I1(fsm_tx[1]),
        .I2(fsm_tx[0]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(\txeq_txcoeff_reg_n_0_[11] ),
        .O(\txeq_txcoeff[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \txeq_txcoeff[5]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[4] ),
        .I1(fsm_tx[1]),
        .I2(fsm_tx[2]),
        .I3(\txeq_txcoeff[5]_i_2_n_0 ),
        .O(\txeq_txcoeff[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA0E0A0A0A020A0A0)) 
    \txeq_txcoeff[5]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[11] ),
        .I1(fsm_tx[1]),
        .I2(fsm_tx[0]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(\txeq_txcoeff_reg_n_0_[12] ),
        .O(\txeq_txcoeff[5]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \txeq_txcoeff[6]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[5] ),
        .I1(fsm_tx[1]),
        .I2(fsm_tx[2]),
        .I3(\txeq_txcoeff[6]_i_2_n_0 ),
        .O(\txeq_txcoeff[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCACCCCCC00000000)) 
    \txeq_txcoeff[6]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(fsm_tx[1]),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(fsm_tx[0]),
        .O(\txeq_txcoeff[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[7]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[6] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[7]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[13] ),
        .O(\txeq_txcoeff[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[7]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[14] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[13] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[7] ),
        .O(\txeq_txcoeff[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[8]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[7] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[8]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[14] ),
        .O(\txeq_txcoeff[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[8]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[15] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[14] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[8] ),
        .O(\txeq_txcoeff[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[9]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[9]_i_2_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[15] ),
        .O(\txeq_txcoeff[9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[9]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[15] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[9] ),
        .O(\txeq_txcoeff[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000004000F000400)) 
    \txeq_txcoeff_cnt[0]_i_1 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(fsm_tx[2]),
        .I3(fsm_tx[0]),
        .I4(fsm_tx[1]),
        .I5(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(txeq_txcoeff_cnt[0]));
  (* SOFT_HLUTNM = "soft_lutpair1783" *) 
  LUT5 #(
    .INIT(32'h00006000)) 
    \txeq_txcoeff_cnt[1]_i_1 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(fsm_tx[0]),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[2]),
        .O(txeq_txcoeff_cnt[1]));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[0]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[1]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[0] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[0]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[10] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[10]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[10] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[11] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[11]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[11] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[12] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[12]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[12] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[13] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[13]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[13] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[14] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[14]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[14] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[15] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[15]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[15] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[16] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[16]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[16] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[17] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[17]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[17] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[18] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[18]_i_2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[18] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[1] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[1]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[2] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[2]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[3] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[3]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[3] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[4] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[4]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[4] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[5] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[5]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[5] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[6] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[6]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[6] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[7] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[7]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[7] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[8] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[8]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[8] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[9] 
       (.C(\fs_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[9]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[9] ),
        .R(rst_cpllreset));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pipe_eq" *) 
module xdma_0_pcie2_ip_pipe_eq_34
   (eq_rxeq_adapt_done_1,
    TXPRECURSOR,
    TXMAINCURSOR,
    TXPOSTCURSOR,
    rst_cpllreset,
    \lf_reg2_reg[5] );
  output eq_rxeq_adapt_done_1;
  output [4:0]TXPRECURSOR;
  output [6:0]TXMAINCURSOR;
  output [4:0]TXPOSTCURSOR;
  input rst_cpllreset;
  input \lf_reg2_reg[5] ;

  wire \FSM_onehot_fsm_rx[1]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm_rx[1]_i_2__0_n_0 ;
  wire \FSM_onehot_fsm_rx[3]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm_rx[4]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[1] ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[2] ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[3] ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[4] ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[5] ;
  wire \FSM_onehot_fsm_rx_reg_n_0_[6] ;
  wire \FSM_sequential_fsm_tx[1]_i_2__0_n_0 ;
  wire \FSM_sequential_fsm_tx[2]_i_2__0_n_0 ;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire eq_rxeq_adapt_done_1;
  wire [2:0]fsm_tx;
  wire [2:0]fsm_tx__0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2;
  wire [11:0]in10;
  wire \lf_reg2_reg[5] ;
  wire [17:0]p_0_out;
  wire rst_cpllreset;
  wire rxeq_adapt_done_i_2__0_n_0;
  wire rxeq_adapt_done_reg_i_2__0_n_0;
  wire rxeq_adapt_done_reg_reg_n_0;
  wire [2:0]rxeq_cnt;
  wire \rxeq_cnt_reg_n_0_[0] ;
  wire \rxeq_cnt_reg_n_0_[1] ;
  wire \rxeq_cnt_reg_n_0_[2] ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rxeq_control_reg2;
  wire [5:0]rxeq_fs;
  wire \rxeq_fs[5]_i_1__0_n_0 ;
  wire \rxeq_fs_reg_n_0_[0] ;
  wire \rxeq_fs_reg_n_0_[1] ;
  wire \rxeq_fs_reg_n_0_[2] ;
  wire \rxeq_fs_reg_n_0_[3] ;
  wire \rxeq_fs_reg_n_0_[4] ;
  wire \rxeq_fs_reg_n_0_[5] ;
  wire [5:0]rxeq_lf;
  wire \rxeq_lf[5]_i_1__0_n_0 ;
  wire \rxeq_lf_reg_n_0_[0] ;
  wire \rxeq_lf_reg_n_0_[1] ;
  wire \rxeq_lf_reg_n_0_[2] ;
  wire \rxeq_lf_reg_n_0_[3] ;
  wire \rxeq_lf_reg_n_0_[4] ;
  wire \rxeq_lf_reg_n_0_[5] ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]rxeq_lffs_reg2;
  wire rxeq_new_txcoeff_req;
  wire rxeq_new_txcoeff_req_reg_n_0;
  wire \rxeq_preset[0]_i_1__0_n_0 ;
  wire \rxeq_preset[1]_i_1__0_n_0 ;
  wire \rxeq_preset[2]_i_1__0_n_0 ;
  wire \rxeq_preset[2]_i_2__0_n_0 ;
  wire \rxeq_preset[2]_i_3__0_n_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]rxeq_preset_reg2;
  wire \rxeq_preset_reg_n_0_[0] ;
  wire \rxeq_preset_reg_n_0_[1] ;
  wire \rxeq_preset_reg_n_0_[2] ;
  wire rxeq_preset_valid;
  wire rxeq_scan_i_n_0;
  wire rxeq_scan_i_n_1;
  wire rxeq_scan_i_n_2;
  wire rxeq_scan_i_n_3;
  wire rxeq_scan_i_n_4;
  wire [17:0]rxeq_txcoeff;
  wire \rxeq_txcoeff_reg_n_0_[0] ;
  wire \rxeq_txcoeff_reg_n_0_[1] ;
  wire \rxeq_txcoeff_reg_n_0_[2] ;
  wire \rxeq_txcoeff_reg_n_0_[3] ;
  wire \rxeq_txcoeff_reg_n_0_[4] ;
  wire \rxeq_txcoeff_reg_n_0_[5] ;
  wire [3:0]rxeq_txpreset;
  wire \rxeq_txpreset[3]_i_1__0_n_0 ;
  wire \rxeq_txpreset[3]_i_3__0_n_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]rxeq_txpreset_reg2;
  wire \rxeq_txpreset_reg_n_0_[0] ;
  wire \rxeq_txpreset_reg_n_0_[1] ;
  wire \rxeq_txpreset_reg_n_0_[2] ;
  wire \rxeq_txpreset_reg_n_0_[3] ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_en_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_user_mode_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]rxeq_user_txcoeff_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]txeq_control_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]txeq_deemph_reg2;
  wire \txeq_preset[17]_i_1__0_n_0 ;
  wire \txeq_preset[3]_i_1__0_n_0 ;
  wire \txeq_preset[7]_i_1__0_n_0 ;
  wire \txeq_preset[7]_i_2__0_n_0 ;
  wire txeq_preset_done;
  wire txeq_preset_done_i_1__0_n_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txeq_preset_reg2;
  wire \txeq_preset_reg_n_0_[0] ;
  wire \txeq_preset_reg_n_0_[10] ;
  wire \txeq_preset_reg_n_0_[11] ;
  wire \txeq_preset_reg_n_0_[12] ;
  wire \txeq_preset_reg_n_0_[13] ;
  wire \txeq_preset_reg_n_0_[14] ;
  wire \txeq_preset_reg_n_0_[15] ;
  wire \txeq_preset_reg_n_0_[16] ;
  wire \txeq_preset_reg_n_0_[17] ;
  wire \txeq_preset_reg_n_0_[1] ;
  wire \txeq_preset_reg_n_0_[2] ;
  wire \txeq_preset_reg_n_0_[3] ;
  wire \txeq_preset_reg_n_0_[7] ;
  wire \txeq_preset_reg_n_0_[8] ;
  wire \txeq_preset_reg_n_0_[9] ;
  wire txeq_txcoeff;
  wire \txeq_txcoeff[0]_i_1__0_n_0 ;
  wire \txeq_txcoeff[0]_i_2__0_n_0 ;
  wire \txeq_txcoeff[10]_i_1__0_n_0 ;
  wire \txeq_txcoeff[10]_i_2__0_n_0 ;
  wire \txeq_txcoeff[11]_i_1__0_n_0 ;
  wire \txeq_txcoeff[11]_i_2__0_n_0 ;
  wire \txeq_txcoeff[12]_i_1__0_n_0 ;
  wire \txeq_txcoeff[12]_i_2__0_n_0 ;
  wire \txeq_txcoeff[13]_i_1__0_n_0 ;
  wire \txeq_txcoeff[13]_i_2__0_n_0 ;
  wire \txeq_txcoeff[14]_i_1__0_n_0 ;
  wire \txeq_txcoeff[14]_i_2__0_n_0 ;
  wire \txeq_txcoeff[15]_i_1__0_n_0 ;
  wire \txeq_txcoeff[15]_i_2__0_n_0 ;
  wire \txeq_txcoeff[16]_i_1__0_n_0 ;
  wire \txeq_txcoeff[16]_i_2__0_n_0 ;
  wire \txeq_txcoeff[17]_i_1__0_n_0 ;
  wire \txeq_txcoeff[17]_i_2__0_n_0 ;
  wire \txeq_txcoeff[18]_i_2__0_n_0 ;
  wire \txeq_txcoeff[18]_i_3__0_n_0 ;
  wire \txeq_txcoeff[1]_i_1__0_n_0 ;
  wire \txeq_txcoeff[1]_i_2__0_n_0 ;
  wire \txeq_txcoeff[2]_i_1__0_n_0 ;
  wire \txeq_txcoeff[2]_i_2__0_n_0 ;
  wire \txeq_txcoeff[3]_i_1__0_n_0 ;
  wire \txeq_txcoeff[3]_i_2__0_n_0 ;
  wire \txeq_txcoeff[4]_i_1__0_n_0 ;
  wire \txeq_txcoeff[4]_i_2__0_n_0 ;
  wire \txeq_txcoeff[5]_i_1__0_n_0 ;
  wire \txeq_txcoeff[5]_i_2__0_n_0 ;
  wire \txeq_txcoeff[6]_i_1__0_n_0 ;
  wire \txeq_txcoeff[6]_i_2__0_n_0 ;
  wire \txeq_txcoeff[7]_i_1__0_n_0 ;
  wire \txeq_txcoeff[7]_i_2__0_n_0 ;
  wire \txeq_txcoeff[8]_i_1__0_n_0 ;
  wire \txeq_txcoeff[8]_i_2__0_n_0 ;
  wire \txeq_txcoeff[9]_i_1__0_n_0 ;
  wire \txeq_txcoeff[9]_i_2__0_n_0 ;
  wire [1:0]txeq_txcoeff_cnt;
  wire \txeq_txcoeff_cnt_reg_n_0_[0] ;
  wire \txeq_txcoeff_cnt_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[0] ;
  wire \txeq_txcoeff_reg_n_0_[10] ;
  wire \txeq_txcoeff_reg_n_0_[11] ;
  wire \txeq_txcoeff_reg_n_0_[12] ;
  wire \txeq_txcoeff_reg_n_0_[13] ;
  wire \txeq_txcoeff_reg_n_0_[14] ;
  wire \txeq_txcoeff_reg_n_0_[15] ;
  wire \txeq_txcoeff_reg_n_0_[16] ;
  wire \txeq_txcoeff_reg_n_0_[17] ;
  wire \txeq_txcoeff_reg_n_0_[18] ;
  wire \txeq_txcoeff_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[2] ;
  wire \txeq_txcoeff_reg_n_0_[3] ;
  wire \txeq_txcoeff_reg_n_0_[4] ;
  wire \txeq_txcoeff_reg_n_0_[5] ;
  wire \txeq_txcoeff_reg_n_0_[6] ;
  wire \txeq_txcoeff_reg_n_0_[7] ;
  wire \txeq_txcoeff_reg_n_0_[8] ;
  wire \txeq_txcoeff_reg_n_0_[9] ;

  LUT5 #(
    .INIT(32'hABABABAA)) 
    \FSM_onehot_fsm_rx[1]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx[1]_i_2__0_n_0 ),
        .I1(rxeq_control_reg2[0]),
        .I2(rxeq_control_reg2[1]),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm_rx[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \FSM_onehot_fsm_rx[1]_i_2__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm_rx_reg_n_0_[5] ),
        .O(\FSM_onehot_fsm_rx[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF8FF88888888)) 
    \FSM_onehot_fsm_rx[3]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .I3(\rxeq_cnt_reg_n_0_[1] ),
        .I4(\rxeq_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_rx[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1833" *) 
  LUT5 #(
    .INIT(32'h2ABA2AAA)) 
    \FSM_onehot_fsm_rx[4]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\rxeq_cnt_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_rx[4]_i_1__0_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_rx[1]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_scan_i_n_4),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_rx[3]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[4] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_rx[4]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[5] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_scan_i_n_3),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[5] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_rx_reg[6] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_scan_i_n_2),
        .Q(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'hC04FC043C04FF04F)) 
    \FSM_sequential_fsm_tx[0]_i_1__0 
       (.I0(\FSM_sequential_fsm_tx[1]_i_2__0_n_0 ),
        .I1(fsm_tx[0]),
        .I2(fsm_tx[1]),
        .I3(fsm_tx[2]),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(fsm_tx__0[0]));
  LUT6 #(
    .INIT(64'h3F703F7C3F7C0F70)) 
    \FSM_sequential_fsm_tx[1]_i_1__0 
       (.I0(\FSM_sequential_fsm_tx[1]_i_2__0_n_0 ),
        .I1(fsm_tx[0]),
        .I2(fsm_tx[1]),
        .I3(fsm_tx[2]),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(fsm_tx__0[1]));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_fsm_tx[1]_i_2__0 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fsm_tx[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h3A2A2A227F7F7F77)) 
    \FSM_sequential_fsm_tx[2]_i_1__0 
       (.I0(fsm_tx[2]),
        .I1(fsm_tx[1]),
        .I2(fsm_tx[0]),
        .I3(txeq_control_reg2[1]),
        .I4(txeq_control_reg2[0]),
        .I5(\FSM_sequential_fsm_tx[2]_i_2__0_n_0 ),
        .O(fsm_tx__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1831" *) 
  LUT5 #(
    .INIT(32'hD0FFDFFF)) 
    \FSM_sequential_fsm_tx[2]_i_2__0 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(fsm_tx[0]),
        .I3(fsm_tx[1]),
        .I4(txeq_preset_done),
        .O(\FSM_sequential_fsm_tx[2]_i_2__0_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_tx_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(fsm_tx__0[0]),
        .Q(fsm_tx[0]),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_tx_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(fsm_tx__0[1]),
        .Q(fsm_tx[1]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_tx_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(fsm_tx__0[2]),
        .Q(fsm_tx[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE gen3_reg1_reg
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(gen3_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE gen3_reg2_reg
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(rst_cpllreset));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_22__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .O(TXPOSTCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_23__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[16] ),
        .O(TXPOSTCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_24__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .O(TXPOSTCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_25__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .O(TXPOSTCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_26__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[13] ),
        .O(TXPOSTCURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_27__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[4] ),
        .O(TXPRECURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_28__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[3] ),
        .O(TXPRECURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_29__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[2] ),
        .O(TXPRECURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_30__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[1] ),
        .O(TXPRECURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_31__0 
       (.I0(\txeq_txcoeff_reg_n_0_[0] ),
        .I1(gen3_reg2),
        .O(TXPRECURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_32__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .O(TXMAINCURSOR[6]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_33__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .O(TXMAINCURSOR[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_34__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .O(TXMAINCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_35__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[9] ),
        .O(TXMAINCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_36__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[8] ),
        .O(TXMAINCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_37 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[7] ),
        .O(TXMAINCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtp_channel.gtpe2_channel_i_i_38 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[6] ),
        .O(TXMAINCURSOR[0]));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFFFFFF)) 
    rxeq_adapt_done_i_2__0
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[5] ),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I5(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .O(rxeq_adapt_done_i_2__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_scan_i_n_1),
        .Q(eq_rxeq_adapt_done_1),
        .R(rst_cpllreset));
  LUT3 #(
    .INIT(8'h08)) 
    rxeq_adapt_done_reg_i_2__0
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_control_reg2[0]),
        .I2(rxeq_control_reg2[1]),
        .O(rxeq_adapt_done_reg_i_2__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg_reg
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_scan_i_n_0),
        .Q(rxeq_adapt_done_reg_reg_n_0),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h8888FFF8)) 
    \rxeq_cnt[0]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I4(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[0]));
  (* SOFT_HLUTNM = "soft_lutpair1834" *) 
  LUT4 #(
    .INIT(16'h6660)) 
    \rxeq_cnt[1]_i_1__0 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(rxeq_cnt[1]));
  (* SOFT_HLUTNM = "soft_lutpair1833" *) 
  LUT5 #(
    .INIT(32'h78787800)) 
    \rxeq_cnt[2]_i_1__0 
       (.I0(\rxeq_cnt_reg_n_0_[0] ),
        .I1(\rxeq_cnt_reg_n_0_[1] ),
        .I2(\rxeq_cnt_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(rxeq_cnt[2]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_cnt[0]),
        .Q(\rxeq_cnt_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_cnt[1]),
        .Q(\rxeq_cnt_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_cnt[2]),
        .Q(\rxeq_cnt_reg_n_0_[2] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_control_reg1_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_control_reg1_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_control_reg2_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_control_reg1[0]),
        .Q(rxeq_control_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_control_reg2_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_control_reg1[1]),
        .Q(rxeq_control_reg2[1]),
        .R(rst_cpllreset));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[0]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[0]),
        .O(rxeq_fs[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[1]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[1]),
        .O(rxeq_fs[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[2]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[2]),
        .O(rxeq_fs[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[3]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[3]),
        .O(rxeq_fs[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[4]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[4]),
        .O(rxeq_fs[4]));
  LUT3 #(
    .INIT(8'hF8)) 
    \rxeq_fs[5]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_rx[1]_i_2__0_n_0 ),
        .O(\rxeq_fs[5]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_fs[5]_i_2__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(rxeq_lffs_reg2[5]),
        .O(rxeq_fs[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[0]),
        .Q(\rxeq_fs_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[1]),
        .Q(\rxeq_fs_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[2]),
        .Q(\rxeq_fs_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[3]),
        .Q(\rxeq_fs_reg_n_0_[3] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[4] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[4]),
        .Q(\rxeq_fs_reg_n_0_[4] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[5] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[5]),
        .Q(\rxeq_fs_reg_n_0_[5] ),
        .R(rst_cpllreset));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[0]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[0]),
        .O(rxeq_lf[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[1]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[1]),
        .O(rxeq_lf[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[2]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[2]),
        .O(rxeq_lf[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[3]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[3]),
        .O(rxeq_lf[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[4]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[4]),
        .O(rxeq_lf[4]));
  LUT5 #(
    .INIT(32'hEAAAAAAA)) 
    \rxeq_lf[5]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx[1]_i_2__0_n_0 ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[0] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .O(\rxeq_lf[5]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \rxeq_lf[5]_i_2__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I1(rxeq_lffs_reg2[5]),
        .O(rxeq_lf[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[0]),
        .Q(\rxeq_lf_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[1]),
        .Q(\rxeq_lf_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[2]),
        .Q(\rxeq_lf_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[3]),
        .Q(\rxeq_lf_reg_n_0_[3] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[4] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[4]),
        .Q(\rxeq_lf_reg_n_0_[4] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[5] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[5]),
        .Q(\rxeq_lf_reg_n_0_[5] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[4] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg1_reg[5] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[0]),
        .Q(rxeq_lffs_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[1]),
        .Q(rxeq_lffs_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[2]),
        .Q(rxeq_lffs_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[3]),
        .Q(rxeq_lffs_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[4] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[4]),
        .Q(rxeq_lffs_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_lffs_reg2_reg[5] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[5]),
        .Q(rxeq_lffs_reg2[5]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_new_txcoeff_req_reg
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_new_txcoeff_req),
        .Q(rxeq_new_txcoeff_req_reg_n_0),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'hA8FFA800)) 
    \rxeq_preset[0]_i_1__0 
       (.I0(rxeq_preset_reg2[0]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I3(\rxeq_preset[2]_i_2__0_n_0 ),
        .I4(\rxeq_preset_reg_n_0_[0] ),
        .O(\rxeq_preset[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hA8FFA800)) 
    \rxeq_preset[1]_i_1__0 
       (.I0(rxeq_preset_reg2[1]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I3(\rxeq_preset[2]_i_2__0_n_0 ),
        .I4(\rxeq_preset_reg_n_0_[1] ),
        .O(\rxeq_preset[1]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hA8FFA800)) 
    \rxeq_preset[2]_i_1__0 
       (.I0(rxeq_preset_reg2[2]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I3(\rxeq_preset[2]_i_2__0_n_0 ),
        .I4(\rxeq_preset_reg_n_0_[2] ),
        .O(\rxeq_preset[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0002)) 
    \rxeq_preset[2]_i_2__0 
       (.I0(\rxeq_preset[2]_i_3__0_n_0 ),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[5] ),
        .I4(rxeq_adapt_done_reg_i_2__0_n_0),
        .I5(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .O(\rxeq_preset[2]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1834" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \rxeq_preset[2]_i_3__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(\rxeq_preset[2]_i_3__0_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg1_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg1_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg1_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg2_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_preset_reg1[0]),
        .Q(rxeq_preset_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg2_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_preset_reg1[1]),
        .Q(rxeq_preset_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_preset_reg2_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_preset_reg1[2]),
        .Q(rxeq_preset_reg2[2]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(\rxeq_preset[0]_i_1__0_n_0 ),
        .Q(\rxeq_preset_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(\rxeq_preset[1]_i_1__0_n_0 ),
        .Q(\rxeq_preset_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(\rxeq_preset[2]_i_1__0_n_0 ),
        .Q(\rxeq_preset_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_preset_valid_reg
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .Q(rxeq_preset_valid),
        .R(rst_cpllreset));
  xdma_0_pcie2_ip_rxeq_scan rxeq_scan_i
       (.D({rxeq_scan_i_n_2,rxeq_scan_i_n_3,rxeq_scan_i_n_4}),
        .\FSM_onehot_fsm_rx_reg[5] ({\rxeq_cnt_reg_n_0_[2] ,\rxeq_cnt_reg_n_0_[1] ,\rxeq_cnt_reg_n_0_[0] }),
        .Q({\FSM_onehot_fsm_rx_reg_n_0_[6] ,\FSM_onehot_fsm_rx_reg_n_0_[5] ,\FSM_onehot_fsm_rx_reg_n_0_[4] ,\FSM_onehot_fsm_rx_reg_n_0_[2] ,\FSM_onehot_fsm_rx_reg_n_0_[1] }),
        .adapt_done_reg_0(rxeq_scan_i_n_0),
        .eq_rxeq_adapt_done_1(eq_rxeq_adapt_done_1),
        .\fs_reg1_reg[5]_0 ({\rxeq_fs_reg_n_0_[5] ,\rxeq_fs_reg_n_0_[4] ,\rxeq_fs_reg_n_0_[3] ,\rxeq_fs_reg_n_0_[2] ,\rxeq_fs_reg_n_0_[1] ,\rxeq_fs_reg_n_0_[0] }),
        .\lf_reg1_reg[5]_0 ({\rxeq_lf_reg_n_0_[5] ,\rxeq_lf_reg_n_0_[4] ,\rxeq_lf_reg_n_0_[3] ,\rxeq_lf_reg_n_0_[2] ,\rxeq_lf_reg_n_0_[1] ,\rxeq_lf_reg_n_0_[0] }),
        .\lf_reg2_reg[5]_0 (\lf_reg2_reg[5] ),
        .new_txcoeff_done_reg_0(rxeq_scan_i_n_1),
        .new_txcoeff_req_reg1_reg_0(rxeq_new_txcoeff_req_reg_n_0),
        .out(rxeq_control_reg2),
        .\preset_reg1_reg[2]_0 ({\rxeq_preset_reg_n_0_[2] ,\rxeq_preset_reg_n_0_[1] ,\rxeq_preset_reg_n_0_[0] }),
        .rst_cpllreset(rst_cpllreset),
        .rxeq_adapt_done_reg(rxeq_adapt_done_i_2__0_n_0),
        .rxeq_adapt_done_reg_reg(\FSM_onehot_fsm_rx[1]_i_2__0_n_0 ),
        .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_i_2__0_n_0),
        .rxeq_adapt_done_reg_reg_1(rxeq_adapt_done_reg_reg_n_0),
        .rxeq_new_txcoeff_req(rxeq_new_txcoeff_req),
        .rxeq_preset_valid(rxeq_preset_valid),
        .\txcoeff_reg1_reg[17]_0 ({in10,\rxeq_txcoeff_reg_n_0_[5] ,\rxeq_txcoeff_reg_n_0_[4] ,\rxeq_txcoeff_reg_n_0_[3] ,\rxeq_txcoeff_reg_n_0_[2] ,\rxeq_txcoeff_reg_n_0_[1] ,\rxeq_txcoeff_reg_n_0_[0] }),
        .\txpreset_reg1_reg[3]_0 ({\rxeq_txpreset_reg_n_0_[3] ,\rxeq_txpreset_reg_n_0_[2] ,\rxeq_txpreset_reg_n_0_[1] ,\rxeq_txpreset_reg_n_0_[0] }));
  (* SOFT_HLUTNM = "soft_lutpair1835" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[0]_i_1__0 
       (.I0(in10[0]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[0]));
  (* SOFT_HLUTNM = "soft_lutpair1840" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[10]_i_1__0 
       (.I0(in10[10]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[10]));
  (* SOFT_HLUTNM = "soft_lutpair1840" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[11]_i_1__0 
       (.I0(in10[11]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[11]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[12]_i_1__0 
       (.I0(txeq_deemph_reg2[0]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[12]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[13]_i_1__0 
       (.I0(txeq_deemph_reg2[1]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[13]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[14]_i_1__0 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[14]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[15]_i_1__0 
       (.I0(txeq_deemph_reg2[3]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[15]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[16]_i_1__0 
       (.I0(txeq_deemph_reg2[4]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[16]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[17]_i_1__0 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[17]));
  (* SOFT_HLUTNM = "soft_lutpair1835" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[1]_i_1__0 
       (.I0(in10[1]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[1]));
  (* SOFT_HLUTNM = "soft_lutpair1836" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[2]_i_1__0 
       (.I0(in10[2]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[2]));
  (* SOFT_HLUTNM = "soft_lutpair1836" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[3]_i_1__0 
       (.I0(in10[3]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[3]));
  (* SOFT_HLUTNM = "soft_lutpair1837" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[4]_i_1__0 
       (.I0(in10[4]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[4]));
  (* SOFT_HLUTNM = "soft_lutpair1837" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[5]_i_1__0 
       (.I0(in10[5]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[5]));
  (* SOFT_HLUTNM = "soft_lutpair1838" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[6]_i_1__0 
       (.I0(in10[6]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[6]));
  (* SOFT_HLUTNM = "soft_lutpair1838" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[7]_i_1__0 
       (.I0(in10[7]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[7]));
  (* SOFT_HLUTNM = "soft_lutpair1839" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[8]_i_1__0 
       (.I0(in10[8]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[8]));
  (* SOFT_HLUTNM = "soft_lutpair1839" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txcoeff[9]_i_1__0 
       (.I0(in10[9]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txcoeff[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[0]),
        .Q(\rxeq_txcoeff_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[10] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[10]),
        .Q(in10[4]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[11] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[11]),
        .Q(in10[5]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[12] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[12]),
        .Q(in10[6]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[13] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[13]),
        .Q(in10[7]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[14] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[14]),
        .Q(in10[8]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[15] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[15]),
        .Q(in10[9]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[16] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[16]),
        .Q(in10[10]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[17] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[17]),
        .Q(in10[11]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[1]),
        .Q(\rxeq_txcoeff_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[2]),
        .Q(\rxeq_txcoeff_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[3]),
        .Q(\rxeq_txcoeff_reg_n_0_[3] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[4] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[4]),
        .Q(\rxeq_txcoeff_reg_n_0_[4] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[5] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[5]),
        .Q(\rxeq_txcoeff_reg_n_0_[5] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[6] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[6]),
        .Q(in10[0]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[7] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[7]),
        .Q(in10[1]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[8] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[8]),
        .Q(in10[2]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[9] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[9]),
        .Q(in10[3]),
        .R(rst_cpllreset));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txpreset[0]_i_1__0 
       (.I0(rxeq_txpreset_reg2[0]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txpreset[0]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txpreset[1]_i_1__0 
       (.I0(rxeq_txpreset_reg2[1]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txpreset[1]));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txpreset[2]_i_1__0 
       (.I0(rxeq_txpreset_reg2[2]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txpreset[2]));
  LUT5 #(
    .INIT(32'hFFFFF044)) 
    \rxeq_txpreset[3]_i_1__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[6] ),
        .I1(\rxeq_txpreset[3]_i_3__0_n_0 ),
        .I2(rxeq_control_reg2[1]),
        .I3(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .I4(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .O(\rxeq_txpreset[3]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \rxeq_txpreset[3]_i_2__0 
       (.I0(rxeq_txpreset_reg2[3]),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_txpreset[3]));
  LUT3 #(
    .INIT(8'h01)) 
    \rxeq_txpreset[3]_i_3__0 
       (.I0(\FSM_onehot_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_rx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_rx_reg_n_0_[5] ),
        .O(\rxeq_txpreset[3]_i_3__0_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg1_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg1_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg1_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg1_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg2_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[0]),
        .Q(rxeq_txpreset_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg2_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[1]),
        .Q(rxeq_txpreset_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg2_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[2]),
        .Q(rxeq_txpreset_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_txpreset_reg2_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[3]),
        .Q(rxeq_txpreset_reg2[3]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txpreset[0]),
        .Q(\rxeq_txpreset_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txpreset[1]),
        .Q(\rxeq_txpreset_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txpreset[2]),
        .Q(\rxeq_txpreset_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txpreset[3]),
        .Q(\rxeq_txpreset_reg_n_0_[3] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_user_en_reg1_reg
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_en_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_user_en_reg2_reg
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_en_reg1),
        .Q(rxeq_user_en_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_user_mode_reg1_reg
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_mode_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_user_mode_reg2_reg
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_mode_reg1),
        .Q(rxeq_user_mode_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[10] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[10]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[11] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[11]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[12] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[12]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[13] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[13]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[14] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[14]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[15] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[15]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[16] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[16]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[17] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[17]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[4] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[5] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[6] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[6]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[7] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[7]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[8] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[8]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[9] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[9]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[0]),
        .Q(rxeq_user_txcoeff_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[10] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[10]),
        .Q(rxeq_user_txcoeff_reg2[10]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[11] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[11]),
        .Q(rxeq_user_txcoeff_reg2[11]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[12] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[12]),
        .Q(rxeq_user_txcoeff_reg2[12]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[13] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[13]),
        .Q(rxeq_user_txcoeff_reg2[13]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[14] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[14]),
        .Q(rxeq_user_txcoeff_reg2[14]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[15] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[15]),
        .Q(rxeq_user_txcoeff_reg2[15]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[16] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[16]),
        .Q(rxeq_user_txcoeff_reg2[16]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[17] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[17]),
        .Q(rxeq_user_txcoeff_reg2[17]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[1]),
        .Q(rxeq_user_txcoeff_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[2]),
        .Q(rxeq_user_txcoeff_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[3]),
        .Q(rxeq_user_txcoeff_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[4] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[4]),
        .Q(rxeq_user_txcoeff_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[5] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[5]),
        .Q(rxeq_user_txcoeff_reg2[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[6] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[6]),
        .Q(rxeq_user_txcoeff_reg2[6]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[7] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[7]),
        .Q(rxeq_user_txcoeff_reg2[7]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[8] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[8]),
        .Q(rxeq_user_txcoeff_reg2[8]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[9] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[9]),
        .Q(rxeq_user_txcoeff_reg2[9]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_control_reg1_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_control_reg1_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_control_reg2_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_control_reg1[0]),
        .Q(txeq_control_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_control_reg2_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_control_reg1[1]),
        .Q(txeq_control_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \txeq_deemph_reg1_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[0]),
        .S(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg1_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg1_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg1_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg1_reg[4] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg1_reg[5] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \txeq_deemph_reg2_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[0]),
        .Q(txeq_deemph_reg2[0]),
        .S(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg2_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[1]),
        .Q(txeq_deemph_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg2_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[2]),
        .Q(txeq_deemph_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg2_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[3]),
        .Q(txeq_deemph_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg2_reg[4] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[4]),
        .Q(txeq_deemph_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_deemph_reg2_reg[5] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_deemph_reg1[5]),
        .Q(txeq_deemph_reg2[5]),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h00040000)) 
    \txeq_preset[0]_i_1__0 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .I2(rst_cpllreset),
        .I3(txeq_preset_reg2[2]),
        .I4(txeq_preset_reg2[0]),
        .O(p_0_out[0]));
  LUT5 #(
    .INIT(32'hAAEABBAF)) 
    \txeq_preset[10]_i_1__0 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[0]),
        .O(p_0_out[10]));
  LUT5 #(
    .INIT(32'hFFFF1811)) 
    \txeq_preset[11]_i_1__0 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(rst_cpllreset),
        .O(p_0_out[11]));
  LUT5 #(
    .INIT(32'h01111510)) 
    \txeq_preset[12]_i_1__0 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .I4(txeq_preset_reg2[1]),
        .O(p_0_out[12]));
  LUT5 #(
    .INIT(32'h01000010)) 
    \txeq_preset[13]_i_1__0 
       (.I0(txeq_preset_reg2[2]),
        .I1(rst_cpllreset),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[1]),
        .O(p_0_out[13]));
  LUT5 #(
    .INIT(32'h00100100)) 
    \txeq_preset[14]_i_1__0 
       (.I0(txeq_preset_reg2[2]),
        .I1(rst_cpllreset),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[0]),
        .O(p_0_out[14]));
  LUT4 #(
    .INIT(16'hF0F1)) 
    \txeq_preset[15]_i_1__0 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[1]),
        .I2(rst_cpllreset),
        .I3(txeq_preset_reg2[3]),
        .O(p_0_out[15]));
  LUT4 #(
    .INIT(16'h0006)) 
    \txeq_preset[16]_i_1__0 
       (.I0(txeq_preset_reg2[3]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[2]),
        .I3(rst_cpllreset),
        .O(p_0_out[16]));
  LUT4 #(
    .INIT(16'hAABA)) 
    \txeq_preset[17]_i_1__0 
       (.I0(rst_cpllreset),
        .I1(fsm_tx[0]),
        .I2(fsm_tx[1]),
        .I3(fsm_tx[2]),
        .O(\txeq_preset[17]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF1091)) 
    \txeq_preset[17]_i_2__0 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(rst_cpllreset),
        .O(p_0_out[17]));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[1]_i_1__0 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[2]),
        .I4(txeq_preset_reg2[0]),
        .O(p_0_out[1]));
  LUT4 #(
    .INIT(16'h4440)) 
    \txeq_preset[2]_i_1__0 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .O(p_0_out[2]));
  LUT5 #(
    .INIT(32'h00441140)) 
    \txeq_preset[3]_i_1__0 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[1]),
        .O(\txeq_preset[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000AAAA3C00AAAA)) 
    \txeq_preset[7]_i_1__0 
       (.I0(\txeq_preset_reg_n_0_[7] ),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[2]),
        .I3(\txeq_preset[7]_i_2__0_n_0 ),
        .I4(\txeq_preset[17]_i_1__0_n_0 ),
        .I5(rst_cpllreset),
        .O(\txeq_preset[7]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \txeq_preset[7]_i_2__0 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .O(\txeq_preset[7]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hAABEAFAF)) 
    \txeq_preset[8]_i_1__0 
       (.I0(rst_cpllreset),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[1]),
        .O(p_0_out[8]));
  LUT5 #(
    .INIT(32'hCFCCCCFD)) 
    \txeq_preset[9]_i_1__0 
       (.I0(txeq_preset_reg2[1]),
        .I1(rst_cpllreset),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[0]),
        .I4(txeq_preset_reg2[2]),
        .O(p_0_out[9]));
  (* SOFT_HLUTNM = "soft_lutpair1832" *) 
  LUT3 #(
    .INIT(8'h04)) 
    txeq_preset_done_i_1__0
       (.I0(fsm_tx[2]),
        .I1(fsm_tx[1]),
        .I2(fsm_tx[0]),
        .O(txeq_preset_done_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txeq_preset_done_reg
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_preset_done_i_1__0_n_0),
        .Q(txeq_preset_done),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg1_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg1_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg1_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg1_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg2_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_preset_reg1[0]),
        .Q(txeq_preset_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg2_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_preset_reg1[1]),
        .Q(txeq_preset_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg2_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_preset_reg1[2]),
        .Q(txeq_preset_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txeq_preset_reg2_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_preset_reg1[3]),
        .Q(txeq_preset_reg2[3]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[0]),
        .Q(\txeq_preset_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[10] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[10]),
        .Q(\txeq_preset_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[11] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[11]),
        .Q(\txeq_preset_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[12] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[12]),
        .Q(\txeq_preset_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[13] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[13]),
        .Q(\txeq_preset_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[14] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[14]),
        .Q(\txeq_preset_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[15] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[15]),
        .Q(\txeq_preset_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[16] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[16]),
        .Q(\txeq_preset_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[17] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[17]),
        .Q(\txeq_preset_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[1]),
        .Q(\txeq_preset_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[2]),
        .Q(\txeq_preset_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[3]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[7] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(\txeq_preset[7]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[8] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[8]),
        .Q(\txeq_preset_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[9] 
       (.C(\lf_reg2_reg[5] ),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(p_0_out[9]),
        .Q(\txeq_preset_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h45404040)) 
    \txeq_txcoeff[0]_i_1__0 
       (.I0(fsm_tx[2]),
        .I1(\txeq_txcoeff[0]_i_2__0_n_0 ),
        .I2(fsm_tx[1]),
        .I3(fsm_tx[0]),
        .I4(\txeq_txcoeff_reg_n_0_[6] ),
        .O(\txeq_txcoeff[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[0]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[7] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[0] ),
        .O(\txeq_txcoeff[0]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[10]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[10]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[16] ),
        .O(\txeq_txcoeff[10]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[10]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[16] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[10] ),
        .O(\txeq_txcoeff[10]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[11]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[10] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[11]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[17] ),
        .O(\txeq_txcoeff[11]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[11]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[18] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[17] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[11] ),
        .O(\txeq_txcoeff[11]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[12]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[11] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[12]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[18] ),
        .O(\txeq_txcoeff[12]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[12]_i_2__0 
       (.I0(txeq_deemph_reg2[0]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[18] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[12] ),
        .O(\txeq_txcoeff[12]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[13]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[12] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[13]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(txeq_deemph_reg2[0]),
        .O(\txeq_txcoeff[13]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[13]_i_2__0 
       (.I0(txeq_deemph_reg2[1]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(txeq_deemph_reg2[0]),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[13] ),
        .O(\txeq_txcoeff[13]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[14]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[14]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(txeq_deemph_reg2[1]),
        .O(\txeq_txcoeff[14]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[14]_i_2__0 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(txeq_deemph_reg2[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[14] ),
        .O(\txeq_txcoeff[14]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[15]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[14] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[15]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(txeq_deemph_reg2[2]),
        .O(\txeq_txcoeff[15]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[15]_i_2__0 
       (.I0(txeq_deemph_reg2[3]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(txeq_deemph_reg2[2]),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[15] ),
        .O(\txeq_txcoeff[15]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[16]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[15] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[16]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(txeq_deemph_reg2[3]),
        .O(\txeq_txcoeff[16]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[16]_i_2__0 
       (.I0(txeq_deemph_reg2[4]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(txeq_deemph_reg2[3]),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[16] ),
        .O(\txeq_txcoeff[16]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[17]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[17]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(txeq_deemph_reg2[4]),
        .O(\txeq_txcoeff[17]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[17]_i_2__0 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(txeq_deemph_reg2[4]),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[17] ),
        .O(\txeq_txcoeff[17]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFF040FFF)) 
    \txeq_txcoeff[18]_i_1__0 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(fsm_tx[2]),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .O(txeq_txcoeff));
  LUT6 #(
    .INIT(64'h440F440044004400)) 
    \txeq_txcoeff[18]_i_2__0 
       (.I0(fsm_tx[1]),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .I2(\txeq_txcoeff[18]_i_3__0_n_0 ),
        .I3(fsm_tx[2]),
        .I4(txeq_deemph_reg2[5]),
        .I5(fsm_tx[0]),
        .O(\txeq_txcoeff[18]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1831" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \txeq_txcoeff[18]_i_3__0 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(fsm_tx[1]),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .O(\txeq_txcoeff[18]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[1]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[0] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[1]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[7] ),
        .O(\txeq_txcoeff[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[1]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[7] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[1] ),
        .O(\txeq_txcoeff[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[2]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[1] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[2]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[8] ),
        .O(\txeq_txcoeff[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[2]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[8] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[2] ),
        .O(\txeq_txcoeff[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[3]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[2] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[3]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[9] ),
        .O(\txeq_txcoeff[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[3]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[10] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[9] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[3] ),
        .O(\txeq_txcoeff[3]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \txeq_txcoeff[4]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[3] ),
        .I1(fsm_tx[1]),
        .I2(fsm_tx[2]),
        .I3(\txeq_txcoeff[4]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCACCCCCC00000000)) 
    \txeq_txcoeff[4]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[11] ),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(fsm_tx[1]),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(fsm_tx[0]),
        .O(\txeq_txcoeff[4]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \txeq_txcoeff[5]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[4] ),
        .I1(fsm_tx[1]),
        .I2(fsm_tx[2]),
        .I3(\txeq_txcoeff[5]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[5]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCACCCCCC00000000)) 
    \txeq_txcoeff[5]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[12] ),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(fsm_tx[1]),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(fsm_tx[0]),
        .O(\txeq_txcoeff[5]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \txeq_txcoeff[6]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[5] ),
        .I1(fsm_tx[1]),
        .I2(fsm_tx[2]),
        .I3(\txeq_txcoeff[6]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[6]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCACCCCCC00000000)) 
    \txeq_txcoeff[6]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(fsm_tx[1]),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(fsm_tx[0]),
        .O(\txeq_txcoeff[6]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[7]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[6] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[7]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[13] ),
        .O(\txeq_txcoeff[7]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[7]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[14] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[13] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[7] ),
        .O(\txeq_txcoeff[7]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[8]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[7] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[8]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[14] ),
        .O(\txeq_txcoeff[8]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[8]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[15] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[14] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[8] ),
        .O(\txeq_txcoeff[8]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h30BB308830883088)) 
    \txeq_txcoeff[9]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(fsm_tx[2]),
        .I2(\txeq_txcoeff[9]_i_2__0_n_0 ),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[0]),
        .I5(\txeq_txcoeff_reg_n_0_[15] ),
        .O(\txeq_txcoeff[9]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \txeq_txcoeff[9]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\txeq_txcoeff_reg_n_0_[15] ),
        .I4(fsm_tx[0]),
        .I5(\txeq_preset_reg_n_0_[9] ),
        .O(\txeq_txcoeff[9]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h000004000F000400)) 
    \txeq_txcoeff_cnt[0]_i_1__0 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(fsm_tx[2]),
        .I3(fsm_tx[0]),
        .I4(fsm_tx[1]),
        .I5(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(txeq_txcoeff_cnt[0]));
  (* SOFT_HLUTNM = "soft_lutpair1832" *) 
  LUT5 #(
    .INIT(32'h00006000)) 
    \txeq_txcoeff_cnt[1]_i_1__0 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(fsm_tx[0]),
        .I3(fsm_tx[1]),
        .I4(fsm_tx[2]),
        .O(txeq_txcoeff_cnt[1]));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[0]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[1]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[0] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[0]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[10] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[10]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[10] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[11] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[11]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[11] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[12] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[12]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[12] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[13] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[13]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[13] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[14] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[14]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[14] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[15] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[15]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[15] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[16] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[16]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[16] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[17] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[17]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[17] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[18] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[18]_i_2__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[18] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[1] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[1]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[2] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[2]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[3] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[3]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[3] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[4] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[4]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[4] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[5] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[5]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[5] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[6] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[6]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[6] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[7] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[7]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[7] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[8] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[8]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[8] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[9] 
       (.C(\lf_reg2_reg[5] ),
        .CE(txeq_txcoeff),
        .D(\txeq_txcoeff[9]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[9] ),
        .R(rst_cpllreset));
endmodule

module xdma_0_pcie2_ip_pipe_sync
   (p_1_in,
    out,
    p_1_in0_in,
    txphinitdone_reg3_reg_0,
    Q,
    sync_txdlyen_0,
    \txsync_fsm.txsync_done_reg_0 ,
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0 ,
    \txsync_fsm.txsync_done_reg_1 ,
    \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ,
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ,
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ,
    rst_cpllreset,
    rxphaligndone_s_reg2_reg_0,
    SYNC_TXPHALIGNDONE,
    SYNC_TXSYNC_START,
    SYNC_MMCM_LOCK,
    SYNC_TXDLYSRESETDONE,
    SYNC_TXPHINITDONE,
    SYNC_RATE_IDLE,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXCDRLOCK,
    SYNC_TXSYNCDONE,
    SYNC_RXDLYSRESETDONE,
    SYNC_RXPHALIGNDONE_M,
    SYNC_RXPHALIGNDONE_S,
    SYNC_RXSYNCDONE);
  output p_1_in;
  output out;
  output p_1_in0_in;
  output txphinitdone_reg3_reg_0;
  output [2:0]Q;
  output sync_txdlyen_0;
  output [0:0]\txsync_fsm.txsync_done_reg_0 ;
  input \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0 ;
  input \txsync_fsm.txsync_done_reg_1 ;
  input \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ;
  input \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ;
  input \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ;
  input rst_cpllreset;
  input rxphaligndone_s_reg2_reg_0;
  input SYNC_TXPHALIGNDONE;
  input SYNC_TXSYNC_START;
  input SYNC_MMCM_LOCK;
  input SYNC_TXDLYSRESETDONE;
  input SYNC_TXPHINITDONE;
  input SYNC_RATE_IDLE;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input SYNC_RXCDRLOCK;
  input SYNC_TXSYNCDONE;
  input SYNC_RXDLYSRESETDONE;
  input SYNC_RXPHALIGNDONE_M;
  input SYNC_RXPHALIGNDONE_S;
  input SYNC_RXSYNCDONE;

  wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ;
  wire [2:0]Q;
  wire SYNC_MMCM_LOCK;
  wire SYNC_RATE_IDLE;
  wire SYNC_RXCDRLOCK;
  wire SYNC_RXDLYSRESETDONE;
  wire SYNC_RXPHALIGNDONE_M;
  wire SYNC_RXPHALIGNDONE_S;
  wire SYNC_RXSYNCDONE;
  wire SYNC_TXDLYSRESETDONE;
  wire SYNC_TXPHALIGNDONE;
  wire SYNC_TXPHINITDONE;
  wire SYNC_TXSYNCDONE;
  wire SYNC_TXSYNC_START;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2;
  wire rst_cpllreset;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg2;
  wire rxphaligndone_s_reg2_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg2;
  wire sync_txdlyen_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg3;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg3;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg3;
  wire \txsync_fsm.txdlyen_i_1_n_0 ;
  wire \txsync_fsm.txsync_done_i_1_n_0 ;
  wire [0:0]\txsync_fsm.txsync_done_reg_0 ;
  wire \txsync_fsm.txsync_done_reg_1 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg3;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg3;

  assign out = txphaligndone_reg3;
  assign p_1_in = txphaligndone_reg2;
  assign p_1_in0_in = txphinitdone_reg2;
  assign txphinitdone_reg3_reg_0 = txphinitdone_reg3;
  LUT5 #(
    .INIT(32'h1D1DFF1D)) 
    \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1 
       (.I0(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0 ),
        .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ),
        .I2(txsync_start_reg2),
        .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ),
        .I4(\txsync_fsm.txsync_done_reg_1 ),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2 
       (.I0(Q[1]),
        .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1 
       (.I0(mmcm_lock_reg2),
        .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ),
        .I3(txsync_start_reg2),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFD0D0D0)) 
    \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1 
       (.I0(txdlysresetdone_reg2),
        .I1(txdlysresetdone_reg3),
        .I2(Q[0]),
        .I3(mmcm_lock_reg2),
        .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h44F44444)) 
    \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1 
       (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0 ),
        .I1(Q[1]),
        .I2(txdlysresetdone_reg2),
        .I3(txdlysresetdone_reg3),
        .I4(Q[0]),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF8FFF8F888888888)) 
    \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1 
       (.I0(\txsync_fsm.txsync_done_reg_1 ),
        .I1(Q[2]),
        .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ),
        .I3(txphinitdone_reg3),
        .I4(txphinitdone_reg2),
        .I5(Q[1]),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEAFFEAEA2A002A2A)) 
    \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1 
       (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ),
        .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ),
        .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ),
        .I3(txphaligndone_reg3),
        .I4(txphaligndone_reg2),
        .I5(Q[2]),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[1] 
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0 ),
        .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[2] 
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0 ),
        .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[3] 
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0 ),
        .Q(Q[0]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4] 
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0 ),
        .Q(Q[1]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[5] 
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0 ),
        .Q(Q[2]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6] 
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0 ),
        .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE gen3_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(gen3_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE gen3_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_MMCM_LOCK),
        .Q(mmcm_lock_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_idle_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_idle_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RXCDRLOCK),
        .Q(rxcdrlock_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxdlysresetdone_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RXDLYSRESETDONE),
        .Q(rxdlysresetdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxdlysresetdone_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(rxdlysresetdone_reg1),
        .Q(rxdlysresetdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxelecidle_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(gt_rx_elec_idle_wire_filter),
        .Q(rxelecidle_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxelecidle_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(rxelecidle_reg1),
        .Q(rxelecidle_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxphaligndone_m_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RXPHALIGNDONE_M),
        .Q(rxphaligndone_m_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxphaligndone_m_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(rxphaligndone_m_reg1),
        .Q(rxphaligndone_m_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxphaligndone_s_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RXPHALIGNDONE_S),
        .Q(rxphaligndone_s_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxphaligndone_s_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(rxphaligndone_s_reg1),
        .Q(rxphaligndone_s_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsync_donem_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsync_donem_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsync_donem_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(rxsync_donem_reg1),
        .Q(rxsync_donem_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsync_start_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsync_start_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsync_start_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(rxsync_start_reg1),
        .Q(rxsync_start_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsyncdone_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RXSYNCDONE),
        .Q(rxsyncdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsyncdone_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(rxsyncdone_reg1),
        .Q(rxsyncdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txdlysresetdone_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_TXDLYSRESETDONE),
        .Q(txdlysresetdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txdlysresetdone_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(txdlysresetdone_reg1),
        .Q(txdlysresetdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txdlysresetdone_reg3_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(txdlysresetdone_reg2),
        .Q(txdlysresetdone_reg3),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphaligndone_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_TXPHALIGNDONE),
        .Q(txphaligndone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphaligndone_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(txphaligndone_reg1),
        .Q(txphaligndone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphaligndone_reg3_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(txphaligndone_reg2),
        .Q(txphaligndone_reg3),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphinitdone_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_TXPHINITDONE),
        .Q(txphinitdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphinitdone_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(txphinitdone_reg1),
        .Q(txphinitdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphinitdone_reg3_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(txphinitdone_reg2),
        .Q(txphinitdone_reg3),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'hABAAA8AA)) 
    \txsync_fsm.txdlyen_i_1 
       (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ),
        .I1(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0 ),
        .I2(txsync_start_reg2),
        .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ),
        .I4(sync_txdlyen_0),
        .O(\txsync_fsm.txdlyen_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \txsync_fsm.txdlyen_reg 
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(\txsync_fsm.txdlyen_i_1_n_0 ),
        .Q(sync_txdlyen_0),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'h222F222222202222)) 
    \txsync_fsm.txsync_done_i_1 
       (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ),
        .I1(\txsync_fsm.txsync_done_reg_1 ),
        .I2(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0 ),
        .I3(txsync_start_reg2),
        .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ),
        .I5(\txsync_fsm.txsync_done_reg_0 ),
        .O(\txsync_fsm.txsync_done_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \txsync_fsm.txsync_done_reg 
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_i_1_n_0 ),
        .Q(\txsync_fsm.txsync_done_reg_0 ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsync_start_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_TXSYNC_START),
        .Q(txsync_start_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsync_start_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(txsync_start_reg1),
        .Q(txsync_start_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsync_start_reg3_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(txsync_start_reg2),
        .Q(txsync_start_reg3),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsyncdone_reg1_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_TXSYNCDONE),
        .Q(txsyncdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsyncdone_reg2_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(txsyncdone_reg1),
        .Q(txsyncdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsyncdone_reg3_reg
       (.C(rxphaligndone_s_reg2_reg_0),
        .CE(1'b1),
        .D(txsyncdone_reg2),
        .Q(txsyncdone_reg3),
        .R(rst_cpllreset));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pipe_sync" *) 
module xdma_0_pcie2_ip_pipe_sync_35
   (p_1_in0_in,
    out,
    Q,
    \txsync_fsm.txsync_done_reg_0 ,
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0 ,
    \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ,
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ,
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ,
    rst_cpllreset,
    rxsyncdone_reg2_reg_0,
    SYNC_TXPHALIGNDONE,
    SYNC_TXSYNC_START,
    QRST_MMCM_LOCK,
    SYNC_TXDLYSRESETDONE,
    SYNC_TXPHINITDONE,
    SYNC_RATE_IDLE,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXCDRLOCK,
    SYNC_TXSYNCDONE,
    SYNC_RXDLYSRESETDONE,
    SYNC_RXPHALIGNDONE_M,
    SYNC_RXPHALIGNDONE_S,
    SYNC_RXSYNCDONE);
  output p_1_in0_in;
  output out;
  output [2:0]Q;
  output [0:0]\txsync_fsm.txsync_done_reg_0 ;
  input \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0 ;
  input \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ;
  input \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ;
  input \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ;
  input rst_cpllreset;
  input rxsyncdone_reg2_reg_0;
  input SYNC_TXPHALIGNDONE;
  input SYNC_TXSYNC_START;
  input QRST_MMCM_LOCK;
  input SYNC_TXDLYSRESETDONE;
  input SYNC_TXPHINITDONE;
  input SYNC_RATE_IDLE;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input SYNC_RXCDRLOCK;
  input SYNC_TXSYNCDONE;
  input SYNC_RXDLYSRESETDONE;
  input SYNC_RXPHALIGNDONE_M;
  input SYNC_RXPHALIGNDONE_S;
  input SYNC_RXSYNCDONE;

  wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ;
  wire [2:0]Q;
  wire QRST_MMCM_LOCK;
  wire SYNC_RATE_IDLE;
  wire SYNC_RXCDRLOCK;
  wire SYNC_RXDLYSRESETDONE;
  wire SYNC_RXPHALIGNDONE_M;
  wire SYNC_RXPHALIGNDONE_S;
  wire SYNC_RXSYNCDONE;
  wire SYNC_TXDLYSRESETDONE;
  wire SYNC_TXPHALIGNDONE;
  wire SYNC_TXPHINITDONE;
  wire SYNC_TXSYNCDONE;
  wire SYNC_TXSYNC_START;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2;
  wire rst_cpllreset;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxdlysresetdone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxelecidle_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_m_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxphaligndone_s_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_donem_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsync_start_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxsyncdone_reg2;
  wire rxsyncdone_reg2_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txdlysresetdone_reg3;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphaligndone_reg3;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txphinitdone_reg3;
  wire \txsync_fsm.txsync_done_i_1__0_n_0 ;
  wire [0:0]\txsync_fsm.txsync_done_reg_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsync_start_reg3;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txsyncdone_reg3;

  assign out = txphinitdone_reg3;
  assign p_1_in0_in = txphinitdone_reg2;
  LUT4 #(
    .INIT(16'hFF1D)) 
    \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0 
       (.I0(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0 ),
        .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ),
        .I2(txsync_start_reg2),
        .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ),
        .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0 
       (.I0(mmcm_lock_reg2),
        .I1(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ),
        .I3(txsync_start_reg2),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFD0D0D0)) 
    \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0 
       (.I0(txdlysresetdone_reg2),
        .I1(txdlysresetdone_reg3),
        .I2(Q[0]),
        .I3(mmcm_lock_reg2),
        .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h44F44444)) 
    \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0 
       (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0 ),
        .I1(Q[1]),
        .I2(txdlysresetdone_reg2),
        .I3(txdlysresetdone_reg3),
        .I4(Q[0]),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF450045004500)) 
    \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0 
       (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 ),
        .I1(txphaligndone_reg3),
        .I2(txphaligndone_reg2),
        .I3(Q[2]),
        .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0 ),
        .I5(Q[1]),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hAA080808)) 
    \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0 
       (.I0(Q[2]),
        .I1(txphaligndone_reg2),
        .I2(txphaligndone_reg3),
        .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 ),
        .I4(\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 ),
        .O(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[1] 
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0 ),
        .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[2] 
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0 ),
        .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[2] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[3] 
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0 ),
        .Q(Q[0]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4] 
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0 ),
        .Q(Q[1]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[5] 
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0 ),
        .Q(Q[2]),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6] 
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0 ),
        .Q(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE gen3_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(gen3_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE gen3_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(QRST_MMCM_LOCK),
        .Q(mmcm_lock_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_idle_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_idle_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RXCDRLOCK),
        .Q(rxcdrlock_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxdlysresetdone_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RXDLYSRESETDONE),
        .Q(rxdlysresetdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxdlysresetdone_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(rxdlysresetdone_reg1),
        .Q(rxdlysresetdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxelecidle_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(gt_rx_elec_idle_wire_filter),
        .Q(rxelecidle_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxelecidle_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(rxelecidle_reg1),
        .Q(rxelecidle_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxphaligndone_m_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RXPHALIGNDONE_M),
        .Q(rxphaligndone_m_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxphaligndone_m_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(rxphaligndone_m_reg1),
        .Q(rxphaligndone_m_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxphaligndone_s_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RXPHALIGNDONE_S),
        .Q(rxphaligndone_s_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxphaligndone_s_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(rxphaligndone_s_reg1),
        .Q(rxphaligndone_s_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsync_donem_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsync_donem_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsync_donem_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(rxsync_donem_reg1),
        .Q(rxsync_donem_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsync_start_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsync_start_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsync_start_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(rxsync_start_reg1),
        .Q(rxsync_start_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsyncdone_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_RXSYNCDONE),
        .Q(rxsyncdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxsyncdone_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(rxsyncdone_reg1),
        .Q(rxsyncdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txdlysresetdone_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_TXDLYSRESETDONE),
        .Q(txdlysresetdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txdlysresetdone_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(txdlysresetdone_reg1),
        .Q(txdlysresetdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txdlysresetdone_reg3_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(txdlysresetdone_reg2),
        .Q(txdlysresetdone_reg3),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphaligndone_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_TXPHALIGNDONE),
        .Q(txphaligndone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphaligndone_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(txphaligndone_reg1),
        .Q(txphaligndone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphaligndone_reg3_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(txphaligndone_reg2),
        .Q(txphaligndone_reg3),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphinitdone_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_TXPHINITDONE),
        .Q(txphinitdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphinitdone_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(txphinitdone_reg1),
        .Q(txphinitdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txphinitdone_reg3_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(txphinitdone_reg2),
        .Q(txphinitdone_reg3),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'hABAAA8AA)) 
    \txsync_fsm.txsync_done_i_1__0 
       (.I0(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[6] ),
        .I1(\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0 ),
        .I2(txsync_start_reg2),
        .I3(\FSM_onehot_txsync_fsm.fsm_tx_reg_n_0_[1] ),
        .I4(\txsync_fsm.txsync_done_reg_0 ),
        .O(\txsync_fsm.txsync_done_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \txsync_fsm.txsync_done_reg 
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_i_1__0_n_0 ),
        .Q(\txsync_fsm.txsync_done_reg_0 ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsync_start_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_TXSYNC_START),
        .Q(txsync_start_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsync_start_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(txsync_start_reg1),
        .Q(txsync_start_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsync_start_reg3_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(txsync_start_reg2),
        .Q(txsync_start_reg3),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsyncdone_reg1_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(SYNC_TXSYNCDONE),
        .Q(txsyncdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsyncdone_reg2_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(txsyncdone_reg1),
        .Q(txsyncdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txsyncdone_reg3_reg
       (.C(rxsyncdone_reg2_reg_0),
        .CE(1'b1),
        .D(txsyncdone_reg2),
        .Q(txsyncdone_reg3),
        .R(rst_cpllreset));
endmodule

module xdma_0_pcie2_ip_pipe_user
   (out,
    txcompliance_reg2_reg_0,
    rst_idle_reg2_reg_0,
    user_oobclk_0,
    user_rxbufreset_0,
    user_rxpcsreset_0,
    user_eyescanreset_0,
    user_rxcdrfreqreset_0,
    user_rxcdrreset_0,
    user_rxpmareset_0,
    \gtp_channel.gtpe2_channel_i ,
    user_resetovrd_0,
    D,
    SYNC_RXCDRLOCK,
    gt_rx_phy_status_wire_filter,
    txcompliance_reg2_reg_1,
    txcompliance_reg2_reg_2,
    txelecidle_reg2_reg_0,
    rst_cpllreset,
    pclk_sel_reg1_reg_0,
    \rxvalid_cnt_reg[3]_0 ,
    gt_rxresetdone_0,
    gt_txresetdone_0,
    pipe_tx0_elec_idle_gt,
    TXCHARDISPMODE,
    gt_rxcdrlock_0,
    SR,
    gt_rxvalid_0,
    RXSTATUS,
    rst_idle_reg1_reg_0,
    Q,
    eq_rxeq_adapt_done_0,
    gt_rx_elec_idle_wire_filter,
    gt_rxvalid_q_reg,
    gt_rx_phy_status_q_reg,
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4] ,
    p_1_in0_in,
    \txsync_fsm.txsync_done_reg ,
    p_1_in);
  output out;
  output txcompliance_reg2_reg_0;
  output rst_idle_reg2_reg_0;
  output user_oobclk_0;
  output user_rxbufreset_0;
  output user_rxpcsreset_0;
  output user_eyescanreset_0;
  output user_rxcdrfreqreset_0;
  output user_rxcdrreset_0;
  output user_rxpmareset_0;
  output \gtp_channel.gtpe2_channel_i ;
  output user_resetovrd_0;
  output [0:0]D;
  output SYNC_RXCDRLOCK;
  output [0:0]gt_rx_phy_status_wire_filter;
  output txcompliance_reg2_reg_1;
  output txcompliance_reg2_reg_2;
  output txelecidle_reg2_reg_0;
  input rst_cpllreset;
  input pclk_sel_reg1_reg_0;
  input \rxvalid_cnt_reg[3]_0 ;
  input gt_rxresetdone_0;
  input gt_txresetdone_0;
  input pipe_tx0_elec_idle_gt;
  input [0:0]TXCHARDISPMODE;
  input gt_rxcdrlock_0;
  input [0:0]SR;
  input gt_rxvalid_0;
  input [0:0]RXSTATUS;
  input [0:0]rst_idle_reg1_reg_0;
  input [1:0]Q;
  input eq_rxeq_adapt_done_0;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input gt_rxvalid_q_reg;
  input [0:0]gt_rx_phy_status_q_reg;
  input \FSM_onehot_txsync_fsm.fsm_tx_reg[4] ;
  input p_1_in0_in;
  input \txsync_fsm.txsync_done_reg ;
  input p_1_in;

  wire [0:0]D;
  wire \FSM_onehot_resetovrd.fsm[0]_i_1_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[0]_i_2_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[1]_i_1_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[1]_i_2_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[2]_i_1_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[2]_i_2_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[3]_i_1_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[3]_i_2_n_0 ;
  wire \FSM_onehot_resetovrd.fsm_reg_n_0_[0] ;
  wire \FSM_onehot_resetovrd.fsm_reg_n_0_[1] ;
  wire \FSM_onehot_resetovrd.fsm_reg_n_0_[2] ;
  wire \FSM_onehot_resetovrd.fsm_reg_n_0_[3] ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg[4] ;
  wire [1:0]Q;
  wire [0:0]RXSTATUS;
  wire [0:0]SR;
  wire SYNC_RXCDRLOCK;
  wire [0:0]TXCHARDISPMODE;
  wire eq_rxeq_adapt_done_0;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [0:0]gt_rx_phy_status_q_reg;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire gt_rxcdrlock_0;
  wire gt_rxresetdone_0;
  wire gt_rxvalid_0;
  wire gt_rxvalid_q_i_5_n_0;
  wire gt_rxvalid_q_reg;
  wire gt_txresetdone_0;
  wire \gtp_channel.gtpe2_channel_i ;
  wire [1:0]oobclk_cnt;
  wire \oobclk_div.oobclk_i_1_n_0 ;
  wire [3:0]p_0_in__1;
  wire [3:0]p_0_in__2;
  wire p_1_in;
  wire p_1_in0_in;
  wire [1:0]p_1_in__0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg1;
  wire pclk_sel_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg2;
  wire pipe_tx0_elec_idle_gt;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg2;
  wire [7:0]reset_cnt0;
  wire \resetovrd.reset[0]_i_1_n_0 ;
  wire \resetovrd.reset[1]_i_1_n_0 ;
  wire \resetovrd.reset[2]_i_1_n_0 ;
  wire \resetovrd.reset[3]_i_1_n_0 ;
  wire \resetovrd.reset[4]_i_1_n_0 ;
  wire \resetovrd.reset[5]_i_1_n_0 ;
  wire \resetovrd.reset[6]_i_1_n_0 ;
  wire \resetovrd.reset[7]_i_1_n_0 ;
  wire \resetovrd.reset[7]_i_2_n_0 ;
  wire \resetovrd.reset_cnt[1]_i_1_n_0 ;
  wire \resetovrd.reset_cnt[4]_i_1_n_0 ;
  wire \resetovrd.reset_cnt[7]_i_1_n_0 ;
  wire [7:0]\resetovrd.reset_cnt_reg ;
  wire \resetovrd.reset_reg_n_0_[7] ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg2;
  wire rst_cpllreset;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg1;
  wire [0:0]rst_idle_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg2;
  wire [3:0]rxcdrlock_cnt_reg;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg2;
  wire [3:0]rxvalid_cnt_reg;
  wire \rxvalid_cnt_reg[3]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg2;
  wire txcompliance_reg2_reg_1;
  wire txcompliance_reg2_reg_2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg2;
  wire txelecidle_reg2_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg2;
  wire \txsync_fsm.txsync_done_reg ;
  wire user_eyescanreset_0;
  wire user_oobclk_0;
  wire user_resetovrd_0;
  wire user_rxbufreset_0;
  wire user_rxcdrfreqreset_0;
  wire user_rxcdrreset_0;
  wire user_rxdfelpmreset_0;
  wire user_rxpcsreset_0;
  wire user_rxpmareset_0;

  assign out = txelecidle_reg2;
  assign rst_idle_reg2_reg_0 = rst_idle_reg2;
  assign txcompliance_reg2_reg_0 = txcompliance_reg2;
  LUT6 #(
    .INIT(64'hFFFFFFFEAAAAAAAA)) 
    \FSM_onehot_resetovrd.fsm[0]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_eyescanreset_0),
        .I2(user_rxpcsreset_0),
        .I3(user_rxpmareset_0),
        .I4(\FSM_onehot_resetovrd.fsm[0]_i_2_n_0 ),
        .I5(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .O(\FSM_onehot_resetovrd.fsm[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \FSM_onehot_resetovrd.fsm[0]_i_2 
       (.I0(user_rxbufreset_0),
        .I1(user_rxcdrfreqreset_0),
        .I2(\resetovrd.reset_reg_n_0_[7] ),
        .I3(rxresetdone_reg2),
        .I4(user_rxcdrreset_0),
        .I5(user_rxdfelpmreset_0),
        .O(\FSM_onehot_resetovrd.fsm[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \FSM_onehot_resetovrd.fsm[1]_i_1 
       (.I0(resetovrd_start_reg2),
        .I1(\FSM_onehot_resetovrd.fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_resetovrd.fsm[1]_i_2_n_0 ),
        .I3(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .O(\FSM_onehot_resetovrd.fsm[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1803" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \FSM_onehot_resetovrd.fsm[1]_i_2 
       (.I0(user_eyescanreset_0),
        .I1(user_rxpcsreset_0),
        .I2(user_rxpmareset_0),
        .I3(\FSM_onehot_resetovrd.fsm[0]_i_2_n_0 ),
        .O(\FSM_onehot_resetovrd.fsm[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \FSM_onehot_resetovrd.fsm[2]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[3] ),
        .I1(\resetovrd.reset_cnt_reg [5]),
        .I2(\resetovrd.reset_cnt_reg [4]),
        .I3(\FSM_onehot_resetovrd.fsm[2]_i_2_n_0 ),
        .I4(\resetovrd.reset_cnt_reg [6]),
        .I5(\resetovrd.reset_cnt_reg [7]),
        .O(\FSM_onehot_resetovrd.fsm[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1802" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \FSM_onehot_resetovrd.fsm[2]_i_2 
       (.I0(\resetovrd.reset_cnt_reg [3]),
        .I1(\resetovrd.reset_cnt_reg [0]),
        .I2(\resetovrd.reset_cnt_reg [1]),
        .I3(\resetovrd.reset_cnt_reg [2]),
        .O(\FSM_onehot_resetovrd.fsm[2]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \FSM_onehot_resetovrd.fsm[3]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm[3]_i_2_n_0 ),
        .I1(\FSM_onehot_resetovrd.fsm_reg_n_0_[3] ),
        .I2(resetovrd_start_reg2),
        .I3(\FSM_onehot_resetovrd.fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_resetovrd.fsm[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1801" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \FSM_onehot_resetovrd.fsm[3]_i_2 
       (.I0(\resetovrd.reset_cnt_reg [7]),
        .I1(\resetovrd.reset_cnt_reg [6]),
        .I2(\FSM_onehot_resetovrd.fsm[2]_i_2_n_0 ),
        .I3(\resetovrd.reset_cnt_reg [4]),
        .I4(\resetovrd.reset_cnt_reg [5]),
        .O(\FSM_onehot_resetovrd.fsm[3]_i_2_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_resetovrd.fsm_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_resetovrd.fsm[0]_i_1_n_0 ),
        .Q(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010" *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_resetovrd.fsm_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_resetovrd.fsm[1]_i_1_n_0 ),
        .Q(\FSM_onehot_resetovrd.fsm_reg_n_0_[1] ),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_resetovrd.fsm_reg[2] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_resetovrd.fsm[2]_i_1_n_0 ),
        .Q(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_resetovrd.fsm_reg[3] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_resetovrd.fsm[3]_i_1_n_0 ),
        .Q(\FSM_onehot_resetovrd.fsm_reg_n_0_[3] ),
        .R(rst_cpllreset));
  LUT4 #(
    .INIT(16'h8F88)) 
    \FSM_onehot_txsync_fsm.fsm_tx[4]_i_2 
       (.I0(txcompliance_reg2),
        .I1(txelecidle_reg2),
        .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg[4] ),
        .I3(p_1_in0_in),
        .O(txcompliance_reg2_reg_1));
  LUT4 #(
    .INIT(16'h7077)) 
    \FSM_onehot_txsync_fsm.fsm_tx[5]_i_2 
       (.I0(txcompliance_reg2),
        .I1(txelecidle_reg2),
        .I2(\txsync_fsm.txsync_done_reg ),
        .I3(p_1_in),
        .O(txcompliance_reg2_reg_2));
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3 
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .O(txelecidle_reg2_reg_0));
  LUT5 #(
    .INIT(32'hFFFFE0FF)) 
    gt_rx_phy_status_q_i_1__0
       (.I0(rate_idle_reg2),
        .I1(rate_rxsync_reg2),
        .I2(gt_rx_phy_status_q_reg),
        .I3(rst_idle_reg2),
        .I4(rate_done_reg2),
        .O(gt_rx_phy_status_wire_filter));
  LUT6 #(
    .INIT(64'hBFFFBFFFFFFFBFFF)) 
    gt_rxvalid_q_i_3
       (.I0(gt_rxvalid_q_i_5_n_0),
        .I1(gt_rxvalid_0),
        .I2(rate_idle_reg2),
        .I3(rst_idle_reg2),
        .I4(gt_rx_elec_idle_wire_filter),
        .I5(gt_rxvalid_q_reg),
        .O(\gtp_channel.gtpe2_channel_i ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    gt_rxvalid_q_i_5
       (.I0(rxvalid_cnt_reg[3]),
        .I1(rxvalid_cnt_reg[0]),
        .I2(rxvalid_cnt_reg[1]),
        .I3(rxvalid_cnt_reg[2]),
        .O(gt_rxvalid_q_i_5_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \gtp_channel.gtpe2_channel_i_i_3 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[1] ),
        .O(user_resetovrd_0));
  (* SOFT_HLUTNM = "soft_lutpair1809" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oobclk_div.oobclk_cnt[0]_i_1 
       (.I0(oobclk_cnt[0]),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1809" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \oobclk_div.oobclk_cnt[1]_i_1 
       (.I0(oobclk_cnt[0]),
        .I1(oobclk_cnt[1]),
        .O(p_1_in__0[1]));
  FDRE #(
    .INIT(1'b0)) 
    \oobclk_div.oobclk_cnt_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_1_in__0[0]),
        .Q(oobclk_cnt[0]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \oobclk_div.oobclk_cnt_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_1_in__0[1]),
        .Q(oobclk_cnt[1]),
        .R(rst_cpllreset));
  LUT3 #(
    .INIT(8'hB8)) 
    \oobclk_div.oobclk_i_1 
       (.I0(oobclk_cnt[1]),
        .I1(pclk_sel_reg2),
        .I2(oobclk_cnt[0]),
        .O(\oobclk_div.oobclk_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \oobclk_div.oobclk_reg 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\oobclk_div.oobclk_i_1_n_0 ),
        .Q(user_oobclk_0),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE pclk_sel_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(pclk_sel_reg1_reg_0),
        .Q(pclk_sel_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE pclk_sel_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(pclk_sel_reg1),
        .Q(pclk_sel_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_done_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(Q[1]),
        .Q(rate_done_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_done_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rate_done_reg1),
        .Q(rate_done_reg2),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_gen3_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_gen3_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_gen3_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rate_gen3_reg1),
        .Q(rate_gen3_reg2),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_idle_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(Q[0]),
        .Q(rate_idle_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_idle_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_rxsync_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_rxsync_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_rxsync_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rate_rxsync_reg1),
        .Q(rate_rxsync_reg2),
        .R(SR));
  LUT2 #(
    .INIT(4'h8)) 
    \resetdone_reg1[0]_i_1 
       (.I0(rxresetdone_reg2),
        .I1(txresetdone_reg2),
        .O(D));
  LUT5 #(
    .INIT(32'h00FB00F0)) 
    \resetovrd.reset[0]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm[3]_i_2_n_0 ),
        .I1(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .I2(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I3(rst_cpllreset),
        .I4(user_rxpmareset_0),
        .O(\resetovrd.reset[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1808" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[1]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxpmareset_0),
        .O(\resetovrd.reset[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1808" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[2]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxcdrreset_0),
        .O(\resetovrd.reset[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1807" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[3]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxcdrfreqreset_0),
        .O(\resetovrd.reset[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1807" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[4]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxdfelpmreset_0),
        .O(\resetovrd.reset[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1803" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[5]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_eyescanreset_0),
        .O(\resetovrd.reset[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1806" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[6]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxpcsreset_0),
        .O(\resetovrd.reset[6]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFF4)) 
    \resetovrd.reset[7]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm[3]_i_2_n_0 ),
        .I1(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .I2(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I3(rst_cpllreset),
        .O(\resetovrd.reset[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1806" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[7]_i_2 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxbufreset_0),
        .O(\resetovrd.reset[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1805" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \resetovrd.reset_cnt[0]_i_1 
       (.I0(\resetovrd.reset_cnt_reg [0]),
        .O(reset_cnt0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1805" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \resetovrd.reset_cnt[1]_i_1 
       (.I0(\resetovrd.reset_cnt_reg [0]),
        .I1(\resetovrd.reset_cnt_reg [1]),
        .O(\resetovrd.reset_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1804" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \resetovrd.reset_cnt[2]_i_1 
       (.I0(\resetovrd.reset_cnt_reg [0]),
        .I1(\resetovrd.reset_cnt_reg [1]),
        .I2(\resetovrd.reset_cnt_reg [2]),
        .O(reset_cnt0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1804" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \resetovrd.reset_cnt[3]_i_1 
       (.I0(\resetovrd.reset_cnt_reg [2]),
        .I1(\resetovrd.reset_cnt_reg [1]),
        .I2(\resetovrd.reset_cnt_reg [0]),
        .I3(\resetovrd.reset_cnt_reg [3]),
        .O(reset_cnt0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1802" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \resetovrd.reset_cnt[4]_i_1 
       (.I0(\resetovrd.reset_cnt_reg [4]),
        .I1(\resetovrd.reset_cnt_reg [2]),
        .I2(\resetovrd.reset_cnt_reg [1]),
        .I3(\resetovrd.reset_cnt_reg [0]),
        .I4(\resetovrd.reset_cnt_reg [3]),
        .O(\resetovrd.reset_cnt[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \resetovrd.reset_cnt[5]_i_1 
       (.I0(\resetovrd.reset_cnt_reg [5]),
        .I1(\resetovrd.reset_cnt_reg [3]),
        .I2(\resetovrd.reset_cnt_reg [0]),
        .I3(\resetovrd.reset_cnt_reg [1]),
        .I4(\resetovrd.reset_cnt_reg [2]),
        .I5(\resetovrd.reset_cnt_reg [4]),
        .O(reset_cnt0[5]));
  LUT4 #(
    .INIT(16'hAAA9)) 
    \resetovrd.reset_cnt[6]_i_1 
       (.I0(\resetovrd.reset_cnt_reg [6]),
        .I1(\resetovrd.reset_cnt_reg [5]),
        .I2(\resetovrd.reset_cnt_reg [4]),
        .I3(\FSM_onehot_resetovrd.fsm[2]_i_2_n_0 ),
        .O(reset_cnt0[6]));
  LUT4 #(
    .INIT(16'hF1FF)) 
    \resetovrd.reset_cnt[7]_i_1 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .I1(\FSM_onehot_resetovrd.fsm_reg_n_0_[3] ),
        .I2(rst_cpllreset),
        .I3(\FSM_onehot_resetovrd.fsm[3]_i_2_n_0 ),
        .O(\resetovrd.reset_cnt[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1801" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \resetovrd.reset_cnt[7]_i_2 
       (.I0(\resetovrd.reset_cnt_reg [7]),
        .I1(\resetovrd.reset_cnt_reg [6]),
        .I2(\FSM_onehot_resetovrd.fsm[2]_i_2_n_0 ),
        .I3(\resetovrd.reset_cnt_reg [4]),
        .I4(\resetovrd.reset_cnt_reg [5]),
        .O(reset_cnt0[7]));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0[0]),
        .Q(\resetovrd.reset_cnt_reg [0]),
        .S(\resetovrd.reset_cnt[7]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\resetovrd.reset_cnt[1]_i_1_n_0 ),
        .Q(\resetovrd.reset_cnt_reg [1]),
        .S(\resetovrd.reset_cnt[7]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[2] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0[2]),
        .Q(\resetovrd.reset_cnt_reg [2]),
        .S(\resetovrd.reset_cnt[7]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[3] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0[3]),
        .Q(\resetovrd.reset_cnt_reg [3]),
        .S(\resetovrd.reset_cnt[7]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[4] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\resetovrd.reset_cnt[4]_i_1_n_0 ),
        .Q(\resetovrd.reset_cnt_reg [4]),
        .S(\resetovrd.reset_cnt[7]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[5] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0[5]),
        .Q(\resetovrd.reset_cnt_reg [5]),
        .S(\resetovrd.reset_cnt[7]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[6] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0[6]),
        .Q(\resetovrd.reset_cnt_reg [6]),
        .S(\resetovrd.reset_cnt[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_cnt_reg[7] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0[7]),
        .Q(\resetovrd.reset_cnt_reg [7]),
        .R(\resetovrd.reset_cnt[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\resetovrd.reset[0]_i_1_n_0 ),
        .Q(user_rxpmareset_0),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1_n_0 ),
        .D(\resetovrd.reset[1]_i_1_n_0 ),
        .Q(user_rxcdrreset_0),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[2] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1_n_0 ),
        .D(\resetovrd.reset[2]_i_1_n_0 ),
        .Q(user_rxcdrfreqreset_0),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[3] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1_n_0 ),
        .D(\resetovrd.reset[3]_i_1_n_0 ),
        .Q(user_rxdfelpmreset_0),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[4] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1_n_0 ),
        .D(\resetovrd.reset[4]_i_1_n_0 ),
        .Q(user_eyescanreset_0),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[5] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1_n_0 ),
        .D(\resetovrd.reset[5]_i_1_n_0 ),
        .Q(user_rxpcsreset_0),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[6] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1_n_0 ),
        .D(\resetovrd.reset[6]_i_1_n_0 ),
        .Q(user_rxbufreset_0),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[7] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1_n_0 ),
        .D(\resetovrd.reset[7]_i_2_n_0 ),
        .Q(\resetovrd.reset_reg_n_0_[7] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE resetovrd_start_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(1'b0),
        .Q(resetovrd_start_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE resetovrd_start_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(resetovrd_start_reg1),
        .Q(resetovrd_start_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rst_idle_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rst_idle_reg1_reg_0),
        .Q(rst_idle_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rst_idle_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(SR));
  LUT5 #(
    .INIT(32'h8A0A0A0A)) 
    \rxcdrlock_cnt[0]_i_1__0 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg[2]),
        .I2(rxcdrlock_cnt_reg[0]),
        .I3(rxcdrlock_cnt_reg[1]),
        .I4(rxcdrlock_cnt_reg[3]),
        .O(p_0_in__1[0]));
  LUT5 #(
    .INIT(32'hA8282828)) 
    \rxcdrlock_cnt[1]_i_1__0 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg[0]),
        .I2(rxcdrlock_cnt_reg[1]),
        .I3(rxcdrlock_cnt_reg[2]),
        .I4(rxcdrlock_cnt_reg[3]),
        .O(p_0_in__1[1]));
  LUT5 #(
    .INIT(32'hBCCC0000)) 
    \rxcdrlock_cnt[2]_i_1__0 
       (.I0(rxcdrlock_cnt_reg[3]),
        .I1(rxcdrlock_cnt_reg[2]),
        .I2(rxcdrlock_cnt_reg[1]),
        .I3(rxcdrlock_cnt_reg[0]),
        .I4(rxcdrlock_reg2),
        .O(p_0_in__1[2]));
  LUT5 #(
    .INIT(32'hA8888888)) 
    \rxcdrlock_cnt[3]_i_1__0 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg[3]),
        .I2(rxcdrlock_cnt_reg[1]),
        .I3(rxcdrlock_cnt_reg[0]),
        .I4(rxcdrlock_cnt_reg[2]),
        .O(p_0_in__1[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__1[0]),
        .Q(rxcdrlock_cnt_reg[0]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__1[1]),
        .Q(rxcdrlock_cnt_reg[1]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[2] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__1[2]),
        .Q(rxcdrlock_cnt_reg[2]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[3] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__1[3]),
        .Q(rxcdrlock_cnt_reg[3]),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h80000000)) 
    \rxcdrlock_reg1[0]_i_1 
       (.I0(gt_rxcdrlock_0),
        .I1(rxcdrlock_cnt_reg[3]),
        .I2(rxcdrlock_cnt_reg[1]),
        .I3(rxcdrlock_cnt_reg[0]),
        .I4(rxcdrlock_cnt_reg[2]),
        .O(SYNC_RXCDRLOCK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(gt_rxcdrlock_0),
        .Q(rxcdrlock_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_adapt_done_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(eq_rxeq_adapt_done_0),
        .Q(rxeq_adapt_done_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_adapt_done_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rxeq_adapt_done_reg1),
        .Q(rxeq_adapt_done_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxresetdone_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(gt_rxresetdone_0),
        .Q(rxresetdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxresetdone_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxstatus_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(RXSTATUS),
        .Q(rxstatus_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxstatus_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rxstatus_reg1),
        .Q(rxstatus_reg2),
        .R(SR));
  LUT6 #(
    .INIT(64'h8080000000FF0000)) 
    \rxvalid_cnt[0]_i_1 
       (.I0(rxvalid_cnt_reg[3]),
        .I1(rxvalid_cnt_reg[1]),
        .I2(rxvalid_cnt_reg[2]),
        .I3(rxstatus_reg2),
        .I4(rxvalid_reg2),
        .I5(rxvalid_cnt_reg[0]),
        .O(p_0_in__2[0]));
  LUT6 #(
    .INIT(64'h80000000E6660000)) 
    \rxvalid_cnt[1]_i_1 
       (.I0(rxvalid_cnt_reg[0]),
        .I1(rxvalid_cnt_reg[1]),
        .I2(rxvalid_cnt_reg[2]),
        .I3(rxvalid_cnt_reg[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__2[1]));
  LUT6 #(
    .INIT(64'h80000000EA6A0000)) 
    \rxvalid_cnt[2]_i_1 
       (.I0(rxvalid_cnt_reg[2]),
        .I1(rxvalid_cnt_reg[1]),
        .I2(rxvalid_cnt_reg[0]),
        .I3(rxvalid_cnt_reg[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__2[2]));
  LUT6 #(
    .INIT(64'hD444444400000000)) 
    \rxvalid_cnt[3]_i_1 
       (.I0(rxstatus_reg2),
        .I1(rxvalid_cnt_reg[3]),
        .I2(rxvalid_cnt_reg[0]),
        .I3(rxvalid_cnt_reg[1]),
        .I4(rxvalid_cnt_reg[2]),
        .I5(rxvalid_reg2),
        .O(p_0_in__2[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[0]),
        .Q(rxvalid_cnt_reg[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[1]),
        .Q(rxvalid_cnt_reg[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[2] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[2]),
        .Q(rxvalid_cnt_reg[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[3] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[3]),
        .Q(rxvalid_cnt_reg[3]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxvalid_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(gt_rxvalid_0),
        .Q(rxvalid_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxvalid_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rxvalid_reg1),
        .Q(rxvalid_reg2),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txcompliance_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(TXCHARDISPMODE),
        .Q(txcompliance_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txcompliance_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(txcompliance_reg1),
        .Q(txcompliance_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txelecidle_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(pipe_tx0_elec_idle_gt),
        .Q(txelecidle_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txelecidle_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(txelecidle_reg1),
        .Q(txelecidle_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txresetdone_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(gt_txresetdone_0),
        .Q(txresetdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txresetdone_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(rst_cpllreset));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_pipe_user" *) 
module xdma_0_pcie2_ip_pipe_user_36
   (out,
    txcompliance_reg2_reg_0,
    user_oobclk_1,
    user_rxbufreset_1,
    user_rxpcsreset_1,
    user_eyescanreset_1,
    user_rxcdrfreqreset_1,
    user_rxcdrreset_1,
    user_rxpmareset_1,
    \gtp_channel.gtpe2_channel_i ,
    D,
    SYNC_RXCDRLOCK,
    user_resetovrd_1,
    rst_idle_reg2_reg_0,
    gt_rx_phy_status_wire_filter,
    SYNC_TXPHINITDONE,
    rxsyncallin,
    SYNC_TXPHALIGNDONE,
    txcompliance_reg2_reg_1,
    txelecidle_reg2_reg_0,
    rst_cpllreset,
    pclk_sel_reg1_reg_0,
    \rxvalid_cnt_reg[3]_0 ,
    gt_rxresetdone_1,
    gt_txresetdone_1,
    pipe_tx1_elec_idle_gt,
    txcompliance_reg1_reg_0,
    gt_rxcdrlock_1,
    SR,
    gt_rxvalid_1,
    RXSTATUS,
    rst_idle_reg1_reg_0,
    Q,
    eq_rxeq_adapt_done_1,
    gt_rx_elec_idle_wire_filter,
    gt_rxvalid_q_reg,
    reg_clock_locked,
    phy_rdy_n_int_reg,
    gt_rx_phy_status_q_reg,
    txphinitdone_reg1_reg,
    txphinitdone_reg1_reg_0,
    txphinitdone_reg1_reg_1,
    txphinitdone_reg1_reg_2,
    SYNC_RXPHALIGNDONE_S,
    SYNC_RXPHALIGNDONE_M,
    txphaligndone_reg1_reg,
    txphaligndone_reg1_reg_0,
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4] ,
    p_1_in0_in);
  output out;
  output txcompliance_reg2_reg_0;
  output user_oobclk_1;
  output user_rxbufreset_1;
  output user_rxpcsreset_1;
  output user_eyescanreset_1;
  output user_rxcdrfreqreset_1;
  output user_rxcdrreset_1;
  output user_rxpmareset_1;
  output \gtp_channel.gtpe2_channel_i ;
  output [0:0]D;
  output SYNC_RXCDRLOCK;
  output user_resetovrd_1;
  output rst_idle_reg2_reg_0;
  output [0:0]gt_rx_phy_status_wire_filter;
  output SYNC_TXPHINITDONE;
  output rxsyncallin;
  output SYNC_TXPHALIGNDONE;
  output txcompliance_reg2_reg_1;
  output txelecidle_reg2_reg_0;
  input rst_cpllreset;
  input pclk_sel_reg1_reg_0;
  input \rxvalid_cnt_reg[3]_0 ;
  input gt_rxresetdone_1;
  input gt_txresetdone_1;
  input pipe_tx1_elec_idle_gt;
  input [0:0]txcompliance_reg1_reg_0;
  input gt_rxcdrlock_1;
  input [0:0]SR;
  input gt_rxvalid_1;
  input [0:0]RXSTATUS;
  input [0:0]rst_idle_reg1_reg_0;
  input [1:0]Q;
  input eq_rxeq_adapt_done_1;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input gt_rxvalid_q_reg;
  input reg_clock_locked;
  input phy_rdy_n_int_reg;
  input [0:0]gt_rx_phy_status_q_reg;
  input txphinitdone_reg1_reg;
  input txphinitdone_reg1_reg_0;
  input txphinitdone_reg1_reg_1;
  input txphinitdone_reg1_reg_2;
  input SYNC_RXPHALIGNDONE_S;
  input SYNC_RXPHALIGNDONE_M;
  input txphaligndone_reg1_reg;
  input txphaligndone_reg1_reg_0;
  input \FSM_onehot_txsync_fsm.fsm_tx_reg[4] ;
  input p_1_in0_in;

  wire [0:0]D;
  wire \FSM_onehot_resetovrd.fsm[0]_i_1__0_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[0]_i_2__0_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[1]_i_1__0_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[1]_i_2__0_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[2]_i_1__0_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[3]_i_1__0_n_0 ;
  wire \FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0 ;
  wire \FSM_onehot_resetovrd.fsm_reg_n_0_[0] ;
  wire \FSM_onehot_resetovrd.fsm_reg_n_0_[1] ;
  wire \FSM_onehot_resetovrd.fsm_reg_n_0_[2] ;
  wire \FSM_onehot_resetovrd.fsm_reg_n_0_[3] ;
  wire \FSM_onehot_txsync_fsm.fsm_tx_reg[4] ;
  wire [1:0]Q;
  wire [0:0]RXSTATUS;
  wire [0:0]SR;
  wire SYNC_RXCDRLOCK;
  wire SYNC_RXPHALIGNDONE_M;
  wire SYNC_RXPHALIGNDONE_S;
  wire SYNC_TXPHALIGNDONE;
  wire SYNC_TXPHINITDONE;
  wire eq_rxeq_adapt_done_1;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [0:0]gt_rx_phy_status_q_reg;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire gt_rxcdrlock_1;
  wire gt_rxresetdone_1;
  wire gt_rxvalid_1;
  wire gt_rxvalid_q_i_5__0_n_0;
  wire gt_rxvalid_q_reg;
  wire gt_txresetdone_1;
  wire \gtp_channel.gtpe2_channel_i ;
  wire [1:0]oobclk_cnt;
  wire \oobclk_div.oobclk_i_1__0_n_0 ;
  wire [3:0]p_0_in__4;
  wire [3:0]p_0_in__5;
  wire p_1_in0_in;
  wire [1:0]p_1_in__0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg1;
  wire pclk_sel_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire pclk_sel_reg2;
  wire phy_rdy_n_int_reg;
  wire pipe_tx1_elec_idle_gt;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_done_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_gen3_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_idle_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rate_rxsync_reg2;
  wire reg_clock_locked;
  wire [7:0]reset_cnt0__0;
  wire \resetovrd.reset[0]_i_1__0_n_0 ;
  wire \resetovrd.reset[1]_i_1__0_n_0 ;
  wire \resetovrd.reset[2]_i_1__0_n_0 ;
  wire \resetovrd.reset[3]_i_1__0_n_0 ;
  wire \resetovrd.reset[4]_i_1__0_n_0 ;
  wire \resetovrd.reset[5]_i_1__0_n_0 ;
  wire \resetovrd.reset[6]_i_1__0_n_0 ;
  wire \resetovrd.reset[7]_i_1__0_n_0 ;
  wire \resetovrd.reset[7]_i_2__0_n_0 ;
  wire \resetovrd.reset_cnt[1]_i_1__0_n_0 ;
  wire \resetovrd.reset_cnt[4]_i_1__0_n_0 ;
  wire \resetovrd.reset_cnt[7]_i_1__0_n_0 ;
  wire [7:0]\resetovrd.reset_cnt_reg ;
  wire \resetovrd.reset_reg_n_0_[7] ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire resetovrd_start_reg2;
  wire rst_cpllreset;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg1;
  wire [0:0]rst_idle_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rst_idle_reg2;
  wire rst_idle_reg2_reg_0;
  wire [3:0]rxcdrlock_cnt_reg;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxcdrlock_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxeq_adapt_done_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxresetdone_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxstatus_reg2;
  wire rxsyncallin;
  wire [3:0]rxvalid_cnt_reg;
  wire \rxvalid_cnt_reg[3]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rxvalid_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg1;
  wire [0:0]txcompliance_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txcompliance_reg2;
  wire txcompliance_reg2_reg_1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txelecidle_reg2;
  wire txelecidle_reg2_reg_0;
  wire txphaligndone_reg1_reg;
  wire txphaligndone_reg1_reg_0;
  wire txphinitdone_reg1_reg;
  wire txphinitdone_reg1_reg_0;
  wire txphinitdone_reg1_reg_1;
  wire txphinitdone_reg1_reg_2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire txresetdone_reg2;
  wire user_eyescanreset_1;
  wire user_oobclk_1;
  wire user_resetovrd_1;
  wire user_rxbufreset_1;
  wire user_rxcdrfreqreset_1;
  wire user_rxcdrreset_1;
  wire user_rxdfelpmreset_1;
  wire user_rxpcsreset_1;
  wire user_rxpmareset_1;

  assign out = txelecidle_reg2;
  assign txcompliance_reg2_reg_0 = txcompliance_reg2;
  LUT6 #(
    .INIT(64'hFFFFFFFEAAAAAAAA)) 
    \FSM_onehot_resetovrd.fsm[0]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_eyescanreset_1),
        .I2(user_rxpcsreset_1),
        .I3(user_rxpmareset_1),
        .I4(\FSM_onehot_resetovrd.fsm[0]_i_2__0_n_0 ),
        .I5(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .O(\FSM_onehot_resetovrd.fsm[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \FSM_onehot_resetovrd.fsm[0]_i_2__0 
       (.I0(user_rxbufreset_1),
        .I1(user_rxcdrfreqreset_1),
        .I2(\resetovrd.reset_reg_n_0_[7] ),
        .I3(rxresetdone_reg2),
        .I4(user_rxcdrreset_1),
        .I5(user_rxdfelpmreset_1),
        .O(\FSM_onehot_resetovrd.fsm[0]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \FSM_onehot_resetovrd.fsm[1]_i_1__0 
       (.I0(resetovrd_start_reg2),
        .I1(\FSM_onehot_resetovrd.fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_resetovrd.fsm[1]_i_2__0_n_0 ),
        .I3(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .O(\FSM_onehot_resetovrd.fsm[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1843" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \FSM_onehot_resetovrd.fsm[1]_i_2__0 
       (.I0(user_eyescanreset_1),
        .I1(user_rxpcsreset_1),
        .I2(user_rxpmareset_1),
        .I3(\FSM_onehot_resetovrd.fsm[0]_i_2__0_n_0 ),
        .O(\FSM_onehot_resetovrd.fsm[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \FSM_onehot_resetovrd.fsm[2]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[3] ),
        .I1(\resetovrd.reset_cnt_reg [5]),
        .I2(\resetovrd.reset_cnt_reg [4]),
        .I3(\FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0 ),
        .I4(\resetovrd.reset_cnt_reg [6]),
        .I5(\resetovrd.reset_cnt_reg [7]),
        .O(\FSM_onehot_resetovrd.fsm[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1842" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \FSM_onehot_resetovrd.fsm[2]_i_2__0 
       (.I0(\resetovrd.reset_cnt_reg [3]),
        .I1(\resetovrd.reset_cnt_reg [0]),
        .I2(\resetovrd.reset_cnt_reg [1]),
        .I3(\resetovrd.reset_cnt_reg [2]),
        .O(\FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \FSM_onehot_resetovrd.fsm[3]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0 ),
        .I1(\FSM_onehot_resetovrd.fsm_reg_n_0_[3] ),
        .I2(resetovrd_start_reg2),
        .I3(\FSM_onehot_resetovrd.fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_resetovrd.fsm[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1841" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \FSM_onehot_resetovrd.fsm[3]_i_2__0 
       (.I0(\resetovrd.reset_cnt_reg [7]),
        .I1(\resetovrd.reset_cnt_reg [6]),
        .I2(\FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0 ),
        .I3(\resetovrd.reset_cnt_reg [4]),
        .I4(\resetovrd.reset_cnt_reg [5]),
        .O(\FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_resetovrd.fsm_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_resetovrd.fsm[0]_i_1__0_n_0 ),
        .Q(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010" *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_resetovrd.fsm_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_resetovrd.fsm[1]_i_1__0_n_0 ),
        .Q(\FSM_onehot_resetovrd.fsm_reg_n_0_[1] ),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_resetovrd.fsm_reg[2] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_resetovrd.fsm[2]_i_1__0_n_0 ),
        .Q(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_RESETOVRD:1000,FSM_RESET_INIT:0100,FSM_RESET:0001,FSM_IDLE:0010" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_resetovrd.fsm_reg[3] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_resetovrd.fsm[3]_i_1__0_n_0 ),
        .Q(\FSM_onehot_resetovrd.fsm_reg_n_0_[3] ),
        .R(rst_cpllreset));
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__0 
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .O(txelecidle_reg2_reg_0));
  LUT4 #(
    .INIT(16'h8F88)) 
    \FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0 
       (.I0(txcompliance_reg2),
        .I1(txelecidle_reg2),
        .I2(\FSM_onehot_txsync_fsm.fsm_tx_reg[4] ),
        .I3(p_1_in0_in),
        .O(txcompliance_reg2_reg_1));
  LUT5 #(
    .INIT(32'hFFFFE0FF)) 
    gt_rx_phy_status_q_i_1
       (.I0(rate_idle_reg2),
        .I1(rate_rxsync_reg2),
        .I2(gt_rx_phy_status_q_reg),
        .I3(rst_idle_reg2),
        .I4(rate_done_reg2),
        .O(gt_rx_phy_status_wire_filter));
  LUT6 #(
    .INIT(64'hBFFFBFFFFFFFBFFF)) 
    gt_rxvalid_q_i_3__0
       (.I0(gt_rxvalid_q_i_5__0_n_0),
        .I1(gt_rxvalid_1),
        .I2(rate_idle_reg2),
        .I3(rst_idle_reg2),
        .I4(gt_rx_elec_idle_wire_filter),
        .I5(gt_rxvalid_q_reg),
        .O(\gtp_channel.gtpe2_channel_i ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    gt_rxvalid_q_i_5__0
       (.I0(rxvalid_cnt_reg[3]),
        .I1(rxvalid_cnt_reg[0]),
        .I2(rxvalid_cnt_reg[1]),
        .I3(rxvalid_cnt_reg[2]),
        .O(gt_rxvalid_q_i_5__0_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \gtp_channel.gtpe2_channel_i_i_3__0 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[1] ),
        .O(user_resetovrd_1));
  LUT6 #(
    .INIT(64'hF8F8F8F8F8000000)) 
    \gtp_channel.gtpe2_channel_i_i_4 
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .I2(SYNC_RXPHALIGNDONE_S),
        .I3(txphinitdone_reg1_reg_0),
        .I4(txphinitdone_reg1_reg_1),
        .I5(SYNC_RXPHALIGNDONE_M),
        .O(rxsyncallin));
  LUT6 #(
    .INIT(64'hF8F8F8F8F8000000)) 
    \gtp_channel.gtpe2_channel_i_i_5 
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .I2(txphaligndone_reg1_reg),
        .I3(txphinitdone_reg1_reg_0),
        .I4(txphinitdone_reg1_reg_1),
        .I5(txphaligndone_reg1_reg_0),
        .O(SYNC_TXPHALIGNDONE));
  (* SOFT_HLUTNM = "soft_lutpair1849" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oobclk_div.oobclk_cnt[0]_i_1 
       (.I0(oobclk_cnt[0]),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1849" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \oobclk_div.oobclk_cnt[1]_i_1 
       (.I0(oobclk_cnt[0]),
        .I1(oobclk_cnt[1]),
        .O(p_1_in__0[1]));
  FDRE #(
    .INIT(1'b0)) 
    \oobclk_div.oobclk_cnt_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_1_in__0[0]),
        .Q(oobclk_cnt[0]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \oobclk_div.oobclk_cnt_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_1_in__0[1]),
        .Q(oobclk_cnt[1]),
        .R(rst_cpllreset));
  LUT3 #(
    .INIT(8'hB8)) 
    \oobclk_div.oobclk_i_1__0 
       (.I0(oobclk_cnt[1]),
        .I1(pclk_sel_reg2),
        .I2(oobclk_cnt[0]),
        .O(\oobclk_div.oobclk_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \oobclk_div.oobclk_reg 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\oobclk_div.oobclk_i_1__0_n_0 ),
        .Q(user_oobclk_1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE pclk_sel_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(pclk_sel_reg1_reg_0),
        .Q(pclk_sel_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE pclk_sel_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(pclk_sel_reg1),
        .Q(pclk_sel_reg2),
        .R(rst_cpllreset));
  LUT3 #(
    .INIT(8'h04)) 
    phy_rdy_n_int_i_1
       (.I0(rst_idle_reg2),
        .I1(reg_clock_locked),
        .I2(phy_rdy_n_int_reg),
        .O(rst_idle_reg2_reg_0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_done_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(Q[1]),
        .Q(rate_done_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_done_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rate_done_reg1),
        .Q(rate_done_reg2),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_gen3_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_gen3_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_gen3_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rate_gen3_reg1),
        .Q(rate_gen3_reg2),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_idle_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(Q[0]),
        .Q(rate_idle_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_idle_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_rxsync_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_rxsync_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rate_rxsync_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rate_rxsync_reg1),
        .Q(rate_rxsync_reg2),
        .R(SR));
  LUT2 #(
    .INIT(4'h8)) 
    \resetdone_reg1[1]_i_1 
       (.I0(rxresetdone_reg2),
        .I1(txresetdone_reg2),
        .O(D));
  LUT5 #(
    .INIT(32'h00FB00F0)) 
    \resetovrd.reset[0]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0 ),
        .I1(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .I2(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I3(rst_cpllreset),
        .I4(user_rxpmareset_1),
        .O(\resetovrd.reset[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1848" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[1]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxpmareset_1),
        .O(\resetovrd.reset[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1848" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[2]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxcdrreset_1),
        .O(\resetovrd.reset[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1847" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[3]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxcdrfreqreset_1),
        .O(\resetovrd.reset[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1847" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[4]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxdfelpmreset_1),
        .O(\resetovrd.reset[4]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1843" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[5]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_eyescanreset_1),
        .O(\resetovrd.reset[5]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1846" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[6]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxpcsreset_1),
        .O(\resetovrd.reset[6]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hFFF4)) 
    \resetovrd.reset[7]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0 ),
        .I1(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .I2(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I3(rst_cpllreset),
        .O(\resetovrd.reset[7]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1846" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \resetovrd.reset[7]_i_2__0 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[2] ),
        .I1(user_rxbufreset_1),
        .O(\resetovrd.reset[7]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1845" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \resetovrd.reset_cnt[0]_i_1__0 
       (.I0(\resetovrd.reset_cnt_reg [0]),
        .O(reset_cnt0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1845" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \resetovrd.reset_cnt[1]_i_1__0 
       (.I0(\resetovrd.reset_cnt_reg [0]),
        .I1(\resetovrd.reset_cnt_reg [1]),
        .O(\resetovrd.reset_cnt[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1844" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \resetovrd.reset_cnt[2]_i_1__0 
       (.I0(\resetovrd.reset_cnt_reg [0]),
        .I1(\resetovrd.reset_cnt_reg [1]),
        .I2(\resetovrd.reset_cnt_reg [2]),
        .O(reset_cnt0__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1844" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \resetovrd.reset_cnt[3]_i_1__0 
       (.I0(\resetovrd.reset_cnt_reg [2]),
        .I1(\resetovrd.reset_cnt_reg [1]),
        .I2(\resetovrd.reset_cnt_reg [0]),
        .I3(\resetovrd.reset_cnt_reg [3]),
        .O(reset_cnt0__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1842" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \resetovrd.reset_cnt[4]_i_1__0 
       (.I0(\resetovrd.reset_cnt_reg [4]),
        .I1(\resetovrd.reset_cnt_reg [2]),
        .I2(\resetovrd.reset_cnt_reg [1]),
        .I3(\resetovrd.reset_cnt_reg [0]),
        .I4(\resetovrd.reset_cnt_reg [3]),
        .O(\resetovrd.reset_cnt[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \resetovrd.reset_cnt[5]_i_1__0 
       (.I0(\resetovrd.reset_cnt_reg [5]),
        .I1(\resetovrd.reset_cnt_reg [3]),
        .I2(\resetovrd.reset_cnt_reg [0]),
        .I3(\resetovrd.reset_cnt_reg [1]),
        .I4(\resetovrd.reset_cnt_reg [2]),
        .I5(\resetovrd.reset_cnt_reg [4]),
        .O(reset_cnt0__0[5]));
  LUT4 #(
    .INIT(16'hAAA9)) 
    \resetovrd.reset_cnt[6]_i_1__0 
       (.I0(\resetovrd.reset_cnt_reg [6]),
        .I1(\resetovrd.reset_cnt_reg [5]),
        .I2(\resetovrd.reset_cnt_reg [4]),
        .I3(\FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0 ),
        .O(reset_cnt0__0[6]));
  LUT4 #(
    .INIT(16'hF1FF)) 
    \resetovrd.reset_cnt[7]_i_1__0 
       (.I0(\FSM_onehot_resetovrd.fsm_reg_n_0_[0] ),
        .I1(\FSM_onehot_resetovrd.fsm_reg_n_0_[3] ),
        .I2(rst_cpllreset),
        .I3(\FSM_onehot_resetovrd.fsm[3]_i_2__0_n_0 ),
        .O(\resetovrd.reset_cnt[7]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1841" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \resetovrd.reset_cnt[7]_i_2__0 
       (.I0(\resetovrd.reset_cnt_reg [7]),
        .I1(\resetovrd.reset_cnt_reg [6]),
        .I2(\FSM_onehot_resetovrd.fsm[2]_i_2__0_n_0 ),
        .I3(\resetovrd.reset_cnt_reg [4]),
        .I4(\resetovrd.reset_cnt_reg [5]),
        .O(reset_cnt0__0[7]));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0__0[0]),
        .Q(\resetovrd.reset_cnt_reg [0]),
        .S(\resetovrd.reset_cnt[7]_i_1__0_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\resetovrd.reset_cnt[1]_i_1__0_n_0 ),
        .Q(\resetovrd.reset_cnt_reg [1]),
        .S(\resetovrd.reset_cnt[7]_i_1__0_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[2] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0__0[2]),
        .Q(\resetovrd.reset_cnt_reg [2]),
        .S(\resetovrd.reset_cnt[7]_i_1__0_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[3] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0__0[3]),
        .Q(\resetovrd.reset_cnt_reg [3]),
        .S(\resetovrd.reset_cnt[7]_i_1__0_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[4] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\resetovrd.reset_cnt[4]_i_1__0_n_0 ),
        .Q(\resetovrd.reset_cnt_reg [4]),
        .S(\resetovrd.reset_cnt[7]_i_1__0_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[5] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0__0[5]),
        .Q(\resetovrd.reset_cnt_reg [5]),
        .S(\resetovrd.reset_cnt[7]_i_1__0_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \resetovrd.reset_cnt_reg[6] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0__0[6]),
        .Q(\resetovrd.reset_cnt_reg [6]),
        .S(\resetovrd.reset_cnt[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_cnt_reg[7] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(reset_cnt0__0[7]),
        .Q(\resetovrd.reset_cnt_reg [7]),
        .R(\resetovrd.reset_cnt[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(\resetovrd.reset[0]_i_1__0_n_0 ),
        .Q(user_rxpmareset_1),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1__0_n_0 ),
        .D(\resetovrd.reset[1]_i_1__0_n_0 ),
        .Q(user_rxcdrreset_1),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[2] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1__0_n_0 ),
        .D(\resetovrd.reset[2]_i_1__0_n_0 ),
        .Q(user_rxcdrfreqreset_1),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[3] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1__0_n_0 ),
        .D(\resetovrd.reset[3]_i_1__0_n_0 ),
        .Q(user_rxdfelpmreset_1),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[4] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1__0_n_0 ),
        .D(\resetovrd.reset[4]_i_1__0_n_0 ),
        .Q(user_eyescanreset_1),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[5] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1__0_n_0 ),
        .D(\resetovrd.reset[5]_i_1__0_n_0 ),
        .Q(user_rxpcsreset_1),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[6] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1__0_n_0 ),
        .D(\resetovrd.reset[6]_i_1__0_n_0 ),
        .Q(user_rxbufreset_1),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \resetovrd.reset_reg[7] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(\resetovrd.reset[7]_i_1__0_n_0 ),
        .D(\resetovrd.reset[7]_i_2__0_n_0 ),
        .Q(\resetovrd.reset_reg_n_0_[7] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE resetovrd_start_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(1'b0),
        .Q(resetovrd_start_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE resetovrd_start_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(resetovrd_start_reg1),
        .Q(resetovrd_start_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rst_idle_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rst_idle_reg1_reg_0),
        .Q(rst_idle_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rst_idle_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(SR));
  LUT5 #(
    .INIT(32'h8A0A0A0A)) 
    \rxcdrlock_cnt[0]_i_1 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg[2]),
        .I2(rxcdrlock_cnt_reg[0]),
        .I3(rxcdrlock_cnt_reg[1]),
        .I4(rxcdrlock_cnt_reg[3]),
        .O(p_0_in__4[0]));
  LUT5 #(
    .INIT(32'hA8282828)) 
    \rxcdrlock_cnt[1]_i_1 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg[0]),
        .I2(rxcdrlock_cnt_reg[1]),
        .I3(rxcdrlock_cnt_reg[2]),
        .I4(rxcdrlock_cnt_reg[3]),
        .O(p_0_in__4[1]));
  LUT5 #(
    .INIT(32'hBCCC0000)) 
    \rxcdrlock_cnt[2]_i_1 
       (.I0(rxcdrlock_cnt_reg[3]),
        .I1(rxcdrlock_cnt_reg[2]),
        .I2(rxcdrlock_cnt_reg[1]),
        .I3(rxcdrlock_cnt_reg[0]),
        .I4(rxcdrlock_reg2),
        .O(p_0_in__4[2]));
  LUT5 #(
    .INIT(32'hA8888888)) 
    \rxcdrlock_cnt[3]_i_1 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg[3]),
        .I2(rxcdrlock_cnt_reg[1]),
        .I3(rxcdrlock_cnt_reg[0]),
        .I4(rxcdrlock_cnt_reg[2]),
        .O(p_0_in__4[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[0]),
        .Q(rxcdrlock_cnt_reg[0]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[1]),
        .Q(rxcdrlock_cnt_reg[1]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[2] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[2]),
        .Q(rxcdrlock_cnt_reg[2]),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[3] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[3]),
        .Q(rxcdrlock_cnt_reg[3]),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h80000000)) 
    \rxcdrlock_reg1[1]_i_1 
       (.I0(gt_rxcdrlock_1),
        .I1(rxcdrlock_cnt_reg[3]),
        .I2(rxcdrlock_cnt_reg[1]),
        .I3(rxcdrlock_cnt_reg[0]),
        .I4(rxcdrlock_cnt_reg[2]),
        .O(SYNC_RXCDRLOCK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(gt_rxcdrlock_1),
        .Q(rxcdrlock_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_adapt_done_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(eq_rxeq_adapt_done_1),
        .Q(rxeq_adapt_done_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxeq_adapt_done_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rxeq_adapt_done_reg1),
        .Q(rxeq_adapt_done_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxresetdone_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(gt_rxresetdone_1),
        .Q(rxresetdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxresetdone_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxstatus_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(RXSTATUS),
        .Q(rxstatus_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxstatus_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rxstatus_reg1),
        .Q(rxstatus_reg2),
        .R(SR));
  LUT6 #(
    .INIT(64'h8080000000FF0000)) 
    \rxvalid_cnt[0]_i_1__0 
       (.I0(rxvalid_cnt_reg[3]),
        .I1(rxvalid_cnt_reg[1]),
        .I2(rxvalid_cnt_reg[2]),
        .I3(rxstatus_reg2),
        .I4(rxvalid_reg2),
        .I5(rxvalid_cnt_reg[0]),
        .O(p_0_in__5[0]));
  LUT6 #(
    .INIT(64'h808000F000F00000)) 
    \rxvalid_cnt[1]_i_1__0 
       (.I0(rxvalid_cnt_reg[3]),
        .I1(rxvalid_cnt_reg[2]),
        .I2(rxvalid_reg2),
        .I3(rxstatus_reg2),
        .I4(rxvalid_cnt_reg[1]),
        .I5(rxvalid_cnt_reg[0]),
        .O(p_0_in__5[1]));
  LUT6 #(
    .INIT(64'h80000000BFC00000)) 
    \rxvalid_cnt[2]_i_1__0 
       (.I0(rxvalid_cnt_reg[3]),
        .I1(rxvalid_cnt_reg[0]),
        .I2(rxvalid_cnt_reg[1]),
        .I3(rxvalid_cnt_reg[2]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__5[2]));
  LUT6 #(
    .INIT(64'hC440404040404040)) 
    \rxvalid_cnt[3]_i_1__0 
       (.I0(rxstatus_reg2),
        .I1(rxvalid_reg2),
        .I2(rxvalid_cnt_reg[3]),
        .I3(rxvalid_cnt_reg[0]),
        .I4(rxvalid_cnt_reg[1]),
        .I5(rxvalid_cnt_reg[2]),
        .O(p_0_in__5[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[0] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__5[0]),
        .Q(rxvalid_cnt_reg[0]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[1] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__5[1]),
        .Q(rxvalid_cnt_reg[1]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[2] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__5[2]),
        .Q(rxvalid_cnt_reg[2]),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[3] 
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(p_0_in__5[3]),
        .Q(rxvalid_cnt_reg[3]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxvalid_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(gt_rxvalid_1),
        .Q(rxvalid_reg1),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rxvalid_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(rxvalid_reg1),
        .Q(rxvalid_reg2),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txcompliance_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(txcompliance_reg1_reg_0),
        .Q(txcompliance_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txcompliance_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(txcompliance_reg1),
        .Q(txcompliance_reg2),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txelecidle_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(pipe_tx1_elec_idle_gt),
        .Q(txelecidle_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txelecidle_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(txelecidle_reg1),
        .Q(txelecidle_reg2),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'hF8F8F8F8F8000000)) 
    txphinitdone_reg1_i_1
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .I2(txphinitdone_reg1_reg),
        .I3(txphinitdone_reg1_reg_0),
        .I4(txphinitdone_reg1_reg_1),
        .I5(txphinitdone_reg1_reg_2),
        .O(SYNC_TXPHINITDONE));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txresetdone_reg1_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(gt_txresetdone_1),
        .Q(txresetdone_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE txresetdone_reg2_reg
       (.C(\rxvalid_cnt_reg[3]_0 ),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(rst_cpllreset));
endmodule

module xdma_0_pcie2_ip_pipe_wrapper
   (CLK,
    \userclk1_i1.usrclk1_i1 ,
    pci_exp_txn,
    pci_exp_txp,
    pipe_rx0_chanisaligned_gt,
    gt_rx_elec_idle_wire_filter,
    gt_rx_data_wire_filter,
    gt_rx_data_k_wire_filter,
    pipe_rx1_chanisaligned_gt,
    sys_rst_n_0,
    mmcm_i,
    \gtp_channel.gtpe2_channel_i ,
    \gtp_channel.gtpe2_channel_i_0 ,
    \gtp_channel.gtpe2_channel_i_1 ,
    \gtp_channel.gtpe2_channel_i_2 ,
    rst_idle_reg2_reg,
    gt_rx_phy_status_wire_filter,
    sys_clk,
    pipe_tx0_elec_idle_gt,
    TXCHARDISPMODE,
    pci_exp_rxn,
    pci_exp_rxp,
    pipe_rx0_polarity_gt,
    pipe_tx_deemph_gt,
    pipe_tx_rcvr_det_gt,
    Q,
    \gtp_channel.gtpe2_channel_i_3 ,
    \gtp_channel.gtpe2_channel_i_4 ,
    \gtp_channel.gtpe2_channel_i_5 ,
    pipe_tx1_elec_idle_gt,
    txcompliance_reg1_reg,
    pipe_rx1_polarity_gt,
    \gtp_channel.gtpe2_channel_i_6 ,
    \gtp_channel.gtpe2_channel_i_7 ,
    \gtp_channel.gtpe2_channel_i_8 ,
    sys_rst_n,
    \gt_rx_status_q_reg[0] ,
    \gt_rx_status_q_reg[0]_0 ,
    \gt_rx_status_q_reg[2] ,
    reg_clock_locked,
    D,
    int_pclk_sel_slave);
  output CLK;
  output \userclk1_i1.usrclk1_i1 ;
  output [1:0]pci_exp_txn;
  output [1:0]pci_exp_txp;
  output pipe_rx0_chanisaligned_gt;
  output [1:0]gt_rx_elec_idle_wire_filter;
  output [31:0]gt_rx_data_wire_filter;
  output [3:0]gt_rx_data_k_wire_filter;
  output pipe_rx1_chanisaligned_gt;
  output sys_rst_n_0;
  output mmcm_i;
  output \gtp_channel.gtpe2_channel_i ;
  output [2:0]\gtp_channel.gtpe2_channel_i_0 ;
  output [2:0]\gtp_channel.gtpe2_channel_i_1 ;
  output \gtp_channel.gtpe2_channel_i_2 ;
  output rst_idle_reg2_reg;
  output [1:0]gt_rx_phy_status_wire_filter;
  input sys_clk;
  input pipe_tx0_elec_idle_gt;
  input [0:0]TXCHARDISPMODE;
  input [1:0]pci_exp_rxn;
  input [1:0]pci_exp_rxp;
  input pipe_rx0_polarity_gt;
  input pipe_tx_deemph_gt;
  input pipe_tx_rcvr_det_gt;
  input [1:0]Q;
  input [2:0]\gtp_channel.gtpe2_channel_i_3 ;
  input [15:0]\gtp_channel.gtpe2_channel_i_4 ;
  input [1:0]\gtp_channel.gtpe2_channel_i_5 ;
  input pipe_tx1_elec_idle_gt;
  input [0:0]txcompliance_reg1_reg;
  input pipe_rx1_polarity_gt;
  input [1:0]\gtp_channel.gtpe2_channel_i_6 ;
  input [15:0]\gtp_channel.gtpe2_channel_i_7 ;
  input [1:0]\gtp_channel.gtpe2_channel_i_8 ;
  input sys_rst_n;
  input \gt_rx_status_q_reg[0] ;
  input \gt_rx_status_q_reg[0]_0 ;
  input \gt_rx_status_q_reg[2] ;
  input reg_clock_locked;
  input [0:0]D;
  input [1:0]int_pclk_sel_slave;

  wire CLK;
  wire [0:0]D;
  wire DRP_START0;
  wire DRP_START00_out;
  wire DRP_X160;
  wire DRP_X1602_out;
  wire [1:0]Q;
  wire SYNC_TXSYNC_START0;
  wire SYNC_TXSYNC_START01_out;
  wire [0:0]TXCHARDISPMODE;
  wire drp_done_0;
  wire drp_done_1;
  wire eq_rxeq_adapt_done_0;
  wire eq_rxeq_adapt_done_1;
  wire [6:0]eq_txeq_maincursor_0;
  wire [6:0]eq_txeq_maincursor_7;
  wire [4:0]eq_txeq_postcursor_0;
  wire [4:0]eq_txeq_postcursor_5;
  wire [4:0]eq_txeq_precursor_0;
  wire [4:0]eq_txeq_precursor_5;
  wire gt_cpllpdrefclk;
  wire gt_phystatus_0;
  wire gt_phystatus_1;
  wire [3:0]gt_rx_data_k_wire_filter;
  wire [31:0]gt_rx_data_wire_filter;
  wire [1:0]gt_rx_elec_idle_wire_filter;
  wire [1:0]gt_rx_phy_status_wire_filter;
  wire \gt_rx_status_q_reg[0] ;
  wire \gt_rx_status_q_reg[0]_0 ;
  wire \gt_rx_status_q_reg[2] ;
  wire gt_rxcdrlock_0;
  wire gt_rxcdrlock_1;
  wire [3:0]\gt_rxchbondi[1]_0 ;
  wire gt_rxratedone_0;
  wire gt_rxratedone_1;
  wire gt_rxresetdone_0;
  wire gt_rxresetdone_1;
  wire gt_rxsyncout_0;
  wire gt_rxvalid_0;
  wire gt_rxvalid_1;
  wire gt_txratedone_0;
  wire gt_txratedone_1;
  wire gt_txresetdone_0;
  wire gt_txresetdone_1;
  wire gt_txsyncdone_0;
  wire gt_txsyncdone_1;
  wire gt_txsyncout_0;
  wire \gtp_channel.gtpe2_channel_i ;
  wire [2:0]\gtp_channel.gtpe2_channel_i_0 ;
  wire [2:0]\gtp_channel.gtpe2_channel_i_1 ;
  wire \gtp_channel.gtpe2_channel_i_2 ;
  wire [2:0]\gtp_channel.gtpe2_channel_i_3 ;
  wire [15:0]\gtp_channel.gtpe2_channel_i_4 ;
  wire [1:0]\gtp_channel.gtpe2_channel_i_5 ;
  wire [1:0]\gtp_channel.gtpe2_channel_i_6 ;
  wire [15:0]\gtp_channel.gtpe2_channel_i_7 ;
  wire [1:0]\gtp_channel.gtpe2_channel_i_8 ;
  wire \gtp_pipe_reset.gtp_pipe_reset_i_n_0 ;
  wire \gtp_pipe_reset.gtp_pipe_reset_i_n_11 ;
  wire [1:0]int_pclk_sel_slave;
  wire mmcm_i;
  wire p_0_in4_in;
  wire p_0_in4_in_1;
  wire p_1_in;
  wire p_1_in0_in;
  wire p_1_in0_in_0;
  wire p_1_in5_in;
  wire p_1_in5_in_2;
  wire [1:0]pci_exp_rxn;
  wire [1:0]pci_exp_rxp;
  wire [1:0]pci_exp_txn;
  wire [1:0]pci_exp_txp;
  wire \pipe_clock_int.pipe_clock_i_n_1 ;
  wire \pipe_clock_int.pipe_clock_i_n_3 ;
  wire \pipe_lane[0].gt_wrapper_i_n_0 ;
  wire \pipe_lane[0].gt_wrapper_i_n_11 ;
  wire \pipe_lane[0].gt_wrapper_i_n_14 ;
  wire \pipe_lane[0].gt_wrapper_i_n_15 ;
  wire \pipe_lane[0].gt_wrapper_i_n_16 ;
  wire \pipe_lane[0].gt_wrapper_i_n_21 ;
  wire \pipe_lane[0].gt_wrapper_i_n_22 ;
  wire \pipe_lane[0].gt_wrapper_i_n_23 ;
  wire \pipe_lane[0].gt_wrapper_i_n_24 ;
  wire \pipe_lane[0].gt_wrapper_i_n_25 ;
  wire \pipe_lane[0].gt_wrapper_i_n_26 ;
  wire \pipe_lane[0].gt_wrapper_i_n_27 ;
  wire \pipe_lane[0].gt_wrapper_i_n_28 ;
  wire \pipe_lane[0].gt_wrapper_i_n_29 ;
  wire \pipe_lane[0].gt_wrapper_i_n_30 ;
  wire \pipe_lane[0].gt_wrapper_i_n_31 ;
  wire \pipe_lane[0].gt_wrapper_i_n_32 ;
  wire \pipe_lane[0].gt_wrapper_i_n_33 ;
  wire \pipe_lane[0].gt_wrapper_i_n_34 ;
  wire \pipe_lane[0].gt_wrapper_i_n_35 ;
  wire \pipe_lane[0].gt_wrapper_i_n_36 ;
  wire \pipe_lane[0].gt_wrapper_i_n_37 ;
  wire \pipe_lane[0].gt_wrapper_i_n_7 ;
  wire \pipe_lane[0].gt_wrapper_i_n_8 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_1 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_10 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_11 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_12 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_13 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_14 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_15 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_16 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_17 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_18 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_19 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_2 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_3 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_4 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_5 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_6 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_7 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_8 ;
  wire \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_9 ;
  wire \pipe_lane[0].gtp_pipe_rate.gtp_pipe_rate_i_n_0 ;
  wire \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1 ;
  wire \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2 ;
  wire \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_3 ;
  wire \pipe_lane[0].pipe_sync_i_n_1 ;
  wire \pipe_lane[0].pipe_sync_i_n_3 ;
  wire \pipe_lane[0].pipe_sync_i_n_4 ;
  wire \pipe_lane[0].pipe_sync_i_n_5 ;
  wire \pipe_lane[0].pipe_sync_i_n_6 ;
  wire \pipe_lane[0].pipe_user_i_n_15 ;
  wire \pipe_lane[0].pipe_user_i_n_16 ;
  wire \pipe_lane[0].pipe_user_i_n_17 ;
  wire \pipe_lane[0].pipe_user_i_n_2 ;
  wire \pipe_lane[1].gt_wrapper_i_n_0 ;
  wire \pipe_lane[1].gt_wrapper_i_n_12 ;
  wire \pipe_lane[1].gt_wrapper_i_n_14 ;
  wire \pipe_lane[1].gt_wrapper_i_n_15 ;
  wire \pipe_lane[1].gt_wrapper_i_n_16 ;
  wire \pipe_lane[1].gt_wrapper_i_n_20 ;
  wire \pipe_lane[1].gt_wrapper_i_n_21 ;
  wire \pipe_lane[1].gt_wrapper_i_n_22 ;
  wire \pipe_lane[1].gt_wrapper_i_n_23 ;
  wire \pipe_lane[1].gt_wrapper_i_n_24 ;
  wire \pipe_lane[1].gt_wrapper_i_n_25 ;
  wire \pipe_lane[1].gt_wrapper_i_n_26 ;
  wire \pipe_lane[1].gt_wrapper_i_n_27 ;
  wire \pipe_lane[1].gt_wrapper_i_n_28 ;
  wire \pipe_lane[1].gt_wrapper_i_n_29 ;
  wire \pipe_lane[1].gt_wrapper_i_n_30 ;
  wire \pipe_lane[1].gt_wrapper_i_n_31 ;
  wire \pipe_lane[1].gt_wrapper_i_n_32 ;
  wire \pipe_lane[1].gt_wrapper_i_n_33 ;
  wire \pipe_lane[1].gt_wrapper_i_n_34 ;
  wire \pipe_lane[1].gt_wrapper_i_n_35 ;
  wire \pipe_lane[1].gt_wrapper_i_n_36 ;
  wire \pipe_lane[1].gt_wrapper_i_n_6 ;
  wire \pipe_lane[1].gt_wrapper_i_n_8 ;
  wire \pipe_lane[1].gt_wrapper_i_n_9 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_1 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_10 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_11 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_12 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_13 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_14 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_15 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_16 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_17 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_18 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_19 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_2 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_3 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_4 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_5 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_6 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_7 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_8 ;
  wire \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_9 ;
  wire \pipe_lane[1].gtp_pipe_rate.gtp_pipe_rate_i_n_0 ;
  wire \pipe_lane[1].pipe_sync_i_n_1 ;
  wire \pipe_lane[1].pipe_sync_i_n_2 ;
  wire \pipe_lane[1].pipe_sync_i_n_3 ;
  wire \pipe_lane[1].pipe_sync_i_n_4 ;
  wire \pipe_lane[1].pipe_user_i_n_15 ;
  wire \pipe_lane[1].pipe_user_i_n_18 ;
  wire \pipe_lane[1].pipe_user_i_n_19 ;
  wire pipe_rx0_chanisaligned_gt;
  wire pipe_rx0_polarity_gt;
  wire pipe_rx1_chanisaligned_gt;
  wire pipe_rx1_polarity_gt;
  wire pipe_tx0_elec_idle_gt;
  wire pipe_tx1_elec_idle_gt;
  wire pipe_tx_deemph_gt;
  wire pipe_tx_rcvr_det_gt;
  wire qdrp_done;
  wire \qpll_wrapper_i/PLL0RESET0 ;
  wire \qpll_wrapper_i/cpllrst ;
  wire qrst_drp_start;
  wire rate_done_0;
  wire rate_done_1;
  wire rate_idle_0;
  wire rate_idle_1;
  wire [0:0]rate_rate_0;
  wire [0:0]rate_rate_3;
  wire rate_txsync_start_0;
  wire rate_txsync_start_1;
  wire reg_clock_locked;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire reset_n_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire reset_n_reg2;
  wire rst_cpllreset;
  wire rst_dclk_reset;
  wire rst_drp_start;
  wire rst_drp_x16;
  wire rst_gtreset;
  wire rst_idle_reg2_reg;
  wire rst_rxusrclk_reset;
  wire rst_userrdy;
  wire rxdlysresetdone_1;
  wire rxsyncallin;
  wire sync_txdlyen_0;
  wire sync_txsync_done_0;
  wire sync_txsync_done_1;
  wire sys_clk;
  wire sys_rst_n;
  wire sys_rst_n_0;
  wire [0:0]txcompliance_reg1_reg;
  wire txdlysresetdone_1;
  wire txsyncallin;
  wire user_eyescanreset_0;
  wire user_eyescanreset_1;
  wire user_oobclk_0;
  wire user_oobclk_1;
  wire [1:0]user_resetdone;
  wire user_resetovrd_0;
  wire user_resetovrd_1;
  wire user_rxbufreset_0;
  wire user_rxbufreset_1;
  wire user_rxcdrfreqreset_0;
  wire user_rxcdrfreqreset_1;
  wire user_rxcdrlock_0;
  wire user_rxcdrlock_1;
  wire user_rxcdrreset_0;
  wire user_rxcdrreset_1;
  wire user_rxpcsreset_0;
  wire user_rxpcsreset_1;
  wire user_rxpmareset_0;
  wire user_rxpmareset_1;
  wire \userclk1_i1.usrclk1_i1 ;

  (* box_type = "PRIMITIVE" *) 
  BUFG cpllpd_refclk_inst
       (.I(sys_clk),
        .O(gt_cpllpdrefclk));
  xdma_0_pcie2_ip_gtp_pipe_reset \gtp_pipe_reset.gtp_pipe_reset_i 
       (.CLK(\pipe_clock_int.pipe_clock_i_n_1 ),
        .D(user_resetdone),
        .\FSM_onehot_fsm_reg[11]_0 (SYNC_TXSYNC_START01_out),
        .\FSM_onehot_fsm_reg[1]_0 (\gtp_pipe_reset.gtp_pipe_reset_i_n_11 ),
        .PLL0RESET0(\qpll_wrapper_i/PLL0RESET0 ),
        .Q({rate_txsync_start_0,rate_idle_0}),
        .QRST_QPLLLOCK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1 ),
        .SR(\gtp_pipe_reset.gtp_pipe_reset_i_n_0 ),
        .SYNC_MMCM_LOCK(\pipe_clock_int.pipe_clock_i_n_3 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START0),
        .\cfg_wait_cnt_reg[5]_0 (CLK),
        .cpllrst(\qpll_wrapper_i/cpllrst ),
        .\drp_done_reg1_reg[1]_0 ({drp_done_1,drp_done_0}),
        .out(reset_n_reg2),
        .\phystatus_reg1_reg[1]_0 ({gt_phystatus_1,gt_phystatus_0}),
        .rst_cpllreset(rst_cpllreset),
        .rst_dclk_reset(rst_dclk_reset),
        .rst_drp_start(rst_drp_start),
        .rst_drp_x16(rst_drp_x16),
        .rst_gtreset(rst_gtreset),
        .rst_userrdy(rst_userrdy),
        .\rxcdrlock_reg1_reg[1]_0 ({user_rxcdrlock_1,user_rxcdrlock_0}),
        .\rxpmaresetdone_reg1_reg[1]_0 ({\pipe_lane[1].gt_wrapper_i_n_9 ,\pipe_lane[0].gt_wrapper_i_n_8 }),
        .rxusrclk_rst_reg2_reg_0(rst_rxusrclk_reset),
        .\txsync_done_reg1_reg[1]_0 ({sync_txsync_done_1,sync_txsync_done_0}),
        .txsync_start_reg1_reg({rate_txsync_start_1,rate_idle_1}));
  xdma_0_pcie2_ip_pipe_clock \pipe_clock_int.pipe_clock_i 
       (.CLK(\pipe_clock_int.pipe_clock_i_n_1 ),
        .SYNC_MMCM_LOCK(\pipe_clock_int.pipe_clock_i_n_3 ),
        .int_pclk_sel_slave(int_pclk_sel_slave),
        .mmcm_i_0(mmcm_i),
        .\pclk_i1_bufgctrl.pclk_i1_0 (CLK),
        .\pclk_sel_reg1_reg[0]_0 (\pipe_lane[0].gtp_pipe_rate.gtp_pipe_rate_i_n_0 ),
        .\pclk_sel_reg1_reg[1]_0 (\pipe_lane[1].gtp_pipe_rate.gtp_pipe_rate_i_n_0 ),
        .\txoutclk_i.txoutclk_i_0 (\pipe_lane[0].gt_wrapper_i_n_14 ),
        .\userclk1_i1.usrclk1_i1_0 (\userclk1_i1.usrclk1_i1 ));
  xdma_0_pcie2_ip_gt_wrapper \pipe_lane[0].gt_wrapper_i 
       (.CLK(\pipe_clock_int.pipe_clock_i_n_1 ),
        .D({\pipe_lane[0].gt_wrapper_i_n_21 ,\pipe_lane[0].gt_wrapper_i_n_22 ,\pipe_lane[0].gt_wrapper_i_n_23 ,\pipe_lane[0].gt_wrapper_i_n_24 ,\pipe_lane[0].gt_wrapper_i_n_25 ,\pipe_lane[0].gt_wrapper_i_n_26 ,\pipe_lane[0].gt_wrapper_i_n_27 ,\pipe_lane[0].gt_wrapper_i_n_28 ,\pipe_lane[0].gt_wrapper_i_n_29 ,\pipe_lane[0].gt_wrapper_i_n_30 ,\pipe_lane[0].gt_wrapper_i_n_31 ,\pipe_lane[0].gt_wrapper_i_n_32 ,\pipe_lane[0].gt_wrapper_i_n_33 ,\pipe_lane[0].gt_wrapper_i_n_34 ,\pipe_lane[0].gt_wrapper_i_n_35 ,\pipe_lane[0].gt_wrapper_i_n_36 }),
        .DRPADDR(\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_18 ),
        .DRPDI({\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_2 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_3 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_4 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_5 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_6 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_7 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_8 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_9 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_10 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_11 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_12 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_13 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_14 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_15 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_16 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_17 }),
        .Q({\pipe_lane[0].pipe_sync_i_n_4 ,\pipe_lane[0].pipe_sync_i_n_5 ,\pipe_lane[0].pipe_sync_i_n_6 }),
        .RXCHBONDO(\gt_rxchbondi[1]_0 ),
        .RXRATE(rate_rate_0),
        .RXSTATUS(\pipe_lane[0].gt_wrapper_i_n_37 ),
        .SYNC_RXDLYSRESETDONE(rxdlysresetdone_1),
        .SYNC_RXPHALIGNDONE_M(\pipe_lane[0].gt_wrapper_i_n_7 ),
        .SYNC_RXSYNCDONE(\pipe_lane[0].gt_wrapper_i_n_11 ),
        .SYNC_TXDLYSRESETDONE(txdlysresetdone_1),
        .SYNC_TXPHALIGNDONE(txsyncallin),
        .SYNC_TXSYNCDONE(gt_txsyncdone_0),
        .TXCHARDISPMODE(TXCHARDISPMODE),
        .TXMAINCURSOR(eq_txeq_maincursor_0),
        .TXPOSTCURSOR(eq_txeq_postcursor_0),
        .TXPRECURSOR(eq_txeq_precursor_0),
        .gt_rx_data_k_wire_filter(gt_rx_data_k_wire_filter[1:0]),
        .gt_rx_data_wire_filter(gt_rx_data_wire_filter[15:0]),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[0]),
        .\gt_rx_status_q_reg[0] (\gt_rx_status_q_reg[0] ),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2] ),
        .gt_rxcdrlock_0(gt_rxcdrlock_0),
        .gt_rxratedone_0(gt_rxratedone_0),
        .gt_rxresetdone_0(gt_rxresetdone_0),
        .gt_rxsyncout_0(gt_rxsyncout_0),
        .gt_rxvalid_0(gt_rxvalid_0),
        .gt_txratedone_0(gt_txratedone_0),
        .gt_txresetdone_0(gt_txresetdone_0),
        .gt_txsyncout_0(gt_txsyncout_0),
        .\gtp_channel.gtpe2_channel_i_0 (\pipe_lane[0].gt_wrapper_i_n_0 ),
        .\gtp_channel.gtpe2_channel_i_1 (gt_phystatus_0),
        .\gtp_channel.gtpe2_channel_i_10 (\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_3 ),
        .\gtp_channel.gtpe2_channel_i_11 (CLK),
        .\gtp_channel.gtpe2_channel_i_12 (Q),
        .\gtp_channel.gtpe2_channel_i_13 (\gtp_channel.gtpe2_channel_i_3 ),
        .\gtp_channel.gtpe2_channel_i_14 (\gtp_channel.gtpe2_channel_i_4 ),
        .\gtp_channel.gtpe2_channel_i_15 (\gtp_channel.gtpe2_channel_i_5 ),
        .\gtp_channel.gtpe2_channel_i_2 (\pipe_lane[0].gt_wrapper_i_n_8 ),
        .\gtp_channel.gtpe2_channel_i_3 (\pipe_lane[0].gt_wrapper_i_n_14 ),
        .\gtp_channel.gtpe2_channel_i_4 (\pipe_lane[0].gt_wrapper_i_n_15 ),
        .\gtp_channel.gtpe2_channel_i_5 (\pipe_lane[0].gt_wrapper_i_n_16 ),
        .\gtp_channel.gtpe2_channel_i_6 (\gtp_channel.gtpe2_channel_i_1 ),
        .\gtp_channel.gtpe2_channel_i_7 (\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_1 ),
        .\gtp_channel.gtpe2_channel_i_8 (\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_19 ),
        .\gtp_channel.gtpe2_channel_i_9 (\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2 ),
        .pci_exp_rxn(pci_exp_rxn[0]),
        .pci_exp_rxp(pci_exp_rxp[0]),
        .pci_exp_txn(pci_exp_txn[0]),
        .pci_exp_txp(pci_exp_txp[0]),
        .pipe_rx0_chanisaligned_gt(pipe_rx0_chanisaligned_gt),
        .pipe_rx0_polarity_gt(pipe_rx0_polarity_gt),
        .pipe_tx0_elec_idle_gt(pipe_tx0_elec_idle_gt),
        .pipe_tx_deemph_gt(pipe_tx_deemph_gt),
        .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt),
        .rst_gtreset(rst_gtreset),
        .rst_userrdy(rst_userrdy),
        .rxdlysresetdone_reg1_reg(\pipe_lane[1].gt_wrapper_i_n_6 ),
        .rxsyncallin(rxsyncallin),
        .sync_txdlyen_0(sync_txdlyen_0),
        .txdlysresetdone_reg1_reg(\pipe_lane[1].gt_wrapper_i_n_14 ),
        .user_eyescanreset_0(user_eyescanreset_0),
        .user_oobclk_0(user_oobclk_0),
        .user_resetovrd_0(user_resetovrd_0),
        .user_rxbufreset_0(user_rxbufreset_0),
        .user_rxcdrfreqreset_0(user_rxcdrfreqreset_0),
        .user_rxcdrreset_0(user_rxcdrreset_0),
        .user_rxpcsreset_0(user_rxpcsreset_0),
        .user_rxpmareset_0(user_rxpmareset_0));
  xdma_0_pcie2_ip_gtp_pipe_drp \pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i 
       (.CLK(\pipe_clock_int.pipe_clock_i_n_1 ),
        .D({\pipe_lane[0].gt_wrapper_i_n_21 ,\pipe_lane[0].gt_wrapper_i_n_22 ,\pipe_lane[0].gt_wrapper_i_n_23 ,\pipe_lane[0].gt_wrapper_i_n_24 ,\pipe_lane[0].gt_wrapper_i_n_25 ,\pipe_lane[0].gt_wrapper_i_n_26 ,\pipe_lane[0].gt_wrapper_i_n_27 ,\pipe_lane[0].gt_wrapper_i_n_28 ,\pipe_lane[0].gt_wrapper_i_n_29 ,\pipe_lane[0].gt_wrapper_i_n_30 ,\pipe_lane[0].gt_wrapper_i_n_31 ,\pipe_lane[0].gt_wrapper_i_n_32 ,\pipe_lane[0].gt_wrapper_i_n_33 ,\pipe_lane[0].gt_wrapper_i_n_34 ,\pipe_lane[0].gt_wrapper_i_n_35 ,\pipe_lane[0].gt_wrapper_i_n_36 }),
        .DRPADDR(\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_18 ),
        .DRPDI({\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_2 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_3 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_4 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_5 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_6 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_7 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_8 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_9 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_10 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_11 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_12 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_13 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_14 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_15 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_16 ,\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_17 }),
        .DRP_START00_out(DRP_START00_out),
        .DRP_X160(DRP_X160),
        .done_reg_0(drp_done_0),
        .\fsm_reg[1]_0 (\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_1 ),
        .\fsm_reg[1]_1 (\pipe_lane[0].gtp_pipe_drp.gtp_pipe_drp_i_n_19 ),
        .rdy_reg1_reg_0(\pipe_lane[0].gt_wrapper_i_n_0 ),
        .rst_dclk_reset(rst_dclk_reset));
  xdma_0_pcie2_ip_gtp_pipe_rate \pipe_lane[0].gtp_pipe_rate.gtp_pipe_rate_i 
       (.D(D),
        .DRP_START00_out(DRP_START00_out),
        .DRP_X160(DRP_X160),
        .Q({rate_txsync_start_0,rate_done_0,rate_idle_0}),
        .RXRATE(rate_rate_0),
        .drp_done_reg1_reg_0(drp_done_0),
        .gt_rxratedone_0(gt_rxratedone_0),
        .gt_txratedone_0(gt_txratedone_0),
        .pclk_sel_reg_0(\pipe_lane[0].gtp_pipe_rate.gtp_pipe_rate_i_n_0 ),
        .phystatus_reg1_reg_0(gt_phystatus_0),
        .rst_cpllreset(rst_cpllreset),
        .rst_drp_start(rst_drp_start),
        .rst_drp_x16(rst_drp_x16),
        .rxpmaresetdone_reg1_reg_0(\pipe_lane[0].gt_wrapper_i_n_8 ),
        .\txdata_wait_cnt_reg[0]_0 (CLK),
        .txsync_done_reg1_reg_0(sync_txsync_done_0));
  xdma_0_pcie2_ip_pipe_eq \pipe_lane[0].pipe_eq.pipe_eq_i 
       (.TXMAINCURSOR(eq_txeq_maincursor_0),
        .TXPOSTCURSOR(eq_txeq_postcursor_0),
        .TXPRECURSOR(eq_txeq_precursor_0),
        .eq_rxeq_adapt_done_0(eq_rxeq_adapt_done_0),
        .\fs_reg2_reg[5] (CLK),
        .rst_cpllreset(rst_cpllreset));
  xdma_0_pcie2_ip_gt_common \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i 
       (.CLK(\pipe_clock_int.pipe_clock_i_n_1 ),
        .PLL0RESET0(\qpll_wrapper_i/PLL0RESET0 ),
        .QRST_DRP_DONE(qdrp_done),
        .QRST_DRP_START(qrst_drp_start),
        .QRST_QPLLLOCK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1 ),
        .cpllrst(\qpll_wrapper_i/cpllrst ),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .\gtp_common.gtpe2_common_i (\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2 ),
        .\gtp_common.gtpe2_common_i_0 (\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_3 ),
        .rst_dclk_reset(rst_dclk_reset),
        .sys_clk(sys_clk));
  xdma_0_pcie2_ip_pipe_sync \pipe_lane[0].pipe_sync_i 
       (.\FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0 (\pipe_lane[0].pipe_user_i_n_15 ),
        .\FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 (\pipe_lane[0].pipe_user_i_n_17 ),
        .\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 (p_0_in4_in),
        .\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 (p_1_in5_in),
        .Q({\pipe_lane[0].pipe_sync_i_n_4 ,\pipe_lane[0].pipe_sync_i_n_5 ,\pipe_lane[0].pipe_sync_i_n_6 }),
        .SYNC_MMCM_LOCK(\pipe_clock_int.pipe_clock_i_n_3 ),
        .SYNC_RATE_IDLE(rate_idle_0),
        .SYNC_RXCDRLOCK(user_rxcdrlock_0),
        .SYNC_RXDLYSRESETDONE(rxdlysresetdone_1),
        .SYNC_RXPHALIGNDONE_M(\pipe_lane[0].gt_wrapper_i_n_7 ),
        .SYNC_RXPHALIGNDONE_S(\pipe_lane[1].gt_wrapper_i_n_8 ),
        .SYNC_RXSYNCDONE(\pipe_lane[0].gt_wrapper_i_n_11 ),
        .SYNC_TXDLYSRESETDONE(txdlysresetdone_1),
        .SYNC_TXPHALIGNDONE(txsyncallin),
        .SYNC_TXPHINITDONE(\pipe_lane[1].pipe_user_i_n_15 ),
        .SYNC_TXSYNCDONE(gt_txsyncdone_0),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START0),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[0]),
        .out(\pipe_lane[0].pipe_sync_i_n_1 ),
        .p_1_in(p_1_in),
        .p_1_in0_in(p_1_in0_in),
        .rst_cpllreset(rst_cpllreset),
        .rxphaligndone_s_reg2_reg_0(CLK),
        .sync_txdlyen_0(sync_txdlyen_0),
        .txphinitdone_reg3_reg_0(\pipe_lane[0].pipe_sync_i_n_3 ),
        .\txsync_fsm.txsync_done_reg_0 (sync_txsync_done_0),
        .\txsync_fsm.txsync_done_reg_1 (\pipe_lane[0].pipe_user_i_n_16 ));
  xdma_0_pcie2_ip_pipe_user \pipe_lane[0].pipe_user_i 
       (.D(user_resetdone[0]),
        .\FSM_onehot_txsync_fsm.fsm_tx_reg[4] (\pipe_lane[0].pipe_sync_i_n_3 ),
        .Q({rate_done_0,rate_idle_0}),
        .RXSTATUS(\pipe_lane[0].gt_wrapper_i_n_37 ),
        .SR(rst_rxusrclk_reset),
        .SYNC_RXCDRLOCK(user_rxcdrlock_0),
        .TXCHARDISPMODE(TXCHARDISPMODE),
        .eq_rxeq_adapt_done_0(eq_rxeq_adapt_done_0),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[0]),
        .gt_rx_phy_status_q_reg(gt_phystatus_0),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[0]),
        .gt_rxcdrlock_0(gt_rxcdrlock_0),
        .gt_rxresetdone_0(gt_rxresetdone_0),
        .gt_rxvalid_0(gt_rxvalid_0),
        .gt_rxvalid_q_reg(\gt_rx_status_q_reg[0] ),
        .gt_txresetdone_0(gt_txresetdone_0),
        .\gtp_channel.gtpe2_channel_i (\gtp_channel.gtpe2_channel_i ),
        .out(p_1_in5_in),
        .p_1_in(p_1_in),
        .p_1_in0_in(p_1_in0_in),
        .pclk_sel_reg1_reg_0(\pipe_lane[0].gtp_pipe_rate.gtp_pipe_rate_i_n_0 ),
        .pipe_tx0_elec_idle_gt(pipe_tx0_elec_idle_gt),
        .rst_cpllreset(rst_cpllreset),
        .rst_idle_reg1_reg_0(\gtp_pipe_reset.gtp_pipe_reset_i_n_11 ),
        .rst_idle_reg2_reg_0(\pipe_lane[0].pipe_user_i_n_2 ),
        .\rxvalid_cnt_reg[3]_0 (CLK),
        .txcompliance_reg2_reg_0(p_0_in4_in),
        .txcompliance_reg2_reg_1(\pipe_lane[0].pipe_user_i_n_15 ),
        .txcompliance_reg2_reg_2(\pipe_lane[0].pipe_user_i_n_16 ),
        .txelecidle_reg2_reg_0(\pipe_lane[0].pipe_user_i_n_17 ),
        .\txsync_fsm.txsync_done_reg (\pipe_lane[0].pipe_sync_i_n_1 ),
        .user_eyescanreset_0(user_eyescanreset_0),
        .user_oobclk_0(user_oobclk_0),
        .user_resetovrd_0(user_resetovrd_0),
        .user_rxbufreset_0(user_rxbufreset_0),
        .user_rxcdrfreqreset_0(user_rxcdrfreqreset_0),
        .user_rxcdrreset_0(user_rxcdrreset_0),
        .user_rxpcsreset_0(user_rxpcsreset_0),
        .user_rxpmareset_0(user_rxpmareset_0));
  xdma_0_pcie2_ip_gt_wrapper_31 \pipe_lane[1].gt_wrapper_i 
       (.CLK(\pipe_clock_int.pipe_clock_i_n_1 ),
        .D({\pipe_lane[1].gt_wrapper_i_n_20 ,\pipe_lane[1].gt_wrapper_i_n_21 ,\pipe_lane[1].gt_wrapper_i_n_22 ,\pipe_lane[1].gt_wrapper_i_n_23 ,\pipe_lane[1].gt_wrapper_i_n_24 ,\pipe_lane[1].gt_wrapper_i_n_25 ,\pipe_lane[1].gt_wrapper_i_n_26 ,\pipe_lane[1].gt_wrapper_i_n_27 ,\pipe_lane[1].gt_wrapper_i_n_28 ,\pipe_lane[1].gt_wrapper_i_n_29 ,\pipe_lane[1].gt_wrapper_i_n_30 ,\pipe_lane[1].gt_wrapper_i_n_31 ,\pipe_lane[1].gt_wrapper_i_n_32 ,\pipe_lane[1].gt_wrapper_i_n_33 ,\pipe_lane[1].gt_wrapper_i_n_34 ,\pipe_lane[1].gt_wrapper_i_n_35 }),
        .DRPADDR(\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_2 ),
        .DRPDI({\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_4 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_5 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_6 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_7 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_8 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_9 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_10 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_11 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_12 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_13 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_14 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_15 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_16 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_17 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_18 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_19 }),
        .Q({\pipe_lane[1].pipe_sync_i_n_2 ,\pipe_lane[1].pipe_sync_i_n_3 ,\pipe_lane[1].pipe_sync_i_n_4 }),
        .RXCHBONDO(\gt_rxchbondi[1]_0 ),
        .RXRATE(rate_rate_3),
        .RXSTATUS(\pipe_lane[1].gt_wrapper_i_n_36 ),
        .SYNC_RXPHALIGNDONE_S(\pipe_lane[1].gt_wrapper_i_n_8 ),
        .SYNC_RXSYNCDONE(\pipe_lane[1].gt_wrapper_i_n_12 ),
        .SYNC_TXPHALIGNDONE(txsyncallin),
        .SYNC_TXSYNCDONE(gt_txsyncdone_1),
        .TXMAINCURSOR(eq_txeq_maincursor_7),
        .TXPOSTCURSOR(eq_txeq_postcursor_5),
        .TXPRECURSOR(eq_txeq_precursor_5),
        .gt_rx_data_k_wire_filter(gt_rx_data_k_wire_filter[3:2]),
        .gt_rx_data_wire_filter(gt_rx_data_wire_filter[31:16]),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[1]),
        .\gt_rx_status_q_reg[0] (\gt_rx_status_q_reg[0]_0 ),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2] ),
        .gt_rxcdrlock_1(gt_rxcdrlock_1),
        .gt_rxratedone_1(gt_rxratedone_1),
        .gt_rxresetdone_1(gt_rxresetdone_1),
        .gt_rxsyncout_0(gt_rxsyncout_0),
        .gt_rxvalid_1(gt_rxvalid_1),
        .gt_txratedone_1(gt_txratedone_1),
        .gt_txresetdone_1(gt_txresetdone_1),
        .gt_txsyncout_0(gt_txsyncout_0),
        .\gtp_channel.gtpe2_channel_i_0 (\pipe_lane[1].gt_wrapper_i_n_0 ),
        .\gtp_channel.gtpe2_channel_i_1 (gt_phystatus_1),
        .\gtp_channel.gtpe2_channel_i_10 (\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_2 ),
        .\gtp_channel.gtpe2_channel_i_11 (\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_3 ),
        .\gtp_channel.gtpe2_channel_i_12 (CLK),
        .\gtp_channel.gtpe2_channel_i_13 (\gtp_channel.gtpe2_channel_i_6 ),
        .\gtp_channel.gtpe2_channel_i_14 (\gtp_channel.gtpe2_channel_i_3 ),
        .\gtp_channel.gtpe2_channel_i_15 (\gtp_channel.gtpe2_channel_i_7 ),
        .\gtp_channel.gtpe2_channel_i_16 (txcompliance_reg1_reg),
        .\gtp_channel.gtpe2_channel_i_17 (\gtp_channel.gtpe2_channel_i_8 ),
        .\gtp_channel.gtpe2_channel_i_2 (\pipe_lane[1].gt_wrapper_i_n_6 ),
        .\gtp_channel.gtpe2_channel_i_3 (\pipe_lane[1].gt_wrapper_i_n_9 ),
        .\gtp_channel.gtpe2_channel_i_4 (\pipe_lane[1].gt_wrapper_i_n_14 ),
        .\gtp_channel.gtpe2_channel_i_5 (\pipe_lane[1].gt_wrapper_i_n_15 ),
        .\gtp_channel.gtpe2_channel_i_6 (\pipe_lane[1].gt_wrapper_i_n_16 ),
        .\gtp_channel.gtpe2_channel_i_7 (\gtp_channel.gtpe2_channel_i_0 ),
        .\gtp_channel.gtpe2_channel_i_8 (\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_1 ),
        .\gtp_channel.gtpe2_channel_i_9 (\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_3 ),
        .pci_exp_rxn(pci_exp_rxn[1]),
        .pci_exp_rxp(pci_exp_rxp[1]),
        .pci_exp_txn(pci_exp_txn[1]),
        .pci_exp_txp(pci_exp_txp[1]),
        .pipe_rx1_chanisaligned_gt(pipe_rx1_chanisaligned_gt),
        .pipe_rx1_polarity_gt(pipe_rx1_polarity_gt),
        .pipe_tx1_elec_idle_gt(pipe_tx1_elec_idle_gt),
        .pipe_tx_deemph_gt(pipe_tx_deemph_gt),
        .pipe_tx_rcvr_det_gt(pipe_tx_rcvr_det_gt),
        .rst_gtreset(rst_gtreset),
        .rst_userrdy(rst_userrdy),
        .rxsyncallin(rxsyncallin),
        .user_eyescanreset_1(user_eyescanreset_1),
        .user_oobclk_1(user_oobclk_1),
        .user_resetovrd_1(user_resetovrd_1),
        .user_rxbufreset_1(user_rxbufreset_1),
        .user_rxcdrfreqreset_1(user_rxcdrfreqreset_1),
        .user_rxcdrreset_1(user_rxcdrreset_1),
        .user_rxpcsreset_1(user_rxpcsreset_1),
        .user_rxpmareset_1(user_rxpmareset_1));
  xdma_0_pcie2_ip_gtp_pipe_drp_32 \pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i 
       (.CLK(\pipe_clock_int.pipe_clock_i_n_1 ),
        .D({\pipe_lane[1].gt_wrapper_i_n_20 ,\pipe_lane[1].gt_wrapper_i_n_21 ,\pipe_lane[1].gt_wrapper_i_n_22 ,\pipe_lane[1].gt_wrapper_i_n_23 ,\pipe_lane[1].gt_wrapper_i_n_24 ,\pipe_lane[1].gt_wrapper_i_n_25 ,\pipe_lane[1].gt_wrapper_i_n_26 ,\pipe_lane[1].gt_wrapper_i_n_27 ,\pipe_lane[1].gt_wrapper_i_n_28 ,\pipe_lane[1].gt_wrapper_i_n_29 ,\pipe_lane[1].gt_wrapper_i_n_30 ,\pipe_lane[1].gt_wrapper_i_n_31 ,\pipe_lane[1].gt_wrapper_i_n_32 ,\pipe_lane[1].gt_wrapper_i_n_33 ,\pipe_lane[1].gt_wrapper_i_n_34 ,\pipe_lane[1].gt_wrapper_i_n_35 }),
        .DRPADDR(\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_2 ),
        .DRPDI({\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_4 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_5 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_6 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_7 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_8 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_9 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_10 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_11 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_12 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_13 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_14 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_15 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_16 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_17 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_18 ,\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_19 }),
        .DRP_START0(DRP_START0),
        .DRP_X1602_out(DRP_X1602_out),
        .done_reg_0(drp_done_1),
        .\fsm_reg[1]_0 (\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_1 ),
        .\fsm_reg[1]_1 (\pipe_lane[1].gtp_pipe_drp.gtp_pipe_drp_i_n_3 ),
        .rdy_reg1_reg_0(\pipe_lane[1].gt_wrapper_i_n_0 ),
        .rst_dclk_reset(rst_dclk_reset));
  xdma_0_pcie2_ip_gtp_pipe_rate_33 \pipe_lane[1].gtp_pipe_rate.gtp_pipe_rate_i 
       (.D(D),
        .DRP_START0(DRP_START0),
        .DRP_X1602_out(DRP_X1602_out),
        .Q({rate_txsync_start_1,rate_done_1,rate_idle_1}),
        .RXRATE(rate_rate_3),
        .drp_done_reg1_reg_0(drp_done_1),
        .gt_rxratedone_1(gt_rxratedone_1),
        .gt_txratedone_1(gt_txratedone_1),
        .pclk_sel_reg_0(\pipe_lane[1].gtp_pipe_rate.gtp_pipe_rate_i_n_0 ),
        .phystatus_reg1_reg_0(gt_phystatus_1),
        .rst_cpllreset(rst_cpllreset),
        .rst_drp_start(rst_drp_start),
        .rst_drp_x16(rst_drp_x16),
        .rxpmaresetdone_reg1_reg_0(\pipe_lane[1].gt_wrapper_i_n_9 ),
        .\txdata_wait_cnt_reg[0]_0 (CLK),
        .txsync_done_reg1_reg_0(sync_txsync_done_1));
  xdma_0_pcie2_ip_pipe_eq_34 \pipe_lane[1].pipe_eq.pipe_eq_i 
       (.TXMAINCURSOR(eq_txeq_maincursor_7),
        .TXPOSTCURSOR(eq_txeq_postcursor_5),
        .TXPRECURSOR(eq_txeq_precursor_5),
        .eq_rxeq_adapt_done_1(eq_rxeq_adapt_done_1),
        .\lf_reg2_reg[5] (CLK),
        .rst_cpllreset(rst_cpllreset));
  xdma_0_pcie2_ip_pipe_sync_35 \pipe_lane[1].pipe_sync_i 
       (.\FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0 (\pipe_lane[1].pipe_user_i_n_18 ),
        .\FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0 (\pipe_lane[1].pipe_user_i_n_19 ),
        .\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0 (p_1_in5_in_2),
        .\FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1 (p_0_in4_in_1),
        .Q({\pipe_lane[1].pipe_sync_i_n_2 ,\pipe_lane[1].pipe_sync_i_n_3 ,\pipe_lane[1].pipe_sync_i_n_4 }),
        .QRST_MMCM_LOCK(\pipe_clock_int.pipe_clock_i_n_3 ),
        .SYNC_RATE_IDLE(rate_idle_1),
        .SYNC_RXCDRLOCK(user_rxcdrlock_1),
        .SYNC_RXDLYSRESETDONE(rxdlysresetdone_1),
        .SYNC_RXPHALIGNDONE_M(\pipe_lane[0].gt_wrapper_i_n_7 ),
        .SYNC_RXPHALIGNDONE_S(\pipe_lane[1].gt_wrapper_i_n_8 ),
        .SYNC_RXSYNCDONE(\pipe_lane[1].gt_wrapper_i_n_12 ),
        .SYNC_TXDLYSRESETDONE(txdlysresetdone_1),
        .SYNC_TXPHALIGNDONE(txsyncallin),
        .SYNC_TXPHINITDONE(\pipe_lane[1].pipe_user_i_n_15 ),
        .SYNC_TXSYNCDONE(gt_txsyncdone_1),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START01_out),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[1]),
        .out(\pipe_lane[1].pipe_sync_i_n_1 ),
        .p_1_in0_in(p_1_in0_in_0),
        .rst_cpllreset(rst_cpllreset),
        .rxsyncdone_reg2_reg_0(CLK),
        .\txsync_fsm.txsync_done_reg_0 (sync_txsync_done_1));
  xdma_0_pcie2_ip_pipe_user_36 \pipe_lane[1].pipe_user_i 
       (.D(user_resetdone[1]),
        .\FSM_onehot_txsync_fsm.fsm_tx_reg[4] (\pipe_lane[1].pipe_sync_i_n_1 ),
        .Q({rate_done_1,rate_idle_1}),
        .RXSTATUS(\pipe_lane[1].gt_wrapper_i_n_36 ),
        .SR(rst_rxusrclk_reset),
        .SYNC_RXCDRLOCK(user_rxcdrlock_1),
        .SYNC_RXPHALIGNDONE_M(\pipe_lane[0].gt_wrapper_i_n_7 ),
        .SYNC_RXPHALIGNDONE_S(\pipe_lane[1].gt_wrapper_i_n_8 ),
        .SYNC_TXPHALIGNDONE(txsyncallin),
        .SYNC_TXPHINITDONE(\pipe_lane[1].pipe_user_i_n_15 ),
        .eq_rxeq_adapt_done_1(eq_rxeq_adapt_done_1),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[1]),
        .gt_rx_phy_status_q_reg(gt_phystatus_1),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[1]),
        .gt_rxcdrlock_1(gt_rxcdrlock_1),
        .gt_rxresetdone_1(gt_rxresetdone_1),
        .gt_rxvalid_1(gt_rxvalid_1),
        .gt_rxvalid_q_reg(\gt_rx_status_q_reg[0]_0 ),
        .gt_txresetdone_1(gt_txresetdone_1),
        .\gtp_channel.gtpe2_channel_i (\gtp_channel.gtpe2_channel_i_2 ),
        .out(p_1_in5_in_2),
        .p_1_in0_in(p_1_in0_in_0),
        .pclk_sel_reg1_reg_0(\pipe_lane[1].gtp_pipe_rate.gtp_pipe_rate_i_n_0 ),
        .phy_rdy_n_int_reg(\pipe_lane[0].pipe_user_i_n_2 ),
        .pipe_tx1_elec_idle_gt(pipe_tx1_elec_idle_gt),
        .reg_clock_locked(reg_clock_locked),
        .rst_cpllreset(rst_cpllreset),
        .rst_idle_reg1_reg_0(\gtp_pipe_reset.gtp_pipe_reset_i_n_11 ),
        .rst_idle_reg2_reg_0(rst_idle_reg2_reg),
        .rxsyncallin(rxsyncallin),
        .\rxvalid_cnt_reg[3]_0 (CLK),
        .txcompliance_reg1_reg_0(txcompliance_reg1_reg),
        .txcompliance_reg2_reg_0(p_0_in4_in_1),
        .txcompliance_reg2_reg_1(\pipe_lane[1].pipe_user_i_n_18 ),
        .txelecidle_reg2_reg_0(\pipe_lane[1].pipe_user_i_n_19 ),
        .txphaligndone_reg1_reg(\pipe_lane[1].gt_wrapper_i_n_15 ),
        .txphaligndone_reg1_reg_0(\pipe_lane[0].gt_wrapper_i_n_15 ),
        .txphinitdone_reg1_reg(\pipe_lane[1].gt_wrapper_i_n_16 ),
        .txphinitdone_reg1_reg_0(p_1_in5_in),
        .txphinitdone_reg1_reg_1(p_0_in4_in),
        .txphinitdone_reg1_reg_2(\pipe_lane[0].gt_wrapper_i_n_16 ),
        .user_eyescanreset_1(user_eyescanreset_1),
        .user_oobclk_1(user_oobclk_1),
        .user_resetovrd_1(user_resetovrd_1),
        .user_rxbufreset_1(user_rxbufreset_1),
        .user_rxcdrfreqreset_1(user_rxcdrfreqreset_1),
        .user_rxcdrreset_1(user_rxcdrreset_1),
        .user_rxpcsreset_1(user_rxpcsreset_1),
        .user_rxpmareset_1(user_rxpmareset_1));
  LUT1 #(
    .INIT(2'h1)) 
    pl_phy_lnk_up_q_i_1
       (.I0(sys_rst_n),
        .O(sys_rst_n_0));
  xdma_0_pcie2_ip_qpll_reset \qpll_reset.qpll_reset_i 
       (.D(D),
        .Q(qrst_drp_start),
        .QRST_DRP_DONE(qdrp_done),
        .QRST_QPLLLOCK(\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i_n_1 ),
        .SS(\gtp_pipe_reset.gtp_pipe_reset_i_n_0 ),
        .SYNC_MMCM_LOCK(\pipe_clock_int.pipe_clock_i_n_3 ),
        .mmcm_lock_reg1_reg_0(CLK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDCE reset_n_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .CLR(sys_rst_n_0),
        .D(1'b1),
        .Q(reset_n_reg1));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDCE reset_n_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .CLR(sys_rst_n_0),
        .D(reset_n_reg1),
        .Q(reset_n_reg2));
endmodule

module xdma_0_pcie2_ip_qpll_drp
   (QRST_DRP_DONE,
    Q,
    \di_reg[15]_0 ,
    qpll_drp_en,
    qpll_drp_we,
    rst_dclk_reset,
    QRST_DRP_START,
    CLK,
    qpll_drp_rdy,
    QRST_QPLLLOCK,
    D);
  output [0:0]QRST_DRP_DONE;
  output [4:0]Q;
  output [15:0]\di_reg[15]_0 ;
  output qpll_drp_en;
  output qpll_drp_we;
  input rst_dclk_reset;
  input QRST_DRP_START;
  input CLK;
  input qpll_drp_rdy;
  input [0:0]QRST_QPLLLOCK;
  input [15:0]D;

  wire CLK;
  wire [15:0]D;
  wire [4:0]Q;
  wire [0:0]QRST_DRP_DONE;
  wire QRST_DRP_START;
  wire [0:0]QRST_QPLLLOCK;
  wire \addr[0]_i_1_n_0 ;
  wire \addr[1]_i_1_n_0 ;
  wire \addr[2]_i_1_n_0 ;
  wire \addr[5]_i_1_n_0 ;
  wire \addr[7]_i_1_n_0 ;
  wire \crscode_reg_n_0_[0] ;
  wire \crscode_reg_n_0_[1] ;
  wire \crscode_reg_n_0_[2] ;
  wire \crscode_reg_n_0_[3] ;
  wire \crscode_reg_n_0_[4] ;
  wire \crscode_reg_n_0_[5] ;
  wire [15:0]di;
  wire \di[11]_i_2_n_0 ;
  wire \di[12]_i_2_n_0 ;
  wire \di[13]_i_2_n_0 ;
  wire \di[14]_i_2_n_0 ;
  wire \di[15]_i_2_n_0 ;
  wire [15:0]\di_reg[15]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [15:0]do_reg2;
  wire done;
  wire \fsm[1]_i_2_n_0 ;
  wire \fsm[1]_i_3_n_0 ;
  wire \fsm_inferred__1/i___0_n_0 ;
  wire \fsm_inferred__1/i___1_n_0 ;
  wire \fsm_inferred__1/i__n_0 ;
  wire \fsm_reg_n_0_[0] ;
  wire \fsm_reg_n_0_[1] ;
  wire \fsm_reg_n_0_[2] ;
  wire \fsm_reg_n_0_[3] ;
  wire \fsm_reg_n_0_[4] ;
  wire \fsm_reg_n_0_[5] ;
  wire \fsm_reg_n_0_[6] ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire gen3_reg2;
  wire \gtp_common.gtpe2_common_i_i_4_n_0 ;
  wire \gtp_common.gtpe2_common_i_i_5_n_0 ;
  wire index;
  wire \index[0]_i_1_n_0 ;
  wire \index[0]_i_2_n_0 ;
  wire \index[1]_i_1_n_0 ;
  wire \index[2]_i_1_n_0 ;
  wire \index[2]_i_2_n_0 ;
  wire \index[2]_i_3_n_0 ;
  wire \index[2]_i_5_n_0 ;
  wire \index_reg_n_0_[0] ;
  wire \index_reg_n_0_[1] ;
  wire \index_reg_n_0_[2] ;
  wire [1:0]load_cnt;
  wire \load_cnt[0]_i_1__1_n_0 ;
  wire \load_cnt[1]_i_1_n_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire ovrd_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire ovrd_reg2;
  wire [6:0]p_0_in__0;
  wire p_1_in;
  wire [5:0]p_2_in;
  wire qpll_drp_en;
  wire qpll_drp_rdy;
  wire qpll_drp_we;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire rdy_reg2;
  wire rst_dclk_reset;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire start_reg2;

  (* SOFT_HLUTNM = "soft_lutpair1800" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \addr[0]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .O(\addr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1799" *) 
  LUT3 #(
    .INIT(8'h0D)) 
    \addr[1]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[1] ),
        .O(\addr[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1798" *) 
  LUT3 #(
    .INIT(8'h4D)) 
    \addr[2]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[2] ),
        .I2(\index_reg_n_0_[0] ),
        .O(\addr[2]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \addr[5]_i_1 
       (.I0(\index_reg_n_0_[0] ),
        .I1(\index_reg_n_0_[1] ),
        .O(\addr[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1799" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \addr[7]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .O(\addr[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\addr[0]_i_1_n_0 ),
        .Q(Q[0]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\addr[1]_i_1_n_0 ),
        .Q(Q[1]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\addr[2]_i_1_n_0 ),
        .Q(Q[2]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\addr[5]_i_1_n_0 ),
        .Q(Q[3]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\addr[7]_i_1_n_0 ),
        .Q(Q[4]),
        .R(rst_dclk_reset));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[0]_i_1 
       (.I0(do_reg2[1]),
        .I1(\index_reg_n_0_[2] ),
        .O(p_2_in[0]));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[1]_i_1 
       (.I0(do_reg2[2]),
        .I1(\index_reg_n_0_[2] ),
        .O(p_2_in[1]));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[2]_i_1 
       (.I0(do_reg2[3]),
        .I1(\index_reg_n_0_[2] ),
        .O(p_2_in[2]));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[3]_i_1 
       (.I0(do_reg2[4]),
        .I1(\index_reg_n_0_[2] ),
        .O(p_2_in[3]));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[4]_i_1 
       (.I0(do_reg2[5]),
        .I1(\index_reg_n_0_[2] ),
        .O(p_2_in[4]));
  LUT4 #(
    .INIT(16'hC080)) 
    \crscode[5]_i_1 
       (.I0(ovrd_reg2),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[1] ),
        .I3(\index_reg_n_0_[2] ),
        .O(p_1_in));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[5]_i_2 
       (.I0(do_reg2[6]),
        .I1(\index_reg_n_0_[2] ),
        .O(p_2_in[5]));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[0] 
       (.C(CLK),
        .CE(p_1_in),
        .D(p_2_in[0]),
        .Q(\crscode_reg_n_0_[0] ),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[1] 
       (.C(CLK),
        .CE(p_1_in),
        .D(p_2_in[1]),
        .Q(\crscode_reg_n_0_[1] ),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[2] 
       (.C(CLK),
        .CE(p_1_in),
        .D(p_2_in[2]),
        .Q(\crscode_reg_n_0_[2] ),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[3] 
       (.C(CLK),
        .CE(p_1_in),
        .D(p_2_in[3]),
        .Q(\crscode_reg_n_0_[3] ),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[4] 
       (.C(CLK),
        .CE(p_1_in),
        .D(p_2_in[4]),
        .Q(\crscode_reg_n_0_[4] ),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[5] 
       (.C(CLK),
        .CE(p_1_in),
        .D(p_2_in[5]),
        .Q(\crscode_reg_n_0_[5] ),
        .R(rst_dclk_reset));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[0]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(do_reg2[0]),
        .O(di[0]));
  LUT5 #(
    .INIT(32'h0CC5CCCC)) 
    \di[10]_i_1 
       (.I0(\crscode_reg_n_0_[0] ),
        .I1(do_reg2[10]),
        .I2(\index_reg_n_0_[1] ),
        .I3(\index_reg_n_0_[0] ),
        .I4(\index_reg_n_0_[2] ),
        .O(di[10]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000090)) 
    \di[11]_i_1 
       (.I0(\crscode_reg_n_0_[0] ),
        .I1(\crscode_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(\index_reg_n_0_[0] ),
        .I4(\index_reg_n_0_[1] ),
        .I5(\di[11]_i_2_n_0 ),
        .O(di[11]));
  LUT5 #(
    .INIT(32'h40FF4022)) 
    \di[11]_i_2 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(ovrd_reg2),
        .I3(\index_reg_n_0_[2] ),
        .I4(do_reg2[11]),
        .O(\di[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00AA00AAAAAAC3AA)) 
    \di[12]_i_1 
       (.I0(do_reg2[12]),
        .I1(\di[12]_i_2_n_0 ),
        .I2(\crscode_reg_n_0_[2] ),
        .I3(\index_reg_n_0_[2] ),
        .I4(\index_reg_n_0_[0] ),
        .I5(\index_reg_n_0_[1] ),
        .O(di[12]));
  LUT2 #(
    .INIT(4'hE)) 
    \di[12]_i_2 
       (.I0(\crscode_reg_n_0_[0] ),
        .I1(\crscode_reg_n_0_[1] ),
        .O(\di[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00AAAAFFAAAAC3AA)) 
    \di[13]_i_1 
       (.I0(do_reg2[13]),
        .I1(\di[13]_i_2_n_0 ),
        .I2(\crscode_reg_n_0_[3] ),
        .I3(\index_reg_n_0_[2] ),
        .I4(\index_reg_n_0_[0] ),
        .I5(\index_reg_n_0_[1] ),
        .O(di[13]));
  (* SOFT_HLUTNM = "soft_lutpair1795" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \di[13]_i_2 
       (.I0(\crscode_reg_n_0_[1] ),
        .I1(\crscode_reg_n_0_[0] ),
        .I2(\crscode_reg_n_0_[2] ),
        .O(\di[13]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0AAFAA3A)) 
    \di[14]_i_1 
       (.I0(do_reg2[14]),
        .I1(\di[14]_i_2_n_0 ),
        .I2(\index_reg_n_0_[2] ),
        .I3(\index_reg_n_0_[0] ),
        .I4(\index_reg_n_0_[1] ),
        .O(di[14]));
  (* SOFT_HLUTNM = "soft_lutpair1795" *) 
  LUT5 #(
    .INIT(32'h0001FFFE)) 
    \di[14]_i_2 
       (.I0(\crscode_reg_n_0_[3] ),
        .I1(\crscode_reg_n_0_[1] ),
        .I2(\crscode_reg_n_0_[0] ),
        .I3(\crscode_reg_n_0_[2] ),
        .I4(\crscode_reg_n_0_[4] ),
        .O(\di[14]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0CC5CCCC)) 
    \di[15]_i_1 
       (.I0(\di[15]_i_2_n_0 ),
        .I1(do_reg2[15]),
        .I2(\index_reg_n_0_[1] ),
        .I3(\index_reg_n_0_[0] ),
        .I4(\index_reg_n_0_[2] ),
        .O(di[15]));
  LUT6 #(
    .INIT(64'h00000001FFFFFFFE)) 
    \di[15]_i_2 
       (.I0(\crscode_reg_n_0_[1] ),
        .I1(\crscode_reg_n_0_[0] ),
        .I2(\crscode_reg_n_0_[2] ),
        .I3(\crscode_reg_n_0_[3] ),
        .I4(\crscode_reg_n_0_[4] ),
        .I5(\crscode_reg_n_0_[5] ),
        .O(\di[15]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[1]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(do_reg2[1]),
        .O(di[1]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[2]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(do_reg2[2]),
        .O(di[2]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[3]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(do_reg2[3]),
        .O(di[3]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[4]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(do_reg2[4]),
        .O(di[4]));
  LUT4 #(
    .INIT(16'h2AAB)) 
    \di[5]_i_1 
       (.I0(do_reg2[5]),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(\index_reg_n_0_[2] ),
        .O(di[5]));
  LUT4 #(
    .INIT(16'h2BA8)) 
    \di[6]_i_1 
       (.I0(do_reg2[6]),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(\index_reg_n_0_[0] ),
        .O(di[6]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[7]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(do_reg2[7]),
        .O(di[7]));
  LUT4 #(
    .INIT(16'h2AAB)) 
    \di[8]_i_1 
       (.I0(do_reg2[8]),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(\index_reg_n_0_[2] ),
        .O(di[8]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[9]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(do_reg2[9]),
        .O(di[9]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[0]),
        .Q(\di_reg[15]_0 [0]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[10]),
        .Q(\di_reg[15]_0 [10]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[11]),
        .Q(\di_reg[15]_0 [11]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[12]),
        .Q(\di_reg[15]_0 [12]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[13]),
        .Q(\di_reg[15]_0 [13]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[14]),
        .Q(\di_reg[15]_0 [14]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[15]),
        .Q(\di_reg[15]_0 [15]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[1]),
        .Q(\di_reg[15]_0 [1]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[2]),
        .Q(\di_reg[15]_0 [2]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[3]),
        .Q(\di_reg[15]_0 [3]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[4]),
        .Q(\di_reg[15]_0 [4]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[5]),
        .Q(\di_reg[15]_0 [5]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[6]),
        .Q(\di_reg[15]_0 [6]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[7]),
        .Q(\di_reg[15]_0 [7]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[8]),
        .Q(\di_reg[15]_0 [8]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(di[9]),
        .Q(\di_reg[15]_0 [9]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(do_reg1[0]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[10]),
        .Q(do_reg1[10]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[11]),
        .Q(do_reg1[11]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[12]),
        .Q(do_reg1[12]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[13]),
        .Q(do_reg1[13]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[14]),
        .Q(do_reg1[14]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[15]),
        .Q(do_reg1[15]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(do_reg1[1]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(do_reg1[2]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(do_reg1[3]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[4]),
        .Q(do_reg1[4]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[5]),
        .Q(do_reg1[5]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[6]),
        .Q(do_reg1[6]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[7]),
        .Q(do_reg1[7]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[8]),
        .Q(do_reg1[8]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg1_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[9]),
        .Q(do_reg1[9]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \do_reg2_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(rst_dclk_reset));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    done_i_1__1
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[6] ),
        .I2(start_reg2),
        .I3(\fsm_reg_n_0_[4] ),
        .I4(\fsm_reg_n_0_[0] ),
        .I5(\gtp_common.gtpe2_common_i_i_5_n_0 ),
        .O(done));
  FDRE #(
    .INIT(1'b0)) 
    done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(done),
        .Q(QRST_DRP_DONE),
        .R(rst_dclk_reset));
  LUT5 #(
    .INIT(32'h5DFF5D5D)) 
    \fsm[0]_i_1__1 
       (.I0(\fsm_inferred__1/i___1_n_0 ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(start_reg2),
        .I3(\fsm[1]_i_3_n_0 ),
        .I4(\fsm_reg_n_0_[6] ),
        .O(p_0_in__0[0]));
  LUT6 #(
    .INIT(64'hFFAAEAAAEAAAEAAA)) 
    \fsm[1]_i_1__1 
       (.I0(\fsm[1]_i_2_n_0 ),
        .I1(start_reg2),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(\fsm_inferred__1/i___1_n_0 ),
        .I4(\fsm_reg_n_0_[6] ),
        .I5(\fsm[1]_i_3_n_0 ),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1797" *) 
  LUT4 #(
    .INIT(16'h0888)) 
    \fsm[1]_i_2 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_inferred__1/i___1_n_0 ),
        .I2(load_cnt[1]),
        .I3(load_cnt[0]),
        .O(\fsm[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1798" *) 
  LUT3 #(
    .INIT(8'hF7)) 
    \fsm[1]_i_3 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .O(\fsm[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1797" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \fsm[2]_i_1__1 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_inferred__1/i___1_n_0 ),
        .I2(load_cnt[1]),
        .I3(load_cnt[0]),
        .O(p_0_in__0[2]));
  LUT4 #(
    .INIT(16'h88C8)) 
    \fsm[3]_i_1 
       (.I0(\fsm_reg_n_0_[2] ),
        .I1(\fsm_inferred__1/i___1_n_0 ),
        .I2(\fsm_reg_n_0_[3] ),
        .I3(rdy_reg2),
        .O(p_0_in__0[3]));
  LUT3 #(
    .INIT(8'h80)) 
    \fsm[4]_i_1 
       (.I0(rdy_reg2),
        .I1(\fsm_reg_n_0_[3] ),
        .I2(\fsm_inferred__1/i___1_n_0 ),
        .O(p_0_in__0[4]));
  LUT4 #(
    .INIT(16'h88C8)) 
    \fsm[5]_i_1 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_inferred__1/i___1_n_0 ),
        .I2(\fsm_reg_n_0_[5] ),
        .I3(rdy_reg2),
        .O(p_0_in__0[5]));
  LUT3 #(
    .INIT(8'h80)) 
    \fsm[6]_i_1 
       (.I0(rdy_reg2),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_inferred__1/i___1_n_0 ),
        .O(p_0_in__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair1796" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \fsm_inferred__1/i_ 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[3] ),
        .O(\fsm_inferred__1/i__n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1796" *) 
  LUT4 #(
    .INIT(16'hFEE8)) 
    \fsm_inferred__1/i___0 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[3] ),
        .O(\fsm_inferred__1/i___0_n_0 ));
  LUT5 #(
    .INIT(32'h00000116)) 
    \fsm_inferred__1/i___1 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[6] ),
        .I3(\fsm_inferred__1/i__n_0 ),
        .I4(\fsm_inferred__1/i___0_n_0 ),
        .O(\fsm_inferred__1/i___1_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) 
  FDSE #(
    .INIT(1'b1)) 
    \fsm_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(\fsm_reg_n_0_[0] ),
        .S(rst_dclk_reset));
  (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(\fsm_reg_n_0_[1] ),
        .R(rst_dclk_reset));
  (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(\fsm_reg_n_0_[2] ),
        .R(rst_dclk_reset));
  (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(\fsm_reg_n_0_[3] ),
        .R(rst_dclk_reset));
  (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[4]),
        .Q(\fsm_reg_n_0_[4] ),
        .R(rst_dclk_reset));
  (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[5]),
        .Q(\fsm_reg_n_0_[5] ),
        .R(rst_dclk_reset));
  (* FSM_ENCODED_STATES = "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[6]),
        .Q(\fsm_reg_n_0_[6] ),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE gen3_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(gen3_reg1),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE gen3_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(rst_dclk_reset));
  LUT6 #(
    .INIT(64'h0000000000000014)) 
    \gtp_common.gtpe2_common_i_i_1 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[4] ),
        .I3(\fsm_reg_n_0_[6] ),
        .I4(\fsm_reg_n_0_[1] ),
        .I5(\gtp_common.gtpe2_common_i_i_4_n_0 ),
        .O(qpll_drp_en));
  (* SOFT_HLUTNM = "soft_lutpair1792" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    \gtp_common.gtpe2_common_i_i_2 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[6] ),
        .I3(\fsm_reg_n_0_[0] ),
        .I4(\gtp_common.gtpe2_common_i_i_5_n_0 ),
        .O(qpll_drp_we));
  LUT2 #(
    .INIT(4'hE)) 
    \gtp_common.gtpe2_common_i_i_4 
       (.I0(\fsm_reg_n_0_[3] ),
        .I1(\fsm_reg_n_0_[5] ),
        .O(\gtp_common.gtpe2_common_i_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1794" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \gtp_common.gtpe2_common_i_i_5 
       (.I0(\fsm_reg_n_0_[5] ),
        .I1(\fsm_reg_n_0_[3] ),
        .I2(\fsm_reg_n_0_[2] ),
        .O(\gtp_common.gtpe2_common_i_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000FFFF20000000)) 
    \index[0]_i_1 
       (.I0(\index[0]_i_2_n_0 ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[6] ),
        .I3(\index[2]_i_3_n_0 ),
        .I4(index),
        .I5(\index_reg_n_0_[0] ),
        .O(\index[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1800" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \index[0]_i_2 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[2] ),
        .O(\index[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h1000FFFFC0000000)) 
    \index[1]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index[2]_i_2_n_0 ),
        .I3(\index[2]_i_3_n_0 ),
        .I4(index),
        .I5(\index_reg_n_0_[1] ),
        .O(\index[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5000FFFF80000000)) 
    \index[2]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index[2]_i_2_n_0 ),
        .I3(\index[2]_i_3_n_0 ),
        .I4(index),
        .I5(\index_reg_n_0_[2] ),
        .O(\index[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1792" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \index[2]_i_2 
       (.I0(\fsm_reg_n_0_[6] ),
        .I1(\fsm_reg_n_0_[1] ),
        .O(\index[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1794" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \index[2]_i_3 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[3] ),
        .I3(\fsm_reg_n_0_[2] ),
        .I4(\fsm_reg_n_0_[4] ),
        .O(\index[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFEFEED)) 
    \index[2]_i_4 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\index[2]_i_5_n_0 ),
        .I2(\fsm_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[3] ),
        .I4(\fsm_reg_n_0_[5] ),
        .I5(\fsm_reg_n_0_[4] ),
        .O(index));
  LUT2 #(
    .INIT(4'hE)) 
    \index[2]_i_5 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[6] ),
        .O(\index[2]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\index[0]_i_1_n_0 ),
        .Q(\index_reg_n_0_[0] ),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\index[1]_i_1_n_0 ),
        .Q(\index_reg_n_0_[1] ),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\index[2]_i_1_n_0 ),
        .Q(\index_reg_n_0_[2] ),
        .R(rst_dclk_reset));
  (* SOFT_HLUTNM = "soft_lutpair1793" *) 
  LUT5 #(
    .INIT(32'h00B00000)) 
    \load_cnt[0]_i_1__1 
       (.I0(load_cnt[1]),
        .I1(load_cnt[0]),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[6] ),
        .I4(\index[2]_i_3_n_0 ),
        .O(\load_cnt[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1793" *) 
  LUT5 #(
    .INIT(32'h00E00000)) 
    \load_cnt[1]_i_1 
       (.I0(load_cnt[1]),
        .I1(load_cnt[0]),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[6] ),
        .I4(\index[2]_i_3_n_0 ),
        .O(\load_cnt[1]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1__1_n_0 ),
        .Q(load_cnt[0]),
        .R(rst_dclk_reset));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\load_cnt[1]_i_1_n_0 ),
        .Q(load_cnt[1]),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE ovrd_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(ovrd_reg1),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE ovrd_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ovrd_reg1),
        .Q(ovrd_reg2),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE qplllock_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(QRST_QPLLLOCK),
        .Q(qplllock_reg1),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE qplllock_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rdy_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(qpll_drp_rdy),
        .Q(rdy_reg1),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE rdy_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE start_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(QRST_DRP_START),
        .Q(start_reg1),
        .R(rst_dclk_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE start_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(rst_dclk_reset));
endmodule

module xdma_0_pcie2_ip_qpll_reset
   (Q,
    SS,
    mmcm_lock_reg1_reg_0,
    D,
    QRST_DRP_DONE,
    QRST_QPLLLOCK,
    SYNC_MMCM_LOCK);
  output [0:0]Q;
  input [0:0]SS;
  input mmcm_lock_reg1_reg_0;
  input [0:0]D;
  input [0:0]QRST_DRP_DONE;
  input [0:0]QRST_QPLLLOCK;
  input SYNC_MMCM_LOCK;

  wire [0:0]D;
  wire \FSM_onehot_fsm[0]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm[1]_i_1_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1_n_0 ;
  wire \FSM_onehot_fsm_reg_n_0_[0] ;
  wire \FSM_onehot_fsm_reg_n_0_[1] ;
  wire [0:0]Q;
  wire [0:0]QRST_DRP_DONE;
  wire [0:0]QRST_QPLLLOCK;
  wire [0:0]SS;
  wire SYNC_MMCM_LOCK;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]cplllock_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]cplllock_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire drp_done_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg1;
  wire mmcm_lock_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire mmcm_lock_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire qplllock_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]qpllpd_in_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]qpllpd_in_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]qpllreset_in_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]qpllreset_in_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [1:0]rate_reg2;

  LUT4 #(
    .INIT(16'hAAA8)) 
    \FSM_onehot_fsm[0]_i_1__2 
       (.I0(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I1(qplllock_reg2),
        .I2(cplllock_reg2[0]),
        .I3(cplllock_reg2[1]),
        .O(\FSM_onehot_fsm[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0FFFFFFF00000044)) 
    \FSM_onehot_fsm[1]_i_1 
       (.I0(qplllock_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I2(mmcm_lock_reg2),
        .I3(cplllock_reg2[1]),
        .I4(cplllock_reg2[0]),
        .I5(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF800080008000)) 
    \FSM_onehot_fsm[2]_i_1 
       (.I0(mmcm_lock_reg2),
        .I1(cplllock_reg2[1]),
        .I2(cplllock_reg2[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I4(drp_done_reg2),
        .I5(Q),
        .O(\FSM_onehot_fsm[2]_i_1_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000" *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[0]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .S(SS));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .R(SS));
  (* FSM_ENCODED_STATES = "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1_n_0 ),
        .Q(Q),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \cplllock_reg1_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(cplllock_reg1[0]),
        .S(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \cplllock_reg1_reg[1] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(cplllock_reg1[1]),
        .S(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \cplllock_reg2_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(cplllock_reg1[0]),
        .Q(cplllock_reg2[0]),
        .S(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \cplllock_reg2_reg[1] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(cplllock_reg1[1]),
        .Q(cplllock_reg2[1]),
        .S(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \drp_done_reg1_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(QRST_DRP_DONE),
        .Q(drp_done_reg1),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \drp_done_reg2_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(drp_done_reg1),
        .Q(drp_done_reg2),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(SYNC_MMCM_LOCK),
        .Q(mmcm_lock_reg1),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \qplllock_reg1_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(QRST_QPLLLOCK),
        .Q(qplllock_reg1),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \qplllock_reg2_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \qpllpd_in_reg1_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(qpllpd_in_reg1[0]),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \qpllpd_in_reg1_reg[1] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(qpllpd_in_reg1[1]),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \qpllpd_in_reg2_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(qpllpd_in_reg1[0]),
        .Q(qpllpd_in_reg2[0]),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \qpllpd_in_reg2_reg[1] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(qpllpd_in_reg1[1]),
        .Q(qpllpd_in_reg2[1]),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \qpllreset_in_reg1_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(qpllreset_in_reg1[0]),
        .S(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \qpllreset_in_reg1_reg[1] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(qpllreset_in_reg1[1]),
        .S(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \qpllreset_in_reg2_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(qpllreset_in_reg1[0]),
        .Q(qpllreset_in_reg2[0]),
        .S(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDSE \qpllreset_in_reg2_reg[1] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(qpllreset_in_reg1[1]),
        .Q(qpllreset_in_reg2[1]),
        .S(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_reg1_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(D),
        .Q(rate_reg1[0]),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_reg1_reg[1] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_reg1[1]),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_reg2_reg[0] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(rate_reg1[0]),
        .Q(rate_reg2[0]),
        .R(SS));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \rate_reg2_reg[1] 
       (.C(mmcm_lock_reg1_reg_0),
        .CE(1'b1),
        .D(rate_reg1[1]),
        .Q(rate_reg2[1]),
        .R(SS));
endmodule

module xdma_0_pcie2_ip_qpll_wrapper
   (cpllrst,
    qpll_drp_rdy,
    QRST_QPLLLOCK,
    \gtp_common.gtpe2_common_i_0 ,
    \gtp_common.gtpe2_common_i_1 ,
    D,
    gt_cpllpdrefclk,
    CLK,
    qpll_drp_en,
    qpll_drp_we,
    sys_clk,
    PLL0RESET0,
    \gtp_common.gtpe2_common_i_2 ,
    Q);
  output cpllrst;
  output qpll_drp_rdy;
  output [0:0]QRST_QPLLLOCK;
  output \gtp_common.gtpe2_common_i_0 ;
  output \gtp_common.gtpe2_common_i_1 ;
  output [15:0]D;
  input gt_cpllpdrefclk;
  input CLK;
  input qpll_drp_en;
  input qpll_drp_we;
  input sys_clk;
  input PLL0RESET0;
  input [15:0]\gtp_common.gtpe2_common_i_2 ;
  input [4:0]Q;

  wire CLK;
  wire [15:0]D;
  wire PLL0RESET0;
  wire [4:0]Q;
  wire [0:0]QRST_QPLLLOCK;
  wire cpllpd;
  wire cpllrst;
  wire gt_cpllpdrefclk;
  wire \gtp_common.gtpe2_common_i_0 ;
  wire \gtp_common.gtpe2_common_i_1 ;
  wire [15:0]\gtp_common.gtpe2_common_i_2 ;
  wire qpll_drp_en;
  wire qpll_drp_rdy;
  wire qpll_drp_we;
  wire sys_clk;
  wire \NLW_gtp_common.gtpe2_common_i_PLL0FBCLKLOST_UNCONNECTED ;
  wire \NLW_gtp_common.gtpe2_common_i_PLL0REFCLKLOST_UNCONNECTED ;
  wire \NLW_gtp_common.gtpe2_common_i_PLL1FBCLKLOST_UNCONNECTED ;
  wire \NLW_gtp_common.gtpe2_common_i_PLL1LOCK_UNCONNECTED ;
  wire \NLW_gtp_common.gtpe2_common_i_PLL1OUTCLK_UNCONNECTED ;
  wire \NLW_gtp_common.gtpe2_common_i_PLL1OUTREFCLK_UNCONNECTED ;
  wire \NLW_gtp_common.gtpe2_common_i_PLL1REFCLKLOST_UNCONNECTED ;
  wire \NLW_gtp_common.gtpe2_common_i_REFCLKOUTMONITOR0_UNCONNECTED ;
  wire \NLW_gtp_common.gtpe2_common_i_REFCLKOUTMONITOR1_UNCONNECTED ;
  wire [7:0]\NLW_gtp_common.gtpe2_common_i_DMONITOROUT_UNCONNECTED ;
  wire [15:0]\NLW_gtp_common.gtpe2_common_i_PMARSVDOUT_UNCONNECTED ;

  xdma_0_pcie2_ip_gtp_cpllpd_ovrd cpllPDInst
       (.cpllpd(cpllpd),
        .cpllrst(cpllrst),
        .gt_cpllpdrefclk(gt_cpllpdrefclk));
  (* box_type = "PRIMITIVE" *) 
  GTPE2_COMMON #(
    .BIAS_CFG(64'h0000000000050001),
    .COMMON_CFG(32'h00000000),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK0_INVERTED(1'b0),
    .IS_GTGREFCLK1_INVERTED(1'b0),
    .IS_PLL0LOCKDETCLK_INVERTED(1'b0),
    .IS_PLL1LOCKDETCLK_INVERTED(1'b0),
    .PLL0_CFG(27'h01F024C),
    .PLL0_DMON_CFG(1'b0),
    .PLL0_FBDIV(5),
    .PLL0_FBDIV_45(5),
    .PLL0_INIT_CFG(24'h00001E),
    .PLL0_LOCK_CFG(9'h1E8),
    .PLL0_REFCLK_DIV(1),
    .PLL1_CFG(27'h01F024C),
    .PLL1_DMON_CFG(1'b0),
    .PLL1_FBDIV(5),
    .PLL1_FBDIV_45(5),
    .PLL1_INIT_CFG(24'h00001E),
    .PLL1_LOCK_CFG(9'h1E8),
    .PLL1_REFCLK_DIV(1),
    .PLL_CLKOUT_CFG(8'b00000000),
    .RSVD_ATTR0(16'h0000),
    .RSVD_ATTR1(16'h0000),
    .SIM_PLL0REFCLK_SEL(3'b001),
    .SIM_PLL1REFCLK_SEL(3'b001),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_VERSION("1.0")) 
    \gtp_common.gtpe2_common_i 
       (.BGBYPASSB(1'b1),
        .BGMONITORENB(1'b1),
        .BGPDB(1'b1),
        .BGRCALOVRD({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .BGRCALOVRDENB(1'b1),
        .DMONITOROUT(\NLW_gtp_common.gtpe2_common_i_DMONITOROUT_UNCONNECTED [7:0]),
        .DRPADDR({Q[4],1'b0,Q[3],Q[3],Q[4],Q[2:0]}),
        .DRPCLK(CLK),
        .DRPDI(\gtp_common.gtpe2_common_i_2 ),
        .DRPDO(D),
        .DRPEN(qpll_drp_en),
        .DRPRDY(qpll_drp_rdy),
        .DRPWE(qpll_drp_we),
        .GTEASTREFCLK0(1'b0),
        .GTEASTREFCLK1(1'b0),
        .GTGREFCLK0(1'b0),
        .GTGREFCLK1(1'b0),
        .GTREFCLK0(sys_clk),
        .GTREFCLK1(1'b0),
        .GTWESTREFCLK0(1'b0),
        .GTWESTREFCLK1(1'b0),
        .PLL0FBCLKLOST(\NLW_gtp_common.gtpe2_common_i_PLL0FBCLKLOST_UNCONNECTED ),
        .PLL0LOCK(QRST_QPLLLOCK),
        .PLL0LOCKDETCLK(1'b0),
        .PLL0LOCKEN(1'b1),
        .PLL0OUTCLK(\gtp_common.gtpe2_common_i_0 ),
        .PLL0OUTREFCLK(\gtp_common.gtpe2_common_i_1 ),
        .PLL0PD(cpllpd),
        .PLL0REFCLKLOST(\NLW_gtp_common.gtpe2_common_i_PLL0REFCLKLOST_UNCONNECTED ),
        .PLL0REFCLKSEL({1'b0,1'b0,1'b1}),
        .PLL0RESET(PLL0RESET0),
        .PLL1FBCLKLOST(\NLW_gtp_common.gtpe2_common_i_PLL1FBCLKLOST_UNCONNECTED ),
        .PLL1LOCK(\NLW_gtp_common.gtpe2_common_i_PLL1LOCK_UNCONNECTED ),
        .PLL1LOCKDETCLK(1'b0),
        .PLL1LOCKEN(1'b1),
        .PLL1OUTCLK(\NLW_gtp_common.gtpe2_common_i_PLL1OUTCLK_UNCONNECTED ),
        .PLL1OUTREFCLK(\NLW_gtp_common.gtpe2_common_i_PLL1OUTREFCLK_UNCONNECTED ),
        .PLL1PD(1'b1),
        .PLL1REFCLKLOST(\NLW_gtp_common.gtpe2_common_i_PLL1REFCLKLOST_UNCONNECTED ),
        .PLL1REFCLKSEL({1'b0,1'b0,1'b1}),
        .PLL1RESET(1'b1),
        .PLLRSVD1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PLLRSVD2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PMARSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PMARSVDOUT(\NLW_gtp_common.gtpe2_common_i_PMARSVDOUT_UNCONNECTED [15:0]),
        .RCALENB(1'b1),
        .REFCLKOUTMONITOR0(\NLW_gtp_common.gtpe2_common_i_REFCLKOUTMONITOR0_UNCONNECTED ),
        .REFCLKOUTMONITOR1(\NLW_gtp_common.gtpe2_common_i_REFCLKOUTMONITOR1_UNCONNECTED ));
endmodule

module xdma_0_pcie2_ip_rxeq_scan
   (adapt_done_reg_0,
    new_txcoeff_done_reg_0,
    D,
    rxeq_new_txcoeff_req,
    rst_cpllreset,
    new_txcoeff_req_reg1_reg_0,
    \lf_reg2_reg[5]_0 ,
    rxeq_preset_valid,
    out,
    rxeq_adapt_done_reg_reg,
    Q,
    rxeq_adapt_done_reg_reg_0,
    rxeq_adapt_done_reg_reg_1,
    rxeq_adapt_done_reg,
    eq_rxeq_adapt_done_1,
    \FSM_onehot_fsm_rx_reg[5] ,
    \preset_reg1_reg[2]_0 ,
    \txpreset_reg1_reg[3]_0 ,
    \txcoeff_reg1_reg[17]_0 ,
    \fs_reg1_reg[5]_0 ,
    \lf_reg1_reg[5]_0 );
  output adapt_done_reg_0;
  output new_txcoeff_done_reg_0;
  output [2:0]D;
  output rxeq_new_txcoeff_req;
  input rst_cpllreset;
  input new_txcoeff_req_reg1_reg_0;
  input \lf_reg2_reg[5]_0 ;
  input rxeq_preset_valid;
  input [1:0]out;
  input rxeq_adapt_done_reg_reg;
  input [4:0]Q;
  input rxeq_adapt_done_reg_reg_0;
  input rxeq_adapt_done_reg_reg_1;
  input rxeq_adapt_done_reg;
  input eq_rxeq_adapt_done_1;
  input [2:0]\FSM_onehot_fsm_rx_reg[5] ;
  input [2:0]\preset_reg1_reg[2]_0 ;
  input [3:0]\txpreset_reg1_reg[3]_0 ;
  input [17:0]\txcoeff_reg1_reg[17]_0 ;
  input [5:0]\fs_reg1_reg[5]_0 ;
  input [5:0]\lf_reg1_reg[5]_0 ;

  wire [2:0]D;
  wire \FSM_onehot_fsm[1]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm[3]_i_2__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_10__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_11__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_12__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_2__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_3__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_4__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_5__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_6__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_7__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_8__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_9__0_n_0 ;
  wire \FSM_onehot_fsm_reg_n_0_[1] ;
  wire \FSM_onehot_fsm_reg_n_0_[2] ;
  wire \FSM_onehot_fsm_reg_n_0_[3] ;
  wire \FSM_onehot_fsm_reg_n_0_[4] ;
  wire \FSM_onehot_fsm_rx[6]_i_2__0_n_0 ;
  wire [2:0]\FSM_onehot_fsm_rx_reg[5] ;
  wire [4:0]Q;
  wire adapt_done;
  wire adapt_done_cnt_i_1__0_n_0;
  wire adapt_done_cnt_i_2__0_n_0;
  wire adapt_done_cnt_reg_n_0;
  wire adapt_done_reg_0;
  wire [21:0]converge_cnt;
  wire [21:0]converge_cnt0;
  wire \converge_cnt[3]_i_3__0_n_0 ;
  wire \converge_cnt_reg[11]_i_2__0_n_0 ;
  wire \converge_cnt_reg[11]_i_2__0_n_1 ;
  wire \converge_cnt_reg[11]_i_2__0_n_2 ;
  wire \converge_cnt_reg[11]_i_2__0_n_3 ;
  wire \converge_cnt_reg[15]_i_2__0_n_0 ;
  wire \converge_cnt_reg[15]_i_2__0_n_1 ;
  wire \converge_cnt_reg[15]_i_2__0_n_2 ;
  wire \converge_cnt_reg[15]_i_2__0_n_3 ;
  wire \converge_cnt_reg[19]_i_2__0_n_0 ;
  wire \converge_cnt_reg[19]_i_2__0_n_1 ;
  wire \converge_cnt_reg[19]_i_2__0_n_2 ;
  wire \converge_cnt_reg[19]_i_2__0_n_3 ;
  wire \converge_cnt_reg[21]_i_2__0_n_3 ;
  wire \converge_cnt_reg[3]_i_2__0_n_0 ;
  wire \converge_cnt_reg[3]_i_2__0_n_1 ;
  wire \converge_cnt_reg[3]_i_2__0_n_2 ;
  wire \converge_cnt_reg[3]_i_2__0_n_3 ;
  wire \converge_cnt_reg[7]_i_2__0_n_0 ;
  wire \converge_cnt_reg[7]_i_2__0_n_1 ;
  wire \converge_cnt_reg[7]_i_2__0_n_2 ;
  wire \converge_cnt_reg[7]_i_2__0_n_3 ;
  wire \converge_cnt_reg_n_0_[0] ;
  wire \converge_cnt_reg_n_0_[10] ;
  wire \converge_cnt_reg_n_0_[11] ;
  wire \converge_cnt_reg_n_0_[12] ;
  wire \converge_cnt_reg_n_0_[13] ;
  wire \converge_cnt_reg_n_0_[14] ;
  wire \converge_cnt_reg_n_0_[15] ;
  wire \converge_cnt_reg_n_0_[16] ;
  wire \converge_cnt_reg_n_0_[17] ;
  wire \converge_cnt_reg_n_0_[18] ;
  wire \converge_cnt_reg_n_0_[19] ;
  wire \converge_cnt_reg_n_0_[1] ;
  wire \converge_cnt_reg_n_0_[20] ;
  wire \converge_cnt_reg_n_0_[21] ;
  wire \converge_cnt_reg_n_0_[2] ;
  wire \converge_cnt_reg_n_0_[3] ;
  wire \converge_cnt_reg_n_0_[4] ;
  wire \converge_cnt_reg_n_0_[5] ;
  wire \converge_cnt_reg_n_0_[6] ;
  wire \converge_cnt_reg_n_0_[7] ;
  wire \converge_cnt_reg_n_0_[8] ;
  wire \converge_cnt_reg_n_0_[9] ;
  wire eq_rxeq_adapt_done_1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg1;
  wire [5:0]\fs_reg1_reg[5]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg1;
  wire [5:0]\lf_reg1_reg[5]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg2;
  wire \lf_reg2_reg[5]_0 ;
  wire new_txcoeff_done;
  wire new_txcoeff_done_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg1;
  wire new_txcoeff_req_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg2;
  wire [1:0]out;
  wire preset_done;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg1;
  wire [2:0]\preset_reg1_reg[2]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg2;
  wire rst_cpllreset;
  wire rxeq_adapt_done_reg;
  wire rxeq_adapt_done_reg_reg;
  wire rxeq_adapt_done_reg_reg_0;
  wire rxeq_adapt_done_reg_reg_1;
  wire rxeq_new_txcoeff_req;
  wire rxeq_preset_valid;
  wire rxeqscan_adapt_done;
  wire rxeqscan_new_txcoeff_done;
  wire rxeqscan_preset_done;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg1;
  wire [17:0]\txcoeff_reg1_reg[17]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg1;
  wire [3:0]\txpreset_reg1_reg[3]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg2;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h0001FF01AAABFFFB)) 
    \FSM_onehot_fsm[1]_i_1__0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(preset_valid_reg2),
        .I5(new_txcoeff_req_reg2),
        .O(\FSM_onehot_fsm[1]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \FSM_onehot_fsm[2]_i_1__3 
       (.I0(preset_valid_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[2]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h10FF101010101010)) 
    \FSM_onehot_fsm[3]_i_1__3 
       (.I0(\FSM_onehot_fsm[4]_i_3__0_n_0 ),
        .I1(\FSM_onehot_fsm[3]_i_2__0_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_2__0_n_0 ),
        .I3(preset_valid_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I5(new_txcoeff_req_reg2),
        .O(\FSM_onehot_fsm[3]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1829" *) 
  LUT4 #(
    .INIT(16'h04FF)) 
    \FSM_onehot_fsm[3]_i_2__0 
       (.I0(adapt_done_cnt_reg_n_0),
        .I1(out[1]),
        .I2(out[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[3]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFFF)) 
    \FSM_onehot_fsm[4]_i_10__0 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .I1(\converge_cnt_reg_n_0_[1] ),
        .I2(\converge_cnt_reg_n_0_[9] ),
        .I3(\converge_cnt_reg_n_0_[21] ),
        .I4(\converge_cnt_reg_n_0_[2] ),
        .I5(\converge_cnt_reg_n_0_[14] ),
        .O(\FSM_onehot_fsm[4]_i_10__0_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \FSM_onehot_fsm[4]_i_11__0 
       (.I0(\converge_cnt_reg_n_0_[16] ),
        .I1(\converge_cnt_reg_n_0_[17] ),
        .I2(\converge_cnt_reg_n_0_[18] ),
        .I3(\converge_cnt_reg_n_0_[19] ),
        .O(\FSM_onehot_fsm[4]_i_11__0_n_0 ));
  LUT4 #(
    .INIT(16'hFFDF)) 
    \FSM_onehot_fsm[4]_i_12__0 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .I1(\converge_cnt_reg_n_0_[8] ),
        .I2(\converge_cnt_reg_n_0_[15] ),
        .I3(\converge_cnt_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[4]_i_12__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFD0FFD0FFD0)) 
    \FSM_onehot_fsm[4]_i_1__0 
       (.I0(\FSM_onehot_fsm[4]_i_2__0_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_3__0_n_0 ),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm[4]_i_4__0_n_0 ),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I5(new_txcoeff_req_reg2),
        .O(\FSM_onehot_fsm[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[4]_i_2__0 
       (.I0(\FSM_onehot_fsm[4]_i_5__0_n_0 ),
        .I1(\converge_cnt_reg_n_0_[20] ),
        .I2(\converge_cnt_reg_n_0_[12] ),
        .I3(\converge_cnt_reg_n_0_[10] ),
        .I4(\converge_cnt_reg_n_0_[8] ),
        .I5(\FSM_onehot_fsm[4]_i_6__0_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000020000)) 
    \FSM_onehot_fsm[4]_i_3__0 
       (.I0(\FSM_onehot_fsm[4]_i_6__0_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_7__0_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_8__0_n_0 ),
        .I3(\converge_cnt_reg_n_0_[10] ),
        .I4(\converge_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_fsm[4]_i_9__0_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1828" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    \FSM_onehot_fsm[4]_i_4__0 
       (.I0(adapt_done_cnt_reg_n_0),
        .I1(out[1]),
        .I2(out[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[4]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[4]_i_5__0 
       (.I0(\FSM_onehot_fsm[4]_i_10__0_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_9__0_n_0 ),
        .I2(\converge_cnt_reg_n_0_[11] ),
        .I3(\converge_cnt_reg_n_0_[15] ),
        .I4(\converge_cnt_reg_n_0_[13] ),
        .I5(\converge_cnt_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[4]_i_5__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \FSM_onehot_fsm[4]_i_6__0 
       (.I0(\converge_cnt_reg_n_0_[4] ),
        .I1(\converge_cnt_reg_n_0_[5] ),
        .I2(\converge_cnt_reg_n_0_[7] ),
        .I3(\converge_cnt_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm[4]_i_11__0_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_6__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFBFF)) 
    \FSM_onehot_fsm[4]_i_7__0 
       (.I0(\converge_cnt_reg_n_0_[13] ),
        .I1(\converge_cnt_reg_n_0_[9] ),
        .I2(\converge_cnt_reg_n_0_[21] ),
        .I3(\converge_cnt_reg_n_0_[11] ),
        .I4(\FSM_onehot_fsm[4]_i_12__0_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_7__0_n_0 ));
  LUT4 #(
    .INIT(16'hEFFF)) 
    \FSM_onehot_fsm[4]_i_8__0 
       (.I0(\converge_cnt_reg_n_0_[3] ),
        .I1(\converge_cnt_reg_n_0_[12] ),
        .I2(\converge_cnt_reg_n_0_[14] ),
        .I3(\converge_cnt_reg_n_0_[0] ),
        .O(\FSM_onehot_fsm[4]_i_8__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_onehot_fsm[4]_i_9__0 
       (.I0(out[1]),
        .I1(out[0]),
        .O(\FSM_onehot_fsm[4]_i_9__0_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[2] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[4] ),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h40FF4040)) 
    \FSM_onehot_fsm_rx[2]_i_1__0 
       (.I0(out[1]),
        .I1(out[0]),
        .I2(Q[0]),
        .I3(rxeqscan_preset_done),
        .I4(Q[1]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hF444444444444444)) 
    \FSM_onehot_fsm_rx[5]_i_1__0 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(Q[3]),
        .I2(\FSM_onehot_fsm_rx_reg[5] [2]),
        .I3(\FSM_onehot_fsm_rx_reg[5] [1]),
        .I4(\FSM_onehot_fsm_rx_reg[5] [0]),
        .I5(Q[2]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFE0E0E0)) 
    \FSM_onehot_fsm_rx[6]_i_1__0 
       (.I0(out[0]),
        .I1(out[1]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(rxeqscan_preset_done),
        .I5(\FSM_onehot_fsm_rx[6]_i_2__0_n_0 ),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair1830" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_fsm_rx[6]_i_2__0 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(Q[3]),
        .O(\FSM_onehot_fsm_rx[6]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000AAAFFFF0800)) 
    adapt_done_cnt_i_1__0
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .I5(adapt_done_cnt_i_2__0_n_0),
        .O(adapt_done_cnt_i_1__0_n_0));
  LUT5 #(
    .INIT(32'h00FF0101)) 
    adapt_done_cnt_i_2__0
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .O(adapt_done_cnt_i_2__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_cnt_reg
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(adapt_done_cnt_i_1__0_n_0),
        .Q(adapt_done_cnt_reg_n_0),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'hF8000000)) 
    adapt_done_i_1__0
       (.I0(out[0]),
        .I1(out[1]),
        .I2(adapt_done_cnt_reg_n_0),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .O(adapt_done));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_reg
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(adapt_done),
        .Q(rxeqscan_adapt_done),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[0]_i_1__0 
       (.I0(converge_cnt0[0]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[0]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[10]_i_1__0 
       (.I0(converge_cnt0[10]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[10]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[11]_i_1__0 
       (.I0(converge_cnt0[11]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[11]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[12]_i_1__0 
       (.I0(converge_cnt0[12]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[12]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[13]_i_1__0 
       (.I0(converge_cnt0[13]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[13]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[14]_i_1__0 
       (.I0(converge_cnt0[14]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[14]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[15]_i_1__0 
       (.I0(converge_cnt0[15]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[15]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[16]_i_1__0 
       (.I0(converge_cnt0[16]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[16]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[17]_i_1__0 
       (.I0(converge_cnt0[17]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[17]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[18]_i_1__0 
       (.I0(converge_cnt0[18]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[18]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[19]_i_1__0 
       (.I0(converge_cnt0[19]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[19]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[1]_i_1__0 
       (.I0(converge_cnt0[1]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[1]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[20]_i_1__0 
       (.I0(converge_cnt0[20]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[20]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[21]_i_1__0 
       (.I0(converge_cnt0[21]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[21]));
  (* SOFT_HLUTNM = "soft_lutpair1829" *) 
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[2]_i_1__0 
       (.I0(converge_cnt0[2]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[2]));
  (* SOFT_HLUTNM = "soft_lutpair1828" *) 
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[3]_i_1__0 
       (.I0(converge_cnt0[3]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[3]));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[3]_i_3__0 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .O(\converge_cnt[3]_i_3__0_n_0 ));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[4]_i_1__0 
       (.I0(converge_cnt0[4]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[4]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[5]_i_1__0 
       (.I0(converge_cnt0[5]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[5]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[6]_i_1__0 
       (.I0(converge_cnt0[6]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[6]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[7]_i_1__0 
       (.I0(converge_cnt0[7]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[7]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[8]_i_1__0 
       (.I0(converge_cnt0[8]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[8]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[9]_i_1__0 
       (.I0(converge_cnt0[9]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[9]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[0]),
        .Q(\converge_cnt_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[10]),
        .Q(\converge_cnt_reg_n_0_[10] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[11]),
        .Q(\converge_cnt_reg_n_0_[11] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[11]_i_2__0 
       (.CI(\converge_cnt_reg[7]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[11]_i_2__0_n_0 ,\converge_cnt_reg[11]_i_2__0_n_1 ,\converge_cnt_reg[11]_i_2__0_n_2 ,\converge_cnt_reg[11]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[11:8]),
        .S({\converge_cnt_reg_n_0_[11] ,\converge_cnt_reg_n_0_[10] ,\converge_cnt_reg_n_0_[9] ,\converge_cnt_reg_n_0_[8] }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[12]),
        .Q(\converge_cnt_reg_n_0_[12] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[13]),
        .Q(\converge_cnt_reg_n_0_[13] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[14]),
        .Q(\converge_cnt_reg_n_0_[14] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[15]),
        .Q(\converge_cnt_reg_n_0_[15] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[15]_i_2__0 
       (.CI(\converge_cnt_reg[11]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[15]_i_2__0_n_0 ,\converge_cnt_reg[15]_i_2__0_n_1 ,\converge_cnt_reg[15]_i_2__0_n_2 ,\converge_cnt_reg[15]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[15:12]),
        .S({\converge_cnt_reg_n_0_[15] ,\converge_cnt_reg_n_0_[14] ,\converge_cnt_reg_n_0_[13] ,\converge_cnt_reg_n_0_[12] }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[16]),
        .Q(\converge_cnt_reg_n_0_[16] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[17]),
        .Q(\converge_cnt_reg_n_0_[17] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[18]),
        .Q(\converge_cnt_reg_n_0_[18] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[19]),
        .Q(\converge_cnt_reg_n_0_[19] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[19]_i_2__0 
       (.CI(\converge_cnt_reg[15]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[19]_i_2__0_n_0 ,\converge_cnt_reg[19]_i_2__0_n_1 ,\converge_cnt_reg[19]_i_2__0_n_2 ,\converge_cnt_reg[19]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[19:16]),
        .S({\converge_cnt_reg_n_0_[19] ,\converge_cnt_reg_n_0_[18] ,\converge_cnt_reg_n_0_[17] ,\converge_cnt_reg_n_0_[16] }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[1]),
        .Q(\converge_cnt_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[20]),
        .Q(\converge_cnt_reg_n_0_[20] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[21]),
        .Q(\converge_cnt_reg_n_0_[21] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[21]_i_2__0 
       (.CI(\converge_cnt_reg[19]_i_2__0_n_0 ),
        .CO({\NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED [3:1],\converge_cnt_reg[21]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED [3:2],converge_cnt0[21:20]}),
        .S({1'b0,1'b0,\converge_cnt_reg_n_0_[21] ,\converge_cnt_reg_n_0_[20] }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[2]),
        .Q(\converge_cnt_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[3]),
        .Q(\converge_cnt_reg_n_0_[3] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[3]_i_2__0 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[3]_i_2__0_n_0 ,\converge_cnt_reg[3]_i_2__0_n_1 ,\converge_cnt_reg[3]_i_2__0_n_2 ,\converge_cnt_reg[3]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\converge_cnt_reg_n_0_[0] }),
        .O(converge_cnt0[3:0]),
        .S({\converge_cnt_reg_n_0_[3] ,\converge_cnt_reg_n_0_[2] ,\converge_cnt_reg_n_0_[1] ,\converge_cnt[3]_i_3__0_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[4]),
        .Q(\converge_cnt_reg_n_0_[4] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[5]),
        .Q(\converge_cnt_reg_n_0_[5] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[6]),
        .Q(\converge_cnt_reg_n_0_[6] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[7]),
        .Q(\converge_cnt_reg_n_0_[7] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[7]_i_2__0 
       (.CI(\converge_cnt_reg[3]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[7]_i_2__0_n_0 ,\converge_cnt_reg[7]_i_2__0_n_1 ,\converge_cnt_reg[7]_i_2__0_n_2 ,\converge_cnt_reg[7]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[7:4]),
        .S({\converge_cnt_reg_n_0_[7] ,\converge_cnt_reg_n_0_[6] ,\converge_cnt_reg_n_0_[5] ,\converge_cnt_reg_n_0_[4] }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[8]),
        .Q(\converge_cnt_reg_n_0_[8] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[9]),
        .Q(\converge_cnt_reg_n_0_[9] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[0] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [0]),
        .Q(fs_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [1]),
        .Q(fs_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [2]),
        .Q(fs_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[3] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [3]),
        .Q(fs_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[4] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [4]),
        .Q(fs_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[5] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [5]),
        .Q(fs_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[0] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[0]),
        .Q(fs_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[1]),
        .Q(fs_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[2]),
        .Q(fs_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[3] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[3]),
        .Q(fs_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[4] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[4]),
        .Q(fs_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[5] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[5]),
        .Q(fs_reg2[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[0] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [0]),
        .Q(lf_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [1]),
        .Q(lf_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [2]),
        .Q(lf_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[3] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [3]),
        .Q(lf_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[4] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [4]),
        .Q(lf_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[5] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [5]),
        .Q(lf_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[0] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[0]),
        .Q(lf_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[1]),
        .Q(lf_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[2]),
        .Q(lf_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[3] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[3]),
        .Q(lf_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[4] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[4]),
        .Q(lf_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[5] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[5]),
        .Q(lf_reg2[5]),
        .R(rst_cpllreset));
  LUT2 #(
    .INIT(4'h8)) 
    new_txcoeff_done_i_1__0
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .O(new_txcoeff_done));
  FDRE #(
    .INIT(1'b0)) 
    new_txcoeff_done_reg
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(new_txcoeff_done),
        .Q(rxeqscan_new_txcoeff_done),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE new_txcoeff_req_reg1_reg
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1_reg_0),
        .Q(new_txcoeff_req_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE new_txcoeff_req_reg2_reg
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1),
        .Q(new_txcoeff_req_reg2),
        .R(rst_cpllreset));
  LUT3 #(
    .INIT(8'hEA)) 
    preset_done_i_1__0
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(preset_done));
  FDRE #(
    .INIT(1'b0)) 
    preset_done_reg
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(preset_done),
        .Q(rxeqscan_preset_done),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg1_reg[0] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\preset_reg1_reg[2]_0 [0]),
        .Q(preset_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg1_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\preset_reg1_reg[2]_0 [1]),
        .Q(preset_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg1_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\preset_reg1_reg[2]_0 [2]),
        .Q(preset_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg2_reg[0] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(preset_reg1[0]),
        .Q(preset_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg2_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(preset_reg1[1]),
        .Q(preset_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg2_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(preset_reg1[2]),
        .Q(preset_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE preset_valid_reg1_reg
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(rxeq_preset_valid),
        .Q(preset_valid_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE preset_valid_reg2_reg
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(preset_valid_reg1),
        .Q(preset_valid_reg2),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'hA800FFFFA8000000)) 
    rxeq_adapt_done_i_1__0
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(rxeq_adapt_done_reg_reg_1),
        .I2(rxeqscan_adapt_done),
        .I3(Q[3]),
        .I4(rxeq_adapt_done_reg),
        .I5(eq_rxeq_adapt_done_1),
        .O(new_txcoeff_done_reg_0));
  LUT6 #(
    .INIT(64'hFF00FF33AA00A800)) 
    rxeq_adapt_done_reg_i_1__0
       (.I0(rxeqscan_adapt_done),
        .I1(rxeq_adapt_done_reg_reg),
        .I2(rxeqscan_new_txcoeff_done),
        .I3(Q[3]),
        .I4(rxeq_adapt_done_reg_reg_0),
        .I5(rxeq_adapt_done_reg_reg_1),
        .O(adapt_done_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair1830" *) 
  LUT2 #(
    .INIT(4'h2)) 
    rxeq_new_txcoeff_req_i_1__0
       (.I0(Q[3]),
        .I1(rxeqscan_new_txcoeff_done),
        .O(rxeq_new_txcoeff_req));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[0] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [0]),
        .Q(txcoeff_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[10] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [10]),
        .Q(txcoeff_reg1[10]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[11] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [11]),
        .Q(txcoeff_reg1[11]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[12] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [12]),
        .Q(txcoeff_reg1[12]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[13] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [13]),
        .Q(txcoeff_reg1[13]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[14] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [14]),
        .Q(txcoeff_reg1[14]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[15] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [15]),
        .Q(txcoeff_reg1[15]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[16] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [16]),
        .Q(txcoeff_reg1[16]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[17] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [17]),
        .Q(txcoeff_reg1[17]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [1]),
        .Q(txcoeff_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [2]),
        .Q(txcoeff_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[3] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [3]),
        .Q(txcoeff_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[4] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [4]),
        .Q(txcoeff_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[5] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [5]),
        .Q(txcoeff_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[6] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [6]),
        .Q(txcoeff_reg1[6]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[7] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [7]),
        .Q(txcoeff_reg1[7]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[8] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [8]),
        .Q(txcoeff_reg1[8]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[9] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [9]),
        .Q(txcoeff_reg1[9]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[0] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[0]),
        .Q(txcoeff_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[10] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[10]),
        .Q(txcoeff_reg2[10]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[11] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[11]),
        .Q(txcoeff_reg2[11]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[12] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[12]),
        .Q(txcoeff_reg2[12]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[13] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[13]),
        .Q(txcoeff_reg2[13]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[14] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[14]),
        .Q(txcoeff_reg2[14]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[15] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[15]),
        .Q(txcoeff_reg2[15]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[16] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[16]),
        .Q(txcoeff_reg2[16]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[17] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[17]),
        .Q(txcoeff_reg2[17]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[1]),
        .Q(txcoeff_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[2]),
        .Q(txcoeff_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[3] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[3]),
        .Q(txcoeff_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[4] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[4]),
        .Q(txcoeff_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[5] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[5]),
        .Q(txcoeff_reg2[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[6] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[6]),
        .Q(txcoeff_reg2[6]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[7] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[7]),
        .Q(txcoeff_reg2[7]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[8] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[8]),
        .Q(txcoeff_reg2[8]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[9] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[9]),
        .Q(txcoeff_reg2[9]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg1_reg[0] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txpreset_reg1_reg[3]_0 [0]),
        .Q(txpreset_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg1_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txpreset_reg1_reg[3]_0 [1]),
        .Q(txpreset_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg1_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txpreset_reg1_reg[3]_0 [2]),
        .Q(txpreset_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg1_reg[3] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txpreset_reg1_reg[3]_0 [3]),
        .Q(txpreset_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg2_reg[0] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txpreset_reg1[0]),
        .Q(txpreset_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg2_reg[1] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txpreset_reg1[1]),
        .Q(txpreset_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg2_reg[2] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txpreset_reg1[2]),
        .Q(txpreset_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg2_reg[3] 
       (.C(\lf_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txpreset_reg1[3]),
        .Q(txpreset_reg2[3]),
        .R(rst_cpllreset));
endmodule

(* ORIG_REF_NAME = "xdma_0_pcie2_ip_rxeq_scan" *) 
module xdma_0_pcie2_ip_rxeq_scan_37
   (adapt_done_reg_0,
    new_txcoeff_done_reg_0,
    D,
    rxeq_new_txcoeff_req,
    rst_cpllreset,
    new_txcoeff_req_reg1_reg_0,
    \fs_reg2_reg[5]_0 ,
    rxeq_preset_valid,
    out,
    rxeq_adapt_done_reg_reg,
    Q,
    rxeq_adapt_done_reg_reg_0,
    rxeq_adapt_done_reg_reg_1,
    rxeq_adapt_done_reg,
    eq_rxeq_adapt_done_0,
    \FSM_onehot_fsm_rx_reg[5] ,
    \preset_reg1_reg[2]_0 ,
    \txpreset_reg1_reg[3]_0 ,
    \txcoeff_reg1_reg[17]_0 ,
    \fs_reg1_reg[5]_0 ,
    \lf_reg1_reg[5]_0 );
  output adapt_done_reg_0;
  output new_txcoeff_done_reg_0;
  output [2:0]D;
  output rxeq_new_txcoeff_req;
  input rst_cpllreset;
  input new_txcoeff_req_reg1_reg_0;
  input \fs_reg2_reg[5]_0 ;
  input rxeq_preset_valid;
  input [1:0]out;
  input rxeq_adapt_done_reg_reg;
  input [4:0]Q;
  input rxeq_adapt_done_reg_reg_0;
  input rxeq_adapt_done_reg_reg_1;
  input rxeq_adapt_done_reg;
  input eq_rxeq_adapt_done_0;
  input [2:0]\FSM_onehot_fsm_rx_reg[5] ;
  input [2:0]\preset_reg1_reg[2]_0 ;
  input [3:0]\txpreset_reg1_reg[3]_0 ;
  input [17:0]\txcoeff_reg1_reg[17]_0 ;
  input [5:0]\fs_reg1_reg[5]_0 ;
  input [5:0]\lf_reg1_reg[5]_0 ;

  wire [2:0]D;
  wire \FSM_onehot_fsm[1]_i_1_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm[3]_i_2_n_0 ;
  wire \FSM_onehot_fsm[4]_i_10_n_0 ;
  wire \FSM_onehot_fsm[4]_i_11_n_0 ;
  wire \FSM_onehot_fsm[4]_i_12_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_2_n_0 ;
  wire \FSM_onehot_fsm[4]_i_3_n_0 ;
  wire \FSM_onehot_fsm[4]_i_4_n_0 ;
  wire \FSM_onehot_fsm[4]_i_5_n_0 ;
  wire \FSM_onehot_fsm[4]_i_6_n_0 ;
  wire \FSM_onehot_fsm[4]_i_7_n_0 ;
  wire \FSM_onehot_fsm[4]_i_8_n_0 ;
  wire \FSM_onehot_fsm[4]_i_9_n_0 ;
  wire \FSM_onehot_fsm_reg_n_0_[1] ;
  wire \FSM_onehot_fsm_reg_n_0_[2] ;
  wire \FSM_onehot_fsm_reg_n_0_[3] ;
  wire \FSM_onehot_fsm_reg_n_0_[4] ;
  wire \FSM_onehot_fsm_rx[6]_i_2_n_0 ;
  wire [2:0]\FSM_onehot_fsm_rx_reg[5] ;
  wire [4:0]Q;
  wire adapt_done;
  wire adapt_done_cnt_i_1_n_0;
  wire adapt_done_cnt_i_2_n_0;
  wire adapt_done_cnt_reg_n_0;
  wire adapt_done_reg_0;
  wire [21:0]converge_cnt;
  wire [21:0]converge_cnt0;
  wire \converge_cnt[3]_i_3_n_0 ;
  wire \converge_cnt_reg[11]_i_2_n_0 ;
  wire \converge_cnt_reg[11]_i_2_n_1 ;
  wire \converge_cnt_reg[11]_i_2_n_2 ;
  wire \converge_cnt_reg[11]_i_2_n_3 ;
  wire \converge_cnt_reg[15]_i_2_n_0 ;
  wire \converge_cnt_reg[15]_i_2_n_1 ;
  wire \converge_cnt_reg[15]_i_2_n_2 ;
  wire \converge_cnt_reg[15]_i_2_n_3 ;
  wire \converge_cnt_reg[19]_i_2_n_0 ;
  wire \converge_cnt_reg[19]_i_2_n_1 ;
  wire \converge_cnt_reg[19]_i_2_n_2 ;
  wire \converge_cnt_reg[19]_i_2_n_3 ;
  wire \converge_cnt_reg[21]_i_2_n_3 ;
  wire \converge_cnt_reg[3]_i_2_n_0 ;
  wire \converge_cnt_reg[3]_i_2_n_1 ;
  wire \converge_cnt_reg[3]_i_2_n_2 ;
  wire \converge_cnt_reg[3]_i_2_n_3 ;
  wire \converge_cnt_reg[7]_i_2_n_0 ;
  wire \converge_cnt_reg[7]_i_2_n_1 ;
  wire \converge_cnt_reg[7]_i_2_n_2 ;
  wire \converge_cnt_reg[7]_i_2_n_3 ;
  wire \converge_cnt_reg_n_0_[0] ;
  wire \converge_cnt_reg_n_0_[10] ;
  wire \converge_cnt_reg_n_0_[11] ;
  wire \converge_cnt_reg_n_0_[12] ;
  wire \converge_cnt_reg_n_0_[13] ;
  wire \converge_cnt_reg_n_0_[14] ;
  wire \converge_cnt_reg_n_0_[15] ;
  wire \converge_cnt_reg_n_0_[16] ;
  wire \converge_cnt_reg_n_0_[17] ;
  wire \converge_cnt_reg_n_0_[18] ;
  wire \converge_cnt_reg_n_0_[19] ;
  wire \converge_cnt_reg_n_0_[1] ;
  wire \converge_cnt_reg_n_0_[20] ;
  wire \converge_cnt_reg_n_0_[21] ;
  wire \converge_cnt_reg_n_0_[2] ;
  wire \converge_cnt_reg_n_0_[3] ;
  wire \converge_cnt_reg_n_0_[4] ;
  wire \converge_cnt_reg_n_0_[5] ;
  wire \converge_cnt_reg_n_0_[6] ;
  wire \converge_cnt_reg_n_0_[7] ;
  wire \converge_cnt_reg_n_0_[8] ;
  wire \converge_cnt_reg_n_0_[9] ;
  wire eq_rxeq_adapt_done_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg1;
  wire [5:0]\fs_reg1_reg[5]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]fs_reg2;
  wire \fs_reg2_reg[5]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg1;
  wire [5:0]\lf_reg1_reg[5]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [5:0]lf_reg2;
  wire new_txcoeff_done;
  wire new_txcoeff_done_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg1;
  wire new_txcoeff_req_reg1_reg_0;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire new_txcoeff_req_reg2;
  wire [1:0]out;
  wire preset_done;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg1;
  wire [2:0]\preset_reg1_reg[2]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [2:0]preset_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg1;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire preset_valid_reg2;
  wire rst_cpllreset;
  wire rxeq_adapt_done_reg;
  wire rxeq_adapt_done_reg_reg;
  wire rxeq_adapt_done_reg_reg_0;
  wire rxeq_adapt_done_reg_reg_1;
  wire rxeq_new_txcoeff_req;
  wire rxeq_preset_valid;
  wire rxeqscan_adapt_done;
  wire rxeqscan_new_txcoeff_done;
  wire rxeqscan_preset_done;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg1;
  wire [17:0]\txcoeff_reg1_reg[17]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [17:0]txcoeff_reg2;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg1;
  wire [3:0]\txpreset_reg1_reg[3]_0 ;
  (* SHIFT_EXTRACT = "NO" *) (* async_reg = "true" *) wire [3:0]txpreset_reg2;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h0001FF01AAABFFFB)) 
    \FSM_onehot_fsm[1]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(preset_valid_reg2),
        .I5(new_txcoeff_req_reg2),
        .O(\FSM_onehot_fsm[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \FSM_onehot_fsm[2]_i_1__1 
       (.I0(preset_valid_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[2]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h4F444444)) 
    \FSM_onehot_fsm[3]_i_1__2 
       (.I0(\FSM_onehot_fsm[3]_i_2_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_2_n_0 ),
        .I2(preset_valid_reg2),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1780" *) 
  LUT4 #(
    .INIT(16'h04FF)) 
    \FSM_onehot_fsm[3]_i_2 
       (.I0(adapt_done_cnt_reg_n_0),
        .I1(out[1]),
        .I2(out[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF55750000)) 
    \FSM_onehot_fsm[4]_i_1 
       (.I0(\FSM_onehot_fsm[4]_i_2_n_0 ),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[1]),
        .I3(out[0]),
        .I4(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I5(new_txcoeff_done),
        .O(\FSM_onehot_fsm[4]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_onehot_fsm[4]_i_10 
       (.I0(out[1]),
        .I1(out[0]),
        .O(\FSM_onehot_fsm[4]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \FSM_onehot_fsm[4]_i_11 
       (.I0(\converge_cnt_reg_n_0_[16] ),
        .I1(\converge_cnt_reg_n_0_[17] ),
        .I2(\converge_cnt_reg_n_0_[18] ),
        .I3(\converge_cnt_reg_n_0_[19] ),
        .O(\FSM_onehot_fsm[4]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'hFFF7)) 
    \FSM_onehot_fsm[4]_i_12 
       (.I0(\converge_cnt_reg_n_0_[21] ),
        .I1(\converge_cnt_reg_n_0_[10] ),
        .I2(\converge_cnt_reg_n_0_[2] ),
        .I3(\converge_cnt_reg_n_0_[12] ),
        .O(\FSM_onehot_fsm[4]_i_12_n_0 ));
  LUT5 #(
    .INIT(32'hFEF0FEFE)) 
    \FSM_onehot_fsm[4]_i_2 
       (.I0(\FSM_onehot_fsm[4]_i_3_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_4_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_5_n_0 ),
        .I3(\FSM_onehot_fsm[4]_i_6_n_0 ),
        .I4(\FSM_onehot_fsm[4]_i_7_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFBFF)) 
    \FSM_onehot_fsm[4]_i_3 
       (.I0(\converge_cnt_reg_n_0_[21] ),
        .I1(\converge_cnt_reg_n_0_[15] ),
        .I2(\converge_cnt_reg_n_0_[3] ),
        .I3(\converge_cnt_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm[4]_i_8_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \FSM_onehot_fsm[4]_i_4 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .I1(\converge_cnt_reg_n_0_[0] ),
        .I2(\converge_cnt_reg_n_0_[8] ),
        .I3(\converge_cnt_reg_n_0_[20] ),
        .I4(\FSM_onehot_fsm[4]_i_9_n_0 ),
        .I5(\FSM_onehot_fsm[4]_i_10_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \FSM_onehot_fsm[4]_i_5 
       (.I0(\converge_cnt_reg_n_0_[4] ),
        .I1(\converge_cnt_reg_n_0_[5] ),
        .I2(\converge_cnt_reg_n_0_[7] ),
        .I3(\converge_cnt_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm[4]_i_11_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF7FF)) 
    \FSM_onehot_fsm[4]_i_6 
       (.I0(\converge_cnt_reg_n_0_[13] ),
        .I1(\converge_cnt_reg_n_0_[9] ),
        .I2(\converge_cnt_reg_n_0_[20] ),
        .I3(\converge_cnt_reg_n_0_[3] ),
        .I4(\FSM_onehot_fsm[4]_i_12_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    \FSM_onehot_fsm[4]_i_7 
       (.I0(\converge_cnt_reg_n_0_[14] ),
        .I1(\converge_cnt_reg_n_0_[8] ),
        .I2(\converge_cnt_reg_n_0_[15] ),
        .I3(\converge_cnt_reg_n_0_[0] ),
        .I4(\FSM_onehot_fsm[4]_i_10_n_0 ),
        .I5(\FSM_onehot_fsm[4]_i_9_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'hFFF7)) 
    \FSM_onehot_fsm[4]_i_8 
       (.I0(\converge_cnt_reg_n_0_[9] ),
        .I1(\converge_cnt_reg_n_0_[14] ),
        .I2(\converge_cnt_reg_n_0_[10] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .O(\FSM_onehot_fsm[4]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_onehot_fsm[4]_i_9 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .I1(\converge_cnt_reg_n_0_[11] ),
        .O(\FSM_onehot_fsm[4]_i_9_n_0 ));
  (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .S(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[2] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(rst_cpllreset));
  (* FSM_ENCODED_STATES = "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[4] ),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h40FF4040)) 
    \FSM_onehot_fsm_rx[2]_i_1 
       (.I0(out[1]),
        .I1(out[0]),
        .I2(Q[0]),
        .I3(rxeqscan_preset_done),
        .I4(Q[1]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hF444444444444444)) 
    \FSM_onehot_fsm_rx[5]_i_1 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(Q[3]),
        .I2(\FSM_onehot_fsm_rx_reg[5] [2]),
        .I3(\FSM_onehot_fsm_rx_reg[5] [1]),
        .I4(\FSM_onehot_fsm_rx_reg[5] [0]),
        .I5(Q[2]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFE0E0E0)) 
    \FSM_onehot_fsm_rx[6]_i_1 
       (.I0(out[0]),
        .I1(out[1]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(rxeqscan_preset_done),
        .I5(\FSM_onehot_fsm_rx[6]_i_2_n_0 ),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair1781" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_fsm_rx[6]_i_2 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(Q[3]),
        .O(\FSM_onehot_fsm_rx[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000AAAFFFF0800)) 
    adapt_done_cnt_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .I5(adapt_done_cnt_i_2_n_0),
        .O(adapt_done_cnt_i_1_n_0));
  LUT5 #(
    .INIT(32'h00FF0101)) 
    adapt_done_cnt_i_2
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .O(adapt_done_cnt_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_cnt_reg
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(adapt_done_cnt_i_1_n_0),
        .Q(adapt_done_cnt_reg_n_0),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'hF8000000)) 
    adapt_done_i_1
       (.I0(out[0]),
        .I1(out[1]),
        .I2(adapt_done_cnt_reg_n_0),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .O(adapt_done));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_reg
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(adapt_done),
        .Q(rxeqscan_adapt_done),
        .R(rst_cpllreset));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[0]_i_1 
       (.I0(converge_cnt0[0]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[0]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[10]_i_1 
       (.I0(converge_cnt0[10]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[10]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[11]_i_1 
       (.I0(converge_cnt0[11]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[11]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[12]_i_1 
       (.I0(converge_cnt0[12]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[12]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[13]_i_1 
       (.I0(converge_cnt0[13]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[13]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[14]_i_1 
       (.I0(converge_cnt0[14]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[14]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[15]_i_1 
       (.I0(converge_cnt0[15]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[15]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[16]_i_1 
       (.I0(converge_cnt0[16]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[16]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[17]_i_1 
       (.I0(converge_cnt0[17]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[17]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[18]_i_1 
       (.I0(converge_cnt0[18]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[18]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[19]_i_1 
       (.I0(converge_cnt0[19]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[19]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[1]_i_1 
       (.I0(converge_cnt0[1]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[1]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[20]_i_1 
       (.I0(converge_cnt0[20]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[20]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[21]_i_1 
       (.I0(converge_cnt0[21]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[21]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[2]_i_1 
       (.I0(converge_cnt0[2]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[2]));
  (* SOFT_HLUTNM = "soft_lutpair1780" *) 
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[3]_i_1 
       (.I0(converge_cnt0[3]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[3]));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[3]_i_3 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .O(\converge_cnt[3]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[4]_i_1 
       (.I0(converge_cnt0[4]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[4]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[5]_i_1 
       (.I0(converge_cnt0[5]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[5]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[6]_i_1 
       (.I0(converge_cnt0[6]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[6]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[7]_i_1 
       (.I0(converge_cnt0[7]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[7]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[8]_i_1 
       (.I0(converge_cnt0[8]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[8]));
  LUT5 #(
    .INIT(32'h88888088)) 
    \converge_cnt[9]_i_1 
       (.I0(converge_cnt0[9]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[0]),
        .I3(out[1]),
        .I4(adapt_done_cnt_reg_n_0),
        .O(converge_cnt[9]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[0]),
        .Q(\converge_cnt_reg_n_0_[0] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[10]),
        .Q(\converge_cnt_reg_n_0_[10] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[11]),
        .Q(\converge_cnt_reg_n_0_[11] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[11]_i_2 
       (.CI(\converge_cnt_reg[7]_i_2_n_0 ),
        .CO({\converge_cnt_reg[11]_i_2_n_0 ,\converge_cnt_reg[11]_i_2_n_1 ,\converge_cnt_reg[11]_i_2_n_2 ,\converge_cnt_reg[11]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[11:8]),
        .S({\converge_cnt_reg_n_0_[11] ,\converge_cnt_reg_n_0_[10] ,\converge_cnt_reg_n_0_[9] ,\converge_cnt_reg_n_0_[8] }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[12]),
        .Q(\converge_cnt_reg_n_0_[12] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[13]),
        .Q(\converge_cnt_reg_n_0_[13] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[14]),
        .Q(\converge_cnt_reg_n_0_[14] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[15]),
        .Q(\converge_cnt_reg_n_0_[15] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[15]_i_2 
       (.CI(\converge_cnt_reg[11]_i_2_n_0 ),
        .CO({\converge_cnt_reg[15]_i_2_n_0 ,\converge_cnt_reg[15]_i_2_n_1 ,\converge_cnt_reg[15]_i_2_n_2 ,\converge_cnt_reg[15]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[15:12]),
        .S({\converge_cnt_reg_n_0_[15] ,\converge_cnt_reg_n_0_[14] ,\converge_cnt_reg_n_0_[13] ,\converge_cnt_reg_n_0_[12] }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[16]),
        .Q(\converge_cnt_reg_n_0_[16] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[17]),
        .Q(\converge_cnt_reg_n_0_[17] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[18]),
        .Q(\converge_cnt_reg_n_0_[18] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[19]),
        .Q(\converge_cnt_reg_n_0_[19] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[19]_i_2 
       (.CI(\converge_cnt_reg[15]_i_2_n_0 ),
        .CO({\converge_cnt_reg[19]_i_2_n_0 ,\converge_cnt_reg[19]_i_2_n_1 ,\converge_cnt_reg[19]_i_2_n_2 ,\converge_cnt_reg[19]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[19:16]),
        .S({\converge_cnt_reg_n_0_[19] ,\converge_cnt_reg_n_0_[18] ,\converge_cnt_reg_n_0_[17] ,\converge_cnt_reg_n_0_[16] }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[1]),
        .Q(\converge_cnt_reg_n_0_[1] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[20]),
        .Q(\converge_cnt_reg_n_0_[20] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[21]),
        .Q(\converge_cnt_reg_n_0_[21] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[21]_i_2 
       (.CI(\converge_cnt_reg[19]_i_2_n_0 ),
        .CO({\NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED [3:1],\converge_cnt_reg[21]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED [3:2],converge_cnt0[21:20]}),
        .S({1'b0,1'b0,\converge_cnt_reg_n_0_[21] ,\converge_cnt_reg_n_0_[20] }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[2]),
        .Q(\converge_cnt_reg_n_0_[2] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[3]),
        .Q(\converge_cnt_reg_n_0_[3] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[3]_i_2 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[3]_i_2_n_0 ,\converge_cnt_reg[3]_i_2_n_1 ,\converge_cnt_reg[3]_i_2_n_2 ,\converge_cnt_reg[3]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\converge_cnt_reg_n_0_[0] }),
        .O(converge_cnt0[3:0]),
        .S({\converge_cnt_reg_n_0_[3] ,\converge_cnt_reg_n_0_[2] ,\converge_cnt_reg_n_0_[1] ,\converge_cnt[3]_i_3_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[4]),
        .Q(\converge_cnt_reg_n_0_[4] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[5]),
        .Q(\converge_cnt_reg_n_0_[5] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[6]),
        .Q(\converge_cnt_reg_n_0_[6] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[7]),
        .Q(\converge_cnt_reg_n_0_[7] ),
        .R(rst_cpllreset));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \converge_cnt_reg[7]_i_2 
       (.CI(\converge_cnt_reg[3]_i_2_n_0 ),
        .CO({\converge_cnt_reg[7]_i_2_n_0 ,\converge_cnt_reg[7]_i_2_n_1 ,\converge_cnt_reg[7]_i_2_n_2 ,\converge_cnt_reg[7]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[7:4]),
        .S({\converge_cnt_reg_n_0_[7] ,\converge_cnt_reg_n_0_[6] ,\converge_cnt_reg_n_0_[5] ,\converge_cnt_reg_n_0_[4] }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[8]),
        .Q(\converge_cnt_reg_n_0_[8] ),
        .R(rst_cpllreset));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(converge_cnt[9]),
        .Q(\converge_cnt_reg_n_0_[9] ),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[0] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [0]),
        .Q(fs_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [1]),
        .Q(fs_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [2]),
        .Q(fs_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[3] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [3]),
        .Q(fs_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[4] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [4]),
        .Q(fs_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg1_reg[5] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\fs_reg1_reg[5]_0 [5]),
        .Q(fs_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[0] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[0]),
        .Q(fs_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[1]),
        .Q(fs_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[2]),
        .Q(fs_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[3] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[3]),
        .Q(fs_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[4] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[4]),
        .Q(fs_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \fs_reg2_reg[5] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(fs_reg1[5]),
        .Q(fs_reg2[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[0] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [0]),
        .Q(lf_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [1]),
        .Q(lf_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [2]),
        .Q(lf_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[3] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [3]),
        .Q(lf_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[4] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [4]),
        .Q(lf_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg1_reg[5] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\lf_reg1_reg[5]_0 [5]),
        .Q(lf_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[0] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[0]),
        .Q(lf_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[1]),
        .Q(lf_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[2]),
        .Q(lf_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[3] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[3]),
        .Q(lf_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[4] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[4]),
        .Q(lf_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \lf_reg2_reg[5] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(lf_reg1[5]),
        .Q(lf_reg2[5]),
        .R(rst_cpllreset));
  LUT2 #(
    .INIT(4'h8)) 
    new_txcoeff_done_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .O(new_txcoeff_done));
  FDRE #(
    .INIT(1'b0)) 
    new_txcoeff_done_reg
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(new_txcoeff_done),
        .Q(rxeqscan_new_txcoeff_done),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE new_txcoeff_req_reg1_reg
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1_reg_0),
        .Q(new_txcoeff_req_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE new_txcoeff_req_reg2_reg
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1),
        .Q(new_txcoeff_req_reg2),
        .R(rst_cpllreset));
  LUT3 #(
    .INIT(8'hEA)) 
    preset_done_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(preset_done));
  FDRE #(
    .INIT(1'b0)) 
    preset_done_reg
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(preset_done),
        .Q(rxeqscan_preset_done),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg1_reg[0] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\preset_reg1_reg[2]_0 [0]),
        .Q(preset_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg1_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\preset_reg1_reg[2]_0 [1]),
        .Q(preset_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg1_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\preset_reg1_reg[2]_0 [2]),
        .Q(preset_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg2_reg[0] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(preset_reg1[0]),
        .Q(preset_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg2_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(preset_reg1[1]),
        .Q(preset_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \preset_reg2_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(preset_reg1[2]),
        .Q(preset_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE preset_valid_reg1_reg
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(rxeq_preset_valid),
        .Q(preset_valid_reg1),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE preset_valid_reg2_reg
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(preset_valid_reg1),
        .Q(preset_valid_reg2),
        .R(rst_cpllreset));
  LUT6 #(
    .INIT(64'hA800FFFFA8000000)) 
    rxeq_adapt_done_i_1
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(rxeq_adapt_done_reg_reg_1),
        .I2(rxeqscan_adapt_done),
        .I3(Q[3]),
        .I4(rxeq_adapt_done_reg),
        .I5(eq_rxeq_adapt_done_0),
        .O(new_txcoeff_done_reg_0));
  LUT6 #(
    .INIT(64'hFF00FF33AA00A800)) 
    rxeq_adapt_done_reg_i_1
       (.I0(rxeqscan_adapt_done),
        .I1(rxeq_adapt_done_reg_reg),
        .I2(rxeqscan_new_txcoeff_done),
        .I3(Q[3]),
        .I4(rxeq_adapt_done_reg_reg_0),
        .I5(rxeq_adapt_done_reg_reg_1),
        .O(adapt_done_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair1781" *) 
  LUT2 #(
    .INIT(4'h2)) 
    rxeq_new_txcoeff_req_i_1
       (.I0(Q[3]),
        .I1(rxeqscan_new_txcoeff_done),
        .O(rxeq_new_txcoeff_req));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[0] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [0]),
        .Q(txcoeff_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[10] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [10]),
        .Q(txcoeff_reg1[10]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[11] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [11]),
        .Q(txcoeff_reg1[11]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[12] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [12]),
        .Q(txcoeff_reg1[12]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[13] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [13]),
        .Q(txcoeff_reg1[13]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[14] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [14]),
        .Q(txcoeff_reg1[14]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[15] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [15]),
        .Q(txcoeff_reg1[15]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[16] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [16]),
        .Q(txcoeff_reg1[16]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[17] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [17]),
        .Q(txcoeff_reg1[17]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [1]),
        .Q(txcoeff_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [2]),
        .Q(txcoeff_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[3] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [3]),
        .Q(txcoeff_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[4] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [4]),
        .Q(txcoeff_reg1[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[5] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [5]),
        .Q(txcoeff_reg1[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[6] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [6]),
        .Q(txcoeff_reg1[6]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[7] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [7]),
        .Q(txcoeff_reg1[7]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[8] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [8]),
        .Q(txcoeff_reg1[8]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg1_reg[9] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txcoeff_reg1_reg[17]_0 [9]),
        .Q(txcoeff_reg1[9]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[0] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[0]),
        .Q(txcoeff_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[10] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[10]),
        .Q(txcoeff_reg2[10]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[11] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[11]),
        .Q(txcoeff_reg2[11]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[12] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[12]),
        .Q(txcoeff_reg2[12]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[13] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[13]),
        .Q(txcoeff_reg2[13]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[14] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[14]),
        .Q(txcoeff_reg2[14]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[15] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[15]),
        .Q(txcoeff_reg2[15]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[16] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[16]),
        .Q(txcoeff_reg2[16]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[17] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[17]),
        .Q(txcoeff_reg2[17]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[1]),
        .Q(txcoeff_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[2]),
        .Q(txcoeff_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[3] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[3]),
        .Q(txcoeff_reg2[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[4] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[4]),
        .Q(txcoeff_reg2[4]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[5] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[5]),
        .Q(txcoeff_reg2[5]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[6] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[6]),
        .Q(txcoeff_reg2[6]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[7] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[7]),
        .Q(txcoeff_reg2[7]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[8] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[8]),
        .Q(txcoeff_reg2[8]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txcoeff_reg2_reg[9] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txcoeff_reg1[9]),
        .Q(txcoeff_reg2[9]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg1_reg[0] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txpreset_reg1_reg[3]_0 [0]),
        .Q(txpreset_reg1[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg1_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txpreset_reg1_reg[3]_0 [1]),
        .Q(txpreset_reg1[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg1_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txpreset_reg1_reg[3]_0 [2]),
        .Q(txpreset_reg1[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg1_reg[3] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(\txpreset_reg1_reg[3]_0 [3]),
        .Q(txpreset_reg1[3]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg2_reg[0] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txpreset_reg1[0]),
        .Q(txpreset_reg2[0]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg2_reg[1] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txpreset_reg1[1]),
        .Q(txpreset_reg2[1]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg2_reg[2] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txpreset_reg1[2]),
        .Q(txpreset_reg2[2]),
        .R(rst_cpllreset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHIFT_EXTRACT = "NO" *) 
  FDRE \txpreset_reg2_reg[3] 
       (.C(\fs_reg2_reg[5]_0 ),
        .CE(1'b1),
        .D(txpreset_reg1[3]),
        .Q(txpreset_reg2[3]),
        .R(rst_cpllreset));
endmodule

module xdma_0_pcie2_to_pcie3_wrapper
   (pci_exp_txp,
    pci_exp_txn,
    CLK,
    user_reset_out,
    user_lnk_up,
    s_axis_tx_tready_o,
    m_axis_rx_tdata_o,
    m_axis_rx_tkeep_o,
    m_axis_rx_tlast_o,
    m_axis_rx_tvalid_o,
    m_axis_rx_tuser_o,
    fc_nph,
    cfg_mgmt_do,
    cfg_mgmt_rd_wr_done,
    cfg_dcommand,
    cfg_interrupt_mmenable,
    cfg_interrupt_msienable,
    cfg_to_turnoff_o,
    cfg_bus_number_o,
    cfg_device_number_o,
    cfg_function_number_o,
    \pcie_dma_in\.cfg_phy_link_down ,
    \pcie_dma_in\.pcie_rq_seq_num0 ,
    s_aresetn,
    \pcie_dma_in\.cfg_interrupt_sent ,
    \pcie_dma_in\.cfg_interrupt_msi_sent ,
    \m_axis_rq\.tready ,
    \pcie_dma_in\.pcie_rq_seq_num_vld0 ,
    \s_axis_rc\.tkeep ,
    \s_axis_rc\.tuser ,
    \s_axis_rc\.tlast ,
    \s_axis_rc\.tdata ,
    \s_axis_cq\.tdata ,
    \s_axis_cq\.tuser ,
    \s_axis_cq\.tvalid ,
    \s_axis_cq\.tlast ,
    \m_axis_cc\.tready ,
    out,
    \gtp_channel.gtpe2_channel_i ,
    pcie_block_i,
    pcie_block_i_0,
    pcie_block_i_1,
    pcie_block_i_2,
    \gtp_common.gtpe2_common_i ,
    reset_n_reg2_reg,
    \pcie_dma_out\.cfg_interrupt_int ,
    \pcie_dma_out\.cfg_interrupt_msi_int ,
    fc_sel_i,
    cfg_dsn_i,
    \m_axis_cc\.tlast ,
    m_axis_rx_tready_i,
    s_axis_tx_tlast_i,
    s_axis_tx_tvalid_i,
    tx_cfg_gnt_i,
    \pcie_dma_out\.pcie_cq_np_req ,
    rx_np_req_i,
    s_axis_tx_tuser_i,
    rx_np_ok_i,
    \pcie_dma_out\.cfg_fc_sel ,
    cfg_pm_force_state_i,
    cfg_pciecap_interrupt_msgnum_i,
    cfg_turnoff_ok_i,
    pl_directed_link_change_i,
    pl_directed_link_width_i,
    pl_directed_link_speed_i,
    pl_directed_link_auton_i,
    pl_upstream_prefer_deemph_i,
    cfg_aer_interrupt_msgnum_i,
    s_axis_tx_tdata_i,
    s_axis_tx_tkeep_i,
    pcie_block_i_3,
    cfg_mgmt_di_i,
    pcie_block_i_4,
    cfg_mgmt_dwaddr_i,
    cfg_err_tlp_cpl_header_i,
    cfg_interrupt_di_i,
    cfg_err_aer_headerlog_i,
    D,
    s_axis_rq_tuser,
    \m_axis_rq\.tlast ,
    \m_axis_rq\.tvalid ,
    \s_axis_rc\.tready ,
    \s_axis_cq\.tready ,
    \m_axis_cc\.tvalid ,
    \m_axis_cc\.tdata );
  output [1:0]pci_exp_txp;
  output [1:0]pci_exp_txn;
  output CLK;
  output user_reset_out;
  output user_lnk_up;
  output s_axis_tx_tready_o;
  output [63:0]m_axis_rx_tdata_o;
  output [3:0]m_axis_rx_tkeep_o;
  output m_axis_rx_tlast_o;
  output m_axis_rx_tvalid_o;
  output [13:0]m_axis_rx_tuser_o;
  output [7:0]fc_nph;
  output [31:0]cfg_mgmt_do;
  output cfg_mgmt_rd_wr_done;
  output [5:0]cfg_dcommand;
  output [2:0]cfg_interrupt_mmenable;
  output cfg_interrupt_msienable;
  output cfg_to_turnoff_o;
  output [7:0]cfg_bus_number_o;
  output [4:0]cfg_device_number_o;
  output [2:0]cfg_function_number_o;
  output \pcie_dma_in\.cfg_phy_link_down ;
  output [3:0]\pcie_dma_in\.pcie_rq_seq_num0 ;
  output s_aresetn;
  output \pcie_dma_in\.cfg_interrupt_sent ;
  output \pcie_dma_in\.cfg_interrupt_msi_sent ;
  output \m_axis_rq\.tready ;
  output \pcie_dma_in\.pcie_rq_seq_num_vld0 ;
  output [1:0]\s_axis_rc\.tkeep ;
  output [3:0]\s_axis_rc\.tuser ;
  output \s_axis_rc\.tlast ;
  output [63:0]\s_axis_rc\.tdata ;
  output [63:0]\s_axis_cq\.tdata ;
  output [4:0]\s_axis_cq\.tuser ;
  output \s_axis_cq\.tvalid ;
  output \s_axis_cq\.tlast ;
  output \m_axis_cc\.tready ;
  input [1:0]out;
  input [1:0]\gtp_channel.gtpe2_channel_i ;
  input [3:0]pcie_block_i;
  input pcie_block_i_0;
  input pcie_block_i_1;
  input pcie_block_i_2;
  input \gtp_common.gtpe2_common_i ;
  input reset_n_reg2_reg;
  input [0:0]\pcie_dma_out\.cfg_interrupt_int ;
  input [31:0]\pcie_dma_out\.cfg_interrupt_msi_int ;
  input [2:0]fc_sel_i;
  input [63:0]cfg_dsn_i;
  input \m_axis_cc\.tlast ;
  input m_axis_rx_tready_i;
  input s_axis_tx_tlast_i;
  input s_axis_tx_tvalid_i;
  input tx_cfg_gnt_i;
  input [0:0]\pcie_dma_out\.pcie_cq_np_req ;
  input rx_np_req_i;
  input [3:0]s_axis_tx_tuser_i;
  input rx_np_ok_i;
  input [0:0]\pcie_dma_out\.cfg_fc_sel ;
  input [1:0]cfg_pm_force_state_i;
  input [4:0]cfg_pciecap_interrupt_msgnum_i;
  input cfg_turnoff_ok_i;
  input [1:0]pl_directed_link_change_i;
  input [1:0]pl_directed_link_width_i;
  input pl_directed_link_speed_i;
  input pl_directed_link_auton_i;
  input pl_upstream_prefer_deemph_i;
  input [4:0]cfg_aer_interrupt_msgnum_i;
  input [63:0]s_axis_tx_tdata_i;
  input [0:0]s_axis_tx_tkeep_i;
  input [31:0]pcie_block_i_3;
  input [31:0]cfg_mgmt_di_i;
  input [9:0]pcie_block_i_4;
  input [9:0]cfg_mgmt_dwaddr_i;
  input [47:0]cfg_err_tlp_cpl_header_i;
  input [7:0]cfg_interrupt_di_i;
  input [127:0]cfg_err_aer_headerlog_i;
  input [63:0]D;
  input [11:0]s_axis_rq_tuser;
  input \m_axis_rq\.tlast ;
  input \m_axis_rq\.tvalid ;
  input [0:0]\s_axis_rc\.tready ;
  input [0:0]\s_axis_cq\.tready ;
  input \m_axis_cc\.tvalid ;
  input [63:0]\m_axis_cc\.tdata ;

  wire CLK;
  wire [63:0]D;
  wire [4:0]cfg_aer_interrupt_msgnum_i;
  wire [4:0]cfg_aer_interrupt_msgnum_mux;
  wire [7:0]cfg_bus_number_o;
  wire [5:0]cfg_dcommand;
  wire [4:0]cfg_device_number_o;
  wire [63:0]cfg_dsn_i;
  wire [127:0]cfg_err_aer_headerlog_i;
  wire [127:0]cfg_err_aer_headerlog_mux;
  wire [47:0]cfg_err_tlp_cpl_header_i;
  wire [47:0]cfg_err_tlp_cpl_header_mux;
  wire [2:0]cfg_function_number_o;
  wire [7:0]cfg_interrupt_di_i;
  wire [7:0]cfg_interrupt_di_mux;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire [31:0]cfg_mgmt_di_i;
  wire [31:0]cfg_mgmt_di_mux;
  wire [31:0]cfg_mgmt_do;
  wire [9:0]cfg_mgmt_dwaddr_i;
  wire [9:0]cfg_mgmt_dwaddr_mux;
  wire cfg_mgmt_rd_wr_done;
  wire [4:0]cfg_pciecap_interrupt_msgnum_i;
  wire [4:0]cfg_pciecap_interrupt_msgnum_mux;
  wire [1:0]cfg_pm_force_state_i;
  wire [1:0]cfg_pm_force_state_mux;
  wire cfg_to_turnoff_o;
  wire cfg_turnoff_ok_i;
  wire cfg_turnoff_ok_mux;
  wire dmaFlag;
  wire dmaFlag_i_1_n_0;
  wire [7:0]fc_nph;
  wire [2:0]fc_sel_i;
  wire [2:0]fc_sel_mux;
  wire g2ip_cfg_interrupt;
  wire g2ip_cfg_interrupt_assert;
  wire g2ip_cfg_interrupt_rdy;
  wire [1:0]\gtp_channel.gtpe2_channel_i ;
  wire \gtp_common.gtpe2_common_i ;
  wire [63:0]\m_axis_cc\.tdata ;
  wire \m_axis_cc\.tlast ;
  wire \m_axis_cc\.tready ;
  wire \m_axis_cc\.tvalid ;
  wire \m_axis_rq\.tlast ;
  wire \m_axis_rq\.tready ;
  wire \m_axis_rq\.tvalid ;
  wire [63:0]m_axis_rx_tdata_o;
  wire [3:0]m_axis_rx_tkeep_o;
  wire m_axis_rx_tlast_o;
  wire m_axis_rx_tready_i;
  wire m_axis_rx_tready_mux;
  wire [13:0]m_axis_rx_tuser_o;
  wire m_axis_rx_tvalid_o;
  wire [1:0]out;
  wire [1:0]pci_exp_txn;
  wire [1:0]pci_exp_txp;
  wire pcie2_ip_i_i_171_n_0;
  wire pcie2_ip_i_i_172_n_0;
  wire pcie2_ip_i_i_173_n_0;
  wire pcie2_ip_i_i_174_n_0;
  wire pcie2_ip_i_i_175_n_0;
  wire pcie2_ip_i_i_176_n_0;
  wire pcie2_ip_i_i_177_n_0;
  wire pcie2_ip_i_i_178_n_0;
  wire pcie2_ip_i_i_179_n_0;
  wire pcie2_ip_i_i_180_n_0;
  wire pcie2_ip_i_i_181_n_0;
  wire pcie2_ip_i_i_182_n_0;
  wire pcie2_ip_i_i_183_n_0;
  wire pcie2_ip_i_i_184_n_0;
  wire pcie2_ip_i_i_185_n_0;
  wire pcie2_ip_i_i_186_n_0;
  wire pcie2_ip_i_i_187_n_0;
  wire pcie2_ip_i_i_188_n_0;
  wire pcie2_ip_i_i_189_n_0;
  wire pcie2_ip_i_i_190_n_0;
  wire pcie2_ip_i_i_191_n_0;
  wire pcie2_ip_i_i_192_n_0;
  wire pcie2_ip_i_i_193_n_0;
  wire pcie2_ip_i_i_194_n_0;
  wire pcie2_ip_i_i_195_n_0;
  wire pcie2_ip_i_i_196_n_0;
  wire pcie2_ip_i_i_197_n_0;
  wire pcie2_ip_i_i_198_n_0;
  wire pcie2_ip_i_i_199_n_0;
  wire pcie2_ip_i_i_200_n_0;
  wire pcie2_ip_i_i_201_n_0;
  wire pcie2_ip_i_i_202_n_0;
  wire pcie2_ip_i_i_203_n_0;
  wire pcie2_ip_i_i_204_n_0;
  wire pcie2_ip_i_i_205_n_0;
  wire pcie2_ip_i_i_206_n_0;
  wire pcie2_ip_i_i_207_n_0;
  wire pcie2_ip_i_i_208_n_0;
  wire pcie2_ip_i_i_209_n_0;
  wire pcie2_ip_i_i_210_n_0;
  wire pcie2_ip_i_i_211_n_0;
  wire pcie2_ip_i_i_212_n_0;
  wire pcie2_ip_i_i_213_n_0;
  wire pcie2_ip_i_i_214_n_0;
  wire pcie2_ip_i_i_215_n_0;
  wire pcie2_ip_i_i_216_n_0;
  wire pcie2_ip_i_i_217_n_0;
  wire pcie2_ip_i_i_218_n_0;
  wire pcie2_ip_i_i_219_n_0;
  wire pcie2_ip_i_i_220_n_0;
  wire pcie2_ip_i_i_221_n_0;
  wire pcie2_ip_i_i_222_n_0;
  wire pcie2_ip_i_i_223_n_0;
  wire pcie2_ip_i_i_224_n_0;
  wire pcie2_ip_i_i_225_n_0;
  wire pcie2_ip_i_i_226_n_0;
  wire pcie2_ip_i_i_227_n_0;
  wire pcie2_ip_i_i_228_n_0;
  wire pcie2_ip_i_i_229_n_0;
  wire pcie2_ip_i_i_230_n_0;
  wire pcie2_ip_i_i_231_n_0;
  wire pcie2_ip_i_i_232_n_0;
  wire pcie2_ip_i_i_233_n_0;
  wire pcie2_ip_i_i_234_n_0;
  wire pcie2_ip_i_i_77_n_0;
  wire pcie2_ip_i_n_235;
  wire pcie2_ip_i_n_414;
  wire [3:0]pcie_block_i;
  wire pcie_block_i_0;
  wire pcie_block_i_1;
  wire pcie_block_i_2;
  wire [31:0]pcie_block_i_3;
  wire [9:0]pcie_block_i_4;
  wire \pcie_dma_in\.cfg_interrupt_msi_sent ;
  wire \pcie_dma_in\.cfg_interrupt_sent ;
  wire \pcie_dma_in\.cfg_phy_link_down ;
  wire [3:0]\pcie_dma_in\.pcie_rq_seq_num0 ;
  wire \pcie_dma_in\.pcie_rq_seq_num_vld0 ;
  wire [0:0]\pcie_dma_out\.cfg_fc_sel ;
  wire [0:0]\pcie_dma_out\.cfg_interrupt_int ;
  wire [31:0]\pcie_dma_out\.cfg_interrupt_msi_int ;
  wire [0:0]\pcie_dma_out\.pcie_cq_np_req ;
  wire pl_directed_link_auton_i;
  wire pl_directed_link_auton_mux;
  wire [1:0]pl_directed_link_change_i;
  wire [1:0]pl_directed_link_change_mux;
  wire pl_directed_link_speed_i;
  wire pl_directed_link_speed_mux;
  wire [1:0]pl_directed_link_width_i;
  wire [1:0]pl_directed_link_width_mux;
  wire pl_upstream_prefer_deemph_i;
  wire pl_upstream_prefer_deemph_mux;
  wire reset_n_reg2_reg;
  wire rx_np_ok_i;
  wire rx_np_ok_mux;
  wire rx_np_req_i;
  wire rx_np_req_mux;
  wire s_aresetn;
  wire [63:0]\s_axis_cq\.tdata ;
  wire \s_axis_cq\.tlast ;
  wire [0:0]\s_axis_cq\.tready ;
  wire [4:0]\s_axis_cq\.tuser ;
  wire \s_axis_cq\.tvalid ;
  wire [63:0]\s_axis_rc\.tdata ;
  wire [1:0]\s_axis_rc\.tkeep ;
  wire \s_axis_rc\.tlast ;
  wire [0:0]\s_axis_rc\.tready ;
  wire [3:0]\s_axis_rc\.tuser ;
  wire [11:0]s_axis_rq_tuser;
  wire [63:0]s_axis_tx_tdata_i;
  wire [63:0]s_axis_tx_tdata_mux;
  wire [0:0]s_axis_tx_tkeep_i;
  wire [7:7]s_axis_tx_tkeep_mux;
  wire s_axis_tx_tlast_i;
  wire s_axis_tx_tlast_mux;
  wire s_axis_tx_tready_o;
  wire [3:0]s_axis_tx_tuser_i;
  wire [3:0]s_axis_tx_tuser_mux;
  wire s_axis_tx_tvalid_i;
  wire s_axis_tx_tvalid_mux;
  wire tx_cfg_gnt_i;
  wire tx_cfg_gnt_mux;
  wire user_lnk_up;
  wire user_reset_out;
  wire NLW_pcie2_ip_i_cfg_aer_ecrc_check_en_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_aer_ecrc_gen_en_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_aer_rooterr_corr_err_received_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_aer_rooterr_corr_err_reporting_en_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_aer_rooterr_fatal_err_received_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_aer_rooterr_fatal_err_reporting_en_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_aer_rooterr_non_fatal_err_received_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_aer_rooterr_non_fatal_err_reporting_en_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_bridge_serr_en_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_err_aer_headerlog_set_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_err_cpl_rdy_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_interrupt_msixenable_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_interrupt_msixfm_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_assert_int_a_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_assert_int_b_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_assert_int_c_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_assert_int_d_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_deassert_int_a_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_deassert_int_b_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_deassert_int_c_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_deassert_int_d_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_err_cor_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_err_fatal_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_err_non_fatal_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_pm_as_nak_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_pm_pme_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_pme_to_ack_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_msg_received_setslotpowerlimit_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_pmcsr_pme_en_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_pmcsr_pme_status_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_received_func_lvl_rst_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_root_control_pme_int_en_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_root_control_syserr_corr_err_en_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_root_control_syserr_fatal_err_en_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_root_control_syserr_non_fatal_err_en_UNCONNECTED;
  wire NLW_pcie2_ip_i_cfg_slot_control_electromech_il_ctl_pulse_UNCONNECTED;
  wire NLW_pcie2_ip_i_pl_directed_change_done_UNCONNECTED;
  wire NLW_pcie2_ip_i_pl_link_gen2_cap_UNCONNECTED;
  wire NLW_pcie2_ip_i_pl_link_partner_gen2_supported_UNCONNECTED;
  wire NLW_pcie2_ip_i_pl_link_upcfg_cap_UNCONNECTED;
  wire NLW_pcie2_ip_i_pl_received_hot_rst_UNCONNECTED;
  wire NLW_pcie2_ip_i_pl_sel_lnk_rate_UNCONNECTED;
  wire NLW_pcie2_ip_i_tx_cfg_req_UNCONNECTED;
  wire NLW_pcie2_ip_i_tx_err_drop_UNCONNECTED;
  wire NLW_pcie2_ip_i_user_app_rdy_UNCONNECTED;
  wire [15:0]NLW_pcie2_ip_i_cfg_command_UNCONNECTED;
  wire [15:0]NLW_pcie2_ip_i_cfg_dcommand_UNCONNECTED;
  wire [15:0]NLW_pcie2_ip_i_cfg_dcommand2_UNCONNECTED;
  wire [15:0]NLW_pcie2_ip_i_cfg_dstatus_UNCONNECTED;
  wire [7:0]NLW_pcie2_ip_i_cfg_interrupt_do_UNCONNECTED;
  wire [15:0]NLW_pcie2_ip_i_cfg_lcommand_UNCONNECTED;
  wire [15:0]NLW_pcie2_ip_i_cfg_lstatus_UNCONNECTED;
  wire [15:0]NLW_pcie2_ip_i_cfg_msg_data_UNCONNECTED;
  wire [2:0]NLW_pcie2_ip_i_cfg_pcie_link_state_UNCONNECTED;
  wire [1:0]NLW_pcie2_ip_i_cfg_pmcsr_powerstate_UNCONNECTED;
  wire [15:0]NLW_pcie2_ip_i_cfg_status_UNCONNECTED;
  wire [6:0]NLW_pcie2_ip_i_cfg_vc_tcvc_map_UNCONNECTED;
  wire [11:0]NLW_pcie2_ip_i_fc_cpld_UNCONNECTED;
  wire [7:0]NLW_pcie2_ip_i_fc_cplh_UNCONNECTED;
  wire [11:0]NLW_pcie2_ip_i_fc_npd_UNCONNECTED;
  wire [11:0]NLW_pcie2_ip_i_fc_pd_UNCONNECTED;
  wire [7:0]NLW_pcie2_ip_i_fc_ph_UNCONNECTED;
  wire [3:0]NLW_pcie2_ip_i_m_axis_rx_tkeep_UNCONNECTED;
  wire [20:9]NLW_pcie2_ip_i_m_axis_rx_tuser_UNCONNECTED;
  wire [2:0]NLW_pcie2_ip_i_pl_initial_link_width_UNCONNECTED;
  wire [1:0]NLW_pcie2_ip_i_pl_lane_reversal_mode_UNCONNECTED;
  wire [5:0]NLW_pcie2_ip_i_pl_ltssm_state_UNCONNECTED;
  wire [1:0]NLW_pcie2_ip_i_pl_rx_pm_state_UNCONNECTED;
  wire [1:0]NLW_pcie2_ip_i_pl_sel_lnk_width_UNCONNECTED;
  wire [2:0]NLW_pcie2_ip_i_pl_tx_pm_state_UNCONNECTED;
  wire [5:0]NLW_pcie2_ip_i_tx_buf_av_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair2144" *) 
  LUT3 #(
    .INIT(8'h74)) 
    dmaFlag_i_1
       (.I0(m_axis_rx_tuser_o[3]),
        .I1(m_axis_rx_tvalid_o),
        .I2(dmaFlag),
        .O(dmaFlag_i_1_n_0));
  FDSE dmaFlag_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dmaFlag_i_1_n_0),
        .Q(dmaFlag),
        .S(user_reset_out));
  (* CHECK_LICENSE_TYPE = "xdma_0_pcie2_ip,xdma_0_pcie2_ip_pcie2_top,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "xdma_0_pcie2_ip_pcie2_top,Vivado 2024.1" *) 
  xdma_0_pcie2_ip pcie2_ip_i
       (.cfg_aer_ecrc_check_en(NLW_pcie2_ip_i_cfg_aer_ecrc_check_en_UNCONNECTED),
        .cfg_aer_ecrc_gen_en(NLW_pcie2_ip_i_cfg_aer_ecrc_gen_en_UNCONNECTED),
        .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum_mux),
        .cfg_aer_rooterr_corr_err_received(NLW_pcie2_ip_i_cfg_aer_rooterr_corr_err_received_UNCONNECTED),
        .cfg_aer_rooterr_corr_err_reporting_en(NLW_pcie2_ip_i_cfg_aer_rooterr_corr_err_reporting_en_UNCONNECTED),
        .cfg_aer_rooterr_fatal_err_received(NLW_pcie2_ip_i_cfg_aer_rooterr_fatal_err_received_UNCONNECTED),
        .cfg_aer_rooterr_fatal_err_reporting_en(NLW_pcie2_ip_i_cfg_aer_rooterr_fatal_err_reporting_en_UNCONNECTED),
        .cfg_aer_rooterr_non_fatal_err_received(NLW_pcie2_ip_i_cfg_aer_rooterr_non_fatal_err_received_UNCONNECTED),
        .cfg_aer_rooterr_non_fatal_err_reporting_en(NLW_pcie2_ip_i_cfg_aer_rooterr_non_fatal_err_reporting_en_UNCONNECTED),
        .cfg_bridge_serr_en(NLW_pcie2_ip_i_cfg_bridge_serr_en_UNCONNECTED),
        .cfg_bus_number(cfg_bus_number_o),
        .cfg_command({NLW_pcie2_ip_i_cfg_command_UNCONNECTED[15:3],pcie2_ip_i_n_235,NLW_pcie2_ip_i_cfg_command_UNCONNECTED[1:0]}),
        .cfg_dcommand({NLW_pcie2_ip_i_cfg_dcommand_UNCONNECTED[15],cfg_dcommand[5:3],NLW_pcie2_ip_i_cfg_dcommand_UNCONNECTED[11:8],cfg_dcommand[2:0],NLW_pcie2_ip_i_cfg_dcommand_UNCONNECTED[4:0]}),
        .cfg_dcommand2(NLW_pcie2_ip_i_cfg_dcommand2_UNCONNECTED[15:0]),
        .cfg_device_number(cfg_device_number_o),
        .cfg_ds_bus_number({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_ds_device_number({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_ds_function_number({1'b0,1'b0,1'b0}),
        .cfg_dsn({pcie2_ip_i_i_171_n_0,pcie2_ip_i_i_172_n_0,pcie2_ip_i_i_173_n_0,pcie2_ip_i_i_174_n_0,pcie2_ip_i_i_175_n_0,pcie2_ip_i_i_176_n_0,pcie2_ip_i_i_177_n_0,pcie2_ip_i_i_178_n_0,pcie2_ip_i_i_179_n_0,pcie2_ip_i_i_180_n_0,pcie2_ip_i_i_181_n_0,pcie2_ip_i_i_182_n_0,pcie2_ip_i_i_183_n_0,pcie2_ip_i_i_184_n_0,pcie2_ip_i_i_185_n_0,pcie2_ip_i_i_186_n_0,pcie2_ip_i_i_187_n_0,pcie2_ip_i_i_188_n_0,pcie2_ip_i_i_189_n_0,pcie2_ip_i_i_190_n_0,pcie2_ip_i_i_191_n_0,pcie2_ip_i_i_192_n_0,pcie2_ip_i_i_193_n_0,pcie2_ip_i_i_194_n_0,pcie2_ip_i_i_195_n_0,pcie2_ip_i_i_196_n_0,pcie2_ip_i_i_197_n_0,pcie2_ip_i_i_198_n_0,pcie2_ip_i_i_199_n_0,pcie2_ip_i_i_200_n_0,pcie2_ip_i_i_201_n_0,pcie2_ip_i_i_202_n_0,pcie2_ip_i_i_203_n_0,pcie2_ip_i_i_204_n_0,pcie2_ip_i_i_205_n_0,pcie2_ip_i_i_206_n_0,pcie2_ip_i_i_207_n_0,pcie2_ip_i_i_208_n_0,pcie2_ip_i_i_209_n_0,pcie2_ip_i_i_210_n_0,pcie2_ip_i_i_211_n_0,pcie2_ip_i_i_212_n_0,pcie2_ip_i_i_213_n_0,pcie2_ip_i_i_214_n_0,pcie2_ip_i_i_215_n_0,pcie2_ip_i_i_216_n_0,pcie2_ip_i_i_217_n_0,pcie2_ip_i_i_218_n_0,pcie2_ip_i_i_219_n_0,pcie2_ip_i_i_220_n_0,pcie2_ip_i_i_221_n_0,pcie2_ip_i_i_222_n_0,pcie2_ip_i_i_223_n_0,pcie2_ip_i_i_224_n_0,pcie2_ip_i_i_225_n_0,pcie2_ip_i_i_226_n_0,pcie2_ip_i_i_227_n_0,pcie2_ip_i_i_228_n_0,pcie2_ip_i_i_229_n_0,pcie2_ip_i_i_230_n_0,pcie2_ip_i_i_231_n_0,pcie2_ip_i_i_232_n_0,pcie2_ip_i_i_233_n_0,pcie2_ip_i_i_234_n_0}),
        .cfg_dstatus(NLW_pcie2_ip_i_cfg_dstatus_UNCONNECTED[15:0]),
        .cfg_err_acs(1'b0),
        .cfg_err_aer_headerlog(cfg_err_aer_headerlog_mux),
        .cfg_err_aer_headerlog_set(NLW_pcie2_ip_i_cfg_err_aer_headerlog_set_UNCONNECTED),
        .cfg_err_atomic_egress_blocked(1'b0),
        .cfg_err_cor(1'b0),
        .cfg_err_cpl_abort(1'b0),
        .cfg_err_cpl_rdy(NLW_pcie2_ip_i_cfg_err_cpl_rdy_UNCONNECTED),
        .cfg_err_cpl_timeout(1'b0),
        .cfg_err_cpl_unexpect(1'b0),
        .cfg_err_ecrc(1'b0),
        .cfg_err_internal_cor(1'b0),
        .cfg_err_internal_uncor(1'b0),
        .cfg_err_locked(1'b0),
        .cfg_err_malformed(1'b0),
        .cfg_err_mc_blocked(1'b0),
        .cfg_err_norecovery(1'b0),
        .cfg_err_poisoned(1'b0),
        .cfg_err_posted(1'b0),
        .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header_mux),
        .cfg_err_ur(1'b0),
        .cfg_function_number(cfg_function_number_o),
        .cfg_interrupt(g2ip_cfg_interrupt),
        .cfg_interrupt_assert(g2ip_cfg_interrupt_assert),
        .cfg_interrupt_di(cfg_interrupt_di_mux),
        .cfg_interrupt_do(NLW_pcie2_ip_i_cfg_interrupt_do_UNCONNECTED[7:0]),
        .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
        .cfg_interrupt_msienable(cfg_interrupt_msienable),
        .cfg_interrupt_msixenable(NLW_pcie2_ip_i_cfg_interrupt_msixenable_UNCONNECTED),
        .cfg_interrupt_msixfm(NLW_pcie2_ip_i_cfg_interrupt_msixfm_UNCONNECTED),
        .cfg_interrupt_rdy(g2ip_cfg_interrupt_rdy),
        .cfg_interrupt_stat(1'b0),
        .cfg_lcommand(NLW_pcie2_ip_i_cfg_lcommand_UNCONNECTED[15:0]),
        .cfg_lstatus(NLW_pcie2_ip_i_cfg_lstatus_UNCONNECTED[15:0]),
        .cfg_mgmt_byte_en(pcie_block_i),
        .cfg_mgmt_di(cfg_mgmt_di_mux),
        .cfg_mgmt_do(cfg_mgmt_do),
        .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr_mux),
        .cfg_mgmt_rd_en(pcie_block_i_1),
        .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
        .cfg_mgmt_wr_en(pcie_block_i_0),
        .cfg_mgmt_wr_readonly(pcie_block_i_2),
        .cfg_mgmt_wr_rw1c_as_rw(1'b0),
        .cfg_msg_data(NLW_pcie2_ip_i_cfg_msg_data_UNCONNECTED[15:0]),
        .cfg_msg_received(NLW_pcie2_ip_i_cfg_msg_received_UNCONNECTED),
        .cfg_msg_received_assert_int_a(NLW_pcie2_ip_i_cfg_msg_received_assert_int_a_UNCONNECTED),
        .cfg_msg_received_assert_int_b(NLW_pcie2_ip_i_cfg_msg_received_assert_int_b_UNCONNECTED),
        .cfg_msg_received_assert_int_c(NLW_pcie2_ip_i_cfg_msg_received_assert_int_c_UNCONNECTED),
        .cfg_msg_received_assert_int_d(NLW_pcie2_ip_i_cfg_msg_received_assert_int_d_UNCONNECTED),
        .cfg_msg_received_deassert_int_a(NLW_pcie2_ip_i_cfg_msg_received_deassert_int_a_UNCONNECTED),
        .cfg_msg_received_deassert_int_b(NLW_pcie2_ip_i_cfg_msg_received_deassert_int_b_UNCONNECTED),
        .cfg_msg_received_deassert_int_c(NLW_pcie2_ip_i_cfg_msg_received_deassert_int_c_UNCONNECTED),
        .cfg_msg_received_deassert_int_d(NLW_pcie2_ip_i_cfg_msg_received_deassert_int_d_UNCONNECTED),
        .cfg_msg_received_err_cor(NLW_pcie2_ip_i_cfg_msg_received_err_cor_UNCONNECTED),
        .cfg_msg_received_err_fatal(NLW_pcie2_ip_i_cfg_msg_received_err_fatal_UNCONNECTED),
        .cfg_msg_received_err_non_fatal(NLW_pcie2_ip_i_cfg_msg_received_err_non_fatal_UNCONNECTED),
        .cfg_msg_received_pm_as_nak(NLW_pcie2_ip_i_cfg_msg_received_pm_as_nak_UNCONNECTED),
        .cfg_msg_received_pm_pme(NLW_pcie2_ip_i_cfg_msg_received_pm_pme_UNCONNECTED),
        .cfg_msg_received_pme_to_ack(NLW_pcie2_ip_i_cfg_msg_received_pme_to_ack_UNCONNECTED),
        .cfg_msg_received_setslotpowerlimit(NLW_pcie2_ip_i_cfg_msg_received_setslotpowerlimit_UNCONNECTED),
        .cfg_pcie_link_state(NLW_pcie2_ip_i_cfg_pcie_link_state_UNCONNECTED[2:0]),
        .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum_mux),
        .cfg_pm_force_state(cfg_pm_force_state_mux),
        .cfg_pm_force_state_en(1'b0),
        .cfg_pm_halt_aspm_l0s(1'b0),
        .cfg_pm_halt_aspm_l1(1'b0),
        .cfg_pm_send_pme_to(1'b0),
        .cfg_pm_wake(1'b0),
        .cfg_pmcsr_pme_en(NLW_pcie2_ip_i_cfg_pmcsr_pme_en_UNCONNECTED),
        .cfg_pmcsr_pme_status(NLW_pcie2_ip_i_cfg_pmcsr_pme_status_UNCONNECTED),
        .cfg_pmcsr_powerstate(NLW_pcie2_ip_i_cfg_pmcsr_powerstate_UNCONNECTED[1:0]),
        .cfg_received_func_lvl_rst(NLW_pcie2_ip_i_cfg_received_func_lvl_rst_UNCONNECTED),
        .cfg_root_control_pme_int_en(NLW_pcie2_ip_i_cfg_root_control_pme_int_en_UNCONNECTED),
        .cfg_root_control_syserr_corr_err_en(NLW_pcie2_ip_i_cfg_root_control_syserr_corr_err_en_UNCONNECTED),
        .cfg_root_control_syserr_fatal_err_en(NLW_pcie2_ip_i_cfg_root_control_syserr_fatal_err_en_UNCONNECTED),
        .cfg_root_control_syserr_non_fatal_err_en(NLW_pcie2_ip_i_cfg_root_control_syserr_non_fatal_err_en_UNCONNECTED),
        .cfg_slot_control_electromech_il_ctl_pulse(NLW_pcie2_ip_i_cfg_slot_control_electromech_il_ctl_pulse_UNCONNECTED),
        .cfg_status(NLW_pcie2_ip_i_cfg_status_UNCONNECTED[15:0]),
        .cfg_to_turnoff(cfg_to_turnoff_o),
        .cfg_trn_pending(1'b0),
        .cfg_turnoff_ok(cfg_turnoff_ok_mux),
        .cfg_vc_tcvc_map(NLW_pcie2_ip_i_cfg_vc_tcvc_map_UNCONNECTED[6:0]),
        .fc_cpld(NLW_pcie2_ip_i_fc_cpld_UNCONNECTED[11:0]),
        .fc_cplh(NLW_pcie2_ip_i_fc_cplh_UNCONNECTED[7:0]),
        .fc_npd(NLW_pcie2_ip_i_fc_npd_UNCONNECTED[11:0]),
        .fc_nph(fc_nph),
        .fc_pd(NLW_pcie2_ip_i_fc_pd_UNCONNECTED[11:0]),
        .fc_ph(NLW_pcie2_ip_i_fc_ph_UNCONNECTED[7:0]),
        .fc_sel({fc_sel_mux[2],pcie2_ip_i_i_77_n_0,fc_sel_mux[0]}),
        .m_axis_rx_tdata(m_axis_rx_tdata_o),
        .m_axis_rx_tkeep({m_axis_rx_tkeep_o,NLW_pcie2_ip_i_m_axis_rx_tkeep_UNCONNECTED[3:0]}),
        .m_axis_rx_tlast(m_axis_rx_tlast_o),
        .m_axis_rx_tready(m_axis_rx_tready_mux),
        .m_axis_rx_tuser({m_axis_rx_tuser_o[13],NLW_pcie2_ip_i_m_axis_rx_tuser_UNCONNECTED[20],m_axis_rx_tuser_o[12:10],NLW_pcie2_ip_i_m_axis_rx_tuser_UNCONNECTED[16:15],m_axis_rx_tuser_o[9],NLW_pcie2_ip_i_m_axis_rx_tuser_UNCONNECTED[13:9],m_axis_rx_tuser_o[8:0]}),
        .m_axis_rx_tvalid(m_axis_rx_tvalid_o),
        .pci_exp_rxn(\gtp_channel.gtpe2_channel_i ),
        .pci_exp_rxp(out),
        .pci_exp_txn(pci_exp_txn),
        .pci_exp_txp(pci_exp_txp),
        .pl_directed_change_done(NLW_pcie2_ip_i_pl_directed_change_done_UNCONNECTED),
        .pl_directed_link_auton(pl_directed_link_auton_mux),
        .pl_directed_link_change(pl_directed_link_change_mux),
        .pl_directed_link_speed(pl_directed_link_speed_mux),
        .pl_directed_link_width(pl_directed_link_width_mux),
        .pl_downstream_deemph_source(1'b0),
        .pl_initial_link_width(NLW_pcie2_ip_i_pl_initial_link_width_UNCONNECTED[2:0]),
        .pl_lane_reversal_mode(NLW_pcie2_ip_i_pl_lane_reversal_mode_UNCONNECTED[1:0]),
        .pl_link_gen2_cap(NLW_pcie2_ip_i_pl_link_gen2_cap_UNCONNECTED),
        .pl_link_partner_gen2_supported(NLW_pcie2_ip_i_pl_link_partner_gen2_supported_UNCONNECTED),
        .pl_link_upcfg_cap(NLW_pcie2_ip_i_pl_link_upcfg_cap_UNCONNECTED),
        .pl_ltssm_state(NLW_pcie2_ip_i_pl_ltssm_state_UNCONNECTED[5:0]),
        .pl_phy_lnk_up(pcie2_ip_i_n_414),
        .pl_received_hot_rst(NLW_pcie2_ip_i_pl_received_hot_rst_UNCONNECTED),
        .pl_rx_pm_state(NLW_pcie2_ip_i_pl_rx_pm_state_UNCONNECTED[1:0]),
        .pl_sel_lnk_rate(NLW_pcie2_ip_i_pl_sel_lnk_rate_UNCONNECTED),
        .pl_sel_lnk_width(NLW_pcie2_ip_i_pl_sel_lnk_width_UNCONNECTED[1:0]),
        .pl_transmit_hot_rst(1'b0),
        .pl_tx_pm_state(NLW_pcie2_ip_i_pl_tx_pm_state_UNCONNECTED[2:0]),
        .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph_mux),
        .rx_np_ok(rx_np_ok_mux),
        .rx_np_req(rx_np_req_mux),
        .s_axis_tx_tdata(s_axis_tx_tdata_mux),
        .s_axis_tx_tkeep({s_axis_tx_tkeep_mux,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tx_tlast(s_axis_tx_tlast_mux),
        .s_axis_tx_tready(s_axis_tx_tready_o),
        .s_axis_tx_tuser(s_axis_tx_tuser_mux),
        .s_axis_tx_tvalid(s_axis_tx_tvalid_mux),
        .sys_clk(\gtp_common.gtpe2_common_i ),
        .sys_rst_n(reset_n_reg2_reg),
        .tx_buf_av(NLW_pcie2_ip_i_tx_buf_av_UNCONNECTED[5:0]),
        .tx_cfg_gnt(tx_cfg_gnt_mux),
        .tx_cfg_req(NLW_pcie2_ip_i_tx_cfg_req_UNCONNECTED),
        .tx_err_drop(NLW_pcie2_ip_i_tx_err_drop_UNCONNECTED),
        .user_app_rdy(NLW_pcie2_ip_i_user_app_rdy_UNCONNECTED),
        .user_clk_out(CLK),
        .user_lnk_up(user_lnk_up),
        .user_reset_out(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2117" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_100
       (.I0(pcie_block_i_3[10]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[10]),
        .O(cfg_mgmt_di_mux[10]));
  (* SOFT_HLUTNM = "soft_lutpair2112" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_101
       (.I0(pcie_block_i_3[9]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[9]),
        .O(cfg_mgmt_di_mux[9]));
  (* SOFT_HLUTNM = "soft_lutpair2123" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_102
       (.I0(pcie_block_i_3[8]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[8]),
        .O(cfg_mgmt_di_mux[8]));
  (* SOFT_HLUTNM = "soft_lutpair2121" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_103
       (.I0(pcie_block_i_3[7]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[7]),
        .O(cfg_mgmt_di_mux[7]));
  (* SOFT_HLUTNM = "soft_lutpair2114" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_104
       (.I0(pcie_block_i_3[6]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[6]),
        .O(cfg_mgmt_di_mux[6]));
  (* SOFT_HLUTNM = "soft_lutpair2110" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_105
       (.I0(pcie_block_i_3[5]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[5]),
        .O(cfg_mgmt_di_mux[5]));
  (* SOFT_HLUTNM = "soft_lutpair2102" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_106
       (.I0(pcie_block_i_3[4]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[4]),
        .O(cfg_mgmt_di_mux[4]));
  (* SOFT_HLUTNM = "soft_lutpair2107" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_107
       (.I0(pcie_block_i_3[3]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[3]),
        .O(cfg_mgmt_di_mux[3]));
  (* SOFT_HLUTNM = "soft_lutpair2104" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_108
       (.I0(pcie_block_i_3[2]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[2]),
        .O(cfg_mgmt_di_mux[2]));
  (* SOFT_HLUTNM = "soft_lutpair2103" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_109
       (.I0(pcie_block_i_3[1]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[1]),
        .O(cfg_mgmt_di_mux[1]));
  (* SOFT_HLUTNM = "soft_lutpair2106" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_110
       (.I0(pcie_block_i_3[0]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[0]),
        .O(cfg_mgmt_di_mux[0]));
  (* SOFT_HLUTNM = "soft_lutpair2141" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_111
       (.I0(pcie_block_i_4[9]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_dwaddr_i[9]),
        .O(cfg_mgmt_dwaddr_mux[9]));
  (* SOFT_HLUTNM = "soft_lutpair2137" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_112
       (.I0(pcie_block_i_4[8]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_dwaddr_i[8]),
        .O(cfg_mgmt_dwaddr_mux[8]));
  (* SOFT_HLUTNM = "soft_lutpair2142" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_113
       (.I0(pcie_block_i_4[7]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_dwaddr_i[7]),
        .O(cfg_mgmt_dwaddr_mux[7]));
  (* SOFT_HLUTNM = "soft_lutpair2139" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_114
       (.I0(pcie_block_i_4[6]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_dwaddr_i[6]),
        .O(cfg_mgmt_dwaddr_mux[6]));
  (* SOFT_HLUTNM = "soft_lutpair2128" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_115
       (.I0(pcie_block_i_4[5]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_dwaddr_i[5]),
        .O(cfg_mgmt_dwaddr_mux[5]));
  (* SOFT_HLUTNM = "soft_lutpair2126" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_116
       (.I0(pcie_block_i_4[4]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_dwaddr_i[4]),
        .O(cfg_mgmt_dwaddr_mux[4]));
  (* SOFT_HLUTNM = "soft_lutpair2136" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_117
       (.I0(pcie_block_i_4[3]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_dwaddr_i[3]),
        .O(cfg_mgmt_dwaddr_mux[3]));
  (* SOFT_HLUTNM = "soft_lutpair2143" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_118
       (.I0(pcie_block_i_4[2]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_dwaddr_i[2]),
        .O(cfg_mgmt_dwaddr_mux[2]));
  (* SOFT_HLUTNM = "soft_lutpair2140" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_119
       (.I0(pcie_block_i_4[1]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_dwaddr_i[1]),
        .O(cfg_mgmt_dwaddr_mux[1]));
  (* SOFT_HLUTNM = "soft_lutpair2138" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_120
       (.I0(pcie_block_i_4[0]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_dwaddr_i[0]),
        .O(cfg_mgmt_dwaddr_mux[0]));
  (* SOFT_HLUTNM = "soft_lutpair2164" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_121
       (.I0(cfg_err_tlp_cpl_header_i[47]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[47]));
  (* SOFT_HLUTNM = "soft_lutpair2162" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_122
       (.I0(cfg_err_tlp_cpl_header_i[46]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[46]));
  (* SOFT_HLUTNM = "soft_lutpair2155" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_123
       (.I0(cfg_err_tlp_cpl_header_i[45]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[45]));
  (* SOFT_HLUTNM = "soft_lutpair2152" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_124
       (.I0(cfg_err_tlp_cpl_header_i[44]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[44]));
  (* SOFT_HLUTNM = "soft_lutpair2153" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_125
       (.I0(cfg_err_tlp_cpl_header_i[43]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[43]));
  (* SOFT_HLUTNM = "soft_lutpair2152" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_126
       (.I0(cfg_err_tlp_cpl_header_i[42]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[42]));
  (* SOFT_HLUTNM = "soft_lutpair2154" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_127
       (.I0(cfg_err_tlp_cpl_header_i[41]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[41]));
  (* SOFT_HLUTNM = "soft_lutpair2137" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_128
       (.I0(cfg_err_tlp_cpl_header_i[40]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[40]));
  (* SOFT_HLUTNM = "soft_lutpair2170" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_129
       (.I0(cfg_err_tlp_cpl_header_i[39]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[39]));
  (* SOFT_HLUTNM = "soft_lutpair2159" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_130
       (.I0(cfg_err_tlp_cpl_header_i[38]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[38]));
  (* SOFT_HLUTNM = "soft_lutpair2171" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_131
       (.I0(cfg_err_tlp_cpl_header_i[37]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[37]));
  (* SOFT_HLUTNM = "soft_lutpair2164" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_132
       (.I0(cfg_err_tlp_cpl_header_i[36]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[36]));
  (* SOFT_HLUTNM = "soft_lutpair2160" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_133
       (.I0(cfg_err_tlp_cpl_header_i[35]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[35]));
  (* SOFT_HLUTNM = "soft_lutpair2163" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_134
       (.I0(cfg_err_tlp_cpl_header_i[34]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[34]));
  (* SOFT_HLUTNM = "soft_lutpair2179" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_135
       (.I0(cfg_err_tlp_cpl_header_i[33]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[33]));
  (* SOFT_HLUTNM = "soft_lutpair2192" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_136
       (.I0(cfg_err_tlp_cpl_header_i[32]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[32]));
  (* SOFT_HLUTNM = "soft_lutpair2179" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_137
       (.I0(cfg_err_tlp_cpl_header_i[31]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[31]));
  (* SOFT_HLUTNM = "soft_lutpair2173" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_138
       (.I0(cfg_err_tlp_cpl_header_i[30]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[30]));
  (* SOFT_HLUTNM = "soft_lutpair2177" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_139
       (.I0(cfg_err_tlp_cpl_header_i[29]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[29]));
  (* SOFT_HLUTNM = "soft_lutpair2186" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_140
       (.I0(cfg_err_tlp_cpl_header_i[28]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[28]));
  (* SOFT_HLUTNM = "soft_lutpair2207" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_141
       (.I0(cfg_err_tlp_cpl_header_i[27]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[27]));
  (* SOFT_HLUTNM = "soft_lutpair2184" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_142
       (.I0(cfg_err_tlp_cpl_header_i[26]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[26]));
  (* SOFT_HLUTNM = "soft_lutpair2191" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_143
       (.I0(cfg_err_tlp_cpl_header_i[25]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[25]));
  (* SOFT_HLUTNM = "soft_lutpair2211" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_144
       (.I0(cfg_err_tlp_cpl_header_i[24]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[24]));
  (* SOFT_HLUTNM = "soft_lutpair2187" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_145
       (.I0(cfg_err_tlp_cpl_header_i[23]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[23]));
  (* SOFT_HLUTNM = "soft_lutpair2178" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_146
       (.I0(cfg_err_tlp_cpl_header_i[22]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[22]));
  (* SOFT_HLUTNM = "soft_lutpair2201" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_147
       (.I0(cfg_err_tlp_cpl_header_i[21]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[21]));
  (* SOFT_HLUTNM = "soft_lutpair2212" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_148
       (.I0(cfg_err_tlp_cpl_header_i[20]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[20]));
  (* SOFT_HLUTNM = "soft_lutpair2194" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_149
       (.I0(cfg_err_tlp_cpl_header_i[19]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[19]));
  (* SOFT_HLUTNM = "soft_lutpair2204" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_150
       (.I0(cfg_err_tlp_cpl_header_i[18]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[18]));
  (* SOFT_HLUTNM = "soft_lutpair2218" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_151
       (.I0(cfg_err_tlp_cpl_header_i[17]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[17]));
  (* SOFT_HLUTNM = "soft_lutpair2219" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_152
       (.I0(cfg_err_tlp_cpl_header_i[16]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[16]));
  (* SOFT_HLUTNM = "soft_lutpair2213" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_153
       (.I0(cfg_err_tlp_cpl_header_i[15]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[15]));
  (* SOFT_HLUTNM = "soft_lutpair2219" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_154
       (.I0(cfg_err_tlp_cpl_header_i[14]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[14]));
  (* SOFT_HLUTNM = "soft_lutpair2229" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_155
       (.I0(cfg_err_tlp_cpl_header_i[13]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[13]));
  (* SOFT_HLUTNM = "soft_lutpair2221" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_156
       (.I0(cfg_err_tlp_cpl_header_i[12]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[12]));
  (* SOFT_HLUTNM = "soft_lutpair2221" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_157
       (.I0(cfg_err_tlp_cpl_header_i[11]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[11]));
  (* SOFT_HLUTNM = "soft_lutpair2225" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_158
       (.I0(cfg_err_tlp_cpl_header_i[10]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[10]));
  (* SOFT_HLUTNM = "soft_lutpair2224" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_159
       (.I0(cfg_err_tlp_cpl_header_i[9]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[9]));
  (* SOFT_HLUTNM = "soft_lutpair2225" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_160
       (.I0(cfg_err_tlp_cpl_header_i[8]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[8]));
  (* SOFT_HLUTNM = "soft_lutpair2226" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_161
       (.I0(cfg_err_tlp_cpl_header_i[7]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[7]));
  (* SOFT_HLUTNM = "soft_lutpair2223" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_162
       (.I0(cfg_err_tlp_cpl_header_i[6]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[6]));
  (* SOFT_HLUTNM = "soft_lutpair2214" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_163
       (.I0(cfg_err_tlp_cpl_header_i[5]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[5]));
  (* SOFT_HLUTNM = "soft_lutpair2208" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_164
       (.I0(cfg_err_tlp_cpl_header_i[4]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[4]));
  (* SOFT_HLUTNM = "soft_lutpair2193" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_165
       (.I0(cfg_err_tlp_cpl_header_i[3]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[3]));
  (* SOFT_HLUTNM = "soft_lutpair2183" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_166
       (.I0(cfg_err_tlp_cpl_header_i[2]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[2]));
  (* SOFT_HLUTNM = "soft_lutpair2200" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_167
       (.I0(cfg_err_tlp_cpl_header_i[1]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[1]));
  (* SOFT_HLUTNM = "soft_lutpair2190" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_168
       (.I0(cfg_err_tlp_cpl_header_i[0]),
        .I1(dmaFlag),
        .O(cfg_err_tlp_cpl_header_mux[0]));
  (* SOFT_HLUTNM = "soft_lutpair2110" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_169
       (.I0(cfg_pm_force_state_i[1]),
        .I1(dmaFlag),
        .O(cfg_pm_force_state_mux[1]));
  (* SOFT_HLUTNM = "soft_lutpair2107" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_170
       (.I0(cfg_pm_force_state_i[0]),
        .I1(dmaFlag),
        .O(cfg_pm_force_state_mux[0]));
  (* SOFT_HLUTNM = "soft_lutpair2117" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_171
       (.I0(cfg_dsn_i[63]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_171_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2136" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_172
       (.I0(cfg_dsn_i[62]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_172_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2130" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_173
       (.I0(cfg_dsn_i[61]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_173_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2174" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_174
       (.I0(cfg_dsn_i[60]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_174_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2150" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_175
       (.I0(cfg_dsn_i[59]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_175_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2173" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_176
       (.I0(cfg_dsn_i[58]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_176_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2171" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_177
       (.I0(cfg_dsn_i[57]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_177_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2153" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_178
       (.I0(cfg_dsn_i[56]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_178_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2146" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_179
       (.I0(cfg_dsn_i[55]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_179_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2158" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_180
       (.I0(cfg_dsn_i[54]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_180_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2158" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_181
       (.I0(cfg_dsn_i[53]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_181_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2176" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_182
       (.I0(cfg_dsn_i[52]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_182_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2194" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_183
       (.I0(cfg_dsn_i[51]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_183_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2184" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_184
       (.I0(cfg_dsn_i[50]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_184_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2203" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_185
       (.I0(cfg_dsn_i[49]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_185_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2204" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_186
       (.I0(cfg_dsn_i[48]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_186_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2185" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_187
       (.I0(cfg_dsn_i[47]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_187_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2176" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_188
       (.I0(cfg_dsn_i[46]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_188_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2192" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_189
       (.I0(cfg_dsn_i[45]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_189_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2174" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_190
       (.I0(cfg_dsn_i[44]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_190_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2165" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_191
       (.I0(cfg_dsn_i[43]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_191_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2210" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_192
       (.I0(cfg_dsn_i[42]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_192_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2195" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_193
       (.I0(cfg_dsn_i[41]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_193_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2207" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_194
       (.I0(cfg_dsn_i[40]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_194_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2217" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_195
       (.I0(cfg_dsn_i[39]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_195_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2228" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_196
       (.I0(cfg_dsn_i[38]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_196_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2216" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_197
       (.I0(cfg_dsn_i[37]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_197_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2236" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_198
       (.I0(cfg_dsn_i[36]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_198_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2240" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_199
       (.I0(cfg_dsn_i[35]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_199_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2244" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_200
       (.I0(cfg_dsn_i[34]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_200_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2237" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_201
       (.I0(cfg_dsn_i[33]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_201_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2255" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_202
       (.I0(cfg_dsn_i[32]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_202_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2253" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_203
       (.I0(cfg_dsn_i[31]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_203_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2249" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_204
       (.I0(cfg_dsn_i[30]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_204_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2254" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_205
       (.I0(cfg_dsn_i[29]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_205_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2253" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_206
       (.I0(cfg_dsn_i[28]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_206_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2254" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_207
       (.I0(cfg_dsn_i[27]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_207_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2252" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_208
       (.I0(cfg_dsn_i[26]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_208_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2252" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_209
       (.I0(cfg_dsn_i[25]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_209_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2251" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_210
       (.I0(cfg_dsn_i[24]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_210_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2250" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_211
       (.I0(cfg_dsn_i[23]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_211_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2247" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_212
       (.I0(cfg_dsn_i[22]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_212_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2244" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_213
       (.I0(cfg_dsn_i[21]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_213_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2243" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_214
       (.I0(cfg_dsn_i[20]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_214_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2251" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_215
       (.I0(cfg_dsn_i[19]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_215_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2250" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_216
       (.I0(cfg_dsn_i[18]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_216_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2248" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_217
       (.I0(cfg_dsn_i[17]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_217_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2235" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_218
       (.I0(cfg_dsn_i[16]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_218_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2236" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_219
       (.I0(cfg_dsn_i[15]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_219_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2245" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_220
       (.I0(cfg_dsn_i[14]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_220_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2237" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_221
       (.I0(cfg_dsn_i[13]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_221_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2222" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_222
       (.I0(cfg_dsn_i[12]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_222_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2209" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_223
       (.I0(cfg_dsn_i[11]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_223_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2215" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_224
       (.I0(cfg_dsn_i[10]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_224_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2214" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_225
       (.I0(cfg_dsn_i[9]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_225_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2182" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_226
       (.I0(cfg_dsn_i[8]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_226_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2197" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_227
       (.I0(cfg_dsn_i[7]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_227_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2175" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_228
       (.I0(cfg_dsn_i[6]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_228_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2202" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_229
       (.I0(cfg_dsn_i[5]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_229_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2180" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_230
       (.I0(cfg_dsn_i[4]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_230_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2215" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_231
       (.I0(cfg_dsn_i[3]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_231_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2190" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_232
       (.I0(cfg_dsn_i[2]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_232_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2155" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_233
       (.I0(cfg_dsn_i[1]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_233_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2139" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_234
       (.I0(cfg_dsn_i[0]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_234_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2235" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_235
       (.I0(cfg_interrupt_di_i[7]),
        .I1(dmaFlag),
        .O(cfg_interrupt_di_mux[7]));
  (* SOFT_HLUTNM = "soft_lutpair2238" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_236
       (.I0(cfg_interrupt_di_i[6]),
        .I1(dmaFlag),
        .O(cfg_interrupt_di_mux[6]));
  (* SOFT_HLUTNM = "soft_lutpair2240" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_237
       (.I0(cfg_interrupt_di_i[5]),
        .I1(dmaFlag),
        .O(cfg_interrupt_di_mux[5]));
  (* SOFT_HLUTNM = "soft_lutpair2150" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_243
       (.I0(cfg_pciecap_interrupt_msgnum_i[4]),
        .I1(dmaFlag),
        .O(cfg_pciecap_interrupt_msgnum_mux[4]));
  (* SOFT_HLUTNM = "soft_lutpair2123" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_244
       (.I0(cfg_pciecap_interrupt_msgnum_i[3]),
        .I1(dmaFlag),
        .O(cfg_pciecap_interrupt_msgnum_mux[3]));
  (* SOFT_HLUTNM = "soft_lutpair2159" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_245
       (.I0(cfg_pciecap_interrupt_msgnum_i[2]),
        .I1(dmaFlag),
        .O(cfg_pciecap_interrupt_msgnum_mux[2]));
  (* SOFT_HLUTNM = "soft_lutpair2126" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_246
       (.I0(cfg_pciecap_interrupt_msgnum_i[1]),
        .I1(dmaFlag),
        .O(cfg_pciecap_interrupt_msgnum_mux[1]));
  (* SOFT_HLUTNM = "soft_lutpair2127" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_247
       (.I0(cfg_pciecap_interrupt_msgnum_i[0]),
        .I1(dmaFlag),
        .O(cfg_pciecap_interrupt_msgnum_mux[0]));
  (* SOFT_HLUTNM = "soft_lutpair2257" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_248
       (.I0(cfg_turnoff_ok_i),
        .I1(dmaFlag),
        .O(cfg_turnoff_ok_mux));
  (* SOFT_HLUTNM = "soft_lutpair2101" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_249
       (.I0(pl_directed_link_change_i[1]),
        .I1(dmaFlag),
        .O(pl_directed_link_change_mux[1]));
  (* SOFT_HLUTNM = "soft_lutpair2102" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_250
       (.I0(pl_directed_link_change_i[0]),
        .I1(dmaFlag),
        .O(pl_directed_link_change_mux[0]));
  (* SOFT_HLUTNM = "soft_lutpair2105" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_251
       (.I0(pl_directed_link_width_i[1]),
        .I1(dmaFlag),
        .O(pl_directed_link_width_mux[1]));
  (* SOFT_HLUTNM = "soft_lutpair2104" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_252
       (.I0(pl_directed_link_width_i[0]),
        .I1(dmaFlag),
        .O(pl_directed_link_width_mux[0]));
  (* SOFT_HLUTNM = "soft_lutpair2103" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_253
       (.I0(pl_directed_link_speed_i),
        .I1(dmaFlag),
        .O(pl_directed_link_speed_mux));
  (* SOFT_HLUTNM = "soft_lutpair2106" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_254
       (.I0(pl_directed_link_auton_i),
        .I1(dmaFlag),
        .O(pl_directed_link_auton_mux));
  (* SOFT_HLUTNM = "soft_lutpair2100" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_255
       (.I0(pl_upstream_prefer_deemph_i),
        .I1(dmaFlag),
        .O(pl_upstream_prefer_deemph_mux));
  (* SOFT_HLUTNM = "soft_lutpair2230" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_256
       (.I0(cfg_err_aer_headerlog_i[127]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[127]));
  (* SOFT_HLUTNM = "soft_lutpair2212" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_257
       (.I0(cfg_err_aer_headerlog_i[126]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[126]));
  (* SOFT_HLUTNM = "soft_lutpair2238" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_258
       (.I0(cfg_err_aer_headerlog_i[125]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[125]));
  (* SOFT_HLUTNM = "soft_lutpair2239" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_259
       (.I0(cfg_err_aer_headerlog_i[124]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[124]));
  (* SOFT_HLUTNM = "soft_lutpair2242" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_260
       (.I0(cfg_err_aer_headerlog_i[123]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[123]));
  (* SOFT_HLUTNM = "soft_lutpair2245" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_261
       (.I0(cfg_err_aer_headerlog_i[122]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[122]));
  (* SOFT_HLUTNM = "soft_lutpair2230" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_262
       (.I0(cfg_err_aer_headerlog_i[121]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[121]));
  (* SOFT_HLUTNM = "soft_lutpair2234" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_263
       (.I0(cfg_err_aer_headerlog_i[120]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[120]));
  (* SOFT_HLUTNM = "soft_lutpair2233" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_264
       (.I0(cfg_err_aer_headerlog_i[119]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[119]));
  (* SOFT_HLUTNM = "soft_lutpair2249" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_265
       (.I0(cfg_err_aer_headerlog_i[118]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[118]));
  (* SOFT_HLUTNM = "soft_lutpair2231" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_266
       (.I0(cfg_err_aer_headerlog_i[117]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[117]));
  (* SOFT_HLUTNM = "soft_lutpair2241" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_267
       (.I0(cfg_err_aer_headerlog_i[116]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[116]));
  (* SOFT_HLUTNM = "soft_lutpair2241" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_268
       (.I0(cfg_err_aer_headerlog_i[115]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[115]));
  (* SOFT_HLUTNM = "soft_lutpair2243" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_269
       (.I0(cfg_err_aer_headerlog_i[114]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[114]));
  (* SOFT_HLUTNM = "soft_lutpair2232" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_270
       (.I0(cfg_err_aer_headerlog_i[113]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[113]));
  (* SOFT_HLUTNM = "soft_lutpair2226" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_271
       (.I0(cfg_err_aer_headerlog_i[112]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[112]));
  (* SOFT_HLUTNM = "soft_lutpair2228" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_272
       (.I0(cfg_err_aer_headerlog_i[111]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[111]));
  (* SOFT_HLUTNM = "soft_lutpair2213" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_273
       (.I0(cfg_err_aer_headerlog_i[110]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[110]));
  (* SOFT_HLUTNM = "soft_lutpair2206" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_274
       (.I0(cfg_err_aer_headerlog_i[109]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[109]));
  (* SOFT_HLUTNM = "soft_lutpair2201" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_275
       (.I0(cfg_err_aer_headerlog_i[108]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[108]));
  (* SOFT_HLUTNM = "soft_lutpair2183" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_276
       (.I0(cfg_err_aer_headerlog_i[107]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[107]));
  (* SOFT_HLUTNM = "soft_lutpair2187" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_277
       (.I0(cfg_err_aer_headerlog_i[106]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[106]));
  (* SOFT_HLUTNM = "soft_lutpair2161" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_278
       (.I0(cfg_err_aer_headerlog_i[105]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[105]));
  (* SOFT_HLUTNM = "soft_lutpair2181" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_279
       (.I0(cfg_err_aer_headerlog_i[104]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[104]));
  (* SOFT_HLUTNM = "soft_lutpair2206" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_280
       (.I0(cfg_err_aer_headerlog_i[103]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[103]));
  (* SOFT_HLUTNM = "soft_lutpair2191" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_281
       (.I0(cfg_err_aer_headerlog_i[102]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[102]));
  (* SOFT_HLUTNM = "soft_lutpair2181" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_282
       (.I0(cfg_err_aer_headerlog_i[101]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[101]));
  (* SOFT_HLUTNM = "soft_lutpair2199" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_283
       (.I0(cfg_err_aer_headerlog_i[100]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[100]));
  (* SOFT_HLUTNM = "soft_lutpair2203" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_284
       (.I0(cfg_err_aer_headerlog_i[99]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[99]));
  (* SOFT_HLUTNM = "soft_lutpair2196" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_285
       (.I0(cfg_err_aer_headerlog_i[98]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[98]));
  (* SOFT_HLUTNM = "soft_lutpair2186" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_286
       (.I0(cfg_err_aer_headerlog_i[97]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[97]));
  (* SOFT_HLUTNM = "soft_lutpair2172" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_287
       (.I0(cfg_err_aer_headerlog_i[96]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[96]));
  (* SOFT_HLUTNM = "soft_lutpair2198" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_288
       (.I0(cfg_err_aer_headerlog_i[95]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[95]));
  (* SOFT_HLUTNM = "soft_lutpair2156" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_289
       (.I0(cfg_err_aer_headerlog_i[94]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[94]));
  (* SOFT_HLUTNM = "soft_lutpair2145" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_290
       (.I0(cfg_err_aer_headerlog_i[93]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[93]));
  (* SOFT_HLUTNM = "soft_lutpair2151" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_291
       (.I0(cfg_err_aer_headerlog_i[92]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[92]));
  (* SOFT_HLUTNM = "soft_lutpair2154" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_292
       (.I0(cfg_err_aer_headerlog_i[91]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[91]));
  (* SOFT_HLUTNM = "soft_lutpair2156" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_293
       (.I0(cfg_err_aer_headerlog_i[90]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[90]));
  (* SOFT_HLUTNM = "soft_lutpair2124" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_294
       (.I0(cfg_err_aer_headerlog_i[89]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[89]));
  (* SOFT_HLUTNM = "soft_lutpair2122" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_295
       (.I0(cfg_err_aer_headerlog_i[88]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[88]));
  (* SOFT_HLUTNM = "soft_lutpair2148" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_296
       (.I0(cfg_err_aer_headerlog_i[87]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[87]));
  (* SOFT_HLUTNM = "soft_lutpair2147" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_297
       (.I0(cfg_err_aer_headerlog_i[86]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[86]));
  (* SOFT_HLUTNM = "soft_lutpair2160" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_298
       (.I0(cfg_err_aer_headerlog_i[85]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[85]));
  (* SOFT_HLUTNM = "soft_lutpair2157" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_299
       (.I0(cfg_err_aer_headerlog_i[84]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[84]));
  (* SOFT_HLUTNM = "soft_lutpair2149" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_300
       (.I0(cfg_err_aer_headerlog_i[83]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[83]));
  (* SOFT_HLUTNM = "soft_lutpair2166" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_301
       (.I0(cfg_err_aer_headerlog_i[82]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[82]));
  (* SOFT_HLUTNM = "soft_lutpair2134" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_302
       (.I0(cfg_err_aer_headerlog_i[81]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[81]));
  (* SOFT_HLUTNM = "soft_lutpair2128" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_303
       (.I0(cfg_err_aer_headerlog_i[80]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[80]));
  (* SOFT_HLUTNM = "soft_lutpair2121" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_304
       (.I0(cfg_err_aer_headerlog_i[79]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[79]));
  (* SOFT_HLUTNM = "soft_lutpair2118" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_305
       (.I0(cfg_err_aer_headerlog_i[78]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[78]));
  (* SOFT_HLUTNM = "soft_lutpair2119" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_306
       (.I0(cfg_err_aer_headerlog_i[77]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[77]));
  (* SOFT_HLUTNM = "soft_lutpair2116" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_307
       (.I0(cfg_err_aer_headerlog_i[76]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[76]));
  (* SOFT_HLUTNM = "soft_lutpair2109" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_308
       (.I0(cfg_err_aer_headerlog_i[75]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[75]));
  (* SOFT_HLUTNM = "soft_lutpair2167" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_309
       (.I0(cfg_err_aer_headerlog_i[74]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[74]));
  (* SOFT_HLUTNM = "soft_lutpair2140" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_310
       (.I0(cfg_err_aer_headerlog_i[73]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[73]));
  (* SOFT_HLUTNM = "soft_lutpair2142" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_311
       (.I0(cfg_err_aer_headerlog_i[72]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[72]));
  (* SOFT_HLUTNM = "soft_lutpair2138" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_312
       (.I0(cfg_err_aer_headerlog_i[71]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[71]));
  (* SOFT_HLUTNM = "soft_lutpair2145" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_313
       (.I0(cfg_err_aer_headerlog_i[70]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[70]));
  (* SOFT_HLUTNM = "soft_lutpair2146" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_314
       (.I0(cfg_err_aer_headerlog_i[69]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[69]));
  (* SOFT_HLUTNM = "soft_lutpair2143" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_315
       (.I0(cfg_err_aer_headerlog_i[68]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[68]));
  (* SOFT_HLUTNM = "soft_lutpair2133" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_316
       (.I0(cfg_err_aer_headerlog_i[67]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[67]));
  (* SOFT_HLUTNM = "soft_lutpair2141" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_317
       (.I0(cfg_err_aer_headerlog_i[66]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[66]));
  (* SOFT_HLUTNM = "soft_lutpair2148" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_318
       (.I0(cfg_err_aer_headerlog_i[65]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[65]));
  (* SOFT_HLUTNM = "soft_lutpair2135" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_319
       (.I0(cfg_err_aer_headerlog_i[64]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[64]));
  (* SOFT_HLUTNM = "soft_lutpair2129" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_320
       (.I0(cfg_err_aer_headerlog_i[63]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[63]));
  (* SOFT_HLUTNM = "soft_lutpair2168" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_321
       (.I0(cfg_err_aer_headerlog_i[62]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[62]));
  (* SOFT_HLUTNM = "soft_lutpair2120" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_322
       (.I0(cfg_err_aer_headerlog_i[61]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[61]));
  (* SOFT_HLUTNM = "soft_lutpair2162" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_323
       (.I0(cfg_err_aer_headerlog_i[60]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[60]));
  (* SOFT_HLUTNM = "soft_lutpair2157" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_324
       (.I0(cfg_err_aer_headerlog_i[59]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[59]));
  (* SOFT_HLUTNM = "soft_lutpair2165" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_325
       (.I0(cfg_err_aer_headerlog_i[58]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[58]));
  (* SOFT_HLUTNM = "soft_lutpair2149" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_326
       (.I0(cfg_err_aer_headerlog_i[57]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[57]));
  (* SOFT_HLUTNM = "soft_lutpair2169" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_327
       (.I0(cfg_err_aer_headerlog_i[56]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[56]));
  (* SOFT_HLUTNM = "soft_lutpair2163" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_328
       (.I0(cfg_err_aer_headerlog_i[55]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[55]));
  (* SOFT_HLUTNM = "soft_lutpair2125" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_329
       (.I0(cfg_err_aer_headerlog_i[54]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[54]));
  (* SOFT_HLUTNM = "soft_lutpair2199" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_330
       (.I0(cfg_err_aer_headerlog_i[53]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[53]));
  (* SOFT_HLUTNM = "soft_lutpair2172" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_331
       (.I0(cfg_err_aer_headerlog_i[52]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[52]));
  (* SOFT_HLUTNM = "soft_lutpair2195" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_332
       (.I0(cfg_err_aer_headerlog_i[51]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[51]));
  (* SOFT_HLUTNM = "soft_lutpair2205" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_333
       (.I0(cfg_err_aer_headerlog_i[50]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[50]));
  (* SOFT_HLUTNM = "soft_lutpair2178" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_334
       (.I0(cfg_err_aer_headerlog_i[49]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[49]));
  (* SOFT_HLUTNM = "soft_lutpair2180" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_335
       (.I0(cfg_err_aer_headerlog_i[48]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[48]));
  (* SOFT_HLUTNM = "soft_lutpair2205" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_336
       (.I0(cfg_err_aer_headerlog_i[47]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[47]));
  (* SOFT_HLUTNM = "soft_lutpair2170" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_337
       (.I0(cfg_err_aer_headerlog_i[46]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[46]));
  (* SOFT_HLUTNM = "soft_lutpair2182" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_338
       (.I0(cfg_err_aer_headerlog_i[45]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[45]));
  (* SOFT_HLUTNM = "soft_lutpair2175" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_339
       (.I0(cfg_err_aer_headerlog_i[44]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[44]));
  (* SOFT_HLUTNM = "soft_lutpair2188" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_340
       (.I0(cfg_err_aer_headerlog_i[43]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[43]));
  (* SOFT_HLUTNM = "soft_lutpair2211" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_341
       (.I0(cfg_err_aer_headerlog_i[42]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[42]));
  (* SOFT_HLUTNM = "soft_lutpair2189" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_342
       (.I0(cfg_err_aer_headerlog_i[41]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[41]));
  (* SOFT_HLUTNM = "soft_lutpair2177" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_343
       (.I0(cfg_err_aer_headerlog_i[40]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[40]));
  (* SOFT_HLUTNM = "soft_lutpair2220" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_344
       (.I0(cfg_err_aer_headerlog_i[39]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[39]));
  (* SOFT_HLUTNM = "soft_lutpair2210" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_345
       (.I0(cfg_err_aer_headerlog_i[38]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[38]));
  (* SOFT_HLUTNM = "soft_lutpair2189" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_346
       (.I0(cfg_err_aer_headerlog_i[37]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[37]));
  (* SOFT_HLUTNM = "soft_lutpair2188" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_347
       (.I0(cfg_err_aer_headerlog_i[36]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[36]));
  (* SOFT_HLUTNM = "soft_lutpair2208" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_348
       (.I0(cfg_err_aer_headerlog_i[35]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[35]));
  (* SOFT_HLUTNM = "soft_lutpair2224" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_349
       (.I0(cfg_err_aer_headerlog_i[34]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[34]));
  (* SOFT_HLUTNM = "soft_lutpair2216" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_350
       (.I0(cfg_err_aer_headerlog_i[33]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[33]));
  (* SOFT_HLUTNM = "soft_lutpair2218" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_351
       (.I0(cfg_err_aer_headerlog_i[32]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[32]));
  (* SOFT_HLUTNM = "soft_lutpair2202" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_352
       (.I0(cfg_err_aer_headerlog_i[31]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[31]));
  (* SOFT_HLUTNM = "soft_lutpair2196" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_353
       (.I0(cfg_err_aer_headerlog_i[30]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[30]));
  (* SOFT_HLUTNM = "soft_lutpair2233" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_354
       (.I0(cfg_err_aer_headerlog_i[29]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[29]));
  (* SOFT_HLUTNM = "soft_lutpair2223" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_355
       (.I0(cfg_err_aer_headerlog_i[28]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[28]));
  (* SOFT_HLUTNM = "soft_lutpair2222" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_356
       (.I0(cfg_err_aer_headerlog_i[27]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[27]));
  (* SOFT_HLUTNM = "soft_lutpair2220" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_357
       (.I0(cfg_err_aer_headerlog_i[26]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[26]));
  (* SOFT_HLUTNM = "soft_lutpair2229" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_358
       (.I0(cfg_err_aer_headerlog_i[25]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[25]));
  (* SOFT_HLUTNM = "soft_lutpair2246" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_359
       (.I0(cfg_err_aer_headerlog_i[24]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[24]));
  (* SOFT_HLUTNM = "soft_lutpair2234" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_360
       (.I0(cfg_err_aer_headerlog_i[23]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[23]));
  (* SOFT_HLUTNM = "soft_lutpair2248" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_361
       (.I0(cfg_err_aer_headerlog_i[22]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[22]));
  (* SOFT_HLUTNM = "soft_lutpair2232" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_362
       (.I0(cfg_err_aer_headerlog_i[21]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[21]));
  (* SOFT_HLUTNM = "soft_lutpair2231" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_363
       (.I0(cfg_err_aer_headerlog_i[20]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[20]));
  (* SOFT_HLUTNM = "soft_lutpair2239" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_364
       (.I0(cfg_err_aer_headerlog_i[19]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[19]));
  (* SOFT_HLUTNM = "soft_lutpair2246" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_365
       (.I0(cfg_err_aer_headerlog_i[18]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[18]));
  (* SOFT_HLUTNM = "soft_lutpair2227" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_366
       (.I0(cfg_err_aer_headerlog_i[17]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[17]));
  (* SOFT_HLUTNM = "soft_lutpair2227" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_367
       (.I0(cfg_err_aer_headerlog_i[16]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[16]));
  (* SOFT_HLUTNM = "soft_lutpair2242" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_368
       (.I0(cfg_err_aer_headerlog_i[15]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[15]));
  (* SOFT_HLUTNM = "soft_lutpair2247" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_369
       (.I0(cfg_err_aer_headerlog_i[14]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[14]));
  (* SOFT_HLUTNM = "soft_lutpair2185" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_370
       (.I0(cfg_err_aer_headerlog_i[13]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[13]));
  (* SOFT_HLUTNM = "soft_lutpair2198" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_371
       (.I0(cfg_err_aer_headerlog_i[12]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[12]));
  (* SOFT_HLUTNM = "soft_lutpair2131" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_372
       (.I0(cfg_err_aer_headerlog_i[11]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[11]));
  (* SOFT_HLUTNM = "soft_lutpair2112" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_373
       (.I0(cfg_err_aer_headerlog_i[10]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[10]));
  (* SOFT_HLUTNM = "soft_lutpair2132" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_374
       (.I0(cfg_err_aer_headerlog_i[9]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[9]));
  (* SOFT_HLUTNM = "soft_lutpair2108" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_375
       (.I0(cfg_err_aer_headerlog_i[8]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[8]));
  (* SOFT_HLUTNM = "soft_lutpair2113" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_376
       (.I0(cfg_err_aer_headerlog_i[7]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[7]));
  (* SOFT_HLUTNM = "soft_lutpair2151" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_377
       (.I0(cfg_err_aer_headerlog_i[6]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[6]));
  (* SOFT_HLUTNM = "soft_lutpair2161" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_378
       (.I0(cfg_err_aer_headerlog_i[5]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[5]));
  (* SOFT_HLUTNM = "soft_lutpair2114" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_379
       (.I0(cfg_err_aer_headerlog_i[4]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[4]));
  (* SOFT_HLUTNM = "soft_lutpair2111" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_380
       (.I0(cfg_err_aer_headerlog_i[3]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[3]));
  (* SOFT_HLUTNM = "soft_lutpair2144" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_381
       (.I0(cfg_err_aer_headerlog_i[2]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[2]));
  (* SOFT_HLUTNM = "soft_lutpair2166" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_382
       (.I0(cfg_err_aer_headerlog_i[1]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[1]));
  (* SOFT_HLUTNM = "soft_lutpair2147" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_383
       (.I0(cfg_err_aer_headerlog_i[0]),
        .I1(dmaFlag),
        .O(cfg_err_aer_headerlog_mux[0]));
  (* SOFT_HLUTNM = "soft_lutpair2167" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_384
       (.I0(cfg_aer_interrupt_msgnum_i[4]),
        .I1(dmaFlag),
        .O(cfg_aer_interrupt_msgnum_mux[4]));
  (* SOFT_HLUTNM = "soft_lutpair2168" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_385
       (.I0(cfg_aer_interrupt_msgnum_i[3]),
        .I1(dmaFlag),
        .O(cfg_aer_interrupt_msgnum_mux[3]));
  (* SOFT_HLUTNM = "soft_lutpair2115" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_386
       (.I0(cfg_aer_interrupt_msgnum_i[2]),
        .I1(dmaFlag),
        .O(cfg_aer_interrupt_msgnum_mux[2]));
  (* SOFT_HLUTNM = "soft_lutpair2200" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_387
       (.I0(cfg_aer_interrupt_msgnum_i[1]),
        .I1(dmaFlag),
        .O(cfg_aer_interrupt_msgnum_mux[1]));
  (* SOFT_HLUTNM = "soft_lutpair2193" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_388
       (.I0(cfg_aer_interrupt_msgnum_i[0]),
        .I1(dmaFlag),
        .O(cfg_aer_interrupt_msgnum_mux[0]));
  (* SOFT_HLUTNM = "soft_lutpair2256" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_68
       (.I0(s_axis_tx_tuser_i[3]),
        .I1(dmaFlag),
        .O(s_axis_tx_tuser_mux[3]));
  (* SOFT_HLUTNM = "soft_lutpair2256" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_69
       (.I0(s_axis_tx_tuser_i[2]),
        .I1(dmaFlag),
        .O(s_axis_tx_tuser_mux[2]));
  (* SOFT_HLUTNM = "soft_lutpair2257" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_70
       (.I0(s_axis_tx_tuser_i[1]),
        .I1(dmaFlag),
        .O(s_axis_tx_tuser_mux[1]));
  (* SOFT_HLUTNM = "soft_lutpair2169" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_71
       (.I0(s_axis_tx_tuser_i[0]),
        .I1(dmaFlag),
        .O(s_axis_tx_tuser_mux[0]));
  (* SOFT_HLUTNM = "soft_lutpair2255" *) 
  LUT2 #(
    .INIT(4'hE)) 
    pcie2_ip_i_i_72
       (.I0(dmaFlag),
        .I1(tx_cfg_gnt_i),
        .O(tx_cfg_gnt_mux));
  (* SOFT_HLUTNM = "soft_lutpair2197" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_74
       (.I0(rx_np_ok_i),
        .I1(dmaFlag),
        .O(rx_np_ok_mux));
  (* SOFT_HLUTNM = "soft_lutpair2100" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_75
       (.I0(\pcie_dma_out\.pcie_cq_np_req ),
        .I1(dmaFlag),
        .I2(rx_np_req_i),
        .O(rx_np_req_mux));
  (* SOFT_HLUTNM = "soft_lutpair2209" *) 
  LUT2 #(
    .INIT(4'hE)) 
    pcie2_ip_i_i_76
       (.I0(dmaFlag),
        .I1(fc_sel_i[2]),
        .O(fc_sel_mux[2]));
  (* SOFT_HLUTNM = "soft_lutpair2217" *) 
  LUT2 #(
    .INIT(4'h2)) 
    pcie2_ip_i_i_77
       (.I0(fc_sel_i[1]),
        .I1(dmaFlag),
        .O(pcie2_ip_i_i_77_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2109" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_78
       (.I0(\pcie_dma_out\.cfg_fc_sel ),
        .I1(dmaFlag),
        .I2(fc_sel_i[0]),
        .O(fc_sel_mux[0]));
  (* SOFT_HLUTNM = "soft_lutpair2135" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_79
       (.I0(pcie_block_i_3[31]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[31]),
        .O(cfg_mgmt_di_mux[31]));
  (* SOFT_HLUTNM = "soft_lutpair2119" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_80
       (.I0(pcie_block_i_3[30]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[30]),
        .O(cfg_mgmt_di_mux[30]));
  (* SOFT_HLUTNM = "soft_lutpair2118" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_81
       (.I0(pcie_block_i_3[29]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[29]),
        .O(cfg_mgmt_di_mux[29]));
  (* SOFT_HLUTNM = "soft_lutpair2120" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_82
       (.I0(pcie_block_i_3[28]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[28]),
        .O(cfg_mgmt_di_mux[28]));
  (* SOFT_HLUTNM = "soft_lutpair2111" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_83
       (.I0(pcie_block_i_3[27]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[27]),
        .O(cfg_mgmt_di_mux[27]));
  (* SOFT_HLUTNM = "soft_lutpair2105" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_84
       (.I0(pcie_block_i_3[26]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[26]),
        .O(cfg_mgmt_di_mux[26]));
  (* SOFT_HLUTNM = "soft_lutpair2115" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_85
       (.I0(pcie_block_i_3[25]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[25]),
        .O(cfg_mgmt_di_mux[25]));
  (* SOFT_HLUTNM = "soft_lutpair2101" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_86
       (.I0(pcie_block_i_3[24]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[24]),
        .O(cfg_mgmt_di_mux[24]));
  (* SOFT_HLUTNM = "soft_lutpair2108" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_87
       (.I0(pcie_block_i_3[23]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[23]),
        .O(cfg_mgmt_di_mux[23]));
  (* SOFT_HLUTNM = "soft_lutpair2129" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_88
       (.I0(pcie_block_i_3[22]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[22]),
        .O(cfg_mgmt_di_mux[22]));
  (* SOFT_HLUTNM = "soft_lutpair2131" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_89
       (.I0(pcie_block_i_3[21]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[21]),
        .O(cfg_mgmt_di_mux[21]));
  (* SOFT_HLUTNM = "soft_lutpair2127" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_90
       (.I0(pcie_block_i_3[20]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[20]),
        .O(cfg_mgmt_di_mux[20]));
  (* SOFT_HLUTNM = "soft_lutpair2122" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_91
       (.I0(pcie_block_i_3[19]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[19]),
        .O(cfg_mgmt_di_mux[19]));
  (* SOFT_HLUTNM = "soft_lutpair2125" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_92
       (.I0(pcie_block_i_3[18]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[18]),
        .O(cfg_mgmt_di_mux[18]));
  (* SOFT_HLUTNM = "soft_lutpair2133" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_93
       (.I0(pcie_block_i_3[17]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[17]),
        .O(cfg_mgmt_di_mux[17]));
  (* SOFT_HLUTNM = "soft_lutpair2132" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_94
       (.I0(pcie_block_i_3[16]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[16]),
        .O(cfg_mgmt_di_mux[16]));
  (* SOFT_HLUTNM = "soft_lutpair2130" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_95
       (.I0(pcie_block_i_3[15]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[15]),
        .O(cfg_mgmt_di_mux[15]));
  (* SOFT_HLUTNM = "soft_lutpair2124" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_96
       (.I0(pcie_block_i_3[14]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[14]),
        .O(cfg_mgmt_di_mux[14]));
  (* SOFT_HLUTNM = "soft_lutpair2116" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_97
       (.I0(pcie_block_i_3[13]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[13]),
        .O(cfg_mgmt_di_mux[13]));
  (* SOFT_HLUTNM = "soft_lutpair2113" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_98
       (.I0(pcie_block_i_3[12]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[12]),
        .O(cfg_mgmt_di_mux[12]));
  (* SOFT_HLUTNM = "soft_lutpair2134" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_99
       (.I0(pcie_block_i_3[11]),
        .I1(dmaFlag),
        .I2(cfg_mgmt_di_i[11]),
        .O(cfg_mgmt_di_mux[11]));
  LUT1 #(
    .INIT(2'h1)) 
    udma_wrapper_i_147
       (.I0(pcie2_ip_i_n_414),
        .O(\pcie_dma_in\.cfg_phy_link_down ));
  xdma_0_axi_stream_intf xdma_0_axi_stream_intf_i
       (.D(m_axis_rx_tdata_o),
        .E(s_aresetn),
        .cfg_bus_number_o(cfg_bus_number_o),
        .cfg_device_number_o(cfg_device_number_o),
        .cfg_function_number_o(cfg_function_number_o),
        .dmaFlag(dmaFlag),
        .\m_axis_cc\.tdata (\m_axis_cc\.tdata ),
        .\m_axis_cc\.tlast (\m_axis_cc\.tlast ),
        .\m_axis_cc\.tready (\m_axis_cc\.tready ),
        .\m_axis_cc\.tvalid (\m_axis_cc\.tvalid ),
        .\m_axis_rq\.tlast (\m_axis_rq\.tlast ),
        .\m_axis_rq\.tready (\m_axis_rq\.tready ),
        .\m_axis_rq\.tvalid (\m_axis_rq\.tvalid ),
        .m_axis_rx_tkeep_o(m_axis_rx_tkeep_o),
        .m_axis_rx_tlast(m_axis_rx_tlast_o),
        .m_axis_rx_tready(m_axis_rx_tready_mux),
        .m_axis_rx_tready_i(m_axis_rx_tready_i),
        .m_axis_rx_tuser_o(m_axis_rx_tuser_o),
        .m_axis_rx_tvalid(m_axis_rx_tvalid_o),
        .\pcie_dma_in\.pcie_rq_seq_num0 (\pcie_dma_in\.pcie_rq_seq_num0 ),
        .\pcie_dma_in\.pcie_rq_seq_num_vld0 (\pcie_dma_in\.pcie_rq_seq_num_vld0 ),
        .\s_axis_cq\.tdata (\s_axis_cq\.tdata ),
        .\s_axis_cq\.tlast (\s_axis_cq\.tlast ),
        .\s_axis_cq\.tready (\s_axis_cq\.tready ),
        .\s_axis_cq\.tuser (\s_axis_cq\.tuser ),
        .\s_axis_cq\.tvalid (\s_axis_cq\.tvalid ),
        .\s_axis_rc\.tdata (\s_axis_rc\.tdata ),
        .\s_axis_rc\.tkeep (\s_axis_rc\.tkeep ),
        .\s_axis_rc\.tlast (\s_axis_rc\.tlast ),
        .\s_axis_rc\.tready (\s_axis_rc\.tready ),
        .\s_axis_rc\.tuser (\s_axis_rc\.tuser ),
        .s_axis_rq_tuser(s_axis_rq_tuser),
        .s_axis_tx_tdata_i(s_axis_tx_tdata_i),
        .\s_axis_tx_tdata_reg[63] (s_axis_tx_tdata_mux),
        .s_axis_tx_tkeep_i(s_axis_tx_tkeep_i),
        .\s_axis_tx_tkeep_reg[7] (s_axis_tx_tkeep_mux),
        .s_axis_tx_tlast_i(s_axis_tx_tlast_i),
        .s_axis_tx_tlast_reg(s_axis_tx_tlast_mux),
        .s_axis_tx_tready(s_axis_tx_tready_o),
        .s_axis_tx_tvalid_i(s_axis_tx_tvalid_i),
        .s_axis_tx_tvalid_reg(s_axis_tx_tvalid_mux),
        .\tx_64.req_addr_reg[63] (D),
        .user_clk_out(CLK),
        .user_reset_out(user_reset_out));
  xdma_0_cfg_sideband xdma_0_cfg_sideband_i
       (.E(s_aresetn),
        .cfg_command(pcie2_ip_i_n_235),
        .cfg_interrupt(g2ip_cfg_interrupt),
        .cfg_interrupt_assert(g2ip_cfg_interrupt_assert),
        .cfg_interrupt_di(cfg_interrupt_di_mux[4:0]),
        .cfg_interrupt_di_i(cfg_interrupt_di_i[4:0]),
        .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
        .cfg_interrupt_msienable(cfg_interrupt_msienable),
        .cfg_interrupt_rdy(g2ip_cfg_interrupt_rdy),
        .dmaFlag(dmaFlag),
        .\pcie_dma_in\.cfg_interrupt_msi_sent (\pcie_dma_in\.cfg_interrupt_msi_sent ),
        .\pcie_dma_in\.cfg_interrupt_sent (\pcie_dma_in\.cfg_interrupt_sent ),
        .\pcie_dma_out\.cfg_interrupt_int (\pcie_dma_out\.cfg_interrupt_int ),
        .\pcie_dma_out\.cfg_interrupt_msi_int (\pcie_dma_out\.cfg_interrupt_msi_int ),
        .user_clk_out(CLK),
        .user_reset_out(user_reset_out));
endmodule

module xdma_0_rx_demux
   (m_axis_tvalid,
    m_axis_tdata,
    empty_fwft_i_reg,
    \goreg_dm.dout_i_reg[94] ,
    m_axis_tlast,
    m_axis_rx_tready,
    \goreg_dm.dout_i_reg[4] ,
    \goreg_dm.dout_i_reg[59] ,
    req_LTR,
    req_OBFF,
    req_ATS,
    req_VDM,
    \goreg_dm.dout_i_reg[59]_0 ,
    in_packet_q_reg,
    in_packet_q_reg_0,
    in_packet_q_reg_1,
    in_packet_q_reg_2,
    in_packet_q_reg_3,
    in_packet_q_reg_4,
    in_packet_q_reg_5,
    user_reset_out_reg,
    \goreg_bm.dout_i_reg[38] ,
    user_clk_out,
    E,
    m_axis_tready,
    m_axis_rx_tkeep_o,
    m_axis_rx_tlast,
    user_reset_out,
    dmaFlag,
    m_axis_rx_tready_i,
    D,
    m_axis_rx_tvalid,
    \tx_64.req_bar_id_reg[0] ,
    in_packet_q,
    state,
    req_mesg,
    \s_axis_rc\.tready ,
    in_packet_q_0,
    Q,
    m_axis_rx_tuser_o);
  output m_axis_tvalid;
  output [62:0]m_axis_tdata;
  output empty_fwft_i_reg;
  output [63:0]\goreg_dm.dout_i_reg[94] ;
  output m_axis_tlast;
  output m_axis_rx_tready;
  output [2:0]\goreg_dm.dout_i_reg[4] ;
  output [3:0]\goreg_dm.dout_i_reg[59] ;
  output req_LTR;
  output req_OBFF;
  output req_ATS;
  output req_VDM;
  output [7:0]\goreg_dm.dout_i_reg[59]_0 ;
  output in_packet_q_reg;
  output [15:0]in_packet_q_reg_0;
  output [11:0]in_packet_q_reg_1;
  output [9:0]in_packet_q_reg_2;
  output [2:0]in_packet_q_reg_3;
  output [2:0]in_packet_q_reg_4;
  output [2:0]in_packet_q_reg_5;
  output user_reset_out_reg;
  output [31:0]\goreg_bm.dout_i_reg[38] ;
  input user_clk_out;
  input [0:0]E;
  input m_axis_tready;
  input [3:0]m_axis_rx_tkeep_o;
  input m_axis_rx_tlast;
  input user_reset_out;
  input dmaFlag;
  input m_axis_rx_tready_i;
  input [63:0]D;
  input m_axis_rx_tvalid;
  input \tx_64.req_bar_id_reg[0] ;
  input in_packet_q;
  input [0:0]state;
  input req_mesg;
  input [0:0]\s_axis_rc\.tready ;
  input in_packet_q_0;
  input [1:0]Q;
  input [13:0]m_axis_rx_tuser_o;

  wire [63:0]D;
  wire [0:0]E;
  wire [1:0]Q;
  wire active_intfc;
  wire active_intfc1;
  wire active_intfc_i_1_n_0;
  wire \cplfifo_s_axis_tdata[63]_i_1_n_0 ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[0] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[10] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[11] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[12] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[13] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[14] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[15] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[16] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[17] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[18] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[19] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[1] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[20] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[21] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[22] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[23] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[24] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[25] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[26] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[27] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[28] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[29] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[2] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[30] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[31] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[32] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[33] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[34] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[35] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[36] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[37] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[38] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[39] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[3] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[40] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[41] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[42] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[43] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[44] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[45] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[46] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[47] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[48] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[49] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[4] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[50] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[51] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[52] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[53] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[54] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[55] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[56] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[57] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[58] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[59] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[5] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[60] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[61] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[62] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[63] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[6] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[7] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[8] ;
  wire \cplfifo_s_axis_tdata_reg_n_0_[9] ;
  wire [7:4]cplfifo_s_axis_tkeep;
  wire cplfifo_s_axis_tlast_reg_n_0;
  wire cplfifo_s_axis_tready;
  wire [21:0]cplfifo_s_axis_tuser;
  wire cplfifo_s_axis_tvalid;
  wire cplfifo_s_axis_tvalid_i_1_n_0;
  wire cplfifo_s_axis_tvalid_reg_n_0;
  wire dmaFlag;
  wire empty_fwft_i_reg;
  wire [31:0]\goreg_bm.dout_i_reg[38] ;
  wire [2:0]\goreg_dm.dout_i_reg[4] ;
  wire [3:0]\goreg_dm.dout_i_reg[59] ;
  wire [7:0]\goreg_dm.dout_i_reg[59]_0 ;
  wire [63:0]\goreg_dm.dout_i_reg[94] ;
  wire in_packet_q;
  wire in_packet_q_0;
  wire in_packet_q_reg;
  wire [15:0]in_packet_q_reg_0;
  wire [11:0]in_packet_q_reg_1;
  wire [9:0]in_packet_q_reg_2;
  wire [2:0]in_packet_q_reg_3;
  wire [2:0]in_packet_q_reg_4;
  wire [2:0]in_packet_q_reg_5;
  wire in_pkt;
  wire in_pkt_i_1_n_0;
  wire [7:7]m_axis_rx_cpl_tdata;
  wire m_axis_rx_cpl_tlast;
  wire m_axis_rx_cpl_tready;
  wire [6:2]m_axis_rx_tgt_tuser;
  wire [3:0]m_axis_rx_tkeep_o;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire m_axis_rx_tready_i;
  wire [13:0]m_axis_rx_tuser_o;
  wire m_axis_rx_tvalid;
  wire [62:0]m_axis_tdata;
  wire m_axis_tlast;
  wire m_axis_tready;
  wire m_axis_tvalid;
  wire req_ATS;
  wire req_LTR;
  wire req_OBFF;
  wire req_VDM;
  wire req_mesg;
  wire [0:0]\s_axis_rc\.tready ;
  wire [0:0]state;
  wire \tgtfifo_s_axis_tdata[63]_i_1_n_0 ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[0] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[10] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[11] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[12] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[13] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[14] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[15] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[16] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[17] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[18] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[19] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[1] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[20] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[21] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[22] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[23] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[24] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[25] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[26] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[27] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[28] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[29] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[2] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[30] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[31] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[32] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[33] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[34] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[35] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[36] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[37] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[38] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[39] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[3] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[40] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[41] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[42] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[43] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[44] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[45] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[46] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[47] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[48] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[49] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[4] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[50] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[51] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[52] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[53] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[54] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[55] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[56] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[57] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[58] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[59] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[5] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[60] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[61] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[62] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[63] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[6] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[7] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[8] ;
  wire \tgtfifo_s_axis_tdata_reg_n_0_[9] ;
  wire [7:7]tgtfifo_s_axis_tkeep;
  wire tgtfifo_s_axis_tlast_reg_n_0;
  wire tgtfifo_s_axis_tready;
  wire [8:0]tgtfifo_s_axis_tuser;
  wire tgtfifo_s_axis_tvalid_i_1_n_0;
  wire tgtfifo_s_axis_tvalid_i_2_n_0;
  wire tgtfifo_s_axis_tvalid_reg_n_0;
  wire \tx_64.req_ATS_i_2_n_0 ;
  wire \tx_64.req_OBFF_i_2_n_0 ;
  wire \tx_64.req_VDM_i_2_n_0 ;
  wire \tx_64.req_bar_id_reg[0] ;
  wire user_clk_out;
  wire user_reset_out;
  wire user_reset_out_reg;
  wire NLW_dma_cpl_fifo_inst_axis_prog_full_UNCONNECTED;
  wire [7:0]NLW_dma_cpl_fifo_inst_m_axis_tkeep_UNCONNECTED;
  wire [21:0]NLW_dma_cpl_fifo_inst_m_axis_tuser_UNCONNECTED;
  wire NLW_tgt_brdg_fifo_inst_axis_prog_full_UNCONNECTED;
  wire [7:0]NLW_tgt_brdg_fifo_inst_m_axis_tkeep_UNCONNECTED;
  wire [21:0]NLW_tgt_brdg_fifo_inst_m_axis_tuser_UNCONNECTED;

  LUT6 #(
    .INIT(64'hFFFF02FF00000200)) 
    active_intfc_i_1
       (.I0(D[27]),
        .I1(D[28]),
        .I2(D[26]),
        .I3(active_intfc1),
        .I4(in_pkt),
        .I5(active_intfc),
        .O(active_intfc_i_1_n_0));
  LUT5 #(
    .INIT(32'hA0808880)) 
    active_intfc_i_2
       (.I0(m_axis_rx_tvalid),
        .I1(tgtfifo_s_axis_tready),
        .I2(cplfifo_s_axis_tready),
        .I3(in_pkt),
        .I4(active_intfc),
        .O(active_intfc1));
  FDRE active_intfc_reg
       (.C(user_clk_out),
        .CE(1'b1),
        .D(active_intfc_i_1_n_0),
        .Q(active_intfc),
        .R(user_reset_out));
  LUT2 #(
    .INIT(4'h2)) 
    \cplfifo_s_axis_tdata[63]_i_1 
       (.I0(cplfifo_s_axis_tready),
        .I1(user_reset_out),
        .O(\cplfifo_s_axis_tdata[63]_i_1_n_0 ));
  FDRE \cplfifo_s_axis_tdata_reg[0] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[0]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[10] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[10]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[11] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[11]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[12] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[12]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[13] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[13]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[14] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[14]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[15] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[15]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[16] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[16]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[17] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[17]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[18] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[18]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[19] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[19]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[1] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[1]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[20] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[20]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[21] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[21]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[22] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[22]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[23] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[23]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[24] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[24]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[25] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[25]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[26] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[26]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[27] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[27]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[28] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[28]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[29] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[29]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[2] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[2]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[30] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[30]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[31] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[31]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[32] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[32]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[32] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[33] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[33]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[33] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[34] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[34]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[34] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[35] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[35]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[35] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[36] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[36]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[36] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[37] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[37]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[37] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[38] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[38]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[38] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[39] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[39]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[39] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[3] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[3]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[40] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[40]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[40] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[41] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[41]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[41] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[42] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[42]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[42] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[43] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[43]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[43] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[44] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[44]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[45] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[45]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[46] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[46]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[47] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[47]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[48] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[48]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[48] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[49] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[49]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[49] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[4] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[4]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[50] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[50]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[50] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[51] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[51]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[51] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[52] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[52]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[52] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[53] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[53]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[53] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[54] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[54]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[54] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[55] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[55]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[55] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[56] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[56]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[56] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[57] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[57]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[57] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[58] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[58]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[58] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[59] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[59]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[59] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[5] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[5]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[60] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[60]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[60] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[61] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[61]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[61] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[62] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[62]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[62] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[63] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[63]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[63] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[6] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[6]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[7] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[7]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[8] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[8]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tdata_reg[9] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[9]),
        .Q(\cplfifo_s_axis_tdata_reg_n_0_[9] ),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tkeep_reg[4] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tkeep_o[0]),
        .Q(cplfifo_s_axis_tkeep[4]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tkeep_reg[5] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tkeep_o[1]),
        .Q(cplfifo_s_axis_tkeep[5]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tkeep_reg[6] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tkeep_o[2]),
        .Q(cplfifo_s_axis_tkeep[6]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tkeep_reg[7] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tkeep_o[3]),
        .Q(cplfifo_s_axis_tkeep[7]),
        .R(1'b0));
  FDRE cplfifo_s_axis_tlast_reg
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tlast),
        .Q(cplfifo_s_axis_tlast_reg_n_0),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[0] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[0]),
        .Q(cplfifo_s_axis_tuser[0]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[14] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[9]),
        .Q(cplfifo_s_axis_tuser[14]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[17] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[10]),
        .Q(cplfifo_s_axis_tuser[17]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[18] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[11]),
        .Q(cplfifo_s_axis_tuser[18]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[19] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[12]),
        .Q(cplfifo_s_axis_tuser[19]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[1] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[1]),
        .Q(cplfifo_s_axis_tuser[1]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[21] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[13]),
        .Q(cplfifo_s_axis_tuser[21]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[2] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[2]),
        .Q(cplfifo_s_axis_tuser[2]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[3] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[3]),
        .Q(cplfifo_s_axis_tuser[3]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[4] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[4]),
        .Q(cplfifo_s_axis_tuser[4]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[5] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[5]),
        .Q(cplfifo_s_axis_tuser[5]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[6] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[6]),
        .Q(cplfifo_s_axis_tuser[6]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[7] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[7]),
        .Q(cplfifo_s_axis_tuser[7]),
        .R(1'b0));
  FDRE \cplfifo_s_axis_tuser_reg[8] 
       (.C(user_clk_out),
        .CE(\cplfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[8]),
        .Q(cplfifo_s_axis_tuser[8]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h22032200)) 
    cplfifo_s_axis_tvalid_i_1
       (.I0(cplfifo_s_axis_tvalid),
        .I1(user_reset_out),
        .I2(cplfifo_s_axis_tready),
        .I3(active_intfc1),
        .I4(cplfifo_s_axis_tvalid_reg_n_0),
        .O(cplfifo_s_axis_tvalid_i_1_n_0));
  LUT5 #(
    .INIT(32'h888888B8)) 
    cplfifo_s_axis_tvalid_i_2
       (.I0(active_intfc),
        .I1(in_pkt),
        .I2(D[27]),
        .I3(D[28]),
        .I4(D[26]),
        .O(cplfifo_s_axis_tvalid));
  FDRE cplfifo_s_axis_tvalid_reg
       (.C(user_clk_out),
        .CE(1'b1),
        .D(cplfifo_s_axis_tvalid_i_1_n_0),
        .Q(cplfifo_s_axis_tvalid_reg_n_0),
        .R(1'b0));
  (* CHECK_LICENSE_TYPE = "pcie2_fifo_generator_dma_cpl,fifo_generator_v13_1_5,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "fifo_generator_v13_1_5,Vivado 2024.1" *) 
  xdma_0_pcie2_fifo_generator_dma_cpl dma_cpl_fifo_inst
       (.axis_prog_full(NLW_dma_cpl_fifo_inst_axis_prog_full_UNCONNECTED),
        .m_axis_tdata({m_axis_tdata[62:7],m_axis_rx_cpl_tdata,m_axis_tdata[6:0]}),
        .m_axis_tkeep(NLW_dma_cpl_fifo_inst_m_axis_tkeep_UNCONNECTED[7:0]),
        .m_axis_tlast(m_axis_rx_cpl_tlast),
        .m_axis_tready(m_axis_rx_cpl_tready),
        .m_axis_tuser(NLW_dma_cpl_fifo_inst_m_axis_tuser_UNCONNECTED[21:0]),
        .m_axis_tvalid(m_axis_tvalid),
        .s_aclk(user_clk_out),
        .s_aresetn(E),
        .s_axis_tdata({\cplfifo_s_axis_tdata_reg_n_0_[63] ,\cplfifo_s_axis_tdata_reg_n_0_[62] ,\cplfifo_s_axis_tdata_reg_n_0_[61] ,\cplfifo_s_axis_tdata_reg_n_0_[60] ,\cplfifo_s_axis_tdata_reg_n_0_[59] ,\cplfifo_s_axis_tdata_reg_n_0_[58] ,\cplfifo_s_axis_tdata_reg_n_0_[57] ,\cplfifo_s_axis_tdata_reg_n_0_[56] ,\cplfifo_s_axis_tdata_reg_n_0_[55] ,\cplfifo_s_axis_tdata_reg_n_0_[54] ,\cplfifo_s_axis_tdata_reg_n_0_[53] ,\cplfifo_s_axis_tdata_reg_n_0_[52] ,\cplfifo_s_axis_tdata_reg_n_0_[51] ,\cplfifo_s_axis_tdata_reg_n_0_[50] ,\cplfifo_s_axis_tdata_reg_n_0_[49] ,\cplfifo_s_axis_tdata_reg_n_0_[48] ,\cplfifo_s_axis_tdata_reg_n_0_[47] ,\cplfifo_s_axis_tdata_reg_n_0_[46] ,\cplfifo_s_axis_tdata_reg_n_0_[45] ,\cplfifo_s_axis_tdata_reg_n_0_[44] ,\cplfifo_s_axis_tdata_reg_n_0_[43] ,\cplfifo_s_axis_tdata_reg_n_0_[42] ,\cplfifo_s_axis_tdata_reg_n_0_[41] ,\cplfifo_s_axis_tdata_reg_n_0_[40] ,\cplfifo_s_axis_tdata_reg_n_0_[39] ,\cplfifo_s_axis_tdata_reg_n_0_[38] ,\cplfifo_s_axis_tdata_reg_n_0_[37] ,\cplfifo_s_axis_tdata_reg_n_0_[36] ,\cplfifo_s_axis_tdata_reg_n_0_[35] ,\cplfifo_s_axis_tdata_reg_n_0_[34] ,\cplfifo_s_axis_tdata_reg_n_0_[33] ,\cplfifo_s_axis_tdata_reg_n_0_[32] ,\cplfifo_s_axis_tdata_reg_n_0_[31] ,\cplfifo_s_axis_tdata_reg_n_0_[30] ,\cplfifo_s_axis_tdata_reg_n_0_[29] ,\cplfifo_s_axis_tdata_reg_n_0_[28] ,\cplfifo_s_axis_tdata_reg_n_0_[27] ,\cplfifo_s_axis_tdata_reg_n_0_[26] ,\cplfifo_s_axis_tdata_reg_n_0_[25] ,\cplfifo_s_axis_tdata_reg_n_0_[24] ,\cplfifo_s_axis_tdata_reg_n_0_[23] ,\cplfifo_s_axis_tdata_reg_n_0_[22] ,\cplfifo_s_axis_tdata_reg_n_0_[21] ,\cplfifo_s_axis_tdata_reg_n_0_[20] ,\cplfifo_s_axis_tdata_reg_n_0_[19] ,\cplfifo_s_axis_tdata_reg_n_0_[18] ,\cplfifo_s_axis_tdata_reg_n_0_[17] ,\cplfifo_s_axis_tdata_reg_n_0_[16] ,\cplfifo_s_axis_tdata_reg_n_0_[15] ,\cplfifo_s_axis_tdata_reg_n_0_[14] ,\cplfifo_s_axis_tdata_reg_n_0_[13] ,\cplfifo_s_axis_tdata_reg_n_0_[12] ,\cplfifo_s_axis_tdata_reg_n_0_[11] ,\cplfifo_s_axis_tdata_reg_n_0_[10] ,\cplfifo_s_axis_tdata_reg_n_0_[9] ,\cplfifo_s_axis_tdata_reg_n_0_[8] ,\cplfifo_s_axis_tdata_reg_n_0_[7] ,\cplfifo_s_axis_tdata_reg_n_0_[6] ,\cplfifo_s_axis_tdata_reg_n_0_[5] ,\cplfifo_s_axis_tdata_reg_n_0_[4] ,\cplfifo_s_axis_tdata_reg_n_0_[3] ,\cplfifo_s_axis_tdata_reg_n_0_[2] ,\cplfifo_s_axis_tdata_reg_n_0_[1] ,\cplfifo_s_axis_tdata_reg_n_0_[0] }),
        .s_axis_tkeep({cplfifo_s_axis_tkeep,1'b1,1'b1,1'b1,1'b1}),
        .s_axis_tlast(cplfifo_s_axis_tlast_reg_n_0),
        .s_axis_tready(cplfifo_s_axis_tready),
        .s_axis_tuser({cplfifo_s_axis_tuser[21],1'b0,cplfifo_s_axis_tuser[19:17],1'b0,1'b0,cplfifo_s_axis_tuser[14],1'b0,1'b0,1'b0,1'b0,1'b0,cplfifo_s_axis_tuser[8:0]}),
        .s_axis_tvalid(cplfifo_s_axis_tvalid_reg_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1972" *) 
  LUT2 #(
    .INIT(4'hE)) 
    dma_cpl_fifo_inst_i_2
       (.I0(user_reset_out),
        .I1(\s_axis_rc\.tready ),
        .O(m_axis_rx_cpl_tready));
  (* SOFT_HLUTNM = "soft_lutpair1972" *) 
  LUT5 #(
    .INIT(32'h05444444)) 
    in_packet_q_i_1__0
       (.I0(user_reset_out),
        .I1(in_packet_q_0),
        .I2(m_axis_rx_cpl_tlast),
        .I3(m_axis_tvalid),
        .I4(\s_axis_rc\.tready ),
        .O(user_reset_out_reg));
  LUT6 #(
    .INIT(64'h27FF0000FFFFC000)) 
    in_pkt_i_1
       (.I0(active_intfc),
        .I1(cplfifo_s_axis_tready),
        .I2(tgtfifo_s_axis_tready),
        .I3(m_axis_rx_tvalid),
        .I4(in_pkt),
        .I5(m_axis_rx_tlast),
        .O(in_pkt_i_1_n_0));
  FDRE in_pkt_reg
       (.C(user_clk_out),
        .CE(1'b1),
        .D(in_pkt_i_1_n_0),
        .Q(in_pkt),
        .R(user_reset_out));
  LUT6 #(
    .INIT(64'hF480FFFFF4800000)) 
    pcie2_ip_i_i_73
       (.I0(active_intfc),
        .I1(in_pkt),
        .I2(cplfifo_s_axis_tready),
        .I3(tgtfifo_s_axis_tready),
        .I4(dmaFlag),
        .I5(m_axis_rx_tready_i),
        .O(m_axis_rx_tready));
  (* SOFT_HLUTNM = "soft_lutpair1992" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_attr[0]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[11]),
        .O(in_packet_q_reg_3[0]));
  (* SOFT_HLUTNM = "soft_lutpair1992" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_attr[1]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[12]),
        .O(in_packet_q_reg_3[1]));
  (* SOFT_HLUTNM = "soft_lutpair1993" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_attr[2]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[17]),
        .O(in_packet_q_reg_3[2]));
  (* SOFT_HLUTNM = "soft_lutpair1981" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[0]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[31]),
        .O(in_packet_q_reg_1[0]));
  (* SOFT_HLUTNM = "soft_lutpair1986" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[10]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[41]),
        .O(in_packet_q_reg_1[10]));
  (* SOFT_HLUTNM = "soft_lutpair1986" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[11]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[42]),
        .O(in_packet_q_reg_1[11]));
  (* SOFT_HLUTNM = "soft_lutpair1981" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[1]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[32]),
        .O(in_packet_q_reg_1[1]));
  (* SOFT_HLUTNM = "soft_lutpair1982" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[2]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[33]),
        .O(in_packet_q_reg_1[2]));
  (* SOFT_HLUTNM = "soft_lutpair1982" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[3]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[34]),
        .O(in_packet_q_reg_1[3]));
  (* SOFT_HLUTNM = "soft_lutpair1983" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[4]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[35]),
        .O(in_packet_q_reg_1[4]));
  (* SOFT_HLUTNM = "soft_lutpair1983" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[5]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[36]),
        .O(in_packet_q_reg_1[5]));
  (* SOFT_HLUTNM = "soft_lutpair1984" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[6]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[37]),
        .O(in_packet_q_reg_1[6]));
  (* SOFT_HLUTNM = "soft_lutpair1984" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[7]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[38]),
        .O(in_packet_q_reg_1[7]));
  (* SOFT_HLUTNM = "soft_lutpair1985" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[8]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[39]),
        .O(in_packet_q_reg_1[8]));
  (* SOFT_HLUTNM = "soft_lutpair1985" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_byte[9]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[40]),
        .O(in_packet_q_reg_1[9]));
  (* SOFT_HLUTNM = "soft_lutpair1973" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[0]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[47]),
        .O(in_packet_q_reg_0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1978" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[10]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[57]),
        .O(in_packet_q_reg_0[10]));
  (* SOFT_HLUTNM = "soft_lutpair1978" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[11]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[58]),
        .O(in_packet_q_reg_0[11]));
  (* SOFT_HLUTNM = "soft_lutpair1979" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[12]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[59]),
        .O(in_packet_q_reg_0[12]));
  (* SOFT_HLUTNM = "soft_lutpair1979" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[13]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[60]),
        .O(in_packet_q_reg_0[13]));
  (* SOFT_HLUTNM = "soft_lutpair1980" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[14]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[61]),
        .O(in_packet_q_reg_0[14]));
  (* SOFT_HLUTNM = "soft_lutpair1980" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[15]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[62]),
        .O(in_packet_q_reg_0[15]));
  (* SOFT_HLUTNM = "soft_lutpair1973" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[1]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[48]),
        .O(in_packet_q_reg_0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1974" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[2]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[49]),
        .O(in_packet_q_reg_0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1974" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[3]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[50]),
        .O(in_packet_q_reg_0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1975" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[4]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[51]),
        .O(in_packet_q_reg_0[4]));
  (* SOFT_HLUTNM = "soft_lutpair1975" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[5]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[52]),
        .O(in_packet_q_reg_0[5]));
  (* SOFT_HLUTNM = "soft_lutpair1976" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[6]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[53]),
        .O(in_packet_q_reg_0[6]));
  (* SOFT_HLUTNM = "soft_lutpair1976" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[7]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[54]),
        .O(in_packet_q_reg_0[7]));
  (* SOFT_HLUTNM = "soft_lutpair1977" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[8]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[55]),
        .O(in_packet_q_reg_0[8]));
  (* SOFT_HLUTNM = "soft_lutpair1977" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_cid[9]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[56]),
        .O(in_packet_q_reg_0[9]));
  (* SOFT_HLUTNM = "soft_lutpair1995" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_compl_status[0]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[44]),
        .O(in_packet_q_reg_5[0]));
  (* SOFT_HLUTNM = "soft_lutpair1995" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_compl_status[1]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[45]),
        .O(in_packet_q_reg_5[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_compl_status[2]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[46]),
        .O(in_packet_q_reg_5[2]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[0]_i_1 
       (.I0(m_axis_tdata[23]),
        .I1(m_axis_tdata[55]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [0]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[10]_i_1 
       (.I0(m_axis_tdata[17]),
        .I1(m_axis_tdata[49]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [10]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[11]_i_1 
       (.I0(m_axis_tdata[18]),
        .I1(m_axis_tdata[50]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [11]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[12]_i_1 
       (.I0(m_axis_tdata[19]),
        .I1(m_axis_tdata[51]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [12]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[13]_i_1 
       (.I0(m_axis_tdata[20]),
        .I1(m_axis_tdata[52]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [13]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[14]_i_1 
       (.I0(m_axis_tdata[21]),
        .I1(m_axis_tdata[53]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [14]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[15]_i_1 
       (.I0(m_axis_tdata[22]),
        .I1(m_axis_tdata[54]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [15]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[16]_i_1 
       (.I0(m_axis_tdata[7]),
        .I1(m_axis_tdata[39]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [16]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[17]_i_1 
       (.I0(m_axis_tdata[8]),
        .I1(m_axis_tdata[40]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [17]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[18]_i_1 
       (.I0(m_axis_tdata[9]),
        .I1(m_axis_tdata[41]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [18]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[19]_i_1 
       (.I0(m_axis_tdata[10]),
        .I1(m_axis_tdata[42]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [19]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[1]_i_1 
       (.I0(m_axis_tdata[24]),
        .I1(m_axis_tdata[56]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [1]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[20]_i_1 
       (.I0(m_axis_tdata[11]),
        .I1(m_axis_tdata[43]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [20]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[21]_i_1 
       (.I0(m_axis_tdata[12]),
        .I1(m_axis_tdata[44]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [21]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[22]_i_1 
       (.I0(m_axis_tdata[13]),
        .I1(m_axis_tdata[45]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [22]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[23]_i_1 
       (.I0(m_axis_tdata[14]),
        .I1(m_axis_tdata[46]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [23]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[24]_i_1 
       (.I0(m_axis_tdata[0]),
        .I1(m_axis_tdata[31]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [24]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[25]_i_1 
       (.I0(m_axis_tdata[1]),
        .I1(m_axis_tdata[32]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [25]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[26]_i_1 
       (.I0(m_axis_tdata[2]),
        .I1(m_axis_tdata[33]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [26]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[27]_i_1 
       (.I0(m_axis_tdata[3]),
        .I1(m_axis_tdata[34]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [27]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[28]_i_1 
       (.I0(m_axis_tdata[4]),
        .I1(m_axis_tdata[35]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [28]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[29]_i_1 
       (.I0(m_axis_tdata[5]),
        .I1(m_axis_tdata[36]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [29]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[2]_i_1 
       (.I0(m_axis_tdata[25]),
        .I1(m_axis_tdata[57]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [2]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[30]_i_1 
       (.I0(m_axis_tdata[6]),
        .I1(m_axis_tdata[37]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [30]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[31]_i_1 
       (.I0(m_axis_rx_cpl_tdata),
        .I1(m_axis_tdata[38]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [31]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[3]_i_1 
       (.I0(m_axis_tdata[26]),
        .I1(m_axis_tdata[58]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [3]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[4]_i_1 
       (.I0(m_axis_tdata[27]),
        .I1(m_axis_tdata[59]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [4]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[5]_i_1 
       (.I0(m_axis_tdata[28]),
        .I1(m_axis_tdata[60]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [5]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[6]_i_1 
       (.I0(m_axis_tdata[29]),
        .I1(m_axis_tdata[61]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [6]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[7]_i_1 
       (.I0(m_axis_tdata[30]),
        .I1(m_axis_tdata[62]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [7]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[8]_i_1 
       (.I0(m_axis_tdata[15]),
        .I1(m_axis_tdata[47]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [8]));
  LUT4 #(
    .INIT(16'hAAC0)) 
    \rc_64.wr_data[9]_i_1 
       (.I0(m_axis_tdata[16]),
        .I1(m_axis_tdata[48]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\goreg_bm.dout_i_reg[38] [9]));
  (* SOFT_HLUTNM = "soft_lutpair1987" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_len[0]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[0]),
        .O(in_packet_q_reg_2[0]));
  (* SOFT_HLUTNM = "soft_lutpair1987" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_len[1]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[1]),
        .O(in_packet_q_reg_2[1]));
  (* SOFT_HLUTNM = "soft_lutpair1988" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_len[2]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[2]),
        .O(in_packet_q_reg_2[2]));
  (* SOFT_HLUTNM = "soft_lutpair1988" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_len[3]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[3]),
        .O(in_packet_q_reg_2[3]));
  (* SOFT_HLUTNM = "soft_lutpair1989" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_len[4]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[4]),
        .O(in_packet_q_reg_2[4]));
  (* SOFT_HLUTNM = "soft_lutpair1989" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_len[5]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[5]),
        .O(in_packet_q_reg_2[5]));
  (* SOFT_HLUTNM = "soft_lutpair1990" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_len[6]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[6]),
        .O(in_packet_q_reg_2[6]));
  (* SOFT_HLUTNM = "soft_lutpair1990" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_len[7]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_rx_cpl_tdata),
        .O(in_packet_q_reg_2[7]));
  (* SOFT_HLUTNM = "soft_lutpair1991" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_len[8]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[7]),
        .O(in_packet_q_reg_2[8]));
  (* SOFT_HLUTNM = "soft_lutpair1991" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_len[9]_i_2 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[8]),
        .O(in_packet_q_reg_2[9]));
  (* SOFT_HLUTNM = "soft_lutpair1993" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_tc[0]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[19]),
        .O(in_packet_q_reg_4[0]));
  (* SOFT_HLUTNM = "soft_lutpair1994" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_tc[1]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[20]),
        .O(in_packet_q_reg_4[1]));
  (* SOFT_HLUTNM = "soft_lutpair1994" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rc_64.wr_tc[2]_i_1 
       (.I0(in_packet_q_0),
        .I1(m_axis_tvalid),
        .I2(m_axis_tdata[21]),
        .O(in_packet_q_reg_4[2]));
  (* CHECK_LICENSE_TYPE = "pcie2_fifo_generator_tgt_brdg,fifo_generator_v13_1_5,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "fifo_generator_v13_1_5,Vivado 2024.1" *) 
  xdma_0_pcie2_fifo_generator_tgt_brdg tgt_brdg_fifo_inst
       (.axis_prog_full(NLW_tgt_brdg_fifo_inst_axis_prog_full_UNCONNECTED),
        .m_axis_tdata(\goreg_dm.dout_i_reg[94] ),
        .m_axis_tkeep(NLW_tgt_brdg_fifo_inst_m_axis_tkeep_UNCONNECTED[7:0]),
        .m_axis_tlast(m_axis_tlast),
        .m_axis_tready(m_axis_tready),
        .m_axis_tuser({NLW_tgt_brdg_fifo_inst_m_axis_tuser_UNCONNECTED[21:7],m_axis_rx_tgt_tuser,NLW_tgt_brdg_fifo_inst_m_axis_tuser_UNCONNECTED[1:0]}),
        .m_axis_tvalid(empty_fwft_i_reg),
        .s_aclk(user_clk_out),
        .s_aresetn(E),
        .s_axis_tdata({\tgtfifo_s_axis_tdata_reg_n_0_[63] ,\tgtfifo_s_axis_tdata_reg_n_0_[62] ,\tgtfifo_s_axis_tdata_reg_n_0_[61] ,\tgtfifo_s_axis_tdata_reg_n_0_[60] ,\tgtfifo_s_axis_tdata_reg_n_0_[59] ,\tgtfifo_s_axis_tdata_reg_n_0_[58] ,\tgtfifo_s_axis_tdata_reg_n_0_[57] ,\tgtfifo_s_axis_tdata_reg_n_0_[56] ,\tgtfifo_s_axis_tdata_reg_n_0_[55] ,\tgtfifo_s_axis_tdata_reg_n_0_[54] ,\tgtfifo_s_axis_tdata_reg_n_0_[53] ,\tgtfifo_s_axis_tdata_reg_n_0_[52] ,\tgtfifo_s_axis_tdata_reg_n_0_[51] ,\tgtfifo_s_axis_tdata_reg_n_0_[50] ,\tgtfifo_s_axis_tdata_reg_n_0_[49] ,\tgtfifo_s_axis_tdata_reg_n_0_[48] ,\tgtfifo_s_axis_tdata_reg_n_0_[47] ,\tgtfifo_s_axis_tdata_reg_n_0_[46] ,\tgtfifo_s_axis_tdata_reg_n_0_[45] ,\tgtfifo_s_axis_tdata_reg_n_0_[44] ,\tgtfifo_s_axis_tdata_reg_n_0_[43] ,\tgtfifo_s_axis_tdata_reg_n_0_[42] ,\tgtfifo_s_axis_tdata_reg_n_0_[41] ,\tgtfifo_s_axis_tdata_reg_n_0_[40] ,\tgtfifo_s_axis_tdata_reg_n_0_[39] ,\tgtfifo_s_axis_tdata_reg_n_0_[38] ,\tgtfifo_s_axis_tdata_reg_n_0_[37] ,\tgtfifo_s_axis_tdata_reg_n_0_[36] ,\tgtfifo_s_axis_tdata_reg_n_0_[35] ,\tgtfifo_s_axis_tdata_reg_n_0_[34] ,\tgtfifo_s_axis_tdata_reg_n_0_[33] ,\tgtfifo_s_axis_tdata_reg_n_0_[32] ,\tgtfifo_s_axis_tdata_reg_n_0_[31] ,\tgtfifo_s_axis_tdata_reg_n_0_[30] ,\tgtfifo_s_axis_tdata_reg_n_0_[29] ,\tgtfifo_s_axis_tdata_reg_n_0_[28] ,\tgtfifo_s_axis_tdata_reg_n_0_[27] ,\tgtfifo_s_axis_tdata_reg_n_0_[26] ,\tgtfifo_s_axis_tdata_reg_n_0_[25] ,\tgtfifo_s_axis_tdata_reg_n_0_[24] ,\tgtfifo_s_axis_tdata_reg_n_0_[23] ,\tgtfifo_s_axis_tdata_reg_n_0_[22] ,\tgtfifo_s_axis_tdata_reg_n_0_[21] ,\tgtfifo_s_axis_tdata_reg_n_0_[20] ,\tgtfifo_s_axis_tdata_reg_n_0_[19] ,\tgtfifo_s_axis_tdata_reg_n_0_[18] ,\tgtfifo_s_axis_tdata_reg_n_0_[17] ,\tgtfifo_s_axis_tdata_reg_n_0_[16] ,\tgtfifo_s_axis_tdata_reg_n_0_[15] ,\tgtfifo_s_axis_tdata_reg_n_0_[14] ,\tgtfifo_s_axis_tdata_reg_n_0_[13] ,\tgtfifo_s_axis_tdata_reg_n_0_[12] ,\tgtfifo_s_axis_tdata_reg_n_0_[11] ,\tgtfifo_s_axis_tdata_reg_n_0_[10] ,\tgtfifo_s_axis_tdata_reg_n_0_[9] ,\tgtfifo_s_axis_tdata_reg_n_0_[8] ,\tgtfifo_s_axis_tdata_reg_n_0_[7] ,\tgtfifo_s_axis_tdata_reg_n_0_[6] ,\tgtfifo_s_axis_tdata_reg_n_0_[5] ,\tgtfifo_s_axis_tdata_reg_n_0_[4] ,\tgtfifo_s_axis_tdata_reg_n_0_[3] ,\tgtfifo_s_axis_tdata_reg_n_0_[2] ,\tgtfifo_s_axis_tdata_reg_n_0_[1] ,\tgtfifo_s_axis_tdata_reg_n_0_[0] }),
        .s_axis_tkeep({tgtfifo_s_axis_tkeep,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tlast(tgtfifo_s_axis_tlast_reg_n_0),
        .s_axis_tready(tgtfifo_s_axis_tready),
        .s_axis_tuser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,tgtfifo_s_axis_tuser}),
        .s_axis_tvalid(tgtfifo_s_axis_tvalid_reg_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    \tgtfifo_s_axis_tdata[63]_i_1 
       (.I0(tgtfifo_s_axis_tready),
        .I1(user_reset_out),
        .O(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ));
  FDRE \tgtfifo_s_axis_tdata_reg[0] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[0]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[10] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[10]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[11] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[11]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[12] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[12]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[13] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[13]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[14] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[14]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[15] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[15]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[16] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[16]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[17] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[17]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[18] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[18]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[19] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[19]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[1] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[1]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[20] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[20]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[21] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[21]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[22] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[22]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[23] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[23]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[24] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[24]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[25] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[25]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[26] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[26]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[27] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[27]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[28] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[28]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[29] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[29]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[2] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[2]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[30] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[30]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[31] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[31]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[32] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[32]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[32] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[33] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[33]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[33] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[34] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[34]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[34] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[35] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[35]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[35] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[36] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[36]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[36] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[37] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[37]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[37] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[38] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[38]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[38] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[39] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[39]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[39] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[3] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[3]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[40] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[40]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[40] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[41] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[41]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[41] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[42] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[42]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[42] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[43] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[43]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[43] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[44] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[44]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[45] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[45]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[46] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[46]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[47] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[47]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[48] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[48]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[48] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[49] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[49]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[49] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[4] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[4]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[50] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[50]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[50] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[51] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[51]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[51] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[52] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[52]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[52] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[53] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[53]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[53] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[54] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[54]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[54] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[55] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[55]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[55] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[56] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[56]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[56] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[57] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[57]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[57] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[58] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[58]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[58] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[59] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[59]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[59] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[5] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[5]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[60] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[60]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[60] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[61] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[61]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[61] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[62] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[62]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[62] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[63] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[63]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[63] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[6] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[6]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[7] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[7]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[8] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[8]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tdata_reg[9] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(D[9]),
        .Q(\tgtfifo_s_axis_tdata_reg_n_0_[9] ),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tkeep_reg[7] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tkeep_o[3]),
        .Q(tgtfifo_s_axis_tkeep),
        .R(1'b0));
  FDRE tgtfifo_s_axis_tlast_reg
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tlast),
        .Q(tgtfifo_s_axis_tlast_reg_n_0),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tuser_reg[0] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[0]),
        .Q(tgtfifo_s_axis_tuser[0]),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tuser_reg[1] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[1]),
        .Q(tgtfifo_s_axis_tuser[1]),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tuser_reg[2] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[2]),
        .Q(tgtfifo_s_axis_tuser[2]),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tuser_reg[3] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[3]),
        .Q(tgtfifo_s_axis_tuser[3]),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tuser_reg[4] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[4]),
        .Q(tgtfifo_s_axis_tuser[4]),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tuser_reg[5] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[5]),
        .Q(tgtfifo_s_axis_tuser[5]),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tuser_reg[6] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[6]),
        .Q(tgtfifo_s_axis_tuser[6]),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tuser_reg[7] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[7]),
        .Q(tgtfifo_s_axis_tuser[7]),
        .R(1'b0));
  FDRE \tgtfifo_s_axis_tuser_reg[8] 
       (.C(user_clk_out),
        .CE(\tgtfifo_s_axis_tdata[63]_i_1_n_0 ),
        .D(m_axis_rx_tuser_o[8]),
        .Q(tgtfifo_s_axis_tuser[8]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000002F2F2F2)) 
    tgtfifo_s_axis_tvalid_i_1
       (.I0(tgtfifo_s_axis_tvalid_reg_n_0),
        .I1(tgtfifo_s_axis_tready),
        .I2(active_intfc1),
        .I3(in_pkt),
        .I4(active_intfc),
        .I5(tgtfifo_s_axis_tvalid_i_2_n_0),
        .O(tgtfifo_s_axis_tvalid_i_1_n_0));
  LUT6 #(
    .INIT(64'hAAAAABAAAAAAAAAA)) 
    tgtfifo_s_axis_tvalid_i_2
       (.I0(user_reset_out),
        .I1(D[26]),
        .I2(D[28]),
        .I3(D[27]),
        .I4(in_pkt),
        .I5(active_intfc1),
        .O(tgtfifo_s_axis_tvalid_i_2_n_0));
  FDRE tgtfifo_s_axis_tvalid_reg
       (.C(user_clk_out),
        .CE(1'b1),
        .D(tgtfifo_s_axis_tvalid_i_1_n_0),
        .Q(tgtfifo_s_axis_tvalid_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00001E0000000000)) 
    \tx_64.req_ATS_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [34]),
        .I1(\goreg_dm.dout_i_reg[94] [32]),
        .I2(\goreg_dm.dout_i_reg[94] [33]),
        .I3(\tx_64.req_ATS_i_2_n_0 ),
        .I4(\goreg_dm.dout_i_reg[94] [39]),
        .I5(req_mesg),
        .O(req_ATS));
  LUT4 #(
    .INIT(16'h0001)) 
    \tx_64.req_ATS_i_2 
       (.I0(\goreg_dm.dout_i_reg[94] [36]),
        .I1(\goreg_dm.dout_i_reg[94] [35]),
        .I2(\goreg_dm.dout_i_reg[94] [38]),
        .I3(\goreg_dm.dout_i_reg[94] [37]),
        .O(\tx_64.req_ATS_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000040000000000)) 
    \tx_64.req_LTR_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [35]),
        .I1(\goreg_dm.dout_i_reg[94] [36]),
        .I2(\goreg_dm.dout_i_reg[94] [33]),
        .I3(\tx_64.req_OBFF_i_2_n_0 ),
        .I4(\goreg_dm.dout_i_reg[94] [39]),
        .I5(req_mesg),
        .O(req_LTR));
  LUT6 #(
    .INIT(64'h0000400000000000)) 
    \tx_64.req_OBFF_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [35]),
        .I1(\goreg_dm.dout_i_reg[94] [36]),
        .I2(\goreg_dm.dout_i_reg[94] [33]),
        .I3(\tx_64.req_OBFF_i_2_n_0 ),
        .I4(\goreg_dm.dout_i_reg[94] [39]),
        .I5(req_mesg),
        .O(req_OBFF));
  LUT4 #(
    .INIT(16'h0001)) 
    \tx_64.req_OBFF_i_2 
       (.I0(\goreg_dm.dout_i_reg[94] [38]),
        .I1(\goreg_dm.dout_i_reg[94] [37]),
        .I2(\goreg_dm.dout_i_reg[94] [34]),
        .I3(\goreg_dm.dout_i_reg[94] [32]),
        .O(\tx_64.req_OBFF_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2020222000000000)) 
    \tx_64.req_VDM_i_1 
       (.I0(\tx_64.req_VDM_i_2_n_0 ),
        .I1(\goreg_dm.dout_i_reg[94] [39]),
        .I2(state),
        .I3(empty_fwft_i_reg),
        .I4(in_packet_q),
        .I5(\goreg_dm.dout_i_reg[94] [28]),
        .O(req_VDM));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \tx_64.req_VDM_i_2 
       (.I0(\goreg_dm.dout_i_reg[94] [35]),
        .I1(\goreg_dm.dout_i_reg[94] [36]),
        .I2(\goreg_dm.dout_i_reg[94] [33]),
        .I3(\goreg_dm.dout_i_reg[94] [34]),
        .I4(\goreg_dm.dout_i_reg[94] [38]),
        .I5(\goreg_dm.dout_i_reg[94] [37]),
        .O(\tx_64.req_VDM_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h080808080C0C080C)) 
    \tx_64.req_bar_id[0]_i_1 
       (.I0(m_axis_rx_tgt_tuser[3]),
        .I1(\tx_64.req_bar_id_reg[0] ),
        .I2(m_axis_rx_tgt_tuser[2]),
        .I3(m_axis_rx_tgt_tuser[6]),
        .I4(m_axis_rx_tgt_tuser[5]),
        .I5(m_axis_rx_tgt_tuser[4]),
        .O(\goreg_dm.dout_i_reg[4] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1966" *) 
  LUT5 #(
    .INIT(32'h00540000)) 
    \tx_64.req_bar_id[1]_i_1 
       (.I0(m_axis_rx_tgt_tuser[3]),
        .I1(m_axis_rx_tgt_tuser[4]),
        .I2(m_axis_rx_tgt_tuser[5]),
        .I3(m_axis_rx_tgt_tuser[2]),
        .I4(\tx_64.req_bar_id_reg[0] ),
        .O(\goreg_dm.dout_i_reg[4] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1966" *) 
  LUT5 #(
    .INIT(32'h00010000)) 
    \tx_64.req_bar_id[2]_i_1 
       (.I0(m_axis_rx_tgt_tuser[3]),
        .I1(m_axis_rx_tgt_tuser[4]),
        .I2(m_axis_rx_tgt_tuser[5]),
        .I3(m_axis_rx_tgt_tuser[2]),
        .I4(\tx_64.req_bar_id_reg[0] ),
        .O(\goreg_dm.dout_i_reg[4] [2]));
  (* SOFT_HLUTNM = "soft_lutpair1967" *) 
  LUT5 #(
    .INIT(32'h55100000)) 
    \tx_64.req_fbe[0]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [32]),
        .O(\goreg_dm.dout_i_reg[59] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1968" *) 
  LUT5 #(
    .INIT(32'h55100000)) 
    \tx_64.req_fbe[1]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [33]),
        .O(\goreg_dm.dout_i_reg[59] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1969" *) 
  LUT5 #(
    .INIT(32'h55100000)) 
    \tx_64.req_fbe[2]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [34]),
        .O(\goreg_dm.dout_i_reg[59] [2]));
  (* SOFT_HLUTNM = "soft_lutpair1970" *) 
  LUT5 #(
    .INIT(32'h55100000)) 
    \tx_64.req_fbe[3]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [35]),
        .O(\goreg_dm.dout_i_reg[59] [3]));
  (* SOFT_HLUTNM = "soft_lutpair1971" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \tx_64.req_mesg_i_4 
       (.I0(empty_fwft_i_reg),
        .I1(in_packet_q),
        .O(in_packet_q_reg));
  (* SOFT_HLUTNM = "soft_lutpair1967" *) 
  LUT5 #(
    .INIT(32'hAA200000)) 
    \tx_64.req_msg_code[0]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [32]),
        .O(\goreg_dm.dout_i_reg[59]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1968" *) 
  LUT5 #(
    .INIT(32'hAA200000)) 
    \tx_64.req_msg_code[1]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [33]),
        .O(\goreg_dm.dout_i_reg[59]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1969" *) 
  LUT5 #(
    .INIT(32'hAA200000)) 
    \tx_64.req_msg_code[2]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [34]),
        .O(\goreg_dm.dout_i_reg[59]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1970" *) 
  LUT5 #(
    .INIT(32'hAA200000)) 
    \tx_64.req_msg_code[3]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [35]),
        .O(\goreg_dm.dout_i_reg[59]_0 [3]));
  LUT5 #(
    .INIT(32'hAA200000)) 
    \tx_64.req_msg_code[4]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [36]),
        .O(\goreg_dm.dout_i_reg[59]_0 [4]));
  LUT5 #(
    .INIT(32'hAA200000)) 
    \tx_64.req_msg_code[5]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [37]),
        .O(\goreg_dm.dout_i_reg[59]_0 [5]));
  LUT5 #(
    .INIT(32'hAA200000)) 
    \tx_64.req_msg_code[6]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [38]),
        .O(\goreg_dm.dout_i_reg[59]_0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair1971" *) 
  LUT5 #(
    .INIT(32'hAA200000)) 
    \tx_64.req_msg_code[7]_i_1 
       (.I0(\goreg_dm.dout_i_reg[94] [28]),
        .I1(in_packet_q),
        .I2(empty_fwft_i_reg),
        .I3(state),
        .I4(\goreg_dm.dout_i_reg[94] [39]),
        .O(\goreg_dm.dout_i_reg[59]_0 [7]));
endmodule

module xdma_0_tgt_cpl
   (tready_thrtl_reg,
    \FSM_sequential_tx_64.state_reg[1]_0 ,
    s_axis_tx_tgt_tdata,
    \m_axis_cc\.tready ,
    s_axis_tx_tgt_tkeep,
    s_axis_tx_tgt_tvalid,
    \FSM_sequential_transfer_SM_reg[1] ,
    s_axis_tx_tready,
    transfer_SM,
    s_axis_tx_req_tvalid,
    user_reset_out,
    \m_axis_cc\.tvalid ,
    user_clk_out,
    \m_axis_cc\.tdata ,
    \m_axis_cc\.tlast ,
    s_axis_tx_tgt_tready,
    cfg_function_number_o,
    cfg_device_number_o,
    cfg_bus_number_o);
  output tready_thrtl_reg;
  output \FSM_sequential_tx_64.state_reg[1]_0 ;
  output [63:0]s_axis_tx_tgt_tdata;
  output \m_axis_cc\.tready ;
  output [0:0]s_axis_tx_tgt_tkeep;
  output s_axis_tx_tgt_tvalid;
  input \FSM_sequential_transfer_SM_reg[1] ;
  input s_axis_tx_tready;
  input [1:0]transfer_SM;
  input s_axis_tx_req_tvalid;
  input user_reset_out;
  input \m_axis_cc\.tvalid ;
  input user_clk_out;
  input [63:0]\m_axis_cc\.tdata ;
  input \m_axis_cc\.tlast ;
  input s_axis_tx_tgt_tready;
  input [2:0]cfg_function_number_o;
  input [4:0]cfg_device_number_o;
  input [7:0]cfg_bus_number_o;

  wire \FSM_sequential_transfer_SM[1]_i_2_n_0 ;
  wire \FSM_sequential_transfer_SM[1]_i_4_n_0 ;
  wire \FSM_sequential_transfer_SM_reg[1] ;
  wire \FSM_sequential_tx_64.state[0]_i_1__1_n_0 ;
  wire \FSM_sequential_tx_64.state[1]_i_1__1_n_0 ;
  wire \FSM_sequential_tx_64.state_reg[1]_0 ;
  wire [7:0]cfg_bus_number_o;
  wire [4:0]cfg_device_number_o;
  wire [2:0]cfg_function_number_o;
  wire compl_addr;
  wire [63:32]compl_data;
  wire [15:0]compl_rid;
  wire compl_tag;
  wire in_packet_q;
  wire in_packet_q_i_1__2_n_0;
  wire [63:0]\m_axis_cc\.tdata ;
  wire \m_axis_cc\.tlast ;
  wire \m_axis_cc\.tready ;
  wire \m_axis_cc\.tvalid ;
  wire p_0_in;
  wire [47:0]p_6_out;
  wire s_axis_tx_req_tvalid;
  wire \s_axis_tx_tdata[0]_i_4_n_0 ;
  wire \s_axis_tx_tdata[10]_i_4_n_0 ;
  wire \s_axis_tx_tdata[11]_i_4_n_0 ;
  wire \s_axis_tx_tdata[12]_i_4_n_0 ;
  wire \s_axis_tx_tdata[13]_i_5_n_0 ;
  wire \s_axis_tx_tdata[14]_i_4_n_0 ;
  wire \s_axis_tx_tdata[18]_i_4_n_0 ;
  wire \s_axis_tx_tdata[1]_i_4_n_0 ;
  wire \s_axis_tx_tdata[20]_i_4_n_0 ;
  wire \s_axis_tx_tdata[21]_i_4_n_0 ;
  wire \s_axis_tx_tdata[22]_i_4_n_0 ;
  wire \s_axis_tx_tdata[25]_i_4_n_0 ;
  wire \s_axis_tx_tdata[27]_i_4_n_0 ;
  wire \s_axis_tx_tdata[2]_i_4_n_0 ;
  wire \s_axis_tx_tdata[30]_i_4_n_0 ;
  wire \s_axis_tx_tdata[31]_i_7_n_0 ;
  wire \s_axis_tx_tdata[31]_i_8_n_0 ;
  wire \s_axis_tx_tdata[31]_i_9_n_0 ;
  wire \s_axis_tx_tdata[3]_i_4_n_0 ;
  wire \s_axis_tx_tdata[47]_i_7_n_0 ;
  wire \s_axis_tx_tdata[47]_i_8_n_0 ;
  wire \s_axis_tx_tdata[4]_i_4_n_0 ;
  wire \s_axis_tx_tdata[55]_i_4_n_0 ;
  wire \s_axis_tx_tdata[55]_i_5_n_0 ;
  wire \s_axis_tx_tdata[55]_i_6_n_0 ;
  wire \s_axis_tx_tdata[56]_i_4_n_0 ;
  wire \s_axis_tx_tdata[57]_i_4_n_0 ;
  wire \s_axis_tx_tdata[58]_i_4_n_0 ;
  wire \s_axis_tx_tdata[59]_i_4_n_0 ;
  wire \s_axis_tx_tdata[5]_i_4_n_0 ;
  wire \s_axis_tx_tdata[60]_i_4_n_0 ;
  wire \s_axis_tx_tdata[61]_i_4_n_0 ;
  wire \s_axis_tx_tdata[62]_i_4_n_0 ;
  wire \s_axis_tx_tdata[63]_i_6_n_0 ;
  wire \s_axis_tx_tdata[6]_i_4_n_0 ;
  wire \s_axis_tx_tdata[8]_i_4_n_0 ;
  wire \s_axis_tx_tdata[9]_i_4_n_0 ;
  wire [63:0]s_axis_tx_tgt_tdata;
  wire [0:0]s_axis_tx_tgt_tkeep;
  wire s_axis_tx_tgt_tready;
  wire s_axis_tx_tgt_tvalid;
  wire s_axis_tx_tready;
  wire [0:0]state;
  wire [1:0]state__0;
  wire [1:0]transfer_SM;
  wire tready_thrtl_reg;
  wire \tx_64.compl_addr_reg_n_0_[0] ;
  wire \tx_64.compl_addr_reg_n_0_[1] ;
  wire \tx_64.compl_addr_reg_n_0_[3] ;
  wire \tx_64.compl_addr_reg_n_0_[4] ;
  wire \tx_64.compl_addr_reg_n_0_[5] ;
  wire \tx_64.compl_addr_reg_n_0_[6] ;
  wire \tx_64.compl_data_reg_n_0_[32] ;
  wire \tx_64.compl_data_reg_n_0_[33] ;
  wire \tx_64.compl_data_reg_n_0_[34] ;
  wire \tx_64.compl_data_reg_n_0_[35] ;
  wire \tx_64.compl_data_reg_n_0_[36] ;
  wire \tx_64.compl_data_reg_n_0_[37] ;
  wire \tx_64.compl_data_reg_n_0_[38] ;
  wire \tx_64.compl_data_reg_n_0_[39] ;
  wire \tx_64.compl_data_reg_n_0_[40] ;
  wire \tx_64.compl_data_reg_n_0_[41] ;
  wire \tx_64.compl_data_reg_n_0_[42] ;
  wire \tx_64.compl_data_reg_n_0_[43] ;
  wire \tx_64.compl_data_reg_n_0_[44] ;
  wire \tx_64.compl_data_reg_n_0_[45] ;
  wire \tx_64.compl_data_reg_n_0_[46] ;
  wire \tx_64.compl_data_reg_n_0_[47] ;
  wire \tx_64.compl_data_reg_n_0_[48] ;
  wire \tx_64.compl_data_reg_n_0_[49] ;
  wire \tx_64.compl_data_reg_n_0_[50] ;
  wire \tx_64.compl_data_reg_n_0_[51] ;
  wire \tx_64.compl_data_reg_n_0_[52] ;
  wire \tx_64.compl_data_reg_n_0_[53] ;
  wire \tx_64.compl_data_reg_n_0_[54] ;
  wire \tx_64.compl_data_reg_n_0_[55] ;
  wire \tx_64.compl_data_reg_n_0_[56] ;
  wire \tx_64.compl_data_reg_n_0_[57] ;
  wire \tx_64.compl_data_reg_n_0_[58] ;
  wire \tx_64.compl_data_reg_n_0_[59] ;
  wire \tx_64.compl_data_reg_n_0_[60] ;
  wire \tx_64.compl_data_reg_n_0_[61] ;
  wire \tx_64.compl_data_reg_n_0_[62] ;
  wire \tx_64.compl_data_reg_n_0_[63] ;
  wire \tx_64.compl_tag_reg_n_0_[0] ;
  wire \tx_64.compl_tag_reg_n_0_[1] ;
  wire \tx_64.compl_tag_reg_n_0_[2] ;
  wire \tx_64.compl_tag_reg_n_0_[3] ;
  wire \tx_64.compl_tag_reg_n_0_[4] ;
  wire \tx_64.compl_tag_reg_n_0_[5] ;
  wire \tx_64.compl_tag_reg_n_0_[6] ;
  wire \tx_64.compl_tag_reg_n_0_[7] ;
  wire udma_wrapper_i_154_n_0;
  wire user_clk_out;
  wire user_reset_out;

  (* SOFT_HLUTNM = "soft_lutpair2001" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \FSM_sequential_transfer_SM[0]_i_2 
       (.I0(state),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(s_axis_tx_tgt_tvalid));
  LUT6 #(
    .INIT(64'h3F3FAAFF0000AA00)) 
    \FSM_sequential_transfer_SM[1]_i_1 
       (.I0(\FSM_sequential_transfer_SM[1]_i_2_n_0 ),
        .I1(\FSM_sequential_transfer_SM_reg[1] ),
        .I2(s_axis_tx_tready),
        .I3(\FSM_sequential_transfer_SM[1]_i_4_n_0 ),
        .I4(transfer_SM[0]),
        .I5(transfer_SM[1]),
        .O(tready_thrtl_reg));
  LUT6 #(
    .INIT(64'h00000000AA22AA2A)) 
    \FSM_sequential_transfer_SM[1]_i_2 
       (.I0(s_axis_tx_req_tvalid),
        .I1(s_axis_tx_tgt_tdata[13]),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(user_reset_out),
        .I4(state),
        .I5(transfer_SM[1]),
        .O(\FSM_sequential_transfer_SM[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1998" *) 
  LUT5 #(
    .INIT(32'h0000AFAE)) 
    \FSM_sequential_transfer_SM[1]_i_4 
       (.I0(s_axis_tx_req_tvalid),
        .I1(state),
        .I2(user_reset_out),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(transfer_SM[1]),
        .O(\FSM_sequential_transfer_SM[1]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAA20)) 
    \FSM_sequential_tx_64.state[0]_i_1__1 
       (.I0(state__0[0]),
        .I1(in_packet_q),
        .I2(\m_axis_cc\.tvalid ),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(state),
        .O(\FSM_sequential_tx_64.state[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h2A2AFFFF557F5555)) 
    \FSM_sequential_tx_64.state[0]_i_2__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\m_axis_cc\.tvalid ),
        .I2(\m_axis_cc\.tlast ),
        .I3(udma_wrapper_i_154_n_0),
        .I4(s_axis_tx_tgt_tready),
        .I5(state),
        .O(state__0[0]));
  LUT5 #(
    .INIT(32'hAAAAAA20)) 
    \FSM_sequential_tx_64.state[1]_i_1__1 
       (.I0(state__0[1]),
        .I1(in_packet_q),
        .I2(\m_axis_cc\.tvalid ),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(state),
        .O(\FSM_sequential_tx_64.state[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h3FFFCCCC37770000)) 
    \FSM_sequential_tx_64.state[1]_i_2__1 
       (.I0(udma_wrapper_i_154_n_0),
        .I1(s_axis_tx_tgt_tready),
        .I2(\m_axis_cc\.tlast ),
        .I3(\m_axis_cc\.tvalid ),
        .I4(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I5(state),
        .O(state__0[1]));
  (* FSM_ENCODED_STATES = "TX_DW0_DW1:01,TX_DW2:10,TX_WAIT:11,TX_IDLE:00" *) 
  FDRE \FSM_sequential_tx_64.state_reg[0] 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\FSM_sequential_tx_64.state[0]_i_1__1_n_0 ),
        .Q(state),
        .R(user_reset_out));
  (* FSM_ENCODED_STATES = "TX_DW0_DW1:01,TX_DW2:10,TX_WAIT:11,TX_IDLE:00" *) 
  FDRE \FSM_sequential_tx_64.state_reg[1] 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\FSM_sequential_tx_64.state[1]_i_1__1_n_0 ),
        .Q(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .R(user_reset_out));
  LUT5 #(
    .INIT(32'h04544444)) 
    in_packet_q_i_1__2
       (.I0(user_reset_out),
        .I1(in_packet_q),
        .I2(\m_axis_cc\.tvalid ),
        .I3(\m_axis_cc\.tlast ),
        .I4(s_axis_tx_tgt_tready),
        .O(in_packet_q_i_1__2_n_0));
  FDRE in_packet_q_reg
       (.C(user_clk_out),
        .CE(1'b1),
        .D(in_packet_q_i_1__2_n_0),
        .Q(in_packet_q),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[0]_i_3 
       (.I0(\s_axis_tx_tdata[0]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[0]),
        .I5(\tx_64.compl_addr_reg_n_0_[0] ),
        .O(s_axis_tx_tgt_tdata[0]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[0]_i_4 
       (.I0(\m_axis_cc\.tdata [24]),
        .I1(\tx_64.compl_data_reg_n_0_[56] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[10]_i_2 
       (.I0(\s_axis_tx_tdata[10]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[10]),
        .I5(\tx_64.compl_tag_reg_n_0_[2] ),
        .O(s_axis_tx_tgt_tdata[10]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[10]_i_4 
       (.I0(\m_axis_cc\.tdata [18]),
        .I1(\tx_64.compl_data_reg_n_0_[50] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[11]_i_2 
       (.I0(\s_axis_tx_tdata[11]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[11]),
        .I5(\tx_64.compl_tag_reg_n_0_[3] ),
        .O(s_axis_tx_tgt_tdata[11]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[11]_i_4 
       (.I0(\m_axis_cc\.tdata [19]),
        .I1(\tx_64.compl_data_reg_n_0_[51] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[12]_i_2 
       (.I0(\s_axis_tx_tdata[12]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(\m_axis_cc\.tdata [28]),
        .I5(\tx_64.compl_tag_reg_n_0_[4] ),
        .O(s_axis_tx_tgt_tdata[12]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[12]_i_4 
       (.I0(\m_axis_cc\.tdata [20]),
        .I1(\tx_64.compl_data_reg_n_0_[52] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[12]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[13]_i_4 
       (.I0(\s_axis_tx_tdata[13]_i_5_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(\m_axis_cc\.tdata [29]),
        .I5(\tx_64.compl_tag_reg_n_0_[5] ),
        .O(s_axis_tx_tgt_tdata[13]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[13]_i_5 
       (.I0(\m_axis_cc\.tdata [21]),
        .I1(\tx_64.compl_data_reg_n_0_[53] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[13]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[14]_i_2 
       (.I0(\s_axis_tx_tdata[14]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[14]),
        .I5(\tx_64.compl_tag_reg_n_0_[6] ),
        .O(s_axis_tx_tgt_tdata[14]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[14]_i_4 
       (.I0(\m_axis_cc\.tdata [22]),
        .I1(\tx_64.compl_data_reg_n_0_[54] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[14]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[15]_i_3 
       (.I0(\s_axis_tx_tdata[31]_i_7_n_0 ),
        .I1(\tx_64.compl_tag_reg_n_0_[7] ),
        .I2(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I3(\tx_64.compl_data_reg_n_0_[55] ),
        .I4(\m_axis_cc\.tdata [23]),
        .I5(\s_axis_tx_tdata[31]_i_9_n_0 ),
        .O(s_axis_tx_tgt_tdata[15]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[16]_i_3 
       (.I0(\s_axis_tx_tdata[31]_i_7_n_0 ),
        .I1(compl_rid[0]),
        .I2(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I3(\tx_64.compl_data_reg_n_0_[40] ),
        .I4(\m_axis_cc\.tdata [8]),
        .I5(\s_axis_tx_tdata[31]_i_9_n_0 ),
        .O(s_axis_tx_tgt_tdata[16]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[17]_i_3 
       (.I0(\s_axis_tx_tdata[31]_i_7_n_0 ),
        .I1(compl_rid[1]),
        .I2(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I3(\tx_64.compl_data_reg_n_0_[41] ),
        .I4(\m_axis_cc\.tdata [9]),
        .I5(\s_axis_tx_tdata[31]_i_9_n_0 ),
        .O(s_axis_tx_tgt_tdata[17]));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[18]_i_2 
       (.I0(\s_axis_tx_tdata[18]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(\m_axis_cc\.tdata [30]),
        .I5(compl_rid[2]),
        .O(s_axis_tx_tgt_tdata[18]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[18]_i_4 
       (.I0(\m_axis_cc\.tdata [10]),
        .I1(\tx_64.compl_data_reg_n_0_[42] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[18]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[19]_i_3 
       (.I0(\s_axis_tx_tdata[31]_i_7_n_0 ),
        .I1(compl_rid[3]),
        .I2(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I3(\tx_64.compl_data_reg_n_0_[43] ),
        .I4(\m_axis_cc\.tdata [11]),
        .I5(\s_axis_tx_tdata[31]_i_9_n_0 ),
        .O(s_axis_tx_tgt_tdata[19]));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[1]_i_3 
       (.I0(\s_axis_tx_tdata[1]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[1]),
        .I5(\tx_64.compl_addr_reg_n_0_[1] ),
        .O(s_axis_tx_tgt_tdata[1]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[1]_i_4 
       (.I0(\m_axis_cc\.tdata [25]),
        .I1(\tx_64.compl_data_reg_n_0_[57] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[20]_i_2 
       (.I0(\s_axis_tx_tdata[20]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(\m_axis_cc\.tdata [25]),
        .I5(compl_rid[4]),
        .O(s_axis_tx_tgt_tdata[20]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[20]_i_4 
       (.I0(\m_axis_cc\.tdata [12]),
        .I1(\tx_64.compl_data_reg_n_0_[44] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[20]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[21]_i_2 
       (.I0(\s_axis_tx_tdata[21]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(\m_axis_cc\.tdata [26]),
        .I5(compl_rid[5]),
        .O(s_axis_tx_tgt_tdata[21]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[21]_i_4 
       (.I0(\m_axis_cc\.tdata [13]),
        .I1(\tx_64.compl_data_reg_n_0_[45] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[21]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[22]_i_2 
       (.I0(\s_axis_tx_tdata[22]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(\m_axis_cc\.tdata [27]),
        .I5(compl_rid[6]),
        .O(s_axis_tx_tgt_tdata[22]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[22]_i_4 
       (.I0(\m_axis_cc\.tdata [14]),
        .I1(\tx_64.compl_data_reg_n_0_[46] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[22]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[23]_i_3 
       (.I0(\s_axis_tx_tdata[31]_i_7_n_0 ),
        .I1(compl_rid[7]),
        .I2(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I3(\tx_64.compl_data_reg_n_0_[47] ),
        .I4(\m_axis_cc\.tdata [15]),
        .I5(\s_axis_tx_tdata[31]_i_9_n_0 ),
        .O(s_axis_tx_tgt_tdata[23]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[24]_i_3 
       (.I0(\s_axis_tx_tdata[31]_i_7_n_0 ),
        .I1(compl_rid[8]),
        .I2(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I3(\tx_64.compl_data_reg_n_0_[32] ),
        .I4(\m_axis_cc\.tdata [0]),
        .I5(\s_axis_tx_tdata[31]_i_9_n_0 ),
        .O(s_axis_tx_tgt_tdata[24]));
  LUT6 #(
    .INIT(64'hAABABABAAABAAABA)) 
    \s_axis_tx_tdata[25]_i_3 
       (.I0(\s_axis_tx_tdata[25]_i_4_n_0 ),
        .I1(user_reset_out),
        .I2(state),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(p_0_in),
        .I5(\tx_64.compl_data_reg_n_0_[33] ),
        .O(s_axis_tx_tgt_tdata[25]));
  LUT6 #(
    .INIT(64'h0088008800F00000)) 
    \s_axis_tx_tdata[25]_i_4 
       (.I0(p_0_in),
        .I1(\m_axis_cc\.tdata [1]),
        .I2(compl_rid[9]),
        .I3(user_reset_out),
        .I4(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I5(state),
        .O(\s_axis_tx_tdata[25]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[26]_i_3 
       (.I0(\s_axis_tx_tdata[31]_i_7_n_0 ),
        .I1(compl_rid[10]),
        .I2(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I3(\tx_64.compl_data_reg_n_0_[34] ),
        .I4(\m_axis_cc\.tdata [2]),
        .I5(\s_axis_tx_tdata[31]_i_9_n_0 ),
        .O(s_axis_tx_tgt_tdata[26]));
  LUT6 #(
    .INIT(64'hAABABABAAABAAABA)) 
    \s_axis_tx_tdata[27]_i_3 
       (.I0(\s_axis_tx_tdata[27]_i_4_n_0 ),
        .I1(user_reset_out),
        .I2(state),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(p_0_in),
        .I5(\tx_64.compl_data_reg_n_0_[35] ),
        .O(s_axis_tx_tgt_tdata[27]));
  LUT6 #(
    .INIT(64'h0088008800F00000)) 
    \s_axis_tx_tdata[27]_i_4 
       (.I0(p_0_in),
        .I1(\m_axis_cc\.tdata [3]),
        .I2(compl_rid[11]),
        .I3(user_reset_out),
        .I4(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I5(state),
        .O(\s_axis_tx_tdata[27]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[28]_i_3 
       (.I0(\s_axis_tx_tdata[31]_i_7_n_0 ),
        .I1(compl_rid[12]),
        .I2(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I3(\tx_64.compl_data_reg_n_0_[36] ),
        .I4(\m_axis_cc\.tdata [4]),
        .I5(\s_axis_tx_tdata[31]_i_9_n_0 ),
        .O(s_axis_tx_tgt_tdata[28]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[29]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_7_n_0 ),
        .I1(compl_rid[13]),
        .I2(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I3(\tx_64.compl_data_reg_n_0_[37] ),
        .I4(\m_axis_cc\.tdata [5]),
        .I5(\s_axis_tx_tdata[31]_i_9_n_0 ),
        .O(s_axis_tx_tgt_tdata[29]));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[2]_i_2 
       (.I0(\s_axis_tx_tdata[2]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[2]),
        .I5(p_0_in),
        .O(s_axis_tx_tgt_tdata[2]));
  LUT6 #(
    .INIT(64'h0000AC000000A000)) 
    \s_axis_tx_tdata[2]_i_4 
       (.I0(\m_axis_cc\.tdata [26]),
        .I1(\tx_64.compl_data_reg_n_0_[58] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8888888)) 
    \s_axis_tx_tdata[30]_i_2 
       (.I0(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I1(\tx_64.compl_data_reg_n_0_[38] ),
        .I2(state),
        .I3(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .I4(\m_axis_cc\.tdata [6]),
        .I5(\s_axis_tx_tdata[30]_i_4_n_0 ),
        .O(s_axis_tx_tgt_tdata[30]));
  LUT6 #(
    .INIT(64'h8888888F88888888)) 
    \s_axis_tx_tdata[30]_i_4 
       (.I0(compl_rid[14]),
        .I1(\s_axis_tx_tdata[31]_i_7_n_0 ),
        .I2(p_6_out[47]),
        .I3(p_6_out[45]),
        .I4(p_6_out[46]),
        .I5(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .O(\s_axis_tx_tdata[30]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[31]_i_4 
       (.I0(\s_axis_tx_tdata[31]_i_7_n_0 ),
        .I1(compl_rid[15]),
        .I2(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I3(\tx_64.compl_data_reg_n_0_[39] ),
        .I4(\m_axis_cc\.tdata [7]),
        .I5(\s_axis_tx_tdata[31]_i_9_n_0 ),
        .O(s_axis_tx_tgt_tdata[31]));
  (* SOFT_HLUTNM = "soft_lutpair1996" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \s_axis_tx_tdata[31]_i_7 
       (.I0(user_reset_out),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .O(\s_axis_tx_tdata[31]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2000" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    \s_axis_tx_tdata[31]_i_8 
       (.I0(p_0_in),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(state),
        .O(\s_axis_tx_tdata[31]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1997" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    \s_axis_tx_tdata[31]_i_9 
       (.I0(p_0_in),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(state),
        .O(\s_axis_tx_tdata[31]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[32]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[32]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [24]),
        .I4(\m_axis_cc\.tdata [56]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[32]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[33]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[33]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [25]),
        .I4(\m_axis_cc\.tdata [57]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[33]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[34]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[34]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [26]),
        .I4(\m_axis_cc\.tdata [58]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[34]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[35]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[35]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [27]),
        .I4(\m_axis_cc\.tdata [59]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[35]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[36]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[36]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [28]),
        .I4(\m_axis_cc\.tdata [60]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[36]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[37]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[37]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [29]),
        .I4(\m_axis_cc\.tdata [61]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[37]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[38]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[38]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [30]),
        .I4(\m_axis_cc\.tdata [62]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[38]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[39]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[39]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [31]),
        .I4(\m_axis_cc\.tdata [63]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[39]));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[3]_i_2 
       (.I0(\s_axis_tx_tdata[3]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[3]),
        .I5(\tx_64.compl_addr_reg_n_0_[3] ),
        .O(s_axis_tx_tgt_tdata[3]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[3]_i_4 
       (.I0(\m_axis_cc\.tdata [27]),
        .I1(\tx_64.compl_data_reg_n_0_[59] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[40]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[40]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [16]),
        .I4(\m_axis_cc\.tdata [48]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[40]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[41]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[41]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [17]),
        .I4(\m_axis_cc\.tdata [49]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[41]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[42]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[42]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [18]),
        .I4(\m_axis_cc\.tdata [50]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[42]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[43]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[43]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [19]),
        .I4(\m_axis_cc\.tdata [51]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[43]));
  (* SOFT_HLUTNM = "soft_lutpair1999" *) 
  LUT5 #(
    .INIT(32'h0A000C00)) 
    \s_axis_tx_tdata[44]_i_3 
       (.I0(\m_axis_cc\.tdata [52]),
        .I1(\m_axis_cc\.tdata [20]),
        .I2(user_reset_out),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(p_0_in),
        .O(s_axis_tx_tgt_tdata[44]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[45]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[45]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [21]),
        .I4(\m_axis_cc\.tdata [53]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[45]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[46]_i_3 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[46]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [22]),
        .I4(\m_axis_cc\.tdata [54]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[46]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[47]_i_4 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[47]),
        .I2(\s_axis_tx_tdata[47]_i_8_n_0 ),
        .I3(\m_axis_cc\.tdata [23]),
        .I4(\m_axis_cc\.tdata [55]),
        .I5(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .O(s_axis_tx_tgt_tdata[47]));
  (* SOFT_HLUTNM = "soft_lutpair1998" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \s_axis_tx_tdata[47]_i_7 
       (.I0(user_reset_out),
        .I1(state),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(\s_axis_tx_tdata[47]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2000" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \s_axis_tx_tdata[47]_i_8 
       (.I0(user_reset_out),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(p_0_in),
        .O(\s_axis_tx_tdata[47]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[48]_i_2 
       (.I0(\s_axis_tx_tdata[55]_i_4_n_0 ),
        .I1(cfg_function_number_o[0]),
        .I2(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .I3(\m_axis_cc\.tdata [40]),
        .I4(\m_axis_cc\.tdata [8]),
        .I5(\s_axis_tx_tdata[55]_i_6_n_0 ),
        .O(s_axis_tx_tgt_tdata[48]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[49]_i_2 
       (.I0(\s_axis_tx_tdata[55]_i_4_n_0 ),
        .I1(cfg_function_number_o[1]),
        .I2(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .I3(\m_axis_cc\.tdata [41]),
        .I4(\m_axis_cc\.tdata [9]),
        .I5(\s_axis_tx_tdata[55]_i_6_n_0 ),
        .O(s_axis_tx_tgt_tdata[49]));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[4]_i_2 
       (.I0(\s_axis_tx_tdata[4]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[4]),
        .I5(\tx_64.compl_addr_reg_n_0_[4] ),
        .O(s_axis_tx_tgt_tdata[4]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[4]_i_4 
       (.I0(\m_axis_cc\.tdata [28]),
        .I1(\tx_64.compl_data_reg_n_0_[60] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[50]_i_2 
       (.I0(\s_axis_tx_tdata[55]_i_4_n_0 ),
        .I1(cfg_function_number_o[2]),
        .I2(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .I3(\m_axis_cc\.tdata [42]),
        .I4(\m_axis_cc\.tdata [10]),
        .I5(\s_axis_tx_tdata[55]_i_6_n_0 ),
        .O(s_axis_tx_tgt_tdata[50]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[51]_i_2 
       (.I0(\s_axis_tx_tdata[55]_i_4_n_0 ),
        .I1(cfg_device_number_o[0]),
        .I2(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .I3(\m_axis_cc\.tdata [43]),
        .I4(\m_axis_cc\.tdata [11]),
        .I5(\s_axis_tx_tdata[55]_i_6_n_0 ),
        .O(s_axis_tx_tgt_tdata[51]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[52]_i_2 
       (.I0(\s_axis_tx_tdata[55]_i_4_n_0 ),
        .I1(cfg_device_number_o[1]),
        .I2(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .I3(\m_axis_cc\.tdata [44]),
        .I4(\m_axis_cc\.tdata [12]),
        .I5(\s_axis_tx_tdata[55]_i_6_n_0 ),
        .O(s_axis_tx_tgt_tdata[52]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[53]_i_2 
       (.I0(\s_axis_tx_tdata[55]_i_4_n_0 ),
        .I1(cfg_device_number_o[2]),
        .I2(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .I3(\m_axis_cc\.tdata [45]),
        .I4(\m_axis_cc\.tdata [13]),
        .I5(\s_axis_tx_tdata[55]_i_6_n_0 ),
        .O(s_axis_tx_tgt_tdata[53]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[54]_i_2 
       (.I0(\s_axis_tx_tdata[55]_i_4_n_0 ),
        .I1(cfg_device_number_o[3]),
        .I2(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .I3(\m_axis_cc\.tdata [46]),
        .I4(\m_axis_cc\.tdata [14]),
        .I5(\s_axis_tx_tdata[55]_i_6_n_0 ),
        .O(s_axis_tx_tgt_tdata[54]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[55]_i_2 
       (.I0(\s_axis_tx_tdata[55]_i_4_n_0 ),
        .I1(cfg_device_number_o[4]),
        .I2(\s_axis_tx_tdata[55]_i_5_n_0 ),
        .I3(\m_axis_cc\.tdata [47]),
        .I4(\m_axis_cc\.tdata [15]),
        .I5(\s_axis_tx_tdata[55]_i_6_n_0 ),
        .O(s_axis_tx_tgt_tdata[55]));
  (* SOFT_HLUTNM = "soft_lutpair2001" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \s_axis_tx_tdata[55]_i_4 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(state),
        .I2(user_reset_out),
        .I3(\m_axis_cc\.tdata [24]),
        .O(\s_axis_tx_tdata[55]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1999" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \s_axis_tx_tdata[55]_i_5 
       (.I0(user_reset_out),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(p_0_in),
        .O(\s_axis_tx_tdata[55]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1997" *) 
  LUT5 #(
    .INIT(32'h00000F88)) 
    \s_axis_tx_tdata[55]_i_6 
       (.I0(\m_axis_cc\.tdata [24]),
        .I1(state),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .O(\s_axis_tx_tdata[55]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0C080400)) 
    \s_axis_tx_tdata[56]_i_2 
       (.I0(p_0_in),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(\m_axis_cc\.tdata [0]),
        .I4(\m_axis_cc\.tdata [32]),
        .I5(\s_axis_tx_tdata[56]_i_4_n_0 ),
        .O(s_axis_tx_tgt_tdata[56]));
  LUT6 #(
    .INIT(64'h00000A0000000C00)) 
    \s_axis_tx_tdata[56]_i_4 
       (.I0(\m_axis_cc\.tdata [16]),
        .I1(cfg_bus_number_o[0]),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(\m_axis_cc\.tdata [24]),
        .O(\s_axis_tx_tdata[56]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0C080400)) 
    \s_axis_tx_tdata[57]_i_2 
       (.I0(p_0_in),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(\m_axis_cc\.tdata [1]),
        .I4(\m_axis_cc\.tdata [33]),
        .I5(\s_axis_tx_tdata[57]_i_4_n_0 ),
        .O(s_axis_tx_tgt_tdata[57]));
  LUT6 #(
    .INIT(64'h00000A0000000C00)) 
    \s_axis_tx_tdata[57]_i_4 
       (.I0(\m_axis_cc\.tdata [17]),
        .I1(cfg_bus_number_o[1]),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(\m_axis_cc\.tdata [24]),
        .O(\s_axis_tx_tdata[57]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0C080400)) 
    \s_axis_tx_tdata[58]_i_2 
       (.I0(p_0_in),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(\m_axis_cc\.tdata [2]),
        .I4(\m_axis_cc\.tdata [34]),
        .I5(\s_axis_tx_tdata[58]_i_4_n_0 ),
        .O(s_axis_tx_tgt_tdata[58]));
  LUT6 #(
    .INIT(64'h00000A0000000C00)) 
    \s_axis_tx_tdata[58]_i_4 
       (.I0(\m_axis_cc\.tdata [18]),
        .I1(cfg_bus_number_o[2]),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(\m_axis_cc\.tdata [24]),
        .O(\s_axis_tx_tdata[58]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0C080400)) 
    \s_axis_tx_tdata[59]_i_2 
       (.I0(p_0_in),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(\m_axis_cc\.tdata [3]),
        .I4(\m_axis_cc\.tdata [35]),
        .I5(\s_axis_tx_tdata[59]_i_4_n_0 ),
        .O(s_axis_tx_tgt_tdata[59]));
  LUT6 #(
    .INIT(64'h00000A0000000C00)) 
    \s_axis_tx_tdata[59]_i_4 
       (.I0(\m_axis_cc\.tdata [19]),
        .I1(cfg_bus_number_o[3]),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(\m_axis_cc\.tdata [24]),
        .O(\s_axis_tx_tdata[59]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[5]_i_2 
       (.I0(\s_axis_tx_tdata[5]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[5]),
        .I5(\tx_64.compl_addr_reg_n_0_[5] ),
        .O(s_axis_tx_tgt_tdata[5]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[5]_i_4 
       (.I0(\m_axis_cc\.tdata [29]),
        .I1(\tx_64.compl_data_reg_n_0_[61] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0C080400)) 
    \s_axis_tx_tdata[60]_i_2 
       (.I0(p_0_in),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(\m_axis_cc\.tdata [4]),
        .I4(\m_axis_cc\.tdata [36]),
        .I5(\s_axis_tx_tdata[60]_i_4_n_0 ),
        .O(s_axis_tx_tgt_tdata[60]));
  LUT6 #(
    .INIT(64'h00000A0000000C00)) 
    \s_axis_tx_tdata[60]_i_4 
       (.I0(\m_axis_cc\.tdata [20]),
        .I1(cfg_bus_number_o[4]),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(\m_axis_cc\.tdata [24]),
        .O(\s_axis_tx_tdata[60]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0C080400)) 
    \s_axis_tx_tdata[61]_i_2 
       (.I0(p_0_in),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(\m_axis_cc\.tdata [5]),
        .I4(\m_axis_cc\.tdata [37]),
        .I5(\s_axis_tx_tdata[61]_i_4_n_0 ),
        .O(s_axis_tx_tgt_tdata[61]));
  LUT6 #(
    .INIT(64'h00000A0000000C00)) 
    \s_axis_tx_tdata[61]_i_4 
       (.I0(\m_axis_cc\.tdata [21]),
        .I1(cfg_bus_number_o[5]),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(\m_axis_cc\.tdata [24]),
        .O(\s_axis_tx_tdata[61]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0C080400)) 
    \s_axis_tx_tdata[62]_i_2 
       (.I0(p_0_in),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(\m_axis_cc\.tdata [6]),
        .I4(\m_axis_cc\.tdata [38]),
        .I5(\s_axis_tx_tdata[62]_i_4_n_0 ),
        .O(s_axis_tx_tgt_tdata[62]));
  LUT6 #(
    .INIT(64'h00000A0000000C00)) 
    \s_axis_tx_tdata[62]_i_4 
       (.I0(\m_axis_cc\.tdata [22]),
        .I1(cfg_bus_number_o[6]),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(\m_axis_cc\.tdata [24]),
        .O(\s_axis_tx_tdata[62]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0C080400)) 
    \s_axis_tx_tdata[63]_i_4 
       (.I0(p_0_in),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(\m_axis_cc\.tdata [7]),
        .I4(\m_axis_cc\.tdata [39]),
        .I5(\s_axis_tx_tdata[63]_i_6_n_0 ),
        .O(s_axis_tx_tgt_tdata[63]));
  LUT6 #(
    .INIT(64'h00000A0000000C00)) 
    \s_axis_tx_tdata[63]_i_6 
       (.I0(\m_axis_cc\.tdata [23]),
        .I1(cfg_bus_number_o[7]),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(\m_axis_cc\.tdata [24]),
        .O(\s_axis_tx_tdata[63]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[6]_i_2 
       (.I0(\s_axis_tx_tdata[6]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[6]),
        .I5(\tx_64.compl_addr_reg_n_0_[6] ),
        .O(s_axis_tx_tgt_tdata[6]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[6]_i_4 
       (.I0(\m_axis_cc\.tdata [30]),
        .I1(\tx_64.compl_data_reg_n_0_[62] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \s_axis_tx_tdata[7]_i_2 
       (.I0(\s_axis_tx_tdata[47]_i_7_n_0 ),
        .I1(p_6_out[7]),
        .I2(\s_axis_tx_tdata[31]_i_8_n_0 ),
        .I3(\tx_64.compl_data_reg_n_0_[63] ),
        .I4(\m_axis_cc\.tdata [31]),
        .I5(\s_axis_tx_tdata[31]_i_9_n_0 ),
        .O(s_axis_tx_tgt_tdata[7]));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[8]_i_2 
       (.I0(\s_axis_tx_tdata[8]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[8]),
        .I5(\tx_64.compl_tag_reg_n_0_[0] ),
        .O(s_axis_tx_tgt_tdata[8]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[8]_i_4 
       (.I0(\m_axis_cc\.tdata [16]),
        .I1(\tx_64.compl_data_reg_n_0_[48] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[8]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAABEAAAEAABAAAAA)) 
    \s_axis_tx_tdata[9]_i_2 
       (.I0(\s_axis_tx_tdata[9]_i_4_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(p_6_out[9]),
        .I5(\tx_64.compl_tag_reg_n_0_[1] ),
        .O(s_axis_tx_tgt_tdata[9]));
  LUT6 #(
    .INIT(64'h0000AC0000000000)) 
    \s_axis_tx_tdata[9]_i_4 
       (.I0(\m_axis_cc\.tdata [17]),
        .I1(\tx_64.compl_data_reg_n_0_[49] ),
        .I2(p_0_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(\s_axis_tx_tdata[9]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000FFFF00000100)) 
    \s_axis_tx_tkeep[7]_i_6 
       (.I0(p_6_out[47]),
        .I1(p_6_out[45]),
        .I2(p_6_out[46]),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .I5(state),
        .O(s_axis_tx_tgt_tkeep));
  FDRE \tx_64.compl_addr_reg[0] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [0]),
        .Q(\tx_64.compl_addr_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_addr_reg[1] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [1]),
        .Q(\tx_64.compl_addr_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_addr_reg[2] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [2]),
        .Q(p_0_in),
        .R(user_reset_out));
  FDRE \tx_64.compl_addr_reg[3] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [3]),
        .Q(\tx_64.compl_addr_reg_n_0_[3] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_addr_reg[4] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [4]),
        .Q(\tx_64.compl_addr_reg_n_0_[4] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_addr_reg[5] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [5]),
        .Q(\tx_64.compl_addr_reg_n_0_[5] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_addr_reg[6] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [6]),
        .Q(\tx_64.compl_addr_reg_n_0_[6] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_at_reg[0] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [8]),
        .Q(p_6_out[10]),
        .R(user_reset_out));
  FDRE \tx_64.compl_at_reg[1] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [9]),
        .Q(p_6_out[11]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[0] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [16]),
        .Q(p_6_out[32]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[10] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [26]),
        .Q(p_6_out[42]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[11] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [27]),
        .Q(p_6_out[43]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[1] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [17]),
        .Q(p_6_out[33]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[2] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [18]),
        .Q(p_6_out[34]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[3] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [19]),
        .Q(p_6_out[35]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[4] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [20]),
        .Q(p_6_out[36]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[5] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [21]),
        .Q(p_6_out[37]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[6] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [22]),
        .Q(p_6_out[38]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[7] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [23]),
        .Q(p_6_out[39]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[8] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [24]),
        .Q(p_6_out[40]),
        .R(user_reset_out));
  FDRE \tx_64.compl_byte_reg[9] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [25]),
        .Q(p_6_out[41]),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2002" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[32]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [32]),
        .O(compl_data[32]));
  (* SOFT_HLUTNM = "soft_lutpair2002" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[33]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [33]),
        .O(compl_data[33]));
  (* SOFT_HLUTNM = "soft_lutpair2003" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[34]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [34]),
        .O(compl_data[34]));
  (* SOFT_HLUTNM = "soft_lutpair2003" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[35]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [35]),
        .O(compl_data[35]));
  (* SOFT_HLUTNM = "soft_lutpair2004" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[36]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [36]),
        .O(compl_data[36]));
  (* SOFT_HLUTNM = "soft_lutpair2004" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[37]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [37]),
        .O(compl_data[37]));
  (* SOFT_HLUTNM = "soft_lutpair2005" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[38]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [38]),
        .O(compl_data[38]));
  (* SOFT_HLUTNM = "soft_lutpair2005" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[39]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [39]),
        .O(compl_data[39]));
  (* SOFT_HLUTNM = "soft_lutpair2006" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[40]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [40]),
        .O(compl_data[40]));
  (* SOFT_HLUTNM = "soft_lutpair2006" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[41]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [41]),
        .O(compl_data[41]));
  (* SOFT_HLUTNM = "soft_lutpair2007" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[42]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [42]),
        .O(compl_data[42]));
  (* SOFT_HLUTNM = "soft_lutpair2007" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[43]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [43]),
        .O(compl_data[43]));
  (* SOFT_HLUTNM = "soft_lutpair2008" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[44]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [44]),
        .O(compl_data[44]));
  (* SOFT_HLUTNM = "soft_lutpair2008" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[45]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [45]),
        .O(compl_data[45]));
  (* SOFT_HLUTNM = "soft_lutpair2009" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[46]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [46]),
        .O(compl_data[46]));
  (* SOFT_HLUTNM = "soft_lutpair2009" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[47]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [47]),
        .O(compl_data[47]));
  (* SOFT_HLUTNM = "soft_lutpair2010" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[48]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [48]),
        .O(compl_data[48]));
  (* SOFT_HLUTNM = "soft_lutpair2010" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[49]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [49]),
        .O(compl_data[49]));
  (* SOFT_HLUTNM = "soft_lutpair2011" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[50]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [50]),
        .O(compl_data[50]));
  (* SOFT_HLUTNM = "soft_lutpair2011" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[51]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [51]),
        .O(compl_data[51]));
  (* SOFT_HLUTNM = "soft_lutpair2012" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[52]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [52]),
        .O(compl_data[52]));
  (* SOFT_HLUTNM = "soft_lutpair2012" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[53]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [53]),
        .O(compl_data[53]));
  (* SOFT_HLUTNM = "soft_lutpair2013" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[54]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [54]),
        .O(compl_data[54]));
  (* SOFT_HLUTNM = "soft_lutpair2013" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[55]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [55]),
        .O(compl_data[55]));
  (* SOFT_HLUTNM = "soft_lutpair2014" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[56]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [56]),
        .O(compl_data[56]));
  (* SOFT_HLUTNM = "soft_lutpair2014" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[57]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [57]),
        .O(compl_data[57]));
  (* SOFT_HLUTNM = "soft_lutpair2015" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[58]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [58]),
        .O(compl_data[58]));
  (* SOFT_HLUTNM = "soft_lutpair2015" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[59]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [59]),
        .O(compl_data[59]));
  (* SOFT_HLUTNM = "soft_lutpair2016" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[60]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [60]),
        .O(compl_data[60]));
  (* SOFT_HLUTNM = "soft_lutpair2016" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[61]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [61]),
        .O(compl_data[61]));
  (* SOFT_HLUTNM = "soft_lutpair2017" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[62]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [62]),
        .O(compl_data[62]));
  (* SOFT_HLUTNM = "soft_lutpair2017" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \tx_64.compl_data[63]_i_1 
       (.I0(p_0_in),
        .I1(state),
        .I2(\m_axis_cc\.tdata [63]),
        .O(compl_data[63]));
  FDRE \tx_64.compl_data_reg[32] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[32]),
        .Q(\tx_64.compl_data_reg_n_0_[32] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[33] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[33]),
        .Q(\tx_64.compl_data_reg_n_0_[33] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[34] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[34]),
        .Q(\tx_64.compl_data_reg_n_0_[34] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[35] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[35]),
        .Q(\tx_64.compl_data_reg_n_0_[35] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[36] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[36]),
        .Q(\tx_64.compl_data_reg_n_0_[36] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[37] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[37]),
        .Q(\tx_64.compl_data_reg_n_0_[37] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[38] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[38]),
        .Q(\tx_64.compl_data_reg_n_0_[38] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[39] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[39]),
        .Q(\tx_64.compl_data_reg_n_0_[39] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[40] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[40]),
        .Q(\tx_64.compl_data_reg_n_0_[40] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[41] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[41]),
        .Q(\tx_64.compl_data_reg_n_0_[41] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[42] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[42]),
        .Q(\tx_64.compl_data_reg_n_0_[42] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[43] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[43]),
        .Q(\tx_64.compl_data_reg_n_0_[43] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[44] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[44]),
        .Q(\tx_64.compl_data_reg_n_0_[44] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[45] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[45]),
        .Q(\tx_64.compl_data_reg_n_0_[45] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[46] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[46]),
        .Q(\tx_64.compl_data_reg_n_0_[46] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[47] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[47]),
        .Q(\tx_64.compl_data_reg_n_0_[47] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[48] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[48]),
        .Q(\tx_64.compl_data_reg_n_0_[48] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[49] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[49]),
        .Q(\tx_64.compl_data_reg_n_0_[49] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[50] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[50]),
        .Q(\tx_64.compl_data_reg_n_0_[50] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[51] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[51]),
        .Q(\tx_64.compl_data_reg_n_0_[51] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[52] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[52]),
        .Q(\tx_64.compl_data_reg_n_0_[52] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[53] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[53]),
        .Q(\tx_64.compl_data_reg_n_0_[53] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[54] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[54]),
        .Q(\tx_64.compl_data_reg_n_0_[54] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[55] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[55]),
        .Q(\tx_64.compl_data_reg_n_0_[55] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[56] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[56]),
        .Q(\tx_64.compl_data_reg_n_0_[56] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[57] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[57]),
        .Q(\tx_64.compl_data_reg_n_0_[57] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[58] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[58]),
        .Q(\tx_64.compl_data_reg_n_0_[58] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[59] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[59]),
        .Q(\tx_64.compl_data_reg_n_0_[59] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[60] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[60]),
        .Q(\tx_64.compl_data_reg_n_0_[60] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[61] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[61]),
        .Q(\tx_64.compl_data_reg_n_0_[61] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[62] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[62]),
        .Q(\tx_64.compl_data_reg_n_0_[62] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_data_reg[63] 
       (.C(user_clk_out),
        .CE(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .D(compl_data[63]),
        .Q(\tx_64.compl_data_reg_n_0_[63] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_ep_reg 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [46]),
        .Q(p_6_out[14]),
        .R(user_reset_out));
  FDRE \tx_64.compl_len_reg[0] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [32]),
        .Q(p_6_out[0]),
        .R(user_reset_out));
  FDRE \tx_64.compl_len_reg[1] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [33]),
        .Q(p_6_out[1]),
        .R(user_reset_out));
  FDRE \tx_64.compl_len_reg[2] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [34]),
        .Q(p_6_out[2]),
        .R(user_reset_out));
  FDRE \tx_64.compl_len_reg[3] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [35]),
        .Q(p_6_out[3]),
        .R(user_reset_out));
  FDRE \tx_64.compl_len_reg[4] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [36]),
        .Q(p_6_out[4]),
        .R(user_reset_out));
  FDRE \tx_64.compl_len_reg[5] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [37]),
        .Q(p_6_out[5]),
        .R(user_reset_out));
  FDRE \tx_64.compl_len_reg[6] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [38]),
        .Q(p_6_out[6]),
        .R(user_reset_out));
  FDRE \tx_64.compl_len_reg[7] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [39]),
        .Q(p_6_out[7]),
        .R(user_reset_out));
  FDRE \tx_64.compl_len_reg[8] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [40]),
        .Q(p_6_out[8]),
        .R(user_reset_out));
  FDRE \tx_64.compl_len_reg[9] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [41]),
        .Q(p_6_out[9]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[0] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [48]),
        .Q(compl_rid[0]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[10] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [58]),
        .Q(compl_rid[10]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[11] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [59]),
        .Q(compl_rid[11]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[12] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [60]),
        .Q(compl_rid[12]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[13] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [61]),
        .Q(compl_rid[13]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[14] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [62]),
        .Q(compl_rid[14]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[15] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [63]),
        .Q(compl_rid[15]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[1] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [49]),
        .Q(compl_rid[1]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[2] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [50]),
        .Q(compl_rid[2]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[3] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [51]),
        .Q(compl_rid[3]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[4] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [52]),
        .Q(compl_rid[4]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[5] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [53]),
        .Q(compl_rid[5]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[6] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [54]),
        .Q(compl_rid[6]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[7] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [55]),
        .Q(compl_rid[7]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[8] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [56]),
        .Q(compl_rid[8]),
        .R(user_reset_out));
  FDRE \tx_64.compl_rid_reg[9] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [57]),
        .Q(compl_rid[9]),
        .R(user_reset_out));
  LUT4 #(
    .INIT(16'h0004)) 
    \tx_64.compl_status[2]_i_1 
       (.I0(in_packet_q),
        .I1(\m_axis_cc\.tvalid ),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .O(compl_addr));
  FDRE \tx_64.compl_status_reg[0] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [43]),
        .Q(p_6_out[45]),
        .R(user_reset_out));
  FDRE \tx_64.compl_status_reg[1] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [44]),
        .Q(p_6_out[46]),
        .R(user_reset_out));
  FDRE \tx_64.compl_status_reg[2] 
       (.C(user_clk_out),
        .CE(compl_addr),
        .D(\m_axis_cc\.tdata [45]),
        .Q(p_6_out[47]),
        .R(user_reset_out));
  LUT2 #(
    .INIT(4'h2)) 
    \tx_64.compl_tag[7]_i_1 
       (.I0(state),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(compl_tag));
  FDRE \tx_64.compl_tag_reg[0] 
       (.C(user_clk_out),
        .CE(compl_tag),
        .D(\m_axis_cc\.tdata [0]),
        .Q(\tx_64.compl_tag_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_tag_reg[1] 
       (.C(user_clk_out),
        .CE(compl_tag),
        .D(\m_axis_cc\.tdata [1]),
        .Q(\tx_64.compl_tag_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_tag_reg[2] 
       (.C(user_clk_out),
        .CE(compl_tag),
        .D(\m_axis_cc\.tdata [2]),
        .Q(\tx_64.compl_tag_reg_n_0_[2] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_tag_reg[3] 
       (.C(user_clk_out),
        .CE(compl_tag),
        .D(\m_axis_cc\.tdata [3]),
        .Q(\tx_64.compl_tag_reg_n_0_[3] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_tag_reg[4] 
       (.C(user_clk_out),
        .CE(compl_tag),
        .D(\m_axis_cc\.tdata [4]),
        .Q(\tx_64.compl_tag_reg_n_0_[4] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_tag_reg[5] 
       (.C(user_clk_out),
        .CE(compl_tag),
        .D(\m_axis_cc\.tdata [5]),
        .Q(\tx_64.compl_tag_reg_n_0_[5] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_tag_reg[6] 
       (.C(user_clk_out),
        .CE(compl_tag),
        .D(\m_axis_cc\.tdata [6]),
        .Q(\tx_64.compl_tag_reg_n_0_[6] ),
        .R(user_reset_out));
  FDRE \tx_64.compl_tag_reg[7] 
       (.C(user_clk_out),
        .CE(compl_tag),
        .D(\m_axis_cc\.tdata [7]),
        .Q(\tx_64.compl_tag_reg_n_0_[7] ),
        .R(user_reset_out));
  LUT3 #(
    .INIT(8'hFE)) 
    udma_wrapper_i_154
       (.I0(p_6_out[47]),
        .I1(p_6_out[45]),
        .I2(p_6_out[46]),
        .O(udma_wrapper_i_154_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1996" *) 
  LUT5 #(
    .INIT(32'hEFFFCDCD)) 
    udma_wrapper_i_2
       (.I0(state),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(udma_wrapper_i_154_n_0),
        .I4(s_axis_tx_tgt_tready),
        .O(\m_axis_cc\.tready ));
endmodule

module xdma_0_tgt_req
   (req_mesg,
    in_packet_q,
    \FSM_sequential_tx_64.state_reg[1]_0 ,
    in_packet_q_reg_0,
    m_axis_tready,
    \s_axis_cq\.tdata ,
    \s_axis_cq\.tuser ,
    \s_axis_cq\.tvalid ,
    \s_axis_cq\.tlast ,
    user_reset_out,
    user_clk_out,
    req_OBFF,
    req_LTR,
    req_ATS,
    req_VDM,
    \tx_64.req_tag_reg[0]_0 ,
    \tx_64.req_rid_reg[15]_0 ,
    \s_axis_cq\.tready ,
    \tx_64.req_VDM_reg_0 ,
    m_axis_tlast,
    D,
    \tx_64.req_msg_code_reg[7]_0 ,
    \tx_64.req_bar_id_reg[2]_0 );
  output req_mesg;
  output in_packet_q;
  output [0:0]\FSM_sequential_tx_64.state_reg[1]_0 ;
  output in_packet_q_reg_0;
  output m_axis_tready;
  output [63:0]\s_axis_cq\.tdata ;
  output [4:0]\s_axis_cq\.tuser ;
  output \s_axis_cq\.tvalid ;
  output \s_axis_cq\.tlast ;
  input user_reset_out;
  input user_clk_out;
  input req_OBFF;
  input req_LTR;
  input req_ATS;
  input req_VDM;
  input \tx_64.req_tag_reg[0]_0 ;
  input [63:0]\tx_64.req_rid_reg[15]_0 ;
  input [0:0]\s_axis_cq\.tready ;
  input \tx_64.req_VDM_reg_0 ;
  input m_axis_tlast;
  input [3:0]D;
  input [7:0]\tx_64.req_msg_code_reg[7]_0 ;
  input [2:0]\tx_64.req_bar_id_reg[2]_0 ;

  wire [3:0]D;
  wire \FSM_sequential_tx_64.state[1]_i_2__0_n_0 ;
  wire [0:0]\FSM_sequential_tx_64.state_reg[1]_0 ;
  wire in130;
  wire in_packet_q;
  wire in_packet_q_i_1__1_n_0;
  wire in_packet_q_i_2_n_0;
  wire in_packet_q_i_3_n_0;
  wire in_packet_q_i_4_n_0;
  wire in_packet_q_reg_0;
  wire m_axis_tlast;
  wire m_axis_tready;
  wire p_0_in;
  wire p_0_in22_in;
  wire req_4dw;
  wire req_ATS;
  wire req_LTR;
  wire req_OBFF;
  wire req_VDM;
  wire [1:0]req_at;
  wire [2:0]req_attr;
  wire [31:0]req_data;
  wire [1:1]req_fmt;
  wire [9:0]req_len;
  wire req_mesg;
  wire [15:0]req_rid;
  wire [7:0]req_tag;
  wire [2:0]req_tc;
  wire [2:0]req_type;
  wire req_wr;
  wire [63:0]\s_axis_cq\.tdata ;
  wire \s_axis_cq\.tlast ;
  wire [0:0]\s_axis_cq\.tready ;
  wire [4:0]\s_axis_cq\.tuser ;
  wire \s_axis_cq\.tvalid ;
  wire [3:0]sel0;
  wire [0:0]state;
  wire [1:0]state__0;
  wire tgt_brdg_fifo_inst_i_2_n_0;
  wire \tx_64.req_4dw_i_1__0_n_0 ;
  wire \tx_64.req_VDM_reg_0 ;
  wire \tx_64.req_addr[2]_i_1_n_0 ;
  wire \tx_64.req_addr[2]_i_2_n_0 ;
  wire \tx_64.req_at_reg_n_0_[0] ;
  wire \tx_64.req_at_reg_n_0_[1] ;
  wire \tx_64.req_attr_reg_n_0_[0] ;
  wire \tx_64.req_attr_reg_n_0_[1] ;
  wire \tx_64.req_attr_reg_n_0_[2] ;
  wire [2:0]\tx_64.req_bar_id_reg[2]_0 ;
  wire \tx_64.req_bar_id_reg_n_0_[0] ;
  wire \tx_64.req_bar_id_reg_n_0_[1] ;
  wire \tx_64.req_bar_id_reg_n_0_[2] ;
  wire \tx_64.req_data[31]_i_1_n_0 ;
  wire \tx_64.req_data_reg_n_0_[0] ;
  wire \tx_64.req_data_reg_n_0_[10] ;
  wire \tx_64.req_data_reg_n_0_[11] ;
  wire \tx_64.req_data_reg_n_0_[12] ;
  wire \tx_64.req_data_reg_n_0_[13] ;
  wire \tx_64.req_data_reg_n_0_[14] ;
  wire \tx_64.req_data_reg_n_0_[15] ;
  wire \tx_64.req_data_reg_n_0_[16] ;
  wire \tx_64.req_data_reg_n_0_[17] ;
  wire \tx_64.req_data_reg_n_0_[18] ;
  wire \tx_64.req_data_reg_n_0_[19] ;
  wire \tx_64.req_data_reg_n_0_[1] ;
  wire \tx_64.req_data_reg_n_0_[20] ;
  wire \tx_64.req_data_reg_n_0_[21] ;
  wire \tx_64.req_data_reg_n_0_[22] ;
  wire \tx_64.req_data_reg_n_0_[23] ;
  wire \tx_64.req_data_reg_n_0_[24] ;
  wire \tx_64.req_data_reg_n_0_[25] ;
  wire \tx_64.req_data_reg_n_0_[26] ;
  wire \tx_64.req_data_reg_n_0_[27] ;
  wire \tx_64.req_data_reg_n_0_[28] ;
  wire \tx_64.req_data_reg_n_0_[29] ;
  wire \tx_64.req_data_reg_n_0_[2] ;
  wire \tx_64.req_data_reg_n_0_[30] ;
  wire \tx_64.req_data_reg_n_0_[31] ;
  wire \tx_64.req_data_reg_n_0_[3] ;
  wire \tx_64.req_data_reg_n_0_[4] ;
  wire \tx_64.req_data_reg_n_0_[5] ;
  wire \tx_64.req_data_reg_n_0_[6] ;
  wire \tx_64.req_data_reg_n_0_[7] ;
  wire \tx_64.req_data_reg_n_0_[8] ;
  wire \tx_64.req_data_reg_n_0_[9] ;
  wire \tx_64.req_fbe_reg_n_0_[0] ;
  wire \tx_64.req_fbe_reg_n_0_[1] ;
  wire \tx_64.req_fbe_reg_n_0_[2] ;
  wire \tx_64.req_fbe_reg_n_0_[3] ;
  wire \tx_64.req_len_reg_n_0_[0] ;
  wire \tx_64.req_len_reg_n_0_[1] ;
  wire \tx_64.req_len_reg_n_0_[2] ;
  wire \tx_64.req_len_reg_n_0_[3] ;
  wire \tx_64.req_len_reg_n_0_[4] ;
  wire \tx_64.req_len_reg_n_0_[5] ;
  wire \tx_64.req_len_reg_n_0_[6] ;
  wire \tx_64.req_len_reg_n_0_[7] ;
  wire \tx_64.req_len_reg_n_0_[8] ;
  wire \tx_64.req_len_reg_n_0_[9] ;
  wire \tx_64.req_mesg_i_1_n_0 ;
  wire \tx_64.req_mesg_i_3_n_0 ;
  wire [7:0]\tx_64.req_msg_code_reg[7]_0 ;
  wire \tx_64.req_msg_code_reg_n_0_[0] ;
  wire \tx_64.req_msg_code_reg_n_0_[1] ;
  wire \tx_64.req_msg_code_reg_n_0_[2] ;
  wire \tx_64.req_msg_code_reg_n_0_[3] ;
  wire \tx_64.req_msg_code_reg_n_0_[4] ;
  wire \tx_64.req_msg_code_reg_n_0_[5] ;
  wire \tx_64.req_msg_code_reg_n_0_[6] ;
  wire \tx_64.req_msg_code_reg_n_0_[7] ;
  wire [63:0]\tx_64.req_rid_reg[15]_0 ;
  wire \tx_64.req_rid_reg_n_0_[0] ;
  wire \tx_64.req_rid_reg_n_0_[10] ;
  wire \tx_64.req_rid_reg_n_0_[11] ;
  wire \tx_64.req_rid_reg_n_0_[12] ;
  wire \tx_64.req_rid_reg_n_0_[13] ;
  wire \tx_64.req_rid_reg_n_0_[14] ;
  wire \tx_64.req_rid_reg_n_0_[15] ;
  wire \tx_64.req_rid_reg_n_0_[1] ;
  wire \tx_64.req_rid_reg_n_0_[2] ;
  wire \tx_64.req_rid_reg_n_0_[3] ;
  wire \tx_64.req_rid_reg_n_0_[4] ;
  wire \tx_64.req_rid_reg_n_0_[5] ;
  wire \tx_64.req_rid_reg_n_0_[6] ;
  wire \tx_64.req_rid_reg_n_0_[7] ;
  wire \tx_64.req_rid_reg_n_0_[8] ;
  wire \tx_64.req_rid_reg_n_0_[9] ;
  wire \tx_64.req_tag_reg[0]_0 ;
  wire \tx_64.req_tag_reg_n_0_[0] ;
  wire \tx_64.req_tag_reg_n_0_[1] ;
  wire \tx_64.req_tag_reg_n_0_[2] ;
  wire \tx_64.req_tag_reg_n_0_[3] ;
  wire \tx_64.req_tag_reg_n_0_[4] ;
  wire \tx_64.req_tag_reg_n_0_[5] ;
  wire \tx_64.req_tag_reg_n_0_[6] ;
  wire \tx_64.req_tag_reg_n_0_[7] ;
  wire \tx_64.req_tc_reg_n_0_[0] ;
  wire \tx_64.req_tc_reg_n_0_[1] ;
  wire \tx_64.req_tc_reg_n_0_[2] ;
  wire \tx_64.req_type_reg_n_0_[0] ;
  wire \tx_64.req_type_reg_n_0_[1] ;
  wire \tx_64.req_type_reg_n_0_[2] ;
  wire \tx_64.req_wr_i_1_n_0 ;
  wire \tx_64.req_wr_reg_n_0 ;
  wire udma_wrapper_i_174_n_0;
  wire udma_wrapper_i_175_n_0;
  wire udma_wrapper_i_176_n_0;
  wire udma_wrapper_i_177_n_0;
  wire udma_wrapper_i_178_n_0;
  wire udma_wrapper_i_179_n_0;
  wire udma_wrapper_i_180_n_0;
  wire udma_wrapper_i_181_n_0;
  wire udma_wrapper_i_182_n_0;
  wire udma_wrapper_i_183_n_0;
  wire udma_wrapper_i_184_n_0;
  wire udma_wrapper_i_185_n_0;
  wire udma_wrapper_i_186_n_0;
  wire udma_wrapper_i_187_n_0;
  wire udma_wrapper_i_188_n_0;
  wire udma_wrapper_i_189_n_0;
  wire udma_wrapper_i_190_n_0;
  wire udma_wrapper_i_191_n_0;
  wire udma_wrapper_i_192_n_0;
  wire udma_wrapper_i_193_n_0;
  wire udma_wrapper_i_194_n_0;
  wire udma_wrapper_i_195_n_0;
  wire udma_wrapper_i_196_n_0;
  wire udma_wrapper_i_197_n_0;
  wire udma_wrapper_i_198_n_0;
  wire udma_wrapper_i_199_n_0;
  wire udma_wrapper_i_200_n_0;
  wire udma_wrapper_i_201_n_0;
  wire udma_wrapper_i_202_n_0;
  wire udma_wrapper_i_203_n_0;
  wire udma_wrapper_i_204_n_0;
  wire udma_wrapper_i_205_n_0;
  wire udma_wrapper_i_206_n_0;
  wire udma_wrapper_i_207_n_0;
  wire udma_wrapper_i_208_n_0;
  wire udma_wrapper_i_209_n_0;
  wire udma_wrapper_i_210_n_0;
  wire udma_wrapper_i_211_n_0;
  wire udma_wrapper_i_212_n_0;
  wire udma_wrapper_i_213_n_0;
  wire udma_wrapper_i_214_n_0;
  wire udma_wrapper_i_215_n_0;
  wire udma_wrapper_i_216_n_0;
  wire udma_wrapper_i_217_n_0;
  wire udma_wrapper_i_218_n_0;
  wire udma_wrapper_i_219_n_0;
  wire udma_wrapper_i_220_n_0;
  wire udma_wrapper_i_221_n_0;
  wire udma_wrapper_i_222_n_0;
  wire udma_wrapper_i_223_n_0;
  wire udma_wrapper_i_224_n_0;
  wire udma_wrapper_i_225_n_0;
  wire udma_wrapper_i_226_n_0;
  wire udma_wrapper_i_227_n_0;
  wire udma_wrapper_i_228_n_0;
  wire udma_wrapper_i_229_n_0;
  wire udma_wrapper_i_230_n_0;
  wire udma_wrapper_i_231_n_0;
  wire udma_wrapper_i_232_n_0;
  wire udma_wrapper_i_233_n_0;
  wire udma_wrapper_i_234_n_0;
  wire udma_wrapper_i_235_n_0;
  wire udma_wrapper_i_236_n_0;
  wire udma_wrapper_i_237_n_0;
  wire udma_wrapper_i_238_n_0;
  wire udma_wrapper_i_239_n_0;
  wire udma_wrapper_i_257_n_0;
  wire udma_wrapper_i_258_n_0;
  wire udma_wrapper_i_259_n_0;
  wire udma_wrapper_i_260_n_0;
  wire udma_wrapper_i_261_n_0;
  wire udma_wrapper_i_262_n_0;
  wire udma_wrapper_i_263_n_0;
  wire udma_wrapper_i_280_n_0;
  wire user_clk_out;
  wire user_reset_out;

  LUT6 #(
    .INIT(64'hD580DDBBD580D580)) 
    \FSM_sequential_tx_64.state[0]_i_1__0 
       (.I0(\s_axis_cq\.tready ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(\FSM_sequential_tx_64.state[1]_i_2__0_n_0 ),
        .I3(state),
        .I4(in_packet_q),
        .I5(\tx_64.req_tag_reg[0]_0 ),
        .O(state__0[0]));
  LUT4 #(
    .INIT(16'hF858)) 
    \FSM_sequential_tx_64.state[1]_i_1__0 
       (.I0(\s_axis_cq\.tready ),
        .I1(state),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(\FSM_sequential_tx_64.state[1]_i_2__0_n_0 ),
        .O(state__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair2021" *) 
  LUT5 #(
    .INIT(32'hFFFF5404)) 
    \FSM_sequential_tx_64.state[1]_i_2__0 
       (.I0(state),
        .I1(\tx_64.req_wr_reg_n_0 ),
        .I2(in130),
        .I3(p_0_in22_in),
        .I4(user_reset_out),
        .O(\FSM_sequential_tx_64.state[1]_i_2__0_n_0 ));
  (* FSM_ENCODED_STATES = "RX_DW2:10,RX_WAIT:11,RX_IDLE:00,RX_DW0_DW1:01" *) 
  FDRE \FSM_sequential_tx_64.state_reg[0] 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(state__0[0]),
        .Q(state),
        .R(user_reset_out));
  (* FSM_ENCODED_STATES = "RX_DW2:10,RX_WAIT:11,RX_IDLE:00,RX_DW0_DW1:01" *) 
  FDRE \FSM_sequential_tx_64.state_reg[1] 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(state__0[1]),
        .Q(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .R(user_reset_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8000000)) 
    in_packet_q_i_1__1
       (.I0(in130),
        .I1(p_0_in22_in),
        .I2(\tx_64.req_wr_reg_n_0 ),
        .I3(udma_wrapper_i_184_n_0),
        .I4(in_packet_q_i_2_n_0),
        .I5(in_packet_q_i_3_n_0),
        .O(in_packet_q_i_1__1_n_0));
  LUT3 #(
    .INIT(8'hF8)) 
    in_packet_q_i_2
       (.I0(\tx_64.req_tag_reg[0]_0 ),
        .I1(m_axis_tready),
        .I2(in_packet_q),
        .O(in_packet_q_i_2_n_0));
  LUT6 #(
    .INIT(64'h222200002FFF0000)) 
    in_packet_q_i_3
       (.I0(in_packet_q_i_4_n_0),
        .I1(\s_axis_cq\.tready ),
        .I2(m_axis_tlast),
        .I3(\tx_64.req_tag_reg[0]_0 ),
        .I4(in_packet_q_i_2_n_0),
        .I5(user_reset_out),
        .O(in_packet_q_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2020" *) 
  LUT3 #(
    .INIT(8'h32)) 
    in_packet_q_i_4
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(user_reset_out),
        .I2(state),
        .O(in_packet_q_i_4_n_0));
  FDRE in_packet_q_reg
       (.C(user_clk_out),
        .CE(1'b1),
        .D(in_packet_q_i_1__1_n_0),
        .Q(in_packet_q),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFAE00FF55)) 
    tgt_brdg_fifo_inst_i_1
       (.I0(state),
        .I1(tgt_brdg_fifo_inst_i_2_n_0),
        .I2(\tx_64.req_wr_reg_n_0 ),
        .I3(\s_axis_cq\.tready ),
        .I4(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I5(user_reset_out),
        .O(m_axis_tready));
  (* SOFT_HLUTNM = "soft_lutpair2051" *) 
  LUT2 #(
    .INIT(4'h7)) 
    tgt_brdg_fifo_inst_i_2
       (.I0(p_0_in22_in),
        .I1(in130),
        .O(tgt_brdg_fifo_inst_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2050" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tx_64.req_4dw_i_1__0 
       (.I0(\tx_64.req_rid_reg[15]_0 [29]),
        .I1(req_wr),
        .I2(req_4dw),
        .O(\tx_64.req_4dw_i_1__0_n_0 ));
  FDRE \tx_64.req_4dw_reg 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\tx_64.req_4dw_i_1__0_n_0 ),
        .Q(req_4dw),
        .R(user_reset_out));
  FDRE \tx_64.req_ATS_reg 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_ATS),
        .Q(sel0[2]),
        .R(user_reset_out));
  FDRE \tx_64.req_LTR_reg 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_LTR),
        .Q(sel0[1]),
        .R(user_reset_out));
  FDRE \tx_64.req_OBFF_reg 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_OBFF),
        .Q(sel0[0]),
        .R(user_reset_out));
  FDRE \tx_64.req_VDM_reg 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_VDM),
        .Q(sel0[3]),
        .R(user_reset_out));
  LUT6 #(
    .INIT(64'hB8BB8888B8888888)) 
    \tx_64.req_addr[2]_i_1 
       (.I0(p_0_in),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(\tx_64.req_rid_reg[15]_0 [34]),
        .I3(\tx_64.req_addr[2]_i_2_n_0 ),
        .I4(state),
        .I5(\tx_64.req_rid_reg[15]_0 [2]),
        .O(\tx_64.req_addr[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2051" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \tx_64.req_addr[2]_i_2 
       (.I0(req_4dw),
        .I1(in130),
        .I2(p_0_in22_in),
        .O(\tx_64.req_addr[2]_i_2_n_0 ));
  FDRE \tx_64.req_addr_reg[2] 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\tx_64.req_addr[2]_i_1_n_0 ),
        .Q(p_0_in),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2042" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_at[0]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [10]),
        .O(req_at[0]));
  (* SOFT_HLUTNM = "soft_lutpair2042" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_at[1]_i_1__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [11]),
        .O(req_at[1]));
  FDRE \tx_64.req_at_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_at[0]),
        .Q(\tx_64.req_at_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_at_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_at[1]),
        .Q(\tx_64.req_at_reg_n_0_[1] ),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2043" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_attr[0]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [12]),
        .O(req_attr[0]));
  (* SOFT_HLUTNM = "soft_lutpair2043" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_attr[1]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [13]),
        .O(req_attr[1]));
  (* SOFT_HLUTNM = "soft_lutpair2044" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_attr[2]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [18]),
        .O(req_attr[2]));
  FDRE \tx_64.req_attr_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_attr[0]),
        .Q(\tx_64.req_attr_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_attr_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_attr[1]),
        .Q(\tx_64.req_attr_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.req_attr_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_attr[2]),
        .Q(\tx_64.req_attr_reg_n_0_[2] ),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2024" *) 
  LUT3 #(
    .INIT(8'hF4)) 
    \tx_64.req_bar_id[2]_i_2 
       (.I0(in_packet_q),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(in_packet_q_reg_0));
  FDRE \tx_64.req_bar_id_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(\tx_64.req_bar_id_reg[2]_0 [0]),
        .Q(\tx_64.req_bar_id_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_bar_id_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(\tx_64.req_bar_id_reg[2]_0 [1]),
        .Q(\tx_64.req_bar_id_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.req_bar_id_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(\tx_64.req_bar_id_reg[2]_0 [2]),
        .Q(\tx_64.req_bar_id_reg_n_0_[2] ),
        .R(user_reset_out));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[0]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [0]),
        .I1(\tx_64.req_rid_reg[15]_0 [32]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[0]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[10]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [10]),
        .I1(\tx_64.req_rid_reg[15]_0 [42]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[10]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[11]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [11]),
        .I1(\tx_64.req_rid_reg[15]_0 [43]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[11]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[12]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [12]),
        .I1(\tx_64.req_rid_reg[15]_0 [44]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[12]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[13]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [13]),
        .I1(\tx_64.req_rid_reg[15]_0 [45]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[13]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[14]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [14]),
        .I1(\tx_64.req_rid_reg[15]_0 [46]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[14]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[15]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [15]),
        .I1(\tx_64.req_rid_reg[15]_0 [47]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[15]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[16]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [16]),
        .I1(\tx_64.req_rid_reg[15]_0 [48]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[16]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[17]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [17]),
        .I1(\tx_64.req_rid_reg[15]_0 [49]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[17]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[18]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [18]),
        .I1(\tx_64.req_rid_reg[15]_0 [50]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[18]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[19]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [19]),
        .I1(\tx_64.req_rid_reg[15]_0 [51]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[19]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[1]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [1]),
        .I1(\tx_64.req_rid_reg[15]_0 [33]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[1]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[20]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [20]),
        .I1(\tx_64.req_rid_reg[15]_0 [52]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[20]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[21]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [21]),
        .I1(\tx_64.req_rid_reg[15]_0 [53]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[21]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[22]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [22]),
        .I1(\tx_64.req_rid_reg[15]_0 [54]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[22]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[23]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [23]),
        .I1(\tx_64.req_rid_reg[15]_0 [55]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[23]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[24]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [24]),
        .I1(\tx_64.req_rid_reg[15]_0 [56]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[24]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[25]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [25]),
        .I1(\tx_64.req_rid_reg[15]_0 [57]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[25]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[26]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [26]),
        .I1(\tx_64.req_rid_reg[15]_0 [58]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[26]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[27]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [27]),
        .I1(\tx_64.req_rid_reg[15]_0 [59]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[27]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[28]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [28]),
        .I1(\tx_64.req_rid_reg[15]_0 [60]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[28]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[29]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [29]),
        .I1(\tx_64.req_rid_reg[15]_0 [61]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[29]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[2]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [2]),
        .I1(\tx_64.req_rid_reg[15]_0 [34]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[2]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[30]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [30]),
        .I1(\tx_64.req_rid_reg[15]_0 [62]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[30]));
  LUT5 #(
    .INIT(32'h00FFEA00)) 
    \tx_64.req_data[31]_i_1 
       (.I0(req_4dw),
        .I1(in130),
        .I2(p_0_in22_in),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(state),
        .O(\tx_64.req_data[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[31]_i_2 
       (.I0(\tx_64.req_rid_reg[15]_0 [31]),
        .I1(\tx_64.req_rid_reg[15]_0 [63]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[31]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[3]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [3]),
        .I1(\tx_64.req_rid_reg[15]_0 [35]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[3]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[4]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [4]),
        .I1(\tx_64.req_rid_reg[15]_0 [36]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[5]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [5]),
        .I1(\tx_64.req_rid_reg[15]_0 [37]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[5]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[6]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [6]),
        .I1(\tx_64.req_rid_reg[15]_0 [38]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[6]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[7]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [7]),
        .I1(\tx_64.req_rid_reg[15]_0 [39]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[7]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[8]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [8]),
        .I1(\tx_64.req_rid_reg[15]_0 [40]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[8]));
  LUT6 #(
    .INIT(64'hAAAAAAAA00000CCC)) 
    \tx_64.req_data[9]_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [9]),
        .I1(\tx_64.req_rid_reg[15]_0 [41]),
        .I2(p_0_in22_in),
        .I3(in130),
        .I4(req_4dw),
        .I5(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(req_data[9]));
  FDRE \tx_64.req_data_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[0]),
        .Q(\tx_64.req_data_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[10] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[10]),
        .Q(\tx_64.req_data_reg_n_0_[10] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[11] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[11]),
        .Q(\tx_64.req_data_reg_n_0_[11] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[12] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[12]),
        .Q(\tx_64.req_data_reg_n_0_[12] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[13] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[13]),
        .Q(\tx_64.req_data_reg_n_0_[13] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[14] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[14]),
        .Q(\tx_64.req_data_reg_n_0_[14] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[15] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[15]),
        .Q(\tx_64.req_data_reg_n_0_[15] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[16] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[16]),
        .Q(\tx_64.req_data_reg_n_0_[16] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[17] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[17]),
        .Q(\tx_64.req_data_reg_n_0_[17] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[18] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[18]),
        .Q(\tx_64.req_data_reg_n_0_[18] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[19] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[19]),
        .Q(\tx_64.req_data_reg_n_0_[19] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[1]),
        .Q(\tx_64.req_data_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[20] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[20]),
        .Q(\tx_64.req_data_reg_n_0_[20] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[21] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[21]),
        .Q(\tx_64.req_data_reg_n_0_[21] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[22] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[22]),
        .Q(\tx_64.req_data_reg_n_0_[22] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[23] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[23]),
        .Q(\tx_64.req_data_reg_n_0_[23] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[24] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[24]),
        .Q(\tx_64.req_data_reg_n_0_[24] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[25] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[25]),
        .Q(\tx_64.req_data_reg_n_0_[25] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[26] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[26]),
        .Q(\tx_64.req_data_reg_n_0_[26] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[27] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[27]),
        .Q(\tx_64.req_data_reg_n_0_[27] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[28] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[28]),
        .Q(\tx_64.req_data_reg_n_0_[28] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[29] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[29]),
        .Q(\tx_64.req_data_reg_n_0_[29] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[2]),
        .Q(\tx_64.req_data_reg_n_0_[2] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[30] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[30]),
        .Q(\tx_64.req_data_reg_n_0_[30] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[31] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[31]),
        .Q(\tx_64.req_data_reg_n_0_[31] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[3] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[3]),
        .Q(\tx_64.req_data_reg_n_0_[3] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[4] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[4]),
        .Q(\tx_64.req_data_reg_n_0_[4] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[5] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[5]),
        .Q(\tx_64.req_data_reg_n_0_[5] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[6] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[6]),
        .Q(\tx_64.req_data_reg_n_0_[6] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[7] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[7]),
        .Q(\tx_64.req_data_reg_n_0_[7] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[8] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[8]),
        .Q(\tx_64.req_data_reg_n_0_[8] ),
        .R(user_reset_out));
  FDRE \tx_64.req_data_reg[9] 
       (.C(user_clk_out),
        .CE(\tx_64.req_data[31]_i_1_n_0 ),
        .D(req_data[9]),
        .Q(\tx_64.req_data_reg_n_0_[9] ),
        .R(user_reset_out));
  FDRE \tx_64.req_fbe_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(D[0]),
        .Q(\tx_64.req_fbe_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_fbe_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(D[1]),
        .Q(\tx_64.req_fbe_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.req_fbe_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(D[2]),
        .Q(\tx_64.req_fbe_reg_n_0_[2] ),
        .R(user_reset_out));
  FDRE \tx_64.req_fbe_reg[3] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(D[3]),
        .Q(\tx_64.req_fbe_reg_n_0_[3] ),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2047" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_fmt[1]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [30]),
        .O(req_fmt));
  FDRE \tx_64.req_fmt_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_fmt),
        .Q(p_0_in22_in),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2037" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_len[0]_i_1__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [0]),
        .O(req_len[0]));
  (* SOFT_HLUTNM = "soft_lutpair2037" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_len[1]_i_1__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [1]),
        .O(req_len[1]));
  (* SOFT_HLUTNM = "soft_lutpair2038" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_len[2]_i_1__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [2]),
        .O(req_len[2]));
  (* SOFT_HLUTNM = "soft_lutpair2038" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_len[3]_i_1__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [3]),
        .O(req_len[3]));
  (* SOFT_HLUTNM = "soft_lutpair2039" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_len[4]_i_1__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [4]),
        .O(req_len[4]));
  (* SOFT_HLUTNM = "soft_lutpair2039" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_len[5]_i_1__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [5]),
        .O(req_len[5]));
  (* SOFT_HLUTNM = "soft_lutpair2040" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_len[6]_i_1__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [6]),
        .O(req_len[6]));
  (* SOFT_HLUTNM = "soft_lutpair2040" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_len[7]_i_1__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [7]),
        .O(req_len[7]));
  (* SOFT_HLUTNM = "soft_lutpair2041" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_len[8]_i_1__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [8]),
        .O(req_len[8]));
  (* SOFT_HLUTNM = "soft_lutpair2041" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_len[9]_i_1__0 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [9]),
        .O(req_len[9]));
  FDRE \tx_64.req_len_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_len[0]),
        .Q(\tx_64.req_len_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_len[1]),
        .Q(\tx_64.req_len_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_len[2]),
        .Q(\tx_64.req_len_reg_n_0_[2] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[3] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_len[3]),
        .Q(\tx_64.req_len_reg_n_0_[3] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[4] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_len[4]),
        .Q(\tx_64.req_len_reg_n_0_[4] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[5] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_len[5]),
        .Q(\tx_64.req_len_reg_n_0_[5] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[6] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_len[6]),
        .Q(\tx_64.req_len_reg_n_0_[6] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[7] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_len[7]),
        .Q(\tx_64.req_len_reg_n_0_[7] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[8] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_len[8]),
        .Q(\tx_64.req_len_reg_n_0_[8] ),
        .R(user_reset_out));
  FDRE \tx_64.req_len_reg[9] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_len[9]),
        .Q(\tx_64.req_len_reg_n_0_[9] ),
        .R(user_reset_out));
  LUT5 #(
    .INIT(32'hCB030303)) 
    \tx_64.req_mesg_i_1 
       (.I0(\tx_64.req_mesg_i_3_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(\tx_64.req_VDM_reg_0 ),
        .I4(\s_axis_cq\.tready ),
        .O(\tx_64.req_mesg_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2024" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_mesg_i_2 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [28]),
        .O(req_mesg));
  (* SOFT_HLUTNM = "soft_lutpair2021" *) 
  LUT3 #(
    .INIT(8'h47)) 
    \tx_64.req_mesg_i_3 
       (.I0(p_0_in22_in),
        .I1(in130),
        .I2(\tx_64.req_wr_reg_n_0 ),
        .O(\tx_64.req_mesg_i_3_n_0 ));
  FDRE \tx_64.req_mesg_reg 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_mesg),
        .Q(in130),
        .R(user_reset_out));
  FDRE \tx_64.req_msg_code_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(\tx_64.req_msg_code_reg[7]_0 [0]),
        .Q(\tx_64.req_msg_code_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_msg_code_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(\tx_64.req_msg_code_reg[7]_0 [1]),
        .Q(\tx_64.req_msg_code_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.req_msg_code_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(\tx_64.req_msg_code_reg[7]_0 [2]),
        .Q(\tx_64.req_msg_code_reg_n_0_[2] ),
        .R(user_reset_out));
  FDRE \tx_64.req_msg_code_reg[3] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(\tx_64.req_msg_code_reg[7]_0 [3]),
        .Q(\tx_64.req_msg_code_reg_n_0_[3] ),
        .R(user_reset_out));
  FDRE \tx_64.req_msg_code_reg[4] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(\tx_64.req_msg_code_reg[7]_0 [4]),
        .Q(\tx_64.req_msg_code_reg_n_0_[4] ),
        .R(user_reset_out));
  FDRE \tx_64.req_msg_code_reg[5] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(\tx_64.req_msg_code_reg[7]_0 [5]),
        .Q(\tx_64.req_msg_code_reg_n_0_[5] ),
        .R(user_reset_out));
  FDRE \tx_64.req_msg_code_reg[6] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(\tx_64.req_msg_code_reg[7]_0 [6]),
        .Q(\tx_64.req_msg_code_reg_n_0_[6] ),
        .R(user_reset_out));
  FDRE \tx_64.req_msg_code_reg[7] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(\tx_64.req_msg_code_reg[7]_0 [7]),
        .Q(\tx_64.req_msg_code_reg_n_0_[7] ),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2029" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[0]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [48]),
        .O(req_rid[0]));
  (* SOFT_HLUTNM = "soft_lutpair2034" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[10]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [58]),
        .O(req_rid[10]));
  (* SOFT_HLUTNM = "soft_lutpair2034" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[11]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [59]),
        .O(req_rid[11]));
  (* SOFT_HLUTNM = "soft_lutpair2035" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[12]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [60]),
        .O(req_rid[12]));
  (* SOFT_HLUTNM = "soft_lutpair2035" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[13]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [61]),
        .O(req_rid[13]));
  (* SOFT_HLUTNM = "soft_lutpair2036" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[14]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [62]),
        .O(req_rid[14]));
  (* SOFT_HLUTNM = "soft_lutpair2036" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[15]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [63]),
        .O(req_rid[15]));
  (* SOFT_HLUTNM = "soft_lutpair2029" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[1]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [49]),
        .O(req_rid[1]));
  (* SOFT_HLUTNM = "soft_lutpair2030" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[2]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [50]),
        .O(req_rid[2]));
  (* SOFT_HLUTNM = "soft_lutpair2030" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[3]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [51]),
        .O(req_rid[3]));
  (* SOFT_HLUTNM = "soft_lutpair2031" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[4]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [52]),
        .O(req_rid[4]));
  (* SOFT_HLUTNM = "soft_lutpair2031" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[5]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [53]),
        .O(req_rid[5]));
  (* SOFT_HLUTNM = "soft_lutpair2032" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[6]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [54]),
        .O(req_rid[6]));
  (* SOFT_HLUTNM = "soft_lutpair2032" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[7]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [55]),
        .O(req_rid[7]));
  (* SOFT_HLUTNM = "soft_lutpair2033" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[8]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [56]),
        .O(req_rid[8]));
  (* SOFT_HLUTNM = "soft_lutpair2033" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_rid[9]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [57]),
        .O(req_rid[9]));
  FDRE \tx_64.req_rid_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[0]),
        .Q(\tx_64.req_rid_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[10] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[10]),
        .Q(\tx_64.req_rid_reg_n_0_[10] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[11] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[11]),
        .Q(\tx_64.req_rid_reg_n_0_[11] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[12] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[12]),
        .Q(\tx_64.req_rid_reg_n_0_[12] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[13] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[13]),
        .Q(\tx_64.req_rid_reg_n_0_[13] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[14] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[14]),
        .Q(\tx_64.req_rid_reg_n_0_[14] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[15] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[15]),
        .Q(\tx_64.req_rid_reg_n_0_[15] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[1]),
        .Q(\tx_64.req_rid_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[2]),
        .Q(\tx_64.req_rid_reg_n_0_[2] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[3] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[3]),
        .Q(\tx_64.req_rid_reg_n_0_[3] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[4] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[4]),
        .Q(\tx_64.req_rid_reg_n_0_[4] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[5] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[5]),
        .Q(\tx_64.req_rid_reg_n_0_[5] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[6] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[6]),
        .Q(\tx_64.req_rid_reg_n_0_[6] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[7] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[7]),
        .Q(\tx_64.req_rid_reg_n_0_[7] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[8] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[8]),
        .Q(\tx_64.req_rid_reg_n_0_[8] ),
        .R(user_reset_out));
  FDRE \tx_64.req_rid_reg[9] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_rid[9]),
        .Q(\tx_64.req_rid_reg_n_0_[9] ),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2025" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_tag[0]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [40]),
        .O(req_tag[0]));
  (* SOFT_HLUTNM = "soft_lutpair2025" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_tag[1]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [41]),
        .O(req_tag[1]));
  (* SOFT_HLUTNM = "soft_lutpair2026" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_tag[2]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [42]),
        .O(req_tag[2]));
  (* SOFT_HLUTNM = "soft_lutpair2026" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_tag[3]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [43]),
        .O(req_tag[3]));
  (* SOFT_HLUTNM = "soft_lutpair2027" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_tag[4]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [44]),
        .O(req_tag[4]));
  (* SOFT_HLUTNM = "soft_lutpair2027" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_tag[5]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [45]),
        .O(req_tag[5]));
  (* SOFT_HLUTNM = "soft_lutpair2028" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_tag[6]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [46]),
        .O(req_tag[6]));
  (* SOFT_HLUTNM = "soft_lutpair2028" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_tag[7]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [47]),
        .O(req_tag[7]));
  FDRE \tx_64.req_tag_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_tag[0]),
        .Q(\tx_64.req_tag_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_tag_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_tag[1]),
        .Q(\tx_64.req_tag_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.req_tag_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_tag[2]),
        .Q(\tx_64.req_tag_reg_n_0_[2] ),
        .R(user_reset_out));
  FDRE \tx_64.req_tag_reg[3] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_tag[3]),
        .Q(\tx_64.req_tag_reg_n_0_[3] ),
        .R(user_reset_out));
  FDRE \tx_64.req_tag_reg[4] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_tag[4]),
        .Q(\tx_64.req_tag_reg_n_0_[4] ),
        .R(user_reset_out));
  FDRE \tx_64.req_tag_reg[5] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_tag[5]),
        .Q(\tx_64.req_tag_reg_n_0_[5] ),
        .R(user_reset_out));
  FDRE \tx_64.req_tag_reg[6] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_tag[6]),
        .Q(\tx_64.req_tag_reg_n_0_[6] ),
        .R(user_reset_out));
  FDRE \tx_64.req_tag_reg[7] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_tag[7]),
        .Q(\tx_64.req_tag_reg_n_0_[7] ),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2044" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_tc[0]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [20]),
        .O(req_tc[0]));
  (* SOFT_HLUTNM = "soft_lutpair2045" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_tc[1]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [21]),
        .O(req_tc[1]));
  (* SOFT_HLUTNM = "soft_lutpair2045" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_tc[2]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [22]),
        .O(req_tc[2]));
  FDRE \tx_64.req_tc_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_tc[0]),
        .Q(\tx_64.req_tc_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_tc_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_tc[1]),
        .Q(\tx_64.req_tc_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.req_tc_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_tc[2]),
        .Q(\tx_64.req_tc_reg_n_0_[2] ),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2046" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_type[0]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [24]),
        .O(req_type[0]));
  (* SOFT_HLUTNM = "soft_lutpair2046" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_type[1]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [25]),
        .O(req_type[1]));
  (* SOFT_HLUTNM = "soft_lutpair2047" *) 
  LUT4 #(
    .INIT(16'hAE00)) 
    \tx_64.req_type[2]_i_1 
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(\tx_64.req_tag_reg[0]_0 ),
        .I2(in_packet_q),
        .I3(\tx_64.req_rid_reg[15]_0 [26]),
        .O(req_type[2]));
  FDRE \tx_64.req_type_reg[0] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_type[0]),
        .Q(\tx_64.req_type_reg_n_0_[0] ),
        .R(user_reset_out));
  FDRE \tx_64.req_type_reg[1] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_type[1]),
        .Q(\tx_64.req_type_reg_n_0_[1] ),
        .R(user_reset_out));
  FDRE \tx_64.req_type_reg[2] 
       (.C(user_clk_out),
        .CE(\tx_64.req_mesg_i_1_n_0 ),
        .D(req_type[2]),
        .Q(\tx_64.req_type_reg_n_0_[2] ),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2050" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tx_64.req_wr_i_1 
       (.I0(\tx_64.req_rid_reg[15]_0 [30]),
        .I1(req_wr),
        .I2(\tx_64.req_wr_reg_n_0 ),
        .O(\tx_64.req_wr_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h03CB000003030000)) 
    \tx_64.req_wr_i_2 
       (.I0(\tx_64.req_mesg_i_3_n_0 ),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .I3(user_reset_out),
        .I4(\tx_64.req_VDM_reg_0 ),
        .I5(\s_axis_cq\.tready ),
        .O(req_wr));
  FDRE \tx_64.req_wr_reg 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\tx_64.req_wr_i_1_n_0 ),
        .Q(\tx_64.req_wr_reg_n_0 ),
        .R(user_reset_out));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_100
       (.I0(\tx_64.req_tag_reg_n_0_[5] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_197_n_0),
        .O(\s_axis_cq\.tdata [37]));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_101
       (.I0(\tx_64.req_tag_reg_n_0_[4] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_198_n_0),
        .O(\s_axis_cq\.tdata [36]));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_102
       (.I0(\tx_64.req_tag_reg_n_0_[3] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_199_n_0),
        .O(\s_axis_cq\.tdata [35]));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_103
       (.I0(\tx_64.req_tag_reg_n_0_[2] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_200_n_0),
        .O(\s_axis_cq\.tdata [34]));
  (* SOFT_HLUTNM = "soft_lutpair2020" *) 
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_104
       (.I0(\tx_64.req_tag_reg_n_0_[1] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_201_n_0),
        .O(\s_axis_cq\.tdata [33]));
  (* SOFT_HLUTNM = "soft_lutpair2019" *) 
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_105
       (.I0(\tx_64.req_tag_reg_n_0_[0] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_202_n_0),
        .O(\s_axis_cq\.tdata [32]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_106
       (.I0(udma_wrapper_i_203_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[15] ),
        .I3(\tx_64.req_data_reg_n_0_[7] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [31]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_107
       (.I0(udma_wrapper_i_205_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[14] ),
        .I3(\tx_64.req_data_reg_n_0_[6] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [30]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_108
       (.I0(udma_wrapper_i_206_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[13] ),
        .I3(\tx_64.req_data_reg_n_0_[5] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [29]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_109
       (.I0(udma_wrapper_i_207_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[12] ),
        .I3(\tx_64.req_data_reg_n_0_[4] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [28]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_110
       (.I0(udma_wrapper_i_208_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[11] ),
        .I3(\tx_64.req_data_reg_n_0_[3] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [27]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_111
       (.I0(udma_wrapper_i_209_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[10] ),
        .I3(\tx_64.req_data_reg_n_0_[2] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [26]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_112
       (.I0(udma_wrapper_i_210_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[9] ),
        .I3(\tx_64.req_data_reg_n_0_[1] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [25]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_113
       (.I0(udma_wrapper_i_211_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[8] ),
        .I3(\tx_64.req_data_reg_n_0_[0] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [24]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_114
       (.I0(udma_wrapper_i_212_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[7] ),
        .I3(\tx_64.req_data_reg_n_0_[15] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [23]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_115
       (.I0(udma_wrapper_i_213_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[6] ),
        .I3(\tx_64.req_data_reg_n_0_[14] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [22]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_116
       (.I0(udma_wrapper_i_214_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[5] ),
        .I3(\tx_64.req_data_reg_n_0_[13] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [21]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_117
       (.I0(udma_wrapper_i_215_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[4] ),
        .I3(\tx_64.req_data_reg_n_0_[12] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [20]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_118
       (.I0(udma_wrapper_i_216_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[3] ),
        .I3(\tx_64.req_data_reg_n_0_[11] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [19]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_119
       (.I0(udma_wrapper_i_217_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[2] ),
        .I3(\tx_64.req_data_reg_n_0_[10] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [18]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_120
       (.I0(udma_wrapper_i_218_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[1] ),
        .I3(\tx_64.req_data_reg_n_0_[9] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [17]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_121
       (.I0(udma_wrapper_i_219_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_rid_reg_n_0_[0] ),
        .I3(\tx_64.req_data_reg_n_0_[8] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [16]));
  (* SOFT_HLUTNM = "soft_lutpair2049" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    udma_wrapper_i_122
       (.I0(\tx_64.req_data_reg_n_0_[23] ),
        .I1(udma_wrapper_i_204_n_0),
        .I2(udma_wrapper_i_220_n_0),
        .O(\s_axis_cq\.tdata [15]));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    udma_wrapper_i_123
       (.I0(udma_wrapper_i_184_n_0),
        .I1(in130),
        .I2(udma_wrapper_i_221_n_0),
        .I3(\tx_64.req_data_reg_n_0_[22] ),
        .I4(udma_wrapper_i_222_n_0),
        .O(\s_axis_cq\.tdata [14]));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    udma_wrapper_i_124
       (.I0(udma_wrapper_i_184_n_0),
        .I1(in130),
        .I2(udma_wrapper_i_221_n_0),
        .I3(\tx_64.req_data_reg_n_0_[21] ),
        .I4(udma_wrapper_i_223_n_0),
        .O(\s_axis_cq\.tdata [13]));
  LUT6 #(
    .INIT(64'hFFFFBAAABAAABAAA)) 
    udma_wrapper_i_125
       (.I0(udma_wrapper_i_224_n_0),
        .I1(sel0[3]),
        .I2(sel0[2]),
        .I3(udma_wrapper_i_225_n_0),
        .I4(udma_wrapper_i_174_n_0),
        .I5(\tx_64.req_rid_reg[15]_0 [44]),
        .O(\s_axis_cq\.tdata [12]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF8F8F8)) 
    udma_wrapper_i_126
       (.I0(udma_wrapper_i_204_n_0),
        .I1(\tx_64.req_data_reg_n_0_[19] ),
        .I2(udma_wrapper_i_226_n_0),
        .I3(udma_wrapper_i_227_n_0),
        .I4(\tx_64.req_rid_reg[15]_0 [27]),
        .I5(udma_wrapper_i_228_n_0),
        .O(\s_axis_cq\.tdata [11]));
  (* SOFT_HLUTNM = "soft_lutpair2049" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    udma_wrapper_i_127
       (.I0(\tx_64.req_data_reg_n_0_[18] ),
        .I1(udma_wrapper_i_204_n_0),
        .I2(udma_wrapper_i_229_n_0),
        .O(\s_axis_cq\.tdata [10]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_128
       (.I0(udma_wrapper_i_230_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_len_reg_n_0_[9] ),
        .I3(\tx_64.req_data_reg_n_0_[17] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [9]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_129
       (.I0(udma_wrapper_i_231_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_len_reg_n_0_[8] ),
        .I3(\tx_64.req_data_reg_n_0_[16] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [8]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_130
       (.I0(udma_wrapper_i_232_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_len_reg_n_0_[7] ),
        .I3(\tx_64.req_data_reg_n_0_[31] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [7]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_131
       (.I0(udma_wrapper_i_233_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_len_reg_n_0_[6] ),
        .I3(\tx_64.req_data_reg_n_0_[30] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [6]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_132
       (.I0(udma_wrapper_i_234_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_len_reg_n_0_[5] ),
        .I3(\tx_64.req_data_reg_n_0_[29] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [5]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_133
       (.I0(udma_wrapper_i_235_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_len_reg_n_0_[4] ),
        .I3(\tx_64.req_data_reg_n_0_[28] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [4]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_134
       (.I0(udma_wrapper_i_236_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_len_reg_n_0_[3] ),
        .I3(\tx_64.req_data_reg_n_0_[27] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [3]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_135
       (.I0(udma_wrapper_i_237_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_len_reg_n_0_[2] ),
        .I3(\tx_64.req_data_reg_n_0_[26] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [2]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_136
       (.I0(udma_wrapper_i_238_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_len_reg_n_0_[1] ),
        .I3(\tx_64.req_data_reg_n_0_[25] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [1]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    udma_wrapper_i_137
       (.I0(udma_wrapper_i_239_n_0),
        .I1(udma_wrapper_i_184_n_0),
        .I2(\tx_64.req_len_reg_n_0_[0] ),
        .I3(\tx_64.req_data_reg_n_0_[24] ),
        .I4(udma_wrapper_i_204_n_0),
        .O(\s_axis_cq\.tdata [0]));
  (* SOFT_HLUTNM = "soft_lutpair2022" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    udma_wrapper_i_138
       (.I0(in130),
        .I1(user_reset_out),
        .I2(state),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(\tx_64.req_wr_reg_n_0 ),
        .O(\s_axis_cq\.tuser [4]));
  LUT6 #(
    .INIT(64'h00000C000000AAA0)) 
    udma_wrapper_i_139
       (.I0(\tx_64.req_fbe_reg_n_0_[3] ),
        .I1(\tx_64.req_wr_reg_n_0 ),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(in130),
        .O(\s_axis_cq\.tuser [3]));
  LUT6 #(
    .INIT(64'h00000C000000AAA0)) 
    udma_wrapper_i_140
       (.I0(\tx_64.req_fbe_reg_n_0_[2] ),
        .I1(\tx_64.req_wr_reg_n_0 ),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(in130),
        .O(\s_axis_cq\.tuser [2]));
  LUT6 #(
    .INIT(64'h00000C000000AAA0)) 
    udma_wrapper_i_141
       (.I0(\tx_64.req_fbe_reg_n_0_[1] ),
        .I1(\tx_64.req_wr_reg_n_0 ),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(in130),
        .O(\s_axis_cq\.tuser [1]));
  LUT6 #(
    .INIT(64'h00000C000000AAA0)) 
    udma_wrapper_i_142
       (.I0(\tx_64.req_fbe_reg_n_0_[0] ),
        .I1(\tx_64.req_wr_reg_n_0 ),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(user_reset_out),
        .I5(in130),
        .O(\s_axis_cq\.tuser [0]));
  LUT6 #(
    .INIT(64'h00000000FF004700)) 
    udma_wrapper_i_143
       (.I0(p_0_in22_in),
        .I1(in130),
        .I2(\tx_64.req_wr_reg_n_0 ),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(state),
        .I5(user_reset_out),
        .O(\s_axis_cq\.tlast ));
  (* SOFT_HLUTNM = "soft_lutpair2023" *) 
  LUT4 #(
    .INIT(16'h0032)) 
    udma_wrapper_i_144
       (.I0(state),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(in130),
        .O(\s_axis_cq\.tvalid ));
  LUT6 #(
    .INIT(64'h080808A808080808)) 
    udma_wrapper_i_174
       (.I0(udma_wrapper_i_257_n_0),
        .I1(req_4dw),
        .I2(in130),
        .I3(sel0[2]),
        .I4(sel0[3]),
        .I5(udma_wrapper_i_258_n_0),
        .O(udma_wrapper_i_174_n_0));
  LUT5 #(
    .INIT(32'h00000800)) 
    udma_wrapper_i_175
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(state),
        .I2(user_reset_out),
        .I3(p_0_in),
        .I4(in130),
        .O(udma_wrapper_i_175_n_0));
  LUT5 #(
    .INIT(32'hA8A8AAA8)) 
    udma_wrapper_i_176
       (.I0(udma_wrapper_i_259_n_0),
        .I1(sel0[3]),
        .I2(sel0[2]),
        .I3(sel0[0]),
        .I4(sel0[1]),
        .O(udma_wrapper_i_176_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_177
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [30]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[6] ),
        .I4(\tx_64.req_rid_reg[15]_0 [62]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_177_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_178
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [29]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[5] ),
        .I4(\tx_64.req_rid_reg[15]_0 [61]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_178_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_179
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [28]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[4] ),
        .I4(\tx_64.req_rid_reg[15]_0 [60]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_179_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_180
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [27]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[3] ),
        .I4(\tx_64.req_rid_reg[15]_0 [59]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_180_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_181
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [26]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[2] ),
        .I4(\tx_64.req_rid_reg[15]_0 [58]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_181_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_182
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [25]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[1] ),
        .I4(\tx_64.req_rid_reg[15]_0 [57]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_182_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_183
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [18]),
        .I2(udma_wrapper_i_260_n_0),
        .I3(\tx_64.req_bar_id_reg_n_0_[2] ),
        .I4(\tx_64.req_data_reg_n_0_[10] ),
        .I5(udma_wrapper_i_175_n_0),
        .O(udma_wrapper_i_183_n_0));
  LUT3 #(
    .INIT(8'h04)) 
    udma_wrapper_i_184
       (.I0(user_reset_out),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(state),
        .O(udma_wrapper_i_184_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_185
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [17]),
        .I2(udma_wrapper_i_260_n_0),
        .I3(\tx_64.req_bar_id_reg_n_0_[1] ),
        .I4(\tx_64.req_data_reg_n_0_[9] ),
        .I5(udma_wrapper_i_175_n_0),
        .O(udma_wrapper_i_185_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_186
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [16]),
        .I2(udma_wrapper_i_260_n_0),
        .I3(\tx_64.req_bar_id_reg_n_0_[0] ),
        .I4(\tx_64.req_data_reg_n_0_[8] ),
        .I5(udma_wrapper_i_175_n_0),
        .O(udma_wrapper_i_186_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_187
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [15]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[23] ),
        .I4(\tx_64.req_rid_reg[15]_0 [47]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_187_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_188
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [14]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[22] ),
        .I4(\tx_64.req_rid_reg[15]_0 [46]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_188_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_189
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [13]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[21] ),
        .I4(\tx_64.req_rid_reg[15]_0 [45]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_189_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_190
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [12]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[20] ),
        .I4(\tx_64.req_rid_reg[15]_0 [44]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_190_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_191
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [11]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[19] ),
        .I4(\tx_64.req_rid_reg[15]_0 [43]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_191_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_192
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [10]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[18] ),
        .I4(\tx_64.req_rid_reg[15]_0 [42]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_192_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_193
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [9]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[17] ),
        .I4(\tx_64.req_rid_reg[15]_0 [41]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_193_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_194
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [8]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[16] ),
        .I4(\tx_64.req_rid_reg[15]_0 [40]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_194_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_195
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [7]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[31] ),
        .I4(\tx_64.req_rid_reg[15]_0 [39]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_195_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_196
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [6]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[30] ),
        .I4(\tx_64.req_rid_reg[15]_0 [38]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_196_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_197
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [5]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[29] ),
        .I4(\tx_64.req_rid_reg[15]_0 [37]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_197_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_198
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [4]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[28] ),
        .I4(\tx_64.req_rid_reg[15]_0 [36]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_198_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_199
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [3]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[27] ),
        .I4(\tx_64.req_rid_reg[15]_0 [35]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_199_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_200
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [2]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[26] ),
        .I4(\tx_64.req_rid_reg[15]_0 [34]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_200_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_201
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [1]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[25] ),
        .I4(\tx_64.req_rid_reg[15]_0 [33]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_201_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_202
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [0]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[24] ),
        .I4(\tx_64.req_rid_reg[15]_0 [32]),
        .I5(udma_wrapper_i_176_n_0),
        .O(udma_wrapper_i_202_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_203
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [63]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [31]),
        .I4(\tx_64.req_rid_reg[15]_0 [15]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_203_n_0));
  LUT5 #(
    .INIT(32'h08080008)) 
    udma_wrapper_i_204
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(state),
        .I2(user_reset_out),
        .I3(p_0_in),
        .I4(in130),
        .O(udma_wrapper_i_204_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_205
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [62]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [30]),
        .I4(\tx_64.req_rid_reg[15]_0 [14]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_205_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_206
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [61]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [29]),
        .I4(\tx_64.req_rid_reg[15]_0 [13]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_206_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_207
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [60]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [28]),
        .I4(\tx_64.req_rid_reg[15]_0 [12]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_207_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_208
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [59]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [27]),
        .I4(\tx_64.req_rid_reg[15]_0 [11]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_208_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_209
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [58]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [26]),
        .I4(\tx_64.req_rid_reg[15]_0 [10]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_209_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_210
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [57]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [25]),
        .I4(\tx_64.req_rid_reg[15]_0 [9]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_210_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_211
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [56]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [24]),
        .I4(\tx_64.req_rid_reg[15]_0 [8]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_211_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_212
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [55]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [23]),
        .I4(\tx_64.req_rid_reg[15]_0 [7]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_212_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_213
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [54]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [22]),
        .I4(\tx_64.req_rid_reg[15]_0 [6]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_213_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_214
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [53]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [21]),
        .I4(\tx_64.req_rid_reg[15]_0 [5]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_214_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_215
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [52]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [20]),
        .I4(\tx_64.req_rid_reg[15]_0 [4]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_215_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_216
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [51]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [19]),
        .I4(\tx_64.req_rid_reg[15]_0 [3]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_216_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_217
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [50]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [18]),
        .I4(\tx_64.req_rid_reg[15]_0 [2]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_217_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_218
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [49]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [17]),
        .I4(\tx_64.req_rid_reg[15]_0 [1]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_218_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_219
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [48]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [16]),
        .I4(\tx_64.req_rid_reg[15]_0 [0]),
        .I5(udma_wrapper_i_227_n_0),
        .O(udma_wrapper_i_219_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_220
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [47]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [31]),
        .I4(\tx_64.req_rid_reg[15]_0 [15]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_220_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2018" *) 
  LUT5 #(
    .INIT(32'h0000F400)) 
    udma_wrapper_i_221
       (.I0(p_0_in),
        .I1(state),
        .I2(in130),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(user_reset_out),
        .O(udma_wrapper_i_221_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_222
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [46]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [30]),
        .I4(\tx_64.req_rid_reg[15]_0 [14]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_222_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_223
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [45]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [29]),
        .I4(\tx_64.req_rid_reg[15]_0 [13]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_223_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_224
       (.I0(udma_wrapper_i_227_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [28]),
        .I2(udma_wrapper_i_261_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [12]),
        .I4(\tx_64.req_data_reg_n_0_[20] ),
        .I5(udma_wrapper_i_204_n_0),
        .O(udma_wrapper_i_224_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2022" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    udma_wrapper_i_225
       (.I0(state),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(in130),
        .O(udma_wrapper_i_225_n_0));
  LUT5 #(
    .INIT(32'hFF808080)) 
    udma_wrapper_i_226
       (.I0(sel0[3]),
        .I1(udma_wrapper_i_184_n_0),
        .I2(in130),
        .I3(\tx_64.req_rid_reg[15]_0 [11]),
        .I4(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_226_n_0));
  LUT5 #(
    .INIT(32'h00200000)) 
    udma_wrapper_i_227
       (.I0(in130),
        .I1(user_reset_out),
        .I2(state),
        .I3(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I4(sel0[3]),
        .O(udma_wrapper_i_227_n_0));
  LUT5 #(
    .INIT(32'hFF080808)) 
    udma_wrapper_i_228
       (.I0(\tx_64.req_wr_reg_n_0 ),
        .I1(udma_wrapper_i_184_n_0),
        .I2(in130),
        .I3(\tx_64.req_rid_reg[15]_0 [43]),
        .I4(udma_wrapper_i_174_n_0),
        .O(udma_wrapper_i_228_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_229
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [42]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [26]),
        .I4(\tx_64.req_rid_reg[15]_0 [10]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_229_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_230
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [41]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [25]),
        .I4(\tx_64.req_rid_reg[15]_0 [9]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_230_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_231
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [40]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [24]),
        .I4(\tx_64.req_rid_reg[15]_0 [8]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_231_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_232
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [39]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [23]),
        .I4(\tx_64.req_rid_reg[15]_0 [7]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_232_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_233
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [38]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [22]),
        .I4(\tx_64.req_rid_reg[15]_0 [6]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_233_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_234
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [37]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [21]),
        .I4(\tx_64.req_rid_reg[15]_0 [5]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_234_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_235
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [36]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [20]),
        .I4(\tx_64.req_rid_reg[15]_0 [4]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_235_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_236
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [35]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [19]),
        .I4(\tx_64.req_rid_reg[15]_0 [3]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_236_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_237
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [34]),
        .I2(udma_wrapper_i_227_n_0),
        .I3(\tx_64.req_rid_reg[15]_0 [18]),
        .I4(\tx_64.req_rid_reg[15]_0 [2]),
        .I5(udma_wrapper_i_261_n_0),
        .O(udma_wrapper_i_237_n_0));
  LUT6 #(
    .INIT(64'hFAEEAAAAAAEEAAAA)) 
    udma_wrapper_i_238
       (.I0(udma_wrapper_i_262_n_0),
        .I1(\tx_64.req_at_reg_n_0_[1] ),
        .I2(\tx_64.req_rid_reg[15]_0 [17]),
        .I3(in130),
        .I4(udma_wrapper_i_257_n_0),
        .I5(sel0[3]),
        .O(udma_wrapper_i_238_n_0));
  LUT6 #(
    .INIT(64'hFAEEAAAAAAEEAAAA)) 
    udma_wrapper_i_239
       (.I0(udma_wrapper_i_263_n_0),
        .I1(\tx_64.req_at_reg_n_0_[0] ),
        .I2(\tx_64.req_rid_reg[15]_0 [16]),
        .I3(in130),
        .I4(udma_wrapper_i_257_n_0),
        .I5(sel0[3]),
        .O(udma_wrapper_i_239_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2019" *) 
  LUT3 #(
    .INIT(8'h04)) 
    udma_wrapper_i_257
       (.I0(user_reset_out),
        .I1(state),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .O(udma_wrapper_i_257_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2048" *) 
  LUT2 #(
    .INIT(4'hB)) 
    udma_wrapper_i_258
       (.I0(sel0[1]),
        .I1(sel0[0]),
        .O(udma_wrapper_i_258_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2018" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    udma_wrapper_i_259
       (.I0(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I1(state),
        .I2(user_reset_out),
        .I3(in130),
        .O(udma_wrapper_i_259_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2023" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    udma_wrapper_i_260
       (.I0(state),
        .I1(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I2(user_reset_out),
        .I3(in130),
        .O(udma_wrapper_i_260_n_0));
  LUT5 #(
    .INIT(32'h1D110000)) 
    udma_wrapper_i_261
       (.I0(req_4dw),
        .I1(in130),
        .I2(sel0[3]),
        .I3(udma_wrapper_i_280_n_0),
        .I4(udma_wrapper_i_257_n_0),
        .O(udma_wrapper_i_261_n_0));
  LUT5 #(
    .INIT(32'h0C000808)) 
    udma_wrapper_i_262
       (.I0(\tx_64.req_rid_reg[15]_0 [33]),
        .I1(udma_wrapper_i_259_n_0),
        .I2(sel0[3]),
        .I3(\tx_64.req_rid_reg[15]_0 [1]),
        .I4(udma_wrapper_i_280_n_0),
        .O(udma_wrapper_i_262_n_0));
  LUT5 #(
    .INIT(32'h0C000808)) 
    udma_wrapper_i_263
       (.I0(\tx_64.req_rid_reg[15]_0 [32]),
        .I1(udma_wrapper_i_259_n_0),
        .I2(sel0[3]),
        .I3(\tx_64.req_rid_reg[15]_0 [0]),
        .I4(udma_wrapper_i_280_n_0),
        .O(udma_wrapper_i_263_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2048" *) 
  LUT3 #(
    .INIT(8'hAE)) 
    udma_wrapper_i_280
       (.I0(sel0[2]),
        .I1(sel0[0]),
        .I2(sel0[1]),
        .O(udma_wrapper_i_280_n_0));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_74
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [31]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[7] ),
        .I4(\tx_64.req_rid_reg[15]_0 [63]),
        .I5(udma_wrapper_i_176_n_0),
        .O(\s_axis_cq\.tdata [63]));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_75
       (.I0(\tx_64.req_attr_reg_n_0_[2] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_177_n_0),
        .O(\s_axis_cq\.tdata [62]));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_76
       (.I0(\tx_64.req_attr_reg_n_0_[1] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_178_n_0),
        .O(\s_axis_cq\.tdata [61]));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_77
       (.I0(\tx_64.req_attr_reg_n_0_[0] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_179_n_0),
        .O(\s_axis_cq\.tdata [60]));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_78
       (.I0(\tx_64.req_tc_reg_n_0_[2] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_180_n_0),
        .O(\s_axis_cq\.tdata [59]));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_79
       (.I0(\tx_64.req_tc_reg_n_0_[1] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_181_n_0),
        .O(\s_axis_cq\.tdata [58]));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_80
       (.I0(\tx_64.req_tc_reg_n_0_[0] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_182_n_0),
        .O(\s_axis_cq\.tdata [57]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_81
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [24]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[0] ),
        .I4(\tx_64.req_rid_reg[15]_0 [56]),
        .I5(udma_wrapper_i_176_n_0),
        .O(\s_axis_cq\.tdata [56]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_82
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [23]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[15] ),
        .I4(\tx_64.req_rid_reg[15]_0 [55]),
        .I5(udma_wrapper_i_176_n_0),
        .O(\s_axis_cq\.tdata [55]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_83
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [22]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[14] ),
        .I4(\tx_64.req_rid_reg[15]_0 [54]),
        .I5(udma_wrapper_i_176_n_0),
        .O(\s_axis_cq\.tdata [54]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_84
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [21]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[13] ),
        .I4(\tx_64.req_rid_reg[15]_0 [53]),
        .I5(udma_wrapper_i_176_n_0),
        .O(\s_axis_cq\.tdata [53]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_85
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [20]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[12] ),
        .I4(\tx_64.req_rid_reg[15]_0 [52]),
        .I5(udma_wrapper_i_176_n_0),
        .O(\s_axis_cq\.tdata [52]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    udma_wrapper_i_86
       (.I0(udma_wrapper_i_174_n_0),
        .I1(\tx_64.req_rid_reg[15]_0 [19]),
        .I2(udma_wrapper_i_175_n_0),
        .I3(\tx_64.req_data_reg_n_0_[11] ),
        .I4(\tx_64.req_rid_reg[15]_0 [51]),
        .I5(udma_wrapper_i_176_n_0),
        .O(\s_axis_cq\.tdata [51]));
  LUT6 #(
    .INIT(64'hFFEAEAEAEAEAEAEA)) 
    udma_wrapper_i_87
       (.I0(udma_wrapper_i_183_n_0),
        .I1(udma_wrapper_i_176_n_0),
        .I2(\tx_64.req_rid_reg[15]_0 [50]),
        .I3(\tx_64.req_type_reg_n_0_[2] ),
        .I4(udma_wrapper_i_184_n_0),
        .I5(in130),
        .O(\s_axis_cq\.tdata [50]));
  LUT6 #(
    .INIT(64'hFFEAEAEAEAEAEAEA)) 
    udma_wrapper_i_88
       (.I0(udma_wrapper_i_185_n_0),
        .I1(udma_wrapper_i_176_n_0),
        .I2(\tx_64.req_rid_reg[15]_0 [49]),
        .I3(\tx_64.req_type_reg_n_0_[1] ),
        .I4(udma_wrapper_i_184_n_0),
        .I5(in130),
        .O(\s_axis_cq\.tdata [49]));
  LUT6 #(
    .INIT(64'hFFEAEAEAEAEAEAEA)) 
    udma_wrapper_i_89
       (.I0(udma_wrapper_i_186_n_0),
        .I1(udma_wrapper_i_176_n_0),
        .I2(\tx_64.req_rid_reg[15]_0 [48]),
        .I3(\tx_64.req_type_reg_n_0_[0] ),
        .I4(udma_wrapper_i_184_n_0),
        .I5(in130),
        .O(\s_axis_cq\.tdata [48]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00200000)) 
    udma_wrapper_i_90
       (.I0(\tx_64.req_msg_code_reg_n_0_[7] ),
        .I1(state),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(user_reset_out),
        .I4(in130),
        .I5(udma_wrapper_i_187_n_0),
        .O(\s_axis_cq\.tdata [47]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00200000)) 
    udma_wrapper_i_91
       (.I0(\tx_64.req_msg_code_reg_n_0_[6] ),
        .I1(state),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(user_reset_out),
        .I4(in130),
        .I5(udma_wrapper_i_188_n_0),
        .O(\s_axis_cq\.tdata [46]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00200000)) 
    udma_wrapper_i_92
       (.I0(\tx_64.req_msg_code_reg_n_0_[5] ),
        .I1(state),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(user_reset_out),
        .I4(in130),
        .I5(udma_wrapper_i_189_n_0),
        .O(\s_axis_cq\.tdata [45]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00200000)) 
    udma_wrapper_i_93
       (.I0(\tx_64.req_msg_code_reg_n_0_[4] ),
        .I1(state),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(user_reset_out),
        .I4(in130),
        .I5(udma_wrapper_i_190_n_0),
        .O(\s_axis_cq\.tdata [44]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00200000)) 
    udma_wrapper_i_94
       (.I0(\tx_64.req_msg_code_reg_n_0_[3] ),
        .I1(state),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(user_reset_out),
        .I4(in130),
        .I5(udma_wrapper_i_191_n_0),
        .O(\s_axis_cq\.tdata [43]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00200000)) 
    udma_wrapper_i_95
       (.I0(\tx_64.req_msg_code_reg_n_0_[2] ),
        .I1(state),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(user_reset_out),
        .I4(in130),
        .I5(udma_wrapper_i_192_n_0),
        .O(\s_axis_cq\.tdata [42]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00200000)) 
    udma_wrapper_i_96
       (.I0(\tx_64.req_msg_code_reg_n_0_[1] ),
        .I1(state),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(user_reset_out),
        .I4(in130),
        .I5(udma_wrapper_i_193_n_0),
        .O(\s_axis_cq\.tdata [41]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00200000)) 
    udma_wrapper_i_97
       (.I0(\tx_64.req_msg_code_reg_n_0_[0] ),
        .I1(state),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(user_reset_out),
        .I4(in130),
        .I5(udma_wrapper_i_194_n_0),
        .O(\s_axis_cq\.tdata [40]));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_98
       (.I0(\tx_64.req_tag_reg_n_0_[7] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_195_n_0),
        .O(\s_axis_cq\.tdata [39]));
  LUT5 #(
    .INIT(32'hFFFF0020)) 
    udma_wrapper_i_99
       (.I0(\tx_64.req_tag_reg_n_0_[6] ),
        .I1(user_reset_out),
        .I2(\FSM_sequential_tx_64.state_reg[1]_0 ),
        .I3(state),
        .I4(udma_wrapper_i_196_n_0),
        .O(\s_axis_cq\.tdata [38]));
endmodule

module xdma_0_tx_mux
   (transfer_SM,
    s_axis_tx_tlast_reg_0,
    s_axis_tx_tvalid_reg_0,
    \s_axis_tx_tdata_reg[63]_0 ,
    \s_axis_tx_tkeep_reg[7]_0 ,
    s_axis_tx_req_tready,
    s_axis_tx_tgt_tready,
    \pcie_dma_in\.pcie_rq_seq_num_vld0 ,
    user_reset_out,
    \FSM_sequential_transfer_SM_reg[1]_0 ,
    user_clk_out,
    \FSM_sequential_transfer_SM_reg[0]_0 ,
    \s_axis_tx_tkeep_reg[7]_1 ,
    s_axis_tx_tlast_reg_1,
    s_axis_tx_tready,
    dmaFlag,
    s_axis_tx_tlast_i,
    s_axis_tx_tvalid_i,
    s_axis_tx_tdata_i,
    s_axis_tx_tkeep_i,
    s_axis_tx_tgt_tdata,
    s_axis_tx_req_tdata,
    s_axis_tx_tgt_tvalid,
    s_axis_tx_req_tvalid,
    s_axis_tx_req_tlast,
    \s_axis_tx_tdata_reg[47]_0 ,
    \s_axis_tx_tdata_reg[46]_0 ,
    \s_axis_tx_tdata_reg[45]_0 ,
    \s_axis_tx_tdata_reg[44]_0 ,
    \s_axis_tx_tdata_reg[43]_0 ,
    \s_axis_tx_tdata_reg[42]_0 ,
    \s_axis_tx_tdata_reg[41]_0 ,
    \s_axis_tx_tdata_reg[40]_0 ,
    \s_axis_tx_tdata_reg[39]_0 ,
    \s_axis_tx_tdata_reg[38]_0 ,
    \s_axis_tx_tdata_reg[37]_0 ,
    \s_axis_tx_tdata_reg[36]_0 ,
    \s_axis_tx_tdata_reg[35]_0 ,
    \s_axis_tx_tdata_reg[34]_0 ,
    \s_axis_tx_tdata_reg[31]_0 ,
    \s_axis_tx_tdata_reg[28]_0 ,
    \s_axis_tx_tdata_reg[27]_0 ,
    \s_axis_tx_tdata_reg[26]_0 ,
    \s_axis_tx_tdata_reg[25]_0 ,
    \s_axis_tx_tdata_reg[24]_0 ,
    \s_axis_tx_tdata_reg[23]_0 ,
    \s_axis_tx_tdata_reg[19]_0 ,
    \s_axis_tx_tdata_reg[17]_0 ,
    \s_axis_tx_tdata_reg[16]_0 ,
    \s_axis_tx_tdata_reg[15]_0 ,
    \s_axis_tx_tdata_reg[13]_0 ,
    \s_axis_tx_tdata_reg[1]_0 ,
    \s_axis_tx_tdata_reg[0]_0 );
  output [1:0]transfer_SM;
  output s_axis_tx_tlast_reg_0;
  output s_axis_tx_tvalid_reg_0;
  output [63:0]\s_axis_tx_tdata_reg[63]_0 ;
  output [0:0]\s_axis_tx_tkeep_reg[7]_0 ;
  output s_axis_tx_req_tready;
  output s_axis_tx_tgt_tready;
  output \pcie_dma_in\.pcie_rq_seq_num_vld0 ;
  input user_reset_out;
  input \FSM_sequential_transfer_SM_reg[1]_0 ;
  input user_clk_out;
  input \FSM_sequential_transfer_SM_reg[0]_0 ;
  input \s_axis_tx_tkeep_reg[7]_1 ;
  input s_axis_tx_tlast_reg_1;
  input s_axis_tx_tready;
  input dmaFlag;
  input s_axis_tx_tlast_i;
  input s_axis_tx_tvalid_i;
  input [63:0]s_axis_tx_tdata_i;
  input [0:0]s_axis_tx_tkeep_i;
  input [35:0]s_axis_tx_tgt_tdata;
  input [35:0]s_axis_tx_req_tdata;
  input s_axis_tx_tgt_tvalid;
  input s_axis_tx_req_tvalid;
  input s_axis_tx_req_tlast;
  input \s_axis_tx_tdata_reg[47]_0 ;
  input \s_axis_tx_tdata_reg[46]_0 ;
  input \s_axis_tx_tdata_reg[45]_0 ;
  input \s_axis_tx_tdata_reg[44]_0 ;
  input \s_axis_tx_tdata_reg[43]_0 ;
  input \s_axis_tx_tdata_reg[42]_0 ;
  input \s_axis_tx_tdata_reg[41]_0 ;
  input \s_axis_tx_tdata_reg[40]_0 ;
  input \s_axis_tx_tdata_reg[39]_0 ;
  input \s_axis_tx_tdata_reg[38]_0 ;
  input \s_axis_tx_tdata_reg[37]_0 ;
  input \s_axis_tx_tdata_reg[36]_0 ;
  input \s_axis_tx_tdata_reg[35]_0 ;
  input \s_axis_tx_tdata_reg[34]_0 ;
  input \s_axis_tx_tdata_reg[31]_0 ;
  input \s_axis_tx_tdata_reg[28]_0 ;
  input \s_axis_tx_tdata_reg[27]_0 ;
  input \s_axis_tx_tdata_reg[26]_0 ;
  input \s_axis_tx_tdata_reg[25]_0 ;
  input \s_axis_tx_tdata_reg[24]_0 ;
  input \s_axis_tx_tdata_reg[23]_0 ;
  input \s_axis_tx_tdata_reg[19]_0 ;
  input \s_axis_tx_tdata_reg[17]_0 ;
  input \s_axis_tx_tdata_reg[16]_0 ;
  input \s_axis_tx_tdata_reg[15]_0 ;
  input \s_axis_tx_tdata_reg[13]_0 ;
  input \s_axis_tx_tdata_reg[1]_0 ;
  input \s_axis_tx_tdata_reg[0]_0 ;

  wire \FSM_sequential_transfer_SM_reg[0]_0 ;
  wire \FSM_sequential_transfer_SM_reg[1]_0 ;
  wire dmaFlag;
  wire \pcie_dma_in\.pcie_rq_seq_num_vld0 ;
  wire [35:0]s_axis_tx_req_tdata;
  wire s_axis_tx_req_tlast;
  wire s_axis_tx_req_tready;
  wire s_axis_tx_req_tvalid;
  wire [63:0]s_axis_tx_tdata;
  wire \s_axis_tx_tdata[63]_i_1_n_0 ;
  wire \s_axis_tx_tdata[63]_i_2_n_0 ;
  wire [63:0]s_axis_tx_tdata_i;
  wire \s_axis_tx_tdata_reg[0]_0 ;
  wire \s_axis_tx_tdata_reg[10]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[11]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[12]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[13]_0 ;
  wire \s_axis_tx_tdata_reg[14]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[15]_0 ;
  wire \s_axis_tx_tdata_reg[16]_0 ;
  wire \s_axis_tx_tdata_reg[17]_0 ;
  wire \s_axis_tx_tdata_reg[18]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[19]_0 ;
  wire \s_axis_tx_tdata_reg[1]_0 ;
  wire \s_axis_tx_tdata_reg[20]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[21]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[22]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[23]_0 ;
  wire \s_axis_tx_tdata_reg[24]_0 ;
  wire \s_axis_tx_tdata_reg[25]_0 ;
  wire \s_axis_tx_tdata_reg[26]_0 ;
  wire \s_axis_tx_tdata_reg[27]_0 ;
  wire \s_axis_tx_tdata_reg[28]_0 ;
  wire \s_axis_tx_tdata_reg[29]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[2]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[30]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[31]_0 ;
  wire \s_axis_tx_tdata_reg[32]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[33]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[34]_0 ;
  wire \s_axis_tx_tdata_reg[35]_0 ;
  wire \s_axis_tx_tdata_reg[36]_0 ;
  wire \s_axis_tx_tdata_reg[37]_0 ;
  wire \s_axis_tx_tdata_reg[38]_0 ;
  wire \s_axis_tx_tdata_reg[39]_0 ;
  wire \s_axis_tx_tdata_reg[3]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[40]_0 ;
  wire \s_axis_tx_tdata_reg[41]_0 ;
  wire \s_axis_tx_tdata_reg[42]_0 ;
  wire \s_axis_tx_tdata_reg[43]_0 ;
  wire \s_axis_tx_tdata_reg[44]_0 ;
  wire \s_axis_tx_tdata_reg[45]_0 ;
  wire \s_axis_tx_tdata_reg[46]_0 ;
  wire \s_axis_tx_tdata_reg[47]_0 ;
  wire \s_axis_tx_tdata_reg[48]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[49]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[4]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[50]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[51]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[52]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[53]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[54]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[55]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[56]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[57]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[58]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[59]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[5]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[60]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[61]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[62]_i_1_n_0 ;
  wire [63:0]\s_axis_tx_tdata_reg[63]_0 ;
  wire \s_axis_tx_tdata_reg[63]_i_3_n_0 ;
  wire \s_axis_tx_tdata_reg[6]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[7]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[8]_i_1_n_0 ;
  wire \s_axis_tx_tdata_reg[9]_i_1_n_0 ;
  wire [35:0]s_axis_tx_tgt_tdata;
  wire s_axis_tx_tgt_tready;
  wire s_axis_tx_tgt_tvalid;
  wire [7:7]s_axis_tx_tkeep;
  wire [0:0]s_axis_tx_tkeep_i;
  wire [0:0]\s_axis_tx_tkeep_reg[7]_0 ;
  wire \s_axis_tx_tkeep_reg[7]_1 ;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tlast_i;
  wire s_axis_tx_tlast_reg_0;
  wire s_axis_tx_tlast_reg_1;
  wire s_axis_tx_tready;
  wire s_axis_tx_tvalid;
  wire s_axis_tx_tvalid_i;
  wire s_axis_tx_tvalid_i_1_n_0;
  wire s_axis_tx_tvalid_reg_0;
  wire [1:0]transfer_SM;
  wire user_clk_out;
  wire user_reset_out;

  (* FSM_ENCODED_STATES = "SM_IDLE:00,SM_TGT:01,SM_REQ:11,SM_MSIX:10" *) 
  FDRE \FSM_sequential_transfer_SM_reg[0] 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\FSM_sequential_transfer_SM_reg[0]_0 ),
        .Q(transfer_SM[0]),
        .R(user_reset_out));
  (* FSM_ENCODED_STATES = "SM_IDLE:00,SM_TGT:01,SM_REQ:11,SM_MSIX:10" *) 
  FDRE \FSM_sequential_transfer_SM_reg[1] 
       (.C(user_clk_out),
        .CE(1'b1),
        .D(\FSM_sequential_transfer_SM_reg[1]_0 ),
        .Q(transfer_SM[1]),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2056" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_1
       (.I0(s_axis_tx_tdata[63]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[63]),
        .O(\s_axis_tx_tdata_reg[63]_0 [63]));
  (* SOFT_HLUTNM = "soft_lutpair2060" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_10
       (.I0(s_axis_tx_tdata[54]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[54]),
        .O(\s_axis_tx_tdata_reg[63]_0 [54]));
  (* SOFT_HLUTNM = "soft_lutpair2061" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_11
       (.I0(s_axis_tx_tdata[53]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[53]),
        .O(\s_axis_tx_tdata_reg[63]_0 [53]));
  (* SOFT_HLUTNM = "soft_lutpair2061" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_12
       (.I0(s_axis_tx_tdata[52]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[52]),
        .O(\s_axis_tx_tdata_reg[63]_0 [52]));
  (* SOFT_HLUTNM = "soft_lutpair2062" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_13
       (.I0(s_axis_tx_tdata[51]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[51]),
        .O(\s_axis_tx_tdata_reg[63]_0 [51]));
  (* SOFT_HLUTNM = "soft_lutpair2062" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_14
       (.I0(s_axis_tx_tdata[50]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[50]),
        .O(\s_axis_tx_tdata_reg[63]_0 [50]));
  (* SOFT_HLUTNM = "soft_lutpair2063" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_15
       (.I0(s_axis_tx_tdata[49]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[49]),
        .O(\s_axis_tx_tdata_reg[63]_0 [49]));
  (* SOFT_HLUTNM = "soft_lutpair2063" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_16
       (.I0(s_axis_tx_tdata[48]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[48]),
        .O(\s_axis_tx_tdata_reg[63]_0 [48]));
  (* SOFT_HLUTNM = "soft_lutpair2064" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_17
       (.I0(s_axis_tx_tdata[47]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[47]),
        .O(\s_axis_tx_tdata_reg[63]_0 [47]));
  (* SOFT_HLUTNM = "soft_lutpair2064" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_18
       (.I0(s_axis_tx_tdata[46]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[46]),
        .O(\s_axis_tx_tdata_reg[63]_0 [46]));
  (* SOFT_HLUTNM = "soft_lutpair2065" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_19
       (.I0(s_axis_tx_tdata[45]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[45]),
        .O(\s_axis_tx_tdata_reg[63]_0 [45]));
  (* SOFT_HLUTNM = "soft_lutpair2056" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_2
       (.I0(s_axis_tx_tdata[62]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[62]),
        .O(\s_axis_tx_tdata_reg[63]_0 [62]));
  (* SOFT_HLUTNM = "soft_lutpair2065" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_20
       (.I0(s_axis_tx_tdata[44]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[44]),
        .O(\s_axis_tx_tdata_reg[63]_0 [44]));
  (* SOFT_HLUTNM = "soft_lutpair2066" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_21
       (.I0(s_axis_tx_tdata[43]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[43]),
        .O(\s_axis_tx_tdata_reg[63]_0 [43]));
  (* SOFT_HLUTNM = "soft_lutpair2066" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_22
       (.I0(s_axis_tx_tdata[42]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[42]),
        .O(\s_axis_tx_tdata_reg[63]_0 [42]));
  (* SOFT_HLUTNM = "soft_lutpair2067" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_23
       (.I0(s_axis_tx_tdata[41]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[41]),
        .O(\s_axis_tx_tdata_reg[63]_0 [41]));
  (* SOFT_HLUTNM = "soft_lutpair2067" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_24
       (.I0(s_axis_tx_tdata[40]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[40]),
        .O(\s_axis_tx_tdata_reg[63]_0 [40]));
  (* SOFT_HLUTNM = "soft_lutpair2068" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_25
       (.I0(s_axis_tx_tdata[39]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[39]),
        .O(\s_axis_tx_tdata_reg[63]_0 [39]));
  (* SOFT_HLUTNM = "soft_lutpair2068" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_26
       (.I0(s_axis_tx_tdata[38]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[38]),
        .O(\s_axis_tx_tdata_reg[63]_0 [38]));
  (* SOFT_HLUTNM = "soft_lutpair2069" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_27
       (.I0(s_axis_tx_tdata[37]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[37]),
        .O(\s_axis_tx_tdata_reg[63]_0 [37]));
  (* SOFT_HLUTNM = "soft_lutpair2069" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_28
       (.I0(s_axis_tx_tdata[36]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[36]),
        .O(\s_axis_tx_tdata_reg[63]_0 [36]));
  (* SOFT_HLUTNM = "soft_lutpair2070" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_29
       (.I0(s_axis_tx_tdata[35]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[35]),
        .O(\s_axis_tx_tdata_reg[63]_0 [35]));
  (* SOFT_HLUTNM = "soft_lutpair2057" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_3
       (.I0(s_axis_tx_tdata[61]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[61]),
        .O(\s_axis_tx_tdata_reg[63]_0 [61]));
  (* SOFT_HLUTNM = "soft_lutpair2070" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_30
       (.I0(s_axis_tx_tdata[34]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[34]),
        .O(\s_axis_tx_tdata_reg[63]_0 [34]));
  (* SOFT_HLUTNM = "soft_lutpair2071" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_31
       (.I0(s_axis_tx_tdata[33]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[33]),
        .O(\s_axis_tx_tdata_reg[63]_0 [33]));
  (* SOFT_HLUTNM = "soft_lutpair2071" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_32
       (.I0(s_axis_tx_tdata[32]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[32]),
        .O(\s_axis_tx_tdata_reg[63]_0 [32]));
  (* SOFT_HLUTNM = "soft_lutpair2072" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_33
       (.I0(s_axis_tx_tdata[31]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[31]),
        .O(\s_axis_tx_tdata_reg[63]_0 [31]));
  (* SOFT_HLUTNM = "soft_lutpair2054" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_34
       (.I0(s_axis_tx_tdata[30]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[30]),
        .O(\s_axis_tx_tdata_reg[63]_0 [30]));
  (* SOFT_HLUTNM = "soft_lutpair2055" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_35
       (.I0(s_axis_tx_tdata[29]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[29]),
        .O(\s_axis_tx_tdata_reg[63]_0 [29]));
  (* SOFT_HLUTNM = "soft_lutpair2072" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_36
       (.I0(s_axis_tx_tdata[28]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[28]),
        .O(\s_axis_tx_tdata_reg[63]_0 [28]));
  (* SOFT_HLUTNM = "soft_lutpair2073" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_37
       (.I0(s_axis_tx_tdata[27]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[27]),
        .O(\s_axis_tx_tdata_reg[63]_0 [27]));
  (* SOFT_HLUTNM = "soft_lutpair2073" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_38
       (.I0(s_axis_tx_tdata[26]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[26]),
        .O(\s_axis_tx_tdata_reg[63]_0 [26]));
  (* SOFT_HLUTNM = "soft_lutpair2074" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_39
       (.I0(s_axis_tx_tdata[25]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[25]),
        .O(\s_axis_tx_tdata_reg[63]_0 [25]));
  (* SOFT_HLUTNM = "soft_lutpair2057" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_4
       (.I0(s_axis_tx_tdata[60]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[60]),
        .O(\s_axis_tx_tdata_reg[63]_0 [60]));
  (* SOFT_HLUTNM = "soft_lutpair2074" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_40
       (.I0(s_axis_tx_tdata[24]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[24]),
        .O(\s_axis_tx_tdata_reg[63]_0 [24]));
  (* SOFT_HLUTNM = "soft_lutpair2075" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_41
       (.I0(s_axis_tx_tdata[23]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[23]),
        .O(\s_axis_tx_tdata_reg[63]_0 [23]));
  (* SOFT_HLUTNM = "soft_lutpair2075" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_42
       (.I0(s_axis_tx_tdata[22]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[22]),
        .O(\s_axis_tx_tdata_reg[63]_0 [22]));
  (* SOFT_HLUTNM = "soft_lutpair2076" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_43
       (.I0(s_axis_tx_tdata[21]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[21]),
        .O(\s_axis_tx_tdata_reg[63]_0 [21]));
  (* SOFT_HLUTNM = "soft_lutpair2076" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_44
       (.I0(s_axis_tx_tdata[20]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[20]),
        .O(\s_axis_tx_tdata_reg[63]_0 [20]));
  (* SOFT_HLUTNM = "soft_lutpair2077" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_45
       (.I0(s_axis_tx_tdata[19]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[19]),
        .O(\s_axis_tx_tdata_reg[63]_0 [19]));
  (* SOFT_HLUTNM = "soft_lutpair2077" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_46
       (.I0(s_axis_tx_tdata[18]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[18]),
        .O(\s_axis_tx_tdata_reg[63]_0 [18]));
  (* SOFT_HLUTNM = "soft_lutpair2078" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_47
       (.I0(s_axis_tx_tdata[17]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[17]),
        .O(\s_axis_tx_tdata_reg[63]_0 [17]));
  (* SOFT_HLUTNM = "soft_lutpair2078" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_48
       (.I0(s_axis_tx_tdata[16]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[16]),
        .O(\s_axis_tx_tdata_reg[63]_0 [16]));
  (* SOFT_HLUTNM = "soft_lutpair2054" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_49
       (.I0(s_axis_tx_tdata[15]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[15]),
        .O(\s_axis_tx_tdata_reg[63]_0 [15]));
  (* SOFT_HLUTNM = "soft_lutpair2058" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_5
       (.I0(s_axis_tx_tdata[59]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[59]),
        .O(\s_axis_tx_tdata_reg[63]_0 [59]));
  (* SOFT_HLUTNM = "soft_lutpair2079" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_50
       (.I0(s_axis_tx_tdata[14]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[14]),
        .O(\s_axis_tx_tdata_reg[63]_0 [14]));
  (* SOFT_HLUTNM = "soft_lutpair2079" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_51
       (.I0(s_axis_tx_tdata[13]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[13]),
        .O(\s_axis_tx_tdata_reg[63]_0 [13]));
  (* SOFT_HLUTNM = "soft_lutpair2080" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_52
       (.I0(s_axis_tx_tdata[12]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[12]),
        .O(\s_axis_tx_tdata_reg[63]_0 [12]));
  (* SOFT_HLUTNM = "soft_lutpair2080" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_53
       (.I0(s_axis_tx_tdata[11]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[11]),
        .O(\s_axis_tx_tdata_reg[63]_0 [11]));
  (* SOFT_HLUTNM = "soft_lutpair2081" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_54
       (.I0(s_axis_tx_tdata[10]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[10]),
        .O(\s_axis_tx_tdata_reg[63]_0 [10]));
  (* SOFT_HLUTNM = "soft_lutpair2081" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_55
       (.I0(s_axis_tx_tdata[9]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[9]),
        .O(\s_axis_tx_tdata_reg[63]_0 [9]));
  (* SOFT_HLUTNM = "soft_lutpair2082" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_56
       (.I0(s_axis_tx_tdata[8]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[8]),
        .O(\s_axis_tx_tdata_reg[63]_0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair2082" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_57
       (.I0(s_axis_tx_tdata[7]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[7]),
        .O(\s_axis_tx_tdata_reg[63]_0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair2083" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_58
       (.I0(s_axis_tx_tdata[6]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[6]),
        .O(\s_axis_tx_tdata_reg[63]_0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair2083" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_59
       (.I0(s_axis_tx_tdata[5]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[5]),
        .O(\s_axis_tx_tdata_reg[63]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair2058" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_6
       (.I0(s_axis_tx_tdata[58]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[58]),
        .O(\s_axis_tx_tdata_reg[63]_0 [58]));
  (* SOFT_HLUTNM = "soft_lutpair2084" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_60
       (.I0(s_axis_tx_tdata[4]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[4]),
        .O(\s_axis_tx_tdata_reg[63]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair2084" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_61
       (.I0(s_axis_tx_tdata[3]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[3]),
        .O(\s_axis_tx_tdata_reg[63]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair2085" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_62
       (.I0(s_axis_tx_tdata[2]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[2]),
        .O(\s_axis_tx_tdata_reg[63]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2085" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_63
       (.I0(s_axis_tx_tdata[1]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[1]),
        .O(\s_axis_tx_tdata_reg[63]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2055" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_64
       (.I0(s_axis_tx_tdata[0]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[0]),
        .O(\s_axis_tx_tdata_reg[63]_0 [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_65
       (.I0(s_axis_tx_tkeep),
        .I1(dmaFlag),
        .I2(s_axis_tx_tkeep_i),
        .O(\s_axis_tx_tkeep_reg[7]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2053" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_66
       (.I0(s_axis_tx_tlast),
        .I1(dmaFlag),
        .I2(s_axis_tx_tlast_i),
        .O(s_axis_tx_tlast_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair2053" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_67
       (.I0(s_axis_tx_tvalid),
        .I1(dmaFlag),
        .I2(s_axis_tx_tvalid_i),
        .O(s_axis_tx_tvalid_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair2059" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_7
       (.I0(s_axis_tx_tdata[57]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[57]),
        .O(\s_axis_tx_tdata_reg[63]_0 [57]));
  (* SOFT_HLUTNM = "soft_lutpair2059" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_8
       (.I0(s_axis_tx_tdata[56]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[56]),
        .O(\s_axis_tx_tdata_reg[63]_0 [56]));
  (* SOFT_HLUTNM = "soft_lutpair2060" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    pcie2_ip_i_i_9
       (.I0(s_axis_tx_tdata[55]),
        .I1(dmaFlag),
        .I2(s_axis_tx_tdata_i[55]),
        .O(\s_axis_tx_tdata_reg[63]_0 [55]));
  LUT3 #(
    .INIT(8'h04)) 
    \s_axis_tx_tdata[63]_i_1 
       (.I0(user_reset_out),
        .I1(s_axis_tx_tready),
        .I2(transfer_SM[0]),
        .O(\s_axis_tx_tdata[63]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \s_axis_tx_tdata[63]_i_2 
       (.I0(s_axis_tx_tready),
        .I1(user_reset_out),
        .O(\s_axis_tx_tdata[63]_i_2_n_0 ));
  FDRE \s_axis_tx_tdata_reg[0] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[0]_0 ),
        .Q(s_axis_tx_tdata[0]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[10] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[10]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[10]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[10]_i_1 
       (.I0(s_axis_tx_tgt_tdata[8]),
        .I1(s_axis_tx_req_tdata[8]),
        .O(\s_axis_tx_tdata_reg[10]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[11] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[11]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[11]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[11]_i_1 
       (.I0(s_axis_tx_tgt_tdata[9]),
        .I1(s_axis_tx_req_tdata[9]),
        .O(\s_axis_tx_tdata_reg[11]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[12] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[12]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[12]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[12]_i_1 
       (.I0(s_axis_tx_tgt_tdata[10]),
        .I1(s_axis_tx_req_tdata[10]),
        .O(\s_axis_tx_tdata_reg[12]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[13] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[13]_0 ),
        .Q(s_axis_tx_tdata[13]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[14] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[14]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[14]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[14]_i_1 
       (.I0(s_axis_tx_tgt_tdata[11]),
        .I1(s_axis_tx_req_tdata[11]),
        .O(\s_axis_tx_tdata_reg[14]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[15] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[15]_0 ),
        .Q(s_axis_tx_tdata[15]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[16] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[16]_0 ),
        .Q(s_axis_tx_tdata[16]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[17] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[17]_0 ),
        .Q(s_axis_tx_tdata[17]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[18] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[18]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[18]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[18]_i_1 
       (.I0(s_axis_tx_tgt_tdata[12]),
        .I1(s_axis_tx_req_tdata[12]),
        .O(\s_axis_tx_tdata_reg[18]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[19] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[19]_0 ),
        .Q(s_axis_tx_tdata[19]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[1] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[1]_0 ),
        .Q(s_axis_tx_tdata[1]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[20] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[20]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[20]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[20]_i_1 
       (.I0(s_axis_tx_tgt_tdata[13]),
        .I1(s_axis_tx_req_tdata[13]),
        .O(\s_axis_tx_tdata_reg[20]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[21] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[21]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[21]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[21]_i_1 
       (.I0(s_axis_tx_tgt_tdata[14]),
        .I1(s_axis_tx_req_tdata[14]),
        .O(\s_axis_tx_tdata_reg[21]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[22] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[22]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[22]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[22]_i_1 
       (.I0(s_axis_tx_tgt_tdata[15]),
        .I1(s_axis_tx_req_tdata[15]),
        .O(\s_axis_tx_tdata_reg[22]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[23] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[23]_0 ),
        .Q(s_axis_tx_tdata[23]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[24] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[24]_0 ),
        .Q(s_axis_tx_tdata[24]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[25] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[25]_0 ),
        .Q(s_axis_tx_tdata[25]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[26] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[26]_0 ),
        .Q(s_axis_tx_tdata[26]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[27] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[27]_0 ),
        .Q(s_axis_tx_tdata[27]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[28] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[28]_0 ),
        .Q(s_axis_tx_tdata[28]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[29] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[29]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[29]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[29]_i_1 
       (.I0(s_axis_tx_tgt_tdata[16]),
        .I1(s_axis_tx_req_tdata[16]),
        .O(\s_axis_tx_tdata_reg[29]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[2] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[2]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[2]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[2]_i_1 
       (.I0(s_axis_tx_tgt_tdata[0]),
        .I1(s_axis_tx_req_tdata[0]),
        .O(\s_axis_tx_tdata_reg[2]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[30] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[30]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[30]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[30]_i_1 
       (.I0(s_axis_tx_tgt_tdata[17]),
        .I1(s_axis_tx_req_tdata[17]),
        .O(\s_axis_tx_tdata_reg[30]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[31] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[31]_0 ),
        .Q(s_axis_tx_tdata[31]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[32] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[32]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[32]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[32]_i_1 
       (.I0(s_axis_tx_tgt_tdata[18]),
        .I1(s_axis_tx_req_tdata[18]),
        .O(\s_axis_tx_tdata_reg[32]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[33] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[33]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[33]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[33]_i_1 
       (.I0(s_axis_tx_tgt_tdata[19]),
        .I1(s_axis_tx_req_tdata[19]),
        .O(\s_axis_tx_tdata_reg[33]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[34] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[34]_0 ),
        .Q(s_axis_tx_tdata[34]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[35] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[35]_0 ),
        .Q(s_axis_tx_tdata[35]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[36] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[36]_0 ),
        .Q(s_axis_tx_tdata[36]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[37] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[37]_0 ),
        .Q(s_axis_tx_tdata[37]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[38] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[38]_0 ),
        .Q(s_axis_tx_tdata[38]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[39] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[39]_0 ),
        .Q(s_axis_tx_tdata[39]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[3] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[3]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[3]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[3]_i_1 
       (.I0(s_axis_tx_tgt_tdata[1]),
        .I1(s_axis_tx_req_tdata[1]),
        .O(\s_axis_tx_tdata_reg[3]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[40] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[40]_0 ),
        .Q(s_axis_tx_tdata[40]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[41] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[41]_0 ),
        .Q(s_axis_tx_tdata[41]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[42] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[42]_0 ),
        .Q(s_axis_tx_tdata[42]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[43] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[43]_0 ),
        .Q(s_axis_tx_tdata[43]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[44] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[44]_0 ),
        .Q(s_axis_tx_tdata[44]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[45] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[45]_0 ),
        .Q(s_axis_tx_tdata[45]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[46] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[46]_0 ),
        .Q(s_axis_tx_tdata[46]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[47] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[47]_0 ),
        .Q(s_axis_tx_tdata[47]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE \s_axis_tx_tdata_reg[48] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[48]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[48]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[48]_i_1 
       (.I0(s_axis_tx_tgt_tdata[20]),
        .I1(s_axis_tx_req_tdata[20]),
        .O(\s_axis_tx_tdata_reg[48]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[49] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[49]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[49]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[49]_i_1 
       (.I0(s_axis_tx_tgt_tdata[21]),
        .I1(s_axis_tx_req_tdata[21]),
        .O(\s_axis_tx_tdata_reg[49]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[4] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[4]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[4]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[4]_i_1 
       (.I0(s_axis_tx_tgt_tdata[2]),
        .I1(s_axis_tx_req_tdata[2]),
        .O(\s_axis_tx_tdata_reg[4]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[50] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[50]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[50]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[50]_i_1 
       (.I0(s_axis_tx_tgt_tdata[22]),
        .I1(s_axis_tx_req_tdata[22]),
        .O(\s_axis_tx_tdata_reg[50]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[51] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[51]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[51]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[51]_i_1 
       (.I0(s_axis_tx_tgt_tdata[23]),
        .I1(s_axis_tx_req_tdata[23]),
        .O(\s_axis_tx_tdata_reg[51]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[52] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[52]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[52]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[52]_i_1 
       (.I0(s_axis_tx_tgt_tdata[24]),
        .I1(s_axis_tx_req_tdata[24]),
        .O(\s_axis_tx_tdata_reg[52]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[53] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[53]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[53]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[53]_i_1 
       (.I0(s_axis_tx_tgt_tdata[25]),
        .I1(s_axis_tx_req_tdata[25]),
        .O(\s_axis_tx_tdata_reg[53]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[54] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[54]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[54]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[54]_i_1 
       (.I0(s_axis_tx_tgt_tdata[26]),
        .I1(s_axis_tx_req_tdata[26]),
        .O(\s_axis_tx_tdata_reg[54]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[55] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[55]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[55]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[55]_i_1 
       (.I0(s_axis_tx_tgt_tdata[27]),
        .I1(s_axis_tx_req_tdata[27]),
        .O(\s_axis_tx_tdata_reg[55]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[56] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[56]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[56]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[56]_i_1 
       (.I0(s_axis_tx_tgt_tdata[28]),
        .I1(s_axis_tx_req_tdata[28]),
        .O(\s_axis_tx_tdata_reg[56]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[57] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[57]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[57]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[57]_i_1 
       (.I0(s_axis_tx_tgt_tdata[29]),
        .I1(s_axis_tx_req_tdata[29]),
        .O(\s_axis_tx_tdata_reg[57]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[58] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[58]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[58]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[58]_i_1 
       (.I0(s_axis_tx_tgt_tdata[30]),
        .I1(s_axis_tx_req_tdata[30]),
        .O(\s_axis_tx_tdata_reg[58]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[59] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[59]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[59]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[59]_i_1 
       (.I0(s_axis_tx_tgt_tdata[31]),
        .I1(s_axis_tx_req_tdata[31]),
        .O(\s_axis_tx_tdata_reg[59]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[5] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[5]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[5]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[5]_i_1 
       (.I0(s_axis_tx_tgt_tdata[3]),
        .I1(s_axis_tx_req_tdata[3]),
        .O(\s_axis_tx_tdata_reg[5]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[60] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[60]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[60]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[60]_i_1 
       (.I0(s_axis_tx_tgt_tdata[32]),
        .I1(s_axis_tx_req_tdata[32]),
        .O(\s_axis_tx_tdata_reg[60]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[61] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[61]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[61]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[61]_i_1 
       (.I0(s_axis_tx_tgt_tdata[33]),
        .I1(s_axis_tx_req_tdata[33]),
        .O(\s_axis_tx_tdata_reg[61]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[62] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[62]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[62]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[62]_i_1 
       (.I0(s_axis_tx_tgt_tdata[34]),
        .I1(s_axis_tx_req_tdata[34]),
        .O(\s_axis_tx_tdata_reg[62]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[63] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[63]_i_3_n_0 ),
        .Q(s_axis_tx_tdata[63]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[63]_i_3 
       (.I0(s_axis_tx_tgt_tdata[35]),
        .I1(s_axis_tx_req_tdata[35]),
        .O(\s_axis_tx_tdata_reg[63]_i_3_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[6] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[6]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[6]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[6]_i_1 
       (.I0(s_axis_tx_tgt_tdata[4]),
        .I1(s_axis_tx_req_tdata[4]),
        .O(\s_axis_tx_tdata_reg[6]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[7] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[7]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[7]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[7]_i_1 
       (.I0(s_axis_tx_tgt_tdata[5]),
        .I1(s_axis_tx_req_tdata[5]),
        .O(\s_axis_tx_tdata_reg[7]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[8] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[8]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[8]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[8]_i_1 
       (.I0(s_axis_tx_tgt_tdata[6]),
        .I1(s_axis_tx_req_tdata[6]),
        .O(\s_axis_tx_tdata_reg[8]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tdata_reg[9] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tdata_reg[9]_i_1_n_0 ),
        .Q(s_axis_tx_tdata[9]),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  MUXF7 \s_axis_tx_tdata_reg[9]_i_1 
       (.I0(s_axis_tx_tgt_tdata[7]),
        .I1(s_axis_tx_req_tdata[7]),
        .O(\s_axis_tx_tdata_reg[9]_i_1_n_0 ),
        .S(transfer_SM[1]));
  FDRE \s_axis_tx_tkeep_reg[7] 
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(\s_axis_tx_tkeep_reg[7]_1 ),
        .Q(s_axis_tx_tkeep),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  FDRE s_axis_tx_tlast_reg
       (.C(user_clk_out),
        .CE(\s_axis_tx_tdata[63]_i_2_n_0 ),
        .D(s_axis_tx_tlast_reg_1),
        .Q(s_axis_tx_tlast),
        .R(\s_axis_tx_tdata[63]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hE200FFFFE2000000)) 
    s_axis_tx_tvalid_i_1
       (.I0(s_axis_tx_tgt_tvalid),
        .I1(transfer_SM[1]),
        .I2(s_axis_tx_req_tvalid),
        .I3(transfer_SM[0]),
        .I4(s_axis_tx_tready),
        .I5(s_axis_tx_tvalid),
        .O(s_axis_tx_tvalid_i_1_n_0));
  FDRE s_axis_tx_tvalid_reg
       (.C(user_clk_out),
        .CE(1'b1),
        .D(s_axis_tx_tvalid_i_1_n_0),
        .Q(s_axis_tx_tvalid),
        .R(user_reset_out));
  (* SOFT_HLUTNM = "soft_lutpair2052" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    udma_wrapper_i_148
       (.I0(s_axis_tx_req_tlast),
        .I1(s_axis_tx_tready),
        .I2(transfer_SM[1]),
        .I3(transfer_SM[0]),
        .O(\pcie_dma_in\.pcie_rq_seq_num_vld0 ));
  LUT3 #(
    .INIT(8'h80)) 
    udma_wrapper_i_153
       (.I0(transfer_SM[0]),
        .I1(transfer_SM[1]),
        .I2(s_axis_tx_tready),
        .O(s_axis_tx_req_tready));
  (* SOFT_HLUTNM = "soft_lutpair2052" *) 
  LUT3 #(
    .INIT(8'h40)) 
    udma_wrapper_i_155
       (.I0(transfer_SM[1]),
        .I1(transfer_SM[0]),
        .I2(s_axis_tx_tready),
        .O(s_axis_tx_tgt_tready));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFO" *) 
module xdma_0_xdma_v4_1_29_GenericFIFO
   (D,
    wtlp_dat_vld_ff,
    Q,
    wtlp_dat_ren,
    SR,
    user_clk,
    \WrPtr_reg[0]_0 ,
    WrEn,
    \MemArray_reg[61] );
  output [63:0]D;
  input [0:0]wtlp_dat_vld_ff;
  input [63:0]Q;
  input wtlp_dat_ren;
  input [0:0]SR;
  input user_clk;
  input \WrPtr_reg[0]_0 ;
  input WrEn;
  input [63:0]\MemArray_reg[61] ;

  wire [63:0]D;
  wire [63:0]\MemArray_reg[61] ;
  wire MemArray_reg_0_7_0_5_n_0;
  wire MemArray_reg_0_7_0_5_n_1;
  wire MemArray_reg_0_7_0_5_n_2;
  wire MemArray_reg_0_7_0_5_n_3;
  wire MemArray_reg_0_7_0_5_n_4;
  wire MemArray_reg_0_7_0_5_n_5;
  wire MemArray_reg_0_7_12_17_n_0;
  wire MemArray_reg_0_7_12_17_n_1;
  wire MemArray_reg_0_7_12_17_n_2;
  wire MemArray_reg_0_7_12_17_n_3;
  wire MemArray_reg_0_7_12_17_n_4;
  wire MemArray_reg_0_7_12_17_n_5;
  wire MemArray_reg_0_7_18_23_n_0;
  wire MemArray_reg_0_7_18_23_n_1;
  wire MemArray_reg_0_7_18_23_n_2;
  wire MemArray_reg_0_7_18_23_n_3;
  wire MemArray_reg_0_7_18_23_n_4;
  wire MemArray_reg_0_7_18_23_n_5;
  wire MemArray_reg_0_7_24_29_n_0;
  wire MemArray_reg_0_7_24_29_n_1;
  wire MemArray_reg_0_7_24_29_n_2;
  wire MemArray_reg_0_7_24_29_n_3;
  wire MemArray_reg_0_7_24_29_n_4;
  wire MemArray_reg_0_7_24_29_n_5;
  wire MemArray_reg_0_7_30_35_n_0;
  wire MemArray_reg_0_7_30_35_n_1;
  wire MemArray_reg_0_7_30_35_n_2;
  wire MemArray_reg_0_7_30_35_n_3;
  wire MemArray_reg_0_7_30_35_n_4;
  wire MemArray_reg_0_7_30_35_n_5;
  wire MemArray_reg_0_7_36_41_n_0;
  wire MemArray_reg_0_7_36_41_n_1;
  wire MemArray_reg_0_7_36_41_n_2;
  wire MemArray_reg_0_7_36_41_n_3;
  wire MemArray_reg_0_7_36_41_n_4;
  wire MemArray_reg_0_7_36_41_n_5;
  wire MemArray_reg_0_7_42_47_n_0;
  wire MemArray_reg_0_7_42_47_n_1;
  wire MemArray_reg_0_7_42_47_n_2;
  wire MemArray_reg_0_7_42_47_n_3;
  wire MemArray_reg_0_7_42_47_n_4;
  wire MemArray_reg_0_7_42_47_n_5;
  wire MemArray_reg_0_7_48_53_n_0;
  wire MemArray_reg_0_7_48_53_n_1;
  wire MemArray_reg_0_7_48_53_n_2;
  wire MemArray_reg_0_7_48_53_n_3;
  wire MemArray_reg_0_7_48_53_n_4;
  wire MemArray_reg_0_7_48_53_n_5;
  wire MemArray_reg_0_7_54_59_n_0;
  wire MemArray_reg_0_7_54_59_n_1;
  wire MemArray_reg_0_7_54_59_n_2;
  wire MemArray_reg_0_7_54_59_n_3;
  wire MemArray_reg_0_7_54_59_n_4;
  wire MemArray_reg_0_7_54_59_n_5;
  wire MemArray_reg_0_7_60_65_n_0;
  wire MemArray_reg_0_7_60_65_n_1;
  wire MemArray_reg_0_7_60_65_n_2;
  wire MemArray_reg_0_7_60_65_n_3;
  wire MemArray_reg_0_7_60_65_n_4;
  wire MemArray_reg_0_7_60_65_n_5;
  wire MemArray_reg_0_7_6_11_n_0;
  wire MemArray_reg_0_7_6_11_n_1;
  wire MemArray_reg_0_7_6_11_n_2;
  wire MemArray_reg_0_7_6_11_n_3;
  wire MemArray_reg_0_7_6_11_n_4;
  wire MemArray_reg_0_7_6_11_n_5;
  wire [63:0]Q;
  wire [2:0]RdPtr;
  wire [2:0]RdPtr__0;
  wire [0:0]SR;
  wire WrEn;
  wire [2:0]WrPtr;
  wire [2:0]WrPtr__0;
  wire \WrPtr_reg[0]_0 ;
  wire user_clk;
  wire wtlp_dat_ren;
  wire [0:0]wtlp_dat_vld_ff;
  wire [1:0]NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair1627" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[0]_i_1 
       (.I0(MemArray_reg_0_7_0_5_n_1),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[0]),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair1632" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[10]_i_1 
       (.I0(MemArray_reg_0_7_6_11_n_5),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[10]),
        .O(D[10]));
  (* SOFT_HLUTNM = "soft_lutpair1647" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[11]_i_1 
       (.I0(MemArray_reg_0_7_6_11_n_4),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[11]),
        .O(D[11]));
  (* SOFT_HLUTNM = "soft_lutpair1626" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[12]_i_1 
       (.I0(MemArray_reg_0_7_12_17_n_1),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[12]),
        .O(D[12]));
  (* SOFT_HLUTNM = "soft_lutpair1646" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[13]_i_1 
       (.I0(MemArray_reg_0_7_12_17_n_0),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[13]),
        .O(D[13]));
  (* SOFT_HLUTNM = "soft_lutpair1621" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[14]_i_1 
       (.I0(MemArray_reg_0_7_12_17_n_3),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[14]),
        .O(D[14]));
  (* SOFT_HLUTNM = "soft_lutpair1637" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[15]_i_1 
       (.I0(MemArray_reg_0_7_12_17_n_2),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[15]),
        .O(D[15]));
  (* SOFT_HLUTNM = "soft_lutpair1631" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[16]_i_1 
       (.I0(MemArray_reg_0_7_12_17_n_5),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[16]),
        .O(D[16]));
  (* SOFT_HLUTNM = "soft_lutpair1646" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[17]_i_1 
       (.I0(MemArray_reg_0_7_12_17_n_4),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[17]),
        .O(D[17]));
  (* SOFT_HLUTNM = "soft_lutpair1626" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[18]_i_1 
       (.I0(MemArray_reg_0_7_18_23_n_1),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[18]),
        .O(D[18]));
  (* SOFT_HLUTNM = "soft_lutpair1645" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[19]_i_1 
       (.I0(MemArray_reg_0_7_18_23_n_0),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[19]),
        .O(D[19]));
  (* SOFT_HLUTNM = "soft_lutpair1648" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[1]_i_1 
       (.I0(MemArray_reg_0_7_0_5_n_0),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[1]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair1620" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[20]_i_1 
       (.I0(MemArray_reg_0_7_18_23_n_3),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[20]),
        .O(D[20]));
  (* SOFT_HLUTNM = "soft_lutpair1636" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[21]_i_1 
       (.I0(MemArray_reg_0_7_18_23_n_2),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[21]),
        .O(D[21]));
  (* SOFT_HLUTNM = "soft_lutpair1631" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[22]_i_1 
       (.I0(MemArray_reg_0_7_18_23_n_5),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[22]),
        .O(D[22]));
  (* SOFT_HLUTNM = "soft_lutpair1645" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[23]_i_1 
       (.I0(MemArray_reg_0_7_18_23_n_4),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[23]),
        .O(D[23]));
  (* SOFT_HLUTNM = "soft_lutpair1625" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[24]_i_1 
       (.I0(MemArray_reg_0_7_24_29_n_1),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[24]),
        .O(D[24]));
  (* SOFT_HLUTNM = "soft_lutpair1644" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[25]_i_1 
       (.I0(MemArray_reg_0_7_24_29_n_0),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[25]),
        .O(D[25]));
  (* SOFT_HLUTNM = "soft_lutpair1620" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[26]_i_1 
       (.I0(MemArray_reg_0_7_24_29_n_3),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[26]),
        .O(D[26]));
  (* SOFT_HLUTNM = "soft_lutpair1636" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[27]_i_1 
       (.I0(MemArray_reg_0_7_24_29_n_2),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[27]),
        .O(D[27]));
  (* SOFT_HLUTNM = "soft_lutpair1630" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[28]_i_1 
       (.I0(MemArray_reg_0_7_24_29_n_5),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[28]),
        .O(D[28]));
  (* SOFT_HLUTNM = "soft_lutpair1644" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[29]_i_1 
       (.I0(MemArray_reg_0_7_24_29_n_4),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[29]),
        .O(D[29]));
  (* SOFT_HLUTNM = "soft_lutpair1622" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[2]_i_1 
       (.I0(MemArray_reg_0_7_0_5_n_3),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[2]),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair1625" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[30]_i_1 
       (.I0(MemArray_reg_0_7_30_35_n_1),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[30]),
        .O(D[30]));
  (* SOFT_HLUTNM = "soft_lutpair1643" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[31]_i_1 
       (.I0(MemArray_reg_0_7_30_35_n_0),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[31]),
        .O(D[31]));
  (* SOFT_HLUTNM = "soft_lutpair1619" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[32]_i_1 
       (.I0(MemArray_reg_0_7_30_35_n_3),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[32]),
        .O(D[32]));
  (* SOFT_HLUTNM = "soft_lutpair1635" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[33]_i_1 
       (.I0(MemArray_reg_0_7_30_35_n_2),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[33]),
        .O(D[33]));
  (* SOFT_HLUTNM = "soft_lutpair1630" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[34]_i_1 
       (.I0(MemArray_reg_0_7_30_35_n_5),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[34]),
        .O(D[34]));
  (* SOFT_HLUTNM = "soft_lutpair1643" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[35]_i_1 
       (.I0(MemArray_reg_0_7_30_35_n_4),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[35]),
        .O(D[35]));
  (* SOFT_HLUTNM = "soft_lutpair1624" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[36]_i_1 
       (.I0(MemArray_reg_0_7_36_41_n_1),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[36]),
        .O(D[36]));
  (* SOFT_HLUTNM = "soft_lutpair1642" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[37]_i_1 
       (.I0(MemArray_reg_0_7_36_41_n_0),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[37]),
        .O(D[37]));
  (* SOFT_HLUTNM = "soft_lutpair1619" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[38]_i_1 
       (.I0(MemArray_reg_0_7_36_41_n_3),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[38]),
        .O(D[38]));
  (* SOFT_HLUTNM = "soft_lutpair1635" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[39]_i_1 
       (.I0(MemArray_reg_0_7_36_41_n_2),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[39]),
        .O(D[39]));
  (* SOFT_HLUTNM = "soft_lutpair1638" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[3]_i_1 
       (.I0(MemArray_reg_0_7_0_5_n_2),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[3]),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair1629" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[40]_i_1 
       (.I0(MemArray_reg_0_7_36_41_n_5),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[40]),
        .O(D[40]));
  (* SOFT_HLUTNM = "soft_lutpair1642" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[41]_i_1 
       (.I0(MemArray_reg_0_7_36_41_n_4),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[41]),
        .O(D[41]));
  (* SOFT_HLUTNM = "soft_lutpair1624" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[42]_i_1 
       (.I0(MemArray_reg_0_7_42_47_n_1),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[42]),
        .O(D[42]));
  (* SOFT_HLUTNM = "soft_lutpair1641" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[43]_i_1 
       (.I0(MemArray_reg_0_7_42_47_n_0),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[43]),
        .O(D[43]));
  (* SOFT_HLUTNM = "soft_lutpair1618" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[44]_i_1 
       (.I0(MemArray_reg_0_7_42_47_n_3),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[44]),
        .O(D[44]));
  (* SOFT_HLUTNM = "soft_lutpair1634" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[45]_i_1 
       (.I0(MemArray_reg_0_7_42_47_n_2),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[45]),
        .O(D[45]));
  (* SOFT_HLUTNM = "soft_lutpair1629" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[46]_i_1 
       (.I0(MemArray_reg_0_7_42_47_n_5),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[46]),
        .O(D[46]));
  (* SOFT_HLUTNM = "soft_lutpair1641" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[47]_i_1 
       (.I0(MemArray_reg_0_7_42_47_n_4),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[47]),
        .O(D[47]));
  (* SOFT_HLUTNM = "soft_lutpair1623" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[48]_i_1 
       (.I0(MemArray_reg_0_7_48_53_n_1),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[48]),
        .O(D[48]));
  (* SOFT_HLUTNM = "soft_lutpair1640" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[49]_i_1 
       (.I0(MemArray_reg_0_7_48_53_n_0),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[49]),
        .O(D[49]));
  (* SOFT_HLUTNM = "soft_lutpair1632" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[4]_i_1 
       (.I0(MemArray_reg_0_7_0_5_n_5),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[4]),
        .O(D[4]));
  (* SOFT_HLUTNM = "soft_lutpair1618" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[50]_i_1 
       (.I0(MemArray_reg_0_7_48_53_n_3),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[50]),
        .O(D[50]));
  (* SOFT_HLUTNM = "soft_lutpair1634" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[51]_i_1 
       (.I0(MemArray_reg_0_7_48_53_n_2),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[51]),
        .O(D[51]));
  (* SOFT_HLUTNM = "soft_lutpair1628" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[52]_i_1 
       (.I0(MemArray_reg_0_7_48_53_n_5),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[52]),
        .O(D[52]));
  (* SOFT_HLUTNM = "soft_lutpair1640" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[53]_i_1 
       (.I0(MemArray_reg_0_7_48_53_n_4),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[53]),
        .O(D[53]));
  (* SOFT_HLUTNM = "soft_lutpair1623" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[54]_i_1 
       (.I0(MemArray_reg_0_7_54_59_n_1),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[54]),
        .O(D[54]));
  (* SOFT_HLUTNM = "soft_lutpair1639" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[55]_i_1 
       (.I0(MemArray_reg_0_7_54_59_n_0),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[55]),
        .O(D[55]));
  (* SOFT_HLUTNM = "soft_lutpair1617" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[56]_i_1 
       (.I0(MemArray_reg_0_7_54_59_n_3),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[56]),
        .O(D[56]));
  (* SOFT_HLUTNM = "soft_lutpair1633" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[57]_i_1 
       (.I0(MemArray_reg_0_7_54_59_n_2),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[57]),
        .O(D[57]));
  (* SOFT_HLUTNM = "soft_lutpair1628" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[58]_i_1 
       (.I0(MemArray_reg_0_7_54_59_n_5),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[58]),
        .O(D[58]));
  (* SOFT_HLUTNM = "soft_lutpair1639" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[59]_i_1 
       (.I0(MemArray_reg_0_7_54_59_n_4),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[59]),
        .O(D[59]));
  (* SOFT_HLUTNM = "soft_lutpair1648" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[5]_i_1 
       (.I0(MemArray_reg_0_7_0_5_n_4),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[5]),
        .O(D[5]));
  (* SOFT_HLUTNM = "soft_lutpair1622" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[60]_i_1 
       (.I0(MemArray_reg_0_7_60_65_n_1),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[60]),
        .O(D[60]));
  (* SOFT_HLUTNM = "soft_lutpair1638" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[61]_i_1 
       (.I0(MemArray_reg_0_7_60_65_n_0),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[61]),
        .O(D[61]));
  (* SOFT_HLUTNM = "soft_lutpair1617" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[62]_i_1 
       (.I0(MemArray_reg_0_7_60_65_n_3),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[62]),
        .O(D[62]));
  (* SOFT_HLUTNM = "soft_lutpair1633" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[63]_i_1 
       (.I0(MemArray_reg_0_7_60_65_n_2),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[63]),
        .O(D[63]));
  (* SOFT_HLUTNM = "soft_lutpair1627" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[6]_i_1 
       (.I0(MemArray_reg_0_7_6_11_n_1),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[6]),
        .O(D[6]));
  (* SOFT_HLUTNM = "soft_lutpair1647" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[7]_i_1 
       (.I0(MemArray_reg_0_7_6_11_n_0),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[7]),
        .O(D[7]));
  (* SOFT_HLUTNM = "soft_lutpair1621" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[8]_i_1 
       (.I0(MemArray_reg_0_7_6_11_n_3),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[8]),
        .O(D[8]));
  (* SOFT_HLUTNM = "soft_lutpair1637" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \MemArray[9]_i_1 
       (.I0(MemArray_reg_0_7_6_11_n_2),
        .I1(wtlp_dat_vld_ff),
        .I2(Q[9]),
        .O(D[9]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "576" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_7_0_5
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(\MemArray_reg[61] [1:0]),
        .DIB(\MemArray_reg[61] [3:2]),
        .DIC(\MemArray_reg[61] [5:4]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_7_0_5_n_0,MemArray_reg_0_7_0_5_n_1}),
        .DOB({MemArray_reg_0_7_0_5_n_2,MemArray_reg_0_7_0_5_n_3}),
        .DOC({MemArray_reg_0_7_0_5_n_4,MemArray_reg_0_7_0_5_n_5}),
        .DOD(NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(WrEn));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "576" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_7_12_17
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(\MemArray_reg[61] [13:12]),
        .DIB(\MemArray_reg[61] [15:14]),
        .DIC(\MemArray_reg[61] [17:16]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_7_12_17_n_0,MemArray_reg_0_7_12_17_n_1}),
        .DOB({MemArray_reg_0_7_12_17_n_2,MemArray_reg_0_7_12_17_n_3}),
        .DOC({MemArray_reg_0_7_12_17_n_4,MemArray_reg_0_7_12_17_n_5}),
        .DOD(NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(WrEn));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "576" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_7_18_23
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(\MemArray_reg[61] [19:18]),
        .DIB(\MemArray_reg[61] [21:20]),
        .DIC(\MemArray_reg[61] [23:22]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_7_18_23_n_0,MemArray_reg_0_7_18_23_n_1}),
        .DOB({MemArray_reg_0_7_18_23_n_2,MemArray_reg_0_7_18_23_n_3}),
        .DOC({MemArray_reg_0_7_18_23_n_4,MemArray_reg_0_7_18_23_n_5}),
        .DOD(NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(WrEn));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "576" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_24_29" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M MemArray_reg_0_7_24_29
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(\MemArray_reg[61] [25:24]),
        .DIB(\MemArray_reg[61] [27:26]),
        .DIC(\MemArray_reg[61] [29:28]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_7_24_29_n_0,MemArray_reg_0_7_24_29_n_1}),
        .DOB({MemArray_reg_0_7_24_29_n_2,MemArray_reg_0_7_24_29_n_3}),
        .DOC({MemArray_reg_0_7_24_29_n_4,MemArray_reg_0_7_24_29_n_5}),
        .DOD(NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(WrEn));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "576" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_30_35" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M MemArray_reg_0_7_30_35
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(\MemArray_reg[61] [31:30]),
        .DIB(\MemArray_reg[61] [33:32]),
        .DIC(\MemArray_reg[61] [35:34]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_7_30_35_n_0,MemArray_reg_0_7_30_35_n_1}),
        .DOB({MemArray_reg_0_7_30_35_n_2,MemArray_reg_0_7_30_35_n_3}),
        .DOC({MemArray_reg_0_7_30_35_n_4,MemArray_reg_0_7_30_35_n_5}),
        .DOD(NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(WrEn));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "576" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_36_41" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M MemArray_reg_0_7_36_41
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(\MemArray_reg[61] [37:36]),
        .DIB(\MemArray_reg[61] [39:38]),
        .DIC(\MemArray_reg[61] [41:40]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_7_36_41_n_0,MemArray_reg_0_7_36_41_n_1}),
        .DOB({MemArray_reg_0_7_36_41_n_2,MemArray_reg_0_7_36_41_n_3}),
        .DOC({MemArray_reg_0_7_36_41_n_4,MemArray_reg_0_7_36_41_n_5}),
        .DOD(NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(WrEn));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "576" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_42_47" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M MemArray_reg_0_7_42_47
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(\MemArray_reg[61] [43:42]),
        .DIB(\MemArray_reg[61] [45:44]),
        .DIC(\MemArray_reg[61] [47:46]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_7_42_47_n_0,MemArray_reg_0_7_42_47_n_1}),
        .DOB({MemArray_reg_0_7_42_47_n_2,MemArray_reg_0_7_42_47_n_3}),
        .DOC({MemArray_reg_0_7_42_47_n_4,MemArray_reg_0_7_42_47_n_5}),
        .DOD(NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(WrEn));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "576" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_48_53" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M MemArray_reg_0_7_48_53
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(\MemArray_reg[61] [49:48]),
        .DIB(\MemArray_reg[61] [51:50]),
        .DIC(\MemArray_reg[61] [53:52]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_7_48_53_n_0,MemArray_reg_0_7_48_53_n_1}),
        .DOB({MemArray_reg_0_7_48_53_n_2,MemArray_reg_0_7_48_53_n_3}),
        .DOC({MemArray_reg_0_7_48_53_n_4,MemArray_reg_0_7_48_53_n_5}),
        .DOD(NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(WrEn));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "576" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_54_59" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M MemArray_reg_0_7_54_59
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(\MemArray_reg[61] [55:54]),
        .DIB(\MemArray_reg[61] [57:56]),
        .DIC(\MemArray_reg[61] [59:58]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_7_54_59_n_0,MemArray_reg_0_7_54_59_n_1}),
        .DOB({MemArray_reg_0_7_54_59_n_2,MemArray_reg_0_7_54_59_n_3}),
        .DOC({MemArray_reg_0_7_54_59_n_4,MemArray_reg_0_7_54_59_n_5}),
        .DOD(NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(WrEn));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "576" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_60_65" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M MemArray_reg_0_7_60_65
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(\MemArray_reg[61] [61:60]),
        .DIB(\MemArray_reg[61] [63:62]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_7_60_65_n_0,MemArray_reg_0_7_60_65_n_1}),
        .DOB({MemArray_reg_0_7_60_65_n_2,MemArray_reg_0_7_60_65_n_3}),
        .DOC({MemArray_reg_0_7_60_65_n_4,MemArray_reg_0_7_60_65_n_5}),
        .DOD(NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(WrEn));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "576" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_7_6_11
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(\MemArray_reg[61] [7:6]),
        .DIB(\MemArray_reg[61] [9:8]),
        .DIC(\MemArray_reg[61] [11:10]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_7_6_11_n_0,MemArray_reg_0_7_6_11_n_1}),
        .DOB({MemArray_reg_0_7_6_11_n_2,MemArray_reg_0_7_6_11_n_3}),
        .DOC({MemArray_reg_0_7_6_11_n_4,MemArray_reg_0_7_6_11_n_5}),
        .DOD(NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(WrEn));
  LUT2 #(
    .INIT(4'h6)) 
    \RdPtr[0]_i_1 
       (.I0(RdPtr[0]),
        .I1(wtlp_dat_ren),
        .O(RdPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1615" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \RdPtr[1]_i_1 
       (.I0(RdPtr[0]),
        .I1(wtlp_dat_ren),
        .I2(RdPtr[1]),
        .O(RdPtr__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1615" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \RdPtr[2]_i_1 
       (.I0(wtlp_dat_ren),
        .I1(RdPtr[0]),
        .I2(RdPtr[1]),
        .I3(RdPtr[2]),
        .O(RdPtr__0[2]));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[0]),
        .Q(RdPtr[0]),
        .R(SR));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(RdPtr[1]),
        .R(SR));
  FDRE \RdPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[2]),
        .Q(RdPtr[2]),
        .R(SR));
  LUT2 #(
    .INIT(4'h6)) 
    \WrPtr[0]_i_1 
       (.I0(WrPtr[0]),
        .I1(\WrPtr_reg[0]_0 ),
        .O(WrPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1616" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \WrPtr[1]_i_1 
       (.I0(WrPtr[0]),
        .I1(\WrPtr_reg[0]_0 ),
        .I2(WrPtr[1]),
        .O(WrPtr__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1616" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \WrPtr[2]_i_1 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(WrPtr[0]),
        .I2(WrPtr[1]),
        .I3(WrPtr[2]),
        .O(WrPtr__0[2]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[0]),
        .Q(WrPtr[0]),
        .R(SR));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[1]),
        .Q(WrPtr[1]),
        .R(SR));
  FDRE \WrPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[2]),
        .Q(WrPtr[2]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOAsync" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOAsync
   (empty_ff,
    almost_full_ff_reg_0,
    \Head_reg[18]_0 ,
    Q,
    \FifoCntrRd_reg[1]_0 ,
    \FifoCntrRd_reg[1]_1 ,
    \RdPtr_reg[0]_0 ,
    out,
    D,
    rreq_lbe,
    \rreq_head_info_ff_reg[1][len][3]_i_1_0 ,
    \rreq_head_info_ff_reg[1][fbe][2] ,
    \Head_reg[18]_1 ,
    \Head_reg[23]_0 ,
    \Head_reg[23]_1 ,
    \Head_reg[23]_2 ,
    \Head_reg[29]_0 ,
    \Head_reg[29]_1 ,
    \Head_reg[29]_2 ,
    \Head_reg[29]_3 ,
    O,
    \Head_reg[29]_4 ,
    \Head_reg[30]_0 ,
    \Head_reg[30]_1 ,
    \Head_reg[30]_2 ,
    A,
    \FifoCntrWr_reg[1]_0 ,
    \WrPtr_reg[0]_0 ,
    I13,
    user_clk,
    SR,
    rreq_head_ld_shf_0,
    \Head_reg[121]_0 ,
    \Head_reg[121]_1 ,
    Head0,
    \Head_reg[121]_2 ,
    tag_sel_ff0,
    \rreq_head_info_ff_reg[0][lbe][3] ,
    \rreq_head_info_ff_reg[0][fbe][2] ,
    \FifoCntrWr_reg[2]_0 ,
    payloadOut,
    \RdPtr_reg[0]_1 ,
    user_rst_n_3ff_reg,
    E,
    \FifoCntrRd_reg[1]_2 ,
    H2C_RRQ_RDY_IN0,
    \Head_reg[119]_0 ,
    \FifoCntrWr_reg[1]_1 );
  output empty_ff;
  output almost_full_ff_reg_0;
  output \Head_reg[18]_0 ;
  output [79:0]Q;
  output \FifoCntrRd_reg[1]_0 ;
  output [1:0]\FifoCntrRd_reg[1]_1 ;
  output \RdPtr_reg[0]_0 ;
  output [0:0]out;
  output [0:0]D;
  output [3:0]rreq_lbe;
  output \rreq_head_info_ff_reg[1][len][3]_i_1_0 ;
  output [1:0]\rreq_head_info_ff_reg[1][fbe][2] ;
  output [3:0]\Head_reg[18]_1 ;
  output \Head_reg[23]_0 ;
  output \Head_reg[23]_1 ;
  output \Head_reg[23]_2 ;
  output \Head_reg[29]_0 ;
  output \Head_reg[29]_1 ;
  output \Head_reg[29]_2 ;
  output \Head_reg[29]_3 ;
  output [0:0]O;
  output \Head_reg[29]_4 ;
  output [0:0]\Head_reg[30]_0 ;
  output \Head_reg[30]_1 ;
  output [10:0]\Head_reg[30]_2 ;
  output [10:0]A;
  output [1:0]\FifoCntrWr_reg[1]_0 ;
  output \WrPtr_reg[0]_0 ;
  output [0:0]I13;
  input user_clk;
  input [0:0]SR;
  input rreq_head_ld_shf_0;
  input \Head_reg[121]_0 ;
  input \Head_reg[121]_1 ;
  input [0:0]Head0;
  input \Head_reg[121]_2 ;
  input tag_sel_ff0;
  input [0:0]\rreq_head_info_ff_reg[0][lbe][3] ;
  input [1:0]\rreq_head_info_ff_reg[0][fbe][2] ;
  input \FifoCntrWr_reg[2]_0 ;
  input [0:0]payloadOut;
  input \RdPtr_reg[0]_1 ;
  input [0:0]user_rst_n_3ff_reg;
  input [0:0]E;
  input [0:0]\FifoCntrRd_reg[1]_2 ;
  input H2C_RRQ_RDY_IN0;
  input [91:0]\Head_reg[119]_0 ;
  input [0:0]\FifoCntrWr_reg[1]_1 ;

  wire [10:0]A;
  wire [0:0]D;
  wire [0:0]E;
  wire [2:2]FifoCntrRd;
  wire \FifoCntrRd[0]_i_1__9_n_0 ;
  wire \FifoCntrRd[2]_i_2__4_n_0 ;
  wire \FifoCntrRd_reg[1]_0 ;
  wire [1:0]\FifoCntrRd_reg[1]_1 ;
  wire [0:0]\FifoCntrRd_reg[1]_2 ;
  wire [2:2]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__11_n_0 ;
  wire \FifoCntrWr[2]_i_1__10_n_0 ;
  wire [1:0]\FifoCntrWr_reg[1]_0 ;
  wire [0:0]\FifoCntrWr_reg[1]_1 ;
  wire \FifoCntrWr_reg[2]_0 ;
  wire H2C_RRQ_RDY_IN0;
  wire [0:0]Head0;
  wire \Head[121]_i_1__1_n_0 ;
  wire [91:0]\Head_reg[119]_0 ;
  wire \Head_reg[121]_0 ;
  wire \Head_reg[121]_1 ;
  wire \Head_reg[121]_2 ;
  wire \Head_reg[18]_0 ;
  wire [3:0]\Head_reg[18]_1 ;
  wire \Head_reg[23]_0 ;
  wire \Head_reg[23]_1 ;
  wire \Head_reg[23]_2 ;
  wire \Head_reg[29]_0 ;
  wire \Head_reg[29]_1 ;
  wire \Head_reg[29]_2 ;
  wire \Head_reg[29]_3 ;
  wire \Head_reg[29]_4 ;
  wire [0:0]\Head_reg[30]_0 ;
  wire \Head_reg[30]_1 ;
  wire [10:0]\Head_reg[30]_2 ;
  wire [0:0]I13;
  wire [0:0]O;
  wire [79:0]Q;
  wire \RdPtr[0]_i_1_n_0 ;
  wire \RdPtr[1]_i_1__17_n_0 ;
  wire \RdPtr_reg[0]_0 ;
  wire \RdPtr_reg[0]_1 ;
  wire [0:0]SR;
  wire \WrPtr[0]_i_1_n_0 ;
  wire \WrPtr[1]_i_1_n_0 ;
  wire \WrPtr_reg[0]_0 ;
  wire almost_full_ff_i_1__1_n_0;
  wire almost_full_ff_reg_0;
  wire [30:18]arb_rrq_pay;
  wire \dma_pcie_rq/rreq_64blen0 ;
  wire empty_ff;
  wire empty_ff_i_1__15_n_0;
  wire [0:0]out;
  wire [121:121]p_0_in1_in;
  wire [0:0]payloadOut;
  wire \rreq_head_info_ff[1][fbe][2]_i_2_n_0 ;
  wire \rreq_head_info_ff[1][fbe][3]_i_3_n_0 ;
  wire \rreq_head_info_ff[1][fbe][3]_i_4_n_0 ;
  wire \rreq_head_info_ff[1][len][3]_i_3_n_0 ;
  wire \rreq_head_info_ff[1][len][3]_i_4_n_0 ;
  wire \rreq_head_info_ff[1][len][3]_i_5_n_0 ;
  wire \rreq_head_info_ff[1][rcb][4]_i_10_n_0 ;
  wire \rreq_head_info_ff[1][rcb][4]_i_5_n_0 ;
  wire \rreq_head_info_ff[1][rcb][4]_i_6_n_0 ;
  wire \rreq_head_info_ff[1][rcb][4]_i_7_n_0 ;
  wire \rreq_head_info_ff[1][rcb][4]_i_8_n_0 ;
  wire \rreq_head_info_ff[1][rcb][4]_i_9_n_0 ;
  wire [1:0]\rreq_head_info_ff_reg[0][fbe][2] ;
  wire [0:0]\rreq_head_info_ff_reg[0][lbe][3] ;
  wire \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_0 ;
  wire \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_1 ;
  wire \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_2 ;
  wire \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_3 ;
  wire \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_5 ;
  wire \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_6 ;
  wire \rreq_head_info_ff_reg[0][rcb][7]_i_4_n_7 ;
  wire [1:0]\rreq_head_info_ff_reg[1][fbe][2] ;
  wire \rreq_head_info_ff_reg[1][len][10]_i_1_n_2 ;
  wire \rreq_head_info_ff_reg[1][len][10]_i_1_n_3 ;
  wire \rreq_head_info_ff_reg[1][len][10]_i_3_n_0 ;
  wire \rreq_head_info_ff_reg[1][len][10]_i_3_n_1 ;
  wire \rreq_head_info_ff_reg[1][len][10]_i_3_n_2 ;
  wire \rreq_head_info_ff_reg[1][len][10]_i_3_n_3 ;
  wire \rreq_head_info_ff_reg[1][len][3]_i_1_0 ;
  wire \rreq_head_info_ff_reg[1][len][3]_i_1_n_0 ;
  wire \rreq_head_info_ff_reg[1][len][3]_i_1_n_1 ;
  wire \rreq_head_info_ff_reg[1][len][3]_i_1_n_2 ;
  wire \rreq_head_info_ff_reg[1][len][3]_i_1_n_3 ;
  wire \rreq_head_info_ff_reg[1][len][3]_i_2_n_0 ;
  wire \rreq_head_info_ff_reg[1][len][3]_i_2_n_1 ;
  wire \rreq_head_info_ff_reg[1][len][3]_i_2_n_2 ;
  wire \rreq_head_info_ff_reg[1][len][3]_i_2_n_3 ;
  wire \rreq_head_info_ff_reg[1][len][7]_i_1_n_0 ;
  wire \rreq_head_info_ff_reg[1][len][7]_i_1_n_1 ;
  wire \rreq_head_info_ff_reg[1][len][7]_i_1_n_2 ;
  wire \rreq_head_info_ff_reg[1][len][7]_i_1_n_3 ;
  wire \rreq_head_info_ff_reg[1][len][7]_i_2_n_0 ;
  wire \rreq_head_info_ff_reg[1][len][7]_i_2_n_1 ;
  wire \rreq_head_info_ff_reg[1][len][7]_i_2_n_2 ;
  wire \rreq_head_info_ff_reg[1][len][7]_i_2_n_3 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_0 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_1 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_2 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_3 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_4 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_5 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_6 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_2_n_7 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_0 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_1 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_2 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_3 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_4 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_5 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_6 ;
  wire \rreq_head_info_ff_reg[1][rcb][4]_i_4_n_7 ;
  wire rreq_head_ld_shf_0;
  wire [3:0]rreq_lbe;
  wire tag_sel_ff0;
  wire user_clk;
  wire [0:0]user_rst_n_3ff_reg;
  wire [3:0]\NLW_rreq_head_info_ff_reg[0][rcb][7]_i_5_CO_UNCONNECTED ;
  wire [3:1]\NLW_rreq_head_info_ff_reg[0][rcb][7]_i_5_O_UNCONNECTED ;
  wire [3:2]\NLW_rreq_head_info_ff_reg[1][len][10]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_rreq_head_info_ff_reg[1][len][10]_i_1_O_UNCONNECTED ;
  wire [3:0]\NLW_rreq_head_info_ff_reg[1][len][10]_i_2_CO_UNCONNECTED ;
  wire [3:1]\NLW_rreq_head_info_ff_reg[1][len][10]_i_2_O_UNCONNECTED ;
  wire [1:0]\NLW_rreq_head_info_ff_reg[1][len][3]_i_2_O_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair1383" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__9 
       (.I0(\FifoCntrRd_reg[1]_1 [0]),
        .O(\FifoCntrRd[0]_i_1__9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1383" *) 
  LUT5 #(
    .INIT(32'h666AAAA9)) 
    \FifoCntrRd[2]_i_2__4 
       (.I0(FifoCntrRd),
        .I1(\FifoCntrRd_reg[1]_1 [1]),
        .I2(payloadOut),
        .I3(\FifoCntrWr_reg[2]_0 ),
        .I4(\FifoCntrRd_reg[1]_1 [0]),
        .O(\FifoCntrRd[2]_i_2__4_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrRd[0]_i_1__9_n_0 ),
        .Q(\FifoCntrRd_reg[1]_1 [0]),
        .R(SR));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrRd_reg[1]_2 ),
        .Q(\FifoCntrRd_reg[1]_1 [1]),
        .R(SR));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrRd[2]_i_2__4_n_0 ),
        .Q(FifoCntrRd),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair1384" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__11 
       (.I0(\FifoCntrWr_reg[1]_0 [0]),
        .O(\FifoCntrWr[0]_i_1__11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1384" *) 
  LUT5 #(
    .INIT(32'h666AAAA9)) 
    \FifoCntrWr[2]_i_1__10 
       (.I0(FifoCntrWr),
        .I1(\FifoCntrWr_reg[1]_0 [1]),
        .I2(payloadOut),
        .I3(\FifoCntrWr_reg[2]_0 ),
        .I4(\FifoCntrWr_reg[1]_0 [0]),
        .O(\FifoCntrWr[2]_i_1__10_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[0]_i_1__11_n_0 ),
        .Q(\FifoCntrWr_reg[1]_0 [0]),
        .R(SR));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr_reg[1]_1 ),
        .Q(\FifoCntrWr_reg[1]_0 [1]),
        .R(SR));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[2]_i_1__10_n_0 ),
        .Q(FifoCntrWr),
        .R(SR));
  LUT5 #(
    .INIT(32'hFFFFFF01)) 
    \Head[121]_i_1__1 
       (.I0(FifoCntrRd),
        .I1(\FifoCntrRd_reg[1]_1 [1]),
        .I2(\FifoCntrRd_reg[1]_1 [0]),
        .I3(tag_sel_ff0),
        .I4(\FifoCntrRd_reg[1]_0 ),
        .O(\Head[121]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00220033F0F0F0F0)) 
    \Head[121]_i_2 
       (.I0(\Head_reg[121]_0 ),
        .I1(\Head_reg[121]_1 ),
        .I2(Head0),
        .I3(almost_full_ff_reg_0),
        .I4(\Head_reg[121]_2 ),
        .I5(\FifoCntrRd_reg[1]_0 ),
        .O(p_0_in1_in));
  FDRE \Head_reg[100] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [72]),
        .Q(Q[59]),
        .R(SR));
  FDRE \Head_reg[101] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [73]),
        .Q(Q[60]),
        .R(SR));
  FDRE \Head_reg[102] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [74]),
        .Q(Q[61]),
        .R(SR));
  FDRE \Head_reg[103] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [75]),
        .Q(Q[62]),
        .R(SR));
  FDRE \Head_reg[104] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [76]),
        .Q(Q[63]),
        .R(SR));
  FDRE \Head_reg[105] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [77]),
        .Q(Q[64]),
        .R(SR));
  FDRE \Head_reg[106] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [78]),
        .Q(Q[65]),
        .R(SR));
  FDRE \Head_reg[107] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [79]),
        .Q(Q[66]),
        .R(SR));
  FDRE \Head_reg[108] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [80]),
        .Q(Q[67]),
        .R(SR));
  FDRE \Head_reg[109] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [81]),
        .Q(Q[68]),
        .R(SR));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [2]),
        .Q(Q[2]),
        .R(SR));
  FDRE \Head_reg[110] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [82]),
        .Q(Q[69]),
        .R(SR));
  FDRE \Head_reg[111] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [83]),
        .Q(Q[70]),
        .R(SR));
  FDRE \Head_reg[112] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [84]),
        .Q(Q[71]),
        .R(SR));
  FDRE \Head_reg[113] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [85]),
        .Q(Q[72]),
        .R(SR));
  FDRE \Head_reg[114] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [86]),
        .Q(Q[73]),
        .R(SR));
  FDRE \Head_reg[115] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [87]),
        .Q(Q[74]),
        .R(SR));
  FDRE \Head_reg[116] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [88]),
        .Q(Q[75]),
        .R(SR));
  FDRE \Head_reg[117] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [89]),
        .Q(Q[76]),
        .R(SR));
  FDRE \Head_reg[118] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [90]),
        .Q(Q[77]),
        .R(SR));
  FDRE \Head_reg[119] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [91]),
        .Q(Q[78]),
        .R(SR));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [3]),
        .Q(Q[3]),
        .R(SR));
  FDRE \Head_reg[121] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(p_0_in1_in),
        .Q(Q[79]),
        .R(SR));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [4]),
        .Q(Q[4]),
        .R(SR));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [5]),
        .Q(Q[5]),
        .R(SR));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [6]),
        .Q(Q[6]),
        .R(SR));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [7]),
        .Q(Q[7]),
        .R(SR));
  FDRE \Head_reg[16] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [8]),
        .Q(Q[8]),
        .R(SR));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [9]),
        .Q(arb_rrq_pay[18]),
        .R(SR));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [10]),
        .Q(arb_rrq_pay[19]),
        .R(SR));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [11]),
        .Q(arb_rrq_pay[20]),
        .R(SR));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [12]),
        .Q(arb_rrq_pay[21]),
        .R(SR));
  FDRE \Head_reg[22] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [13]),
        .Q(arb_rrq_pay[22]),
        .R(SR));
  FDRE \Head_reg[23] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [14]),
        .Q(arb_rrq_pay[23]),
        .R(SR));
  FDRE \Head_reg[24] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [15]),
        .Q(arb_rrq_pay[24]),
        .R(SR));
  FDRE \Head_reg[25] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [16]),
        .Q(arb_rrq_pay[25]),
        .R(SR));
  FDRE \Head_reg[26] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [17]),
        .Q(arb_rrq_pay[26]),
        .R(SR));
  FDRE \Head_reg[27] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [18]),
        .Q(arb_rrq_pay[27]),
        .R(SR));
  FDRE \Head_reg[28] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [19]),
        .Q(arb_rrq_pay[28]),
        .R(SR));
  FDRE \Head_reg[29] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [20]),
        .Q(arb_rrq_pay[29]),
        .R(SR));
  FDRE \Head_reg[30] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [21]),
        .Q(arb_rrq_pay[30]),
        .R(SR));
  FDRE \Head_reg[46] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [22]),
        .Q(Q[9]),
        .R(SR));
  FDRE \Head_reg[47] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [23]),
        .Q(Q[10]),
        .R(SR));
  FDRE \Head_reg[48] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [24]),
        .Q(Q[11]),
        .R(SR));
  FDRE \Head_reg[49] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [25]),
        .Q(Q[12]),
        .R(SR));
  FDRE \Head_reg[50] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [26]),
        .Q(Q[13]),
        .R(SR));
  FDRE \Head_reg[51] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [27]),
        .Q(Q[14]),
        .R(SR));
  FDRE \Head_reg[56] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [28]),
        .Q(Q[15]),
        .R(SR));
  FDRE \Head_reg[57] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [29]),
        .Q(Q[16]),
        .R(SR));
  FDRE \Head_reg[58] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [30]),
        .Q(Q[17]),
        .R(SR));
  FDRE \Head_reg[59] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [31]),
        .Q(Q[18]),
        .R(SR));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [32]),
        .Q(Q[19]),
        .R(SR));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [33]),
        .Q(Q[20]),
        .R(SR));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [34]),
        .Q(Q[21]),
        .R(SR));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [35]),
        .Q(Q[22]),
        .R(SR));
  FDRE \Head_reg[64] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [36]),
        .Q(Q[23]),
        .R(SR));
  FDRE \Head_reg[65] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [37]),
        .Q(Q[24]),
        .R(SR));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [38]),
        .Q(Q[25]),
        .R(SR));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [39]),
        .Q(Q[26]),
        .R(SR));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [40]),
        .Q(Q[27]),
        .R(SR));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [41]),
        .Q(Q[28]),
        .R(SR));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [42]),
        .Q(Q[29]),
        .R(SR));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [43]),
        .Q(Q[30]),
        .R(SR));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [44]),
        .Q(Q[31]),
        .R(SR));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [45]),
        .Q(Q[32]),
        .R(SR));
  FDRE \Head_reg[74] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [46]),
        .Q(Q[33]),
        .R(SR));
  FDRE \Head_reg[75] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [47]),
        .Q(Q[34]),
        .R(SR));
  FDRE \Head_reg[76] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [48]),
        .Q(Q[35]),
        .R(SR));
  FDRE \Head_reg[77] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [49]),
        .Q(Q[36]),
        .R(SR));
  FDRE \Head_reg[78] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [50]),
        .Q(Q[37]),
        .R(SR));
  FDRE \Head_reg[79] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [51]),
        .Q(Q[38]),
        .R(SR));
  FDRE \Head_reg[80] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [52]),
        .Q(Q[39]),
        .R(SR));
  FDRE \Head_reg[81] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [53]),
        .Q(Q[40]),
        .R(SR));
  FDRE \Head_reg[82] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [54]),
        .Q(Q[41]),
        .R(SR));
  FDRE \Head_reg[83] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [55]),
        .Q(Q[42]),
        .R(SR));
  FDRE \Head_reg[84] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [56]),
        .Q(Q[43]),
        .R(SR));
  FDRE \Head_reg[85] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [57]),
        .Q(Q[44]),
        .R(SR));
  FDRE \Head_reg[86] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [58]),
        .Q(Q[45]),
        .R(SR));
  FDRE \Head_reg[87] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [59]),
        .Q(Q[46]),
        .R(SR));
  FDRE \Head_reg[88] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [60]),
        .Q(Q[47]),
        .R(SR));
  FDRE \Head_reg[89] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [61]),
        .Q(Q[48]),
        .R(SR));
  FDRE \Head_reg[8] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [0]),
        .Q(Q[0]),
        .R(SR));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [62]),
        .Q(Q[49]),
        .R(SR));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [63]),
        .Q(Q[50]),
        .R(SR));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [64]),
        .Q(Q[51]),
        .R(SR));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [65]),
        .Q(Q[52]),
        .R(SR));
  FDRE \Head_reg[94] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [66]),
        .Q(Q[53]),
        .R(SR));
  FDRE \Head_reg[95] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [67]),
        .Q(Q[54]),
        .R(SR));
  FDRE \Head_reg[96] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [68]),
        .Q(Q[55]),
        .R(SR));
  FDRE \Head_reg[97] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [69]),
        .Q(Q[56]),
        .R(SR));
  FDRE \Head_reg[98] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [70]),
        .Q(Q[57]),
        .R(SR));
  FDRE \Head_reg[99] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [71]),
        .Q(Q[58]),
        .R(SR));
  FDRE \Head_reg[9] 
       (.C(user_clk),
        .CE(\Head[121]_i_1__1_n_0 ),
        .D(\Head_reg[119]_0 [1]),
        .Q(Q[1]),
        .R(SR));
  LUT6 #(
    .INIT(64'h5555777F55554440)) 
    \RdPtr[0]_i_1 
       (.I0(\RdPtr_reg[0]_0 ),
        .I1(tag_sel_ff0),
        .I2(\FifoCntrRd_reg[1]_1 [1]),
        .I3(FifoCntrRd),
        .I4(\FifoCntrRd_reg[1]_0 ),
        .I5(\RdPtr_reg[0]_0 ),
        .O(\RdPtr[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0FF00FF01FE0FF00)) 
    \RdPtr[1]_i_1__17 
       (.I0(\FifoCntrRd_reg[1]_1 [1]),
        .I1(FifoCntrRd),
        .I2(\RdPtr_reg[0]_0 ),
        .I3(out),
        .I4(tag_sel_ff0),
        .I5(\FifoCntrRd_reg[1]_0 ),
        .O(\RdPtr[1]_i_1__17_n_0 ));
  LUT5 #(
    .INIT(32'h11100000)) 
    \RdPtr[1]_i_2__3 
       (.I0(\FifoCntrRd_reg[1]_1 [1]),
        .I1(FifoCntrRd),
        .I2(\FifoCntrWr_reg[2]_0 ),
        .I3(payloadOut),
        .I4(\RdPtr_reg[0]_1 ),
        .O(\FifoCntrRd_reg[1]_0 ));
  (* MAX_FANOUT = "128" *) 
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1_n_0 ),
        .Q(\RdPtr_reg[0]_0 ),
        .R(SR));
  (* MAX_FANOUT = "128" *) 
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[1]_i_1__17_n_0 ),
        .Q(out),
        .R(SR));
  LUT4 #(
    .INIT(16'h5754)) 
    \WrPtr[0]_i_1 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(H2C_RRQ_RDY_IN0),
        .I2(payloadOut),
        .I3(\WrPtr_reg[0]_0 ),
        .O(\WrPtr[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h666F6660)) 
    \WrPtr[1]_i_1 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(I13),
        .I2(H2C_RRQ_RDY_IN0),
        .I3(payloadOut),
        .I4(I13),
        .O(\WrPtr[1]_i_1_n_0 ));
  (* MAX_FANOUT = "128" *) 
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[0]_i_1_n_0 ),
        .Q(\WrPtr_reg[0]_0 ),
        .R(SR));
  (* MAX_FANOUT = "128" *) 
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[1]_i_1_n_0 ),
        .Q(I13),
        .R(SR));
  LUT3 #(
    .INIT(8'hF8)) 
    almost_full_ff_i_1__1
       (.I0(\FifoCntrWr_reg[1]_0 [0]),
        .I1(\FifoCntrWr_reg[1]_0 [1]),
        .I2(FifoCntrWr),
        .O(almost_full_ff_i_1__1_n_0));
  FDRE almost_full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(almost_full_ff_i_1__1_n_0),
        .Q(almost_full_ff_reg_0),
        .R(SR));
  LUT5 #(
    .INIT(32'h57555757)) 
    empty_ff_i_1__15
       (.I0(user_rst_n_3ff_reg),
        .I1(\FifoCntrRd_reg[1]_1 [1]),
        .I2(FifoCntrRd),
        .I3(tag_sel_ff0),
        .I4(\FifoCntrRd_reg[1]_1 [0]),
        .O(empty_ff_i_1__15_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__15_n_0),
        .Q(empty_ff),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h88888888BBBBB88B)) 
    \rreq_head_info_ff[0][fbe][1]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][fbe][2] [0]),
        .I1(rreq_head_ld_shf_0),
        .I2(arb_rrq_pay[18]),
        .I3(Q[15]),
        .I4(\rreq_head_info_ff[1][fbe][2]_i_2_n_0 ),
        .I5(Q[16]),
        .O(\rreq_head_info_ff_reg[1][fbe][2] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1381" *) 
  LUT5 #(
    .INIT(32'h88B8B8B8)) 
    \rreq_head_info_ff[0][fbe][2]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][fbe][2] [1]),
        .I1(rreq_head_ld_shf_0),
        .I2(\rreq_head_info_ff[1][fbe][2]_i_2_n_0 ),
        .I3(Q[15]),
        .I4(Q[16]),
        .O(\rreq_head_info_ff_reg[1][fbe][2] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1379" *) 
  LUT5 #(
    .INIT(32'hB88888B8)) 
    \rreq_head_info_ff[0][lbe][3]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][lbe][3] ),
        .I1(rreq_head_ld_shf_0),
        .I2(rreq_lbe[2]),
        .I3(Q[15]),
        .I4(arb_rrq_pay[18]),
        .O(D));
  LUT5 #(
    .INIT(32'h0000E77E)) 
    \rreq_head_info_ff[0][len][3]_i_2 
       (.I0(arb_rrq_pay[18]),
        .I1(Q[15]),
        .I2(Q[16]),
        .I3(arb_rrq_pay[19]),
        .I4(rreq_head_ld_shf_0),
        .O(\Head_reg[18]_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \rreq_head_info_ff[0][rcb][7]_i_3 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_5 ),
        .I1(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_4 ),
        .I2(\dma_pcie_rq/rreq_64blen0 ),
        .I3(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_5 ),
        .I4(\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_7 ),
        .I5(\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_6 ),
        .O(\Head_reg[29]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1385" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \rreq_head_info_ff[1][fbe][0]_i_1 
       (.I0(Q[16]),
        .I1(Q[15]),
        .O(\Head_reg[18]_1 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1385" *) 
  LUT4 #(
    .INIT(16'h00F9)) 
    \rreq_head_info_ff[1][fbe][1]_i_1 
       (.I0(arb_rrq_pay[18]),
        .I1(Q[15]),
        .I2(\rreq_head_info_ff[1][fbe][2]_i_2_n_0 ),
        .I3(Q[16]),
        .O(\Head_reg[18]_1 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1381" *) 
  LUT3 #(
    .INIT(8'h70)) 
    \rreq_head_info_ff[1][fbe][2]_i_1 
       (.I0(Q[15]),
        .I1(Q[16]),
        .I2(\rreq_head_info_ff[1][fbe][2]_i_2_n_0 ),
        .O(\Head_reg[18]_1 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1382" *) 
  LUT5 #(
    .INIT(32'h7D7D7DD7)) 
    \rreq_head_info_ff[1][fbe][2]_i_2 
       (.I0(\rreq_head_info_ff_reg[1][len][3]_i_1_0 ),
        .I1(arb_rrq_pay[19]),
        .I2(Q[16]),
        .I3(Q[15]),
        .I4(arb_rrq_pay[18]),
        .O(\rreq_head_info_ff[1][fbe][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1382" *) 
  LUT5 #(
    .INIT(32'h1881FFFF)) 
    \rreq_head_info_ff[1][fbe][3]_i_1 
       (.I0(arb_rrq_pay[18]),
        .I1(Q[15]),
        .I2(Q[16]),
        .I3(arb_rrq_pay[19]),
        .I4(\rreq_head_info_ff_reg[1][len][3]_i_1_0 ),
        .O(\Head_reg[18]_1 [3]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \rreq_head_info_ff[1][fbe][3]_i_2 
       (.I0(\rreq_head_info_ff[1][fbe][3]_i_3_n_0 ),
        .I1(\rreq_head_info_ff[1][fbe][3]_i_4_n_0 ),
        .I2(\Head_reg[30]_2 [0]),
        .I3(\Head_reg[30]_2 [1]),
        .I4(\Head_reg[30]_2 [2]),
        .O(\rreq_head_info_ff_reg[1][len][3]_i_1_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \rreq_head_info_ff[1][fbe][3]_i_3 
       (.I0(\Head_reg[30]_2 [6]),
        .I1(\Head_reg[30]_2 [5]),
        .I2(\Head_reg[30]_2 [4]),
        .I3(\Head_reg[30]_2 [3]),
        .O(\rreq_head_info_ff[1][fbe][3]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \rreq_head_info_ff[1][fbe][3]_i_4 
       (.I0(\Head_reg[30]_2 [10]),
        .I1(\Head_reg[30]_2 [9]),
        .I2(\Head_reg[30]_2 [8]),
        .I3(\Head_reg[30]_2 [7]),
        .O(\rreq_head_info_ff[1][fbe][3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rreq_head_info_ff[1][lbe][0]_i_1 
       (.I0(\rreq_head_info_ff_reg[1][len][3]_i_1_0 ),
        .O(rreq_lbe[0]));
  (* SOFT_HLUTNM = "soft_lutpair1380" *) 
  LUT5 #(
    .INIT(32'h00009FF9)) 
    \rreq_head_info_ff[1][lbe][1]_i_1 
       (.I0(arb_rrq_pay[18]),
        .I1(Q[15]),
        .I2(Q[16]),
        .I3(arb_rrq_pay[19]),
        .I4(\rreq_head_info_ff_reg[1][len][3]_i_1_0 ),
        .O(rreq_lbe[1]));
  (* SOFT_HLUTNM = "soft_lutpair1380" *) 
  LUT5 #(
    .INIT(32'h14141441)) 
    \rreq_head_info_ff[1][lbe][2]_i_1 
       (.I0(\rreq_head_info_ff_reg[1][len][3]_i_1_0 ),
        .I1(arb_rrq_pay[19]),
        .I2(Q[16]),
        .I3(Q[15]),
        .I4(arb_rrq_pay[18]),
        .O(rreq_lbe[2]));
  (* SOFT_HLUTNM = "soft_lutpair1379" *) 
  LUT3 #(
    .INIT(8'h82)) 
    \rreq_head_info_ff[1][lbe][3]_i_1 
       (.I0(rreq_lbe[2]),
        .I1(Q[15]),
        .I2(arb_rrq_pay[18]),
        .O(rreq_lbe[3]));
  LUT5 #(
    .INIT(32'h56959556)) 
    \rreq_head_info_ff[1][len][3]_i_3 
       (.I0(A[0]),
        .I1(arb_rrq_pay[18]),
        .I2(Q[15]),
        .I3(Q[16]),
        .I4(arb_rrq_pay[19]),
        .O(\rreq_head_info_ff[1][len][3]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \rreq_head_info_ff[1][len][3]_i_4 
       (.I0(arb_rrq_pay[19]),
        .I1(Q[16]),
        .O(\rreq_head_info_ff[1][len][3]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \rreq_head_info_ff[1][len][3]_i_5 
       (.I0(arb_rrq_pay[18]),
        .I1(Q[15]),
        .O(\rreq_head_info_ff[1][len][3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1386" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rreq_head_info_ff[1][rcb][0]_i_1 
       (.I0(\dma_pcie_rq/rreq_64blen0 ),
        .I1(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_5 ),
        .O(\Head_reg[23]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1386" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rreq_head_info_ff[1][rcb][1]_i_1 
       (.I0(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_5 ),
        .I1(\dma_pcie_rq/rreq_64blen0 ),
        .I2(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_4 ),
        .O(\Head_reg[23]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1378" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \rreq_head_info_ff[1][rcb][2]_i_1 
       (.I0(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_4 ),
        .I1(\dma_pcie_rq/rreq_64blen0 ),
        .I2(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_5 ),
        .I3(\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_7 ),
        .O(\Head_reg[23]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1378" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \rreq_head_info_ff[1][rcb][3]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_7 ),
        .I1(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_5 ),
        .I2(\dma_pcie_rq/rreq_64blen0 ),
        .I3(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_4 ),
        .I4(\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_6 ),
        .O(\Head_reg[29]_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \rreq_head_info_ff[1][rcb][4]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_5 ),
        .I1(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_4 ),
        .I2(\dma_pcie_rq/rreq_64blen0 ),
        .I3(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_5 ),
        .I4(\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_7 ),
        .I5(\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_6 ),
        .O(\Head_reg[29]_1 ));
  LUT2 #(
    .INIT(4'h6)) 
    \rreq_head_info_ff[1][rcb][4]_i_10 
       (.I0(arb_rrq_pay[18]),
        .I1(Q[15]),
        .O(\rreq_head_info_ff[1][rcb][4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \rreq_head_info_ff[1][rcb][4]_i_3 
       (.I0(\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_7 ),
        .I1(\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_6 ),
        .I2(\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_5 ),
        .I3(\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_4 ),
        .I4(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_6 ),
        .I5(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_7 ),
        .O(\dma_pcie_rq/rreq_64blen0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \rreq_head_info_ff[1][rcb][4]_i_5 
       (.I0(arb_rrq_pay[23]),
        .I1(Q[20]),
        .O(\rreq_head_info_ff[1][rcb][4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \rreq_head_info_ff[1][rcb][4]_i_6 
       (.I0(arb_rrq_pay[22]),
        .I1(Q[19]),
        .O(\rreq_head_info_ff[1][rcb][4]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \rreq_head_info_ff[1][rcb][4]_i_7 
       (.I0(arb_rrq_pay[21]),
        .I1(Q[18]),
        .O(\rreq_head_info_ff[1][rcb][4]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \rreq_head_info_ff[1][rcb][4]_i_8 
       (.I0(arb_rrq_pay[20]),
        .I1(Q[17]),
        .O(\rreq_head_info_ff[1][rcb][4]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \rreq_head_info_ff[1][rcb][4]_i_9 
       (.I0(arb_rrq_pay[19]),
        .I1(Q[16]),
        .O(\rreq_head_info_ff[1][rcb][4]_i_9_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \rreq_head_info_ff[1][rcb][5]_i_1 
       (.I0(\Head_reg[29]_3 ),
        .I1(O),
        .O(\Head_reg[29]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1387" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rreq_head_info_ff[1][rcb][6]_i_1 
       (.I0(O),
        .I1(\Head_reg[29]_3 ),
        .I2(\Head_reg[30]_0 ),
        .O(\Head_reg[29]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1387" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \rreq_head_info_ff[1][rcb][7]_i_2 
       (.I0(\Head_reg[30]_0 ),
        .I1(O),
        .I2(\Head_reg[29]_3 ),
        .O(\Head_reg[30]_1 ));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \rreq_head_info_ff_reg[0][rcb][7]_i_4 
       (.CI(\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_0 ),
        .CO({\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_0 ,\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_1 ,\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_2 ,\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({O,\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_5 ,\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_6 ,\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_7 }),
        .S(arb_rrq_pay[29:26]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \rreq_head_info_ff_reg[0][rcb][7]_i_5 
       (.CI(\rreq_head_info_ff_reg[0][rcb][7]_i_4_n_0 ),
        .CO(\NLW_rreq_head_info_ff_reg[0][rcb][7]_i_5_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_rreq_head_info_ff_reg[0][rcb][7]_i_5_O_UNCONNECTED [3:1],\Head_reg[30]_0 }),
        .S({1'b0,1'b0,1'b0,arb_rrq_pay[30]}));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \rreq_head_info_ff_reg[1][len][10]_i_1 
       (.CI(\rreq_head_info_ff_reg[1][len][7]_i_1_n_0 ),
        .CO({\NLW_rreq_head_info_ff_reg[1][len][10]_i_1_CO_UNCONNECTED [3:2],\rreq_head_info_ff_reg[1][len][10]_i_1_n_2 ,\rreq_head_info_ff_reg[1][len][10]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_rreq_head_info_ff_reg[1][len][10]_i_1_O_UNCONNECTED [3],\Head_reg[30]_2 [10:8]}),
        .S({1'b0,A[10:8]}));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \rreq_head_info_ff_reg[1][len][10]_i_2 
       (.CI(\rreq_head_info_ff_reg[1][len][10]_i_3_n_0 ),
        .CO(\NLW_rreq_head_info_ff_reg[1][len][10]_i_2_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_rreq_head_info_ff_reg[1][len][10]_i_2_O_UNCONNECTED [3:1],A[10]}),
        .S({1'b0,1'b0,1'b0,arb_rrq_pay[30]}));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \rreq_head_info_ff_reg[1][len][10]_i_3 
       (.CI(\rreq_head_info_ff_reg[1][len][7]_i_2_n_0 ),
        .CO({\rreq_head_info_ff_reg[1][len][10]_i_3_n_0 ,\rreq_head_info_ff_reg[1][len][10]_i_3_n_1 ,\rreq_head_info_ff_reg[1][len][10]_i_3_n_2 ,\rreq_head_info_ff_reg[1][len][10]_i_3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(A[9:6]),
        .S(arb_rrq_pay[29:26]));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \rreq_head_info_ff_reg[1][len][3]_i_1 
       (.CI(1'b0),
        .CO({\rreq_head_info_ff_reg[1][len][3]_i_1_n_0 ,\rreq_head_info_ff_reg[1][len][3]_i_1_n_1 ,\rreq_head_info_ff_reg[1][len][3]_i_1_n_2 ,\rreq_head_info_ff_reg[1][len][3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,A[0]}),
        .O(\Head_reg[30]_2 [3:0]),
        .S({A[3:1],\rreq_head_info_ff[1][len][3]_i_3_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \rreq_head_info_ff_reg[1][len][3]_i_2 
       (.CI(1'b0),
        .CO({\rreq_head_info_ff_reg[1][len][3]_i_2_n_0 ,\rreq_head_info_ff_reg[1][len][3]_i_2_n_1 ,\rreq_head_info_ff_reg[1][len][3]_i_2_n_2 ,\rreq_head_info_ff_reg[1][len][3]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,arb_rrq_pay[19:18]}),
        .O({A[1:0],\NLW_rreq_head_info_ff_reg[1][len][3]_i_2_O_UNCONNECTED [1:0]}),
        .S({arb_rrq_pay[21:20],\rreq_head_info_ff[1][len][3]_i_4_n_0 ,\rreq_head_info_ff[1][len][3]_i_5_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \rreq_head_info_ff_reg[1][len][7]_i_1 
       (.CI(\rreq_head_info_ff_reg[1][len][3]_i_1_n_0 ),
        .CO({\rreq_head_info_ff_reg[1][len][7]_i_1_n_0 ,\rreq_head_info_ff_reg[1][len][7]_i_1_n_1 ,\rreq_head_info_ff_reg[1][len][7]_i_1_n_2 ,\rreq_head_info_ff_reg[1][len][7]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\Head_reg[30]_2 [7:4]),
        .S(A[7:4]));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \rreq_head_info_ff_reg[1][len][7]_i_2 
       (.CI(\rreq_head_info_ff_reg[1][len][3]_i_2_n_0 ),
        .CO({\rreq_head_info_ff_reg[1][len][7]_i_2_n_0 ,\rreq_head_info_ff_reg[1][len][7]_i_2_n_1 ,\rreq_head_info_ff_reg[1][len][7]_i_2_n_2 ,\rreq_head_info_ff_reg[1][len][7]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(A[5:2]),
        .S(arb_rrq_pay[25:22]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \rreq_head_info_ff_reg[1][rcb][4]_i_2 
       (.CI(\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_0 ),
        .CO({\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_0 ,\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_1 ,\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_2 ,\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,arb_rrq_pay[23:22]}),
        .O({\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_4 ,\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_5 ,\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_6 ,\rreq_head_info_ff_reg[1][rcb][4]_i_2_n_7 }),
        .S({arb_rrq_pay[25:24],\rreq_head_info_ff[1][rcb][4]_i_5_n_0 ,\rreq_head_info_ff[1][rcb][4]_i_6_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \rreq_head_info_ff_reg[1][rcb][4]_i_4 
       (.CI(1'b0),
        .CO({\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_0 ,\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_1 ,\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_2 ,\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI(arb_rrq_pay[21:18]),
        .O({\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_4 ,\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_5 ,\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_6 ,\rreq_head_info_ff_reg[1][rcb][4]_i_4_n_7 }),
        .S({\rreq_head_info_ff[1][rcb][4]_i_7_n_0 ,\rreq_head_info_ff[1][rcb][4]_i_8_n_0 ,\rreq_head_info_ff[1][rcb][4]_i_9_n_0 ,\rreq_head_info_ff[1][rcb][4]_i_10_n_0 }));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOAsync" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOAsync_47
   (empty_ff_reg_0,
    almost_full_ff_reg_0,
    tlp_rdbt_len,
    Q,
    user_clk,
    SR,
    \WrPtr_reg[0]_0 ,
    DataOut,
    arb_rrq_rdy,
    \Head_reg[19]_0 ,
    user_rst_n_3ff_reg,
    S,
    \RdPtr_reg[0]_0 ,
    payloadOut);
  output empty_ff_reg_0;
  output almost_full_ff_reg_0;
  output [7:0]tlp_rdbt_len;
  output [66:0]Q;
  input user_clk;
  input [0:0]SR;
  input \WrPtr_reg[0]_0 ;
  input [75:0]DataOut;
  input arb_rrq_rdy;
  input \Head_reg[19]_0 ;
  input [0:0]user_rst_n_3ff_reg;
  input [2:0]S;
  input \RdPtr_reg[0]_0 ;
  input [75:0]payloadOut;

  wire [75:0]DataOut;
  wire [2:0]FifoCntrRd;
  wire \FifoCntrRd[0]_i_1__13_n_0 ;
  wire \FifoCntrRd[1]_i_1__12_n_0 ;
  wire \FifoCntrRd[2]_i_1__11_n_0 ;
  wire \FifoCntrRd[2]_i_2__7_n_0 ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__15_n_0 ;
  wire \FifoCntrWr[1]_i_1__14_n_0 ;
  wire \FifoCntrWr[2]_i_1__13_n_0 ;
  wire [119:18]Head0_0;
  wire Head1__2;
  wire \Head[119]_i_1__5_n_0 ;
  wire \Head_reg[19]_0 ;
  wire MemArray_reg_0_3_54_59_n_0;
  wire MemArray_reg_0_3_54_59_n_1;
  wire [66:0]Q;
  wire [1:0]RdPtr;
  wire \RdPtr[0]_i_1_n_0 ;
  wire \RdPtr[1]_i_1_n_0 ;
  wire RdPtr_reg0;
  wire \RdPtr_reg[0]_0 ;
  wire [2:0]S;
  wire [0:0]SR;
  wire [1:0]WrPtr;
  wire \WrPtr[0]_i_1__16_n_0 ;
  wire \WrPtr[1]_i_1__16_n_0 ;
  wire \WrPtr_reg[0]_0 ;
  wire almost_full_ff_i_1__5_n_0;
  wire almost_full_ff_reg_0;
  wire arb_rrq_rdy;
  wire empty_ff_i_1__19_n_0;
  wire empty_ff_reg_0;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_10_n_0;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_11_n_0;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_11_n_1;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_11_n_2;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_11_n_3;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_11_n_4;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_11_n_5;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_11_n_6;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_11_n_7;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_12_n_0;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_7_n_0;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_7_n_1;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_7_n_2;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_7_n_3;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_7_n_4;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_7_n_5;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_7_n_6;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_7_n_7;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_8_n_0;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_8_n_1;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_8_n_2;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_8_n_3;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_8_n_4;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_8_n_5;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_8_n_6;
  wire m_axi_arlenissueq_reg_0_15_0_5_i_8_n_7;
  wire m_axi_arlenissueq_reg_0_15_6_7_i_3_n_0;
  wire m_axi_arlenissueq_reg_0_15_6_7_i_4_n_0;
  wire [119:18]p_0_in1_in;
  wire p_3_in;
  wire [75:0]payloadOut;
  wire [7:0]tlp_rdbt_len;
  wire [11:3]tlpbytelength;
  wire user_clk;
  wire [0:0]user_rst_n_3ff_reg;
  wire [1:0]NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED;

  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__13 
       (.I0(FifoCntrRd[0]),
        .O(\FifoCntrRd[0]_i_1__13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair450" *) 
  LUT4 #(
    .INIT(16'hC396)) 
    \FifoCntrRd[1]_i_1__12 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[1]),
        .I3(almost_full_ff_reg_0),
        .O(\FifoCntrRd[1]_i_1__12_n_0 ));
  LUT4 #(
    .INIT(16'h11E1)) 
    \FifoCntrRd[2]_i_1__11 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(arb_rrq_rdy),
        .I3(empty_ff_reg_0),
        .O(\FifoCntrRd[2]_i_1__11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair450" *) 
  LUT5 #(
    .INIT(32'hFC03BD42)) 
    \FifoCntrRd[2]_i_2__7 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[2]),
        .I4(almost_full_ff_reg_0),
        .O(\FifoCntrRd[2]_i_2__7_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__11_n_0 ),
        .D(\FifoCntrRd[0]_i_1__13_n_0 ),
        .Q(FifoCntrRd[0]),
        .R(SR));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__11_n_0 ),
        .D(\FifoCntrRd[1]_i_1__12_n_0 ),
        .Q(FifoCntrRd[1]),
        .R(SR));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__11_n_0 ),
        .D(\FifoCntrRd[2]_i_2__7_n_0 ),
        .Q(FifoCntrRd[2]),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__15 
       (.I0(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair451" *) 
  LUT4 #(
    .INIT(16'hC396)) 
    \FifoCntrWr[1]_i_1__14 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(FifoCntrWr[0]),
        .I2(FifoCntrWr[1]),
        .I3(almost_full_ff_reg_0),
        .O(\FifoCntrWr[1]_i_1__14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair451" *) 
  LUT5 #(
    .INIT(32'hFC03BD42)) 
    \FifoCntrWr[2]_i_1__13 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(FifoCntrWr[0]),
        .I2(FifoCntrWr[1]),
        .I3(FifoCntrWr[2]),
        .I4(almost_full_ff_reg_0),
        .O(\FifoCntrWr[2]_i_1__13_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__11_n_0 ),
        .D(\FifoCntrWr[0]_i_1__15_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(SR));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__11_n_0 ),
        .D(\FifoCntrWr[1]_i_1__14_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(SR));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__11_n_0 ),
        .D(\FifoCntrWr[2]_i_1__13_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(SR));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[100]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[56]),
        .I3(Head0_0[100]),
        .I4(Head1__2),
        .O(p_0_in1_in[100]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[101]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[57]),
        .I3(Head0_0[101]),
        .I4(Head1__2),
        .O(p_0_in1_in[101]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[102]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[58]),
        .I3(Head0_0[102]),
        .I4(Head1__2),
        .O(p_0_in1_in[102]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[103]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[59]),
        .I3(Head0_0[103]),
        .I4(Head1__2),
        .O(p_0_in1_in[103]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[104]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[60]),
        .I3(Head0_0[104]),
        .I4(Head1__2),
        .O(p_0_in1_in[104]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[105]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[61]),
        .I3(Head0_0[105]),
        .I4(Head1__2),
        .O(p_0_in1_in[105]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[106]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[62]),
        .I3(Head0_0[106]),
        .I4(Head1__2),
        .O(p_0_in1_in[106]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[107]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[63]),
        .I3(Head0_0[107]),
        .I4(Head1__2),
        .O(p_0_in1_in[107]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[108]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[64]),
        .I3(Head0_0[108]),
        .I4(Head1__2),
        .O(p_0_in1_in[108]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[109]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[65]),
        .I3(Head0_0[109]),
        .I4(Head1__2),
        .O(p_0_in1_in[109]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[110]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[66]),
        .I3(Head0_0[110]),
        .I4(Head1__2),
        .O(p_0_in1_in[110]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[111]_i_1__6 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[67]),
        .I3(Head0_0[111]),
        .I4(Head1__2),
        .O(p_0_in1_in[111]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[112]_i_1__6 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[68]),
        .I3(Head0_0[112]),
        .I4(Head1__2),
        .O(p_0_in1_in[112]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[113]_i_1__5 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[69]),
        .I3(Head0_0[113]),
        .I4(Head1__2),
        .O(p_0_in1_in[113]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[114]_i_1__5 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[70]),
        .I3(Head0_0[114]),
        .I4(Head1__2),
        .O(p_0_in1_in[114]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[115]_i_1__5 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[71]),
        .I3(Head0_0[115]),
        .I4(Head1__2),
        .O(p_0_in1_in[115]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[116]_i_1__5 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[72]),
        .I3(Head0_0[116]),
        .I4(Head1__2),
        .O(p_0_in1_in[116]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[117]_i_1__5 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[73]),
        .I3(Head0_0[117]),
        .I4(Head1__2),
        .O(p_0_in1_in[117]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[118]_i_1__5 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[74]),
        .I3(Head0_0[118]),
        .I4(Head1__2),
        .O(p_0_in1_in[118]));
  LUT6 #(
    .INIT(64'hAEAEAEAEAEAEAEFF)) 
    \Head[119]_i_1__5 
       (.I0(Head1__2),
        .I1(arb_rrq_rdy),
        .I2(empty_ff_reg_0),
        .I3(FifoCntrRd[2]),
        .I4(FifoCntrRd[1]),
        .I5(FifoCntrRd[0]),
        .O(\Head[119]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[119]_i_2__2 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[75]),
        .I3(Head0_0[119]),
        .I4(Head1__2),
        .O(p_0_in1_in[119]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[18]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[0]),
        .I3(Head0_0[18]),
        .I4(Head1__2),
        .O(p_0_in1_in[18]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[19]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[1]),
        .I3(Head0_0[19]),
        .I4(Head1__2),
        .O(p_0_in1_in[19]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[20]_i_1__10 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[2]),
        .I3(Head0_0[20]),
        .I4(Head1__2),
        .O(p_0_in1_in[20]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[21]_i_1__10 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[3]),
        .I3(Head0_0[21]),
        .I4(Head1__2),
        .O(p_0_in1_in[21]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[22]_i_1__7 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[4]),
        .I3(Head0_0[22]),
        .I4(Head1__2),
        .O(p_0_in1_in[22]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[23]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[5]),
        .I3(Head0_0[23]),
        .I4(Head1__2),
        .O(p_0_in1_in[23]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[24]_i_1__7 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[6]),
        .I3(Head0_0[24]),
        .I4(Head1__2),
        .O(p_0_in1_in[24]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[25]_i_1__7 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[7]),
        .I3(Head0_0[25]),
        .I4(Head1__2),
        .O(p_0_in1_in[25]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[26]_i_1__7 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[8]),
        .I3(Head0_0[26]),
        .I4(Head1__2),
        .O(p_0_in1_in[26]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[27]_i_1__7 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[9]),
        .I3(Head0_0[27]),
        .I4(Head1__2),
        .O(p_0_in1_in[27]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[28]_i_1__7 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[10]),
        .I3(Head0_0[28]),
        .I4(Head1__2),
        .O(p_0_in1_in[28]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[29]_i_1__7 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[11]),
        .I3(Head0_0[29]),
        .I4(Head1__2),
        .O(p_0_in1_in[29]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[56]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[12]),
        .I3(Head0_0[56]),
        .I4(Head1__2),
        .O(p_0_in1_in[56]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[57]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[13]),
        .I3(Head0_0[57]),
        .I4(Head1__2),
        .O(p_0_in1_in[57]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[58]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[14]),
        .I3(Head0_0[58]),
        .I4(Head1__2),
        .O(p_0_in1_in[58]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[59]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[15]),
        .I3(Head0_0[59]),
        .I4(Head1__2),
        .O(p_0_in1_in[59]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[60]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[16]),
        .I3(Head0_0[60]),
        .I4(Head1__2),
        .O(p_0_in1_in[60]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[61]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[17]),
        .I3(Head0_0[61]),
        .I4(Head1__2),
        .O(p_0_in1_in[61]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[62]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[18]),
        .I3(Head0_0[62]),
        .I4(Head1__2),
        .O(p_0_in1_in[62]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[63]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[19]),
        .I3(Head0_0[63]),
        .I4(Head1__2),
        .O(p_0_in1_in[63]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[64]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[20]),
        .I3(Head0_0[64]),
        .I4(Head1__2),
        .O(p_0_in1_in[64]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[65]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[21]),
        .I3(Head0_0[65]),
        .I4(Head1__2),
        .O(p_0_in1_in[65]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[66]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[22]),
        .I3(Head0_0[66]),
        .I4(Head1__2),
        .O(p_0_in1_in[66]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[67]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[23]),
        .I3(Head0_0[67]),
        .I4(Head1__2),
        .O(p_0_in1_in[67]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[68]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[24]),
        .I3(Head0_0[68]),
        .I4(Head1__2),
        .O(p_0_in1_in[68]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[69]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[25]),
        .I3(Head0_0[69]),
        .I4(Head1__2),
        .O(p_0_in1_in[69]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[70]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[26]),
        .I3(Head0_0[70]),
        .I4(Head1__2),
        .O(p_0_in1_in[70]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[71]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[27]),
        .I3(Head0_0[71]),
        .I4(Head1__2),
        .O(p_0_in1_in[71]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[72]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[28]),
        .I3(Head0_0[72]),
        .I4(Head1__2),
        .O(p_0_in1_in[72]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[73]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[29]),
        .I3(Head0_0[73]),
        .I4(Head1__2),
        .O(p_0_in1_in[73]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[74]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[30]),
        .I3(Head0_0[74]),
        .I4(Head1__2),
        .O(p_0_in1_in[74]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[75]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[31]),
        .I3(Head0_0[75]),
        .I4(Head1__2),
        .O(p_0_in1_in[75]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[76]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[32]),
        .I3(Head0_0[76]),
        .I4(Head1__2),
        .O(p_0_in1_in[76]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[77]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[33]),
        .I3(Head0_0[77]),
        .I4(Head1__2),
        .O(p_0_in1_in[77]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[78]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[34]),
        .I3(Head0_0[78]),
        .I4(Head1__2),
        .O(p_0_in1_in[78]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[79]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[35]),
        .I3(Head0_0[79]),
        .I4(Head1__2),
        .O(p_0_in1_in[79]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[80]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[36]),
        .I3(Head0_0[80]),
        .I4(Head1__2),
        .O(p_0_in1_in[80]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[81]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[37]),
        .I3(Head0_0[81]),
        .I4(Head1__2),
        .O(p_0_in1_in[81]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[82]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[38]),
        .I3(Head0_0[82]),
        .I4(Head1__2),
        .O(p_0_in1_in[82]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[83]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[39]),
        .I3(Head0_0[83]),
        .I4(Head1__2),
        .O(p_0_in1_in[83]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[84]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[40]),
        .I3(Head0_0[84]),
        .I4(Head1__2),
        .O(p_0_in1_in[84]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[85]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[41]),
        .I3(Head0_0[85]),
        .I4(Head1__2),
        .O(p_0_in1_in[85]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[86]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[42]),
        .I3(Head0_0[86]),
        .I4(Head1__2),
        .O(p_0_in1_in[86]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[87]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[43]),
        .I3(Head0_0[87]),
        .I4(Head1__2),
        .O(p_0_in1_in[87]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[88]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[44]),
        .I3(Head0_0[88]),
        .I4(Head1__2),
        .O(p_0_in1_in[88]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[89]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[45]),
        .I3(Head0_0[89]),
        .I4(Head1__2),
        .O(p_0_in1_in[89]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[90]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[46]),
        .I3(Head0_0[90]),
        .I4(Head1__2),
        .O(p_0_in1_in[90]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[91]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[47]),
        .I3(Head0_0[91]),
        .I4(Head1__2),
        .O(p_0_in1_in[91]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[92]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[48]),
        .I3(Head0_0[92]),
        .I4(Head1__2),
        .O(p_0_in1_in[92]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[93]_i_1__9 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[49]),
        .I3(Head0_0[93]),
        .I4(Head1__2),
        .O(p_0_in1_in[93]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[94]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[50]),
        .I3(Head0_0[94]),
        .I4(Head1__2),
        .O(p_0_in1_in[94]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[95]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[51]),
        .I3(Head0_0[95]),
        .I4(Head1__2),
        .O(p_0_in1_in[95]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[96]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[52]),
        .I3(Head0_0[96]),
        .I4(Head1__2),
        .O(p_0_in1_in[96]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[97]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[53]),
        .I3(Head0_0[97]),
        .I4(Head1__2),
        .O(p_0_in1_in[97]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[98]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[54]),
        .I3(Head0_0[98]),
        .I4(Head1__2),
        .O(p_0_in1_in[98]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[99]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(DataOut[55]),
        .I3(Head0_0[99]),
        .I4(Head1__2),
        .O(p_0_in1_in[99]));
  FDRE \Head_reg[100] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[100]),
        .Q(Q[47]),
        .R(SR));
  FDRE \Head_reg[101] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[101]),
        .Q(Q[48]),
        .R(SR));
  FDRE \Head_reg[102] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[102]),
        .Q(Q[49]),
        .R(SR));
  FDRE \Head_reg[103] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[103]),
        .Q(Q[50]),
        .R(SR));
  FDRE \Head_reg[104] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[104]),
        .Q(Q[51]),
        .R(SR));
  FDRE \Head_reg[105] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[105]),
        .Q(Q[52]),
        .R(SR));
  FDRE \Head_reg[106] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[106]),
        .Q(Q[53]),
        .R(SR));
  FDRE \Head_reg[107] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[107]),
        .Q(Q[54]),
        .R(SR));
  FDRE \Head_reg[108] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[108]),
        .Q(Q[55]),
        .R(SR));
  FDRE \Head_reg[109] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[109]),
        .Q(Q[56]),
        .R(SR));
  FDRE \Head_reg[110] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[110]),
        .Q(Q[57]),
        .R(SR));
  FDRE \Head_reg[111] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[111]),
        .Q(Q[58]),
        .R(SR));
  FDRE \Head_reg[112] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[112]),
        .Q(Q[59]),
        .R(SR));
  FDRE \Head_reg[113] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[113]),
        .Q(Q[60]),
        .R(SR));
  FDRE \Head_reg[114] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[114]),
        .Q(Q[61]),
        .R(SR));
  FDRE \Head_reg[115] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[115]),
        .Q(Q[62]),
        .R(SR));
  FDRE \Head_reg[116] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[116]),
        .Q(Q[63]),
        .R(SR));
  FDRE \Head_reg[117] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[117]),
        .Q(Q[64]),
        .R(SR));
  FDRE \Head_reg[118] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[118]),
        .Q(Q[65]),
        .R(SR));
  FDRE \Head_reg[119] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[119]),
        .Q(Q[66]),
        .R(SR));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[18]),
        .Q(Q[0]),
        .R(SR));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[19]),
        .Q(Q[1]),
        .R(SR));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[20]),
        .Q(Q[2]),
        .R(SR));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[21]),
        .Q(tlpbytelength[3]),
        .R(SR));
  FDRE \Head_reg[22] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[22]),
        .Q(tlpbytelength[4]),
        .R(SR));
  FDRE \Head_reg[23] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[23]),
        .Q(tlpbytelength[5]),
        .R(SR));
  FDRE \Head_reg[24] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[24]),
        .Q(tlpbytelength[6]),
        .R(SR));
  FDRE \Head_reg[25] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[25]),
        .Q(tlpbytelength[7]),
        .R(SR));
  FDRE \Head_reg[26] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[26]),
        .Q(tlpbytelength[8]),
        .R(SR));
  FDRE \Head_reg[27] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[27]),
        .Q(tlpbytelength[9]),
        .R(SR));
  FDRE \Head_reg[28] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[28]),
        .Q(tlpbytelength[10]),
        .R(SR));
  FDRE \Head_reg[29] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[29]),
        .Q(tlpbytelength[11]),
        .R(SR));
  FDRE \Head_reg[56] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[56]),
        .Q(Q[3]),
        .R(SR));
  FDRE \Head_reg[57] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[57]),
        .Q(Q[4]),
        .R(SR));
  FDRE \Head_reg[58] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[58]),
        .Q(Q[5]),
        .R(SR));
  FDRE \Head_reg[59] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[59]),
        .Q(Q[6]),
        .R(SR));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[60]),
        .Q(Q[7]),
        .R(SR));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[61]),
        .Q(Q[8]),
        .R(SR));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[62]),
        .Q(Q[9]),
        .R(SR));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[63]),
        .Q(Q[10]),
        .R(SR));
  FDRE \Head_reg[64] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[64]),
        .Q(Q[11]),
        .R(SR));
  FDRE \Head_reg[65] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[65]),
        .Q(Q[12]),
        .R(SR));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[66]),
        .Q(Q[13]),
        .R(SR));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[67]),
        .Q(Q[14]),
        .R(SR));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[68]),
        .Q(Q[15]),
        .R(SR));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[69]),
        .Q(Q[16]),
        .R(SR));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[70]),
        .Q(Q[17]),
        .R(SR));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[71]),
        .Q(Q[18]),
        .R(SR));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[72]),
        .Q(Q[19]),
        .R(SR));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[73]),
        .Q(Q[20]),
        .R(SR));
  FDRE \Head_reg[74] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[74]),
        .Q(Q[21]),
        .R(SR));
  FDRE \Head_reg[75] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[75]),
        .Q(Q[22]),
        .R(SR));
  FDRE \Head_reg[76] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[76]),
        .Q(Q[23]),
        .R(SR));
  FDRE \Head_reg[77] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[77]),
        .Q(Q[24]),
        .R(SR));
  FDRE \Head_reg[78] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[78]),
        .Q(Q[25]),
        .R(SR));
  FDRE \Head_reg[79] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[79]),
        .Q(Q[26]),
        .R(SR));
  FDRE \Head_reg[80] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[80]),
        .Q(Q[27]),
        .R(SR));
  FDRE \Head_reg[81] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[81]),
        .Q(Q[28]),
        .R(SR));
  FDRE \Head_reg[82] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[82]),
        .Q(Q[29]),
        .R(SR));
  FDRE \Head_reg[83] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[83]),
        .Q(Q[30]),
        .R(SR));
  FDRE \Head_reg[84] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[84]),
        .Q(Q[31]),
        .R(SR));
  FDRE \Head_reg[85] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[85]),
        .Q(Q[32]),
        .R(SR));
  FDRE \Head_reg[86] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[86]),
        .Q(Q[33]),
        .R(SR));
  FDRE \Head_reg[87] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[87]),
        .Q(Q[34]),
        .R(SR));
  FDRE \Head_reg[88] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[88]),
        .Q(Q[35]),
        .R(SR));
  FDRE \Head_reg[89] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[89]),
        .Q(Q[36]),
        .R(SR));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[90]),
        .Q(Q[37]),
        .R(SR));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[91]),
        .Q(Q[38]),
        .R(SR));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[92]),
        .Q(Q[39]),
        .R(SR));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[93]),
        .Q(Q[40]),
        .R(SR));
  FDRE \Head_reg[94] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[94]),
        .Q(Q[41]),
        .R(SR));
  FDRE \Head_reg[95] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[95]),
        .Q(Q[42]),
        .R(SR));
  FDRE \Head_reg[96] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[96]),
        .Q(Q[43]),
        .R(SR));
  FDRE \Head_reg[97] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[97]),
        .Q(Q[44]),
        .R(SR));
  FDRE \Head_reg[98] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[98]),
        .Q(Q[45]),
        .R(SR));
  FDRE \Head_reg[99] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__5_n_0 ),
        .D(p_0_in1_in[99]),
        .Q(Q[46]),
        .R(SR));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_102_107" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "102" *) 
  (* ram_slice_end = "107" *) 
  RAM32M MemArray_reg_0_3_102_107
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[59:58]),
        .DIB(payloadOut[61:60]),
        .DIC(payloadOut[63:62]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[103:102]),
        .DOB(Head0_0[105:104]),
        .DOC(Head0_0[107:106]),
        .DOD(NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_113" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "108" *) 
  (* ram_slice_end = "113" *) 
  RAM32M MemArray_reg_0_3_108_113
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[65:64]),
        .DIB(payloadOut[67:66]),
        .DIC(payloadOut[69:68]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[109:108]),
        .DOB(Head0_0[111:110]),
        .DOC(Head0_0[113:112]),
        .DOD(NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_114_119" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "114" *) 
  (* ram_slice_end = "119" *) 
  RAM32M MemArray_reg_0_3_114_119
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[71:70]),
        .DIB(payloadOut[73:72]),
        .DIC(payloadOut[75:74]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[115:114]),
        .DOB(Head0_0[117:116]),
        .DOC(Head0_0[119:118]),
        .DOD(NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[1:0]),
        .DIB(payloadOut[3:2]),
        .DIC(payloadOut[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[19:18]),
        .DOB(Head0_0[21:20]),
        .DOC(Head0_0[23:22]),
        .DOD(NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_24_29" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M MemArray_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[7:6]),
        .DIB(payloadOut[9:8]),
        .DIC(payloadOut[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[25:24]),
        .DOB(Head0_0[27:26]),
        .DOC(Head0_0[29:28]),
        .DOD(NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_54_59" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M MemArray_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({1'b0,1'b0}),
        .DIB(payloadOut[13:12]),
        .DIC(payloadOut[15:14]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_54_59_n_0,MemArray_reg_0_3_54_59_n_1}),
        .DOB(Head0_0[57:56]),
        .DOC(Head0_0[59:58]),
        .DOD(NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_60_65" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M MemArray_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[17:16]),
        .DIB(payloadOut[19:18]),
        .DIC(payloadOut[21:20]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[61:60]),
        .DOB(Head0_0[63:62]),
        .DOC(Head0_0[65:64]),
        .DOD(NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_66_71" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M MemArray_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[23:22]),
        .DIB(payloadOut[25:24]),
        .DIC(payloadOut[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[67:66]),
        .DOB(Head0_0[69:68]),
        .DOC(Head0_0[71:70]),
        .DOD(NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_72_77" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M MemArray_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[29:28]),
        .DIB(payloadOut[31:30]),
        .DIC(payloadOut[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[73:72]),
        .DOB(Head0_0[75:74]),
        .DOC(Head0_0[77:76]),
        .DOD(NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_78_83" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "83" *) 
  RAM32M MemArray_reg_0_3_78_83
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[35:34]),
        .DIB(payloadOut[37:36]),
        .DIC(payloadOut[39:38]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[79:78]),
        .DOB(Head0_0[81:80]),
        .DOC(Head0_0[83:82]),
        .DOD(NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_84_89" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "84" *) 
  (* ram_slice_end = "89" *) 
  RAM32M MemArray_reg_0_3_84_89
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[41:40]),
        .DIB(payloadOut[43:42]),
        .DIC(payloadOut[45:44]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[85:84]),
        .DOB(Head0_0[87:86]),
        .DOC(Head0_0[89:88]),
        .DOD(NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_90_95" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "90" *) 
  (* ram_slice_end = "95" *) 
  RAM32M MemArray_reg_0_3_90_95
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[47:46]),
        .DIB(payloadOut[49:48]),
        .DIC(payloadOut[51:50]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[91:90]),
        .DOB(Head0_0[93:92]),
        .DOC(Head0_0[95:94]),
        .DOD(NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "488" *) 
  (* RTL_RAM_NAME = "axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_96_101" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "96" *) 
  (* ram_slice_end = "101" *) 
  RAM32M MemArray_reg_0_3_96_101
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadOut[53:52]),
        .DIB(payloadOut[55:54]),
        .DIC(payloadOut[57:56]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[97:96]),
        .DOB(Head0_0[99:98]),
        .DOC(Head0_0[101:100]),
        .DOD(NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(\Head_reg[19]_0 ));
  LUT6 #(
    .INIT(64'h5557777755544444)) 
    \RdPtr[0]_i_1 
       (.I0(RdPtr[0]),
        .I1(Head1__2),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[2]),
        .I4(\RdPtr_reg[0]_0 ),
        .I5(RdPtr[0]),
        .O(\RdPtr[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0103010100000000)) 
    \RdPtr[0]_i_2__0 
       (.I0(FifoCntrRd[0]),
        .I1(FifoCntrRd[2]),
        .I2(FifoCntrRd[1]),
        .I3(empty_ff_reg_0),
        .I4(arb_rrq_rdy),
        .I5(\Head_reg[19]_0 ),
        .O(Head1__2));
  LUT4 #(
    .INIT(16'h6F60)) 
    \RdPtr[1]_i_1 
       (.I0(RdPtr[0]),
        .I1(RdPtr[1]),
        .I2(RdPtr_reg0),
        .I3(RdPtr[1]),
        .O(\RdPtr[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAFEAA)) 
    \RdPtr[1]_i_2__7 
       (.I0(Head1__2),
        .I1(FifoCntrRd[1]),
        .I2(FifoCntrRd[2]),
        .I3(arb_rrq_rdy),
        .I4(empty_ff_reg_0),
        .O(RdPtr_reg0));
  (* MAX_FANOUT = "128" *) 
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1_n_0 ),
        .Q(RdPtr[0]),
        .R(SR));
  (* MAX_FANOUT = "128" *) 
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[1]_i_1_n_0 ),
        .Q(RdPtr[1]),
        .R(SR));
  LUT4 #(
    .INIT(16'hFB01)) 
    \WrPtr[0]_i_1__16 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(WrPtr[0]),
        .I2(almost_full_ff_reg_0),
        .I3(WrPtr[0]),
        .O(\WrPtr[0]_i_1__16_n_0 ));
  LUT5 #(
    .INIT(32'hFFBE0014)) 
    \WrPtr[1]_i_1__16 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(WrPtr[0]),
        .I2(WrPtr[1]),
        .I3(almost_full_ff_reg_0),
        .I4(WrPtr[1]),
        .O(\WrPtr[1]_i_1__16_n_0 ));
  (* MAX_FANOUT = "128" *) 
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[0]_i_1__16_n_0 ),
        .Q(WrPtr[0]),
        .R(SR));
  (* MAX_FANOUT = "128" *) 
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[1]_i_1__16_n_0 ),
        .Q(WrPtr[1]),
        .R(SR));
  LUT3 #(
    .INIT(8'hF8)) 
    almost_full_ff_i_1__5
       (.I0(FifoCntrWr[1]),
        .I1(FifoCntrWr[0]),
        .I2(FifoCntrWr[2]),
        .O(almost_full_ff_i_1__5_n_0));
  FDRE almost_full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(almost_full_ff_i_1__5_n_0),
        .Q(almost_full_ff_reg_0),
        .R(SR));
  LUT6 #(
    .INIT(64'h5555555555555DFF)) 
    empty_ff_i_1__19
       (.I0(user_rst_n_3ff_reg),
        .I1(arb_rrq_rdy),
        .I2(empty_ff_reg_0),
        .I3(FifoCntrRd[0]),
        .I4(FifoCntrRd[1]),
        .I5(FifoCntrRd[2]),
        .O(empty_ff_i_1__19_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__19_n_0),
        .Q(empty_ff_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    m_axi_arlenissueq_reg_0_15_0_5_i_1
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_7),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_6),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_5),
        .I3(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_7),
        .I4(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_4),
        .O(tlp_rdbt_len[1]));
  LUT6 #(
    .INIT(64'h7F7F7F7F7F7F7FFE)) 
    m_axi_arlenissueq_reg_0_15_0_5_i_10
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_6),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_7),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_4),
        .I3(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_7),
        .I4(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_5),
        .I5(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_6),
        .O(m_axi_arlenissueq_reg_0_15_0_5_i_10_n_0));
  CARRY4 m_axi_arlenissueq_reg_0_15_0_5_i_11
       (.CI(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_0),
        .CO({m_axi_arlenissueq_reg_0_15_0_5_i_11_n_0,m_axi_arlenissueq_reg_0_15_0_5_i_11_n_1,m_axi_arlenissueq_reg_0_15_0_5_i_11_n_2,m_axi_arlenissueq_reg_0_15_0_5_i_11_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({m_axi_arlenissueq_reg_0_15_0_5_i_11_n_4,m_axi_arlenissueq_reg_0_15_0_5_i_11_n_5,m_axi_arlenissueq_reg_0_15_0_5_i_11_n_6,m_axi_arlenissueq_reg_0_15_0_5_i_11_n_7}),
        .S(tlpbytelength[11:8]));
  LUT6 #(
    .INIT(64'hAAA8000000000000)) 
    m_axi_arlenissueq_reg_0_15_0_5_i_12
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_6),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_6),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_5),
        .I3(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_7),
        .I4(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_4),
        .I5(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_7),
        .O(m_axi_arlenissueq_reg_0_15_0_5_i_12_n_0));
  LUT4 #(
    .INIT(16'hFE01)) 
    m_axi_arlenissueq_reg_0_15_0_5_i_2
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_7),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_5),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_6),
        .I3(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_4),
        .O(tlp_rdbt_len[0]));
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    m_axi_arlenissueq_reg_0_15_0_5_i_3
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_5),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_6),
        .I2(p_3_in),
        .I3(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_4),
        .I4(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_7),
        .O(tlp_rdbt_len[3]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    m_axi_arlenissueq_reg_0_15_0_5_i_4
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_6),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_7),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_4),
        .I3(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_7),
        .I4(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_5),
        .I5(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_6),
        .O(tlp_rdbt_len[2]));
  LUT5 #(
    .INIT(32'h6CCCCCC9)) 
    m_axi_arlenissueq_reg_0_15_0_5_i_5
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_10_n_0),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_11_n_7),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_4),
        .I3(m_axi_arlenissueq_reg_0_15_0_5_i_12_n_0),
        .I4(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_5),
        .O(tlp_rdbt_len[5]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    m_axi_arlenissueq_reg_0_15_0_5_i_6
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_4),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_5),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_7),
        .I3(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_4),
        .I4(p_3_in),
        .I5(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_6),
        .O(tlp_rdbt_len[4]));
  CARRY4 m_axi_arlenissueq_reg_0_15_0_5_i_7
       (.CI(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_0),
        .CO({m_axi_arlenissueq_reg_0_15_0_5_i_7_n_0,m_axi_arlenissueq_reg_0_15_0_5_i_7_n_1,m_axi_arlenissueq_reg_0_15_0_5_i_7_n_2,m_axi_arlenissueq_reg_0_15_0_5_i_7_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,tlpbytelength[5:4]}),
        .O({m_axi_arlenissueq_reg_0_15_0_5_i_7_n_4,m_axi_arlenissueq_reg_0_15_0_5_i_7_n_5,m_axi_arlenissueq_reg_0_15_0_5_i_7_n_6,m_axi_arlenissueq_reg_0_15_0_5_i_7_n_7}),
        .S(tlpbytelength[7:4]));
  CARRY4 m_axi_arlenissueq_reg_0_15_0_5_i_8
       (.CI(1'b0),
        .CO({m_axi_arlenissueq_reg_0_15_0_5_i_8_n_0,m_axi_arlenissueq_reg_0_15_0_5_i_8_n_1,m_axi_arlenissueq_reg_0_15_0_5_i_8_n_2,m_axi_arlenissueq_reg_0_15_0_5_i_8_n_3}),
        .CYINIT(1'b0),
        .DI({tlpbytelength[3],Q[2:0]}),
        .O({m_axi_arlenissueq_reg_0_15_0_5_i_8_n_4,m_axi_arlenissueq_reg_0_15_0_5_i_8_n_5,m_axi_arlenissueq_reg_0_15_0_5_i_8_n_6,m_axi_arlenissueq_reg_0_15_0_5_i_8_n_7}),
        .S({tlpbytelength[3],S}));
  LUT3 #(
    .INIT(8'hFE)) 
    m_axi_arlenissueq_reg_0_15_0_5_i_9
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_7),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_5),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_6),
        .O(p_3_in));
  LUT5 #(
    .INIT(32'h6CCCCCC9)) 
    m_axi_arlenissueq_reg_0_15_6_7_i_1
       (.I0(m_axi_arlenissueq_reg_0_15_6_7_i_3_n_0),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_11_n_5),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_11_n_6),
        .I3(m_axi_arlenissueq_reg_0_15_6_7_i_4_n_0),
        .I4(m_axi_arlenissueq_reg_0_15_0_5_i_11_n_7),
        .O(tlp_rdbt_len[7]));
  LUT6 #(
    .INIT(64'h6CCCCCCCCCCCCCC9)) 
    m_axi_arlenissueq_reg_0_15_6_7_i_2
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_10_n_0),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_11_n_6),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_11_n_7),
        .I3(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_5),
        .I4(m_axi_arlenissueq_reg_0_15_0_5_i_12_n_0),
        .I5(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_4),
        .O(tlp_rdbt_len[6]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFE)) 
    m_axi_arlenissueq_reg_0_15_6_7_i_3
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_4),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_5),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_7),
        .I3(m_axi_arlenissueq_reg_0_15_0_5_i_8_n_4),
        .I4(p_3_in),
        .I5(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_6),
        .O(m_axi_arlenissueq_reg_0_15_6_7_i_3_n_0));
  LUT3 #(
    .INIT(8'h80)) 
    m_axi_arlenissueq_reg_0_15_6_7_i_4
       (.I0(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_4),
        .I1(m_axi_arlenissueq_reg_0_15_0_5_i_12_n_0),
        .I2(m_axi_arlenissueq_reg_0_15_0_5_i_7_n_5),
        .O(m_axi_arlenissueq_reg_0_15_6_7_i_4_n_0));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOAsync" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOAsync__parameterized0
   (almost_full_ff_reg_0,
    empty_ff,
    D,
    Q,
    \Head_reg[14]_0 ,
    \FifoCntrRd_reg[1]_0 ,
    \WrPtr_reg[0]_0 ,
    I22,
    \RdPtr_reg[0]_0 ,
    \RdPtr_reg[1]_0 ,
    \Head_reg[10]_0 ,
    \Head_reg[19]_0 ,
    \Head_reg[14]_1 ,
    \Head_reg[14]_2 ,
    \Head_reg[14]_3 ,
    O,
    \Head_reg[10]_1 ,
    \Head_reg[20]_0 ,
    wrq_aabt_noinc,
    \Head_reg[20]_1 ,
    SR,
    user_clk,
    \RdPtr_reg[1]_1 ,
    \WrPtr_reg[0]_1 ,
    \Head_reg[112]_0 ,
    \Head_reg[112]_1 ,
    C2H_WRQ_RDY_IN0,
    \RdPtr_reg[0]_1 ,
    user_rst_n_3ff_reg,
    E,
    \Head_reg[111]_0 );
  output almost_full_ff_reg_0;
  output empty_ff;
  output [3:0]D;
  output [76:0]Q;
  output \Head_reg[14]_0 ;
  output \FifoCntrRd_reg[1]_0 ;
  output \WrPtr_reg[0]_0 ;
  output [0:0]I22;
  output \RdPtr_reg[0]_0 ;
  output [0:0]\RdPtr_reg[1]_0 ;
  output [2:0]\Head_reg[10]_0 ;
  output [8:0]\Head_reg[19]_0 ;
  output \Head_reg[14]_1 ;
  output \Head_reg[14]_2 ;
  output [0:0]\Head_reg[14]_3 ;
  output [2:0]O;
  output [2:0]\Head_reg[10]_1 ;
  output [3:0]\Head_reg[20]_0 ;
  output wrq_aabt_noinc;
  output [9:0]\Head_reg[20]_1 ;
  input [0:0]SR;
  input user_clk;
  input \RdPtr_reg[1]_1 ;
  input \WrPtr_reg[0]_1 ;
  input \Head_reg[112]_0 ;
  input [0:0]\Head_reg[112]_1 ;
  input C2H_WRQ_RDY_IN0;
  input [0:0]\RdPtr_reg[0]_1 ;
  input [0:0]user_rst_n_3ff_reg;
  input [0:0]E;
  input [88:0]\Head_reg[111]_0 ;

  wire C2H_WRQ_RDY_IN0;
  wire [3:0]D;
  wire [0:0]E;
  wire [2:0]FifoCntrRd;
  wire \FifoCntrRd[0]_i_1__8_n_0 ;
  wire \FifoCntrRd[1]_i_1__13_n_0 ;
  wire \FifoCntrRd[2]_i_2__8_n_0 ;
  wire \FifoCntrRd_reg[1]_0 ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__12_n_0 ;
  wire \FifoCntrWr[1]_i_1__15_n_0 ;
  wire \FifoCntrWr[2]_i_1__14_n_0 ;
  wire \Head[112]_i_1__5_n_0 ;
  wire [2:0]\Head_reg[10]_0 ;
  wire [2:0]\Head_reg[10]_1 ;
  wire [88:0]\Head_reg[111]_0 ;
  wire \Head_reg[112]_0 ;
  wire [0:0]\Head_reg[112]_1 ;
  wire \Head_reg[14]_0 ;
  wire \Head_reg[14]_1 ;
  wire \Head_reg[14]_2 ;
  wire [0:0]\Head_reg[14]_3 ;
  wire [8:0]\Head_reg[19]_0 ;
  wire [3:0]\Head_reg[20]_0 ;
  wire [9:0]\Head_reg[20]_1 ;
  wire [0:0]I22;
  wire [2:0]O;
  wire [76:0]Q;
  wire \RdPtr[0]_i_1__0_n_0 ;
  wire \RdPtr[1]_i_1__18_n_0 ;
  wire \RdPtr_reg[0]_0 ;
  wire [0:0]\RdPtr_reg[0]_1 ;
  wire [0:0]\RdPtr_reg[1]_0 ;
  wire \RdPtr_reg[1]_1 ;
  wire [0:0]SR;
  wire \WrPtr[0]_i_1__17_n_0 ;
  wire \WrPtr[1]_i_1__17_n_0 ;
  wire \WrPtr_reg[0]_0 ;
  wire \WrPtr_reg[0]_1 ;
  wire almost_full_ff_i_1__2_n_0;
  wire almost_full_ff_reg_0;
  wire [21:2]arb_wrq_pay;
  wire [10:0]\dma_pcie_rq/data1 ;
  wire [13:0]\dma_pcie_rq/wrq_aabt_whole_len1 ;
  wire [10:0]\dma_pcie_rq/wrq_dwlen_whole ;
  wire empty_ff;
  wire empty_ff_i_1__14_n_0;
  wire [112:7]p_0_in1_in;
  wire user_clk;
  wire [0:0]user_rst_n_3ff_reg;
  wire \wrq_aabt_len_ff[2]_i_3_n_0 ;
  wire \wrq_aabt_len_ff[2]_i_4_n_0 ;
  wire \wrq_aabt_len_ff[2]_i_5_n_0 ;
  wire \wrq_aabt_len_ff[7]_i_3_n_0 ;
  wire \wrq_aabt_len_ff[9]_i_5_n_0 ;
  wire \wrq_aabt_len_ff_reg[2]_i_2_n_0 ;
  wire \wrq_aabt_len_ff_reg[2]_i_2_n_1 ;
  wire \wrq_aabt_len_ff_reg[2]_i_2_n_2 ;
  wire \wrq_aabt_len_ff_reg[2]_i_2_n_3 ;
  wire \wrq_aabt_len_ff_reg[7]_i_2_n_0 ;
  wire \wrq_aabt_len_ff_reg[7]_i_2_n_1 ;
  wire \wrq_aabt_len_ff_reg[7]_i_2_n_2 ;
  wire \wrq_aabt_len_ff_reg[7]_i_2_n_3 ;
  wire \wrq_aabt_len_ff_reg[9]_i_4_n_0 ;
  wire \wrq_aabt_len_ff_reg[9]_i_4_n_1 ;
  wire \wrq_aabt_len_ff_reg[9]_i_4_n_2 ;
  wire \wrq_aabt_len_ff_reg[9]_i_4_n_3 ;
  wire wrq_aabt_noinc;
  wire wrq_aabt_noinc_ff_i_3_n_0;
  wire wrq_aabt_noinc_ff_i_4_n_0;
  wire wrq_aabt_noinc_ff_i_5_n_0;
  wire wrq_aabt_noinc_ff_reg_i_2_n_0;
  wire wrq_aabt_noinc_ff_reg_i_2_n_1;
  wire wrq_aabt_noinc_ff_reg_i_2_n_2;
  wire wrq_aabt_noinc_ff_reg_i_2_n_3;
  wire wrq_aabt_noinc_ff_reg_i_2_n_4;
  wire wrq_aabt_noinc_ff_reg_i_2_n_5;
  wire wrq_aabt_noinc_ff_reg_i_2_n_6;
  wire wrq_aabt_noinc_ff_reg_i_2_n_7;
  wire \wrq_btlen_ff[1]_i_3_n_0 ;
  wire \wrq_btlen_ff[1]_i_4_n_0 ;
  wire \wrq_btlen_ff[5]_i_3_n_0 ;
  wire \wrq_btlen_ff[8]_i_3_n_0 ;
  wire \wrq_btlen_ff[8]_i_5_n_0 ;
  wire \wrq_btlen_ff[8]_i_6_n_0 ;
  wire \wrq_btlen_ff_reg[1]_i_2_n_0 ;
  wire \wrq_btlen_ff_reg[1]_i_2_n_1 ;
  wire \wrq_btlen_ff_reg[1]_i_2_n_2 ;
  wire \wrq_btlen_ff_reg[1]_i_2_n_3 ;
  wire \wrq_btlen_ff_reg[5]_i_2_n_0 ;
  wire \wrq_btlen_ff_reg[5]_i_2_n_1 ;
  wire \wrq_btlen_ff_reg[5]_i_2_n_2 ;
  wire \wrq_btlen_ff_reg[5]_i_2_n_3 ;
  wire \wrq_btlen_ff_reg[8]_i_2_n_2 ;
  wire \wrq_btlen_ff_reg[8]_i_2_n_3 ;
  wire \wrq_dwlen_ff[3]_i_3_n_0 ;
  wire \wrq_dwlen_ff[3]_i_4_n_0 ;
  wire \wrq_dwlen_ff[3]_i_5_n_0 ;
  wire \wrq_dwlen_ff_reg[10]_i_2_n_2 ;
  wire \wrq_dwlen_ff_reg[10]_i_2_n_3 ;
  wire \wrq_dwlen_ff_reg[10]_i_4_n_0 ;
  wire \wrq_dwlen_ff_reg[10]_i_4_n_1 ;
  wire \wrq_dwlen_ff_reg[10]_i_4_n_2 ;
  wire \wrq_dwlen_ff_reg[10]_i_4_n_3 ;
  wire \wrq_dwlen_ff_reg[3]_i_1_n_0 ;
  wire \wrq_dwlen_ff_reg[3]_i_1_n_1 ;
  wire \wrq_dwlen_ff_reg[3]_i_1_n_2 ;
  wire \wrq_dwlen_ff_reg[3]_i_1_n_3 ;
  wire \wrq_dwlen_ff_reg[3]_i_1_n_7 ;
  wire \wrq_dwlen_ff_reg[3]_i_2_n_0 ;
  wire \wrq_dwlen_ff_reg[3]_i_2_n_1 ;
  wire \wrq_dwlen_ff_reg[3]_i_2_n_2 ;
  wire \wrq_dwlen_ff_reg[3]_i_2_n_3 ;
  wire \wrq_dwlen_ff_reg[7]_i_1_n_0 ;
  wire \wrq_dwlen_ff_reg[7]_i_1_n_1 ;
  wire \wrq_dwlen_ff_reg[7]_i_1_n_2 ;
  wire \wrq_dwlen_ff_reg[7]_i_1_n_3 ;
  wire \wrq_dwlen_ff_reg[7]_i_2_n_0 ;
  wire \wrq_dwlen_ff_reg[7]_i_2_n_1 ;
  wire \wrq_dwlen_ff_reg[7]_i_2_n_2 ;
  wire \wrq_dwlen_ff_reg[7]_i_2_n_3 ;
  wire \wrq_fbe_ff[3]_i_3_n_0 ;
  wire \wrq_fbe_ff[3]_i_4_n_0 ;
  wire [3:0]\NLW_wrq_aabt_len_ff_reg[9]_i_6_CO_UNCONNECTED ;
  wire [3:1]\NLW_wrq_aabt_len_ff_reg[9]_i_6_O_UNCONNECTED ;
  wire [3:2]\NLW_wrq_btlen_ff_reg[8]_i_2_CO_UNCONNECTED ;
  wire [3:3]\NLW_wrq_btlen_ff_reg[8]_i_2_O_UNCONNECTED ;
  wire [3:2]\NLW_wrq_dwlen_ff_reg[10]_i_2_CO_UNCONNECTED ;
  wire [3:3]\NLW_wrq_dwlen_ff_reg[10]_i_2_O_UNCONNECTED ;
  wire [3:0]\NLW_wrq_dwlen_ff_reg[10]_i_3_CO_UNCONNECTED ;
  wire [3:1]\NLW_wrq_dwlen_ff_reg[10]_i_3_O_UNCONNECTED ;
  wire [1:0]\NLW_wrq_dwlen_ff_reg[3]_i_2_O_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair1394" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__8 
       (.I0(FifoCntrRd[0]),
        .O(\FifoCntrRd[0]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1394" *) 
  LUT5 #(
    .INIT(32'hEC1313EC)) 
    \FifoCntrRd[1]_i_1__13 
       (.I0(\WrPtr_reg[0]_1 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[112]_0 ),
        .I3(FifoCntrRd[1]),
        .I4(FifoCntrRd[0]),
        .O(\FifoCntrRd[1]_i_1__13_n_0 ));
  LUT6 #(
    .INIT(64'hCCCC9C3CC3C3C6CC)) 
    \FifoCntrRd[2]_i_2__8 
       (.I0(\WrPtr_reg[0]_1 ),
        .I1(FifoCntrRd[2]),
        .I2(FifoCntrRd[1]),
        .I3(\Head_reg[112]_0 ),
        .I4(almost_full_ff_reg_0),
        .I5(FifoCntrRd[0]),
        .O(\FifoCntrRd[2]_i_2__8_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrRd[0]_i_1__8_n_0 ),
        .Q(FifoCntrRd[0]),
        .R(SR));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrRd[1]_i_1__13_n_0 ),
        .Q(FifoCntrRd[1]),
        .R(SR));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrRd[2]_i_2__8_n_0 ),
        .Q(FifoCntrRd[2]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair1395" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__12 
       (.I0(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1395" *) 
  LUT5 #(
    .INIT(32'hEC1313EC)) 
    \FifoCntrWr[1]_i_1__15 
       (.I0(\WrPtr_reg[0]_1 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[112]_0 ),
        .I3(FifoCntrWr[0]),
        .I4(FifoCntrWr[1]),
        .O(\FifoCntrWr[1]_i_1__15_n_0 ));
  LUT6 #(
    .INIT(64'hCCCC9C3CC3C3C6CC)) 
    \FifoCntrWr[2]_i_1__14 
       (.I0(\WrPtr_reg[0]_1 ),
        .I1(FifoCntrWr[2]),
        .I2(FifoCntrWr[1]),
        .I3(\Head_reg[112]_0 ),
        .I4(almost_full_ff_reg_0),
        .I5(FifoCntrWr[0]),
        .O(\FifoCntrWr[2]_i_1__14_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[0]_i_1__12_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(SR));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[1]_i_1__15_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(SR));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[2]_i_1__14_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(SR));
  LUT5 #(
    .INIT(32'hDDDDDDDF)) 
    \Head[112]_i_1__5 
       (.I0(\RdPtr_reg[1]_1 ),
        .I1(\FifoCntrRd_reg[1]_0 ),
        .I2(FifoCntrRd[0]),
        .I3(FifoCntrRd[1]),
        .I4(FifoCntrRd[2]),
        .O(\Head[112]_i_1__5_n_0 ));
  LUT4 #(
    .INIT(16'h03AA)) 
    \Head[112]_i_2 
       (.I0(\Head_reg[112]_1 ),
        .I1(\Head_reg[112]_0 ),
        .I2(almost_full_ff_reg_0),
        .I3(\FifoCntrRd_reg[1]_0 ),
        .O(p_0_in1_in[112]));
  LUT2 #(
    .INIT(4'h2)) 
    \Head[7]_i_1__2 
       (.I0(1'b0),
        .I1(\FifoCntrRd_reg[1]_0 ),
        .O(p_0_in1_in[7]));
  FDRE \Head_reg[0] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [0]),
        .Q(Q[0]),
        .R(SR));
  FDRE \Head_reg[100] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [77]),
        .Q(Q[64]),
        .R(SR));
  FDRE \Head_reg[101] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [78]),
        .Q(Q[65]),
        .R(SR));
  FDRE \Head_reg[102] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [79]),
        .Q(Q[66]),
        .R(SR));
  FDRE \Head_reg[103] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [80]),
        .Q(Q[67]),
        .R(SR));
  FDRE \Head_reg[104] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [81]),
        .Q(Q[68]),
        .R(SR));
  FDRE \Head_reg[105] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [82]),
        .Q(Q[69]),
        .R(SR));
  FDRE \Head_reg[106] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [83]),
        .Q(Q[70]),
        .R(SR));
  FDRE \Head_reg[107] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [84]),
        .Q(Q[71]),
        .R(SR));
  FDRE \Head_reg[108] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [85]),
        .Q(Q[72]),
        .R(SR));
  FDRE \Head_reg[109] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [86]),
        .Q(Q[73]),
        .R(SR));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [7]),
        .Q(arb_wrq_pay[10]),
        .R(SR));
  FDRE \Head_reg[110] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [87]),
        .Q(Q[74]),
        .R(SR));
  FDRE \Head_reg[111] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [88]),
        .Q(Q[75]),
        .R(SR));
  FDRE \Head_reg[112] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(p_0_in1_in[112]),
        .Q(Q[76]),
        .R(SR));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [8]),
        .Q(arb_wrq_pay[11]),
        .R(SR));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [9]),
        .Q(arb_wrq_pay[12]),
        .R(SR));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [10]),
        .Q(arb_wrq_pay[13]),
        .R(SR));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [11]),
        .Q(arb_wrq_pay[14]),
        .R(SR));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [12]),
        .Q(arb_wrq_pay[15]),
        .R(SR));
  FDRE \Head_reg[16] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [13]),
        .Q(arb_wrq_pay[16]),
        .R(SR));
  FDRE \Head_reg[17] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [14]),
        .Q(arb_wrq_pay[17]),
        .R(SR));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [15]),
        .Q(arb_wrq_pay[18]),
        .R(SR));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [16]),
        .Q(arb_wrq_pay[19]),
        .R(SR));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [17]),
        .Q(arb_wrq_pay[20]),
        .R(SR));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [18]),
        .Q(arb_wrq_pay[21]),
        .R(SR));
  FDRE \Head_reg[2] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [1]),
        .Q(arb_wrq_pay[2]),
        .R(SR));
  FDRE \Head_reg[37] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [19]),
        .Q(Q[6]),
        .R(SR));
  FDRE \Head_reg[38] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [20]),
        .Q(Q[7]),
        .R(SR));
  FDRE \Head_reg[39] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [21]),
        .Q(Q[8]),
        .R(SR));
  FDRE \Head_reg[3] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [2]),
        .Q(Q[1]),
        .R(SR));
  FDRE \Head_reg[40] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [22]),
        .Q(Q[9]),
        .R(SR));
  FDRE \Head_reg[41] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [23]),
        .Q(Q[10]),
        .R(SR));
  FDRE \Head_reg[47] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [24]),
        .Q(Q[11]),
        .R(SR));
  FDRE \Head_reg[48] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [25]),
        .Q(Q[12]),
        .R(SR));
  FDRE \Head_reg[49] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [26]),
        .Q(Q[13]),
        .R(SR));
  FDRE \Head_reg[4] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [3]),
        .Q(Q[2]),
        .R(SR));
  FDRE \Head_reg[50] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [27]),
        .Q(Q[14]),
        .R(SR));
  FDRE \Head_reg[51] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [28]),
        .Q(Q[15]),
        .R(SR));
  FDRE \Head_reg[52] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [29]),
        .Q(Q[16]),
        .R(SR));
  FDRE \Head_reg[53] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [30]),
        .Q(Q[17]),
        .R(SR));
  FDRE \Head_reg[54] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [31]),
        .Q(Q[18]),
        .R(SR));
  FDRE \Head_reg[55] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [32]),
        .Q(Q[19]),
        .R(SR));
  FDRE \Head_reg[56] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [33]),
        .Q(Q[20]),
        .R(SR));
  FDRE \Head_reg[57] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [34]),
        .Q(Q[21]),
        .R(SR));
  FDRE \Head_reg[58] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [35]),
        .Q(Q[22]),
        .R(SR));
  FDRE \Head_reg[59] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [36]),
        .Q(Q[23]),
        .R(SR));
  FDRE \Head_reg[5] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [4]),
        .Q(Q[3]),
        .R(SR));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [37]),
        .Q(Q[24]),
        .R(SR));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [38]),
        .Q(Q[25]),
        .R(SR));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [39]),
        .Q(Q[26]),
        .R(SR));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [40]),
        .Q(Q[27]),
        .R(SR));
  FDRE \Head_reg[64] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [41]),
        .Q(Q[28]),
        .R(SR));
  FDRE \Head_reg[65] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [42]),
        .Q(Q[29]),
        .R(SR));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [43]),
        .Q(Q[30]),
        .R(SR));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [44]),
        .Q(Q[31]),
        .R(SR));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [45]),
        .Q(Q[32]),
        .R(SR));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [46]),
        .Q(Q[33]),
        .R(SR));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [47]),
        .Q(Q[34]),
        .R(SR));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [48]),
        .Q(Q[35]),
        .R(SR));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [49]),
        .Q(Q[36]),
        .R(SR));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [50]),
        .Q(Q[37]),
        .R(SR));
  FDRE \Head_reg[74] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [51]),
        .Q(Q[38]),
        .R(SR));
  FDRE \Head_reg[75] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [52]),
        .Q(Q[39]),
        .R(SR));
  FDRE \Head_reg[76] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [53]),
        .Q(Q[40]),
        .R(SR));
  FDRE \Head_reg[77] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [54]),
        .Q(Q[41]),
        .R(SR));
  FDRE \Head_reg[78] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [55]),
        .Q(Q[42]),
        .R(SR));
  FDRE \Head_reg[79] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [56]),
        .Q(Q[43]),
        .R(SR));
  FDRE \Head_reg[7] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(p_0_in1_in[7]),
        .Q(Q[4]),
        .R(SR));
  FDRE \Head_reg[80] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [57]),
        .Q(Q[44]),
        .R(SR));
  FDRE \Head_reg[81] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [58]),
        .Q(Q[45]),
        .R(SR));
  FDRE \Head_reg[82] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [59]),
        .Q(Q[46]),
        .R(SR));
  FDRE \Head_reg[83] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [60]),
        .Q(Q[47]),
        .R(SR));
  FDRE \Head_reg[84] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [61]),
        .Q(Q[48]),
        .R(SR));
  FDRE \Head_reg[85] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [62]),
        .Q(Q[49]),
        .R(SR));
  FDRE \Head_reg[86] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [63]),
        .Q(Q[50]),
        .R(SR));
  FDRE \Head_reg[87] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [64]),
        .Q(Q[51]),
        .R(SR));
  FDRE \Head_reg[88] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [65]),
        .Q(Q[52]),
        .R(SR));
  FDRE \Head_reg[89] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [66]),
        .Q(Q[53]),
        .R(SR));
  FDRE \Head_reg[8] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [5]),
        .Q(Q[5]),
        .R(SR));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [67]),
        .Q(Q[54]),
        .R(SR));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [68]),
        .Q(Q[55]),
        .R(SR));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [69]),
        .Q(Q[56]),
        .R(SR));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [70]),
        .Q(Q[57]),
        .R(SR));
  FDRE \Head_reg[94] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [71]),
        .Q(Q[58]),
        .R(SR));
  FDRE \Head_reg[95] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [72]),
        .Q(Q[59]),
        .R(SR));
  FDRE \Head_reg[96] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [73]),
        .Q(Q[60]),
        .R(SR));
  FDRE \Head_reg[97] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [74]),
        .Q(Q[61]),
        .R(SR));
  FDRE \Head_reg[98] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [75]),
        .Q(Q[62]),
        .R(SR));
  FDRE \Head_reg[99] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [76]),
        .Q(Q[63]),
        .R(SR));
  FDRE \Head_reg[9] 
       (.C(user_clk),
        .CE(\Head[112]_i_1__5_n_0 ),
        .D(\Head_reg[111]_0 [6]),
        .Q(arb_wrq_pay[9]),
        .R(SR));
  LUT6 #(
    .INIT(64'h5555DDDF55551110)) 
    \RdPtr[0]_i_1__0 
       (.I0(\RdPtr_reg[0]_0 ),
        .I1(\RdPtr_reg[1]_1 ),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[2]),
        .I4(\FifoCntrRd_reg[1]_0 ),
        .I5(\RdPtr_reg[0]_0 ),
        .O(\RdPtr[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0FF00FF0FF001FE0)) 
    \RdPtr[1]_i_1__18 
       (.I0(FifoCntrRd[1]),
        .I1(FifoCntrRd[2]),
        .I2(\RdPtr_reg[0]_0 ),
        .I3(\RdPtr_reg[1]_0 ),
        .I4(\RdPtr_reg[1]_1 ),
        .I5(\FifoCntrRd_reg[1]_0 ),
        .O(\RdPtr[1]_i_1__18_n_0 ));
  LUT6 #(
    .INIT(64'h0000111011101110)) 
    \RdPtr[1]_i_2__4 
       (.I0(FifoCntrRd[1]),
        .I1(FifoCntrRd[2]),
        .I2(C2H_WRQ_RDY_IN0),
        .I3(\RdPtr_reg[0]_1 ),
        .I4(FifoCntrRd[0]),
        .I5(\RdPtr_reg[1]_1 ),
        .O(\FifoCntrRd_reg[1]_0 ));
  (* MAX_FANOUT = "128" *) 
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1__0_n_0 ),
        .Q(\RdPtr_reg[0]_0 ),
        .R(SR));
  (* MAX_FANOUT = "128" *) 
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[1]_i_1__18_n_0 ),
        .Q(\RdPtr_reg[1]_0 ),
        .R(SR));
  LUT5 #(
    .INIT(32'hFBF30103)) 
    \WrPtr[0]_i_1__17 
       (.I0(\WrPtr_reg[0]_1 ),
        .I1(\WrPtr_reg[0]_0 ),
        .I2(almost_full_ff_reg_0),
        .I3(\Head_reg[112]_0 ),
        .I4(\WrPtr_reg[0]_0 ),
        .O(\WrPtr[0]_i_1__17_n_0 ));
  LUT6 #(
    .INIT(64'hFFBEFF3C0014003C)) 
    \WrPtr[1]_i_1__17 
       (.I0(\WrPtr_reg[0]_1 ),
        .I1(\WrPtr_reg[0]_0 ),
        .I2(I22),
        .I3(almost_full_ff_reg_0),
        .I4(\Head_reg[112]_0 ),
        .I5(I22),
        .O(\WrPtr[1]_i_1__17_n_0 ));
  (* MAX_FANOUT = "128" *) 
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[0]_i_1__17_n_0 ),
        .Q(\WrPtr_reg[0]_0 ),
        .R(SR));
  (* MAX_FANOUT = "128" *) 
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[1]_i_1__17_n_0 ),
        .Q(I22),
        .R(SR));
  LUT3 #(
    .INIT(8'hF8)) 
    almost_full_ff_i_1__2
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(FifoCntrWr[2]),
        .O(almost_full_ff_i_1__2_n_0));
  FDRE almost_full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(almost_full_ff_i_1__2_n_0),
        .Q(almost_full_ff_reg_0),
        .R(SR));
  LUT5 #(
    .INIT(32'h55575757)) 
    empty_ff_i_1__14
       (.I0(user_rst_n_3ff_reg),
        .I1(FifoCntrRd[1]),
        .I2(FifoCntrRd[2]),
        .I3(\RdPtr_reg[1]_1 ),
        .I4(FifoCntrRd[0]),
        .O(empty_ff_i_1__14_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__14_n_0),
        .Q(empty_ff),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1393" *) 
  LUT1 #(
    .INIT(2'h1)) 
    wrq_0len_ff_i_1
       (.I0(\Head_reg[14]_1 ),
        .O(\Head_reg[14]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1392" *) 
  LUT4 #(
    .INIT(16'h5556)) 
    \wrq_aabt_len_ff[0]_i_1 
       (.I0(\dma_pcie_rq/wrq_aabt_whole_len1 [3]),
        .I1(\dma_pcie_rq/wrq_aabt_whole_len1 [2]),
        .I2(\dma_pcie_rq/wrq_aabt_whole_len1 [0]),
        .I3(\dma_pcie_rq/wrq_aabt_whole_len1 [1]),
        .O(\Head_reg[20]_1 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1392" *) 
  LUT5 #(
    .INIT(32'h5557AAA8)) 
    \wrq_aabt_len_ff[1]_i_1 
       (.I0(\dma_pcie_rq/wrq_aabt_whole_len1 [3]),
        .I1(\dma_pcie_rq/wrq_aabt_whole_len1 [1]),
        .I2(\dma_pcie_rq/wrq_aabt_whole_len1 [0]),
        .I3(\dma_pcie_rq/wrq_aabt_whole_len1 [2]),
        .I4(\dma_pcie_rq/wrq_aabt_whole_len1 [4]),
        .O(\Head_reg[20]_1 [1]));
  LUT6 #(
    .INIT(64'h5557FFFFAAA80000)) 
    \wrq_aabt_len_ff[2]_i_1 
       (.I0(\dma_pcie_rq/wrq_aabt_whole_len1 [4]),
        .I1(\dma_pcie_rq/wrq_aabt_whole_len1 [2]),
        .I2(\dma_pcie_rq/wrq_aabt_whole_len1 [0]),
        .I3(\dma_pcie_rq/wrq_aabt_whole_len1 [1]),
        .I4(\dma_pcie_rq/wrq_aabt_whole_len1 [3]),
        .I5(\dma_pcie_rq/wrq_aabt_whole_len1 [5]),
        .O(\Head_reg[20]_1 [2]));
  LUT2 #(
    .INIT(4'h6)) 
    \wrq_aabt_len_ff[2]_i_3 
       (.I0(arb_wrq_pay[11]),
        .I1(Q[3]),
        .O(\wrq_aabt_len_ff[2]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \wrq_aabt_len_ff[2]_i_4 
       (.I0(arb_wrq_pay[10]),
        .I1(Q[2]),
        .O(\wrq_aabt_len_ff[2]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \wrq_aabt_len_ff[2]_i_5 
       (.I0(arb_wrq_pay[9]),
        .I1(Q[1]),
        .O(\wrq_aabt_len_ff[2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1401" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wrq_aabt_len_ff[3]_i_1 
       (.I0(\wrq_aabt_len_ff[7]_i_3_n_0 ),
        .I1(\dma_pcie_rq/wrq_aabt_whole_len1 [6]),
        .O(\Head_reg[20]_1 [3]));
  (* SOFT_HLUTNM = "soft_lutpair1401" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wrq_aabt_len_ff[4]_i_1 
       (.I0(\wrq_aabt_len_ff[7]_i_3_n_0 ),
        .I1(\dma_pcie_rq/wrq_aabt_whole_len1 [6]),
        .I2(\dma_pcie_rq/wrq_aabt_whole_len1 [7]),
        .O(\Head_reg[20]_1 [4]));
  (* SOFT_HLUTNM = "soft_lutpair1390" *) 
  LUT4 #(
    .INIT(16'hDF20)) 
    \wrq_aabt_len_ff[5]_i_1 
       (.I0(\dma_pcie_rq/wrq_aabt_whole_len1 [6]),
        .I1(\wrq_aabt_len_ff[7]_i_3_n_0 ),
        .I2(\dma_pcie_rq/wrq_aabt_whole_len1 [7]),
        .I3(\dma_pcie_rq/wrq_aabt_whole_len1 [8]),
        .O(\Head_reg[20]_1 [5]));
  (* SOFT_HLUTNM = "soft_lutpair1390" *) 
  LUT5 #(
    .INIT(32'hF7FF0800)) 
    \wrq_aabt_len_ff[6]_i_1 
       (.I0(\dma_pcie_rq/wrq_aabt_whole_len1 [8]),
        .I1(\dma_pcie_rq/wrq_aabt_whole_len1 [7]),
        .I2(\wrq_aabt_len_ff[7]_i_3_n_0 ),
        .I3(\dma_pcie_rq/wrq_aabt_whole_len1 [6]),
        .I4(\dma_pcie_rq/wrq_aabt_whole_len1 [9]),
        .O(\Head_reg[20]_1 [6]));
  LUT6 #(
    .INIT(64'hF7FFFFFF08000000)) 
    \wrq_aabt_len_ff[7]_i_1 
       (.I0(\dma_pcie_rq/wrq_aabt_whole_len1 [9]),
        .I1(\dma_pcie_rq/wrq_aabt_whole_len1 [6]),
        .I2(\wrq_aabt_len_ff[7]_i_3_n_0 ),
        .I3(\dma_pcie_rq/wrq_aabt_whole_len1 [7]),
        .I4(\dma_pcie_rq/wrq_aabt_whole_len1 [8]),
        .I5(\dma_pcie_rq/wrq_aabt_whole_len1 [10]),
        .O(\Head_reg[20]_1 [7]));
  LUT6 #(
    .INIT(64'h5557FFFFFFFFFFFF)) 
    \wrq_aabt_len_ff[7]_i_3 
       (.I0(\dma_pcie_rq/wrq_aabt_whole_len1 [4]),
        .I1(\dma_pcie_rq/wrq_aabt_whole_len1 [2]),
        .I2(\dma_pcie_rq/wrq_aabt_whole_len1 [0]),
        .I3(\dma_pcie_rq/wrq_aabt_whole_len1 [1]),
        .I4(\dma_pcie_rq/wrq_aabt_whole_len1 [3]),
        .I5(\dma_pcie_rq/wrq_aabt_whole_len1 [5]),
        .O(\wrq_aabt_len_ff[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1399" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wrq_aabt_len_ff[8]_i_1 
       (.I0(\wrq_aabt_len_ff[9]_i_5_n_0 ),
        .I1(\dma_pcie_rq/wrq_aabt_whole_len1 [11]),
        .O(\Head_reg[20]_1 [8]));
  (* SOFT_HLUTNM = "soft_lutpair1399" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \wrq_aabt_len_ff[9]_i_2 
       (.I0(\dma_pcie_rq/wrq_aabt_whole_len1 [11]),
        .I1(\wrq_aabt_len_ff[9]_i_5_n_0 ),
        .I2(\dma_pcie_rq/wrq_aabt_whole_len1 [12]),
        .O(\Head_reg[20]_1 [9]));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \wrq_aabt_len_ff[9]_i_5 
       (.I0(\dma_pcie_rq/wrq_aabt_whole_len1 [9]),
        .I1(\dma_pcie_rq/wrq_aabt_whole_len1 [6]),
        .I2(\wrq_aabt_len_ff[7]_i_3_n_0 ),
        .I3(\dma_pcie_rq/wrq_aabt_whole_len1 [7]),
        .I4(\dma_pcie_rq/wrq_aabt_whole_len1 [8]),
        .I5(\dma_pcie_rq/wrq_aabt_whole_len1 [10]),
        .O(\wrq_aabt_len_ff[9]_i_5_n_0 ));
  CARRY4 \wrq_aabt_len_ff_reg[2]_i_2 
       (.CI(1'b0),
        .CO({\wrq_aabt_len_ff_reg[2]_i_2_n_0 ,\wrq_aabt_len_ff_reg[2]_i_2_n_1 ,\wrq_aabt_len_ff_reg[2]_i_2_n_2 ,\wrq_aabt_len_ff_reg[2]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI(arb_wrq_pay[12:9]),
        .O(\dma_pcie_rq/wrq_aabt_whole_len1 [3:0]),
        .S({arb_wrq_pay[12],\wrq_aabt_len_ff[2]_i_3_n_0 ,\wrq_aabt_len_ff[2]_i_4_n_0 ,\wrq_aabt_len_ff[2]_i_5_n_0 }));
  CARRY4 \wrq_aabt_len_ff_reg[7]_i_2 
       (.CI(\wrq_aabt_len_ff_reg[2]_i_2_n_0 ),
        .CO({\wrq_aabt_len_ff_reg[7]_i_2_n_0 ,\wrq_aabt_len_ff_reg[7]_i_2_n_1 ,\wrq_aabt_len_ff_reg[7]_i_2_n_2 ,\wrq_aabt_len_ff_reg[7]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,arb_wrq_pay[14:13]}),
        .O(\dma_pcie_rq/wrq_aabt_whole_len1 [7:4]),
        .S(arb_wrq_pay[16:13]));
  CARRY4 \wrq_aabt_len_ff_reg[9]_i_4 
       (.CI(\wrq_aabt_len_ff_reg[7]_i_2_n_0 ),
        .CO({\wrq_aabt_len_ff_reg[9]_i_4_n_0 ,\wrq_aabt_len_ff_reg[9]_i_4_n_1 ,\wrq_aabt_len_ff_reg[9]_i_4_n_2 ,\wrq_aabt_len_ff_reg[9]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\dma_pcie_rq/wrq_aabt_whole_len1 [11:8]),
        .S(arb_wrq_pay[20:17]));
  CARRY4 \wrq_aabt_len_ff_reg[9]_i_6 
       (.CI(\wrq_aabt_len_ff_reg[9]_i_4_n_0 ),
        .CO({\NLW_wrq_aabt_len_ff_reg[9]_i_6_CO_UNCONNECTED [3:2],\dma_pcie_rq/wrq_aabt_whole_len1 [13],\NLW_wrq_aabt_len_ff_reg[9]_i_6_CO_UNCONNECTED [0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_wrq_aabt_len_ff_reg[9]_i_6_O_UNCONNECTED [3:1],\dma_pcie_rq/wrq_aabt_whole_len1 [12]}),
        .S({1'b0,1'b0,1'b1,arb_wrq_pay[21]}));
  LUT5 #(
    .INIT(32'h03030302)) 
    wrq_aabt_noinc_ff_i_1
       (.I0(wrq_aabt_noinc_ff_reg_i_2_n_5),
        .I1(arb_wrq_pay[2]),
        .I2(Q[0]),
        .I3(wrq_aabt_noinc_ff_reg_i_2_n_6),
        .I4(wrq_aabt_noinc_ff_reg_i_2_n_7),
        .O(wrq_aabt_noinc));
  LUT2 #(
    .INIT(4'h6)) 
    wrq_aabt_noinc_ff_i_3
       (.I0(Q[3]),
        .I1(arb_wrq_pay[11]),
        .O(wrq_aabt_noinc_ff_i_3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    wrq_aabt_noinc_ff_i_4
       (.I0(Q[2]),
        .I1(arb_wrq_pay[10]),
        .O(wrq_aabt_noinc_ff_i_4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    wrq_aabt_noinc_ff_i_5
       (.I0(Q[1]),
        .I1(arb_wrq_pay[9]),
        .O(wrq_aabt_noinc_ff_i_5_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 wrq_aabt_noinc_ff_reg_i_2
       (.CI(1'b0),
        .CO({wrq_aabt_noinc_ff_reg_i_2_n_0,wrq_aabt_noinc_ff_reg_i_2_n_1,wrq_aabt_noinc_ff_reg_i_2_n_2,wrq_aabt_noinc_ff_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,Q[3:1]}),
        .O({wrq_aabt_noinc_ff_reg_i_2_n_4,wrq_aabt_noinc_ff_reg_i_2_n_5,wrq_aabt_noinc_ff_reg_i_2_n_6,wrq_aabt_noinc_ff_reg_i_2_n_7}),
        .S({arb_wrq_pay[12],wrq_aabt_noinc_ff_i_3_n_0,wrq_aabt_noinc_ff_i_4_n_0,wrq_aabt_noinc_ff_i_5_n_0}));
  (* SOFT_HLUTNM = "soft_lutpair1393" *) 
  LUT5 #(
    .INIT(32'h5556FFFF)) 
    \wrq_btlen_ff[0]_i_1 
       (.I0(\dma_pcie_rq/data1 [3]),
        .I1(\dma_pcie_rq/data1 [2]),
        .I2(\dma_pcie_rq/data1 [0]),
        .I3(\dma_pcie_rq/data1 [1]),
        .I4(\Head_reg[14]_1 ),
        .O(\Head_reg[19]_0 [0]));
  LUT6 #(
    .INIT(64'h5557AAA800000000)) 
    \wrq_btlen_ff[1]_i_1 
       (.I0(\dma_pcie_rq/data1 [3]),
        .I1(\dma_pcie_rq/data1 [1]),
        .I2(\dma_pcie_rq/data1 [0]),
        .I3(\dma_pcie_rq/data1 [2]),
        .I4(\dma_pcie_rq/data1 [4]),
        .I5(\Head_reg[14]_1 ),
        .O(\Head_reg[19]_0 [1]));
  LUT2 #(
    .INIT(4'h6)) 
    \wrq_btlen_ff[1]_i_3 
       (.I0(Q[12]),
        .I1(arb_wrq_pay[10]),
        .O(\wrq_btlen_ff[1]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \wrq_btlen_ff[1]_i_4 
       (.I0(Q[11]),
        .I1(arb_wrq_pay[9]),
        .O(\wrq_btlen_ff[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1400" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \wrq_btlen_ff[2]_i_1 
       (.I0(\wrq_btlen_ff[5]_i_3_n_0 ),
        .I1(\dma_pcie_rq/data1 [5]),
        .I2(\Head_reg[14]_1 ),
        .O(\Head_reg[19]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1391" *) 
  LUT4 #(
    .INIT(16'hD200)) 
    \wrq_btlen_ff[3]_i_1 
       (.I0(\dma_pcie_rq/data1 [5]),
        .I1(\wrq_btlen_ff[5]_i_3_n_0 ),
        .I2(\dma_pcie_rq/data1 [6]),
        .I3(\Head_reg[14]_1 ),
        .O(\Head_reg[19]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair1391" *) 
  LUT5 #(
    .INIT(32'hBF400000)) 
    \wrq_btlen_ff[4]_i_1 
       (.I0(\wrq_btlen_ff[5]_i_3_n_0 ),
        .I1(\dma_pcie_rq/data1 [5]),
        .I2(\dma_pcie_rq/data1 [6]),
        .I3(\dma_pcie_rq/data1 [7]),
        .I4(\Head_reg[14]_1 ),
        .O(\Head_reg[19]_0 [4]));
  LUT6 #(
    .INIT(64'hF7FF080000000000)) 
    \wrq_btlen_ff[5]_i_1 
       (.I0(\dma_pcie_rq/data1 [6]),
        .I1(\dma_pcie_rq/data1 [5]),
        .I2(\wrq_btlen_ff[5]_i_3_n_0 ),
        .I3(\dma_pcie_rq/data1 [7]),
        .I4(\dma_pcie_rq/data1 [8]),
        .I5(\Head_reg[14]_1 ),
        .O(\Head_reg[19]_0 [5]));
  LUT6 #(
    .INIT(64'h5557FFFFFFFFFFFF)) 
    \wrq_btlen_ff[5]_i_3 
       (.I0(\dma_pcie_rq/data1 [3]),
        .I1(\dma_pcie_rq/data1 [1]),
        .I2(\dma_pcie_rq/data1 [0]),
        .I3(\dma_pcie_rq/data1 [2]),
        .I4(\dma_pcie_rq/data1 [4]),
        .I5(\Head_reg[14]_1 ),
        .O(\wrq_btlen_ff[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1400" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \wrq_btlen_ff[6]_i_1 
       (.I0(\wrq_btlen_ff[8]_i_3_n_0 ),
        .I1(\dma_pcie_rq/data1 [9]),
        .I2(\Head_reg[14]_1 ),
        .O(\Head_reg[19]_0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair1397" *) 
  LUT4 #(
    .INIT(16'hD200)) 
    \wrq_btlen_ff[7]_i_1 
       (.I0(\dma_pcie_rq/data1 [9]),
        .I1(\wrq_btlen_ff[8]_i_3_n_0 ),
        .I2(\dma_pcie_rq/data1 [10]),
        .I3(\Head_reg[14]_1 ),
        .O(\Head_reg[19]_0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair1397" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    \wrq_btlen_ff[8]_i_1 
       (.I0(\dma_pcie_rq/data1 [9]),
        .I1(\wrq_btlen_ff[8]_i_3_n_0 ),
        .I2(\dma_pcie_rq/data1 [10]),
        .I3(\Head_reg[14]_1 ),
        .O(\Head_reg[19]_0 [8]));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \wrq_btlen_ff[8]_i_3 
       (.I0(\dma_pcie_rq/data1 [6]),
        .I1(\dma_pcie_rq/data1 [5]),
        .I2(\wrq_btlen_ff[5]_i_3_n_0 ),
        .I3(\dma_pcie_rq/data1 [7]),
        .I4(\dma_pcie_rq/data1 [8]),
        .I5(\Head_reg[14]_1 ),
        .O(\wrq_btlen_ff[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \wrq_btlen_ff[8]_i_4 
       (.I0(\wrq_btlen_ff[8]_i_5_n_0 ),
        .I1(arb_wrq_pay[14]),
        .I2(arb_wrq_pay[21]),
        .I3(arb_wrq_pay[13]),
        .I4(arb_wrq_pay[12]),
        .I5(\wrq_btlen_ff[8]_i_6_n_0 ),
        .O(\Head_reg[14]_1 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \wrq_btlen_ff[8]_i_5 
       (.I0(arb_wrq_pay[15]),
        .I1(arb_wrq_pay[17]),
        .I2(arb_wrq_pay[20]),
        .I3(arb_wrq_pay[16]),
        .O(\wrq_btlen_ff[8]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \wrq_btlen_ff[8]_i_6 
       (.I0(arb_wrq_pay[9]),
        .I1(arb_wrq_pay[18]),
        .I2(arb_wrq_pay[19]),
        .I3(arb_wrq_pay[11]),
        .I4(arb_wrq_pay[10]),
        .O(\wrq_btlen_ff[8]_i_6_n_0 ));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \wrq_btlen_ff_reg[1]_i_2 
       (.CI(1'b0),
        .CO({\wrq_btlen_ff_reg[1]_i_2_n_0 ,\wrq_btlen_ff_reg[1]_i_2_n_1 ,\wrq_btlen_ff_reg[1]_i_2_n_2 ,\wrq_btlen_ff_reg[1]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,Q[12:11]}),
        .O(\dma_pcie_rq/data1 [3:0]),
        .S({arb_wrq_pay[12:11],\wrq_btlen_ff[1]_i_3_n_0 ,\wrq_btlen_ff[1]_i_4_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \wrq_btlen_ff_reg[5]_i_2 
       (.CI(\wrq_btlen_ff_reg[1]_i_2_n_0 ),
        .CO({\wrq_btlen_ff_reg[5]_i_2_n_0 ,\wrq_btlen_ff_reg[5]_i_2_n_1 ,\wrq_btlen_ff_reg[5]_i_2_n_2 ,\wrq_btlen_ff_reg[5]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,arb_wrq_pay[13]}),
        .O(\dma_pcie_rq/data1 [7:4]),
        .S(arb_wrq_pay[16:13]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \wrq_btlen_ff_reg[8]_i_2 
       (.CI(\wrq_btlen_ff_reg[5]_i_2_n_0 ),
        .CO({\NLW_wrq_btlen_ff_reg[8]_i_2_CO_UNCONNECTED [3:2],\wrq_btlen_ff_reg[8]_i_2_n_2 ,\wrq_btlen_ff_reg[8]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_wrq_btlen_ff_reg[8]_i_2_O_UNCONNECTED [3],\dma_pcie_rq/data1 [10:8]}),
        .S({1'b0,arb_wrq_pay[19:17]}));
  (* SOFT_HLUTNM = "soft_lutpair1396" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \wrq_dwlen_ff[0]_i_1 
       (.I0(\wrq_dwlen_ff_reg[3]_i_1_n_7 ),
        .I1(\Head_reg[14]_1 ),
        .O(\Head_reg[14]_3 ));
  LUT5 #(
    .INIT(32'h1881E77E)) 
    \wrq_dwlen_ff[3]_i_3 
       (.I0(arb_wrq_pay[9]),
        .I1(Q[11]),
        .I2(Q[12]),
        .I3(arb_wrq_pay[10]),
        .I4(\dma_pcie_rq/wrq_dwlen_whole [0]),
        .O(\wrq_dwlen_ff[3]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \wrq_dwlen_ff[3]_i_4 
       (.I0(arb_wrq_pay[10]),
        .I1(Q[12]),
        .O(\wrq_dwlen_ff[3]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \wrq_dwlen_ff[3]_i_5 
       (.I0(arb_wrq_pay[9]),
        .I1(Q[11]),
        .O(\wrq_dwlen_ff[3]_i_5_n_0 ));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \wrq_dwlen_ff_reg[10]_i_2 
       (.CI(\wrq_dwlen_ff_reg[7]_i_1_n_0 ),
        .CO({\NLW_wrq_dwlen_ff_reg[10]_i_2_CO_UNCONNECTED [3:2],\wrq_dwlen_ff_reg[10]_i_2_n_2 ,\wrq_dwlen_ff_reg[10]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_wrq_dwlen_ff_reg[10]_i_2_O_UNCONNECTED [3],O}),
        .S({1'b0,\dma_pcie_rq/wrq_dwlen_whole [10:8]}));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \wrq_dwlen_ff_reg[10]_i_3 
       (.CI(\wrq_dwlen_ff_reg[10]_i_4_n_0 ),
        .CO(\NLW_wrq_dwlen_ff_reg[10]_i_3_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_wrq_dwlen_ff_reg[10]_i_3_O_UNCONNECTED [3:1],\dma_pcie_rq/wrq_dwlen_whole [10]}),
        .S({1'b0,1'b0,1'b0,arb_wrq_pay[21]}));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \wrq_dwlen_ff_reg[10]_i_4 
       (.CI(\wrq_dwlen_ff_reg[7]_i_2_n_0 ),
        .CO({\wrq_dwlen_ff_reg[10]_i_4_n_0 ,\wrq_dwlen_ff_reg[10]_i_4_n_1 ,\wrq_dwlen_ff_reg[10]_i_4_n_2 ,\wrq_dwlen_ff_reg[10]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\dma_pcie_rq/wrq_dwlen_whole [9:6]),
        .S(arb_wrq_pay[20:17]));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \wrq_dwlen_ff_reg[3]_i_1 
       (.CI(1'b0),
        .CO({\wrq_dwlen_ff_reg[3]_i_1_n_0 ,\wrq_dwlen_ff_reg[3]_i_1_n_1 ,\wrq_dwlen_ff_reg[3]_i_1_n_2 ,\wrq_dwlen_ff_reg[3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\dma_pcie_rq/wrq_dwlen_whole [0]}),
        .O({\Head_reg[10]_1 ,\wrq_dwlen_ff_reg[3]_i_1_n_7 }),
        .S({\dma_pcie_rq/wrq_dwlen_whole [3:1],\wrq_dwlen_ff[3]_i_3_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \wrq_dwlen_ff_reg[3]_i_2 
       (.CI(1'b0),
        .CO({\wrq_dwlen_ff_reg[3]_i_2_n_0 ,\wrq_dwlen_ff_reg[3]_i_2_n_1 ,\wrq_dwlen_ff_reg[3]_i_2_n_2 ,\wrq_dwlen_ff_reg[3]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,arb_wrq_pay[10:9]}),
        .O({\dma_pcie_rq/wrq_dwlen_whole [1:0],\NLW_wrq_dwlen_ff_reg[3]_i_2_O_UNCONNECTED [1:0]}),
        .S({arb_wrq_pay[12:11],\wrq_dwlen_ff[3]_i_4_n_0 ,\wrq_dwlen_ff[3]_i_5_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \wrq_dwlen_ff_reg[7]_i_1 
       (.CI(\wrq_dwlen_ff_reg[3]_i_1_n_0 ),
        .CO({\wrq_dwlen_ff_reg[7]_i_1_n_0 ,\wrq_dwlen_ff_reg[7]_i_1_n_1 ,\wrq_dwlen_ff_reg[7]_i_1_n_2 ,\wrq_dwlen_ff_reg[7]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\Head_reg[20]_0 ),
        .S(\dma_pcie_rq/wrq_dwlen_whole [7:4]));
  (* ADDER_THRESHOLD = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \wrq_dwlen_ff_reg[7]_i_2 
       (.CI(\wrq_dwlen_ff_reg[3]_i_2_n_0 ),
        .CO({\wrq_dwlen_ff_reg[7]_i_2_n_0 ,\wrq_dwlen_ff_reg[7]_i_2_n_1 ,\wrq_dwlen_ff_reg[7]_i_2_n_2 ,\wrq_dwlen_ff_reg[7]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\dma_pcie_rq/wrq_dwlen_whole [5:2]),
        .S(arb_wrq_pay[16:13]));
  LUT2 #(
    .INIT(4'h1)) 
    \wrq_fbe_ff[0]_i_1 
       (.I0(Q[12]),
        .I1(Q[11]),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair1389" *) 
  LUT5 #(
    .INIT(32'h32233333)) 
    \wrq_fbe_ff[1]_i_1 
       (.I0(arb_wrq_pay[10]),
        .I1(Q[12]),
        .I2(Q[11]),
        .I3(arb_wrq_pay[9]),
        .I4(\Head_reg[14]_0 ),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair1388" *) 
  LUT5 #(
    .INIT(32'h26293F3F)) 
    \wrq_fbe_ff[2]_i_1 
       (.I0(arb_wrq_pay[10]),
        .I1(Q[12]),
        .I2(Q[11]),
        .I3(arb_wrq_pay[9]),
        .I4(\Head_reg[14]_0 ),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair1388" *) 
  LUT5 #(
    .INIT(32'h1881FFFF)) 
    \wrq_fbe_ff[3]_i_1 
       (.I0(arb_wrq_pay[9]),
        .I1(Q[11]),
        .I2(Q[12]),
        .I3(arb_wrq_pay[10]),
        .I4(\Head_reg[14]_0 ),
        .O(D[3]));
  LUT6 #(
    .INIT(64'h00000001FFFFFFFF)) 
    \wrq_fbe_ff[3]_i_2 
       (.I0(\wrq_fbe_ff[3]_i_3_n_0 ),
        .I1(\wrq_fbe_ff[3]_i_4_n_0 ),
        .I2(O[2]),
        .I3(\Head_reg[10]_1 [0]),
        .I4(\Head_reg[10]_1 [1]),
        .I5(\Head_reg[14]_1 ),
        .O(\Head_reg[14]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1396" *) 
  LUT4 #(
    .INIT(16'hFFFD)) 
    \wrq_fbe_ff[3]_i_3 
       (.I0(\wrq_dwlen_ff_reg[3]_i_1_n_7 ),
        .I1(O[1]),
        .I2(O[0]),
        .I3(\Head_reg[20]_0 [3]),
        .O(\wrq_fbe_ff[3]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \wrq_fbe_ff[3]_i_4 
       (.I0(\Head_reg[20]_0 [2]),
        .I1(\Head_reg[20]_0 [1]),
        .I2(\Head_reg[20]_0 [0]),
        .I3(\Head_reg[10]_1 [2]),
        .O(\wrq_fbe_ff[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1398" *) 
  LUT4 #(
    .INIT(16'hF66F)) 
    \wrq_lbe_ff[1]_i_1 
       (.I0(arb_wrq_pay[10]),
        .I1(Q[12]),
        .I2(Q[11]),
        .I3(arb_wrq_pay[9]),
        .O(\Head_reg[10]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1398" *) 
  LUT4 #(
    .INIT(16'h6669)) 
    \wrq_lbe_ff[2]_i_1 
       (.I0(arb_wrq_pay[10]),
        .I1(Q[12]),
        .I2(Q[11]),
        .I3(arb_wrq_pay[9]),
        .O(\Head_reg[10]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1389" *) 
  LUT4 #(
    .INIT(16'h6009)) 
    \wrq_lbe_ff[3]_i_2 
       (.I0(arb_wrq_pay[10]),
        .I1(Q[12]),
        .I2(Q[11]),
        .I3(arb_wrq_pay[9]),
        .O(\Head_reg[10]_0 [2]));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOAsync" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOAsync__parameterized0_46
   (empty_ff_reg_0,
    almost_full_ff_reg_0,
    D,
    Q,
    tlp_dstbt_len,
    DIA,
    DIB,
    wmreqset,
    user_clk,
    SR,
    \Head_reg[0]_0 ,
    \Head_reg[110]_0 ,
    \Head_reg[110]_1 ,
    \FifoCntrWr_reg[0]_0 ,
    \RdPtr_reg[1]_0 ,
    Head1__2,
    Head0,
    user_rst_n_3ff_reg,
    p_15_in,
    payloadmuxed);
  output empty_ff_reg_0;
  output almost_full_ff_reg_0;
  output [22:0]D;
  output [86:0]Q;
  output [7:0]tlp_dstbt_len;
  output [1:0]DIA;
  output [1:0]DIB;
  output wmreqset;
  input user_clk;
  input [0:0]SR;
  input \Head_reg[0]_0 ;
  input [86:0]\Head_reg[110]_0 ;
  input \Head_reg[110]_1 ;
  input \FifoCntrWr_reg[0]_0 ;
  input \RdPtr_reg[1]_0 ;
  input Head1__2;
  input [22:0]Head0;
  input [0:0]user_rst_n_3ff_reg;
  input p_15_in;
  input [91:0]payloadmuxed;

  wire [22:0]D;
  wire [1:0]DIA;
  wire [1:0]DIB;
  wire [2:0]FifoCntrRd;
  wire \FifoCntrRd[0]_i_1__14_n_0 ;
  wire \FifoCntrRd[1]_i_1__14_n_0 ;
  wire \FifoCntrRd[2]_i_1__14_n_0 ;
  wire \FifoCntrRd[2]_i_2__9_n_0 ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__16_n_0 ;
  wire \FifoCntrWr[1]_i_1__16_n_0 ;
  wire \FifoCntrWr[2]_i_1__15_n_0 ;
  wire \FifoCntrWr_reg[0]_0 ;
  wire [22:0]Head0;
  wire Head1__2;
  wire Head1__2_0;
  wire \Head[0]_i_1__8_n_0 ;
  wire \Head[100]_i_1__9_n_0 ;
  wire \Head[101]_i_1__9_n_0 ;
  wire \Head[102]_i_1__9_n_0 ;
  wire \Head[103]_i_1__9_n_0 ;
  wire \Head[104]_i_1__9_n_0 ;
  wire \Head[105]_i_1__9_n_0 ;
  wire \Head[106]_i_1__9_n_0 ;
  wire \Head[107]_i_1__9_n_0 ;
  wire \Head[108]_i_1__9_n_0 ;
  wire \Head[109]_i_1__9_n_0 ;
  wire \Head[10]_i_1__10_n_0 ;
  wire \Head[110]_i_1__8_n_0 ;
  wire \Head[110]_i_2_n_0 ;
  wire \Head[11]_i_1__10_n_0 ;
  wire \Head[12]_i_1__10_n_0 ;
  wire \Head[13]_i_1__10_n_0 ;
  wire \Head[14]_i_1__10_n_0 ;
  wire \Head[15]_i_1__10_n_0 ;
  wire \Head[16]_i_1__9_n_0 ;
  wire \Head[17]_i_1__8_n_0 ;
  wire \Head[18]_i_1__11_n_0 ;
  wire \Head[19]_i_1__11_n_0 ;
  wire \Head[20]_i_1__12_n_0 ;
  wire \Head[21]_i_1__12_n_0 ;
  wire \Head[37]_i_1__5_n_0 ;
  wire \Head[38]_i_1__5_n_0 ;
  wire \Head[39]_i_1__5_n_0 ;
  wire \Head[3]_i_1__6_n_0 ;
  wire \Head[40]_i_1__5_n_0 ;
  wire \Head[41]_i_1__5_n_0 ;
  wire \Head[47]_i_1__8_n_0 ;
  wire \Head[48]_i_1__7_n_0 ;
  wire \Head[49]_i_1__7_n_0 ;
  wire \Head[4]_i_1__6_n_0 ;
  wire \Head[50]_i_1__7_n_0 ;
  wire \Head[51]_i_1__7_n_0 ;
  wire \Head[52]_i_1__5_n_0 ;
  wire \Head[53]_i_1__5_n_0 ;
  wire \Head[54]_i_1__5_n_0 ;
  wire \Head[55]_i_1__5_n_0 ;
  wire \Head[56]_i_1__9_n_0 ;
  wire \Head[57]_i_1__9_n_0 ;
  wire \Head[58]_i_1__9_n_0 ;
  wire \Head[59]_i_1__9_n_0 ;
  wire \Head[5]_i_1__6_n_0 ;
  wire \Head[60]_i_1__10_n_0 ;
  wire \Head[61]_i_1__10_n_0 ;
  wire \Head[62]_i_1__10_n_0 ;
  wire \Head[63]_i_1__10_n_0 ;
  wire \Head[64]_i_1__9_n_0 ;
  wire \Head[65]_i_1__9_n_0 ;
  wire \Head[66]_i_1__10_n_0 ;
  wire \Head[67]_i_1__10_n_0 ;
  wire \Head[68]_i_1__10_n_0 ;
  wire \Head[69]_i_1__10_n_0 ;
  wire \Head[70]_i_1__10_n_0 ;
  wire \Head[71]_i_1__10_n_0 ;
  wire \Head[72]_i_1__10_n_0 ;
  wire \Head[73]_i_1__10_n_0 ;
  wire \Head[74]_i_1__9_n_0 ;
  wire \Head[75]_i_1__9_n_0 ;
  wire \Head[76]_i_1__9_n_0 ;
  wire \Head[77]_i_1__9_n_0 ;
  wire \Head[78]_i_1__9_n_0 ;
  wire \Head[79]_i_1__9_n_0 ;
  wire \Head[80]_i_1__9_n_0 ;
  wire \Head[81]_i_1__9_n_0 ;
  wire \Head[82]_i_1__9_n_0 ;
  wire \Head[83]_i_1__9_n_0 ;
  wire \Head[84]_i_1__9_n_0 ;
  wire \Head[85]_i_1__9_n_0 ;
  wire \Head[86]_i_1__9_n_0 ;
  wire \Head[87]_i_1__9_n_0 ;
  wire \Head[88]_i_1__9_n_0 ;
  wire \Head[89]_i_1__9_n_0 ;
  wire \Head[8]_i_1__9_n_0 ;
  wire \Head[90]_i_1__10_n_0 ;
  wire \Head[91]_i_1__10_n_0 ;
  wire \Head[92]_i_1__10_n_0 ;
  wire \Head[93]_i_1__10_n_0 ;
  wire \Head[94]_i_1__9_n_0 ;
  wire \Head[95]_i_1__9_n_0 ;
  wire \Head[96]_i_1__9_n_0 ;
  wire \Head[97]_i_1__9_n_0 ;
  wire \Head[98]_i_1__9_n_0 ;
  wire \Head[99]_i_1__9_n_0 ;
  wire \Head[9]_i_1__9_n_0 ;
  wire \Head_reg[0]_0 ;
  wire [86:0]\Head_reg[110]_0 ;
  wire \Head_reg[110]_1 ;
  wire MemArray_reg_0_3_0_5_n_0;
  wire MemArray_reg_0_3_0_5_n_1;
  wire MemArray_reg_0_3_0_5_n_2;
  wire MemArray_reg_0_3_0_5_n_3;
  wire MemArray_reg_0_3_0_5_n_4;
  wire MemArray_reg_0_3_0_5_n_5;
  wire MemArray_reg_0_3_102_107_n_0;
  wire MemArray_reg_0_3_102_107_n_1;
  wire MemArray_reg_0_3_102_107_n_2;
  wire MemArray_reg_0_3_102_107_n_3;
  wire MemArray_reg_0_3_102_107_n_4;
  wire MemArray_reg_0_3_102_107_n_5;
  wire MemArray_reg_0_3_108_112_n_0;
  wire MemArray_reg_0_3_108_112_n_1;
  wire MemArray_reg_0_3_108_112_n_2;
  wire MemArray_reg_0_3_108_112_n_3;
  wire MemArray_reg_0_3_12_17_n_0;
  wire MemArray_reg_0_3_12_17_n_1;
  wire MemArray_reg_0_3_12_17_n_2;
  wire MemArray_reg_0_3_12_17_n_3;
  wire MemArray_reg_0_3_12_17_n_4;
  wire MemArray_reg_0_3_12_17_n_5;
  wire MemArray_reg_0_3_18_23_n_0;
  wire MemArray_reg_0_3_18_23_n_1;
  wire MemArray_reg_0_3_18_23_n_2;
  wire MemArray_reg_0_3_18_23_n_3;
  wire MemArray_reg_0_3_18_23_n_4;
  wire MemArray_reg_0_3_18_23_n_5;
  wire MemArray_reg_0_3_36_41_n_0;
  wire MemArray_reg_0_3_36_41_n_1;
  wire MemArray_reg_0_3_36_41_n_2;
  wire MemArray_reg_0_3_36_41_n_3;
  wire MemArray_reg_0_3_36_41_n_4;
  wire MemArray_reg_0_3_36_41_n_5;
  wire MemArray_reg_0_3_42_47_n_0;
  wire MemArray_reg_0_3_42_47_n_2;
  wire MemArray_reg_0_3_42_47_n_3;
  wire MemArray_reg_0_3_48_53_n_0;
  wire MemArray_reg_0_3_48_53_n_1;
  wire MemArray_reg_0_3_48_53_n_2;
  wire MemArray_reg_0_3_48_53_n_3;
  wire MemArray_reg_0_3_48_53_n_4;
  wire MemArray_reg_0_3_48_53_n_5;
  wire MemArray_reg_0_3_54_59_n_0;
  wire MemArray_reg_0_3_54_59_n_1;
  wire MemArray_reg_0_3_54_59_n_2;
  wire MemArray_reg_0_3_54_59_n_3;
  wire MemArray_reg_0_3_54_59_n_4;
  wire MemArray_reg_0_3_54_59_n_5;
  wire MemArray_reg_0_3_60_65_n_0;
  wire MemArray_reg_0_3_60_65_n_1;
  wire MemArray_reg_0_3_60_65_n_2;
  wire MemArray_reg_0_3_60_65_n_3;
  wire MemArray_reg_0_3_60_65_n_4;
  wire MemArray_reg_0_3_60_65_n_5;
  wire MemArray_reg_0_3_66_71_n_0;
  wire MemArray_reg_0_3_66_71_n_1;
  wire MemArray_reg_0_3_66_71_n_2;
  wire MemArray_reg_0_3_66_71_n_3;
  wire MemArray_reg_0_3_66_71_n_4;
  wire MemArray_reg_0_3_66_71_n_5;
  wire MemArray_reg_0_3_6_11_n_0;
  wire MemArray_reg_0_3_6_11_n_1;
  wire MemArray_reg_0_3_6_11_n_2;
  wire MemArray_reg_0_3_6_11_n_3;
  wire MemArray_reg_0_3_72_77_n_0;
  wire MemArray_reg_0_3_72_77_n_1;
  wire MemArray_reg_0_3_72_77_n_2;
  wire MemArray_reg_0_3_72_77_n_3;
  wire MemArray_reg_0_3_72_77_n_4;
  wire MemArray_reg_0_3_72_77_n_5;
  wire MemArray_reg_0_3_78_83_n_0;
  wire MemArray_reg_0_3_78_83_n_1;
  wire MemArray_reg_0_3_78_83_n_2;
  wire MemArray_reg_0_3_78_83_n_3;
  wire MemArray_reg_0_3_78_83_n_4;
  wire MemArray_reg_0_3_78_83_n_5;
  wire MemArray_reg_0_3_84_89_n_0;
  wire MemArray_reg_0_3_84_89_n_1;
  wire MemArray_reg_0_3_84_89_n_2;
  wire MemArray_reg_0_3_84_89_n_3;
  wire MemArray_reg_0_3_84_89_n_4;
  wire MemArray_reg_0_3_84_89_n_5;
  wire MemArray_reg_0_3_90_95_n_0;
  wire MemArray_reg_0_3_90_95_n_1;
  wire MemArray_reg_0_3_90_95_n_2;
  wire MemArray_reg_0_3_90_95_n_3;
  wire MemArray_reg_0_3_90_95_n_4;
  wire MemArray_reg_0_3_90_95_n_5;
  wire MemArray_reg_0_3_96_101_n_0;
  wire MemArray_reg_0_3_96_101_n_1;
  wire MemArray_reg_0_3_96_101_n_2;
  wire MemArray_reg_0_3_96_101_n_3;
  wire MemArray_reg_0_3_96_101_n_4;
  wire MemArray_reg_0_3_96_101_n_5;
  wire [86:0]Q;
  wire [1:0]RdPtr;
  wire \RdPtr[0]_i_1_n_0 ;
  wire \RdPtr[1]_i_1__19_n_0 ;
  wire \RdPtr_reg[1]_0 ;
  wire [0:0]SR;
  wire [1:0]WrPtr;
  wire \WrPtr[0]_i_1__18_n_0 ;
  wire \WrPtr[1]_i_1__18_n_0 ;
  wire almost_full_ff_i_1__6_n_0;
  wire almost_full_ff_reg_0;
  wire [3:0]\axi4mm_axi_mm_master_wr/p_0_in1_in ;
  wire empty_ff_i_1__20_n_0;
  wire empty_ff_reg_0;
  wire m_axi_awlenq_reg_0_15_0_5_i_10_n_0;
  wire m_axi_awlenq_reg_0_15_0_5_i_11_n_0;
  wire m_axi_awlenq_reg_0_15_0_5_i_11_n_1;
  wire m_axi_awlenq_reg_0_15_0_5_i_11_n_2;
  wire m_axi_awlenq_reg_0_15_0_5_i_11_n_3;
  wire m_axi_awlenq_reg_0_15_0_5_i_11_n_4;
  wire m_axi_awlenq_reg_0_15_0_5_i_11_n_5;
  wire m_axi_awlenq_reg_0_15_0_5_i_11_n_6;
  wire m_axi_awlenq_reg_0_15_0_5_i_11_n_7;
  wire m_axi_awlenq_reg_0_15_0_5_i_12_n_0;
  wire m_axi_awlenq_reg_0_15_0_5_i_13_n_0;
  wire m_axi_awlenq_reg_0_15_0_5_i_14_n_0;
  wire m_axi_awlenq_reg_0_15_0_5_i_15_n_0;
  wire m_axi_awlenq_reg_0_15_0_5_i_16_n_0;
  wire m_axi_awlenq_reg_0_15_0_5_i_7_n_0;
  wire m_axi_awlenq_reg_0_15_0_5_i_7_n_1;
  wire m_axi_awlenq_reg_0_15_0_5_i_7_n_2;
  wire m_axi_awlenq_reg_0_15_0_5_i_7_n_3;
  wire m_axi_awlenq_reg_0_15_0_5_i_7_n_4;
  wire m_axi_awlenq_reg_0_15_0_5_i_7_n_5;
  wire m_axi_awlenq_reg_0_15_0_5_i_7_n_6;
  wire m_axi_awlenq_reg_0_15_0_5_i_7_n_7;
  wire m_axi_awlenq_reg_0_15_0_5_i_8_n_0;
  wire m_axi_awlenq_reg_0_15_0_5_i_8_n_1;
  wire m_axi_awlenq_reg_0_15_0_5_i_8_n_2;
  wire m_axi_awlenq_reg_0_15_0_5_i_8_n_3;
  wire m_axi_awlenq_reg_0_15_0_5_i_8_n_4;
  wire m_axi_awlenq_reg_0_15_0_5_i_8_n_5;
  wire m_axi_awlenq_reg_0_15_0_5_i_8_n_6;
  wire m_axi_awlenq_reg_0_15_0_5_i_8_n_7;
  wire m_axi_awlenq_reg_0_15_0_5_i_9_n_0;
  wire m_axi_waddrlastq_reg_0_15_0_5_i_5_n_0;
  wire m_axi_waddrlastq_reg_0_15_0_5_i_5_n_1;
  wire m_axi_waddrlastq_reg_0_15_0_5_i_5_n_2;
  wire m_axi_waddrlastq_reg_0_15_0_5_i_5_n_3;
  wire m_axi_waddrlastq_reg_0_15_0_5_i_6_n_0;
  wire m_axi_waddrlastq_reg_0_15_0_5_i_7_n_0;
  wire m_axi_waddrlastq_reg_0_15_0_5_i_8_n_0;
  wire m_axi_waddrlastq_reg_0_15_0_5_i_9_n_0;
  wire p_15_in;
  wire [91:0]payloadmuxed;
  wire [7:0]tlp_dstbt_len;
  wire user_clk;
  wire [0:0]user_rst_n_3ff_reg;
  wire wmreqset;
  wire [1:0]NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_108_112_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_108_112_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [0:0]NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_42_47_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED;

  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__14 
       (.I0(FifoCntrRd[0]),
        .O(\FifoCntrRd[0]_i_1__14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair452" *) 
  LUT4 #(
    .INIT(16'hC396)) 
    \FifoCntrRd[1]_i_1__14 
       (.I0(\FifoCntrWr_reg[0]_0 ),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[1]),
        .I3(almost_full_ff_reg_0),
        .O(\FifoCntrRd[1]_i_1__14_n_0 ));
  LUT3 #(
    .INIT(8'hE1)) 
    \FifoCntrRd[2]_i_1__14 
       (.I0(\FifoCntrWr_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\RdPtr_reg[1]_0 ),
        .O(\FifoCntrRd[2]_i_1__14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair452" *) 
  LUT5 #(
    .INIT(32'hFC03BD42)) 
    \FifoCntrRd[2]_i_2__9 
       (.I0(\FifoCntrWr_reg[0]_0 ),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[2]),
        .I4(almost_full_ff_reg_0),
        .O(\FifoCntrRd[2]_i_2__9_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__14_n_0 ),
        .D(\FifoCntrRd[0]_i_1__14_n_0 ),
        .Q(FifoCntrRd[0]),
        .R(SR));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__14_n_0 ),
        .D(\FifoCntrRd[1]_i_1__14_n_0 ),
        .Q(FifoCntrRd[1]),
        .R(SR));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__14_n_0 ),
        .D(\FifoCntrRd[2]_i_2__9_n_0 ),
        .Q(FifoCntrRd[2]),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__16 
       (.I0(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair453" *) 
  LUT4 #(
    .INIT(16'hC396)) 
    \FifoCntrWr[1]_i_1__16 
       (.I0(\FifoCntrWr_reg[0]_0 ),
        .I1(FifoCntrWr[0]),
        .I2(FifoCntrWr[1]),
        .I3(almost_full_ff_reg_0),
        .O(\FifoCntrWr[1]_i_1__16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair453" *) 
  LUT5 #(
    .INIT(32'hFC03BD42)) 
    \FifoCntrWr[2]_i_1__15 
       (.I0(\FifoCntrWr_reg[0]_0 ),
        .I1(FifoCntrWr[0]),
        .I2(FifoCntrWr[1]),
        .I3(FifoCntrWr[2]),
        .I4(almost_full_ff_reg_0),
        .O(\FifoCntrWr[2]_i_1__15_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__14_n_0 ),
        .D(\FifoCntrWr[0]_i_1__16_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(SR));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__14_n_0 ),
        .D(\FifoCntrWr[1]_i_1__16_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(SR));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__14_n_0 ),
        .D(\FifoCntrWr[2]_i_1__15_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(SR));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[0]_i_1__8 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [0]),
        .I3(MemArray_reg_0_3_0_5_n_1),
        .I4(Head1__2_0),
        .O(\Head[0]_i_1__8_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[100]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [76]),
        .I3(MemArray_reg_0_3_96_101_n_5),
        .I4(Head1__2_0),
        .O(\Head[100]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[101]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [77]),
        .I3(MemArray_reg_0_3_96_101_n_4),
        .I4(Head1__2_0),
        .O(\Head[101]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[102]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [78]),
        .I3(MemArray_reg_0_3_102_107_n_1),
        .I4(Head1__2_0),
        .O(\Head[102]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[103]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [79]),
        .I3(MemArray_reg_0_3_102_107_n_0),
        .I4(Head1__2_0),
        .O(\Head[103]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[104]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [80]),
        .I3(MemArray_reg_0_3_102_107_n_3),
        .I4(Head1__2_0),
        .O(\Head[104]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[105]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [81]),
        .I3(MemArray_reg_0_3_102_107_n_2),
        .I4(Head1__2_0),
        .O(\Head[105]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[106]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [82]),
        .I3(MemArray_reg_0_3_102_107_n_5),
        .I4(Head1__2_0),
        .O(\Head[106]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[107]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [83]),
        .I3(MemArray_reg_0_3_102_107_n_4),
        .I4(Head1__2_0),
        .O(\Head[107]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[108]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [84]),
        .I3(MemArray_reg_0_3_108_112_n_1),
        .I4(Head1__2_0),
        .O(\Head[108]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[109]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [85]),
        .I3(MemArray_reg_0_3_108_112_n_0),
        .I4(Head1__2_0),
        .O(\Head[109]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[10]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [6]),
        .I3(MemArray_reg_0_3_6_11_n_3),
        .I4(Head1__2_0),
        .O(\Head[10]_i_1__10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair454" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[10]_i_1__8 
       (.I0(Q[5]),
        .I1(Head1__2),
        .I2(Head0[1]),
        .O(D[1]));
  LUT5 #(
    .INIT(32'hEEEEEEEF)) 
    \Head[110]_i_1__8 
       (.I0(Head1__2_0),
        .I1(\RdPtr_reg[1]_0 ),
        .I2(FifoCntrRd[2]),
        .I3(FifoCntrRd[1]),
        .I4(FifoCntrRd[0]),
        .O(\Head[110]_i_1__8_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[110]_i_2 
       (.I0(\Head_reg[110]_1 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [86]),
        .I3(MemArray_reg_0_3_108_112_n_3),
        .I4(Head1__2_0),
        .O(\Head[110]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[11]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [7]),
        .I3(MemArray_reg_0_3_6_11_n_2),
        .I4(Head1__2_0),
        .O(\Head[11]_i_1__10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair455" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[11]_i_1__8 
       (.I0(Q[6]),
        .I1(Head1__2),
        .I2(Head0[2]),
        .O(D[2]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[12]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [8]),
        .I3(MemArray_reg_0_3_12_17_n_1),
        .I4(Head1__2_0),
        .O(\Head[12]_i_1__10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair455" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[12]_i_1__8 
       (.I0(Q[7]),
        .I1(Head1__2),
        .I2(Head0[3]),
        .O(D[3]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[13]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [9]),
        .I3(MemArray_reg_0_3_12_17_n_0),
        .I4(Head1__2_0),
        .O(\Head[13]_i_1__10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair456" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[13]_i_1__8 
       (.I0(Q[8]),
        .I1(Head1__2),
        .I2(Head0[4]),
        .O(D[4]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[14]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [10]),
        .I3(MemArray_reg_0_3_12_17_n_3),
        .I4(Head1__2_0),
        .O(\Head[14]_i_1__10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair456" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[14]_i_1__8 
       (.I0(Q[9]),
        .I1(Head1__2),
        .I2(Head0[5]),
        .O(D[5]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[15]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [11]),
        .I3(MemArray_reg_0_3_12_17_n_2),
        .I4(Head1__2_0),
        .O(\Head[15]_i_1__10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair457" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[15]_i_1__8 
       (.I0(Q[10]),
        .I1(Head1__2),
        .I2(Head0[6]),
        .O(D[6]));
  (* SOFT_HLUTNM = "soft_lutpair457" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[16]_i_1__7 
       (.I0(Q[11]),
        .I1(Head1__2),
        .I2(Head0[7]),
        .O(D[7]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[16]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [12]),
        .I3(MemArray_reg_0_3_12_17_n_5),
        .I4(Head1__2_0),
        .O(\Head[16]_i_1__9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair458" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[17]_i_1__6 
       (.I0(Q[12]),
        .I1(Head1__2),
        .I2(Head0[8]),
        .O(D[8]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[17]_i_1__8 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [13]),
        .I3(MemArray_reg_0_3_12_17_n_4),
        .I4(Head1__2_0),
        .O(\Head[17]_i_1__8_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[18]_i_1__11 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [14]),
        .I3(MemArray_reg_0_3_18_23_n_1),
        .I4(Head1__2_0),
        .O(\Head[18]_i_1__11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair458" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[18]_i_1__8 
       (.I0(Q[13]),
        .I1(Head1__2),
        .I2(Head0[9]),
        .O(D[9]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[19]_i_1__11 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [15]),
        .I3(MemArray_reg_0_3_18_23_n_0),
        .I4(Head1__2_0),
        .O(\Head[19]_i_1__11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair459" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[19]_i_1__8 
       (.I0(Q[14]),
        .I1(Head1__2),
        .I2(Head0[10]),
        .O(D[10]));
  (* SOFT_HLUTNM = "soft_lutpair454" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[1]_i_1__5 
       (.I0(Q[0]),
        .I1(Head1__2),
        .I2(Head0[0]),
        .O(D[0]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[20]_i_1__12 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [16]),
        .I3(MemArray_reg_0_3_18_23_n_3),
        .I4(Head1__2_0),
        .O(\Head[20]_i_1__12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair459" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[20]_i_1__9 
       (.I0(Q[15]),
        .I1(Head1__2),
        .I2(Head0[11]),
        .O(D[11]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[21]_i_1__12 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [17]),
        .I3(MemArray_reg_0_3_18_23_n_2),
        .I4(Head1__2_0),
        .O(\Head[21]_i_1__12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair460" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[21]_i_1__9 
       (.I0(Q[16]),
        .I1(Head1__2),
        .I2(Head0[12]),
        .O(D[12]));
  (* SOFT_HLUTNM = "soft_lutpair460" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[23]_i_1__7 
       (.I0(Q[23]),
        .I1(Head1__2),
        .I2(Head0[13]),
        .O(D[13]));
  (* SOFT_HLUTNM = "soft_lutpair461" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[24]_i_1__6 
       (.I0(Q[24]),
        .I1(Head1__2),
        .I2(Head0[14]),
        .O(D[14]));
  (* SOFT_HLUTNM = "soft_lutpair461" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[25]_i_1__6 
       (.I0(Q[25]),
        .I1(Head1__2),
        .I2(Head0[15]),
        .O(D[15]));
  (* SOFT_HLUTNM = "soft_lutpair462" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[26]_i_1__6 
       (.I0(Q[26]),
        .I1(Head1__2),
        .I2(Head0[16]),
        .O(D[16]));
  (* SOFT_HLUTNM = "soft_lutpair462" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[27]_i_1__6 
       (.I0(Q[27]),
        .I1(Head1__2),
        .I2(Head0[17]),
        .O(D[17]));
  (* SOFT_HLUTNM = "soft_lutpair463" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[28]_i_1__6 
       (.I0(Q[28]),
        .I1(Head1__2),
        .I2(Head0[18]),
        .O(D[18]));
  (* SOFT_HLUTNM = "soft_lutpair463" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[29]_i_1__6 
       (.I0(Q[1]),
        .I1(Head1__2),
        .I2(Head0[19]),
        .O(D[19]));
  (* SOFT_HLUTNM = "soft_lutpair464" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[30]_i_1__6 
       (.I0(Q[2]),
        .I1(Head1__2),
        .I2(Head0[20]),
        .O(D[20]));
  (* SOFT_HLUTNM = "soft_lutpair464" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[31]_i_1__5 
       (.I0(Q[3]),
        .I1(Head1__2),
        .I2(Head0[21]),
        .O(D[21]));
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[34]_i_2 
       (.I0(Q[4]),
        .I1(Head1__2),
        .I2(Head0[22]),
        .O(D[22]));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[37]_i_1__5 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [18]),
        .I3(MemArray_reg_0_3_36_41_n_0),
        .I4(Head1__2_0),
        .O(\Head[37]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[38]_i_1__5 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [19]),
        .I3(MemArray_reg_0_3_36_41_n_3),
        .I4(Head1__2_0),
        .O(\Head[38]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[39]_i_1__5 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [20]),
        .I3(MemArray_reg_0_3_36_41_n_2),
        .I4(Head1__2_0),
        .O(\Head[39]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[3]_i_1__6 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [1]),
        .I3(MemArray_reg_0_3_0_5_n_2),
        .I4(Head1__2_0),
        .O(\Head[3]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[40]_i_1__5 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [21]),
        .I3(MemArray_reg_0_3_36_41_n_5),
        .I4(Head1__2_0),
        .O(\Head[40]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[41]_i_1__5 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [22]),
        .I3(MemArray_reg_0_3_36_41_n_4),
        .I4(Head1__2_0),
        .O(\Head[41]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[47]_i_1__8 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [23]),
        .I3(MemArray_reg_0_3_42_47_n_2),
        .I4(Head1__2_0),
        .O(\Head[47]_i_1__8_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[48]_i_1__7 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [24]),
        .I3(MemArray_reg_0_3_48_53_n_1),
        .I4(Head1__2_0),
        .O(\Head[48]_i_1__7_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[49]_i_1__7 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [25]),
        .I3(MemArray_reg_0_3_48_53_n_0),
        .I4(Head1__2_0),
        .O(\Head[49]_i_1__7_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[4]_i_1__6 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [2]),
        .I3(MemArray_reg_0_3_0_5_n_5),
        .I4(Head1__2_0),
        .O(\Head[4]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[50]_i_1__7 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [26]),
        .I3(MemArray_reg_0_3_48_53_n_3),
        .I4(Head1__2_0),
        .O(\Head[50]_i_1__7_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[51]_i_1__7 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [27]),
        .I3(MemArray_reg_0_3_48_53_n_2),
        .I4(Head1__2_0),
        .O(\Head[51]_i_1__7_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[52]_i_1__5 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [28]),
        .I3(MemArray_reg_0_3_48_53_n_5),
        .I4(Head1__2_0),
        .O(\Head[52]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[53]_i_1__5 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [29]),
        .I3(MemArray_reg_0_3_48_53_n_4),
        .I4(Head1__2_0),
        .O(\Head[53]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[54]_i_1__5 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [30]),
        .I3(MemArray_reg_0_3_54_59_n_1),
        .I4(Head1__2_0),
        .O(\Head[54]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[55]_i_1__5 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [31]),
        .I3(MemArray_reg_0_3_54_59_n_0),
        .I4(Head1__2_0),
        .O(\Head[55]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[56]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [32]),
        .I3(MemArray_reg_0_3_54_59_n_3),
        .I4(Head1__2_0),
        .O(\Head[56]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[57]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [33]),
        .I3(MemArray_reg_0_3_54_59_n_2),
        .I4(Head1__2_0),
        .O(\Head[57]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[58]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [34]),
        .I3(MemArray_reg_0_3_54_59_n_5),
        .I4(Head1__2_0),
        .O(\Head[58]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[59]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [35]),
        .I3(MemArray_reg_0_3_54_59_n_4),
        .I4(Head1__2_0),
        .O(\Head[59]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[5]_i_1__6 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [3]),
        .I3(MemArray_reg_0_3_0_5_n_4),
        .I4(Head1__2_0),
        .O(\Head[5]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[60]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [36]),
        .I3(MemArray_reg_0_3_60_65_n_1),
        .I4(Head1__2_0),
        .O(\Head[60]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[61]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [37]),
        .I3(MemArray_reg_0_3_60_65_n_0),
        .I4(Head1__2_0),
        .O(\Head[61]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[62]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [38]),
        .I3(MemArray_reg_0_3_60_65_n_3),
        .I4(Head1__2_0),
        .O(\Head[62]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[63]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [39]),
        .I3(MemArray_reg_0_3_60_65_n_2),
        .I4(Head1__2_0),
        .O(\Head[63]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[64]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [40]),
        .I3(MemArray_reg_0_3_60_65_n_5),
        .I4(Head1__2_0),
        .O(\Head[64]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[65]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [41]),
        .I3(MemArray_reg_0_3_60_65_n_4),
        .I4(Head1__2_0),
        .O(\Head[65]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[66]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [42]),
        .I3(MemArray_reg_0_3_66_71_n_1),
        .I4(Head1__2_0),
        .O(\Head[66]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[67]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [43]),
        .I3(MemArray_reg_0_3_66_71_n_0),
        .I4(Head1__2_0),
        .O(\Head[67]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[68]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [44]),
        .I3(MemArray_reg_0_3_66_71_n_3),
        .I4(Head1__2_0),
        .O(\Head[68]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[69]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [45]),
        .I3(MemArray_reg_0_3_66_71_n_2),
        .I4(Head1__2_0),
        .O(\Head[69]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[70]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [46]),
        .I3(MemArray_reg_0_3_66_71_n_5),
        .I4(Head1__2_0),
        .O(\Head[70]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[71]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [47]),
        .I3(MemArray_reg_0_3_66_71_n_4),
        .I4(Head1__2_0),
        .O(\Head[71]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[72]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [48]),
        .I3(MemArray_reg_0_3_72_77_n_1),
        .I4(Head1__2_0),
        .O(\Head[72]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[73]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [49]),
        .I3(MemArray_reg_0_3_72_77_n_0),
        .I4(Head1__2_0),
        .O(\Head[73]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[74]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [50]),
        .I3(MemArray_reg_0_3_72_77_n_3),
        .I4(Head1__2_0),
        .O(\Head[74]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[75]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [51]),
        .I3(MemArray_reg_0_3_72_77_n_2),
        .I4(Head1__2_0),
        .O(\Head[75]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[76]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [52]),
        .I3(MemArray_reg_0_3_72_77_n_5),
        .I4(Head1__2_0),
        .O(\Head[76]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[77]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [53]),
        .I3(MemArray_reg_0_3_72_77_n_4),
        .I4(Head1__2_0),
        .O(\Head[77]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[78]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [54]),
        .I3(MemArray_reg_0_3_78_83_n_1),
        .I4(Head1__2_0),
        .O(\Head[78]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[79]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [55]),
        .I3(MemArray_reg_0_3_78_83_n_0),
        .I4(Head1__2_0),
        .O(\Head[79]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[80]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [56]),
        .I3(MemArray_reg_0_3_78_83_n_3),
        .I4(Head1__2_0),
        .O(\Head[80]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[81]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [57]),
        .I3(MemArray_reg_0_3_78_83_n_2),
        .I4(Head1__2_0),
        .O(\Head[81]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[82]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [58]),
        .I3(MemArray_reg_0_3_78_83_n_5),
        .I4(Head1__2_0),
        .O(\Head[82]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[83]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [59]),
        .I3(MemArray_reg_0_3_78_83_n_4),
        .I4(Head1__2_0),
        .O(\Head[83]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[84]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [60]),
        .I3(MemArray_reg_0_3_84_89_n_1),
        .I4(Head1__2_0),
        .O(\Head[84]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[85]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [61]),
        .I3(MemArray_reg_0_3_84_89_n_0),
        .I4(Head1__2_0),
        .O(\Head[85]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[86]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [62]),
        .I3(MemArray_reg_0_3_84_89_n_3),
        .I4(Head1__2_0),
        .O(\Head[86]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[87]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [63]),
        .I3(MemArray_reg_0_3_84_89_n_2),
        .I4(Head1__2_0),
        .O(\Head[87]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[88]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [64]),
        .I3(MemArray_reg_0_3_84_89_n_5),
        .I4(Head1__2_0),
        .O(\Head[88]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[89]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [65]),
        .I3(MemArray_reg_0_3_84_89_n_4),
        .I4(Head1__2_0),
        .O(\Head[89]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[8]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [4]),
        .I3(MemArray_reg_0_3_6_11_n_1),
        .I4(Head1__2_0),
        .O(\Head[8]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[90]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [66]),
        .I3(MemArray_reg_0_3_90_95_n_1),
        .I4(Head1__2_0),
        .O(\Head[90]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[91]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [67]),
        .I3(MemArray_reg_0_3_90_95_n_0),
        .I4(Head1__2_0),
        .O(\Head[91]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[92]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [68]),
        .I3(MemArray_reg_0_3_90_95_n_3),
        .I4(Head1__2_0),
        .O(\Head[92]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[93]_i_1__10 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [69]),
        .I3(MemArray_reg_0_3_90_95_n_2),
        .I4(Head1__2_0),
        .O(\Head[93]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[94]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [70]),
        .I3(MemArray_reg_0_3_90_95_n_5),
        .I4(Head1__2_0),
        .O(\Head[94]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[95]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [71]),
        .I3(MemArray_reg_0_3_90_95_n_4),
        .I4(Head1__2_0),
        .O(\Head[95]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[96]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [72]),
        .I3(MemArray_reg_0_3_96_101_n_1),
        .I4(Head1__2_0),
        .O(\Head[96]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[97]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [73]),
        .I3(MemArray_reg_0_3_96_101_n_0),
        .I4(Head1__2_0),
        .O(\Head[97]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[98]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [74]),
        .I3(MemArray_reg_0_3_96_101_n_3),
        .I4(Head1__2_0),
        .O(\Head[98]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[99]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [75]),
        .I3(MemArray_reg_0_3_96_101_n_2),
        .I4(Head1__2_0),
        .O(\Head[99]_i_1__9_n_0 ));
  LUT5 #(
    .INIT(32'h1010FF00)) 
    \Head[9]_i_1__9 
       (.I0(\Head_reg[0]_0 ),
        .I1(almost_full_ff_reg_0),
        .I2(\Head_reg[110]_0 [5]),
        .I3(MemArray_reg_0_3_6_11_n_0),
        .I4(Head1__2_0),
        .O(\Head[9]_i_1__9_n_0 ));
  FDRE \Head_reg[0] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[0]_i_1__8_n_0 ),
        .Q(Q[0]),
        .R(SR));
  FDRE \Head_reg[100] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[100]_i_1__9_n_0 ),
        .Q(Q[76]),
        .R(SR));
  FDRE \Head_reg[101] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[101]_i_1__9_n_0 ),
        .Q(Q[77]),
        .R(SR));
  FDRE \Head_reg[102] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[102]_i_1__9_n_0 ),
        .Q(Q[78]),
        .R(SR));
  FDRE \Head_reg[103] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[103]_i_1__9_n_0 ),
        .Q(Q[79]),
        .R(SR));
  FDRE \Head_reg[104] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[104]_i_1__9_n_0 ),
        .Q(Q[80]),
        .R(SR));
  FDRE \Head_reg[105] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[105]_i_1__9_n_0 ),
        .Q(Q[81]),
        .R(SR));
  FDRE \Head_reg[106] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[106]_i_1__9_n_0 ),
        .Q(Q[82]),
        .R(SR));
  FDRE \Head_reg[107] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[107]_i_1__9_n_0 ),
        .Q(Q[83]),
        .R(SR));
  FDRE \Head_reg[108] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[108]_i_1__9_n_0 ),
        .Q(Q[84]),
        .R(SR));
  FDRE \Head_reg[109] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[109]_i_1__9_n_0 ),
        .Q(Q[85]),
        .R(SR));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[10]_i_1__10_n_0 ),
        .Q(Q[6]),
        .R(SR));
  FDRE \Head_reg[110] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[110]_i_2_n_0 ),
        .Q(Q[86]),
        .R(SR));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[11]_i_1__10_n_0 ),
        .Q(Q[7]),
        .R(SR));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[12]_i_1__10_n_0 ),
        .Q(Q[8]),
        .R(SR));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[13]_i_1__10_n_0 ),
        .Q(Q[9]),
        .R(SR));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[14]_i_1__10_n_0 ),
        .Q(Q[10]),
        .R(SR));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[15]_i_1__10_n_0 ),
        .Q(Q[11]),
        .R(SR));
  FDRE \Head_reg[16] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[16]_i_1__9_n_0 ),
        .Q(Q[12]),
        .R(SR));
  FDRE \Head_reg[17] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[17]_i_1__8_n_0 ),
        .Q(Q[13]),
        .R(SR));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[18]_i_1__11_n_0 ),
        .Q(Q[14]),
        .R(SR));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[19]_i_1__11_n_0 ),
        .Q(Q[15]),
        .R(SR));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[20]_i_1__12_n_0 ),
        .Q(Q[16]),
        .R(SR));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[21]_i_1__12_n_0 ),
        .Q(Q[17]),
        .R(SR));
  FDRE \Head_reg[37] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[37]_i_1__5_n_0 ),
        .Q(Q[18]),
        .R(SR));
  FDRE \Head_reg[38] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[38]_i_1__5_n_0 ),
        .Q(Q[19]),
        .R(SR));
  FDRE \Head_reg[39] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[39]_i_1__5_n_0 ),
        .Q(Q[20]),
        .R(SR));
  FDRE \Head_reg[3] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[3]_i_1__6_n_0 ),
        .Q(Q[1]),
        .R(SR));
  FDRE \Head_reg[40] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[40]_i_1__5_n_0 ),
        .Q(Q[21]),
        .R(SR));
  FDRE \Head_reg[41] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[41]_i_1__5_n_0 ),
        .Q(Q[22]),
        .R(SR));
  FDRE \Head_reg[47] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[47]_i_1__8_n_0 ),
        .Q(Q[23]),
        .R(SR));
  FDRE \Head_reg[48] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[48]_i_1__7_n_0 ),
        .Q(Q[24]),
        .R(SR));
  FDRE \Head_reg[49] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[49]_i_1__7_n_0 ),
        .Q(Q[25]),
        .R(SR));
  FDRE \Head_reg[4] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[4]_i_1__6_n_0 ),
        .Q(Q[2]),
        .R(SR));
  FDRE \Head_reg[50] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[50]_i_1__7_n_0 ),
        .Q(Q[26]),
        .R(SR));
  FDRE \Head_reg[51] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[51]_i_1__7_n_0 ),
        .Q(Q[27]),
        .R(SR));
  FDRE \Head_reg[52] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[52]_i_1__5_n_0 ),
        .Q(Q[28]),
        .R(SR));
  FDRE \Head_reg[53] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[53]_i_1__5_n_0 ),
        .Q(Q[29]),
        .R(SR));
  FDRE \Head_reg[54] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[54]_i_1__5_n_0 ),
        .Q(Q[30]),
        .R(SR));
  FDRE \Head_reg[55] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[55]_i_1__5_n_0 ),
        .Q(Q[31]),
        .R(SR));
  FDRE \Head_reg[56] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[56]_i_1__9_n_0 ),
        .Q(Q[32]),
        .R(SR));
  FDRE \Head_reg[57] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[57]_i_1__9_n_0 ),
        .Q(Q[33]),
        .R(SR));
  FDRE \Head_reg[58] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[58]_i_1__9_n_0 ),
        .Q(Q[34]),
        .R(SR));
  FDRE \Head_reg[59] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[59]_i_1__9_n_0 ),
        .Q(Q[35]),
        .R(SR));
  FDRE \Head_reg[5] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[5]_i_1__6_n_0 ),
        .Q(Q[3]),
        .R(SR));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[60]_i_1__10_n_0 ),
        .Q(Q[36]),
        .R(SR));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[61]_i_1__10_n_0 ),
        .Q(Q[37]),
        .R(SR));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[62]_i_1__10_n_0 ),
        .Q(Q[38]),
        .R(SR));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[63]_i_1__10_n_0 ),
        .Q(Q[39]),
        .R(SR));
  FDRE \Head_reg[64] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[64]_i_1__9_n_0 ),
        .Q(Q[40]),
        .R(SR));
  FDRE \Head_reg[65] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[65]_i_1__9_n_0 ),
        .Q(Q[41]),
        .R(SR));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[66]_i_1__10_n_0 ),
        .Q(Q[42]),
        .R(SR));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[67]_i_1__10_n_0 ),
        .Q(Q[43]),
        .R(SR));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[68]_i_1__10_n_0 ),
        .Q(Q[44]),
        .R(SR));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[69]_i_1__10_n_0 ),
        .Q(Q[45]),
        .R(SR));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[70]_i_1__10_n_0 ),
        .Q(Q[46]),
        .R(SR));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[71]_i_1__10_n_0 ),
        .Q(Q[47]),
        .R(SR));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[72]_i_1__10_n_0 ),
        .Q(Q[48]),
        .R(SR));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[73]_i_1__10_n_0 ),
        .Q(Q[49]),
        .R(SR));
  FDRE \Head_reg[74] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[74]_i_1__9_n_0 ),
        .Q(Q[50]),
        .R(SR));
  FDRE \Head_reg[75] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[75]_i_1__9_n_0 ),
        .Q(Q[51]),
        .R(SR));
  FDRE \Head_reg[76] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[76]_i_1__9_n_0 ),
        .Q(Q[52]),
        .R(SR));
  FDRE \Head_reg[77] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[77]_i_1__9_n_0 ),
        .Q(Q[53]),
        .R(SR));
  FDRE \Head_reg[78] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[78]_i_1__9_n_0 ),
        .Q(Q[54]),
        .R(SR));
  FDRE \Head_reg[79] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[79]_i_1__9_n_0 ),
        .Q(Q[55]),
        .R(SR));
  FDRE \Head_reg[80] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[80]_i_1__9_n_0 ),
        .Q(Q[56]),
        .R(SR));
  FDRE \Head_reg[81] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[81]_i_1__9_n_0 ),
        .Q(Q[57]),
        .R(SR));
  FDRE \Head_reg[82] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[82]_i_1__9_n_0 ),
        .Q(Q[58]),
        .R(SR));
  FDRE \Head_reg[83] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[83]_i_1__9_n_0 ),
        .Q(Q[59]),
        .R(SR));
  FDRE \Head_reg[84] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[84]_i_1__9_n_0 ),
        .Q(Q[60]),
        .R(SR));
  FDRE \Head_reg[85] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[85]_i_1__9_n_0 ),
        .Q(Q[61]),
        .R(SR));
  FDRE \Head_reg[86] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[86]_i_1__9_n_0 ),
        .Q(Q[62]),
        .R(SR));
  FDRE \Head_reg[87] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[87]_i_1__9_n_0 ),
        .Q(Q[63]),
        .R(SR));
  FDRE \Head_reg[88] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[88]_i_1__9_n_0 ),
        .Q(Q[64]),
        .R(SR));
  FDRE \Head_reg[89] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[89]_i_1__9_n_0 ),
        .Q(Q[65]),
        .R(SR));
  FDRE \Head_reg[8] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[8]_i_1__9_n_0 ),
        .Q(Q[4]),
        .R(SR));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[90]_i_1__10_n_0 ),
        .Q(Q[66]),
        .R(SR));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[91]_i_1__10_n_0 ),
        .Q(Q[67]),
        .R(SR));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[92]_i_1__10_n_0 ),
        .Q(Q[68]),
        .R(SR));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[93]_i_1__10_n_0 ),
        .Q(Q[69]),
        .R(SR));
  FDRE \Head_reg[94] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[94]_i_1__9_n_0 ),
        .Q(Q[70]),
        .R(SR));
  FDRE \Head_reg[95] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[95]_i_1__9_n_0 ),
        .Q(Q[71]),
        .R(SR));
  FDRE \Head_reg[96] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[96]_i_1__9_n_0 ),
        .Q(Q[72]),
        .R(SR));
  FDRE \Head_reg[97] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[97]_i_1__9_n_0 ),
        .Q(Q[73]),
        .R(SR));
  FDRE \Head_reg[98] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[98]_i_1__9_n_0 ),
        .Q(Q[74]),
        .R(SR));
  FDRE \Head_reg[99] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[99]_i_1__9_n_0 ),
        .Q(Q[75]),
        .R(SR));
  FDRE \Head_reg[9] 
       (.C(user_clk),
        .CE(\Head[110]_i_1__8_n_0 ),
        .D(\Head[9]_i_1__9_n_0 ),
        .Q(Q[5]),
        .R(SR));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_3_0_5
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[1:0]),
        .DIB(payloadmuxed[3:2]),
        .DIC(payloadmuxed[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_0_5_n_0,MemArray_reg_0_3_0_5_n_1}),
        .DOB({MemArray_reg_0_3_0_5_n_2,MemArray_reg_0_3_0_5_n_3}),
        .DOC({MemArray_reg_0_3_0_5_n_4,MemArray_reg_0_3_0_5_n_5}),
        .DOD(NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_102_107" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "102" *) 
  (* ram_slice_end = "107" *) 
  RAM32M MemArray_reg_0_3_102_107
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[83:82]),
        .DIB(payloadmuxed[85:84]),
        .DIC(payloadmuxed[87:86]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_102_107_n_0,MemArray_reg_0_3_102_107_n_1}),
        .DOB({MemArray_reg_0_3_102_107_n_2,MemArray_reg_0_3_102_107_n_3}),
        .DOC({MemArray_reg_0_3_102_107_n_4,MemArray_reg_0_3_102_107_n_5}),
        .DOD(NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "108" *) 
  (* ram_slice_end = "112" *) 
  RAM32M MemArray_reg_0_3_108_112
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[89:88]),
        .DIB(payloadmuxed[91:90]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_108_112_n_0,MemArray_reg_0_3_108_112_n_1}),
        .DOB({MemArray_reg_0_3_108_112_n_2,MemArray_reg_0_3_108_112_n_3}),
        .DOC(NLW_MemArray_reg_0_3_108_112_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_108_112_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[11:10]),
        .DIB(payloadmuxed[13:12]),
        .DIC(payloadmuxed[15:14]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_12_17_n_0,MemArray_reg_0_3_12_17_n_1}),
        .DOB({MemArray_reg_0_3_12_17_n_2,MemArray_reg_0_3_12_17_n_3}),
        .DOC({MemArray_reg_0_3_12_17_n_4,MemArray_reg_0_3_12_17_n_5}),
        .DOD(NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[17:16]),
        .DIB(payloadmuxed[19:18]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_18_23_n_0,MemArray_reg_0_3_18_23_n_1}),
        .DOB({MemArray_reg_0_3_18_23_n_2,MemArray_reg_0_3_18_23_n_3}),
        .DOC({MemArray_reg_0_3_18_23_n_4,MemArray_reg_0_3_18_23_n_5}),
        .DOD(NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_36_41" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M MemArray_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[21:20]),
        .DIB(payloadmuxed[23:22]),
        .DIC(payloadmuxed[25:24]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_36_41_n_0,MemArray_reg_0_3_36_41_n_1}),
        .DOB({MemArray_reg_0_3_36_41_n_2,MemArray_reg_0_3_36_41_n_3}),
        .DOC({MemArray_reg_0_3_36_41_n_4,MemArray_reg_0_3_36_41_n_5}),
        .DOD(NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_42_47" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M MemArray_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({1'b0,1'b0}),
        .DIB(payloadmuxed[27:26]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_42_47_n_0,NLW_MemArray_reg_0_3_42_47_DOA_UNCONNECTED[0]}),
        .DOB({MemArray_reg_0_3_42_47_n_2,MemArray_reg_0_3_42_47_n_3}),
        .DOC(NLW_MemArray_reg_0_3_42_47_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_48_53" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M MemArray_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[29:28]),
        .DIB(payloadmuxed[31:30]),
        .DIC(payloadmuxed[33:32]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_48_53_n_0,MemArray_reg_0_3_48_53_n_1}),
        .DOB({MemArray_reg_0_3_48_53_n_2,MemArray_reg_0_3_48_53_n_3}),
        .DOC({MemArray_reg_0_3_48_53_n_4,MemArray_reg_0_3_48_53_n_5}),
        .DOD(NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_54_59" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M MemArray_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[35:34]),
        .DIB(payloadmuxed[37:36]),
        .DIC(payloadmuxed[39:38]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_54_59_n_0,MemArray_reg_0_3_54_59_n_1}),
        .DOB({MemArray_reg_0_3_54_59_n_2,MemArray_reg_0_3_54_59_n_3}),
        .DOC({MemArray_reg_0_3_54_59_n_4,MemArray_reg_0_3_54_59_n_5}),
        .DOD(NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_60_65" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M MemArray_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[41:40]),
        .DIB(payloadmuxed[43:42]),
        .DIC(payloadmuxed[45:44]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_60_65_n_0,MemArray_reg_0_3_60_65_n_1}),
        .DOB({MemArray_reg_0_3_60_65_n_2,MemArray_reg_0_3_60_65_n_3}),
        .DOC({MemArray_reg_0_3_60_65_n_4,MemArray_reg_0_3_60_65_n_5}),
        .DOD(NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_66_71" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M MemArray_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[47:46]),
        .DIB(payloadmuxed[49:48]),
        .DIC(payloadmuxed[51:50]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_66_71_n_0,MemArray_reg_0_3_66_71_n_1}),
        .DOB({MemArray_reg_0_3_66_71_n_2,MemArray_reg_0_3_66_71_n_3}),
        .DOC({MemArray_reg_0_3_66_71_n_4,MemArray_reg_0_3_66_71_n_5}),
        .DOD(NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[7:6]),
        .DIB(payloadmuxed[9:8]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_6_11_n_0,MemArray_reg_0_3_6_11_n_1}),
        .DOB({MemArray_reg_0_3_6_11_n_2,MemArray_reg_0_3_6_11_n_3}),
        .DOC(NLW_MemArray_reg_0_3_6_11_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_72_77" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M MemArray_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[53:52]),
        .DIB(payloadmuxed[55:54]),
        .DIC(payloadmuxed[57:56]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_72_77_n_0,MemArray_reg_0_3_72_77_n_1}),
        .DOB({MemArray_reg_0_3_72_77_n_2,MemArray_reg_0_3_72_77_n_3}),
        .DOC({MemArray_reg_0_3_72_77_n_4,MemArray_reg_0_3_72_77_n_5}),
        .DOD(NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_78_83" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "83" *) 
  RAM32M MemArray_reg_0_3_78_83
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[59:58]),
        .DIB(payloadmuxed[61:60]),
        .DIC(payloadmuxed[63:62]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_78_83_n_0,MemArray_reg_0_3_78_83_n_1}),
        .DOB({MemArray_reg_0_3_78_83_n_2,MemArray_reg_0_3_78_83_n_3}),
        .DOC({MemArray_reg_0_3_78_83_n_4,MemArray_reg_0_3_78_83_n_5}),
        .DOD(NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_84_89" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "84" *) 
  (* ram_slice_end = "89" *) 
  RAM32M MemArray_reg_0_3_84_89
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[65:64]),
        .DIB(payloadmuxed[67:66]),
        .DIC(payloadmuxed[69:68]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_84_89_n_0,MemArray_reg_0_3_84_89_n_1}),
        .DOB({MemArray_reg_0_3_84_89_n_2,MemArray_reg_0_3_84_89_n_3}),
        .DOC({MemArray_reg_0_3_84_89_n_4,MemArray_reg_0_3_84_89_n_5}),
        .DOD(NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_90_95" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "90" *) 
  (* ram_slice_end = "95" *) 
  RAM32M MemArray_reg_0_3_90_95
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[71:70]),
        .DIB(payloadmuxed[73:72]),
        .DIC(payloadmuxed[75:74]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_90_95_n_0,MemArray_reg_0_3_90_95_n_1}),
        .DOB({MemArray_reg_0_3_90_95_n_2,MemArray_reg_0_3_90_95_n_3}),
        .DOC({MemArray_reg_0_3_90_95_n_4,MemArray_reg_0_3_90_95_n_5}),
        .DOD(NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "452" *) 
  (* RTL_RAM_NAME = "axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_96_101" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "96" *) 
  (* ram_slice_end = "101" *) 
  RAM32M MemArray_reg_0_3_96_101
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[77:76]),
        .DIB(payloadmuxed[79:78]),
        .DIC(payloadmuxed[81:80]),
        .DID({1'b0,1'b0}),
        .DOA({MemArray_reg_0_3_96_101_n_0,MemArray_reg_0_3_96_101_n_1}),
        .DOB({MemArray_reg_0_3_96_101_n_2,MemArray_reg_0_3_96_101_n_3}),
        .DOC({MemArray_reg_0_3_96_101_n_4,MemArray_reg_0_3_96_101_n_5}),
        .DOD(NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(p_15_in));
  LUT6 #(
    .INIT(64'h5557777755544444)) 
    \RdPtr[0]_i_1 
       (.I0(RdPtr[0]),
        .I1(Head1__2_0),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[2]),
        .I4(\RdPtr_reg[1]_0 ),
        .I5(RdPtr[0]),
        .O(\RdPtr[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0FF01FE00FF0FF00)) 
    \RdPtr[1]_i_1__19 
       (.I0(FifoCntrRd[1]),
        .I1(FifoCntrRd[2]),
        .I2(RdPtr[0]),
        .I3(RdPtr[1]),
        .I4(Head1__2_0),
        .I5(\RdPtr_reg[1]_0 ),
        .O(\RdPtr[1]_i_1__19_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000050001)) 
    \RdPtr[1]_i_2__8 
       (.I0(\FifoCntrWr_reg[0]_0 ),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[2]),
        .I3(FifoCntrRd[1]),
        .I4(\RdPtr_reg[1]_0 ),
        .I5(almost_full_ff_reg_0),
        .O(Head1__2_0));
  (* MAX_FANOUT = "128" *) 
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1_n_0 ),
        .Q(RdPtr[0]),
        .R(SR));
  (* MAX_FANOUT = "128" *) 
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[1]_i_1__19_n_0 ),
        .Q(RdPtr[1]),
        .R(SR));
  LUT4 #(
    .INIT(16'hFB01)) 
    \WrPtr[0]_i_1__18 
       (.I0(\FifoCntrWr_reg[0]_0 ),
        .I1(WrPtr[0]),
        .I2(almost_full_ff_reg_0),
        .I3(WrPtr[0]),
        .O(\WrPtr[0]_i_1__18_n_0 ));
  LUT5 #(
    .INIT(32'hFFBE0014)) 
    \WrPtr[1]_i_1__18 
       (.I0(\FifoCntrWr_reg[0]_0 ),
        .I1(WrPtr[0]),
        .I2(WrPtr[1]),
        .I3(almost_full_ff_reg_0),
        .I4(WrPtr[1]),
        .O(\WrPtr[1]_i_1__18_n_0 ));
  (* MAX_FANOUT = "128" *) 
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[0]_i_1__18_n_0 ),
        .Q(WrPtr[0]),
        .R(SR));
  (* MAX_FANOUT = "128" *) 
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[1]_i_1__18_n_0 ),
        .Q(WrPtr[1]),
        .R(SR));
  LUT3 #(
    .INIT(8'hF8)) 
    almost_full_ff_i_1__6
       (.I0(FifoCntrWr[1]),
        .I1(FifoCntrWr[0]),
        .I2(FifoCntrWr[2]),
        .O(almost_full_ff_i_1__6_n_0));
  FDRE almost_full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(almost_full_ff_i_1__6_n_0),
        .Q(almost_full_ff_reg_0),
        .R(SR));
  LUT5 #(
    .INIT(32'h555555DF)) 
    empty_ff_i_1__20
       (.I0(user_rst_n_3ff_reg),
        .I1(\RdPtr_reg[1]_0 ),
        .I2(FifoCntrRd[0]),
        .I3(FifoCntrRd[1]),
        .I4(FifoCntrRd[2]),
        .O(empty_ff_i_1__20_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__20_n_0),
        .Q(empty_ff_reg_0),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    m_axi_awaddrq_reg_0_15_0_5_i_1
       (.I0(empty_ff_reg_0),
        .O(wmreqset));
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    m_axi_awlenq_reg_0_15_0_5_i_1
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_7_n_4),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_7_n_6),
        .I2(m_axi_awlenq_reg_0_15_0_5_i_7_n_7),
        .I3(m_axi_awlenq_reg_0_15_0_5_i_7_n_5),
        .I4(m_axi_awlenq_reg_0_15_0_5_i_8_n_7),
        .O(tlp_dstbt_len[1]));
  LUT2 #(
    .INIT(4'h2)) 
    m_axi_awlenq_reg_0_15_0_5_i_10
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_8_n_5),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_16_n_0),
        .O(m_axi_awlenq_reg_0_15_0_5_i_10_n_0));
  CARRY4 m_axi_awlenq_reg_0_15_0_5_i_11
       (.CI(m_axi_awlenq_reg_0_15_0_5_i_8_n_0),
        .CO({m_axi_awlenq_reg_0_15_0_5_i_11_n_0,m_axi_awlenq_reg_0_15_0_5_i_11_n_1,m_axi_awlenq_reg_0_15_0_5_i_11_n_2,m_axi_awlenq_reg_0_15_0_5_i_11_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({m_axi_awlenq_reg_0_15_0_5_i_11_n_4,m_axi_awlenq_reg_0_15_0_5_i_11_n_5,m_axi_awlenq_reg_0_15_0_5_i_11_n_6,m_axi_awlenq_reg_0_15_0_5_i_11_n_7}),
        .S(Q[16:13]));
  LUT5 #(
    .INIT(32'h7FFFFFFE)) 
    m_axi_awlenq_reg_0_15_0_5_i_12
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_8_n_5),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_8_n_7),
        .I2(m_axi_awlenq_reg_0_15_0_5_i_9_n_0),
        .I3(m_axi_awlenq_reg_0_15_0_5_i_7_n_4),
        .I4(m_axi_awlenq_reg_0_15_0_5_i_8_n_6),
        .O(m_axi_awlenq_reg_0_15_0_5_i_12_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    m_axi_awlenq_reg_0_15_0_5_i_13
       (.I0(Q[7]),
        .I1(Q[25]),
        .O(m_axi_awlenq_reg_0_15_0_5_i_13_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    m_axi_awlenq_reg_0_15_0_5_i_14
       (.I0(Q[6]),
        .I1(Q[24]),
        .O(m_axi_awlenq_reg_0_15_0_5_i_14_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    m_axi_awlenq_reg_0_15_0_5_i_15
       (.I0(Q[5]),
        .I1(Q[23]),
        .O(m_axi_awlenq_reg_0_15_0_5_i_15_n_0));
  LUT6 #(
    .INIT(64'h5557FFFFFFFFFFFF)) 
    m_axi_awlenq_reg_0_15_0_5_i_16
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_8_n_7),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_7_n_5),
        .I2(m_axi_awlenq_reg_0_15_0_5_i_7_n_7),
        .I3(m_axi_awlenq_reg_0_15_0_5_i_7_n_6),
        .I4(m_axi_awlenq_reg_0_15_0_5_i_7_n_4),
        .I5(m_axi_awlenq_reg_0_15_0_5_i_8_n_6),
        .O(m_axi_awlenq_reg_0_15_0_5_i_16_n_0));
  LUT4 #(
    .INIT(16'hFE01)) 
    m_axi_awlenq_reg_0_15_0_5_i_2
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_7_n_6),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_7_n_7),
        .I2(m_axi_awlenq_reg_0_15_0_5_i_7_n_5),
        .I3(m_axi_awlenq_reg_0_15_0_5_i_7_n_4),
        .O(tlp_dstbt_len[0]));
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    m_axi_awlenq_reg_0_15_0_5_i_3
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_8_n_6),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_7_n_4),
        .I2(m_axi_awlenq_reg_0_15_0_5_i_9_n_0),
        .I3(m_axi_awlenq_reg_0_15_0_5_i_8_n_7),
        .I4(m_axi_awlenq_reg_0_15_0_5_i_8_n_5),
        .O(tlp_dstbt_len[3]));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    m_axi_awlenq_reg_0_15_0_5_i_4
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_8_n_7),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_7_n_5),
        .I2(m_axi_awlenq_reg_0_15_0_5_i_7_n_7),
        .I3(m_axi_awlenq_reg_0_15_0_5_i_7_n_6),
        .I4(m_axi_awlenq_reg_0_15_0_5_i_7_n_4),
        .I5(m_axi_awlenq_reg_0_15_0_5_i_8_n_6),
        .O(tlp_dstbt_len[2]));
  LUT4 #(
    .INIT(16'h78E1)) 
    m_axi_awlenq_reg_0_15_0_5_i_5
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_8_n_4),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_10_n_0),
        .I2(m_axi_awlenq_reg_0_15_0_5_i_11_n_7),
        .I3(m_axi_awlenq_reg_0_15_0_5_i_12_n_0),
        .O(tlp_dstbt_len[5]));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    m_axi_awlenq_reg_0_15_0_5_i_6
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_8_n_7),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_9_n_0),
        .I2(m_axi_awlenq_reg_0_15_0_5_i_7_n_4),
        .I3(m_axi_awlenq_reg_0_15_0_5_i_8_n_6),
        .I4(m_axi_awlenq_reg_0_15_0_5_i_8_n_5),
        .I5(m_axi_awlenq_reg_0_15_0_5_i_8_n_4),
        .O(tlp_dstbt_len[4]));
  CARRY4 m_axi_awlenq_reg_0_15_0_5_i_7
       (.CI(1'b0),
        .CO({m_axi_awlenq_reg_0_15_0_5_i_7_n_0,m_axi_awlenq_reg_0_15_0_5_i_7_n_1,m_axi_awlenq_reg_0_15_0_5_i_7_n_2,m_axi_awlenq_reg_0_15_0_5_i_7_n_3}),
        .CYINIT(1'b0),
        .DI(Q[8:5]),
        .O({m_axi_awlenq_reg_0_15_0_5_i_7_n_4,m_axi_awlenq_reg_0_15_0_5_i_7_n_5,m_axi_awlenq_reg_0_15_0_5_i_7_n_6,m_axi_awlenq_reg_0_15_0_5_i_7_n_7}),
        .S({Q[8],m_axi_awlenq_reg_0_15_0_5_i_13_n_0,m_axi_awlenq_reg_0_15_0_5_i_14_n_0,m_axi_awlenq_reg_0_15_0_5_i_15_n_0}));
  CARRY4 m_axi_awlenq_reg_0_15_0_5_i_8
       (.CI(m_axi_awlenq_reg_0_15_0_5_i_7_n_0),
        .CO({m_axi_awlenq_reg_0_15_0_5_i_8_n_0,m_axi_awlenq_reg_0_15_0_5_i_8_n_1,m_axi_awlenq_reg_0_15_0_5_i_8_n_2,m_axi_awlenq_reg_0_15_0_5_i_8_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,Q[10:9]}),
        .O({m_axi_awlenq_reg_0_15_0_5_i_8_n_4,m_axi_awlenq_reg_0_15_0_5_i_8_n_5,m_axi_awlenq_reg_0_15_0_5_i_8_n_6,m_axi_awlenq_reg_0_15_0_5_i_8_n_7}),
        .S(Q[12:9]));
  LUT3 #(
    .INIT(8'hFE)) 
    m_axi_awlenq_reg_0_15_0_5_i_9
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_7_n_6),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_7_n_7),
        .I2(m_axi_awlenq_reg_0_15_0_5_i_7_n_5),
        .O(m_axi_awlenq_reg_0_15_0_5_i_9_n_0));
  LUT6 #(
    .INIT(64'h6CCCCCCCCCCCCCC9)) 
    m_axi_awlenq_reg_0_15_6_7_i_1
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_12_n_0),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_11_n_5),
        .I2(m_axi_awlenq_reg_0_15_0_5_i_11_n_7),
        .I3(m_axi_awlenq_reg_0_15_0_5_i_10_n_0),
        .I4(m_axi_awlenq_reg_0_15_0_5_i_8_n_4),
        .I5(m_axi_awlenq_reg_0_15_0_5_i_11_n_6),
        .O(tlp_dstbt_len[7]));
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    m_axi_awlenq_reg_0_15_6_7_i_2
       (.I0(m_axi_awlenq_reg_0_15_0_5_i_11_n_7),
        .I1(m_axi_awlenq_reg_0_15_0_5_i_10_n_0),
        .I2(m_axi_awlenq_reg_0_15_0_5_i_8_n_4),
        .I3(m_axi_awlenq_reg_0_15_0_5_i_11_n_6),
        .I4(m_axi_awlenq_reg_0_15_0_5_i_12_n_0),
        .O(tlp_dstbt_len[6]));
  LUT2 #(
    .INIT(4'h9)) 
    m_axi_waddrlastq_reg_0_15_0_5_i_1
       (.I0(\axi4mm_axi_mm_master_wr/p_0_in1_in [1]),
        .I1(\axi4mm_axi_mm_master_wr/p_0_in1_in [0]),
        .O(DIA[1]));
  LUT1 #(
    .INIT(2'h1)) 
    m_axi_waddrlastq_reg_0_15_0_5_i_2
       (.I0(\axi4mm_axi_mm_master_wr/p_0_in1_in [0]),
        .O(DIA[0]));
  LUT3 #(
    .INIT(8'h01)) 
    m_axi_waddrlastq_reg_0_15_0_5_i_3
       (.I0(\axi4mm_axi_mm_master_wr/p_0_in1_in [2]),
        .I1(\axi4mm_axi_mm_master_wr/p_0_in1_in [0]),
        .I2(\axi4mm_axi_mm_master_wr/p_0_in1_in [1]),
        .O(DIB[1]));
  LUT3 #(
    .INIT(8'hA9)) 
    m_axi_waddrlastq_reg_0_15_0_5_i_4
       (.I0(\axi4mm_axi_mm_master_wr/p_0_in1_in [2]),
        .I1(\axi4mm_axi_mm_master_wr/p_0_in1_in [0]),
        .I2(\axi4mm_axi_mm_master_wr/p_0_in1_in [1]),
        .O(DIB[0]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 m_axi_waddrlastq_reg_0_15_0_5_i_5
       (.CI(1'b0),
        .CO({m_axi_waddrlastq_reg_0_15_0_5_i_5_n_0,m_axi_waddrlastq_reg_0_15_0_5_i_5_n_1,m_axi_waddrlastq_reg_0_15_0_5_i_5_n_2,m_axi_waddrlastq_reg_0_15_0_5_i_5_n_3}),
        .CYINIT(1'b0),
        .DI(Q[26:23]),
        .O(\axi4mm_axi_mm_master_wr/p_0_in1_in ),
        .S({m_axi_waddrlastq_reg_0_15_0_5_i_6_n_0,m_axi_waddrlastq_reg_0_15_0_5_i_7_n_0,m_axi_waddrlastq_reg_0_15_0_5_i_8_n_0,m_axi_waddrlastq_reg_0_15_0_5_i_9_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    m_axi_waddrlastq_reg_0_15_0_5_i_6
       (.I0(Q[26]),
        .I1(Q[8]),
        .O(m_axi_waddrlastq_reg_0_15_0_5_i_6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    m_axi_waddrlastq_reg_0_15_0_5_i_7
       (.I0(Q[25]),
        .I1(Q[7]),
        .O(m_axi_waddrlastq_reg_0_15_0_5_i_7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    m_axi_waddrlastq_reg_0_15_0_5_i_8
       (.I0(Q[24]),
        .I1(Q[6]),
        .O(m_axi_waddrlastq_reg_0_15_0_5_i_8_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    m_axi_waddrlastq_reg_0_15_0_5_i_9
       (.I0(Q[23]),
        .I1(Q[5]),
        .O(m_axi_waddrlastq_reg_0_15_0_5_i_9_n_0));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOAsync" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOAsync__parameterized1
   (empty_ff_reg_0,
    almost_full_ff,
    \wb_req_pnd_vec_ff_reg[1] ,
    D,
    empty_ff_reg_1,
    \wb_req_pnd_vec_ff_reg[1]_0 ,
    wbrq_gnt,
    wb_win_vld,
    \Head_reg[32]_0 ,
    user_clk,
    O52,
    \WrPtr_reg[0]_0 ,
    \WrPtr_reg[0]_1 ,
    \WrPtr_reg[0]_2 ,
    Q,
    wcp_rid_ff_0,
    wcp_vld_ff,
    \c2h_xdma_wbrq_req[0][dat] ,
    \h2c_xdma_wbrq_req[0][dat] ,
    wb_dat_fl,
    wb_info_fl,
    c2h_xdma_wbrq_vld,
    \WrPtr_reg[0]_3 ,
    h2c_xdma_wbrq_vld,
    arbhist_ff,
    \Head_reg[31]_0 );
  output empty_ff_reg_0;
  output almost_full_ff;
  output \wb_req_pnd_vec_ff_reg[1] ;
  output [0:0]D;
  output [0:0]empty_ff_reg_1;
  output [0:0]\wb_req_pnd_vec_ff_reg[1]_0 ;
  output [0:0]wbrq_gnt;
  output wb_win_vld;
  output [26:0]\Head_reg[32]_0 ;
  input user_clk;
  input O52;
  input \WrPtr_reg[0]_0 ;
  input [0:0]\WrPtr_reg[0]_1 ;
  input [0:0]\WrPtr_reg[0]_2 ;
  input [1:0]Q;
  input wcp_rid_ff_0;
  input wcp_vld_ff;
  input [24:0]\c2h_xdma_wbrq_req[0][dat] ;
  input [24:0]\h2c_xdma_wbrq_req[0][dat] ;
  input wb_dat_fl;
  input wb_info_fl;
  input c2h_xdma_wbrq_vld;
  input \WrPtr_reg[0]_3 ;
  input h2c_xdma_wbrq_vld;
  input [0:0]arbhist_ff;
  input [0:0]\Head_reg[31]_0 ;

  wire [0:0]D;
  wire [2:0]FifoCntrRd;
  wire \FifoCntrRd[0]_i_1__10_n_0 ;
  wire \FifoCntrRd[1]_i_1__10_n_0 ;
  wire \FifoCntrRd[2]_i_1__8_n_0 ;
  wire \FifoCntrRd[2]_i_2__5_n_0 ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__13_n_0 ;
  wire \FifoCntrWr[1]_i_1__12_n_0 ;
  wire \FifoCntrWr[2]_i_1__12_n_0 ;
  wire [32:0]Head0;
  wire \Head[32]_i_1__3_n_0 ;
  wire \Head[32]_i_3_n_0 ;
  wire [0:0]\Head_reg[31]_0 ;
  wire [26:0]\Head_reg[32]_0 ;
  wire MemArray_reg_0_3_0_5_i_1__2_n_0;
  wire O52;
  wire [1:0]Q;
  wire [1:0]RdPtr;
  wire \RdPtr[0]_i_1_n_0 ;
  wire \RdPtr[0]_i_2_n_0 ;
  wire \RdPtr[1]_i_1_n_0 ;
  wire \RdPtr[1]_i_2__6_n_0 ;
  wire [1:0]WrPtr;
  wire \WrPtr[0]_i_1_n_0 ;
  wire \WrPtr[1]_i_1_n_0 ;
  wire \WrPtr_reg[0]_0 ;
  wire [0:0]\WrPtr_reg[0]_1 ;
  wire [0:0]\WrPtr_reg[0]_2 ;
  wire \WrPtr_reg[0]_3 ;
  wire almost_full_ff;
  wire almost_full_ff_i_1__4_n_0;
  wire [0:0]arbhist_ff;
  wire [24:0]\c2h_xdma_wbrq_req[0][dat] ;
  wire c2h_xdma_wbrq_vld;
  wire empty_ff_i_1__16_n_0;
  wire empty_ff_i_2__7_n_0;
  wire empty_ff_reg_0;
  wire [0:0]empty_ff_reg_1;
  wire [24:0]\h2c_xdma_wbrq_req[0][dat] ;
  wire h2c_xdma_wbrq_vld;
  wire [32:0]p_0_in1_in;
  wire [31:0]payloadmuxed;
  wire user_clk;
  wire wb_dat_fl;
  wire wb_info_fl;
  wire \wb_req_pnd_vec_ff_reg[1] ;
  wire [0:0]\wb_req_pnd_vec_ff_reg[1]_0 ;
  wire wb_win_vld;
  wire [0:0]wbrq_gnt;
  wire wcp_rid_ff_0;
  wire wcp_vld_ff;
  wire [1:0]NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:1]NLW_MemArray_reg_0_3_30_32_DOB_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_30_32_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_30_32_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED;

  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__10 
       (.I0(FifoCntrRd[0]),
        .O(\FifoCntrRd[0]_i_1__10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1337" *) 
  LUT4 #(
    .INIT(16'h956A)) 
    \FifoCntrRd[1]_i_1__10 
       (.I0(FifoCntrRd[0]),
        .I1(\wb_req_pnd_vec_ff_reg[1] ),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(FifoCntrRd[1]),
        .O(\FifoCntrRd[1]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'h77777778)) 
    \FifoCntrRd[2]_i_1__8 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(\wb_req_pnd_vec_ff_reg[1] ),
        .I2(wb_dat_fl),
        .I3(wb_info_fl),
        .I4(empty_ff_reg_0),
        .O(\FifoCntrRd[2]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1337" *) 
  LUT5 #(
    .INIT(32'h95AAAA6A)) 
    \FifoCntrRd[2]_i_2__5 
       (.I0(FifoCntrRd[2]),
        .I1(\wb_req_pnd_vec_ff_reg[1] ),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(FifoCntrRd[1]),
        .I4(FifoCntrRd[0]),
        .O(\FifoCntrRd[2]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'hFBFBFFFBFBFBFBFB)) 
    \FifoCntrRd[2]_i_4 
       (.I0(Q[1]),
        .I1(c2h_xdma_wbrq_vld),
        .I2(almost_full_ff),
        .I3(\WrPtr_reg[0]_3 ),
        .I4(Q[0]),
        .I5(h2c_xdma_wbrq_vld),
        .O(\wb_req_pnd_vec_ff_reg[1] ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__8_n_0 ),
        .D(\FifoCntrRd[0]_i_1__10_n_0 ),
        .Q(FifoCntrRd[0]),
        .R(O52));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__8_n_0 ),
        .D(\FifoCntrRd[1]_i_1__10_n_0 ),
        .Q(FifoCntrRd[1]),
        .R(O52));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__8_n_0 ),
        .D(\FifoCntrRd[2]_i_2__5_n_0 ),
        .Q(FifoCntrRd[2]),
        .R(O52));
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__13 
       (.I0(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1336" *) 
  LUT4 #(
    .INIT(16'h8778)) 
    \FifoCntrWr[1]_i_1__12 
       (.I0(\WrPtr_reg[0]_0 ),
        .I1(\wb_req_pnd_vec_ff_reg[1] ),
        .I2(FifoCntrWr[1]),
        .I3(FifoCntrWr[0]),
        .O(\FifoCntrWr[1]_i_1__12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1336" *) 
  LUT5 #(
    .INIT(32'hA96A6A6A)) 
    \FifoCntrWr[2]_i_1__12 
       (.I0(FifoCntrWr[2]),
        .I1(FifoCntrWr[1]),
        .I2(FifoCntrWr[0]),
        .I3(\WrPtr_reg[0]_0 ),
        .I4(\wb_req_pnd_vec_ff_reg[1] ),
        .O(\FifoCntrWr[2]_i_1__12_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__8_n_0 ),
        .D(\FifoCntrWr[0]_i_1__13_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(O52));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__8_n_0 ),
        .D(\FifoCntrWr[1]_i_1__12_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(O52));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__8_n_0 ),
        .D(\FifoCntrWr[2]_i_1__12_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(O52));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[0]_i_1__4 
       (.I0(Head0[0]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [0]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [0]),
        .O(p_0_in1_in[0]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[10]_i_1__7 
       (.I0(Head0[10]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [10]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [10]),
        .O(p_0_in1_in[10]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[11]_i_1__7 
       (.I0(Head0[11]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [11]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [11]),
        .O(p_0_in1_in[11]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[12]_i_1__7 
       (.I0(Head0[12]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [12]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [12]),
        .O(p_0_in1_in[12]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[13]_i_1__7 
       (.I0(Head0[13]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [13]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [13]),
        .O(p_0_in1_in[13]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[14]_i_1__7 
       (.I0(Head0[14]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [14]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [14]),
        .O(p_0_in1_in[14]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[15]_i_1__7 
       (.I0(Head0[15]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [15]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [15]),
        .O(p_0_in1_in[15]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[16]_i_1__6 
       (.I0(Head0[16]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [16]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [16]),
        .O(p_0_in1_in[16]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[17]_i_1__5 
       (.I0(Head0[17]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [17]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [17]),
        .O(p_0_in1_in[17]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[18]_i_1__7 
       (.I0(Head0[18]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [18]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [18]),
        .O(p_0_in1_in[18]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[19]_i_1__7 
       (.I0(Head0[19]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [19]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [19]),
        .O(p_0_in1_in[19]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[1]_i_1__4 
       (.I0(Head0[1]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [1]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [1]),
        .O(p_0_in1_in[1]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[20]_i_1__8 
       (.I0(Head0[20]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [20]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [20]),
        .O(p_0_in1_in[20]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[21]_i_1__8 
       (.I0(Head0[21]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [21]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [21]),
        .O(p_0_in1_in[21]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[22]_i_1__6 
       (.I0(Head0[22]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [22]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [22]),
        .O(p_0_in1_in[22]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[23]_i_1__6 
       (.I0(Head0[23]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [23]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [23]),
        .O(p_0_in1_in[23]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[2]_i_1__2 
       (.I0(Head0[2]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [2]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [2]),
        .O(p_0_in1_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair1338" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \Head[30]_i_1__5 
       (.I0(\Head[32]_i_3_n_0 ),
        .I1(Head0[30]),
        .O(p_0_in1_in[30]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[31]_i_1__4 
       (.I0(Head0[31]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [24]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [24]),
        .O(p_0_in1_in[31]));
  LUT6 #(
    .INIT(64'h01010101010101FF)) 
    \Head[32]_i_1__3 
       (.I0(FifoCntrRd[0]),
        .I1(FifoCntrRd[1]),
        .I2(FifoCntrRd[2]),
        .I3(empty_ff_reg_0),
        .I4(wb_info_fl),
        .I5(wb_dat_fl),
        .O(\Head[32]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1338" *) 
  LUT3 #(
    .INIT(8'h8B)) 
    \Head[32]_i_2 
       (.I0(Head0[32]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .O(p_0_in1_in[32]));
  (* SOFT_HLUTNM = "soft_lutpair1335" *) 
  LUT5 #(
    .INIT(32'hFFFEFEFE)) 
    \Head[32]_i_3 
       (.I0(\RdPtr[0]_i_2_n_0 ),
        .I1(FifoCntrRd[2]),
        .I2(FifoCntrRd[1]),
        .I3(\WrPtr_reg[0]_0 ),
        .I4(\wb_req_pnd_vec_ff_reg[1] ),
        .O(\Head[32]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[3]_i_1__4 
       (.I0(Head0[3]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [3]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [3]),
        .O(p_0_in1_in[3]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[4]_i_1__4 
       (.I0(Head0[4]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [4]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [4]),
        .O(p_0_in1_in[4]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[5]_i_1__4 
       (.I0(Head0[5]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [5]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [5]),
        .O(p_0_in1_in[5]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[6]_i_1__2 
       (.I0(Head0[6]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [6]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [6]),
        .O(p_0_in1_in[6]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[7]_i_1__3 
       (.I0(Head0[7]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [7]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [7]),
        .O(p_0_in1_in[7]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[8]_i_1__7 
       (.I0(Head0[8]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [8]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [8]),
        .O(p_0_in1_in[8]));
  LUT6 #(
    .INIT(64'h8B88BBBB8B888B88)) 
    \Head[9]_i_1__7 
       (.I0(Head0[9]),
        .I1(\Head[32]_i_3_n_0 ),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\c2h_xdma_wbrq_req[0][dat] [9]),
        .I4(\WrPtr_reg[0]_0 ),
        .I5(\h2c_xdma_wbrq_req[0][dat] [9]),
        .O(p_0_in1_in[9]));
  FDRE \Head_reg[0] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[0]),
        .Q(\Head_reg[32]_0 [0]),
        .R(O52));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[10]),
        .Q(\Head_reg[32]_0 [10]),
        .R(O52));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[11]),
        .Q(\Head_reg[32]_0 [11]),
        .R(O52));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[12]),
        .Q(\Head_reg[32]_0 [12]),
        .R(O52));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[13]),
        .Q(\Head_reg[32]_0 [13]),
        .R(O52));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[14]),
        .Q(\Head_reg[32]_0 [14]),
        .R(O52));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[15]),
        .Q(\Head_reg[32]_0 [15]),
        .R(O52));
  FDRE \Head_reg[16] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[16]),
        .Q(\Head_reg[32]_0 [16]),
        .R(O52));
  FDRE \Head_reg[17] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[17]),
        .Q(\Head_reg[32]_0 [17]),
        .R(O52));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[18]),
        .Q(\Head_reg[32]_0 [18]),
        .R(O52));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[19]),
        .Q(\Head_reg[32]_0 [19]),
        .R(O52));
  FDRE \Head_reg[1] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[1]),
        .Q(\Head_reg[32]_0 [1]),
        .R(O52));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[20]),
        .Q(\Head_reg[32]_0 [20]),
        .R(O52));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[21]),
        .Q(\Head_reg[32]_0 [21]),
        .R(O52));
  FDRE \Head_reg[22] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[22]),
        .Q(\Head_reg[32]_0 [22]),
        .R(O52));
  FDRE \Head_reg[23] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[23]),
        .Q(\Head_reg[32]_0 [23]),
        .R(O52));
  FDRE \Head_reg[2] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[2]),
        .Q(\Head_reg[32]_0 [2]),
        .R(O52));
  FDRE \Head_reg[30] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[30]),
        .Q(\Head_reg[32]_0 [24]),
        .R(O52));
  FDRE \Head_reg[31] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[31]),
        .Q(\Head_reg[32]_0 [25]),
        .R(O52));
  FDRE \Head_reg[32] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[32]),
        .Q(\Head_reg[32]_0 [26]),
        .R(O52));
  FDRE \Head_reg[3] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[3]),
        .Q(\Head_reg[32]_0 [3]),
        .R(O52));
  FDRE \Head_reg[4] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[4]),
        .Q(\Head_reg[32]_0 [4]),
        .R(O52));
  FDRE \Head_reg[5] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[5]),
        .Q(\Head_reg[32]_0 [5]),
        .R(O52));
  FDRE \Head_reg[6] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[6]),
        .Q(\Head_reg[32]_0 [6]),
        .R(O52));
  FDRE \Head_reg[7] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[7]),
        .Q(\Head_reg[32]_0 [7]),
        .R(O52));
  FDRE \Head_reg[8] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[8]),
        .Q(\Head_reg[32]_0 [8]),
        .R(O52));
  FDRE \Head_reg[9] 
       (.C(user_clk),
        .CE(\Head[32]_i_1__3_n_0 ),
        .D(p_0_in1_in[9]),
        .Q(\Head_reg[32]_0 [9]),
        .R(O52));
  LUT1 #(
    .INIT(2'h1)) 
    MemArray_reg_0_3_0_0_i_1
       (.I0(empty_ff_reg_0),
        .O(wb_win_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "132" *) 
  (* RTL_RAM_NAME = "axidma_wb_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_3_0_5
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[1:0]),
        .DIB(payloadmuxed[3:2]),
        .DIC(payloadmuxed[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[1:0]),
        .DOB(Head0[3:2]),
        .DOC(Head0[5:4]),
        .DOD(NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(MemArray_reg_0_3_0_5_i_1__2_n_0));
  LUT2 #(
    .INIT(4'h7)) 
    MemArray_reg_0_3_0_5_i_1__2
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\WrPtr_reg[0]_0 ),
        .O(MemArray_reg_0_3_0_5_i_1__2_n_0));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_0_5_i_2__1
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [1]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [1]),
        .O(payloadmuxed[1]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_0_5_i_3__1
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [0]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [0]),
        .O(payloadmuxed[0]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_0_5_i_4__1
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [3]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [3]),
        .O(payloadmuxed[3]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_0_5_i_5__1
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [2]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [2]),
        .O(payloadmuxed[2]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_0_5_i_6__1
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [5]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [5]),
        .O(payloadmuxed[5]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_0_5_i_7__1
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [4]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [4]),
        .O(payloadmuxed[4]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "132" *) 
  (* RTL_RAM_NAME = "axidma_wb_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[13:12]),
        .DIB(payloadmuxed[15:14]),
        .DIC(payloadmuxed[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[13:12]),
        .DOB(Head0[15:14]),
        .DOC(Head0[17:16]),
        .DOD(NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(MemArray_reg_0_3_0_5_i_1__2_n_0));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_12_17_i_1__2
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [13]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [13]),
        .O(payloadmuxed[13]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_12_17_i_2__2
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [12]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [12]),
        .O(payloadmuxed[12]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_12_17_i_3__2
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [15]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [15]),
        .O(payloadmuxed[15]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_12_17_i_4__2
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [14]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [14]),
        .O(payloadmuxed[14]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_12_17_i_5__1
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [17]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [17]),
        .O(payloadmuxed[17]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_12_17_i_6__1
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [16]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [16]),
        .O(payloadmuxed[16]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "132" *) 
  (* RTL_RAM_NAME = "axidma_wb_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[19:18]),
        .DIB(payloadmuxed[21:20]),
        .DIC(payloadmuxed[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[19:18]),
        .DOB(Head0[21:20]),
        .DOC(Head0[23:22]),
        .DOD(NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(MemArray_reg_0_3_0_5_i_1__2_n_0));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_18_23_i_1
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [19]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [19]),
        .O(payloadmuxed[19]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_18_23_i_2
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [18]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [18]),
        .O(payloadmuxed[18]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_18_23_i_3__0
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [21]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [21]),
        .O(payloadmuxed[21]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_18_23_i_4__0
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [20]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [20]),
        .O(payloadmuxed[20]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_18_23_i_5__0
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [23]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [23]),
        .O(payloadmuxed[23]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_18_23_i_6__0
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [22]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [22]),
        .O(payloadmuxed[22]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "132" *) 
  (* RTL_RAM_NAME = "axidma_wb_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_32" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "32" *) 
  RAM32M MemArray_reg_0_3_30_32
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({payloadmuxed[31],1'b0}),
        .DIB({1'b0,\Head_reg[31]_0 }),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[31:30]),
        .DOB({NLW_MemArray_reg_0_3_30_32_DOB_UNCONNECTED[1],Head0[32]}),
        .DOC(NLW_MemArray_reg_0_3_30_32_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_30_32_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(MemArray_reg_0_3_0_5_i_1__2_n_0));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_30_32_i_1
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [24]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [24]),
        .O(payloadmuxed[31]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "132" *) 
  (* RTL_RAM_NAME = "axidma_wb_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(payloadmuxed[7:6]),
        .DIB(payloadmuxed[9:8]),
        .DIC(payloadmuxed[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[7:6]),
        .DOB(Head0[9:8]),
        .DOC(Head0[11:10]),
        .DOD(NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(MemArray_reg_0_3_0_5_i_1__2_n_0));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_6_11_i_1__2
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [7]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [7]),
        .O(payloadmuxed[7]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_6_11_i_2__2
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [6]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [6]),
        .O(payloadmuxed[6]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_6_11_i_3__2
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [9]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [9]),
        .O(payloadmuxed[9]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_6_11_i_4__2
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [8]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [8]),
        .O(payloadmuxed[8]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_6_11_i_5__2
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [11]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [11]),
        .O(payloadmuxed[11]));
  LUT4 #(
    .INIT(16'h4F44)) 
    MemArray_reg_0_3_6_11_i_6__1
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(\c2h_xdma_wbrq_req[0][dat] [10]),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(\h2c_xdma_wbrq_req[0][dat] [10]),
        .O(payloadmuxed[10]));
  LUT6 #(
    .INIT(64'hDDDDDDDF11111110)) 
    \RdPtr[0]_i_1 
       (.I0(RdPtr[0]),
        .I1(\RdPtr[0]_i_2_n_0 ),
        .I2(FifoCntrRd[2]),
        .I3(FifoCntrRd[1]),
        .I4(MemArray_reg_0_3_0_5_i_1__2_n_0),
        .I5(RdPtr[0]),
        .O(\RdPtr[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFEFEFEFEFEFEFE00)) 
    \RdPtr[0]_i_2 
       (.I0(wb_dat_fl),
        .I1(wb_info_fl),
        .I2(empty_ff_reg_0),
        .I3(FifoCntrRd[2]),
        .I4(FifoCntrRd[1]),
        .I5(FifoCntrRd[0]),
        .O(\RdPtr[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h6F60)) 
    \RdPtr[1]_i_1 
       (.I0(RdPtr[0]),
        .I1(RdPtr[1]),
        .I2(\RdPtr[1]_i_2__6_n_0 ),
        .I3(RdPtr[1]),
        .O(\RdPtr[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1335" *) 
  LUT5 #(
    .INIT(32'h54555555)) 
    \RdPtr[1]_i_2__6 
       (.I0(\RdPtr[0]_i_2_n_0 ),
        .I1(FifoCntrRd[2]),
        .I2(FifoCntrRd[1]),
        .I3(\wb_req_pnd_vec_ff_reg[1] ),
        .I4(\WrPtr_reg[0]_0 ),
        .O(\RdPtr[1]_i_2__6_n_0 ));
  (* MAX_FANOUT = "128" *) 
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1_n_0 ),
        .Q(RdPtr[0]),
        .R(O52));
  (* MAX_FANOUT = "128" *) 
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[1]_i_1_n_0 ),
        .Q(RdPtr[1]),
        .R(O52));
  LUT4 #(
    .INIT(16'hD515)) 
    \WrPtr[0]_i_1 
       (.I0(WrPtr[0]),
        .I1(\wb_req_pnd_vec_ff_reg[1] ),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(WrPtr[0]),
        .O(\WrPtr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1339" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \WrPtr[0]_i_1__13 
       (.I0(empty_ff_reg_0),
        .I1(\WrPtr_reg[0]_1 ),
        .O(D));
  (* SOFT_HLUTNM = "soft_lutpair1339" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \WrPtr[0]_i_1__14 
       (.I0(empty_ff_reg_0),
        .I1(\WrPtr_reg[0]_2 ),
        .O(empty_ff_reg_1));
  LUT5 #(
    .INIT(32'hF6660666)) 
    \WrPtr[1]_i_1 
       (.I0(WrPtr[0]),
        .I1(WrPtr[1]),
        .I2(\wb_req_pnd_vec_ff_reg[1] ),
        .I3(\WrPtr_reg[0]_0 ),
        .I4(WrPtr[1]),
        .O(\WrPtr[1]_i_1_n_0 ));
  (* MAX_FANOUT = "128" *) 
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[0]_i_1_n_0 ),
        .Q(WrPtr[0]),
        .R(O52));
  (* MAX_FANOUT = "128" *) 
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[1]_i_1_n_0 ),
        .Q(WrPtr[1]),
        .R(O52));
  LUT3 #(
    .INIT(8'hEA)) 
    almost_full_ff_i_1__4
       (.I0(FifoCntrWr[2]),
        .I1(FifoCntrWr[1]),
        .I2(FifoCntrWr[0]),
        .O(almost_full_ff_i_1__4_n_0));
  FDRE almost_full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(almost_full_ff_i_1__4_n_0),
        .Q(almost_full_ff),
        .R(O52));
  LUT6 #(
    .INIT(64'hFFFFFFFF000F010F)) 
    empty_ff_i_1__16
       (.I0(wb_dat_fl),
        .I1(wb_info_fl),
        .I2(empty_ff_i_2__7_n_0),
        .I3(FifoCntrRd[0]),
        .I4(empty_ff_reg_0),
        .I5(O52),
        .O(empty_ff_i_1__16_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    empty_ff_i_2__7
       (.I0(FifoCntrRd[2]),
        .I1(FifoCntrRd[1]),
        .O(empty_ff_i_2__7_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__16_n_0),
        .Q(empty_ff_reg_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h5DDD)) 
    \wb_req_pnd_vec_ff[1]_i_1 
       (.I0(\wb_req_pnd_vec_ff_reg[1] ),
        .I1(Q[1]),
        .I2(wcp_rid_ff_0),
        .I3(wcp_vld_ff),
        .O(\wb_req_pnd_vec_ff_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h0404040400040404)) 
    wbrq_vld_nn1_i_2
       (.I0(almost_full_ff),
        .I1(h2c_xdma_wbrq_vld),
        .I2(Q[0]),
        .I3(arbhist_ff),
        .I4(c2h_xdma_wbrq_vld),
        .I5(Q[1]),
        .O(wbrq_gnt));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOHead" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOHead
   (wpl_ld,
    \wrreq_cnt_ff_reg[4] ,
    SR,
    \FifoCntrRd_reg[0]_0 ,
    Q,
    \WrPtr_reg[3]_0 ,
    wpl_vld_nxt,
    wtlp_srcbt_noinc,
    D,
    \Head_reg[21]_0 ,
    \Head_reg[34]_0 ,
    user_clk,
    user_rst_n_3ff_reg,
    Head0,
    \awstrptr_ff_reg[0] ,
    \awstrptr_ff_reg[0]_0 ,
    wpl_vld_ff,
    wtlp_sm_500,
    wtlp_dat_fifo_af_nn1,
    \Head_reg[34]_1 );
  output wpl_ld;
  output \wrreq_cnt_ff_reg[4] ;
  output [0:0]SR;
  output \FifoCntrRd_reg[0]_0 ;
  output [3:0]Q;
  output [3:0]\WrPtr_reg[3]_0 ;
  output wpl_vld_nxt;
  output wtlp_srcbt_noinc;
  output [8:0]D;
  output [8:0]\Head_reg[21]_0 ;
  output [11:0]\Head_reg[34]_0 ;
  input user_clk;
  input [0:0]user_rst_n_3ff_reg;
  input [0:0]Head0;
  input [4:0]\awstrptr_ff_reg[0] ;
  input \awstrptr_ff_reg[0]_0 ;
  input wpl_vld_ff;
  input [2:0]wtlp_sm_500;
  input wtlp_dat_fifo_af_nn1;
  input [22:0]\Head_reg[34]_1 ;

  wire [8:0]D;
  wire \FifoCntrRd[0]_i_1__12_n_0 ;
  wire \FifoCntrRd[1]_i_1__11_n_0 ;
  wire \FifoCntrRd[2]_i_1__10_n_0 ;
  wire \FifoCntrRd[3]_i_1__1_n_0 ;
  wire \FifoCntrRd[4]_i_1_n_0 ;
  wire \FifoCntrRd[4]_i_2_n_0 ;
  wire [4:0]FifoCntrRd_reg;
  wire \FifoCntrRd_reg[0]_0 ;
  wire [0:0]Head0;
  wire \Head[34]_i_1__2_n_0 ;
  wire [8:0]\Head_reg[21]_0 ;
  wire [11:0]\Head_reg[34]_0 ;
  wire [22:0]\Head_reg[34]_1 ;
  wire \Head_reg_n_0_[1] ;
  wire [3:0]Q;
  wire RdPtr1__1;
  wire \RdPtr[0]_i_1__15_n_0 ;
  wire \RdPtr[1]_i_1__15_n_0 ;
  wire \RdPtr[2]_i_1__4_n_0 ;
  wire \RdPtr[2]_i_3__1_n_0 ;
  wire \RdPtr[2]_i_4__1_n_0 ;
  wire \RdPtr[3]_i_1__1_n_0 ;
  wire [0:0]SR;
  wire [3:0]WrPtr__0;
  wire [3:0]\WrPtr_reg[3]_0 ;
  wire [4:0]\awstrptr_ff_reg[0] ;
  wire \awstrptr_ff_reg[0]_0 ;
  wire empty_ff_i_1__18_n_0;
  wire empty_ff_reg_n_0;
  wire [33:0]p_0_in1_in__0;
  wire user_clk;
  wire [0:0]user_rst_n_3ff_reg;
  wire [11:0]wpl_bytelen;
  wire wpl_ld;
  wire wpl_vld_ff;
  wire wpl_vld_nxt;
  wire \wrreq_cnt_ff_reg[4] ;
  wire wtlp_dat_fifo_af_nn1;
  wire \wtlp_dstbt_len_ff[2]_i_3_n_0 ;
  wire \wtlp_dstbt_len_ff[2]_i_4_n_0 ;
  wire \wtlp_dstbt_len_ff[2]_i_5_n_0 ;
  wire \wtlp_dstbt_len_ff[7]_i_3_n_0 ;
  wire \wtlp_dstbt_len_ff[8]_i_4_n_0 ;
  wire \wtlp_dstbt_len_ff_reg[2]_i_2_n_0 ;
  wire \wtlp_dstbt_len_ff_reg[2]_i_2_n_1 ;
  wire \wtlp_dstbt_len_ff_reg[2]_i_2_n_2 ;
  wire \wtlp_dstbt_len_ff_reg[2]_i_2_n_3 ;
  wire \wtlp_dstbt_len_ff_reg[7]_i_2_n_0 ;
  wire \wtlp_dstbt_len_ff_reg[7]_i_2_n_1 ;
  wire \wtlp_dstbt_len_ff_reg[7]_i_2_n_2 ;
  wire \wtlp_dstbt_len_ff_reg[7]_i_2_n_3 ;
  wire \wtlp_dstbt_len_ff_reg[8]_i_3_n_0 ;
  wire \wtlp_dstbt_len_ff_reg[8]_i_3_n_1 ;
  wire \wtlp_dstbt_len_ff_reg[8]_i_3_n_2 ;
  wire \wtlp_dstbt_len_ff_reg[8]_i_3_n_3 ;
  wire [11:0]wtlp_dstbt_whole_len1;
  wire [2:0]wtlp_sm_500;
  wire \wtlp_srcbt_len_ff[2]_i_3_n_0 ;
  wire \wtlp_srcbt_len_ff[2]_i_4_n_0 ;
  wire \wtlp_srcbt_len_ff[2]_i_5_n_0 ;
  wire \wtlp_srcbt_len_ff[7]_i_3_n_0 ;
  wire \wtlp_srcbt_len_ff[8]_i_3_n_0 ;
  wire \wtlp_srcbt_len_ff_reg[2]_i_2_n_0 ;
  wire \wtlp_srcbt_len_ff_reg[2]_i_2_n_1 ;
  wire \wtlp_srcbt_len_ff_reg[2]_i_2_n_2 ;
  wire \wtlp_srcbt_len_ff_reg[2]_i_2_n_3 ;
  wire \wtlp_srcbt_len_ff_reg[7]_i_2_n_0 ;
  wire \wtlp_srcbt_len_ff_reg[7]_i_2_n_1 ;
  wire \wtlp_srcbt_len_ff_reg[7]_i_2_n_2 ;
  wire \wtlp_srcbt_len_ff_reg[7]_i_2_n_3 ;
  wire \wtlp_srcbt_len_ff_reg[8]_i_2_n_0 ;
  wire \wtlp_srcbt_len_ff_reg[8]_i_2_n_1 ;
  wire \wtlp_srcbt_len_ff_reg[8]_i_2_n_2 ;
  wire \wtlp_srcbt_len_ff_reg[8]_i_2_n_3 ;
  wire wtlp_srcbt_noinc;
  wire wtlp_srcbt_noinc_ff_i_3_n_0;
  wire wtlp_srcbt_noinc_ff_i_4_n_0;
  wire wtlp_srcbt_noinc_ff_i_5_n_0;
  wire wtlp_srcbt_noinc_ff_reg_i_2_n_0;
  wire wtlp_srcbt_noinc_ff_reg_i_2_n_1;
  wire wtlp_srcbt_noinc_ff_reg_i_2_n_2;
  wire wtlp_srcbt_noinc_ff_reg_i_2_n_3;
  wire wtlp_srcbt_noinc_ff_reg_i_2_n_4;
  wire wtlp_srcbt_noinc_ff_reg_i_2_n_5;
  wire wtlp_srcbt_noinc_ff_reg_i_2_n_6;
  wire wtlp_srcbt_noinc_ff_reg_i_2_n_7;
  wire [11:0]wtlp_srcbt_whole_len1;

  (* SOFT_HLUTNM = "soft_lutpair382" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__12 
       (.I0(FifoCntrRd_reg[0]),
        .O(\FifoCntrRd[0]_i_1__12_n_0 ));
  LUT3 #(
    .INIT(8'h69)) 
    \FifoCntrRd[1]_i_1__11 
       (.I0(\wrreq_cnt_ff_reg[4] ),
        .I1(FifoCntrRd_reg[1]),
        .I2(FifoCntrRd_reg[0]),
        .O(\FifoCntrRd[1]_i_1__11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair385" *) 
  LUT4 #(
    .INIT(16'h78E1)) 
    \FifoCntrRd[2]_i_1__10 
       (.I0(\wrreq_cnt_ff_reg[4] ),
        .I1(FifoCntrRd_reg[1]),
        .I2(FifoCntrRd_reg[2]),
        .I3(FifoCntrRd_reg[0]),
        .O(\FifoCntrRd[2]_i_1__10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair385" *) 
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \FifoCntrRd[3]_i_1__1 
       (.I0(FifoCntrRd_reg[3]),
        .I1(FifoCntrRd_reg[0]),
        .I2(FifoCntrRd_reg[1]),
        .I3(\wrreq_cnt_ff_reg[4] ),
        .I4(FifoCntrRd_reg[2]),
        .O(\FifoCntrRd[3]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \FifoCntrRd[4]_i_1 
       (.I0(empty_ff_reg_n_0),
        .I1(wpl_ld),
        .I2(\wrreq_cnt_ff_reg[4] ),
        .O(\FifoCntrRd[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h78F0F0F0F0F0F0E1)) 
    \FifoCntrRd[4]_i_2 
       (.I0(FifoCntrRd_reg[2]),
        .I1(FifoCntrRd_reg[3]),
        .I2(FifoCntrRd_reg[4]),
        .I3(FifoCntrRd_reg[0]),
        .I4(FifoCntrRd_reg[1]),
        .I5(\wrreq_cnt_ff_reg[4] ),
        .O(\FifoCntrRd[4]_i_2_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[4]_i_1_n_0 ),
        .D(\FifoCntrRd[0]_i_1__12_n_0 ),
        .Q(FifoCntrRd_reg[0]),
        .R(SR));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[4]_i_1_n_0 ),
        .D(\FifoCntrRd[1]_i_1__11_n_0 ),
        .Q(FifoCntrRd_reg[1]),
        .R(SR));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[4]_i_1_n_0 ),
        .D(\FifoCntrRd[2]_i_1__10_n_0 ),
        .Q(FifoCntrRd_reg[2]),
        .R(SR));
  FDRE \FifoCntrRd_reg[3] 
       (.C(user_clk),
        .CE(\FifoCntrRd[4]_i_1_n_0 ),
        .D(\FifoCntrRd[3]_i_1__1_n_0 ),
        .Q(FifoCntrRd_reg[3]),
        .R(SR));
  FDRE \FifoCntrRd_reg[4] 
       (.C(user_clk),
        .CE(\FifoCntrRd[4]_i_1_n_0 ),
        .D(\FifoCntrRd[4]_i_2_n_0 ),
        .Q(FifoCntrRd_reg[4]),
        .R(SR));
  LUT2 #(
    .INIT(4'h2)) 
    \Head[0]_i_1__6 
       (.I0(Head0),
        .I1(\FifoCntrRd_reg[0]_0 ),
        .O(p_0_in1_in__0[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[33]_i_1__3 
       (.I0(1'b0),
        .I1(\FifoCntrRd_reg[0]_0 ),
        .I2(1'b0),
        .O(p_0_in1_in__0[33]));
  LUT4 #(
    .INIT(16'h222F)) 
    \Head[34]_i_1__2 
       (.I0(wpl_ld),
        .I1(empty_ff_reg_n_0),
        .I2(FifoCntrRd_reg[0]),
        .I3(\RdPtr[2]_i_4__1_n_0 ),
        .O(\Head[34]_i_1__2_n_0 ));
  FDRE \Head_reg[0] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(p_0_in1_in__0[0]),
        .Q(\Head_reg[34]_0 [0]),
        .R(SR));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [1]),
        .Q(wpl_bytelen[0]),
        .R(SR));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [2]),
        .Q(wpl_bytelen[1]),
        .R(SR));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [3]),
        .Q(wpl_bytelen[2]),
        .R(SR));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [4]),
        .Q(wpl_bytelen[3]),
        .R(SR));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [5]),
        .Q(wpl_bytelen[4]),
        .R(SR));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [6]),
        .Q(wpl_bytelen[5]),
        .R(SR));
  FDRE \Head_reg[16] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [7]),
        .Q(wpl_bytelen[6]),
        .R(SR));
  FDRE \Head_reg[17] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [8]),
        .Q(wpl_bytelen[7]),
        .R(SR));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [9]),
        .Q(wpl_bytelen[8]),
        .R(SR));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [10]),
        .Q(wpl_bytelen[9]),
        .R(SR));
  FDRE \Head_reg[1] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [0]),
        .Q(\Head_reg_n_0_[1] ),
        .R(SR));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [11]),
        .Q(wpl_bytelen[10]),
        .R(SR));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [12]),
        .Q(wpl_bytelen[11]),
        .R(SR));
  FDRE \Head_reg[23] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [13]),
        .Q(\Head_reg[34]_0 [1]),
        .R(SR));
  FDRE \Head_reg[24] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [14]),
        .Q(\Head_reg[34]_0 [2]),
        .R(SR));
  FDRE \Head_reg[25] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [15]),
        .Q(\Head_reg[34]_0 [3]),
        .R(SR));
  FDRE \Head_reg[26] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [16]),
        .Q(\Head_reg[34]_0 [4]),
        .R(SR));
  FDRE \Head_reg[27] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [17]),
        .Q(\Head_reg[34]_0 [5]),
        .R(SR));
  FDRE \Head_reg[28] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [18]),
        .Q(\Head_reg[34]_0 [6]),
        .R(SR));
  FDRE \Head_reg[29] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [19]),
        .Q(\Head_reg[34]_0 [7]),
        .R(SR));
  FDRE \Head_reg[30] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [20]),
        .Q(\Head_reg[34]_0 [8]),
        .R(SR));
  FDRE \Head_reg[31] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [21]),
        .Q(\Head_reg[34]_0 [9]),
        .R(SR));
  FDRE \Head_reg[33] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(p_0_in1_in__0[33]),
        .Q(\Head_reg[34]_0 [10]),
        .R(SR));
  FDRE \Head_reg[34] 
       (.C(user_clk),
        .CE(\Head[34]_i_1__2_n_0 ),
        .D(\Head_reg[34]_1 [22]),
        .Q(\Head_reg[34]_0 [11]),
        .R(SR));
  LUT6 #(
    .INIT(64'h0001010101010101)) 
    MemArray_reg_0_15_0_5_i_1
       (.I0(\awstrptr_ff_reg[0] [3]),
        .I1(\awstrptr_ff_reg[0] [4]),
        .I2(\awstrptr_ff_reg[0]_0 ),
        .I3(\awstrptr_ff_reg[0] [2]),
        .I4(\awstrptr_ff_reg[0] [0]),
        .I5(\awstrptr_ff_reg[0] [1]),
        .O(\wrreq_cnt_ff_reg[4] ));
  LUT6 #(
    .INIT(64'hFBFB11FB0404EE04)) 
    \RdPtr[0]_i_1__15 
       (.I0(\RdPtr[2]_i_4__1_n_0 ),
        .I1(\wrreq_cnt_ff_reg[4] ),
        .I2(FifoCntrRd_reg[0]),
        .I3(wpl_ld),
        .I4(empty_ff_reg_n_0),
        .I5(Q[0]),
        .O(\RdPtr[0]_i_1__15_n_0 ));
  LUT6 #(
    .INIT(64'h5555FF7FAAAA0080)) 
    \RdPtr[1]_i_1__15 
       (.I0(Q[0]),
        .I1(\RdPtr[2]_i_4__1_n_0 ),
        .I2(wpl_ld),
        .I3(empty_ff_reg_n_0),
        .I4(\FifoCntrRd_reg[0]_0 ),
        .I5(Q[1]),
        .O(\RdPtr[1]_i_1__15_n_0 ));
  LUT6 #(
    .INIT(64'h5777FFFFA8880000)) 
    \RdPtr[2]_i_1__4 
       (.I0(Q[1]),
        .I1(\FifoCntrRd_reg[0]_0 ),
        .I2(\RdPtr[2]_i_3__1_n_0 ),
        .I3(\RdPtr[2]_i_4__1_n_0 ),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(\RdPtr[2]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair382" *) 
  LUT5 #(
    .INIT(32'h04044404)) 
    \RdPtr[2]_i_2__2 
       (.I0(\RdPtr[2]_i_4__1_n_0 ),
        .I1(\wrreq_cnt_ff_reg[4] ),
        .I2(FifoCntrRd_reg[0]),
        .I3(wpl_ld),
        .I4(empty_ff_reg_n_0),
        .O(\FifoCntrRd_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h000000005555555D)) 
    \RdPtr[2]_i_3__1 
       (.I0(wpl_vld_ff),
        .I1(wtlp_sm_500[0]),
        .I2(wtlp_dat_fifo_af_nn1),
        .I3(wtlp_sm_500[2]),
        .I4(wtlp_sm_500[1]),
        .I5(empty_ff_reg_n_0),
        .O(\RdPtr[2]_i_3__1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \RdPtr[2]_i_4__1 
       (.I0(FifoCntrRd_reg[4]),
        .I1(FifoCntrRd_reg[3]),
        .I2(FifoCntrRd_reg[2]),
        .I3(FifoCntrRd_reg[1]),
        .O(\RdPtr[2]_i_4__1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \RdPtr[3]_i_1__1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(RdPtr1__1),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(\RdPtr[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFE0000)) 
    \RdPtr[3]_i_2__0 
       (.I0(FifoCntrRd_reg[4]),
        .I1(FifoCntrRd_reg[3]),
        .I2(FifoCntrRd_reg[2]),
        .I3(FifoCntrRd_reg[1]),
        .I4(\RdPtr[2]_i_3__1_n_0 ),
        .I5(\FifoCntrRd_reg[0]_0 ),
        .O(RdPtr1__1));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1__15_n_0 ),
        .Q(Q[0]),
        .R(SR));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[1]_i_1__15_n_0 ),
        .Q(Q[1]),
        .R(SR));
  FDRE \RdPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[2]_i_1__4_n_0 ),
        .Q(Q[2]),
        .R(SR));
  FDRE \RdPtr_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[3]_i_1__1_n_0 ),
        .Q(Q[3]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair389" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \WrPtr[0]_i_1__15 
       (.I0(\WrPtr_reg[3]_0 [0]),
        .I1(\wrreq_cnt_ff_reg[4] ),
        .O(WrPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair389" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \WrPtr[1]_i_1__15 
       (.I0(\wrreq_cnt_ff_reg[4] ),
        .I1(\WrPtr_reg[3]_0 [0]),
        .I2(\WrPtr_reg[3]_0 [1]),
        .O(WrPtr__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair386" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \WrPtr[2]_i_1__4 
       (.I0(\WrPtr_reg[3]_0 [1]),
        .I1(\WrPtr_reg[3]_0 [0]),
        .I2(\wrreq_cnt_ff_reg[4] ),
        .I3(\WrPtr_reg[3]_0 [2]),
        .O(WrPtr__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair386" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \WrPtr[3]_i_1__1 
       (.I0(\WrPtr_reg[3]_0 [2]),
        .I1(\wrreq_cnt_ff_reg[4] ),
        .I2(\WrPtr_reg[3]_0 [0]),
        .I3(\WrPtr_reg[3]_0 [1]),
        .I4(\WrPtr_reg[3]_0 [3]),
        .O(WrPtr__0[3]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[0]),
        .Q(\WrPtr_reg[3]_0 [0]),
        .R(SR));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[1]),
        .Q(\WrPtr_reg[3]_0 [1]),
        .R(SR));
  FDRE \WrPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[2]),
        .Q(\WrPtr_reg[3]_0 [2]),
        .R(SR));
  FDRE \WrPtr_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[3]),
        .Q(\WrPtr_reg[3]_0 [3]),
        .R(SR));
  LUT5 #(
    .INIT(32'h57557777)) 
    empty_ff_i_1__18
       (.I0(user_rst_n_3ff_reg),
        .I1(\RdPtr[2]_i_4__1_n_0 ),
        .I2(empty_ff_reg_n_0),
        .I3(wpl_ld),
        .I4(FifoCntrRd_reg[0]),
        .O(empty_ff_i_1__18_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__18_n_0),
        .Q(empty_ff_reg_n_0),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \r_write_ptr[8]_i_1 
       (.I0(user_rst_n_3ff_reg),
        .O(SR));
  LUT6 #(
    .INIT(64'hAAAAAAA2FFFFFFFF)) 
    wpl_vld_ff_i_1
       (.I0(wpl_vld_ff),
        .I1(wtlp_sm_500[0]),
        .I2(wtlp_dat_fifo_af_nn1),
        .I3(wtlp_sm_500[2]),
        .I4(wtlp_sm_500[1]),
        .I5(empty_ff_reg_n_0),
        .O(wpl_vld_nxt));
  (* SOFT_HLUTNM = "soft_lutpair383" *) 
  LUT4 #(
    .INIT(16'h5556)) 
    \wtlp_dstbt_len_ff[0]_i_1 
       (.I0(wtlp_dstbt_whole_len1[3]),
        .I1(wtlp_dstbt_whole_len1[2]),
        .I2(wtlp_dstbt_whole_len1[0]),
        .I3(wtlp_dstbt_whole_len1[1]),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair383" *) 
  LUT5 #(
    .INIT(32'h5557AAA8)) 
    \wtlp_dstbt_len_ff[1]_i_1 
       (.I0(wtlp_dstbt_whole_len1[3]),
        .I1(wtlp_dstbt_whole_len1[1]),
        .I2(wtlp_dstbt_whole_len1[0]),
        .I3(wtlp_dstbt_whole_len1[2]),
        .I4(wtlp_dstbt_whole_len1[4]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h5557FFFFAAA80000)) 
    \wtlp_dstbt_len_ff[2]_i_1 
       (.I0(wtlp_dstbt_whole_len1[4]),
        .I1(wtlp_dstbt_whole_len1[2]),
        .I2(wtlp_dstbt_whole_len1[0]),
        .I3(wtlp_dstbt_whole_len1[1]),
        .I4(wtlp_dstbt_whole_len1[3]),
        .I5(wtlp_dstbt_whole_len1[5]),
        .O(D[2]));
  LUT2 #(
    .INIT(4'h6)) 
    \wtlp_dstbt_len_ff[2]_i_3 
       (.I0(wpl_bytelen[2]),
        .I1(\Head_reg[34]_0 [3]),
        .O(\wtlp_dstbt_len_ff[2]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \wtlp_dstbt_len_ff[2]_i_4 
       (.I0(wpl_bytelen[1]),
        .I1(\Head_reg[34]_0 [2]),
        .O(\wtlp_dstbt_len_ff[2]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \wtlp_dstbt_len_ff[2]_i_5 
       (.I0(wpl_bytelen[0]),
        .I1(\Head_reg[34]_0 [1]),
        .O(\wtlp_dstbt_len_ff[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \wtlp_dstbt_len_ff[3]_i_1 
       (.I0(\wtlp_dstbt_len_ff[7]_i_3_n_0 ),
        .I1(wtlp_dstbt_whole_len1[6]),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair387" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wtlp_dstbt_len_ff[4]_i_1 
       (.I0(\wtlp_dstbt_len_ff[7]_i_3_n_0 ),
        .I1(wtlp_dstbt_whole_len1[6]),
        .I2(wtlp_dstbt_whole_len1[7]),
        .O(D[4]));
  (* SOFT_HLUTNM = "soft_lutpair387" *) 
  LUT4 #(
    .INIT(16'hDF20)) 
    \wtlp_dstbt_len_ff[5]_i_1 
       (.I0(wtlp_dstbt_whole_len1[6]),
        .I1(\wtlp_dstbt_len_ff[7]_i_3_n_0 ),
        .I2(wtlp_dstbt_whole_len1[7]),
        .I3(wtlp_dstbt_whole_len1[8]),
        .O(D[5]));
  (* SOFT_HLUTNM = "soft_lutpair380" *) 
  LUT5 #(
    .INIT(32'hF7FF0800)) 
    \wtlp_dstbt_len_ff[6]_i_1 
       (.I0(wtlp_dstbt_whole_len1[8]),
        .I1(wtlp_dstbt_whole_len1[7]),
        .I2(\wtlp_dstbt_len_ff[7]_i_3_n_0 ),
        .I3(wtlp_dstbt_whole_len1[6]),
        .I4(wtlp_dstbt_whole_len1[9]),
        .O(D[6]));
  LUT6 #(
    .INIT(64'hF7FFFFFF08000000)) 
    \wtlp_dstbt_len_ff[7]_i_1 
       (.I0(wtlp_dstbt_whole_len1[9]),
        .I1(wtlp_dstbt_whole_len1[6]),
        .I2(\wtlp_dstbt_len_ff[7]_i_3_n_0 ),
        .I3(wtlp_dstbt_whole_len1[7]),
        .I4(wtlp_dstbt_whole_len1[8]),
        .I5(wtlp_dstbt_whole_len1[10]),
        .O(D[7]));
  LUT6 #(
    .INIT(64'h5557FFFFFFFFFFFF)) 
    \wtlp_dstbt_len_ff[7]_i_3 
       (.I0(wtlp_dstbt_whole_len1[4]),
        .I1(wtlp_dstbt_whole_len1[2]),
        .I2(wtlp_dstbt_whole_len1[0]),
        .I3(wtlp_dstbt_whole_len1[1]),
        .I4(wtlp_dstbt_whole_len1[3]),
        .I5(wtlp_dstbt_whole_len1[5]),
        .O(\wtlp_dstbt_len_ff[7]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0100FFFF)) 
    \wtlp_dstbt_len_ff[8]_i_1 
       (.I0(wtlp_sm_500[1]),
        .I1(wtlp_sm_500[2]),
        .I2(wtlp_dat_fifo_af_nn1),
        .I3(wtlp_sm_500[0]),
        .I4(wpl_vld_ff),
        .O(wpl_ld));
  LUT3 #(
    .INIT(8'hD2)) 
    \wtlp_dstbt_len_ff[8]_i_2 
       (.I0(wtlp_dstbt_whole_len1[10]),
        .I1(\wtlp_dstbt_len_ff[8]_i_4_n_0 ),
        .I2(wtlp_dstbt_whole_len1[11]),
        .O(D[8]));
  (* SOFT_HLUTNM = "soft_lutpair380" *) 
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \wtlp_dstbt_len_ff[8]_i_4 
       (.I0(wtlp_dstbt_whole_len1[8]),
        .I1(wtlp_dstbt_whole_len1[7]),
        .I2(\wtlp_dstbt_len_ff[7]_i_3_n_0 ),
        .I3(wtlp_dstbt_whole_len1[6]),
        .I4(wtlp_dstbt_whole_len1[9]),
        .O(\wtlp_dstbt_len_ff[8]_i_4_n_0 ));
  CARRY4 \wtlp_dstbt_len_ff_reg[2]_i_2 
       (.CI(1'b0),
        .CO({\wtlp_dstbt_len_ff_reg[2]_i_2_n_0 ,\wtlp_dstbt_len_ff_reg[2]_i_2_n_1 ,\wtlp_dstbt_len_ff_reg[2]_i_2_n_2 ,\wtlp_dstbt_len_ff_reg[2]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI(wpl_bytelen[3:0]),
        .O(wtlp_dstbt_whole_len1[3:0]),
        .S({wpl_bytelen[3],\wtlp_dstbt_len_ff[2]_i_3_n_0 ,\wtlp_dstbt_len_ff[2]_i_4_n_0 ,\wtlp_dstbt_len_ff[2]_i_5_n_0 }));
  CARRY4 \wtlp_dstbt_len_ff_reg[7]_i_2 
       (.CI(\wtlp_dstbt_len_ff_reg[2]_i_2_n_0 ),
        .CO({\wtlp_dstbt_len_ff_reg[7]_i_2_n_0 ,\wtlp_dstbt_len_ff_reg[7]_i_2_n_1 ,\wtlp_dstbt_len_ff_reg[7]_i_2_n_2 ,\wtlp_dstbt_len_ff_reg[7]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,wpl_bytelen[5:4]}),
        .O(wtlp_dstbt_whole_len1[7:4]),
        .S(wpl_bytelen[7:4]));
  CARRY4 \wtlp_dstbt_len_ff_reg[8]_i_3 
       (.CI(\wtlp_dstbt_len_ff_reg[7]_i_2_n_0 ),
        .CO({\wtlp_dstbt_len_ff_reg[8]_i_3_n_0 ,\wtlp_dstbt_len_ff_reg[8]_i_3_n_1 ,\wtlp_dstbt_len_ff_reg[8]_i_3_n_2 ,\wtlp_dstbt_len_ff_reg[8]_i_3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(wtlp_dstbt_whole_len1[11:8]),
        .S(wpl_bytelen[11:8]));
  (* SOFT_HLUTNM = "soft_lutpair384" *) 
  LUT4 #(
    .INIT(16'h5556)) 
    \wtlp_srcbt_len_ff[0]_i_1 
       (.I0(wtlp_srcbt_whole_len1[3]),
        .I1(wtlp_srcbt_whole_len1[2]),
        .I2(wtlp_srcbt_whole_len1[0]),
        .I3(wtlp_srcbt_whole_len1[1]),
        .O(\Head_reg[21]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair384" *) 
  LUT5 #(
    .INIT(32'h5557AAA8)) 
    \wtlp_srcbt_len_ff[1]_i_1 
       (.I0(wtlp_srcbt_whole_len1[3]),
        .I1(wtlp_srcbt_whole_len1[1]),
        .I2(wtlp_srcbt_whole_len1[0]),
        .I3(wtlp_srcbt_whole_len1[2]),
        .I4(wtlp_srcbt_whole_len1[4]),
        .O(\Head_reg[21]_0 [1]));
  LUT6 #(
    .INIT(64'h5557FFFFAAA80000)) 
    \wtlp_srcbt_len_ff[2]_i_1 
       (.I0(wtlp_srcbt_whole_len1[4]),
        .I1(wtlp_srcbt_whole_len1[2]),
        .I2(wtlp_srcbt_whole_len1[0]),
        .I3(wtlp_srcbt_whole_len1[1]),
        .I4(wtlp_srcbt_whole_len1[3]),
        .I5(wtlp_srcbt_whole_len1[5]),
        .O(\Head_reg[21]_0 [2]));
  LUT2 #(
    .INIT(4'h6)) 
    \wtlp_srcbt_len_ff[2]_i_3 
       (.I0(wpl_bytelen[2]),
        .I1(\Head_reg[34]_0 [9]),
        .O(\wtlp_srcbt_len_ff[2]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \wtlp_srcbt_len_ff[2]_i_4 
       (.I0(wpl_bytelen[1]),
        .I1(\Head_reg[34]_0 [8]),
        .O(\wtlp_srcbt_len_ff[2]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \wtlp_srcbt_len_ff[2]_i_5 
       (.I0(wpl_bytelen[0]),
        .I1(\Head_reg[34]_0 [7]),
        .O(\wtlp_srcbt_len_ff[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \wtlp_srcbt_len_ff[3]_i_1 
       (.I0(\wtlp_srcbt_len_ff[7]_i_3_n_0 ),
        .I1(wtlp_srcbt_whole_len1[6]),
        .O(\Head_reg[21]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair388" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wtlp_srcbt_len_ff[4]_i_1 
       (.I0(\wtlp_srcbt_len_ff[7]_i_3_n_0 ),
        .I1(wtlp_srcbt_whole_len1[6]),
        .I2(wtlp_srcbt_whole_len1[7]),
        .O(\Head_reg[21]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair388" *) 
  LUT4 #(
    .INIT(16'hDF20)) 
    \wtlp_srcbt_len_ff[5]_i_1 
       (.I0(wtlp_srcbt_whole_len1[6]),
        .I1(\wtlp_srcbt_len_ff[7]_i_3_n_0 ),
        .I2(wtlp_srcbt_whole_len1[7]),
        .I3(wtlp_srcbt_whole_len1[8]),
        .O(\Head_reg[21]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair381" *) 
  LUT5 #(
    .INIT(32'hF7FF0800)) 
    \wtlp_srcbt_len_ff[6]_i_1 
       (.I0(wtlp_srcbt_whole_len1[8]),
        .I1(wtlp_srcbt_whole_len1[7]),
        .I2(\wtlp_srcbt_len_ff[7]_i_3_n_0 ),
        .I3(wtlp_srcbt_whole_len1[6]),
        .I4(wtlp_srcbt_whole_len1[9]),
        .O(\Head_reg[21]_0 [6]));
  LUT6 #(
    .INIT(64'hF7FFFFFF08000000)) 
    \wtlp_srcbt_len_ff[7]_i_1 
       (.I0(wtlp_srcbt_whole_len1[9]),
        .I1(wtlp_srcbt_whole_len1[6]),
        .I2(\wtlp_srcbt_len_ff[7]_i_3_n_0 ),
        .I3(wtlp_srcbt_whole_len1[7]),
        .I4(wtlp_srcbt_whole_len1[8]),
        .I5(wtlp_srcbt_whole_len1[10]),
        .O(\Head_reg[21]_0 [7]));
  LUT6 #(
    .INIT(64'h5557FFFFFFFFFFFF)) 
    \wtlp_srcbt_len_ff[7]_i_3 
       (.I0(wtlp_srcbt_whole_len1[4]),
        .I1(wtlp_srcbt_whole_len1[2]),
        .I2(wtlp_srcbt_whole_len1[0]),
        .I3(wtlp_srcbt_whole_len1[1]),
        .I4(wtlp_srcbt_whole_len1[3]),
        .I5(wtlp_srcbt_whole_len1[5]),
        .O(\wtlp_srcbt_len_ff[7]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hD2)) 
    \wtlp_srcbt_len_ff[8]_i_1 
       (.I0(wtlp_srcbt_whole_len1[10]),
        .I1(\wtlp_srcbt_len_ff[8]_i_3_n_0 ),
        .I2(wtlp_srcbt_whole_len1[11]),
        .O(\Head_reg[21]_0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair381" *) 
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \wtlp_srcbt_len_ff[8]_i_3 
       (.I0(wtlp_srcbt_whole_len1[8]),
        .I1(wtlp_srcbt_whole_len1[7]),
        .I2(\wtlp_srcbt_len_ff[7]_i_3_n_0 ),
        .I3(wtlp_srcbt_whole_len1[6]),
        .I4(wtlp_srcbt_whole_len1[9]),
        .O(\wtlp_srcbt_len_ff[8]_i_3_n_0 ));
  CARRY4 \wtlp_srcbt_len_ff_reg[2]_i_2 
       (.CI(1'b0),
        .CO({\wtlp_srcbt_len_ff_reg[2]_i_2_n_0 ,\wtlp_srcbt_len_ff_reg[2]_i_2_n_1 ,\wtlp_srcbt_len_ff_reg[2]_i_2_n_2 ,\wtlp_srcbt_len_ff_reg[2]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI(wpl_bytelen[3:0]),
        .O(wtlp_srcbt_whole_len1[3:0]),
        .S({wpl_bytelen[3],\wtlp_srcbt_len_ff[2]_i_3_n_0 ,\wtlp_srcbt_len_ff[2]_i_4_n_0 ,\wtlp_srcbt_len_ff[2]_i_5_n_0 }));
  CARRY4 \wtlp_srcbt_len_ff_reg[7]_i_2 
       (.CI(\wtlp_srcbt_len_ff_reg[2]_i_2_n_0 ),
        .CO({\wtlp_srcbt_len_ff_reg[7]_i_2_n_0 ,\wtlp_srcbt_len_ff_reg[7]_i_2_n_1 ,\wtlp_srcbt_len_ff_reg[7]_i_2_n_2 ,\wtlp_srcbt_len_ff_reg[7]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,wpl_bytelen[5:4]}),
        .O(wtlp_srcbt_whole_len1[7:4]),
        .S(wpl_bytelen[7:4]));
  CARRY4 \wtlp_srcbt_len_ff_reg[8]_i_2 
       (.CI(\wtlp_srcbt_len_ff_reg[7]_i_2_n_0 ),
        .CO({\wtlp_srcbt_len_ff_reg[8]_i_2_n_0 ,\wtlp_srcbt_len_ff_reg[8]_i_2_n_1 ,\wtlp_srcbt_len_ff_reg[8]_i_2_n_2 ,\wtlp_srcbt_len_ff_reg[8]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(wtlp_srcbt_whole_len1[11:8]),
        .S(wpl_bytelen[11:8]));
  LUT4 #(
    .INIT(16'h0F0E)) 
    wtlp_srcbt_noinc_ff_i_1
       (.I0(wtlp_srcbt_noinc_ff_reg_i_2_n_5),
        .I1(wtlp_srcbt_noinc_ff_reg_i_2_n_6),
        .I2(\Head_reg_n_0_[1] ),
        .I3(wtlp_srcbt_noinc_ff_reg_i_2_n_7),
        .O(wtlp_srcbt_noinc));
  LUT2 #(
    .INIT(4'h6)) 
    wtlp_srcbt_noinc_ff_i_3
       (.I0(\Head_reg[34]_0 [9]),
        .I1(wpl_bytelen[2]),
        .O(wtlp_srcbt_noinc_ff_i_3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    wtlp_srcbt_noinc_ff_i_4
       (.I0(\Head_reg[34]_0 [8]),
        .I1(wpl_bytelen[1]),
        .O(wtlp_srcbt_noinc_ff_i_4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    wtlp_srcbt_noinc_ff_i_5
       (.I0(\Head_reg[34]_0 [7]),
        .I1(wpl_bytelen[0]),
        .O(wtlp_srcbt_noinc_ff_i_5_n_0));
  CARRY4 wtlp_srcbt_noinc_ff_reg_i_2
       (.CI(1'b0),
        .CO({wtlp_srcbt_noinc_ff_reg_i_2_n_0,wtlp_srcbt_noinc_ff_reg_i_2_n_1,wtlp_srcbt_noinc_ff_reg_i_2_n_2,wtlp_srcbt_noinc_ff_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,\Head_reg[34]_0 [9:7]}),
        .O({wtlp_srcbt_noinc_ff_reg_i_2_n_4,wtlp_srcbt_noinc_ff_reg_i_2_n_5,wtlp_srcbt_noinc_ff_reg_i_2_n_6,wtlp_srcbt_noinc_ff_reg_i_2_n_7}),
        .S({wpl_bytelen[3],wtlp_srcbt_noinc_ff_i_3_n_0,wtlp_srcbt_noinc_ff_i_4_n_0,wtlp_srcbt_noinc_ff_i_5_n_0}));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOHead2" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOHead2
   (m_axis_rq_tvalid_d_ff_reg,
    m_axis_rq_tlast_d_ff_reg,
    tag_sel_ff_reg,
    tag_sel_ff0,
    E,
    wtlp_hdr_pop00_out,
    \rreq_head_info_ff_reg[0][adr][63] ,
    \reqdtlpSm512_cs_reg[2] ,
    \reqdtlpSm_cs_reg[0] ,
    \rreq_head_info_ff_reg[1][lbe][2] ,
    \reqdtlpSm_cs_reg[1] ,
    \rreq_head_info_ff_reg[1][fbe][3] ,
    wtlp_dat_vld,
    \m_axis_rq_tuser_d_nxt[0]__0 ,
    \wpl_hdr_fbe_ff_reg[3] ,
    \wpl_hdr_lbe_ff_reg[0] ,
    \wpl_hdr_lbe_ff_reg[1] ,
    \wpl_hdr_lbe_ff_reg[2] ,
    \wpl_hdr_lbe_ff_reg[3] ,
    \reqdtlpSm512_cs_reg[0] ,
    \wtlp_dat_cnt_nn1_reg[2] ,
    wtlp_dat_ren,
    wtlp_wpl_wen_500_reg,
    \wtlp_rd_dat_cnt_nn1_reg[2] ,
    wtlp_wpl_wen_503_reg,
    wpl_hdr_btlene1_ff_reg,
    \reqdtlpSm_cs_reg[0]_0 ,
    \reqdtlpSm_cs_reg[1]_0 ,
    rdIssued_0,
    \rreq_head_info_ff_reg[0][tag][0] ,
    \rreq_head_vld_ff_reg[0] ,
    \rreq_head_info_nxt[0][rcb] ,
    \rreq_head_vld_ff_reg[0]_0 ,
    rreq_head_ld_new_1,
    \rreq_head_info_nxt[0][chn] ,
    \rreq_head_info_ff_reg[1][tag][5] ,
    \rreq_head_info_ff_reg[1][rid][5] ,
    \rreq_head_info_ff_reg[1][did][8] ,
    \rreq_head_info_ff_reg[1][adr][63] ,
    \wpl_hdr_btlenm1_ff_reg[9] ,
    \flush_txn_linkdown_ff_reg[3] ,
    \wtlp_hdr_rd_cnt_nn1_reg[2] ,
    wtlp_hdr_rd_ff0,
    SR,
    wcp_vld_ff_reg,
    \wrq_pnd_cnt_ff_reg[2] ,
    \reqdtlpSm512_cs_reg[0]_0 ,
    wpl_hdr_vld_nxt,
    \m_axis_rq\.tvalid ,
    empty_ff_reg_0,
    \rreq_head_vld_ff_reg[0]_1 ,
    \RcbAvail_new_ff_reg[8] ,
    \rreq_head_vld_ff_reg[0]_2 ,
    tag_rd,
    \rreq_head_info_ff_reg[0][tag][0]_0 ,
    \rreq_head_info_ff_reg[0][tag][0]_1 ,
    out,
    \Head_reg[126]_0 ,
    m_axis_rq_tvalid_d_ff_reg_0,
    m_axis_rq_tvalid_d_ff,
    m_axis_rq_tlast_d_nxt,
    D,
    tag_sel_ff,
    reqdtlpSm512_cs,
    force_ready_flush_ff,
    reqdtlpSm_cs,
    \FifoCntrWr_reg[0]_0 ,
    wtlp_hdr_ld_500,
    beatdone,
    \pcie_dma_in\.cfg_phy_link_down ,
    user_rst_n_3ff_reg,
    p_0_in123_out,
    Q,
    \m_axis_rq_thead_d_ff_reg[0][63] ,
    \reqdtlpSm_cs_reg[0]_1 ,
    \rreq_head_info_ff_reg[0][lbe][2] ,
    \rreq_head_info_ff_reg[0][lbe][2]_0 ,
    \rreq_head_info_ff_reg[0][fbe][3] ,
    \rreq_head_info_ff_reg[0][fbe][3]_0 ,
    wtlp_dat_vld_ff,
    \wtlp_dat_vld_ff_reg[0] ,
    wrreq,
    wr_user__0,
    \m_axis_rq_tuser_comb_ff_reg[3] ,
    \m_axis_rq_tuser_comb_ff_reg[3]_0 ,
    \m_axis_rq_tuser_comb_ff_reg[7] ,
    \m_axis_rq_tuser_comb_ff_reg[26] ,
    \beatrem_ff_reg[9] ,
    wr_user,
    m_axis_rq_tlast_d_ff_reg_0,
    \wtlp_dat_cnt_nn1_reg[3] ,
    wtlp_wpl_wen_500,
    \wtlp_rd_dat_cnt_nn1_reg[3] ,
    wtlp_wpl_wen_503,
    p_0_in116_out,
    wpl_hdr_btlene1_ff,
    rdIssued_s10,
    \rdIssued_ff_reg[0] ,
    wpl_hdr_chn_ff,
    \m_axis_rq_thead_d_ff_reg[0][32] ,
    \m_axis_rq_thead_d_ff_reg[0][9] ,
    \m_axis_rq_thead_d_ff_reg[0][10] ,
    \m_axis_rq_tuser_comb_ff_reg[0] ,
    \m_axis_rq_thead_d_ff_reg[0][37] ,
    rreq_rro_ff,
    \canissueRd_ff_reg[0] ,
    \canissueRd_ff_reg[0]_0 ,
    rreq_active0,
    \canissueRd_ff_reg[0]_1 ,
    \canissueRd_ff_reg[1] ,
    RcbAvail_upd_ff,
    RcbAvail_nxt0,
    \rreq_head_info_ff_reg[0][rcb][7] ,
    \rreq_head_info_ff_reg[0][rcb][0] ,
    \rreq_head_info_ff_reg[1][rcb] ,
    \rreq_head_info_ff_reg[0][rcb][1] ,
    \rreq_head_info_ff_reg[0][rcb][2] ,
    \rreq_head_info_ff_reg[0][rcb][3] ,
    \rreq_head_rcb_ok_ff_reg[1] ,
    \rreq_head_info_ff_reg[0][rcb][4] ,
    O,
    \rreq_head_info_ff_reg[0][rcb][7]_0 ,
    RcbAvail_nxt,
    \rreq_head_info_ff_reg[0][rcb][7]_1 ,
    tag_ep_0,
    tag_ep_1,
    empty_ff_0,
    \rreq_head_info_ff_reg[1][chn] ,
    \rreq_head_info_ff_reg[0][chn][0] ,
    \rreq_head_info_ff_reg[0][lbe][0] ,
    \rreq_head_info_ff_reg[0][tag][5] ,
    \tag_dout[1]_1 ,
    \tag_dout[0]_0 ,
    \rreq_head_info_ff_reg[0][rid][5] ,
    \rreq_head_info_ff_reg[0][did][8] ,
    \rreq_head_info_ff_reg[0][adr][63]_0 ,
    \beatrem_ff_reg[9]_0 ,
    \beatrem_ff_reg[9]_1 ,
    \beatrem_ff_reg[8] ,
    \beatrem_ff_reg[5] ,
    \beatrem_ff_reg[4] ,
    flush_txn_linkdown,
    \wtlp_hdr_rd_cnt_nn1_reg[3] ,
    wtlp_hdr_ld_501,
    wcp_vld_ff,
    \wrq_pnd_cnt_ff_reg[3] ,
    wpl_hdr_vld_ff,
    DI,
    S,
    \rreq_head_rcb_ok_ff_reg[1]_i_14_0 ,
    \rreq_head_rcb_ok_ff_reg[1]_i_14_1 ,
    \rreq_head_rcb_ok_ff_reg[1]_i_14_2 ,
    \RdPtr[1]_i_2__3 ,
    \rreq_head_info_ff_reg[0][len][3] ,
    \rreq_head_info_ff_reg[0][len][10] ,
    A,
    user_clk,
    \m_axis_rq\.tready );
  output m_axis_rq_tvalid_d_ff_reg;
  output m_axis_rq_tlast_d_ff_reg;
  output tag_sel_ff_reg;
  output tag_sel_ff0;
  output [0:0]E;
  output wtlp_hdr_pop00_out;
  output [63:0]\rreq_head_info_ff_reg[0][adr][63] ;
  output \reqdtlpSm512_cs_reg[2] ;
  output [0:0]\reqdtlpSm_cs_reg[0] ;
  output [2:0]\rreq_head_info_ff_reg[1][lbe][2] ;
  output \reqdtlpSm_cs_reg[1] ;
  output [1:0]\rreq_head_info_ff_reg[1][fbe][3] ;
  output [0:0]wtlp_dat_vld;
  output [7:0]\m_axis_rq_tuser_d_nxt[0]__0 ;
  output [3:0]\wpl_hdr_fbe_ff_reg[3] ;
  output \wpl_hdr_lbe_ff_reg[0] ;
  output \wpl_hdr_lbe_ff_reg[1] ;
  output \wpl_hdr_lbe_ff_reg[2] ;
  output \wpl_hdr_lbe_ff_reg[3] ;
  output [0:0]\reqdtlpSm512_cs_reg[0] ;
  output [2:0]\wtlp_dat_cnt_nn1_reg[2] ;
  output wtlp_dat_ren;
  output [0:0]wtlp_wpl_wen_500_reg;
  output [2:0]\wtlp_rd_dat_cnt_nn1_reg[2] ;
  output [0:0]wtlp_wpl_wen_503_reg;
  output wpl_hdr_btlene1_ff_reg;
  output \reqdtlpSm_cs_reg[0]_0 ;
  output \reqdtlpSm_cs_reg[1]_0 ;
  output rdIssued_0;
  output [1:0]\rreq_head_info_ff_reg[0][tag][0] ;
  output [1:0]\rreq_head_vld_ff_reg[0] ;
  output [7:0]\rreq_head_info_nxt[0][rcb] ;
  output [1:0]\rreq_head_vld_ff_reg[0]_0 ;
  output rreq_head_ld_new_1;
  output \rreq_head_info_nxt[0][chn] ;
  output [5:0]\rreq_head_info_ff_reg[1][tag][5] ;
  output [5:0]\rreq_head_info_ff_reg[1][rid][5] ;
  output [8:0]\rreq_head_info_ff_reg[1][did][8] ;
  output [61:0]\rreq_head_info_ff_reg[1][adr][63] ;
  output [9:0]\wpl_hdr_btlenm1_ff_reg[9] ;
  output \flush_txn_linkdown_ff_reg[3] ;
  output [3:0]\wtlp_hdr_rd_cnt_nn1_reg[2] ;
  output wtlp_hdr_rd_ff0;
  output [0:0]SR;
  output [0:0]wcp_vld_ff_reg;
  output [2:0]\wrq_pnd_cnt_ff_reg[2] ;
  output [0:0]\reqdtlpSm512_cs_reg[0]_0 ;
  output wpl_hdr_vld_nxt;
  output \m_axis_rq\.tvalid ;
  output empty_ff_reg_0;
  output [0:0]\rreq_head_vld_ff_reg[0]_1 ;
  output [1:0]\RcbAvail_new_ff_reg[8] ;
  output \rreq_head_vld_ff_reg[0]_2 ;
  output [1:0]tag_rd;
  output \rreq_head_info_ff_reg[0][tag][0]_0 ;
  output \rreq_head_info_ff_reg[0][tag][0]_1 ;
  output [10:0]out;
  output [76:0]\Head_reg[126]_0 ;
  input m_axis_rq_tvalid_d_ff_reg_0;
  input m_axis_rq_tvalid_d_ff;
  input m_axis_rq_tlast_d_nxt;
  input [76:0]D;
  input tag_sel_ff;
  input [1:0]reqdtlpSm512_cs;
  input force_ready_flush_ff;
  input [1:0]reqdtlpSm_cs;
  input \FifoCntrWr_reg[0]_0 ;
  input wtlp_hdr_ld_500;
  input beatdone;
  input \pcie_dma_in\.cfg_phy_link_down ;
  input [0:0]user_rst_n_3ff_reg;
  input p_0_in123_out;
  input [61:0]Q;
  input [61:0]\m_axis_rq_thead_d_ff_reg[0][63] ;
  input \reqdtlpSm_cs_reg[0]_1 ;
  input [2:0]\rreq_head_info_ff_reg[0][lbe][2] ;
  input [1:0]\rreq_head_info_ff_reg[0][lbe][2]_0 ;
  input [1:0]\rreq_head_info_ff_reg[0][fbe][3] ;
  input [0:0]\rreq_head_info_ff_reg[0][fbe][3]_0 ;
  input [0:0]wtlp_dat_vld_ff;
  input \wtlp_dat_vld_ff_reg[0] ;
  input wrreq;
  input [7:0]wr_user__0;
  input [3:0]\m_axis_rq_tuser_comb_ff_reg[3] ;
  input [3:0]\m_axis_rq_tuser_comb_ff_reg[3]_0 ;
  input [3:0]\m_axis_rq_tuser_comb_ff_reg[7] ;
  input \m_axis_rq_tuser_comb_ff_reg[26] ;
  input [9:0]\beatrem_ff_reg[9] ;
  input [4:0]wr_user;
  input m_axis_rq_tlast_d_ff_reg_0;
  input [3:0]\wtlp_dat_cnt_nn1_reg[3] ;
  input wtlp_wpl_wen_500;
  input [3:0]\wtlp_rd_dat_cnt_nn1_reg[3] ;
  input wtlp_wpl_wen_503;
  input p_0_in116_out;
  input wpl_hdr_btlene1_ff;
  input rdIssued_s10;
  input \rdIssued_ff_reg[0] ;
  input wpl_hdr_chn_ff;
  input \m_axis_rq_thead_d_ff_reg[0][32] ;
  input [9:0]\m_axis_rq_thead_d_ff_reg[0][9] ;
  input [10:0]\m_axis_rq_thead_d_ff_reg[0][10] ;
  input \m_axis_rq_tuser_comb_ff_reg[0] ;
  input [5:0]\m_axis_rq_thead_d_ff_reg[0][37] ;
  input rreq_rro_ff;
  input \canissueRd_ff_reg[0] ;
  input [1:0]\canissueRd_ff_reg[0]_0 ;
  input rreq_active0;
  input \canissueRd_ff_reg[0]_1 ;
  input \canissueRd_ff_reg[1] ;
  input RcbAvail_upd_ff;
  input [8:0]RcbAvail_nxt0;
  input [7:0]\rreq_head_info_ff_reg[0][rcb][7] ;
  input \rreq_head_info_ff_reg[0][rcb][0] ;
  input [7:0]\rreq_head_info_ff_reg[1][rcb] ;
  input \rreq_head_info_ff_reg[0][rcb][1] ;
  input \rreq_head_info_ff_reg[0][rcb][2] ;
  input \rreq_head_info_ff_reg[0][rcb][3] ;
  input [3:0]\rreq_head_rcb_ok_ff_reg[1] ;
  input \rreq_head_info_ff_reg[0][rcb][4] ;
  input [0:0]O;
  input \rreq_head_info_ff_reg[0][rcb][7]_0 ;
  input [0:0]RcbAvail_nxt;
  input [0:0]\rreq_head_info_ff_reg[0][rcb][7]_1 ;
  input tag_ep_0;
  input tag_ep_1;
  input empty_ff_0;
  input \rreq_head_info_ff_reg[1][chn] ;
  input [79:0]\rreq_head_info_ff_reg[0][chn][0] ;
  input \rreq_head_info_ff_reg[0][lbe][0] ;
  input [5:0]\rreq_head_info_ff_reg[0][tag][5] ;
  input [4:0]\tag_dout[1]_1 ;
  input [4:0]\tag_dout[0]_0 ;
  input [5:0]\rreq_head_info_ff_reg[0][rid][5] ;
  input [8:0]\rreq_head_info_ff_reg[0][did][8] ;
  input [61:0]\rreq_head_info_ff_reg[0][adr][63]_0 ;
  input [9:0]\beatrem_ff_reg[9]_0 ;
  input \beatrem_ff_reg[9]_1 ;
  input \beatrem_ff_reg[8] ;
  input \beatrem_ff_reg[5] ;
  input \beatrem_ff_reg[4] ;
  input flush_txn_linkdown;
  input [3:0]\wtlp_hdr_rd_cnt_nn1_reg[3] ;
  input wtlp_hdr_ld_501;
  input wcp_vld_ff;
  input [3:0]\wrq_pnd_cnt_ff_reg[3] ;
  input wpl_hdr_vld_ff;
  input [0:0]DI;
  input [0:0]S;
  input \rreq_head_rcb_ok_ff_reg[1]_i_14_0 ;
  input \rreq_head_rcb_ok_ff_reg[1]_i_14_1 ;
  input \rreq_head_rcb_ok_ff_reg[1]_i_14_2 ;
  input [0:0]\RdPtr[1]_i_2__3 ;
  input \rreq_head_info_ff_reg[0][len][3] ;
  input [10:0]\rreq_head_info_ff_reg[0][len][10] ;
  input [10:0]A;
  input user_clk;
  input \m_axis_rq\.tready ;

  wire [10:0]A;
  wire [76:0]D;
  wire [0:0]DI;
  wire [0:0]E;
  wire [1:0]FifoCntrRd;
  wire \FifoCntrRd[0]_i_1__7_n_0 ;
  wire \FifoCntrRd[1]_i_1__7_n_0 ;
  wire \FifoCntrRd[1]_i_2_n_0 ;
  wire [1:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__8_n_0 ;
  wire \FifoCntrWr[1]_i_1__11_n_0 ;
  wire \FifoCntrWr_reg[0]_0 ;
  wire \Head[63]_i_1__8_n_0 ;
  wire \Head[63]_i_2_n_0 ;
  wire \Head[63]_i_4_n_0 ;
  wire \Head[63]_i_5_n_0 ;
  wire [76:0]\Head_reg[126]_0 ;
  wire [126:0]MemArray;
  wire \MemArray[126]_i_1_n_0 ;
  wire [0:0]O;
  wire [61:0]Q;
  wire [1:0]\RcbAvail_new_ff_reg[8] ;
  wire [0:0]RcbAvail_nxt;
  wire [8:0]RcbAvail_nxt0;
  wire RcbAvail_upd_ff;
  (* MAX_FANOUT = "128" *) (* RTL_MAX_FANOUT = "found" *) wire RdPtr;
  wire \RdPtr[0]_i_1__9_n_0 ;
  wire [0:0]\RdPtr[1]_i_2__3 ;
  wire [0:0]S;
  wire [0:0]SR;
  wire WrEn0;
  (* MAX_FANOUT = "128" *) (* RTL_MAX_FANOUT = "found" *) wire WrPtr;
  wire beatdone;
  wire \beatrem_ff_reg[4] ;
  wire \beatrem_ff_reg[5] ;
  wire \beatrem_ff_reg[8] ;
  wire [9:0]\beatrem_ff_reg[9] ;
  wire [9:0]\beatrem_ff_reg[9]_0 ;
  wire \beatrem_ff_reg[9]_1 ;
  wire \canissueRd_ff_reg[0] ;
  wire [1:0]\canissueRd_ff_reg[0]_0 ;
  wire \canissueRd_ff_reg[0]_1 ;
  wire \canissueRd_ff_reg[1] ;
  wire empty_ff_0;
  wire empty_ff_i_1__11_n_0;
  wire empty_ff_reg_0;
  wire flush_txn_linkdown;
  wire \flush_txn_linkdown_ff_reg[3] ;
  wire force_ready_flush_ff;
  wire full_ff_i_1__6_n_0;
  wire full_ff_reg_n_0;
  wire [0:0]ldrem;
  wire \m_axis_rq\.tready ;
  wire \m_axis_rq\.tvalid ;
  wire \m_axis_rq_thead_d_ff[0][2]_i_2_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][2]_i_3_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][32]_i_4_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][32]_i_5_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][32]_i_7_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][39]_i_2_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][3]_i_2_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][3]_i_3_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][4]_i_2_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][4]_i_3_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][5]_i_2_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][5]_i_3_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][63]_i_7_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][6]_i_2_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][6]_i_3_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][7]_i_2_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][7]_i_3_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][8]_i_2_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][8]_i_3_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][9]_i_2_n_0 ;
  wire \m_axis_rq_thead_d_ff[0][9]_i_3_n_0 ;
  wire [10:0]\m_axis_rq_thead_d_ff_reg[0][10] ;
  wire \m_axis_rq_thead_d_ff_reg[0][32] ;
  wire [5:0]\m_axis_rq_thead_d_ff_reg[0][37] ;
  wire [61:0]\m_axis_rq_thead_d_ff_reg[0][63] ;
  wire [9:0]\m_axis_rq_thead_d_ff_reg[0][9] ;
  wire m_axis_rq_tlast_d_ff_reg;
  wire m_axis_rq_tlast_d_ff_reg_0;
  wire m_axis_rq_tlast_d_nxt;
  wire m_axis_rq_tlast_d_nxt13_out;
  wire \m_axis_rq_tuser_comb_ff[24]_i_2_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[24]_i_4_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[24]_i_5_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[26]_i_2_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[26]_i_3_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[26]_i_4_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[26]_i_5_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[26]_i_6_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[4]_i_2_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[4]_i_3_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[5]_i_2_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[5]_i_3_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[6]_i_2_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[6]_i_3_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[7]_i_2_n_0 ;
  wire \m_axis_rq_tuser_comb_ff[7]_i_3_n_0 ;
  wire \m_axis_rq_tuser_comb_ff_reg[0] ;
  wire \m_axis_rq_tuser_comb_ff_reg[26] ;
  wire [3:0]\m_axis_rq_tuser_comb_ff_reg[3] ;
  wire [3:0]\m_axis_rq_tuser_comb_ff_reg[3]_0 ;
  wire [3:0]\m_axis_rq_tuser_comb_ff_reg[7] ;
  wire \m_axis_rq_tuser_d_ff[0][0]_i_2_n_0 ;
  wire \m_axis_rq_tuser_d_ff[0][0]_i_3_n_0 ;
  wire \m_axis_rq_tuser_d_ff[0][1]_i_2_n_0 ;
  wire \m_axis_rq_tuser_d_ff[0][1]_i_3_n_0 ;
  wire \m_axis_rq_tuser_d_ff[0][2]_i_2_n_0 ;
  wire \m_axis_rq_tuser_d_ff[0][2]_i_3_n_0 ;
  wire \m_axis_rq_tuser_d_ff[0][3]_i_2_n_0 ;
  wire \m_axis_rq_tuser_d_ff[0][3]_i_3_n_0 ;
  wire [7:0]\m_axis_rq_tuser_d_nxt[0]__0 ;
  wire m_axis_rq_tvalid_d_ff;
  wire m_axis_rq_tvalid_d_ff_i_3_n_0;
  wire m_axis_rq_tvalid_d_ff_reg;
  wire m_axis_rq_tvalid_d_ff_reg_0;
  wire [10:0]out;
  wire p_0_in116_out;
  wire p_0_in123_out;
  wire [126:0]p_1_in;
  wire \pcie_dma_in\.cfg_phy_link_down ;
  wire rdIssued_0;
  wire \rdIssued_ff_reg[0] ;
  wire rdIssued_s01;
  wire rdIssued_s10;
  wire [1:0]reqdtlpSm512_cs;
  wire \reqdtlpSm512_cs[0]_i_12_n_0 ;
  wire \reqdtlpSm512_cs[0]_i_2_n_0 ;
  wire \reqdtlpSm512_cs[0]_i_3_n_0 ;
  wire \reqdtlpSm512_cs[0]_i_4_n_0 ;
  wire \reqdtlpSm512_cs[0]_i_5_n_0 ;
  wire \reqdtlpSm512_cs[0]_i_6_n_0 ;
  wire \reqdtlpSm512_cs[0]_i_7_n_0 ;
  wire \reqdtlpSm512_cs[0]_i_8_n_0 ;
  wire \reqdtlpSm512_cs[0]_i_9_n_0 ;
  wire \reqdtlpSm512_cs[2]_i_2_n_0 ;
  wire \reqdtlpSm512_cs[2]_i_3_n_0 ;
  wire \reqdtlpSm512_cs[2]_i_4_n_0 ;
  wire [0:0]\reqdtlpSm512_cs_reg[0] ;
  wire [0:0]\reqdtlpSm512_cs_reg[0]_0 ;
  wire \reqdtlpSm512_cs_reg[2] ;
  wire [1:0]reqdtlpSm_cs;
  wire \reqdtlpSm_cs[0]_i_2_n_0 ;
  wire \reqdtlpSm_cs[0]_i_3_n_0 ;
  wire \reqdtlpSm_cs[0]_i_4_n_0 ;
  wire \reqdtlpSm_cs[0]_i_5_n_0 ;
  wire \reqdtlpSm_cs[0]_i_9_n_0 ;
  wire \reqdtlpSm_cs[1]_i_2_n_0 ;
  wire \reqdtlpSm_cs[1]_i_3_n_0 ;
  wire [0:0]\reqdtlpSm_cs_reg[0] ;
  wire \reqdtlpSm_cs_reg[0]_0 ;
  wire \reqdtlpSm_cs_reg[0]_1 ;
  wire \reqdtlpSm_cs_reg[1] ;
  wire \reqdtlpSm_cs_reg[1]_0 ;
  wire rreq_active0;
  wire [7:0]rreq_head_info_both_rcb_nxt;
  wire \rreq_head_info_ff[0][len][10]_i_2_n_0 ;
  wire \rreq_head_info_ff[0][len][10]_i_3_n_0 ;
  wire \rreq_head_info_ff[0][len][10]_i_4_n_0 ;
  wire \rreq_head_info_ff[0][len][3]_i_3_n_0 ;
  wire \rreq_head_info_ff[0][len][3]_i_4_n_0 ;
  wire \rreq_head_info_ff[0][len][3]_i_5_n_0 ;
  wire \rreq_head_info_ff[0][len][3]_i_6_n_0 ;
  wire \rreq_head_info_ff[0][len][7]_i_2_n_0 ;
  wire \rreq_head_info_ff[0][len][7]_i_3_n_0 ;
  wire \rreq_head_info_ff[0][len][7]_i_4_n_0 ;
  wire \rreq_head_info_ff[0][len][7]_i_5_n_0 ;
  wire \rreq_head_info_ff[0][rcb][6]_i_2_n_0 ;
  wire \rreq_head_info_ff[0][rcb][6]_i_3_n_0 ;
  wire \rreq_head_info_ff[0][rcb][7]_i_2_n_0 ;
  wire \rreq_head_info_ff[0][rcb][7]_i_6_n_0 ;
  wire \rreq_head_info_ff[0][rcb][7]_i_7_n_0 ;
  wire [63:0]\rreq_head_info_ff_reg[0][adr][63] ;
  wire [61:0]\rreq_head_info_ff_reg[0][adr][63]_0 ;
  wire [79:0]\rreq_head_info_ff_reg[0][chn][0] ;
  wire [8:0]\rreq_head_info_ff_reg[0][did][8] ;
  wire [1:0]\rreq_head_info_ff_reg[0][fbe][3] ;
  wire [0:0]\rreq_head_info_ff_reg[0][fbe][3]_0 ;
  wire \rreq_head_info_ff_reg[0][lbe][0] ;
  wire [2:0]\rreq_head_info_ff_reg[0][lbe][2] ;
  wire [1:0]\rreq_head_info_ff_reg[0][lbe][2]_0 ;
  wire [10:0]\rreq_head_info_ff_reg[0][len][10] ;
  wire \rreq_head_info_ff_reg[0][len][10]_i_1_n_2 ;
  wire \rreq_head_info_ff_reg[0][len][10]_i_1_n_3 ;
  wire \rreq_head_info_ff_reg[0][len][3] ;
  wire \rreq_head_info_ff_reg[0][len][3]_i_1_n_0 ;
  wire \rreq_head_info_ff_reg[0][len][3]_i_1_n_1 ;
  wire \rreq_head_info_ff_reg[0][len][3]_i_1_n_2 ;
  wire \rreq_head_info_ff_reg[0][len][3]_i_1_n_3 ;
  wire \rreq_head_info_ff_reg[0][len][7]_i_1_n_0 ;
  wire \rreq_head_info_ff_reg[0][len][7]_i_1_n_1 ;
  wire \rreq_head_info_ff_reg[0][len][7]_i_1_n_2 ;
  wire \rreq_head_info_ff_reg[0][len][7]_i_1_n_3 ;
  wire \rreq_head_info_ff_reg[0][rcb][0] ;
  wire \rreq_head_info_ff_reg[0][rcb][1] ;
  wire \rreq_head_info_ff_reg[0][rcb][2] ;
  wire \rreq_head_info_ff_reg[0][rcb][3] ;
  wire \rreq_head_info_ff_reg[0][rcb][4] ;
  wire [7:0]\rreq_head_info_ff_reg[0][rcb][7] ;
  wire \rreq_head_info_ff_reg[0][rcb][7]_0 ;
  wire [0:0]\rreq_head_info_ff_reg[0][rcb][7]_1 ;
  wire [5:0]\rreq_head_info_ff_reg[0][rid][5] ;
  wire [1:0]\rreq_head_info_ff_reg[0][tag][0] ;
  wire \rreq_head_info_ff_reg[0][tag][0]_0 ;
  wire \rreq_head_info_ff_reg[0][tag][0]_1 ;
  wire [5:0]\rreq_head_info_ff_reg[0][tag][5] ;
  wire [61:0]\rreq_head_info_ff_reg[1][adr][63] ;
  wire \rreq_head_info_ff_reg[1][chn] ;
  wire [8:0]\rreq_head_info_ff_reg[1][did][8] ;
  wire [1:0]\rreq_head_info_ff_reg[1][fbe][3] ;
  wire [2:0]\rreq_head_info_ff_reg[1][lbe][2] ;
  wire [7:0]\rreq_head_info_ff_reg[1][rcb] ;
  wire [5:0]\rreq_head_info_ff_reg[1][rid][5] ;
  wire [5:0]\rreq_head_info_ff_reg[1][tag][5] ;
  wire \rreq_head_info_nxt[0][chn] ;
  wire [7:0]\rreq_head_info_nxt[0][rcb] ;
  wire rreq_head_ld_new_1;
  wire \rreq_head_rcb_ok_ff[0]_i_10_n_0 ;
  wire \rreq_head_rcb_ok_ff[0]_i_11_n_0 ;
  wire \rreq_head_rcb_ok_ff[0]_i_12_n_0 ;
  wire \rreq_head_rcb_ok_ff[0]_i_5_n_0 ;
  wire \rreq_head_rcb_ok_ff[0]_i_6_n_0 ;
  wire \rreq_head_rcb_ok_ff[0]_i_7_n_0 ;
  wire \rreq_head_rcb_ok_ff[0]_i_8_n_0 ;
  wire \rreq_head_rcb_ok_ff[0]_i_9_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_10_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_11_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_12_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_16_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_17_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_18_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_19_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_20_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_21_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_22_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_23_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_3_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_4_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_5_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_6_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_7_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_8_n_0 ;
  wire \rreq_head_rcb_ok_ff[1]_i_9_n_0 ;
  wire \rreq_head_rcb_ok_ff_reg[0]_i_2_n_0 ;
  wire \rreq_head_rcb_ok_ff_reg[0]_i_2_n_1 ;
  wire \rreq_head_rcb_ok_ff_reg[0]_i_2_n_2 ;
  wire \rreq_head_rcb_ok_ff_reg[0]_i_2_n_3 ;
  wire [3:0]\rreq_head_rcb_ok_ff_reg[1] ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_13_n_3 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_14_0 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_14_1 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_14_2 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_14_n_0 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_14_n_1 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_14_n_2 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_14_n_3 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_15_n_0 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_15_n_1 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_15_n_2 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_15_n_3 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_2_n_0 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_2_n_1 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_2_n_2 ;
  wire \rreq_head_rcb_ok_ff_reg[1]_i_2_n_3 ;
  wire \rreq_head_vld_ff[0]_i_3_n_0 ;
  wire [1:0]\rreq_head_vld_ff_reg[0] ;
  wire [1:0]\rreq_head_vld_ff_reg[0]_0 ;
  wire [0:0]\rreq_head_vld_ff_reg[0]_1 ;
  wire \rreq_head_vld_ff_reg[0]_2 ;
  wire rreq_rro_ff;
  wire [4:0]\tag_dout[0]_0 ;
  wire [4:0]\tag_dout[1]_1 ;
  wire tag_ep_0;
  wire tag_ep_1;
  wire [1:0]tag_rd;
  wire tag_sel_ff;
  wire tag_sel_ff0;
  wire tag_sel_ff_reg;
  wire user_clk;
  wire [0:0]user_rst_n_3ff_reg;
  wire wcp_vld_ff;
  wire [0:0]wcp_vld_ff_reg;
  wire \wpl_hdr_adr_ff[63]_i_3_n_0 ;
  wire wpl_hdr_btlene1_ff;
  wire wpl_hdr_btlene1_ff_reg;
  wire [9:0]\wpl_hdr_btlenm1_ff_reg[9] ;
  wire wpl_hdr_chn_ff;
  wire [3:0]\wpl_hdr_fbe_ff_reg[3] ;
  wire \wpl_hdr_lbe_ff_reg[0] ;
  wire \wpl_hdr_lbe_ff_reg[1] ;
  wire \wpl_hdr_lbe_ff_reg[2] ;
  wire \wpl_hdr_lbe_ff_reg[3] ;
  wire wpl_hdr_vld_ff;
  wire wpl_hdr_vld_nxt;
  wire [4:0]wr_user;
  wire [7:0]wr_user__0;
  wire \wrq_pnd_cnt_ff[3]_i_3_n_0 ;
  wire [2:0]\wrq_pnd_cnt_ff_reg[2] ;
  wire [3:0]\wrq_pnd_cnt_ff_reg[3] ;
  wire wrreq;
  wire \wseq_ff[3]_i_4_n_0 ;
  wire [2:0]\wtlp_dat_cnt_nn1_reg[2] ;
  wire [3:0]\wtlp_dat_cnt_nn1_reg[3] ;
  wire wtlp_dat_ren;
  wire [0:0]wtlp_dat_vld;
  wire [0:0]wtlp_dat_vld6_in;
  wire [0:0]wtlp_dat_vld_ff;
  wire \wtlp_dat_vld_ff[0]_i_2_n_0 ;
  wire \wtlp_dat_vld_ff[0]_i_3_n_0 ;
  wire \wtlp_dat_vld_ff[0]_i_4_n_0 ;
  wire \wtlp_dat_vld_ff[0]_i_6_n_0 ;
  wire \wtlp_dat_vld_ff_reg[0] ;
  wire wtlp_hdr_av_i_2_n_0;
  wire wtlp_hdr_ld_500;
  wire wtlp_hdr_ld_501;
  wire wtlp_hdr_pop00_out;
  wire \wtlp_hdr_rd_cnt_nn1[3]_i_2_n_0 ;
  wire \wtlp_hdr_rd_cnt_nn1[3]_i_3_n_0 ;
  wire [3:0]\wtlp_hdr_rd_cnt_nn1_reg[2] ;
  wire [3:0]\wtlp_hdr_rd_cnt_nn1_reg[3] ;
  wire wtlp_hdr_rd_ff0;
  wire [2:0]\wtlp_rd_dat_cnt_nn1_reg[2] ;
  wire [3:0]\wtlp_rd_dat_cnt_nn1_reg[3] ;
  wire wtlp_wpl_wen_500;
  wire [0:0]wtlp_wpl_wen_500_reg;
  wire wtlp_wpl_wen_503;
  wire [0:0]wtlp_wpl_wen_503_reg;
  wire [3:2]\NLW_rreq_head_info_ff_reg[0][len][10]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_rreq_head_info_ff_reg[0][len][10]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_rreq_head_rcb_ok_ff_reg[0]_i_1_CO_UNCONNECTED ;
  wire [3:0]\NLW_rreq_head_rcb_ok_ff_reg[0]_i_1_O_UNCONNECTED ;
  wire [3:0]\NLW_rreq_head_rcb_ok_ff_reg[0]_i_2_O_UNCONNECTED ;
  wire [3:1]\NLW_rreq_head_rcb_ok_ff_reg[1]_i_1_CO_UNCONNECTED ;
  wire [3:0]\NLW_rreq_head_rcb_ok_ff_reg[1]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_rreq_head_rcb_ok_ff_reg[1]_i_13_CO_UNCONNECTED ;
  wire [3:0]\NLW_rreq_head_rcb_ok_ff_reg[1]_i_13_O_UNCONNECTED ;
  wire [3:0]\NLW_rreq_head_rcb_ok_ff_reg[1]_i_2_O_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair1564" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__7 
       (.I0(FifoCntrRd[0]),
        .O(\FifoCntrRd[0]_i_1__7_n_0 ));
  LUT4 #(
    .INIT(16'h22D2)) 
    \FifoCntrRd[1]_i_1__7 
       (.I0(\m_axis_rq\.tready ),
        .I1(empty_ff_reg_0),
        .I2(m_axis_rq_tvalid_d_ff),
        .I3(full_ff_reg_n_0),
        .O(\FifoCntrRd[1]_i_1__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1564" *) 
  LUT4 #(
    .INIT(16'hD22D)) 
    \FifoCntrRd[1]_i_2 
       (.I0(m_axis_rq_tvalid_d_ff),
        .I1(full_ff_reg_n_0),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[0]),
        .O(\FifoCntrRd[1]_i_2_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[1]_i_1__7_n_0 ),
        .D(\FifoCntrRd[0]_i_1__7_n_0 ),
        .Q(FifoCntrRd[0]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[1]_i_1__7_n_0 ),
        .D(\FifoCntrRd[1]_i_2_n_0 ),
        .Q(FifoCntrRd[1]),
        .R(\Head[63]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1565" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__8 
       (.I0(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1565" *) 
  LUT4 #(
    .INIT(16'hD22D)) 
    \FifoCntrWr[1]_i_1__11 
       (.I0(m_axis_rq_tvalid_d_ff),
        .I1(full_ff_reg_n_0),
        .I2(FifoCntrWr[1]),
        .I3(FifoCntrWr[0]),
        .O(\FifoCntrWr[1]_i_1__11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1571" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \FifoCntrWr[3]_i_1__3 
       (.I0(wtlp_hdr_pop00_out),
        .I1(\FifoCntrWr_reg[0]_0 ),
        .I2(wtlp_hdr_ld_500),
        .O(E));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[1]_i_1__7_n_0 ),
        .D(\FifoCntrWr[0]_i_1__8_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[1]_i_1__7_n_0 ),
        .D(\FifoCntrWr[1]_i_1__11_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(\Head[63]_i_1__8_n_0 ));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[0]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[0]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[0]),
        .O(p_1_in[0]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[10]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[10]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[10]),
        .O(p_1_in[10]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[11]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[11]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[11]),
        .O(p_1_in[11]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[126]_i_1__1 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[76]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[126]),
        .O(p_1_in[126]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[12]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[12]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[12]),
        .O(p_1_in[12]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[13]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[13]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[13]),
        .O(p_1_in[13]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[14]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[14]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[14]),
        .O(p_1_in[14]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[15]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[15]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[15]),
        .O(p_1_in[15]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[16]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[16]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[16]),
        .O(p_1_in[16]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[17]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[17]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[17]),
        .O(p_1_in[17]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[18]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[18]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[18]),
        .O(p_1_in[18]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[19]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[19]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[19]),
        .O(p_1_in[19]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[1]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[1]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[1]),
        .O(p_1_in[1]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[20]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[20]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[20]),
        .O(p_1_in[20]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[21]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[21]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[21]),
        .O(p_1_in[21]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[22]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[22]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[22]),
        .O(p_1_in[22]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[23]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[23]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[23]),
        .O(p_1_in[23]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[24]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[24]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[24]),
        .O(p_1_in[24]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[25]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[25]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[25]),
        .O(p_1_in[25]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[26]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[26]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[26]),
        .O(p_1_in[26]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[27]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[27]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[27]),
        .O(p_1_in[27]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[28]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[28]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[28]),
        .O(p_1_in[28]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[29]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[29]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[29]),
        .O(p_1_in[29]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[2]_i_1__1 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[2]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[2]),
        .O(p_1_in[2]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[30]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[30]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[30]),
        .O(p_1_in[30]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[31]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[31]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[31]),
        .O(p_1_in[31]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[32]_i_1__2 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[32]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[32]),
        .O(p_1_in[32]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[33]_i_1__2 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[33]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[33]),
        .O(p_1_in[33]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[34]_i_1__1 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[34]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[34]),
        .O(p_1_in[34]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[35]_i_1__1 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[35]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[35]),
        .O(p_1_in[35]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[36]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[36]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[36]),
        .O(p_1_in[36]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[37]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[37]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[37]),
        .O(p_1_in[37]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[38]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[38]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[38]),
        .O(p_1_in[38]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[39]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[39]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[39]),
        .O(p_1_in[39]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[3]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[3]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[3]),
        .O(p_1_in[3]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[40]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[40]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[40]),
        .O(p_1_in[40]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[41]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[41]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[41]),
        .O(p_1_in[41]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[42]_i_1__1 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[42]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[42]),
        .O(p_1_in[42]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[43]_i_1__1 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[43]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[43]),
        .O(p_1_in[43]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[44]_i_1__1 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[44]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[44]),
        .O(p_1_in[44]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[45]_i_1__1 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[45]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[45]),
        .O(p_1_in[45]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[46]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[46]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[46]),
        .O(p_1_in[46]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[47]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[47]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[47]),
        .O(p_1_in[47]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[48]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[48]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[48]),
        .O(p_1_in[48]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[49]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[49]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[49]),
        .O(p_1_in[49]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[4]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[4]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[4]),
        .O(p_1_in[4]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[50]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[50]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[50]),
        .O(p_1_in[50]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[51]_i_1__4 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[51]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[51]),
        .O(p_1_in[51]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[52]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[52]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[52]),
        .O(p_1_in[52]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[53]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[53]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[53]),
        .O(p_1_in[53]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[54]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[54]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[54]),
        .O(p_1_in[54]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[55]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[55]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[55]),
        .O(p_1_in[55]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[56]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[56]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[56]),
        .O(p_1_in[56]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[57]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[57]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[57]),
        .O(p_1_in[57]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[58]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[58]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[58]),
        .O(p_1_in[58]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[59]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[59]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[59]),
        .O(p_1_in[59]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[5]_i_1__3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[5]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[5]),
        .O(p_1_in[5]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[60]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[60]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[60]),
        .O(p_1_in[60]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[61]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[61]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[61]),
        .O(p_1_in[61]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[62]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[62]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[62]),
        .O(p_1_in[62]));
  LUT2 #(
    .INIT(4'hB)) 
    \Head[63]_i_1__8 
       (.I0(\pcie_dma_in\.cfg_phy_link_down ),
        .I1(user_rst_n_3ff_reg),
        .O(\Head[63]_i_1__8_n_0 ));
  LUT4 #(
    .INIT(16'h3075)) 
    \Head[63]_i_2 
       (.I0(FifoCntrRd[1]),
        .I1(empty_ff_reg_0),
        .I2(\m_axis_rq\.tready ),
        .I3(FifoCntrRd[0]),
        .O(\Head[63]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[63]_i_3 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[63]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[63]),
        .O(p_1_in[63]));
  LUT5 #(
    .INIT(32'h00004F00)) 
    \Head[63]_i_4 
       (.I0(empty_ff_reg_0),
        .I1(\m_axis_rq\.tready ),
        .I2(FifoCntrRd[0]),
        .I3(m_axis_rq_tvalid_d_ff),
        .I4(full_ff_reg_n_0),
        .O(\Head[63]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFB0FFFF)) 
    \Head[63]_i_5 
       (.I0(empty_ff_reg_0),
        .I1(\m_axis_rq\.tready ),
        .I2(FifoCntrRd[0]),
        .I3(full_ff_reg_n_0),
        .I4(m_axis_rq_tvalid_d_ff),
        .O(\Head[63]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[66]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[64]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[66]),
        .O(p_1_in[66]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[67]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[65]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[67]),
        .O(p_1_in[67]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[68]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[66]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[68]),
        .O(p_1_in[68]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[69]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[67]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[69]),
        .O(p_1_in[69]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[6]_i_1__1 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[6]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[6]),
        .O(p_1_in[6]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[70]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[68]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[70]),
        .O(p_1_in[70]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[71]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[69]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[71]),
        .O(p_1_in[71]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[72]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[70]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[72]),
        .O(p_1_in[72]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[73]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[71]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[73]),
        .O(p_1_in[73]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[7]_i_1__1 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[7]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[7]),
        .O(p_1_in[7]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[8]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[8]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[8]),
        .O(p_1_in[8]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[90]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[72]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[90]),
        .O(p_1_in[90]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[91]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[73]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[91]),
        .O(p_1_in[91]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[92]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[74]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[92]),
        .O(p_1_in[92]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[93]_i_1__6 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[75]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[93]),
        .O(p_1_in[93]));
  LUT5 #(
    .INIT(32'hFFFC0808)) 
    \Head[9]_i_1__5 
       (.I0(\Head[63]_i_4_n_0 ),
        .I1(D[9]),
        .I2(FifoCntrRd[1]),
        .I3(\Head[63]_i_5_n_0 ),
        .I4(MemArray[9]),
        .O(p_1_in[9]));
  FDRE \Head_reg[0] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[0]),
        .Q(\Head_reg[126]_0 [0]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[10]),
        .Q(\Head_reg[126]_0 [10]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[11]),
        .Q(\Head_reg[126]_0 [11]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[126] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[126]),
        .Q(\Head_reg[126]_0 [76]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[12]),
        .Q(\Head_reg[126]_0 [12]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[13]),
        .Q(\Head_reg[126]_0 [13]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[14]),
        .Q(\Head_reg[126]_0 [14]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[15]),
        .Q(\Head_reg[126]_0 [15]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[16] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[16]),
        .Q(\Head_reg[126]_0 [16]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[17] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[17]),
        .Q(\Head_reg[126]_0 [17]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[18]),
        .Q(\Head_reg[126]_0 [18]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[19]),
        .Q(\Head_reg[126]_0 [19]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[1] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[1]),
        .Q(\Head_reg[126]_0 [1]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[20]),
        .Q(\Head_reg[126]_0 [20]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[21]),
        .Q(\Head_reg[126]_0 [21]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[22] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[22]),
        .Q(\Head_reg[126]_0 [22]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[23] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[23]),
        .Q(\Head_reg[126]_0 [23]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[24] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[24]),
        .Q(\Head_reg[126]_0 [24]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[25] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[25]),
        .Q(\Head_reg[126]_0 [25]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[26] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[26]),
        .Q(\Head_reg[126]_0 [26]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[27] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[27]),
        .Q(\Head_reg[126]_0 [27]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[28] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[28]),
        .Q(\Head_reg[126]_0 [28]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[29] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[29]),
        .Q(\Head_reg[126]_0 [29]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[2] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[2]),
        .Q(\Head_reg[126]_0 [2]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[30] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[30]),
        .Q(\Head_reg[126]_0 [30]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[31] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[31]),
        .Q(\Head_reg[126]_0 [31]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[32] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[32]),
        .Q(\Head_reg[126]_0 [32]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[33] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[33]),
        .Q(\Head_reg[126]_0 [33]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[34] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[34]),
        .Q(\Head_reg[126]_0 [34]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[35] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[35]),
        .Q(\Head_reg[126]_0 [35]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[36] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[36]),
        .Q(\Head_reg[126]_0 [36]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[37] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[37]),
        .Q(\Head_reg[126]_0 [37]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[38] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[38]),
        .Q(\Head_reg[126]_0 [38]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[39] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[39]),
        .Q(\Head_reg[126]_0 [39]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[3] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[3]),
        .Q(\Head_reg[126]_0 [3]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[40] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[40]),
        .Q(\Head_reg[126]_0 [40]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[41] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[41]),
        .Q(\Head_reg[126]_0 [41]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[42] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[42]),
        .Q(\Head_reg[126]_0 [42]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[43] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[43]),
        .Q(\Head_reg[126]_0 [43]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[44] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[44]),
        .Q(\Head_reg[126]_0 [44]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[45] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[45]),
        .Q(\Head_reg[126]_0 [45]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[46] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[46]),
        .Q(\Head_reg[126]_0 [46]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[47] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[47]),
        .Q(\Head_reg[126]_0 [47]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[48] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[48]),
        .Q(\Head_reg[126]_0 [48]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[49] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[49]),
        .Q(\Head_reg[126]_0 [49]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[4] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[4]),
        .Q(\Head_reg[126]_0 [4]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[50] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[50]),
        .Q(\Head_reg[126]_0 [50]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[51] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[51]),
        .Q(\Head_reg[126]_0 [51]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[52] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[52]),
        .Q(\Head_reg[126]_0 [52]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[53] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[53]),
        .Q(\Head_reg[126]_0 [53]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[54] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[54]),
        .Q(\Head_reg[126]_0 [54]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[55] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[55]),
        .Q(\Head_reg[126]_0 [55]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[56] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[56]),
        .Q(\Head_reg[126]_0 [56]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[57] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[57]),
        .Q(\Head_reg[126]_0 [57]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[58] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[58]),
        .Q(\Head_reg[126]_0 [58]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[59] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[59]),
        .Q(\Head_reg[126]_0 [59]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[5] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[5]),
        .Q(\Head_reg[126]_0 [5]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[60]),
        .Q(\Head_reg[126]_0 [60]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[61]),
        .Q(\Head_reg[126]_0 [61]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[62]),
        .Q(\Head_reg[126]_0 [62]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[63]),
        .Q(\Head_reg[126]_0 [63]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[66]),
        .Q(\Head_reg[126]_0 [64]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[67]),
        .Q(\Head_reg[126]_0 [65]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[68]),
        .Q(\Head_reg[126]_0 [66]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[69]),
        .Q(\Head_reg[126]_0 [67]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[6] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[6]),
        .Q(\Head_reg[126]_0 [6]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[70]),
        .Q(\Head_reg[126]_0 [68]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[71]),
        .Q(\Head_reg[126]_0 [69]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[72]),
        .Q(\Head_reg[126]_0 [70]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[73]),
        .Q(\Head_reg[126]_0 [71]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[7] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[7]),
        .Q(\Head_reg[126]_0 [7]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[8] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[8]),
        .Q(\Head_reg[126]_0 [8]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[90]),
        .Q(\Head_reg[126]_0 [72]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[91]),
        .Q(\Head_reg[126]_0 [73]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[92]),
        .Q(\Head_reg[126]_0 [74]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[93]),
        .Q(\Head_reg[126]_0 [75]),
        .R(\Head[63]_i_1__8_n_0 ));
  FDRE \Head_reg[9] 
       (.C(user_clk),
        .CE(\Head[63]_i_2_n_0 ),
        .D(p_1_in[9]),
        .Q(\Head_reg[126]_0 [9]),
        .R(\Head[63]_i_1__8_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \MemArray[126]_i_1 
       (.I0(full_ff_reg_n_0),
        .I1(m_axis_rq_tvalid_d_ff),
        .I2(WrPtr),
        .O(\MemArray[126]_i_1_n_0 ));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[0] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[0]),
        .Q(MemArray[0]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[10] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[10]),
        .Q(MemArray[10]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[11] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[11]),
        .Q(MemArray[11]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[126] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[76]),
        .Q(MemArray[126]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[12] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[12]),
        .Q(MemArray[12]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[13] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[13]),
        .Q(MemArray[13]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[14] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[14]),
        .Q(MemArray[14]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[15] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[15]),
        .Q(MemArray[15]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[16] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[16]),
        .Q(MemArray[16]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[17] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[17]),
        .Q(MemArray[17]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[18] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[18]),
        .Q(MemArray[18]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[19] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[19]),
        .Q(MemArray[19]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[1] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[1]),
        .Q(MemArray[1]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[20] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[20]),
        .Q(MemArray[20]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[21] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[21]),
        .Q(MemArray[21]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[22] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[22]),
        .Q(MemArray[22]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[23] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[23]),
        .Q(MemArray[23]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[24] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[24]),
        .Q(MemArray[24]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[25] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[25]),
        .Q(MemArray[25]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[26] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[26]),
        .Q(MemArray[26]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[27] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[27]),
        .Q(MemArray[27]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[28] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[28]),
        .Q(MemArray[28]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[29] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[29]),
        .Q(MemArray[29]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[2] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[2]),
        .Q(MemArray[2]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[30] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[30]),
        .Q(MemArray[30]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[31] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[31]),
        .Q(MemArray[31]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[32] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[32]),
        .Q(MemArray[32]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[33] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[33]),
        .Q(MemArray[33]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[34] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[34]),
        .Q(MemArray[34]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[35] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[35]),
        .Q(MemArray[35]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[36] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[36]),
        .Q(MemArray[36]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[37] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[37]),
        .Q(MemArray[37]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[38] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[38]),
        .Q(MemArray[38]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[39] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[39]),
        .Q(MemArray[39]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[3] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[3]),
        .Q(MemArray[3]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[40] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[40]),
        .Q(MemArray[40]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[41] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[41]),
        .Q(MemArray[41]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[42] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[42]),
        .Q(MemArray[42]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[43] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[43]),
        .Q(MemArray[43]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[44] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[44]),
        .Q(MemArray[44]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[45] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[45]),
        .Q(MemArray[45]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[46] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[46]),
        .Q(MemArray[46]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[47] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[47]),
        .Q(MemArray[47]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[48] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[48]),
        .Q(MemArray[48]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[49] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[49]),
        .Q(MemArray[49]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[4] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[4]),
        .Q(MemArray[4]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[50] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[50]),
        .Q(MemArray[50]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[51] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[51]),
        .Q(MemArray[51]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[52] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[52]),
        .Q(MemArray[52]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[53] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[53]),
        .Q(MemArray[53]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[54] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[54]),
        .Q(MemArray[54]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[55] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[55]),
        .Q(MemArray[55]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[56] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[56]),
        .Q(MemArray[56]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[57] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[57]),
        .Q(MemArray[57]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[58] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[58]),
        .Q(MemArray[58]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[59] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[59]),
        .Q(MemArray[59]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[5] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[5]),
        .Q(MemArray[5]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[60] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[60]),
        .Q(MemArray[60]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[61] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[61]),
        .Q(MemArray[61]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[62] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[62]),
        .Q(MemArray[62]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[63] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[63]),
        .Q(MemArray[63]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[66] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[64]),
        .Q(MemArray[66]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[67] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[65]),
        .Q(MemArray[67]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[68] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[66]),
        .Q(MemArray[68]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[69] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[67]),
        .Q(MemArray[69]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[6] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[6]),
        .Q(MemArray[6]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[70] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[68]),
        .Q(MemArray[70]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[71] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[69]),
        .Q(MemArray[71]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[72] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[70]),
        .Q(MemArray[72]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[73] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[71]),
        .Q(MemArray[73]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[7] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[7]),
        .Q(MemArray[7]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[8] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[8]),
        .Q(MemArray[8]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[90] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[72]),
        .Q(MemArray[90]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[91] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[73]),
        .Q(MemArray[91]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[92] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[74]),
        .Q(MemArray[92]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[93] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[75]),
        .Q(MemArray[93]),
        .R(1'b0));
  (* RAM_STYLE = "distributed" *) 
  FDRE \MemArray_reg[9] 
       (.C(user_clk),
        .CE(\MemArray[126]_i_1_n_0 ),
        .D(D[9]),
        .Q(MemArray[9]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    RQ_FIFOi_0
       (.I0(1'b0),
        .O(WrPtr));
  LUT3 #(
    .INIT(8'h08)) 
    \RdPtr[0]_i_1__9 
       (.I0(RdPtr),
        .I1(user_rst_n_3ff_reg),
        .I2(\pcie_dma_in\.cfg_phy_link_down ),
        .O(\RdPtr[0]_i_1__9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1547" *) 
  LUT5 #(
    .INIT(32'hDF00FFFF)) 
    \RdPtr[1]_i_3__0 
       (.I0(\canissueRd_ff_reg[0]_0 [0]),
        .I1(rdIssued_0),
        .I2(\canissueRd_ff_reg[0]_0 [1]),
        .I3(rreq_active0),
        .I4(\RdPtr[1]_i_2__3 ),
        .O(\rreq_head_vld_ff_reg[0]_2 ));
  LUT4 #(
    .INIT(16'h0800)) 
    \RdPtr[2]_i_2__1 
       (.I0(wtlp_dat_vld6_in),
        .I1(reqdtlpSm512_cs[1]),
        .I2(reqdtlpSm_cs[1]),
        .I3(reqdtlpSm_cs[0]),
        .O(wtlp_dat_ren));
  LUT6 #(
    .INIT(64'h1015101500001015)) 
    \RdPtr[3]_i_2 
       (.I0(empty_ff_0),
        .I1(tag_ep_1),
        .I2(tag_sel_ff),
        .I3(tag_ep_0),
        .I4(\canissueRd_ff_reg[0]_0 [1]),
        .I5(\rreq_head_vld_ff[0]_i_3_n_0 ),
        .O(tag_sel_ff0));
  LUT5 #(
    .INIT(32'h000B0000)) 
    \RdPtr[4]_i_2__0 
       (.I0(\rreq_head_vld_ff[0]_i_3_n_0 ),
        .I1(\canissueRd_ff_reg[0]_0 [1]),
        .I2(tag_ep_1),
        .I3(empty_ff_0),
        .I4(tag_sel_ff),
        .O(tag_rd[1]));
  LUT5 #(
    .INIT(32'h0000000B)) 
    \RdPtr[4]_i_3 
       (.I0(\rreq_head_vld_ff[0]_i_3_n_0 ),
        .I1(\canissueRd_ff_reg[0]_0 [1]),
        .I2(tag_ep_0),
        .I3(empty_ff_0),
        .I4(tag_sel_ff),
        .O(tag_rd[0]));
  (* MAX_FANOUT = "128" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1__9_n_0 ),
        .Q(RdPtr),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1561" *) 
  LUT3 #(
    .INIT(8'h8B)) 
    \beatrem_ff[0]_i_1__0 
       (.I0(\beatrem_ff_reg[9]_0 [0]),
        .I1(ldrem),
        .I2(\beatrem_ff_reg[9] [0]),
        .O(\wpl_hdr_btlenm1_ff_reg[9] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1561" *) 
  LUT4 #(
    .INIT(16'hAAC3)) 
    \beatrem_ff[1]_i_1__0 
       (.I0(\beatrem_ff_reg[9]_0 [1]),
        .I1(\beatrem_ff_reg[9] [1]),
        .I2(\beatrem_ff_reg[9] [0]),
        .I3(ldrem),
        .O(\wpl_hdr_btlenm1_ff_reg[9] [1]));
  LUT5 #(
    .INIT(32'hAAAACCC3)) 
    \beatrem_ff[2]_i_1__0 
       (.I0(\beatrem_ff_reg[9]_0 [2]),
        .I1(\beatrem_ff_reg[9] [2]),
        .I2(\beatrem_ff_reg[9] [0]),
        .I3(\beatrem_ff_reg[9] [1]),
        .I4(ldrem),
        .O(\wpl_hdr_btlenm1_ff_reg[9] [2]));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFFC0003)) 
    \beatrem_ff[3]_i_1__0 
       (.I0(\beatrem_ff_reg[9]_0 [3]),
        .I1(\beatrem_ff_reg[9] [0]),
        .I2(\beatrem_ff_reg[9] [1]),
        .I3(\beatrem_ff_reg[9] [2]),
        .I4(\beatrem_ff_reg[9] [3]),
        .I5(ldrem),
        .O(\wpl_hdr_btlenm1_ff_reg[9] [3]));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFFC0003)) 
    \beatrem_ff[4]_i_1__0 
       (.I0(\beatrem_ff_reg[9]_0 [4]),
        .I1(\beatrem_ff_reg[4] ),
        .I2(\beatrem_ff_reg[9] [3]),
        .I3(\beatrem_ff_reg[9] [2]),
        .I4(\beatrem_ff_reg[9] [4]),
        .I5(ldrem),
        .O(\wpl_hdr_btlenm1_ff_reg[9] [4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAF0F0F0C3)) 
    \beatrem_ff[5]_i_1__0 
       (.I0(\beatrem_ff_reg[9]_0 [5]),
        .I1(\beatrem_ff_reg[5] ),
        .I2(\beatrem_ff_reg[9] [5]),
        .I3(\beatrem_ff_reg[9] [0]),
        .I4(\beatrem_ff_reg[9] [1]),
        .I5(ldrem),
        .O(\wpl_hdr_btlenm1_ff_reg[9] [5]));
  LUT4 #(
    .INIT(16'hAA3C)) 
    \beatrem_ff[6]_i_1__0 
       (.I0(\beatrem_ff_reg[9]_0 [6]),
        .I1(\beatrem_ff_reg[8] ),
        .I2(\beatrem_ff_reg[9] [6]),
        .I3(ldrem),
        .O(\wpl_hdr_btlenm1_ff_reg[9] [6]));
  LUT5 #(
    .INIT(32'hAAAAF03C)) 
    \beatrem_ff[7]_i_1__0 
       (.I0(\beatrem_ff_reg[9]_0 [7]),
        .I1(\beatrem_ff_reg[8] ),
        .I2(\beatrem_ff_reg[9] [7]),
        .I3(\beatrem_ff_reg[9] [6]),
        .I4(ldrem),
        .O(\wpl_hdr_btlenm1_ff_reg[9] [7]));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFF3000C)) 
    \beatrem_ff[8]_i_1 
       (.I0(\beatrem_ff_reg[9]_0 [8]),
        .I1(\beatrem_ff_reg[8] ),
        .I2(\beatrem_ff_reg[9] [6]),
        .I3(\beatrem_ff_reg[9] [7]),
        .I4(\beatrem_ff_reg[9] [8]),
        .I5(ldrem),
        .O(\wpl_hdr_btlenm1_ff_reg[9] [8]));
  LUT6 #(
    .INIT(64'hFF30FF20FF00FF00)) 
    \beatrem_ff[9]_i_1 
       (.I0(reqdtlpSm_cs[0]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[1]),
        .I3(ldrem),
        .I4(reqdtlpSm512_cs[0]),
        .I5(wtlp_dat_vld6_in),
        .O(\reqdtlpSm_cs_reg[0] ));
  LUT4 #(
    .INIT(16'hAAC3)) 
    \beatrem_ff[9]_i_2 
       (.I0(\beatrem_ff_reg[9]_0 [9]),
        .I1(\beatrem_ff_reg[9] [9]),
        .I2(\beatrem_ff_reg[9]_1 ),
        .I3(ldrem),
        .O(\wpl_hdr_btlenm1_ff_reg[9] [9]));
  LUT6 #(
    .INIT(64'h000000000F020002)) 
    \beatrem_ff[9]_i_3 
       (.I0(wrreq),
        .I1(p_0_in123_out),
        .I2(reqdtlpSm_cs[1]),
        .I3(reqdtlpSm512_cs[0]),
        .I4(wtlp_dat_vld6_in),
        .I5(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(ldrem));
  LUT6 #(
    .INIT(64'hFCFCFFF00000AAA0)) 
    \canissueRd_ff[0]_i_1 
       (.I0(\canissueRd_ff_reg[0] ),
        .I1(\canissueRd_ff_reg[0]_0 [1]),
        .I2(rreq_active0),
        .I3(\canissueRd_ff_reg[0]_0 [0]),
        .I4(rdIssued_0),
        .I5(\canissueRd_ff_reg[0]_1 ),
        .O(\rreq_head_vld_ff_reg[0] [0]));
  LUT6 #(
    .INIT(64'hCCFF00C000AA0080)) 
    \canissueRd_ff[1]_i_1 
       (.I0(\canissueRd_ff_reg[1] ),
        .I1(rreq_active0),
        .I2(\canissueRd_ff_reg[0]_0 [0]),
        .I3(rdIssued_0),
        .I4(\canissueRd_ff_reg[0]_0 [1]),
        .I5(\canissueRd_ff_reg[0]_1 ),
        .O(\rreq_head_vld_ff_reg[0] [1]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00001055)) 
    empty_ff_i_1__11
       (.I0(FifoCntrRd[1]),
        .I1(empty_ff_reg_0),
        .I2(\m_axis_rq\.tready ),
        .I3(FifoCntrRd[0]),
        .I4(WrEn0),
        .I5(\Head[63]_i_1__8_n_0 ),
        .O(empty_ff_i_1__11_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1560" *) 
  LUT2 #(
    .INIT(4'h2)) 
    empty_ff_i_2__4
       (.I0(m_axis_rq_tvalid_d_ff),
        .I1(full_ff_reg_n_0),
        .O(WrEn0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__11_n_0),
        .Q(empty_ff_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000064406464)) 
    full_ff_i_1__6
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(WrEn0),
        .I3(empty_ff_reg_0),
        .I4(\m_axis_rq\.tready ),
        .I5(\Head[63]_i_1__8_n_0 ),
        .O(full_ff_i_1__6_n_0));
  FDRE full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(full_ff_i_1__6_n_0),
        .Q(full_ff_reg_n_0),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \m_axis_rq\.tvalid_INST_0 
       (.I0(empty_ff_reg_0),
        .O(\m_axis_rq\.tvalid ));
  LUT6 #(
    .INIT(64'h0A0000000C000000)) 
    \m_axis_rq_thead_d_ff[0][0]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][10] [0]),
        .I1(\m_axis_rq_thead_d_ff_reg[0][9] [0]),
        .I2(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I3(wtlp_dat_vld6_in),
        .I4(reqdtlpSm512_cs[0]),
        .I5(reqdtlpSm_cs[1]),
        .O(\rreq_head_info_ff_reg[0][adr][63] [0]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_thead_d_ff[0][10]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .I1(Q[8]),
        .I2(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I3(\m_axis_rq_thead_d_ff_reg[0][63] [8]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][10] [10]),
        .I5(rdIssued_0),
        .O(\rreq_head_info_ff_reg[0][adr][63] [10]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \m_axis_rq_thead_d_ff[0][11]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][39]_i_2_n_0 ),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(\m_axis_rq_thead_d_ff_reg[0][63] [9]),
        .I3(Q[9]),
        .I4(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [11]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][12]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [10]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[10]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [12]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][13]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [11]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[11]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [13]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][14]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [12]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[12]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [14]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][15]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [13]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[13]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [15]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][16]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [14]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[14]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [16]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][17]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [15]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[15]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [17]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][18]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [16]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[16]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [18]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][19]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [17]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[17]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [19]));
  LUT6 #(
    .INIT(64'h0A0000000C000000)) 
    \m_axis_rq_thead_d_ff[0][1]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][10] [1]),
        .I1(\m_axis_rq_thead_d_ff_reg[0][9] [1]),
        .I2(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I3(wtlp_dat_vld6_in),
        .I4(reqdtlpSm512_cs[0]),
        .I5(reqdtlpSm_cs[1]),
        .O(\rreq_head_info_ff_reg[0][adr][63] [1]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][20]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [18]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[18]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [20]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][21]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [19]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[19]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [21]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][22]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [20]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[20]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [22]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][23]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [21]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[21]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [23]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][24]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [22]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[22]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [24]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][25]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [23]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[23]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [25]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][26]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [24]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[24]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [26]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][27]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [25]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[25]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [27]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][28]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [26]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[26]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [28]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][29]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [27]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[27]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [29]));
  LUT6 #(
    .INIT(64'hFFFFFFFFF888F000)) 
    \m_axis_rq_thead_d_ff[0][2]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I1(p_0_in123_out),
        .I2(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [0]),
        .I5(\m_axis_rq_thead_d_ff[0][2]_i_2_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [2]));
  LUT6 #(
    .INIT(64'h00000000FFFFF888)) 
    \m_axis_rq_thead_d_ff[0][2]_i_2 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][9] [2]),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_5_n_0 ),
        .I2(Q[0]),
        .I3(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I4(\m_axis_rq_thead_d_ff[0][2]_i_3_n_0 ),
        .I5(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_thead_d_ff[0][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF800080008000)) 
    \m_axis_rq_thead_d_ff[0][2]_i_3 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][10] [2]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [0]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_thead_d_ff[0][2]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][30]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [28]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[28]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [30]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][31]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [29]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[29]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [31]));
  LUT6 #(
    .INIT(64'hFFFFFFFFF888F000)) 
    \m_axis_rq_thead_d_ff[0][32]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I1(p_0_in123_out),
        .I2(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I3(Q[30]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [30]),
        .I5(\m_axis_rq_thead_d_ff[0][32]_i_4_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [32]));
  LUT6 #(
    .INIT(64'h0800000000000000)) 
    \m_axis_rq_thead_d_ff[0][32]_i_2 
       (.I0(rdIssued_s01),
        .I1(reqdtlpSm512_cs[1]),
        .I2(reqdtlpSm_cs[1]),
        .I3(reqdtlpSm512_cs[0]),
        .I4(wtlp_dat_vld6_in),
        .I5(beatdone),
        .O(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hA200AAAAA200A200)) 
    \m_axis_rq_thead_d_ff[0][32]_i_3 
       (.I0(\m_axis_rq_thead_d_ff[0][63]_i_7_n_0 ),
        .I1(reqdtlpSm512_cs[0]),
        .I2(reqdtlpSm_cs[1]),
        .I3(reqdtlpSm512_cs[1]),
        .I4(p_0_in123_out),
        .I5(beatdone),
        .O(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFFF888)) 
    \m_axis_rq_thead_d_ff[0][32]_i_4 
       (.I0(wpl_hdr_chn_ff),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_5_n_0 ),
        .I2(Q[30]),
        .I3(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I4(\m_axis_rq_thead_d_ff[0][32]_i_7_n_0 ),
        .I5(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_thead_d_ff[0][32]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1560" *) 
  LUT5 #(
    .INIT(32'h00008A00)) 
    \m_axis_rq_thead_d_ff[0][32]_i_5 
       (.I0(reqdtlpSm512_cs[0]),
        .I1(force_ready_flush_ff),
        .I2(full_ff_reg_n_0),
        .I3(m_axis_rq_tvalid_d_ff),
        .I4(reqdtlpSm_cs[1]),
        .O(\m_axis_rq_thead_d_ff[0][32]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF800080008000)) 
    \m_axis_rq_thead_d_ff[0][32]_i_7 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][37] [0]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [30]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_thead_d_ff[0][32]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_thead_d_ff[0][33]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .I1(Q[31]),
        .I2(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I3(\m_axis_rq_thead_d_ff_reg[0][63] [31]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][37] [1]),
        .I5(rdIssued_0),
        .O(\rreq_head_info_ff_reg[0][adr][63] [33]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_thead_d_ff[0][34]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .I1(Q[32]),
        .I2(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I3(\m_axis_rq_thead_d_ff_reg[0][63] [32]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][37] [2]),
        .I5(rdIssued_0),
        .O(\rreq_head_info_ff_reg[0][adr][63] [34]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_thead_d_ff[0][35]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .I1(Q[33]),
        .I2(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I3(\m_axis_rq_thead_d_ff_reg[0][63] [33]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][37] [3]),
        .I5(rdIssued_0),
        .O(\rreq_head_info_ff_reg[0][adr][63] [35]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_thead_d_ff[0][36]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .I1(Q[34]),
        .I2(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I3(\m_axis_rq_thead_d_ff_reg[0][63] [34]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][37] [4]),
        .I5(rdIssued_0),
        .O(\rreq_head_info_ff_reg[0][adr][63] [36]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_thead_d_ff[0][37]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .I1(Q[35]),
        .I2(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I3(\m_axis_rq_thead_d_ff_reg[0][63] [35]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][37] [5]),
        .I5(rdIssued_0),
        .O(\rreq_head_info_ff_reg[0][adr][63] [37]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][38]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [36]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[36]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [38]));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \m_axis_rq_thead_d_ff[0][39]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][39]_i_2_n_0 ),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(\m_axis_rq_thead_d_ff_reg[0][63] [37]),
        .I3(Q[37]),
        .I4(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [39]));
  (* SOFT_HLUTNM = "soft_lutpair1551" *) 
  LUT5 #(
    .INIT(32'h00000800)) 
    \m_axis_rq_thead_d_ff[0][39]_i_2 
       (.I0(reqdtlpSm512_cs[0]),
        .I1(rdIssued_s01),
        .I2(reqdtlpSm512_cs[1]),
        .I3(wtlp_dat_vld6_in),
        .I4(reqdtlpSm_cs[1]),
        .O(\m_axis_rq_thead_d_ff[0][39]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF888F000)) 
    \m_axis_rq_thead_d_ff[0][3]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I1(p_0_in123_out),
        .I2(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I3(Q[1]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [1]),
        .I5(\m_axis_rq_thead_d_ff[0][3]_i_2_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [3]));
  LUT6 #(
    .INIT(64'h00000000FFFFF888)) 
    \m_axis_rq_thead_d_ff[0][3]_i_2 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][9] [3]),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_5_n_0 ),
        .I2(Q[1]),
        .I3(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I4(\m_axis_rq_thead_d_ff[0][3]_i_3_n_0 ),
        .I5(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_thead_d_ff[0][3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF800080008000)) 
    \m_axis_rq_thead_d_ff[0][3]_i_3 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][10] [3]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [1]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_thead_d_ff[0][3]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][40]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [38]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[38]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [40]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][41]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [39]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[39]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [41]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][42]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [40]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[40]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [42]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][43]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [41]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[41]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [43]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][44]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [42]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[42]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [44]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][45]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [43]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[43]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [45]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][46]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [44]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[44]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [46]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][47]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [45]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[45]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [47]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][48]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [46]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[46]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [48]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][49]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [47]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[47]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [49]));
  LUT6 #(
    .INIT(64'hFFFFFFFFF888F000)) 
    \m_axis_rq_thead_d_ff[0][4]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I1(p_0_in123_out),
        .I2(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I3(Q[2]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [2]),
        .I5(\m_axis_rq_thead_d_ff[0][4]_i_2_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [4]));
  LUT6 #(
    .INIT(64'h00000000FFFFF888)) 
    \m_axis_rq_thead_d_ff[0][4]_i_2 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][9] [4]),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_5_n_0 ),
        .I2(Q[2]),
        .I3(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I4(\m_axis_rq_thead_d_ff[0][4]_i_3_n_0 ),
        .I5(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_thead_d_ff[0][4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF800080008000)) 
    \m_axis_rq_thead_d_ff[0][4]_i_3 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][10] [4]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [2]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_thead_d_ff[0][4]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][50]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [48]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[48]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [50]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][51]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [49]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[49]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [51]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][52]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [50]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[50]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [52]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][53]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [51]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[51]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [53]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][54]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [52]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[52]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [54]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][55]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [53]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[53]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [55]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][56]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [54]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[54]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [56]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][57]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [55]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[55]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [57]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][58]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [56]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[56]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [58]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][59]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [57]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[57]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [59]));
  LUT6 #(
    .INIT(64'hFFFFFFFFF888F000)) 
    \m_axis_rq_thead_d_ff[0][5]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I1(p_0_in123_out),
        .I2(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I3(Q[3]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [3]),
        .I5(\m_axis_rq_thead_d_ff[0][5]_i_2_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [5]));
  LUT6 #(
    .INIT(64'h00000000FFFFF888)) 
    \m_axis_rq_thead_d_ff[0][5]_i_2 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][9] [5]),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_5_n_0 ),
        .I2(Q[3]),
        .I3(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I4(\m_axis_rq_thead_d_ff[0][5]_i_3_n_0 ),
        .I5(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_thead_d_ff[0][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF800080008000)) 
    \m_axis_rq_thead_d_ff[0][5]_i_3 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][10] [5]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [3]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_thead_d_ff[0][5]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][60]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [58]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[58]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [60]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_thead_d_ff[0][61]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .I1(Q[59]),
        .I2(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I3(\m_axis_rq_thead_d_ff_reg[0][63] [59]),
        .I4(rreq_rro_ff),
        .I5(rdIssued_0),
        .O(\rreq_head_info_ff_reg[0][adr][63] [61]));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][62]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [60]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[60]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [62]));
  (* SOFT_HLUTNM = "soft_lutpair1557" *) 
  LUT5 #(
    .INIT(32'hFFFF0002)) 
    \m_axis_rq_thead_d_ff[0][63]_i_1 
       (.I0(rdIssued_s01),
        .I1(reqdtlpSm512_cs[0]),
        .I2(reqdtlpSm_cs[1]),
        .I3(reqdtlpSm512_cs[1]),
        .I4(wtlp_dat_vld6_in),
        .O(\reqdtlpSm512_cs_reg[0] ));
  LUT4 #(
    .INIT(16'hF888)) 
    \m_axis_rq_thead_d_ff[0][63]_i_2 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][63] [61]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(Q[61]),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [63]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000001)) 
    \m_axis_rq_thead_d_ff[0][63]_i_3 
       (.I0(\rdIssued_ff_reg[0] ),
        .I1(reqdtlpSm512_cs[1]),
        .I2(reqdtlpSm512_cs[1]),
        .I3(reqdtlpSm_cs[1]),
        .I4(reqdtlpSm_cs[0]),
        .I5(wtlp_dat_vld6_in),
        .O(rdIssued_s01));
  LUT6 #(
    .INIT(64'hFF01010100000000)) 
    \m_axis_rq_thead_d_ff[0][63]_i_4 
       (.I0(reqdtlpSm512_cs[0]),
        .I1(reqdtlpSm_cs[1]),
        .I2(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I3(\reqdtlpSm_cs[0]_i_5_n_0 ),
        .I4(beatdone),
        .I5(p_0_in123_out),
        .O(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h30303030B0B0FFB0)) 
    \m_axis_rq_thead_d_ff[0][63]_i_5 
       (.I0(beatdone),
        .I1(\reqdtlpSm_cs_reg[0]_1 ),
        .I2(\m_axis_rq_thead_d_ff[0][63]_i_7_n_0 ),
        .I3(wrreq),
        .I4(\reqdtlpSm_cs[0]_i_9_n_0 ),
        .I5(p_0_in123_out),
        .O(\m_axis_rq_thead_d_ff[0][63]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1556" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \m_axis_rq_thead_d_ff[0][63]_i_7 
       (.I0(wrreq),
        .I1(wtlp_dat_vld6_in),
        .I2(reqdtlpSm512_cs[1]),
        .I3(reqdtlpSm_cs[1]),
        .I4(rdIssued_s01),
        .O(\m_axis_rq_thead_d_ff[0][63]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF888F000)) 
    \m_axis_rq_thead_d_ff[0][6]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I1(p_0_in123_out),
        .I2(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I3(Q[4]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [4]),
        .I5(\m_axis_rq_thead_d_ff[0][6]_i_2_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [6]));
  LUT6 #(
    .INIT(64'h00000000FFFFF888)) 
    \m_axis_rq_thead_d_ff[0][6]_i_2 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][9] [6]),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_5_n_0 ),
        .I2(Q[4]),
        .I3(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I4(\m_axis_rq_thead_d_ff[0][6]_i_3_n_0 ),
        .I5(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_thead_d_ff[0][6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF800080008000)) 
    \m_axis_rq_thead_d_ff[0][6]_i_3 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][10] [6]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [4]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_thead_d_ff[0][6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF888F000)) 
    \m_axis_rq_thead_d_ff[0][7]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I1(p_0_in123_out),
        .I2(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I3(Q[5]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [5]),
        .I5(\m_axis_rq_thead_d_ff[0][7]_i_2_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [7]));
  LUT6 #(
    .INIT(64'h00000000FFFFF888)) 
    \m_axis_rq_thead_d_ff[0][7]_i_2 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][9] [7]),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_5_n_0 ),
        .I2(Q[5]),
        .I3(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I4(\m_axis_rq_thead_d_ff[0][7]_i_3_n_0 ),
        .I5(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_thead_d_ff[0][7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF800080008000)) 
    \m_axis_rq_thead_d_ff[0][7]_i_3 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][10] [7]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [5]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_thead_d_ff[0][7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF888F000)) 
    \m_axis_rq_thead_d_ff[0][8]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I1(p_0_in123_out),
        .I2(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I3(Q[6]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [6]),
        .I5(\m_axis_rq_thead_d_ff[0][8]_i_2_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [8]));
  LUT6 #(
    .INIT(64'h00000000FFFFF888)) 
    \m_axis_rq_thead_d_ff[0][8]_i_2 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][9] [8]),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_5_n_0 ),
        .I2(Q[6]),
        .I3(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I4(\m_axis_rq_thead_d_ff[0][8]_i_3_n_0 ),
        .I5(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_thead_d_ff[0][8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF800080008000)) 
    \m_axis_rq_thead_d_ff[0][8]_i_3 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][10] [8]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [6]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_thead_d_ff[0][8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF888F000)) 
    \m_axis_rq_thead_d_ff[0][9]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I1(p_0_in123_out),
        .I2(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I3(Q[7]),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [7]),
        .I5(\m_axis_rq_thead_d_ff[0][9]_i_2_n_0 ),
        .O(\rreq_head_info_ff_reg[0][adr][63] [9]));
  LUT6 #(
    .INIT(64'h00000000FFFFF888)) 
    \m_axis_rq_thead_d_ff[0][9]_i_2 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][9] [9]),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_5_n_0 ),
        .I2(Q[7]),
        .I3(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I4(\m_axis_rq_thead_d_ff[0][9]_i_3_n_0 ),
        .I5(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_thead_d_ff[0][9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF800080008000)) 
    \m_axis_rq_thead_d_ff[0][9]_i_3 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][10] [9]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\m_axis_rq_thead_d_ff_reg[0][63] [7]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_thead_d_ff[0][9]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    m_axis_rq_tlast_d_ff_i_1
       (.I0(m_axis_rq_tlast_d_nxt),
        .I1(m_axis_rq_tlast_d_nxt13_out),
        .I2(D[76]),
        .O(m_axis_rq_tlast_d_ff_reg));
  LUT6 #(
    .INIT(64'h00F0F0B000000010)) 
    m_axis_rq_tlast_d_ff_i_3
       (.I0(reqdtlpSm512_cs[0]),
        .I1(m_axis_rq_tlast_d_ff_reg_0),
        .I2(rdIssued_s01),
        .I3(reqdtlpSm_cs[1]),
        .I4(reqdtlpSm512_cs[1]),
        .I5(wtlp_dat_vld6_in),
        .O(m_axis_rq_tlast_d_nxt13_out));
  (* SOFT_HLUTNM = "soft_lutpair1552" *) 
  LUT5 #(
    .INIT(32'hFFFF88F8)) 
    \m_axis_rq_tuser_comb_ff[0]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I1(wr_user__0[0]),
        .I2(\m_axis_rq_tuser_d_ff[0][0]_i_3_n_0 ),
        .I3(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I4(\m_axis_rq_tuser_d_ff[0][0]_i_2_n_0 ),
        .O(\wpl_hdr_fbe_ff_reg[3] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1553" *) 
  LUT5 #(
    .INIT(32'hFFFF88F8)) 
    \m_axis_rq_tuser_comb_ff[1]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I1(wr_user__0[1]),
        .I2(\m_axis_rq_tuser_d_ff[0][1]_i_3_n_0 ),
        .I3(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I4(\m_axis_rq_tuser_d_ff[0][1]_i_2_n_0 ),
        .O(\wpl_hdr_fbe_ff_reg[3] [1]));
  LUT6 #(
    .INIT(64'hFFFFAA80AA80AA80)) 
    \m_axis_rq_tuser_comb_ff[24]_i_1 
       (.I0(wr_user[1]),
        .I1(\m_axis_rq_tuser_comb_ff[24]_i_2_n_0 ),
        .I2(wrreq),
        .I3(\m_axis_rq_tuser_comb_ff[24]_i_4_n_0 ),
        .I4(D[72]),
        .I5(\m_axis_rq_tuser_comb_ff[24]_i_5_n_0 ),
        .O(\m_axis_rq_tuser_d_nxt[0]__0 [4]));
  LUT4 #(
    .INIT(16'h0001)) 
    \m_axis_rq_tuser_comb_ff[24]_i_2 
       (.I0(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(p_0_in123_out),
        .O(\m_axis_rq_tuser_comb_ff[24]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hD0D0FFD000000000)) 
    \m_axis_rq_tuser_comb_ff[24]_i_4 
       (.I0(reqdtlpSm512_cs[0]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[1]),
        .I3(beatdone),
        .I4(p_0_in123_out),
        .I5(\m_axis_rq_thead_d_ff[0][63]_i_7_n_0 ),
        .O(\m_axis_rq_tuser_comb_ff[24]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FEFEFEFF)) 
    \m_axis_rq_tuser_comb_ff[24]_i_5 
       (.I0(reqdtlpSm512_cs[0]),
        .I1(reqdtlpSm_cs[1]),
        .I2(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I3(wrreq),
        .I4(p_0_in123_out),
        .I5(wtlp_dat_vld6_in),
        .O(\m_axis_rq_tuser_comb_ff[24]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAA80AA80AA80)) 
    \m_axis_rq_tuser_comb_ff[25]_i_1 
       (.I0(wr_user[2]),
        .I1(\m_axis_rq_tuser_comb_ff[24]_i_2_n_0 ),
        .I2(wrreq),
        .I3(\m_axis_rq_tuser_comb_ff[24]_i_4_n_0 ),
        .I4(D[73]),
        .I5(\m_axis_rq_tuser_comb_ff[24]_i_5_n_0 ),
        .O(\m_axis_rq_tuser_d_nxt[0]__0 [5]));
  LUT5 #(
    .INIT(32'hFFFFFF40)) 
    \m_axis_rq_tuser_comb_ff[26]_i_1 
       (.I0(p_0_in123_out),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I2(\m_axis_rq_tuser_comb_ff[26]_i_2_n_0 ),
        .I3(\m_axis_rq_tuser_comb_ff[26]_i_3_n_0 ),
        .I4(\m_axis_rq_tuser_comb_ff[26]_i_4_n_0 ),
        .O(\m_axis_rq_tuser_d_nxt[0]__0 [6]));
  LUT6 #(
    .INIT(64'hA0ACA0ACACACA0AC)) 
    \m_axis_rq_tuser_comb_ff[26]_i_2 
       (.I0(wr_user[3]),
        .I1(D[74]),
        .I2(wrreq),
        .I3(m_axis_rq_tvalid_d_ff),
        .I4(full_ff_reg_n_0),
        .I5(force_ready_flush_ff),
        .O(\m_axis_rq_tuser_comb_ff[26]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h88F8F88888888888)) 
    \m_axis_rq_tuser_comb_ff[26]_i_3 
       (.I0(D[74]),
        .I1(\m_axis_rq_tuser_comb_ff[26]_i_5_n_0 ),
        .I2(\m_axis_rq_tuser_comb_ff_reg[26] ),
        .I3(\beatrem_ff_reg[9] [0]),
        .I4(\beatrem_ff_reg[9] [1]),
        .I5(\reqdtlpSm_cs[0]_i_5_n_0 ),
        .O(\m_axis_rq_tuser_comb_ff[26]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h08FF0808)) 
    \m_axis_rq_tuser_comb_ff[26]_i_4 
       (.I0(wr_user[3]),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_7_n_0 ),
        .I2(\reqdtlpSm_cs_reg[0]_1 ),
        .I3(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I4(\m_axis_rq_tuser_comb_ff[26]_i_6_n_0 ),
        .O(\m_axis_rq_tuser_comb_ff[26]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1562" *) 
  LUT4 #(
    .INIT(16'h22A2)) 
    \m_axis_rq_tuser_comb_ff[26]_i_5 
       (.I0(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I1(m_axis_rq_tvalid_d_ff),
        .I2(full_ff_reg_n_0),
        .I3(force_ready_flush_ff),
        .O(\m_axis_rq_tuser_comb_ff[26]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000808FF000B08)) 
    \m_axis_rq_tuser_comb_ff[26]_i_6 
       (.I0(wr_user[3]),
        .I1(wrreq),
        .I2(p_0_in123_out),
        .I3(D[74]),
        .I4(\rdIssued_ff_reg[0] ),
        .I5(wtlp_dat_vld6_in),
        .O(\m_axis_rq_tuser_comb_ff[26]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAA80AA80AA80)) 
    \m_axis_rq_tuser_comb_ff[27]_i_1 
       (.I0(wr_user[4]),
        .I1(\m_axis_rq_tuser_comb_ff[24]_i_2_n_0 ),
        .I2(wrreq),
        .I3(\m_axis_rq_tuser_comb_ff[24]_i_4_n_0 ),
        .I4(D[75]),
        .I5(\m_axis_rq_tuser_comb_ff[24]_i_5_n_0 ),
        .O(\m_axis_rq_tuser_d_nxt[0]__0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair1554" *) 
  LUT5 #(
    .INIT(32'hFFFF88F8)) 
    \m_axis_rq_tuser_comb_ff[2]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I1(wr_user__0[2]),
        .I2(\m_axis_rq_tuser_d_ff[0][2]_i_3_n_0 ),
        .I3(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I4(\m_axis_rq_tuser_d_ff[0][2]_i_2_n_0 ),
        .O(\wpl_hdr_fbe_ff_reg[3] [2]));
  (* SOFT_HLUTNM = "soft_lutpair1555" *) 
  LUT5 #(
    .INIT(32'hFFFF88F8)) 
    \m_axis_rq_tuser_comb_ff[3]_i_1 
       (.I0(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I1(wr_user__0[3]),
        .I2(\m_axis_rq_tuser_d_ff[0][3]_i_3_n_0 ),
        .I3(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I4(\m_axis_rq_tuser_d_ff[0][3]_i_2_n_0 ),
        .O(\wpl_hdr_fbe_ff_reg[3] [3]));
  LUT5 #(
    .INIT(32'hEAEAFFEA)) 
    \m_axis_rq_tuser_comb_ff[4]_i_1 
       (.I0(\m_axis_rq_tuser_comb_ff[4]_i_2_n_0 ),
        .I1(\m_axis_rq_tuser_comb_ff[24]_i_4_n_0 ),
        .I2(wr_user__0[4]),
        .I3(\m_axis_rq_tuser_comb_ff[4]_i_3_n_0 ),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\wpl_hdr_lbe_ff_reg[0] ));
  LUT6 #(
    .INIT(64'hFF08080808080808)) 
    \m_axis_rq_tuser_comb_ff[4]_i_2 
       (.I0(D[68]),
        .I1(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I2(wtlp_dat_vld6_in),
        .I3(\m_axis_rq_tuser_comb_ff_reg[7] [0]),
        .I4(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I5(p_0_in123_out),
        .O(\m_axis_rq_tuser_comb_ff[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_tuser_comb_ff[4]_i_3 
       (.I0(\reqdtlpSm512_cs[2]_i_2_n_0 ),
        .I1(D[68]),
        .I2(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I3(wr_user__0[4]),
        .I4(\m_axis_rq_tuser_comb_ff_reg[7] [0]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_tuser_comb_ff[4]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hEAEAFFEA)) 
    \m_axis_rq_tuser_comb_ff[5]_i_1 
       (.I0(\m_axis_rq_tuser_comb_ff[5]_i_2_n_0 ),
        .I1(\m_axis_rq_tuser_comb_ff[24]_i_4_n_0 ),
        .I2(wr_user__0[5]),
        .I3(\m_axis_rq_tuser_comb_ff[5]_i_3_n_0 ),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\wpl_hdr_lbe_ff_reg[1] ));
  LUT6 #(
    .INIT(64'hFF08080808080808)) 
    \m_axis_rq_tuser_comb_ff[5]_i_2 
       (.I0(D[69]),
        .I1(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I2(wtlp_dat_vld6_in),
        .I3(\m_axis_rq_tuser_comb_ff_reg[7] [1]),
        .I4(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I5(p_0_in123_out),
        .O(\m_axis_rq_tuser_comb_ff[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_tuser_comb_ff[5]_i_3 
       (.I0(\reqdtlpSm512_cs[2]_i_2_n_0 ),
        .I1(D[69]),
        .I2(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I3(wr_user__0[5]),
        .I4(\m_axis_rq_tuser_comb_ff_reg[7] [1]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_tuser_comb_ff[5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hEAEAFFEA)) 
    \m_axis_rq_tuser_comb_ff[6]_i_1 
       (.I0(\m_axis_rq_tuser_comb_ff[6]_i_2_n_0 ),
        .I1(\m_axis_rq_tuser_comb_ff[24]_i_4_n_0 ),
        .I2(wr_user__0[6]),
        .I3(\m_axis_rq_tuser_comb_ff[6]_i_3_n_0 ),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\wpl_hdr_lbe_ff_reg[2] ));
  LUT6 #(
    .INIT(64'hFF08080808080808)) 
    \m_axis_rq_tuser_comb_ff[6]_i_2 
       (.I0(D[70]),
        .I1(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I2(wtlp_dat_vld6_in),
        .I3(\m_axis_rq_tuser_comb_ff_reg[7] [2]),
        .I4(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I5(p_0_in123_out),
        .O(\m_axis_rq_tuser_comb_ff[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_tuser_comb_ff[6]_i_3 
       (.I0(\reqdtlpSm512_cs[2]_i_2_n_0 ),
        .I1(D[70]),
        .I2(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I3(wr_user__0[6]),
        .I4(\m_axis_rq_tuser_comb_ff_reg[7] [2]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_tuser_comb_ff[6]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hEAEAFFEA)) 
    \m_axis_rq_tuser_comb_ff[7]_i_1 
       (.I0(\m_axis_rq_tuser_comb_ff[7]_i_2_n_0 ),
        .I1(\m_axis_rq_tuser_comb_ff[24]_i_4_n_0 ),
        .I2(wr_user__0[7]),
        .I3(\m_axis_rq_tuser_comb_ff[7]_i_3_n_0 ),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\wpl_hdr_lbe_ff_reg[3] ));
  LUT6 #(
    .INIT(64'hFF08080808080808)) 
    \m_axis_rq_tuser_comb_ff[7]_i_2 
       (.I0(D[71]),
        .I1(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I2(wtlp_dat_vld6_in),
        .I3(\m_axis_rq_tuser_comb_ff_reg[7] [3]),
        .I4(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I5(p_0_in123_out),
        .O(\m_axis_rq_tuser_comb_ff[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_tuser_comb_ff[7]_i_3 
       (.I0(\reqdtlpSm512_cs[2]_i_2_n_0 ),
        .I1(D[71]),
        .I2(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I3(wr_user__0[7]),
        .I4(\m_axis_rq_tuser_comb_ff_reg[7] [3]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_tuser_comb_ff[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1552" *) 
  LUT5 #(
    .INIT(32'hEAEAFFEA)) 
    \m_axis_rq_tuser_d_ff[0][0]_i_1 
       (.I0(\m_axis_rq_tuser_d_ff[0][0]_i_2_n_0 ),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I2(wr_user__0[0]),
        .I3(\m_axis_rq_tuser_d_ff[0][0]_i_3_n_0 ),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_tuser_d_nxt[0]__0 [0]));
  LUT6 #(
    .INIT(64'hFF08080808080808)) 
    \m_axis_rq_tuser_d_ff[0][0]_i_2 
       (.I0(\m_axis_rq_tuser_comb_ff_reg[3] [0]),
        .I1(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I2(wtlp_dat_vld6_in),
        .I3(\m_axis_rq_tuser_comb_ff_reg[3]_0 [0]),
        .I4(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I5(p_0_in123_out),
        .O(\m_axis_rq_tuser_d_ff[0][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_tuser_d_ff[0][0]_i_3 
       (.I0(\reqdtlpSm512_cs[2]_i_2_n_0 ),
        .I1(\m_axis_rq_tuser_comb_ff_reg[3] [0]),
        .I2(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I3(wr_user__0[0]),
        .I4(\m_axis_rq_tuser_comb_ff_reg[3]_0 [0]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_tuser_d_ff[0][0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1553" *) 
  LUT5 #(
    .INIT(32'hEAEAFFEA)) 
    \m_axis_rq_tuser_d_ff[0][1]_i_1 
       (.I0(\m_axis_rq_tuser_d_ff[0][1]_i_2_n_0 ),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I2(wr_user__0[1]),
        .I3(\m_axis_rq_tuser_d_ff[0][1]_i_3_n_0 ),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_tuser_d_nxt[0]__0 [1]));
  LUT6 #(
    .INIT(64'hFF08080808080808)) 
    \m_axis_rq_tuser_d_ff[0][1]_i_2 
       (.I0(\m_axis_rq_tuser_comb_ff_reg[3] [1]),
        .I1(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I2(wtlp_dat_vld6_in),
        .I3(\m_axis_rq_tuser_comb_ff_reg[3]_0 [1]),
        .I4(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I5(p_0_in123_out),
        .O(\m_axis_rq_tuser_d_ff[0][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_tuser_d_ff[0][1]_i_3 
       (.I0(\reqdtlpSm512_cs[2]_i_2_n_0 ),
        .I1(\m_axis_rq_tuser_comb_ff_reg[3] [1]),
        .I2(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I3(wr_user__0[1]),
        .I4(\m_axis_rq_tuser_comb_ff_reg[3]_0 [1]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_tuser_d_ff[0][1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1554" *) 
  LUT5 #(
    .INIT(32'hEAEAFFEA)) 
    \m_axis_rq_tuser_d_ff[0][2]_i_1 
       (.I0(\m_axis_rq_tuser_d_ff[0][2]_i_2_n_0 ),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I2(wr_user__0[2]),
        .I3(\m_axis_rq_tuser_d_ff[0][2]_i_3_n_0 ),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_tuser_d_nxt[0]__0 [2]));
  LUT6 #(
    .INIT(64'hFF08080808080808)) 
    \m_axis_rq_tuser_d_ff[0][2]_i_2 
       (.I0(\m_axis_rq_tuser_comb_ff_reg[3] [2]),
        .I1(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I2(wtlp_dat_vld6_in),
        .I3(\m_axis_rq_tuser_comb_ff_reg[3]_0 [2]),
        .I4(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I5(p_0_in123_out),
        .O(\m_axis_rq_tuser_d_ff[0][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_tuser_d_ff[0][2]_i_3 
       (.I0(\reqdtlpSm512_cs[2]_i_2_n_0 ),
        .I1(\m_axis_rq_tuser_comb_ff_reg[3] [2]),
        .I2(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I3(wr_user__0[2]),
        .I4(\m_axis_rq_tuser_comb_ff_reg[3]_0 [2]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_tuser_d_ff[0][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1555" *) 
  LUT5 #(
    .INIT(32'hEAEAFFEA)) 
    \m_axis_rq_tuser_d_ff[0][3]_i_1 
       (.I0(\m_axis_rq_tuser_d_ff[0][3]_i_2_n_0 ),
        .I1(\m_axis_rq_thead_d_ff[0][32]_i_3_n_0 ),
        .I2(wr_user__0[3]),
        .I3(\m_axis_rq_tuser_d_ff[0][3]_i_3_n_0 ),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\m_axis_rq_tuser_d_nxt[0]__0 [3]));
  LUT6 #(
    .INIT(64'hFF08080808080808)) 
    \m_axis_rq_tuser_d_ff[0][3]_i_2 
       (.I0(\m_axis_rq_tuser_comb_ff_reg[3] [3]),
        .I1(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I2(wtlp_dat_vld6_in),
        .I3(\m_axis_rq_tuser_comb_ff_reg[3]_0 [3]),
        .I4(\m_axis_rq_thead_d_ff[0][32]_i_2_n_0 ),
        .I5(p_0_in123_out),
        .O(\m_axis_rq_tuser_d_ff[0][3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \m_axis_rq_tuser_d_ff[0][3]_i_3 
       (.I0(\reqdtlpSm512_cs[2]_i_2_n_0 ),
        .I1(\m_axis_rq_tuser_comb_ff_reg[3] [3]),
        .I2(\m_axis_rq_thead_d_ff_reg[0][32] ),
        .I3(wr_user__0[3]),
        .I4(\m_axis_rq_tuser_comb_ff_reg[3]_0 [3]),
        .I5(\m_axis_rq_tuser_comb_ff_reg[0] ),
        .O(\m_axis_rq_tuser_d_ff[0][3]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    m_axis_rq_tvalid_d_ff_i_1
       (.I0(m_axis_rq_tvalid_d_ff_reg_0),
        .I1(m_axis_rq_tvalid_d_ff_i_3_n_0),
        .I2(m_axis_rq_tvalid_d_ff),
        .O(m_axis_rq_tvalid_d_ff_reg));
  LUT6 #(
    .INIT(64'h000000008C000F00)) 
    m_axis_rq_tvalid_d_ff_i_3
       (.I0(beatdone),
        .I1(wtlp_dat_vld6_in),
        .I2(reqdtlpSm512_cs[0]),
        .I3(rdIssued_s01),
        .I4(reqdtlpSm512_cs[1]),
        .I5(reqdtlpSm_cs[1]),
        .O(m_axis_rq_tvalid_d_ff_i_3_n_0));
  LUT5 #(
    .INIT(32'h08000000)) 
    \rdIssued_ff[0]_i_1 
       (.I0(reqdtlpSm512_cs[0]),
        .I1(rdIssued_s01),
        .I2(reqdtlpSm512_cs[1]),
        .I3(reqdtlpSm_cs[1]),
        .I4(wtlp_dat_vld6_in),
        .O(rdIssued_0));
  LUT6 #(
    .INIT(64'hFFFFAAAAFFFEAAAA)) 
    \reqdtlpSm512_cs[0]_i_1 
       (.I0(\reqdtlpSm_cs_reg[0]_0 ),
        .I1(\reqdtlpSm512_cs[0]_i_2_n_0 ),
        .I2(\reqdtlpSm512_cs[0]_i_3_n_0 ),
        .I3(\reqdtlpSm512_cs[0]_i_4_n_0 ),
        .I4(\reqdtlpSm512_cs[0]_i_5_n_0 ),
        .I5(\reqdtlpSm512_cs[0]_i_6_n_0 ),
        .O(wpl_hdr_btlene1_ff_reg));
  LUT5 #(
    .INIT(32'h00CC2020)) 
    \reqdtlpSm512_cs[0]_i_12 
       (.I0(reqdtlpSm512_cs[1]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I4(wtlp_dat_vld6_in),
        .O(\reqdtlpSm512_cs[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h00000000000000FE)) 
    \reqdtlpSm512_cs[0]_i_2 
       (.I0(\reqdtlpSm_cs[0]_i_2_n_0 ),
        .I1(\reqdtlpSm_cs[0]_i_3_n_0 ),
        .I2(\reqdtlpSm512_cs[0]_i_7_n_0 ),
        .I3(\reqdtlpSm512_cs[0]_i_8_n_0 ),
        .I4(\reqdtlpSm512_cs[0]_i_9_n_0 ),
        .I5(wpl_hdr_btlene1_ff),
        .O(\reqdtlpSm512_cs[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000AAA8)) 
    \reqdtlpSm512_cs[0]_i_3 
       (.I0(rdIssued_s10),
        .I1(\reqdtlpSm_cs[0]_i_2_n_0 ),
        .I2(\reqdtlpSm_cs[0]_i_3_n_0 ),
        .I3(\reqdtlpSm512_cs[0]_i_7_n_0 ),
        .I4(\reqdtlpSm512_cs[0]_i_8_n_0 ),
        .I5(\reqdtlpSm512_cs[0]_i_9_n_0 ),
        .O(\reqdtlpSm512_cs[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEE000000000)) 
    \reqdtlpSm512_cs[0]_i_4 
       (.I0(\reqdtlpSm512_cs[0]_i_8_n_0 ),
        .I1(\reqdtlpSm512_cs[0]_i_9_n_0 ),
        .I2(\reqdtlpSm_cs[0]_i_2_n_0 ),
        .I3(\reqdtlpSm_cs[0]_i_3_n_0 ),
        .I4(\reqdtlpSm512_cs[0]_i_7_n_0 ),
        .I5(p_0_in116_out),
        .O(\reqdtlpSm512_cs[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFEFEFEFEFEFEFEFF)) 
    \reqdtlpSm512_cs[0]_i_5 
       (.I0(\m_axis_rq_thead_d_ff[0][39]_i_2_n_0 ),
        .I1(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I2(\reqdtlpSm512_cs[0]_i_8_n_0 ),
        .I3(\reqdtlpSm512_cs[2]_i_4_n_0 ),
        .I4(\reqdtlpSm_cs[0]_i_4_n_0 ),
        .I5(\reqdtlpSm512_cs[0]_i_12_n_0 ),
        .O(\reqdtlpSm512_cs[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEE000000000)) 
    \reqdtlpSm512_cs[0]_i_6 
       (.I0(\reqdtlpSm512_cs[0]_i_8_n_0 ),
        .I1(\reqdtlpSm512_cs[0]_i_9_n_0 ),
        .I2(\reqdtlpSm_cs[0]_i_2_n_0 ),
        .I3(\reqdtlpSm_cs[0]_i_3_n_0 ),
        .I4(\reqdtlpSm512_cs[0]_i_7_n_0 ),
        .I5(wrreq),
        .O(\reqdtlpSm512_cs[0]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'hEAEE)) 
    \reqdtlpSm512_cs[0]_i_7 
       (.I0(\reqdtlpSm_cs[0]_i_4_n_0 ),
        .I1(\reqdtlpSm_cs[0]_i_5_n_0 ),
        .I2(p_0_in123_out),
        .I3(beatdone),
        .O(\reqdtlpSm512_cs[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF000031000000)) 
    \reqdtlpSm512_cs[0]_i_8 
       (.I0(wrreq),
        .I1(wtlp_dat_vld6_in),
        .I2(\rdIssued_ff_reg[0] ),
        .I3(\reqdtlpSm_cs_reg[0]_1 ),
        .I4(reqdtlpSm_cs[1]),
        .I5(\reqdtlpSm_cs[1]_i_2_n_0 ),
        .O(\reqdtlpSm512_cs[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAEAAAEAAAEEEE)) 
    \reqdtlpSm512_cs[0]_i_9 
       (.I0(\m_axis_rq_thead_d_ff[0][39]_i_2_n_0 ),
        .I1(p_0_in123_out),
        .I2(beatdone),
        .I3(\reqdtlpSm_cs[0]_i_5_n_0 ),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I5(\rdIssued_ff_reg[0] ),
        .O(\reqdtlpSm512_cs[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFECCC2000)) 
    \reqdtlpSm512_cs[2]_i_1 
       (.I0(reqdtlpSm512_cs[1]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(\reqdtlpSm512_cs[2]_i_2_n_0 ),
        .I4(\reqdtlpSm512_cs[2]_i_3_n_0 ),
        .I5(\reqdtlpSm512_cs[2]_i_4_n_0 ),
        .O(\reqdtlpSm512_cs_reg[2] ));
  LUT5 #(
    .INIT(32'h0000EEEF)) 
    \reqdtlpSm512_cs[2]_i_2 
       (.I0(reqdtlpSm_cs[1]),
        .I1(reqdtlpSm512_cs[0]),
        .I2(wrreq),
        .I3(p_0_in123_out),
        .I4(wtlp_dat_vld6_in),
        .O(\reqdtlpSm512_cs[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1556" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \reqdtlpSm512_cs[2]_i_3 
       (.I0(wtlp_dat_vld6_in),
        .I1(reqdtlpSm512_cs[1]),
        .I2(rdIssued_s01),
        .O(\reqdtlpSm512_cs[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h04440044CCCCCCCC)) 
    \reqdtlpSm512_cs[2]_i_4 
       (.I0(reqdtlpSm_cs[1]),
        .I1(reqdtlpSm512_cs[1]),
        .I2(beatdone),
        .I3(wtlp_dat_vld6_in),
        .I4(\reqdtlpSm_cs_reg[0]_1 ),
        .I5(rdIssued_s01),
        .O(\reqdtlpSm512_cs[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFEFEFFFEFFFE)) 
    \reqdtlpSm_cs[0]_i_1 
       (.I0(\reqdtlpSm_cs[0]_i_2_n_0 ),
        .I1(\reqdtlpSm_cs[0]_i_3_n_0 ),
        .I2(\reqdtlpSm_cs[0]_i_4_n_0 ),
        .I3(\reqdtlpSm_cs[0]_i_5_n_0 ),
        .I4(p_0_in123_out),
        .I5(beatdone),
        .O(\reqdtlpSm_cs_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h40FF40FF40FF4040)) 
    \reqdtlpSm_cs[0]_i_2 
       (.I0(wtlp_dat_vld6_in),
        .I1(\reqdtlpSm_cs_reg[0]_1 ),
        .I2(reqdtlpSm_cs[0]),
        .I3(\reqdtlpSm_cs[0]_i_9_n_0 ),
        .I4(wrreq),
        .I5(p_0_in123_out),
        .O(\reqdtlpSm_cs[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2E222A2222222A22)) 
    \reqdtlpSm_cs[0]_i_3 
       (.I0(reqdtlpSm_cs[0]),
        .I1(rdIssued_s01),
        .I2(reqdtlpSm_cs[1]),
        .I3(reqdtlpSm512_cs[1]),
        .I4(wtlp_dat_vld6_in),
        .I5(wrreq),
        .O(\reqdtlpSm_cs[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1557" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    \reqdtlpSm_cs[0]_i_4 
       (.I0(reqdtlpSm512_cs[0]),
        .I1(rdIssued_s01),
        .I2(reqdtlpSm512_cs[1]),
        .I3(reqdtlpSm_cs[1]),
        .I4(wtlp_dat_vld6_in),
        .O(\reqdtlpSm_cs[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1551" *) 
  LUT5 #(
    .INIT(32'h08000000)) 
    \reqdtlpSm_cs[0]_i_5 
       (.I0(wtlp_dat_vld6_in),
        .I1(reqdtlpSm512_cs[0]),
        .I2(reqdtlpSm_cs[1]),
        .I3(reqdtlpSm512_cs[1]),
        .I4(rdIssued_s01),
        .O(\reqdtlpSm_cs[0]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'hFFEF)) 
    \reqdtlpSm_cs[0]_i_9 
       (.I0(reqdtlpSm_cs[1]),
        .I1(reqdtlpSm512_cs[1]),
        .I2(rdIssued_s01),
        .I3(reqdtlpSm512_cs[0]),
        .O(\reqdtlpSm_cs[0]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFF8)) 
    \reqdtlpSm_cs[1]_i_1 
       (.I0(\reqdtlpSm_cs[1]_i_2_n_0 ),
        .I1(reqdtlpSm_cs[1]),
        .I2(\reqdtlpSm_cs[1]_i_3_n_0 ),
        .I3(\m_axis_rq_thead_d_ff[0][63]_i_4_n_0 ),
        .I4(\m_axis_rq_thead_d_ff[0][39]_i_2_n_0 ),
        .O(\reqdtlpSm_cs_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h004F0000FFFFFFFF)) 
    \reqdtlpSm_cs[1]_i_2 
       (.I0(force_ready_flush_ff),
        .I1(full_ff_reg_n_0),
        .I2(m_axis_rq_tvalid_d_ff),
        .I3(reqdtlpSm_cs[1]),
        .I4(reqdtlpSm512_cs[1]),
        .I5(rdIssued_s01),
        .O(\reqdtlpSm_cs[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000022A0000022A2)) 
    \reqdtlpSm_cs[1]_i_3 
       (.I0(reqdtlpSm_cs[1]),
        .I1(reqdtlpSm512_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(reqdtlpSm_cs[1]),
        .I4(wtlp_dat_vld6_in),
        .I5(wrreq),
        .O(\reqdtlpSm_cs[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1607" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][10]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [8]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [25]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [8]));
  (* SOFT_HLUTNM = "soft_lutpair1607" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][11]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [9]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [26]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [9]));
  (* SOFT_HLUTNM = "soft_lutpair1606" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][12]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [10]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [27]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [10]));
  (* SOFT_HLUTNM = "soft_lutpair1606" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][13]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [11]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [28]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [11]));
  (* SOFT_HLUTNM = "soft_lutpair1605" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][14]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [12]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [29]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [12]));
  (* SOFT_HLUTNM = "soft_lutpair1605" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][15]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [13]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [30]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [13]));
  (* SOFT_HLUTNM = "soft_lutpair1604" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][16]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [14]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [31]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [14]));
  (* SOFT_HLUTNM = "soft_lutpair1604" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][17]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [15]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [32]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [15]));
  (* SOFT_HLUTNM = "soft_lutpair1603" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][18]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [16]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [33]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [16]));
  (* SOFT_HLUTNM = "soft_lutpair1603" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][19]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [17]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [34]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [17]));
  (* SOFT_HLUTNM = "soft_lutpair1602" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][20]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [18]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [35]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [18]));
  (* SOFT_HLUTNM = "soft_lutpair1602" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][21]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [19]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [36]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [19]));
  (* SOFT_HLUTNM = "soft_lutpair1601" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][22]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [20]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [37]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [20]));
  (* SOFT_HLUTNM = "soft_lutpair1601" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][23]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [21]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [38]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [21]));
  (* SOFT_HLUTNM = "soft_lutpair1600" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][24]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [22]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [39]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [22]));
  (* SOFT_HLUTNM = "soft_lutpair1600" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][25]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [23]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [40]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [23]));
  (* SOFT_HLUTNM = "soft_lutpair1599" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][26]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [24]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [41]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [24]));
  (* SOFT_HLUTNM = "soft_lutpair1599" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][27]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [25]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [42]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [25]));
  (* SOFT_HLUTNM = "soft_lutpair1598" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][28]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [26]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [43]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [26]));
  (* SOFT_HLUTNM = "soft_lutpair1598" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][29]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [27]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [44]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [27]));
  (* SOFT_HLUTNM = "soft_lutpair1611" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][2]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [0]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [17]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1597" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][30]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [28]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [45]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [28]));
  (* SOFT_HLUTNM = "soft_lutpair1597" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][31]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [29]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [46]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [29]));
  (* SOFT_HLUTNM = "soft_lutpair1596" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][32]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [30]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [47]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [30]));
  (* SOFT_HLUTNM = "soft_lutpair1596" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][33]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [31]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [48]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [31]));
  (* SOFT_HLUTNM = "soft_lutpair1595" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][34]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [32]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [49]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [32]));
  (* SOFT_HLUTNM = "soft_lutpair1595" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][35]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [33]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [50]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [33]));
  (* SOFT_HLUTNM = "soft_lutpair1594" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][36]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [34]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [51]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [34]));
  (* SOFT_HLUTNM = "soft_lutpair1594" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][37]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [35]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [52]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [35]));
  (* SOFT_HLUTNM = "soft_lutpair1593" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][38]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [36]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [53]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [36]));
  (* SOFT_HLUTNM = "soft_lutpair1593" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][39]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [37]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [54]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [37]));
  (* SOFT_HLUTNM = "soft_lutpair1611" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][3]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [1]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [18]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1592" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][40]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [38]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [55]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [38]));
  (* SOFT_HLUTNM = "soft_lutpair1592" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][41]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [39]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [56]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [39]));
  (* SOFT_HLUTNM = "soft_lutpair1591" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][42]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [40]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [57]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [40]));
  (* SOFT_HLUTNM = "soft_lutpair1591" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][43]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [41]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [58]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [41]));
  (* SOFT_HLUTNM = "soft_lutpair1590" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][44]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [42]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [59]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [42]));
  (* SOFT_HLUTNM = "soft_lutpair1590" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][45]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [43]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [60]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [43]));
  (* SOFT_HLUTNM = "soft_lutpair1589" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][46]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [44]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [61]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [44]));
  (* SOFT_HLUTNM = "soft_lutpair1589" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][47]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [45]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [62]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [45]));
  (* SOFT_HLUTNM = "soft_lutpair1588" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][48]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [46]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [63]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [46]));
  (* SOFT_HLUTNM = "soft_lutpair1588" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][49]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [47]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [64]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [47]));
  (* SOFT_HLUTNM = "soft_lutpair1610" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][4]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [2]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [19]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [2]));
  (* SOFT_HLUTNM = "soft_lutpair1587" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][50]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [48]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [65]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [48]));
  (* SOFT_HLUTNM = "soft_lutpair1587" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][51]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [49]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [66]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [49]));
  (* SOFT_HLUTNM = "soft_lutpair1586" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][52]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [50]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [67]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [50]));
  (* SOFT_HLUTNM = "soft_lutpair1586" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][53]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [51]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [68]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [51]));
  (* SOFT_HLUTNM = "soft_lutpair1585" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][54]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [52]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [69]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [52]));
  (* SOFT_HLUTNM = "soft_lutpair1585" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][55]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [53]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [70]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [53]));
  (* SOFT_HLUTNM = "soft_lutpair1584" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][56]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [54]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [71]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [54]));
  (* SOFT_HLUTNM = "soft_lutpair1584" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][57]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [55]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [72]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [55]));
  (* SOFT_HLUTNM = "soft_lutpair1583" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][58]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [56]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [73]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [56]));
  (* SOFT_HLUTNM = "soft_lutpair1583" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][59]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [57]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [74]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [57]));
  (* SOFT_HLUTNM = "soft_lutpair1610" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][5]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [3]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [20]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [3]));
  (* SOFT_HLUTNM = "soft_lutpair1582" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][60]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [58]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [75]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [58]));
  (* SOFT_HLUTNM = "soft_lutpair1582" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][61]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [59]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [76]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [59]));
  (* SOFT_HLUTNM = "soft_lutpair1581" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][62]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [60]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [77]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [60]));
  (* SOFT_HLUTNM = "soft_lutpair1581" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][63]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [61]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [78]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [61]));
  (* SOFT_HLUTNM = "soft_lutpair1609" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][6]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [4]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [21]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [4]));
  (* SOFT_HLUTNM = "soft_lutpair1609" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][7]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [5]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [22]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [5]));
  (* SOFT_HLUTNM = "soft_lutpair1608" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][8]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [6]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [23]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [6]));
  (* SOFT_HLUTNM = "soft_lutpair1608" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][adr][9]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][adr][63]_0 [7]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [24]),
        .O(\rreq_head_info_ff_reg[1][adr][63] [7]));
  (* SOFT_HLUTNM = "soft_lutpair1572" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][chn][0]_i_1 
       (.I0(\rreq_head_info_ff_reg[1][chn] ),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [79]),
        .O(\rreq_head_info_nxt[0][chn] ));
  (* SOFT_HLUTNM = "soft_lutpair1580" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][did][0]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][did][8] [0]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [0]),
        .O(\rreq_head_info_ff_reg[1][did][8] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1580" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][did][1]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][did][8] [1]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [1]),
        .O(\rreq_head_info_ff_reg[1][did][8] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1579" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][did][2]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][did][8] [2]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [2]),
        .O(\rreq_head_info_ff_reg[1][did][8] [2]));
  (* SOFT_HLUTNM = "soft_lutpair1579" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][did][3]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][did][8] [3]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [3]),
        .O(\rreq_head_info_ff_reg[1][did][8] [3]));
  (* SOFT_HLUTNM = "soft_lutpair1578" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][did][4]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][did][8] [4]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [4]),
        .O(\rreq_head_info_ff_reg[1][did][8] [4]));
  (* SOFT_HLUTNM = "soft_lutpair1578" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][did][5]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][did][8] [5]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [5]),
        .O(\rreq_head_info_ff_reg[1][did][8] [5]));
  (* SOFT_HLUTNM = "soft_lutpair1577" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][did][6]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][did][8] [6]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [6]),
        .O(\rreq_head_info_ff_reg[1][did][8] [6]));
  (* SOFT_HLUTNM = "soft_lutpair1577" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][did][7]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][did][8] [7]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [7]),
        .O(\rreq_head_info_ff_reg[1][did][8] [7]));
  (* SOFT_HLUTNM = "soft_lutpair1576" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][did][8]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][did][8] [8]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [8]),
        .O(\rreq_head_info_ff_reg[1][did][8] [8]));
  (* SOFT_HLUTNM = "soft_lutpair1563" *) 
  LUT4 #(
    .INIT(16'h888B)) 
    \rreq_head_info_ff[0][fbe][0]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][fbe][3] [0]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [15]),
        .I3(\rreq_head_info_ff_reg[0][chn][0] [16]),
        .O(\rreq_head_info_ff_reg[1][fbe][3] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1570" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][fbe][3]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][fbe][3] [1]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][fbe][3]_0 ),
        .O(\rreq_head_info_ff_reg[1][fbe][3] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1572" *) 
  LUT3 #(
    .INIT(8'h8B)) 
    \rreq_head_info_ff[0][lbe][0]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][lbe][2] [0]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][lbe][0] ),
        .O(\rreq_head_info_ff_reg[1][lbe][2] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1569" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][lbe][1]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][lbe][2] [1]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][lbe][2]_0 [0]),
        .O(\rreq_head_info_ff_reg[1][lbe][2] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1570" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][lbe][2]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][lbe][2] [2]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][lbe][2]_0 [1]),
        .O(\rreq_head_info_ff_reg[1][lbe][2] [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][len][10]_i_2 
       (.I0(\rreq_head_info_ff_reg[0][len][10] [10]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(A[10]),
        .O(\rreq_head_info_ff[0][len][10]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][len][10]_i_3 
       (.I0(\rreq_head_info_ff_reg[0][len][10] [9]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(A[9]),
        .O(\rreq_head_info_ff[0][len][10]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][len][10]_i_4 
       (.I0(\rreq_head_info_ff_reg[0][len][10] [8]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(A[8]),
        .O(\rreq_head_info_ff[0][len][10]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][len][3]_i_3 
       (.I0(\rreq_head_info_ff_reg[0][len][10] [3]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(A[3]),
        .O(\rreq_head_info_ff[0][len][3]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][len][3]_i_4 
       (.I0(\rreq_head_info_ff_reg[0][len][10] [2]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(A[2]),
        .O(\rreq_head_info_ff[0][len][3]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][len][3]_i_5 
       (.I0(\rreq_head_info_ff_reg[0][len][10] [1]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(A[1]),
        .O(\rreq_head_info_ff[0][len][3]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][len][3]_i_6 
       (.I0(\rreq_head_info_ff_reg[0][len][10] [0]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(A[0]),
        .O(\rreq_head_info_ff[0][len][3]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][len][7]_i_2 
       (.I0(\rreq_head_info_ff_reg[0][len][10] [7]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(A[7]),
        .O(\rreq_head_info_ff[0][len][7]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][len][7]_i_3 
       (.I0(\rreq_head_info_ff_reg[0][len][10] [6]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(A[6]),
        .O(\rreq_head_info_ff[0][len][7]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][len][7]_i_4 
       (.I0(\rreq_head_info_ff_reg[0][len][10] [5]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(A[5]),
        .O(\rreq_head_info_ff[0][len][7]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][len][7]_i_5 
       (.I0(\rreq_head_info_ff_reg[0][len][10] [4]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(A[4]),
        .O(\rreq_head_info_ff[0][len][7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFB8F0B800B8F0B8)) 
    \rreq_head_info_ff[0][rcb][0]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [0]),
        .I1(\canissueRd_ff_reg[0]_0 [0]),
        .I2(\rreq_head_info_ff_reg[0][rcb][0] ),
        .I3(rdIssued_0),
        .I4(\canissueRd_ff_reg[0]_0 [1]),
        .I5(\rreq_head_info_ff_reg[1][rcb] [0]),
        .O(\rreq_head_info_nxt[0][rcb] [0]));
  LUT6 #(
    .INIT(64'hFFB8F0B800B8F0B8)) 
    \rreq_head_info_ff[0][rcb][1]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [1]),
        .I1(\canissueRd_ff_reg[0]_0 [0]),
        .I2(\rreq_head_info_ff_reg[0][rcb][1] ),
        .I3(rdIssued_0),
        .I4(\canissueRd_ff_reg[0]_0 [1]),
        .I5(\rreq_head_info_ff_reg[1][rcb] [1]),
        .O(\rreq_head_info_nxt[0][rcb] [1]));
  LUT6 #(
    .INIT(64'hFFB8F0B800B8F0B8)) 
    \rreq_head_info_ff[0][rcb][2]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [2]),
        .I1(\canissueRd_ff_reg[0]_0 [0]),
        .I2(\rreq_head_info_ff_reg[0][rcb][2] ),
        .I3(rdIssued_0),
        .I4(\canissueRd_ff_reg[0]_0 [1]),
        .I5(\rreq_head_info_ff_reg[1][rcb] [2]),
        .O(\rreq_head_info_nxt[0][rcb] [2]));
  LUT6 #(
    .INIT(64'hFFB8F0B800B8F0B8)) 
    \rreq_head_info_ff[0][rcb][3]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [3]),
        .I1(\canissueRd_ff_reg[0]_0 [0]),
        .I2(\rreq_head_info_ff_reg[0][rcb][3] ),
        .I3(rdIssued_0),
        .I4(\canissueRd_ff_reg[0]_0 [1]),
        .I5(\rreq_head_info_ff_reg[1][rcb] [3]),
        .O(\rreq_head_info_nxt[0][rcb] [3]));
  LUT6 #(
    .INIT(64'hFFB8F0B800B8F0B8)) 
    \rreq_head_info_ff[0][rcb][4]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [4]),
        .I1(\canissueRd_ff_reg[0]_0 [0]),
        .I2(\rreq_head_info_ff_reg[0][rcb][4] ),
        .I3(rdIssued_0),
        .I4(\canissueRd_ff_reg[0]_0 [1]),
        .I5(\rreq_head_info_ff_reg[1][rcb] [4]),
        .O(\rreq_head_info_nxt[0][rcb] [4]));
  LUT6 #(
    .INIT(64'hFFFFE22E0000E22E)) 
    \rreq_head_info_ff[0][rcb][5]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [5]),
        .I1(\rreq_head_vld_ff[0]_i_3_n_0 ),
        .I2(O),
        .I3(\rreq_head_info_ff_reg[0][rcb][7]_0 ),
        .I4(\reqdtlpSm_cs_reg[1] ),
        .I5(\rreq_head_info_ff_reg[1][rcb] [5]),
        .O(\rreq_head_info_nxt[0][rcb] [5]));
  LUT6 #(
    .INIT(64'hFFFFFFFFEBEEAAAA)) 
    \rreq_head_info_ff[0][rcb][6]_i_1 
       (.I0(\rreq_head_info_ff[0][rcb][6]_i_2_n_0 ),
        .I1(\rreq_head_info_ff_reg[0][rcb][7]_1 ),
        .I2(\rreq_head_info_ff_reg[0][rcb][7]_0 ),
        .I3(O),
        .I4(\rreq_head_info_ff[0][rcb][7]_i_6_n_0 ),
        .I5(\rreq_head_info_ff[0][rcb][6]_i_3_n_0 ),
        .O(\rreq_head_info_nxt[0][rcb] [6]));
  (* SOFT_HLUTNM = "soft_lutpair1567" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \rreq_head_info_ff[0][rcb][6]_i_2 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [6]),
        .I1(rdIssued_0),
        .I2(\canissueRd_ff_reg[0]_0 [0]),
        .O(\rreq_head_info_ff[0][rcb][6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1563" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rreq_head_info_ff[0][rcb][6]_i_3 
       (.I0(\rreq_head_info_ff_reg[1][rcb] [6]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .O(\rreq_head_info_ff[0][rcb][6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFBAAAAAAA)) 
    \rreq_head_info_ff[0][rcb][7]_i_1 
       (.I0(\rreq_head_info_ff[0][rcb][7]_i_2_n_0 ),
        .I1(\rreq_head_info_ff_reg[0][rcb][7]_0 ),
        .I2(O),
        .I3(\rreq_head_info_ff_reg[0][rcb][7]_1 ),
        .I4(\rreq_head_info_ff[0][rcb][7]_i_6_n_0 ),
        .I5(\rreq_head_info_ff[0][rcb][7]_i_7_n_0 ),
        .O(\rreq_head_info_nxt[0][rcb] [7]));
  (* SOFT_HLUTNM = "soft_lutpair1568" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \rreq_head_info_ff[0][rcb][7]_i_2 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [7]),
        .I1(rdIssued_0),
        .I2(\canissueRd_ff_reg[0]_0 [0]),
        .O(\rreq_head_info_ff[0][rcb][7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1566" *) 
  LUT3 #(
    .INIT(8'h35)) 
    \rreq_head_info_ff[0][rcb][7]_i_6 
       (.I0(\canissueRd_ff_reg[0]_0 [0]),
        .I1(\canissueRd_ff_reg[0]_0 [1]),
        .I2(rdIssued_0),
        .O(\rreq_head_info_ff[0][rcb][7]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1569" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rreq_head_info_ff[0][rcb][7]_i_7 
       (.I0(\rreq_head_info_ff_reg[1][rcb] [7]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .O(\rreq_head_info_ff[0][rcb][7]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1576" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][rid][0]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rid][5] [0]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [9]),
        .O(\rreq_head_info_ff_reg[1][rid][5] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1575" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][rid][1]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rid][5] [1]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [10]),
        .O(\rreq_head_info_ff_reg[1][rid][5] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1575" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][rid][2]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rid][5] [2]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [11]),
        .O(\rreq_head_info_ff_reg[1][rid][5] [2]));
  (* SOFT_HLUTNM = "soft_lutpair1574" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][rid][3]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rid][5] [3]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [12]),
        .O(\rreq_head_info_ff_reg[1][rid][5] [3]));
  (* SOFT_HLUTNM = "soft_lutpair1574" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][rid][4]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rid][5] [4]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [13]),
        .O(\rreq_head_info_ff_reg[1][rid][5] [4]));
  (* SOFT_HLUTNM = "soft_lutpair1573" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][rid][5]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][rid][5] [5]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\rreq_head_info_ff_reg[0][chn][0] [14]),
        .O(\rreq_head_info_ff_reg[1][rid][5] [5]));
  (* SOFT_HLUTNM = "soft_lutpair1573" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[0][tag][0]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][tag][5] [0]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(tag_sel_ff),
        .O(\rreq_head_info_ff_reg[1][tag][5] [0]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rreq_head_info_ff[0][tag][1]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][tag][5] [1]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\tag_dout[1]_1 [0]),
        .I3(tag_sel_ff),
        .I4(\tag_dout[0]_0 [0]),
        .O(\rreq_head_info_ff_reg[1][tag][5] [1]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rreq_head_info_ff[0][tag][2]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][tag][5] [2]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\tag_dout[1]_1 [1]),
        .I3(tag_sel_ff),
        .I4(\tag_dout[0]_0 [1]),
        .O(\rreq_head_info_ff_reg[1][tag][5] [2]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rreq_head_info_ff[0][tag][3]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][tag][5] [3]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\tag_dout[1]_1 [2]),
        .I3(tag_sel_ff),
        .I4(\tag_dout[0]_0 [2]),
        .O(\rreq_head_info_ff_reg[1][tag][5] [3]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rreq_head_info_ff[0][tag][4]_i_1 
       (.I0(\rreq_head_info_ff_reg[0][tag][5] [4]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\tag_dout[1]_1 [3]),
        .I3(tag_sel_ff),
        .I4(\tag_dout[0]_0 [3]),
        .O(\rreq_head_info_ff_reg[1][tag][5] [4]));
  (* SOFT_HLUTNM = "soft_lutpair1568" *) 
  LUT2 #(
    .INIT(4'hD)) 
    \rreq_head_info_ff[0][tag][5]_i_1 
       (.I0(\canissueRd_ff_reg[0]_0 [0]),
        .I1(rdIssued_0),
        .O(\rreq_head_vld_ff_reg[0]_1 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rreq_head_info_ff[0][tag][5]_i_2 
       (.I0(\rreq_head_info_ff_reg[0][tag][5] [5]),
        .I1(\reqdtlpSm_cs_reg[1] ),
        .I2(\tag_dout[1]_1 [4]),
        .I3(tag_sel_ff),
        .I4(\tag_dout[0]_0 [4]),
        .O(\rreq_head_info_ff_reg[1][tag][5] [5]));
  (* SOFT_HLUTNM = "soft_lutpair1566" *) 
  LUT3 #(
    .INIT(8'hC2)) 
    \rreq_head_info_ff[1][rcb][7]_i_1 
       (.I0(\canissueRd_ff_reg[0]_0 [0]),
        .I1(\canissueRd_ff_reg[0]_0 [1]),
        .I2(rdIssued_0),
        .O(rreq_head_ld_new_1));
  CARRY4 \rreq_head_info_ff_reg[0][len][10]_i_1 
       (.CI(\rreq_head_info_ff_reg[0][len][7]_i_1_n_0 ),
        .CO({\NLW_rreq_head_info_ff_reg[0][len][10]_i_1_CO_UNCONNECTED [3:2],\rreq_head_info_ff_reg[0][len][10]_i_1_n_2 ,\rreq_head_info_ff_reg[0][len][10]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_rreq_head_info_ff_reg[0][len][10]_i_1_O_UNCONNECTED [3],out[10:8]}),
        .S({1'b0,\rreq_head_info_ff[0][len][10]_i_2_n_0 ,\rreq_head_info_ff[0][len][10]_i_3_n_0 ,\rreq_head_info_ff[0][len][10]_i_4_n_0 }));
  CARRY4 \rreq_head_info_ff_reg[0][len][3]_i_1 
       (.CI(1'b0),
        .CO({\rreq_head_info_ff_reg[0][len][3]_i_1_n_0 ,\rreq_head_info_ff_reg[0][len][3]_i_1_n_1 ,\rreq_head_info_ff_reg[0][len][3]_i_1_n_2 ,\rreq_head_info_ff_reg[0][len][3]_i_1_n_3 }),
        .CYINIT(\rreq_head_info_ff_reg[0][len][3] ),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(out[3:0]),
        .S({\rreq_head_info_ff[0][len][3]_i_3_n_0 ,\rreq_head_info_ff[0][len][3]_i_4_n_0 ,\rreq_head_info_ff[0][len][3]_i_5_n_0 ,\rreq_head_info_ff[0][len][3]_i_6_n_0 }));
  CARRY4 \rreq_head_info_ff_reg[0][len][7]_i_1 
       (.CI(\rreq_head_info_ff_reg[0][len][3]_i_1_n_0 ),
        .CO({\rreq_head_info_ff_reg[0][len][7]_i_1_n_0 ,\rreq_head_info_ff_reg[0][len][7]_i_1_n_1 ,\rreq_head_info_ff_reg[0][len][7]_i_1_n_2 ,\rreq_head_info_ff_reg[0][len][7]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(out[7:4]),
        .S({\rreq_head_info_ff[0][len][7]_i_2_n_0 ,\rreq_head_info_ff[0][len][7]_i_3_n_0 ,\rreq_head_info_ff[0][len][7]_i_4_n_0 ,\rreq_head_info_ff[0][len][7]_i_5_n_0 }));
  LUT6 #(
    .INIT(64'h4141414188224411)) 
    \rreq_head_rcb_ok_ff[0]_i_10 
       (.I0(\rreq_head_info_nxt[0][rcb] [4]),
        .I1(\rreq_head_info_nxt[0][rcb] [5]),
        .I2(\rreq_head_rcb_ok_ff_reg[1] [0]),
        .I3(RcbAvail_nxt0[5]),
        .I4(RcbAvail_nxt0[4]),
        .I5(RcbAvail_upd_ff),
        .O(\rreq_head_rcb_ok_ff[0]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'h00845521)) 
    \rreq_head_rcb_ok_ff[0]_i_11 
       (.I0(\rreq_head_info_nxt[0][rcb] [3]),
        .I1(RcbAvail_nxt0[2]),
        .I2(RcbAvail_nxt0[3]),
        .I3(RcbAvail_upd_ff),
        .I4(\rreq_head_info_nxt[0][rcb] [2]),
        .O(\rreq_head_rcb_ok_ff[0]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'h00845521)) 
    \rreq_head_rcb_ok_ff[0]_i_12 
       (.I0(\rreq_head_info_nxt[0][rcb] [1]),
        .I1(RcbAvail_nxt0[0]),
        .I2(RcbAvail_nxt0[1]),
        .I3(RcbAvail_upd_ff),
        .I4(\rreq_head_info_nxt[0][rcb] [0]),
        .O(\rreq_head_rcb_ok_ff[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h7171713030307130)) 
    \rreq_head_rcb_ok_ff[0]_i_5 
       (.I0(\rreq_head_info_nxt[0][rcb] [6]),
        .I1(\rreq_head_info_nxt[0][rcb] [7]),
        .I2(RcbAvail_nxt),
        .I3(RcbAvail_nxt0[6]),
        .I4(RcbAvail_upd_ff),
        .I5(\rreq_head_rcb_ok_ff_reg[1] [1]),
        .O(\rreq_head_rcb_ok_ff[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0F004F4F0F000404)) 
    \rreq_head_rcb_ok_ff[0]_i_6 
       (.I0(\rreq_head_info_nxt[0][rcb] [4]),
        .I1(RcbAvail_nxt0[4]),
        .I2(\rreq_head_info_nxt[0][rcb] [5]),
        .I3(\rreq_head_rcb_ok_ff_reg[1] [0]),
        .I4(RcbAvail_upd_ff),
        .I5(RcbAvail_nxt0[5]),
        .O(\rreq_head_rcb_ok_ff[0]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h07010500)) 
    \rreq_head_rcb_ok_ff[0]_i_7 
       (.I0(\rreq_head_info_nxt[0][rcb] [3]),
        .I1(\rreq_head_info_nxt[0][rcb] [2]),
        .I2(RcbAvail_upd_ff),
        .I3(RcbAvail_nxt0[3]),
        .I4(RcbAvail_nxt0[2]),
        .O(\rreq_head_rcb_ok_ff[0]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h07010500)) 
    \rreq_head_rcb_ok_ff[0]_i_8 
       (.I0(\rreq_head_info_nxt[0][rcb] [1]),
        .I1(\rreq_head_info_nxt[0][rcb] [0]),
        .I2(RcbAvail_upd_ff),
        .I3(RcbAvail_nxt0[1]),
        .I4(RcbAvail_nxt0[0]),
        .O(\rreq_head_rcb_ok_ff[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h8282824141418241)) 
    \rreq_head_rcb_ok_ff[0]_i_9 
       (.I0(\rreq_head_info_nxt[0][rcb] [6]),
        .I1(\rreq_head_info_nxt[0][rcb] [7]),
        .I2(RcbAvail_nxt),
        .I3(RcbAvail_nxt0[6]),
        .I4(RcbAvail_upd_ff),
        .I5(\rreq_head_rcb_ok_ff_reg[1] [1]),
        .O(\rreq_head_rcb_ok_ff[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h09090000A050A959)) 
    \rreq_head_rcb_ok_ff[1]_i_10 
       (.I0(rreq_head_info_both_rcb_nxt[5]),
        .I1(RcbAvail_nxt0[5]),
        .I2(RcbAvail_upd_ff),
        .I3(\rreq_head_rcb_ok_ff_reg[1] [0]),
        .I4(RcbAvail_nxt0[4]),
        .I5(rreq_head_info_both_rcb_nxt[4]),
        .O(\rreq_head_rcb_ok_ff[1]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'h18141211)) 
    \rreq_head_rcb_ok_ff[1]_i_11 
       (.I0(rreq_head_info_both_rcb_nxt[3]),
        .I1(rreq_head_info_both_rcb_nxt[2]),
        .I2(RcbAvail_upd_ff),
        .I3(RcbAvail_nxt0[3]),
        .I4(RcbAvail_nxt0[2]),
        .O(\rreq_head_rcb_ok_ff[1]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'h18141211)) 
    \rreq_head_rcb_ok_ff[1]_i_12 
       (.I0(rreq_head_info_both_rcb_nxt[1]),
        .I1(rreq_head_info_both_rcb_nxt[0]),
        .I2(RcbAvail_upd_ff),
        .I3(RcbAvail_nxt0[1]),
        .I4(RcbAvail_nxt0[0]),
        .O(\rreq_head_rcb_ok_ff[1]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h36353333C6CACCCC)) 
    \rreq_head_rcb_ok_ff[1]_i_16 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [7]),
        .I1(\rreq_head_info_ff_reg[1][rcb] [7]),
        .I2(rdIssued_0),
        .I3(\canissueRd_ff_reg[0]_0 [1]),
        .I4(\canissueRd_ff_reg[0]_0 [0]),
        .I5(\rreq_head_rcb_ok_ff_reg[1]_i_14_2 ),
        .O(\rreq_head_rcb_ok_ff[1]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h36353333C6CACCCC)) 
    \rreq_head_rcb_ok_ff[1]_i_17 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [6]),
        .I1(\rreq_head_info_ff_reg[1][rcb] [6]),
        .I2(rdIssued_0),
        .I3(\canissueRd_ff_reg[0]_0 [1]),
        .I4(\canissueRd_ff_reg[0]_0 [0]),
        .I5(\rreq_head_rcb_ok_ff_reg[1]_i_14_1 ),
        .O(\rreq_head_rcb_ok_ff[1]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h36353333C6CACCCC)) 
    \rreq_head_rcb_ok_ff[1]_i_18 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [5]),
        .I1(\rreq_head_info_ff_reg[1][rcb] [5]),
        .I2(rdIssued_0),
        .I3(\canissueRd_ff_reg[0]_0 [1]),
        .I4(\canissueRd_ff_reg[0]_0 [0]),
        .I5(\rreq_head_rcb_ok_ff_reg[1]_i_14_0 ),
        .O(\rreq_head_rcb_ok_ff[1]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h36353333C6CACCCC)) 
    \rreq_head_rcb_ok_ff[1]_i_19 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [4]),
        .I1(\rreq_head_info_ff_reg[1][rcb] [4]),
        .I2(rdIssued_0),
        .I3(\canissueRd_ff_reg[0]_0 [1]),
        .I4(\canissueRd_ff_reg[0]_0 [0]),
        .I5(\rreq_head_info_ff_reg[0][rcb][4] ),
        .O(\rreq_head_rcb_ok_ff[1]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h36353333C6CACCCC)) 
    \rreq_head_rcb_ok_ff[1]_i_20 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [3]),
        .I1(\rreq_head_info_ff_reg[1][rcb] [3]),
        .I2(rdIssued_0),
        .I3(\canissueRd_ff_reg[0]_0 [1]),
        .I4(\canissueRd_ff_reg[0]_0 [0]),
        .I5(\rreq_head_info_ff_reg[0][rcb][3] ),
        .O(\rreq_head_rcb_ok_ff[1]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h36353333C6CACCCC)) 
    \rreq_head_rcb_ok_ff[1]_i_21 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [2]),
        .I1(\rreq_head_info_ff_reg[1][rcb] [2]),
        .I2(rdIssued_0),
        .I3(\canissueRd_ff_reg[0]_0 [1]),
        .I4(\canissueRd_ff_reg[0]_0 [0]),
        .I5(\rreq_head_info_ff_reg[0][rcb][2] ),
        .O(\rreq_head_rcb_ok_ff[1]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'h36353333C6CACCCC)) 
    \rreq_head_rcb_ok_ff[1]_i_22 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [1]),
        .I1(\rreq_head_info_ff_reg[1][rcb] [1]),
        .I2(rdIssued_0),
        .I3(\canissueRd_ff_reg[0]_0 [1]),
        .I4(\canissueRd_ff_reg[0]_0 [0]),
        .I5(\rreq_head_info_ff_reg[0][rcb][1] ),
        .O(\rreq_head_rcb_ok_ff[1]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'h36353333C6CACCCC)) 
    \rreq_head_rcb_ok_ff[1]_i_23 
       (.I0(\rreq_head_info_ff_reg[0][rcb][7] [0]),
        .I1(\rreq_head_info_ff_reg[1][rcb] [0]),
        .I2(rdIssued_0),
        .I3(\canissueRd_ff_reg[0]_0 [1]),
        .I4(\canissueRd_ff_reg[0]_0 [0]),
        .I5(\rreq_head_info_ff_reg[0][rcb][0] ),
        .O(\rreq_head_rcb_ok_ff[1]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF504444FF50)) 
    \rreq_head_rcb_ok_ff[1]_i_3 
       (.I0(\rreq_head_rcb_ok_ff_reg[1]_i_13_n_3 ),
        .I1(\rreq_head_rcb_ok_ff_reg[1] [2]),
        .I2(RcbAvail_nxt0[7]),
        .I3(RcbAvail_nxt0[8]),
        .I4(RcbAvail_upd_ff),
        .I5(\rreq_head_rcb_ok_ff_reg[1] [3]),
        .O(\rreq_head_rcb_ok_ff[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0A0A221105052211)) 
    \rreq_head_rcb_ok_ff[1]_i_4 
       (.I0(\rreq_head_rcb_ok_ff_reg[1]_i_13_n_3 ),
        .I1(RcbAvail_nxt0[8]),
        .I2(\rreq_head_rcb_ok_ff_reg[1] [3]),
        .I3(RcbAvail_nxt0[7]),
        .I4(RcbAvail_upd_ff),
        .I5(\rreq_head_rcb_ok_ff_reg[1] [2]),
        .O(\rreq_head_rcb_ok_ff[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h22222222BBB222B2)) 
    \rreq_head_rcb_ok_ff[1]_i_5 
       (.I0(RcbAvail_nxt),
        .I1(rreq_head_info_both_rcb_nxt[7]),
        .I2(RcbAvail_nxt0[6]),
        .I3(RcbAvail_upd_ff),
        .I4(\rreq_head_rcb_ok_ff_reg[1] [1]),
        .I5(rreq_head_info_both_rcb_nxt[6]),
        .O(\rreq_head_rcb_ok_ff[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0F002F2F0F000202)) 
    \rreq_head_rcb_ok_ff[1]_i_6 
       (.I0(RcbAvail_nxt0[4]),
        .I1(rreq_head_info_both_rcb_nxt[4]),
        .I2(rreq_head_info_both_rcb_nxt[5]),
        .I3(\rreq_head_rcb_ok_ff_reg[1] [0]),
        .I4(RcbAvail_upd_ff),
        .I5(RcbAvail_nxt0[5]),
        .O(\rreq_head_rcb_ok_ff[1]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h07010500)) 
    \rreq_head_rcb_ok_ff[1]_i_7 
       (.I0(rreq_head_info_both_rcb_nxt[3]),
        .I1(rreq_head_info_both_rcb_nxt[2]),
        .I2(RcbAvail_upd_ff),
        .I3(RcbAvail_nxt0[3]),
        .I4(RcbAvail_nxt0[2]),
        .O(\rreq_head_rcb_ok_ff[1]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h07010500)) 
    \rreq_head_rcb_ok_ff[1]_i_8 
       (.I0(rreq_head_info_both_rcb_nxt[1]),
        .I1(rreq_head_info_both_rcb_nxt[0]),
        .I2(RcbAvail_upd_ff),
        .I3(RcbAvail_nxt0[1]),
        .I4(RcbAvail_nxt0[0]),
        .O(\rreq_head_rcb_ok_ff[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hA95900000000A959)) 
    \rreq_head_rcb_ok_ff[1]_i_9 
       (.I0(rreq_head_info_both_rcb_nxt[6]),
        .I1(RcbAvail_nxt0[6]),
        .I2(RcbAvail_upd_ff),
        .I3(\rreq_head_rcb_ok_ff_reg[1] [1]),
        .I4(RcbAvail_nxt),
        .I5(rreq_head_info_both_rcb_nxt[7]),
        .O(\rreq_head_rcb_ok_ff[1]_i_9_n_0 ));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 \rreq_head_rcb_ok_ff_reg[0]_i_1 
       (.CI(\rreq_head_rcb_ok_ff_reg[0]_i_2_n_0 ),
        .CO({\NLW_rreq_head_rcb_ok_ff_reg[0]_i_1_CO_UNCONNECTED [3:1],\RcbAvail_new_ff_reg[8] [0]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,DI}),
        .O(\NLW_rreq_head_rcb_ok_ff_reg[0]_i_1_O_UNCONNECTED [3:0]),
        .S({1'b0,1'b0,1'b0,S}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 \rreq_head_rcb_ok_ff_reg[0]_i_2 
       (.CI(1'b0),
        .CO({\rreq_head_rcb_ok_ff_reg[0]_i_2_n_0 ,\rreq_head_rcb_ok_ff_reg[0]_i_2_n_1 ,\rreq_head_rcb_ok_ff_reg[0]_i_2_n_2 ,\rreq_head_rcb_ok_ff_reg[0]_i_2_n_3 }),
        .CYINIT(1'b1),
        .DI({\rreq_head_rcb_ok_ff[0]_i_5_n_0 ,\rreq_head_rcb_ok_ff[0]_i_6_n_0 ,\rreq_head_rcb_ok_ff[0]_i_7_n_0 ,\rreq_head_rcb_ok_ff[0]_i_8_n_0 }),
        .O(\NLW_rreq_head_rcb_ok_ff_reg[0]_i_2_O_UNCONNECTED [3:0]),
        .S({\rreq_head_rcb_ok_ff[0]_i_9_n_0 ,\rreq_head_rcb_ok_ff[0]_i_10_n_0 ,\rreq_head_rcb_ok_ff[0]_i_11_n_0 ,\rreq_head_rcb_ok_ff[0]_i_12_n_0 }));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 \rreq_head_rcb_ok_ff_reg[1]_i_1 
       (.CI(\rreq_head_rcb_ok_ff_reg[1]_i_2_n_0 ),
        .CO({\NLW_rreq_head_rcb_ok_ff_reg[1]_i_1_CO_UNCONNECTED [3:1],\RcbAvail_new_ff_reg[8] [1]}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\rreq_head_rcb_ok_ff[1]_i_3_n_0 }),
        .O(\NLW_rreq_head_rcb_ok_ff_reg[1]_i_1_O_UNCONNECTED [3:0]),
        .S({1'b0,1'b0,1'b0,\rreq_head_rcb_ok_ff[1]_i_4_n_0 }));
  CARRY4 \rreq_head_rcb_ok_ff_reg[1]_i_13 
       (.CI(\rreq_head_rcb_ok_ff_reg[1]_i_14_n_0 ),
        .CO({\NLW_rreq_head_rcb_ok_ff_reg[1]_i_13_CO_UNCONNECTED [3:1],\rreq_head_rcb_ok_ff_reg[1]_i_13_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\NLW_rreq_head_rcb_ok_ff_reg[1]_i_13_O_UNCONNECTED [3:0]),
        .S({1'b0,1'b0,1'b0,1'b1}));
  CARRY4 \rreq_head_rcb_ok_ff_reg[1]_i_14 
       (.CI(\rreq_head_rcb_ok_ff_reg[1]_i_15_n_0 ),
        .CO({\rreq_head_rcb_ok_ff_reg[1]_i_14_n_0 ,\rreq_head_rcb_ok_ff_reg[1]_i_14_n_1 ,\rreq_head_rcb_ok_ff_reg[1]_i_14_n_2 ,\rreq_head_rcb_ok_ff_reg[1]_i_14_n_3 }),
        .CYINIT(1'b0),
        .DI(\rreq_head_info_nxt[0][rcb] [7:4]),
        .O(rreq_head_info_both_rcb_nxt[7:4]),
        .S({\rreq_head_rcb_ok_ff[1]_i_16_n_0 ,\rreq_head_rcb_ok_ff[1]_i_17_n_0 ,\rreq_head_rcb_ok_ff[1]_i_18_n_0 ,\rreq_head_rcb_ok_ff[1]_i_19_n_0 }));
  CARRY4 \rreq_head_rcb_ok_ff_reg[1]_i_15 
       (.CI(1'b0),
        .CO({\rreq_head_rcb_ok_ff_reg[1]_i_15_n_0 ,\rreq_head_rcb_ok_ff_reg[1]_i_15_n_1 ,\rreq_head_rcb_ok_ff_reg[1]_i_15_n_2 ,\rreq_head_rcb_ok_ff_reg[1]_i_15_n_3 }),
        .CYINIT(1'b0),
        .DI(\rreq_head_info_nxt[0][rcb] [3:0]),
        .O(rreq_head_info_both_rcb_nxt[3:0]),
        .S({\rreq_head_rcb_ok_ff[1]_i_20_n_0 ,\rreq_head_rcb_ok_ff[1]_i_21_n_0 ,\rreq_head_rcb_ok_ff[1]_i_22_n_0 ,\rreq_head_rcb_ok_ff[1]_i_23_n_0 }));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 \rreq_head_rcb_ok_ff_reg[1]_i_2 
       (.CI(1'b0),
        .CO({\rreq_head_rcb_ok_ff_reg[1]_i_2_n_0 ,\rreq_head_rcb_ok_ff_reg[1]_i_2_n_1 ,\rreq_head_rcb_ok_ff_reg[1]_i_2_n_2 ,\rreq_head_rcb_ok_ff_reg[1]_i_2_n_3 }),
        .CYINIT(1'b1),
        .DI({\rreq_head_rcb_ok_ff[1]_i_5_n_0 ,\rreq_head_rcb_ok_ff[1]_i_6_n_0 ,\rreq_head_rcb_ok_ff[1]_i_7_n_0 ,\rreq_head_rcb_ok_ff[1]_i_8_n_0 }),
        .O(\NLW_rreq_head_rcb_ok_ff_reg[1]_i_2_O_UNCONNECTED [3:0]),
        .S({\rreq_head_rcb_ok_ff[1]_i_9_n_0 ,\rreq_head_rcb_ok_ff[1]_i_10_n_0 ,\rreq_head_rcb_ok_ff[1]_i_11_n_0 ,\rreq_head_rcb_ok_ff[1]_i_12_n_0 }));
  LUT6 #(
    .INIT(64'hAAAAABFBFFFFFFFF)) 
    \rreq_head_vld_ff[0]_i_1 
       (.I0(\reqdtlpSm_cs_reg[1] ),
        .I1(tag_ep_0),
        .I2(tag_sel_ff),
        .I3(tag_ep_1),
        .I4(empty_ff_0),
        .I5(\rreq_head_vld_ff[0]_i_3_n_0 ),
        .O(\rreq_head_vld_ff_reg[0]_0 [0]));
  LUT6 #(
    .INIT(64'h0800000000000000)) 
    \rreq_head_vld_ff[0]_i_2 
       (.I0(wtlp_dat_vld6_in),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[1]),
        .I3(rdIssued_s01),
        .I4(reqdtlpSm512_cs[0]),
        .I5(\canissueRd_ff_reg[0]_0 [1]),
        .O(\reqdtlpSm_cs_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair1567" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rreq_head_vld_ff[0]_i_3 
       (.I0(rdIssued_0),
        .I1(\canissueRd_ff_reg[0]_0 [0]),
        .O(\rreq_head_vld_ff[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1547" *) 
  LUT4 #(
    .INIT(16'hAF08)) 
    \rreq_head_vld_ff[1]_i_1 
       (.I0(rreq_active0),
        .I1(\canissueRd_ff_reg[0]_0 [0]),
        .I2(rdIssued_0),
        .I3(\canissueRd_ff_reg[0]_0 [1]),
        .O(\rreq_head_vld_ff_reg[0]_0 [1]));
  LUT2 #(
    .INIT(4'h6)) 
    tag_sel_ff_i_1
       (.I0(tag_sel_ff0),
        .I1(tag_sel_ff),
        .O(tag_sel_ff_reg));
  (* SOFT_HLUTNM = "soft_lutpair1614" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \tlp_rrq_snt_ff[0]_i_1 
       (.I0(rdIssued_0),
        .I1(\m_axis_rq_thead_d_ff_reg[0][37] [0]),
        .O(\rreq_head_info_ff_reg[0][tag][0] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1614" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \tlp_rrq_snt_ff[1]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][37] [0]),
        .I1(rdIssued_0),
        .O(\rreq_head_info_ff_reg[0][tag][0] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1612" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \tlp_rrq_tag_ff[0][5]_i_1 
       (.I0(\m_axis_rq_thead_d_ff_reg[0][37] [0]),
        .I1(rdIssued_0),
        .O(\rreq_head_info_ff_reg[0][tag][0]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1612" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \tlp_rrq_tag_ff[1][5]_i_1 
       (.I0(rdIssued_0),
        .I1(\m_axis_rq_thead_d_ff_reg[0][37] [0]),
        .O(\rreq_head_info_ff_reg[0][tag][0]_0 ));
  LUT5 #(
    .INIT(32'h0040FFFF)) 
    \wpl_hdr_adr_ff[63]_i_1 
       (.I0(reqdtlpSm_cs[1]),
        .I1(reqdtlpSm512_cs[0]),
        .I2(wtlp_dat_vld6_in),
        .I3(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I4(wpl_hdr_vld_ff),
        .O(wtlp_hdr_pop00_out));
  LUT3 #(
    .INIT(8'hB0)) 
    \wpl_hdr_adr_ff[63]_i_2 
       (.I0(force_ready_flush_ff),
        .I1(full_ff_reg_n_0),
        .I2(m_axis_rq_tvalid_d_ff),
        .O(wtlp_dat_vld6_in));
  LUT2 #(
    .INIT(4'hD)) 
    \wpl_hdr_adr_ff[63]_i_3 
       (.I0(rdIssued_s01),
        .I1(reqdtlpSm512_cs[1]),
        .O(\wpl_hdr_adr_ff[63]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1571" *) 
  LUT2 #(
    .INIT(4'h7)) 
    wpl_hdr_vld_ff_i_1
       (.I0(wtlp_hdr_pop00_out),
        .I1(\FifoCntrWr_reg[0]_0 ),
        .O(wpl_hdr_vld_nxt));
  (* SOFT_HLUTNM = "soft_lutpair1548" *) 
  LUT5 #(
    .INIT(32'h96669696)) 
    \wrq_pnd_cnt_ff[1]_i_1 
       (.I0(\wrq_pnd_cnt_ff_reg[3] [0]),
        .I1(\wrq_pnd_cnt_ff_reg[3] [1]),
        .I2(wcp_vld_ff),
        .I3(wr_user[0]),
        .I4(wtlp_hdr_rd_ff0),
        .O(\wrq_pnd_cnt_ff_reg[2] [0]));
  LUT6 #(
    .INIT(64'hA9A96AA96A6A6A6A)) 
    \wrq_pnd_cnt_ff[2]_i_1 
       (.I0(\wrq_pnd_cnt_ff_reg[3] [2]),
        .I1(\wrq_pnd_cnt_ff_reg[3] [0]),
        .I2(\wrq_pnd_cnt_ff_reg[3] [1]),
        .I3(wtlp_hdr_rd_ff0),
        .I4(wr_user[0]),
        .I5(wcp_vld_ff),
        .O(\wrq_pnd_cnt_ff_reg[2] [1]));
  LUT6 #(
    .INIT(64'hAAAAAAAAA9AAAAAA)) 
    \wrq_pnd_cnt_ff[3]_i_1 
       (.I0(wcp_vld_ff),
        .I1(wr_user[0]),
        .I2(reqdtlpSm_cs[1]),
        .I3(reqdtlpSm512_cs[0]),
        .I4(wtlp_dat_vld6_in),
        .I5(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(wcp_vld_ff_reg));
  LUT4 #(
    .INIT(16'h78E1)) 
    \wrq_pnd_cnt_ff[3]_i_2 
       (.I0(\wrq_pnd_cnt_ff_reg[3] [2]),
        .I1(\wrq_pnd_cnt_ff_reg[3] [1]),
        .I2(\wrq_pnd_cnt_ff_reg[3] [3]),
        .I3(\wrq_pnd_cnt_ff[3]_i_3_n_0 ),
        .O(\wrq_pnd_cnt_ff_reg[2] [2]));
  (* SOFT_HLUTNM = "soft_lutpair1548" *) 
  LUT5 #(
    .INIT(32'h75FF0075)) 
    \wrq_pnd_cnt_ff[3]_i_3 
       (.I0(wcp_vld_ff),
        .I1(wr_user[0]),
        .I2(wtlp_hdr_rd_ff0),
        .I3(\wrq_pnd_cnt_ff_reg[3] [1]),
        .I4(\wrq_pnd_cnt_ff_reg[3] [0]),
        .O(\wrq_pnd_cnt_ff[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h40000000FFFFFFFF)) 
    \wseq_ff[3]_i_1 
       (.I0(\wseq_ff[3]_i_4_n_0 ),
        .I1(wr_user[4]),
        .I2(wr_user[3]),
        .I3(wr_user[1]),
        .I4(wr_user[2]),
        .I5(user_rst_n_3ff_reg),
        .O(SR));
  (* SOFT_HLUTNM = "soft_lutpair1549" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \wseq_ff[3]_i_2 
       (.I0(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I1(wtlp_dat_vld6_in),
        .I2(reqdtlpSm512_cs[0]),
        .I3(reqdtlpSm_cs[1]),
        .I4(wr_user[0]),
        .O(\reqdtlpSm512_cs_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1549" *) 
  LUT5 #(
    .INIT(32'hFFFFEFFF)) 
    \wseq_ff[3]_i_4 
       (.I0(wr_user[0]),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\wseq_ff[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1558" *) 
  LUT4 #(
    .INIT(16'h9969)) 
    \wtlp_dat_cnt_nn1[1]_i_1 
       (.I0(\wtlp_dat_cnt_nn1_reg[3] [0]),
        .I1(\wtlp_dat_cnt_nn1_reg[3] [1]),
        .I2(wtlp_wpl_wen_500),
        .I3(wtlp_dat_ren),
        .O(\wtlp_dat_cnt_nn1_reg[2] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1558" *) 
  LUT5 #(
    .INIT(32'hA6AAAA59)) 
    \wtlp_dat_cnt_nn1[2]_i_1 
       (.I0(\wtlp_dat_cnt_nn1_reg[3] [2]),
        .I1(wtlp_wpl_wen_500),
        .I2(wtlp_dat_ren),
        .I3(\wtlp_dat_cnt_nn1_reg[3] [1]),
        .I4(\wtlp_dat_cnt_nn1_reg[3] [0]),
        .O(\wtlp_dat_cnt_nn1_reg[2] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1613" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wtlp_dat_cnt_nn1[3]_i_1 
       (.I0(wtlp_wpl_wen_500),
        .I1(wtlp_dat_ren),
        .O(wtlp_wpl_wen_500_reg));
  LUT6 #(
    .INIT(64'hF0F078F0E1E1F0E1)) 
    \wtlp_dat_cnt_nn1[3]_i_2 
       (.I0(\wtlp_dat_cnt_nn1_reg[3] [2]),
        .I1(\wtlp_dat_cnt_nn1_reg[3] [1]),
        .I2(\wtlp_dat_cnt_nn1_reg[3] [3]),
        .I3(wtlp_wpl_wen_500),
        .I4(wtlp_dat_ren),
        .I5(\wtlp_dat_cnt_nn1_reg[3] [0]),
        .O(\wtlp_dat_cnt_nn1_reg[2] [2]));
  LUT2 #(
    .INIT(4'hE)) 
    \wtlp_dat_vld_ff[0]_i_1 
       (.I0(\wtlp_dat_vld_ff[0]_i_2_n_0 ),
        .I1(\wtlp_dat_vld_ff[0]_i_3_n_0 ),
        .O(wtlp_dat_vld));
  LUT6 #(
    .INIT(64'h0F0000000808AA08)) 
    \wtlp_dat_vld_ff[0]_i_2 
       (.I0(\wtlp_dat_vld_ff[0]_i_4_n_0 ),
        .I1(wtlp_dat_vld_ff),
        .I2(wtlp_dat_vld6_in),
        .I3(rdIssued_s01),
        .I4(reqdtlpSm512_cs[1]),
        .I5(\wtlp_dat_vld_ff_reg[0] ),
        .O(\wtlp_dat_vld_ff[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0A0A3A0AAA0A0A0A)) 
    \wtlp_dat_vld_ff[0]_i_3 
       (.I0(\wtlp_dat_vld_ff[0]_i_6_n_0 ),
        .I1(beatdone),
        .I2(rdIssued_s01),
        .I3(reqdtlpSm512_cs[0]),
        .I4(reqdtlpSm_cs[1]),
        .I5(reqdtlpSm512_cs[1]),
        .O(\wtlp_dat_vld_ff[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF00FF00FFB0)) 
    \wtlp_dat_vld_ff[0]_i_4 
       (.I0(p_0_in123_out),
        .I1(wrreq),
        .I2(wtlp_dat_vld_ff),
        .I3(reqdtlpSm512_cs[1]),
        .I4(wtlp_dat_vld6_in),
        .I5(reqdtlpSm_cs[1]),
        .O(\wtlp_dat_vld_ff[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1562" *) 
  LUT4 #(
    .INIT(16'h22A2)) 
    \wtlp_dat_vld_ff[0]_i_6 
       (.I0(wtlp_dat_vld_ff),
        .I1(m_axis_rq_tvalid_d_ff),
        .I2(full_ff_reg_n_0),
        .I3(force_ready_flush_ff),
        .O(\wtlp_dat_vld_ff[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEFEEEFEEEEEE)) 
    wtlp_hdr_av_i_1
       (.I0(wtlp_hdr_av_i_2_n_0),
        .I1(\wtlp_hdr_rd_cnt_nn1_reg[2] [3]),
        .I2(flush_txn_linkdown),
        .I3(\wtlp_hdr_rd_cnt_nn1_reg[3] [0]),
        .I4(\wtlp_hdr_rd_cnt_nn1_reg[3] [1]),
        .I5(\wtlp_hdr_rd_cnt_nn1[3]_i_2_n_0 ),
        .O(\flush_txn_linkdown_ff_reg[3] ));
  LUT6 #(
    .INIT(64'h5554145544555554)) 
    wtlp_hdr_av_i_2
       (.I0(flush_txn_linkdown),
        .I1(\wtlp_hdr_rd_cnt_nn1_reg[3] [2]),
        .I2(\wtlp_hdr_rd_cnt_nn1_reg[3] [1]),
        .I3(\wtlp_hdr_rd_cnt_nn1_reg[3] [0]),
        .I4(wtlp_hdr_rd_ff0),
        .I5(wtlp_hdr_ld_501),
        .O(wtlp_hdr_av_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1550" *) 
  LUT4 #(
    .INIT(16'h0096)) 
    \wtlp_hdr_rd_cnt_nn1[0]_i_1 
       (.I0(\wtlp_hdr_rd_cnt_nn1_reg[3] [0]),
        .I1(wtlp_hdr_rd_ff0),
        .I2(wtlp_hdr_ld_501),
        .I3(flush_txn_linkdown),
        .O(\wtlp_hdr_rd_cnt_nn1_reg[2] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1550" *) 
  LUT5 #(
    .INIT(32'h0000DB24)) 
    \wtlp_hdr_rd_cnt_nn1[1]_i_1 
       (.I0(wtlp_hdr_ld_501),
        .I1(wtlp_hdr_rd_ff0),
        .I2(\wtlp_hdr_rd_cnt_nn1_reg[3] [0]),
        .I3(\wtlp_hdr_rd_cnt_nn1_reg[3] [1]),
        .I4(flush_txn_linkdown),
        .O(\wtlp_hdr_rd_cnt_nn1_reg[2] [1]));
  LUT6 #(
    .INIT(64'h00000000DFFB2004)) 
    \wtlp_hdr_rd_cnt_nn1[2]_i_1 
       (.I0(wtlp_hdr_ld_501),
        .I1(wtlp_hdr_rd_ff0),
        .I2(\wtlp_hdr_rd_cnt_nn1_reg[3] [0]),
        .I3(\wtlp_hdr_rd_cnt_nn1_reg[3] [1]),
        .I4(\wtlp_hdr_rd_cnt_nn1_reg[3] [2]),
        .I5(flush_txn_linkdown),
        .O(\wtlp_hdr_rd_cnt_nn1_reg[2] [2]));
  LUT6 #(
    .INIT(64'h00000000FE7F0180)) 
    \wtlp_hdr_rd_cnt_nn1[3]_i_1 
       (.I0(\wtlp_hdr_rd_cnt_nn1_reg[3] [2]),
        .I1(\wtlp_hdr_rd_cnt_nn1_reg[3] [1]),
        .I2(\wtlp_hdr_rd_cnt_nn1[3]_i_2_n_0 ),
        .I3(\wtlp_hdr_rd_cnt_nn1[3]_i_3_n_0 ),
        .I4(\wtlp_hdr_rd_cnt_nn1_reg[3] [3]),
        .I5(flush_txn_linkdown),
        .O(\wtlp_hdr_rd_cnt_nn1_reg[2] [3]));
  LUT5 #(
    .INIT(32'hFFFFEFFF)) 
    \wtlp_hdr_rd_cnt_nn1[3]_i_2 
       (.I0(wtlp_hdr_ld_501),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .O(\wtlp_hdr_rd_cnt_nn1[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h55556555FFFFFFFF)) 
    \wtlp_hdr_rd_cnt_nn1[3]_i_3 
       (.I0(wtlp_hdr_ld_501),
        .I1(reqdtlpSm_cs[1]),
        .I2(reqdtlpSm512_cs[0]),
        .I3(wtlp_dat_vld6_in),
        .I4(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I5(\wtlp_hdr_rd_cnt_nn1_reg[3] [0]),
        .O(\wtlp_hdr_rd_cnt_nn1[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000044040000)) 
    wtlp_hdr_rd_ff_i_1
       (.I0(\wpl_hdr_adr_ff[63]_i_3_n_0 ),
        .I1(m_axis_rq_tvalid_d_ff),
        .I2(full_ff_reg_n_0),
        .I3(force_ready_flush_ff),
        .I4(reqdtlpSm512_cs[0]),
        .I5(reqdtlpSm_cs[1]),
        .O(wtlp_hdr_rd_ff0));
  (* SOFT_HLUTNM = "soft_lutpair1559" *) 
  LUT4 #(
    .INIT(16'h9969)) 
    \wtlp_rd_dat_cnt_nn1[1]_i_1 
       (.I0(\wtlp_rd_dat_cnt_nn1_reg[3] [1]),
        .I1(\wtlp_rd_dat_cnt_nn1_reg[3] [0]),
        .I2(wtlp_wpl_wen_503),
        .I3(wtlp_dat_ren),
        .O(\wtlp_rd_dat_cnt_nn1_reg[2] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1559" *) 
  LUT5 #(
    .INIT(32'hA6AAAA59)) 
    \wtlp_rd_dat_cnt_nn1[2]_i_1 
       (.I0(\wtlp_rd_dat_cnt_nn1_reg[3] [2]),
        .I1(wtlp_wpl_wen_503),
        .I2(wtlp_dat_ren),
        .I3(\wtlp_rd_dat_cnt_nn1_reg[3] [1]),
        .I4(\wtlp_rd_dat_cnt_nn1_reg[3] [0]),
        .O(\wtlp_rd_dat_cnt_nn1_reg[2] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1613" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wtlp_rd_dat_cnt_nn1[3]_i_1 
       (.I0(wtlp_wpl_wen_503),
        .I1(wtlp_dat_ren),
        .O(wtlp_wpl_wen_503_reg));
  LUT6 #(
    .INIT(64'hF0F078F0E1E1F0E1)) 
    \wtlp_rd_dat_cnt_nn1[3]_i_2 
       (.I0(\wtlp_rd_dat_cnt_nn1_reg[3] [2]),
        .I1(\wtlp_rd_dat_cnt_nn1_reg[3] [1]),
        .I2(\wtlp_rd_dat_cnt_nn1_reg[3] [3]),
        .I3(wtlp_wpl_wen_503),
        .I4(wtlp_dat_ren),
        .I5(\wtlp_rd_dat_cnt_nn1_reg[3] [0]),
        .O(\wtlp_rd_dat_cnt_nn1_reg[2] [2]));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOHead" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOHead__parameterized0
   (\WrPtr_reg[0]_0 ,
    \Head_reg[0]_0 ,
    wb_info_fl,
    empty_ff_reg_0,
    empty_ff_reg_1,
    user_clk,
    Q,
    wb_win_vld,
    O52,
    arbstall,
    empty_ff,
    D);
  output [0:0]\WrPtr_reg[0]_0 ;
  output \Head_reg[0]_0 ;
  output wb_info_fl;
  output empty_ff_reg_0;
  output empty_ff_reg_1;
  input user_clk;
  input [0:0]Q;
  input wb_win_vld;
  input O52;
  input arbstall;
  input empty_ff;
  input [0:0]D;

  wire [0:0]D;
  wire \FifoCntrRd[0]_i_1__11_n_0 ;
  wire \FifoCntrRd[1]_i_1__9_n_0 ;
  wire \FifoCntrRd[2]_i_1__9_n_0 ;
  wire \FifoCntrRd[2]_i_2__6_n_0 ;
  wire \FifoCntrRd_reg_n_0_[0] ;
  wire \FifoCntrRd_reg_n_0_[1] ;
  wire \FifoCntrRd_reg_n_0_[2] ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__14_n_0 ;
  wire \FifoCntrWr[1]_i_1__10_n_0 ;
  wire \FifoCntrWr[2]_i_1__11_n_0 ;
  wire \Head[0]_i_1__5_n_0 ;
  wire \Head[0]_i_2_n_0 ;
  wire \Head[0]_i_3_n_0 ;
  wire \Head_reg[0]_0 ;
  wire MemArray_reg_0_3_0_0_n_0;
  wire O52;
  wire [0:0]Q;
  wire [1:0]RdPtr;
  wire \RdPtr[1]_i_2__5_n_0 ;
  wire [1:0]RdPtr_0;
  wire [1:1]WrPtr;
  wire [1:1]WrPtr_1;
  wire [0:0]\WrPtr_reg[0]_0 ;
  wire almost_full_ff_i_1__3_n_0;
  wire arbstall;
  wire empty_ff;
  wire empty_ff_i_1__17_n_0;
  wire empty_ff_reg_0;
  wire empty_ff_reg_1;
  wire user_clk;
  wire wb_info_fl;
  wire wb_win_vld;
  wire NLW_MemArray_reg_0_3_0_0_SPO_UNCONNECTED;

  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__11 
       (.I0(\FifoCntrRd_reg_n_0_[0] ),
        .O(\FifoCntrRd[0]_i_1__11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1331" *) 
  LUT3 #(
    .INIT(8'h96)) 
    \FifoCntrRd[1]_i_1__9 
       (.I0(\FifoCntrRd_reg_n_0_[0] ),
        .I1(\FifoCntrRd_reg_n_0_[1] ),
        .I2(empty_ff),
        .O(\FifoCntrRd[1]_i_1__9_n_0 ));
  LUT3 #(
    .INIT(8'h1E)) 
    \FifoCntrRd[2]_i_1__9 
       (.I0(arbstall),
        .I1(empty_ff_reg_0),
        .I2(empty_ff),
        .O(\FifoCntrRd[2]_i_1__9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1331" *) 
  LUT4 #(
    .INIT(16'hA69A)) 
    \FifoCntrRd[2]_i_2__6 
       (.I0(\FifoCntrRd_reg_n_0_[2] ),
        .I1(\FifoCntrRd_reg_n_0_[1] ),
        .I2(empty_ff),
        .I3(\FifoCntrRd_reg_n_0_[0] ),
        .O(\FifoCntrRd[2]_i_2__6_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__9_n_0 ),
        .D(\FifoCntrRd[0]_i_1__11_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[0] ),
        .R(O52));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__9_n_0 ),
        .D(\FifoCntrRd[1]_i_1__9_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[1] ),
        .R(O52));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__9_n_0 ),
        .D(\FifoCntrRd[2]_i_2__6_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[2] ),
        .R(O52));
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__14 
       (.I0(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1330" *) 
  LUT3 #(
    .INIT(8'h96)) 
    \FifoCntrWr[1]_i_1__10 
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(empty_ff),
        .O(\FifoCntrWr[1]_i_1__10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1330" *) 
  LUT4 #(
    .INIT(16'hA69A)) 
    \FifoCntrWr[2]_i_1__11 
       (.I0(FifoCntrWr[2]),
        .I1(FifoCntrWr[0]),
        .I2(empty_ff),
        .I3(FifoCntrWr[1]),
        .O(\FifoCntrWr[2]_i_1__11_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__9_n_0 ),
        .D(\FifoCntrWr[0]_i_1__14_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(O52));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__9_n_0 ),
        .D(\FifoCntrWr[1]_i_1__10_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(O52));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__9_n_0 ),
        .D(\FifoCntrWr[2]_i_1__11_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(O52));
  LUT6 #(
    .INIT(64'hBA8AFFFFBA8A0000)) 
    \Head[0]_i_1__5 
       (.I0(MemArray_reg_0_3_0_0_n_0),
        .I1(empty_ff),
        .I2(\Head[0]_i_2_n_0 ),
        .I3(Q),
        .I4(\Head[0]_i_3_n_0 ),
        .I5(\Head_reg[0]_0 ),
        .O(\Head[0]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1329" *) 
  LUT5 #(
    .INIT(32'h01010103)) 
    \Head[0]_i_2 
       (.I0(\FifoCntrRd_reg_n_0_[0] ),
        .I1(\FifoCntrRd_reg_n_0_[2] ),
        .I2(\FifoCntrRd_reg_n_0_[1] ),
        .I3(empty_ff_reg_0),
        .I4(arbstall),
        .O(\Head[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1329" *) 
  LUT5 #(
    .INIT(32'h1111111F)) 
    \Head[0]_i_3 
       (.I0(arbstall),
        .I1(empty_ff_reg_0),
        .I2(\FifoCntrRd_reg_n_0_[2] ),
        .I3(\FifoCntrRd_reg_n_0_[1] ),
        .I4(\FifoCntrRd_reg_n_0_[0] ),
        .O(\Head[0]_i_3_n_0 ));
  FDRE \Head_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\Head[0]_i_1__5_n_0 ),
        .Q(\Head_reg[0]_0 ),
        .R(O52));
  (* RTL_RAM_BITS = "4" *) 
  (* RTL_RAM_NAME = "WB_CHNL_FIFO/MemArray_reg" *) 
  (* RTL_RAM_TYPE = "RAM_TDP" *) 
  (* XILINX_LEGACY_PRIM = "RAM16X1D" *) 
  (* XILINX_TRANSFORM_PINMAP = "GND:DPRA4,A4" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "0" *) 
  RAM32X1D #(
    .INIT(32'h00000000)) 
    MemArray_reg_0_3_0_0
       (.A0(\WrPtr_reg[0]_0 ),
        .A1(WrPtr_1),
        .A2(1'b0),
        .A3(1'b0),
        .A4(1'b0),
        .D(Q),
        .DPO(MemArray_reg_0_3_0_0_n_0),
        .DPRA0(RdPtr_0[0]),
        .DPRA1(RdPtr_0[1]),
        .DPRA2(1'b0),
        .DPRA3(1'b0),
        .DPRA4(1'b0),
        .SPO(NLW_MemArray_reg_0_3_0_0_SPO_UNCONNECTED),
        .WCLK(user_clk),
        .WE(wb_win_vld));
  LUT2 #(
    .INIT(4'h1)) 
    MemArray_reg_0_3_108_112_i_5
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .O(empty_ff_reg_1));
  LUT6 #(
    .INIT(64'h5559AAAA5559AAA9)) 
    \RdPtr[0]_i_1__12 
       (.I0(RdPtr_0[0]),
        .I1(empty_ff),
        .I2(\FifoCntrRd_reg_n_0_[1] ),
        .I3(\FifoCntrRd_reg_n_0_[2] ),
        .I4(empty_ff_reg_1),
        .I5(\FifoCntrRd_reg_n_0_[0] ),
        .O(RdPtr[0]));
  LUT6 #(
    .INIT(64'h5AAA5A59AAAAAAAA)) 
    \RdPtr[1]_i_1__13 
       (.I0(RdPtr_0[1]),
        .I1(\FifoCntrRd_reg_n_0_[0] ),
        .I2(empty_ff_reg_1),
        .I3(\RdPtr[1]_i_2__5_n_0 ),
        .I4(empty_ff),
        .I5(RdPtr_0[0]),
        .O(RdPtr[1]));
  LUT2 #(
    .INIT(4'hE)) 
    \RdPtr[1]_i_2__5 
       (.I0(\FifoCntrRd_reg_n_0_[2] ),
        .I1(\FifoCntrRd_reg_n_0_[1] ),
        .O(\RdPtr[1]_i_2__5_n_0 ));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr[0]),
        .Q(RdPtr_0[0]),
        .R(O52));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr[1]),
        .Q(RdPtr_0[1]),
        .R(O52));
  LUT3 #(
    .INIT(8'h9A)) 
    \WrPtr[1]_i_1__13 
       (.I0(WrPtr_1),
        .I1(empty_ff),
        .I2(\WrPtr_reg[0]_0 ),
        .O(WrPtr));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(\WrPtr_reg[0]_0 ),
        .R(O52));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr),
        .Q(WrPtr_1),
        .R(O52));
  LUT4 #(
    .INIT(16'hBAAA)) 
    almost_full_ff_i_1__3
       (.I0(FifoCntrWr[2]),
        .I1(empty_ff),
        .I2(FifoCntrWr[1]),
        .I3(FifoCntrWr[0]),
        .O(almost_full_ff_i_1__3_n_0));
  FDRE almost_full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(almost_full_ff_i_1__3_n_0),
        .Q(wb_info_fl),
        .R(O52));
  LUT6 #(
    .INIT(64'hFFFFFFFF00030103)) 
    empty_ff_i_1__17
       (.I0(arbstall),
        .I1(\FifoCntrRd_reg_n_0_[2] ),
        .I2(\FifoCntrRd_reg_n_0_[1] ),
        .I3(\FifoCntrRd_reg_n_0_[0] ),
        .I4(empty_ff_reg_0),
        .I5(O52),
        .O(empty_ff_i_1__17_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__17_n_0),
        .Q(empty_ff_reg_0),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOHead" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOHead__parameterized1
   (payloadmuxed_0,
    empty_ff_reg_0,
    DataOut,
    full_ff_reg_0,
    \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35 ,
    \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35_0 ,
    almost_full_ff_2,
    rrq_rdy_nn1,
    out,
    empty_ff_reg_1,
    \FifoCntrRd_reg[2]_0 ,
    user_clk,
    \Head_reg[15]_0 ,
    \Head_reg[32]_0 ,
    \Head_reg[46]_0 ,
    DataIn,
    empty_ff_reg_2);
  output [1:0]payloadmuxed_0;
  output empty_ff_reg_0;
  output [81:0]DataOut;
  output full_ff_reg_0;
  input \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35 ;
  input \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35_0 ;
  input almost_full_ff_2;
  input rrq_rdy_nn1;
  input out;
  input empty_ff_reg_1;
  input \FifoCntrRd_reg[2]_0 ;
  input user_clk;
  input [7:0]\Head_reg[15]_0 ;
  input [12:0]\Head_reg[32]_0 ;
  input \Head_reg[46]_0 ;
  input [58:0]DataIn;
  input empty_ff_reg_2;

  wire [58:0]DataIn;
  wire [81:0]DataOut;
  wire [2:0]FifoCntrRd;
  wire \FifoCntrRd[0]_i_1_n_0 ;
  wire \FifoCntrRd[1]_i_1_n_0 ;
  wire \FifoCntrRd[2]_i_1_n_0 ;
  wire \FifoCntrRd_reg[2]_0 ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1_n_0 ;
  wire \FifoCntrWr[1]_i_1_n_0 ;
  wire \FifoCntrWr[2]_i_1_n_0 ;
  wire [119:8]Head0;
  wire Head1;
  wire \Head[119]_i_1_n_0 ;
  wire \Head[33]_i_1__1_n_0 ;
  wire \Head[47]_i_1__4_n_0 ;
  wire \Head[60]_i_1__5_n_0 ;
  wire [7:0]\Head_reg[15]_0 ;
  wire [12:0]\Head_reg[32]_0 ;
  wire \Head_reg[46]_0 ;
  wire [1:0]RdPtr;
  wire [1:0]RdPtr__0;
  wire [1:0]WrPtr;
  wire [1:0]WrPtr__0;
  wire almost_full_ff_2;
  wire \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35 ;
  wire \axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35_0 ;
  wire empty_ff_i_1_n_0;
  wire empty_ff_reg_0;
  wire empty_ff_reg_1;
  wire empty_ff_reg_2;
  wire full_ff_i_1_n_0;
  wire full_ff_reg_0;
  wire out;
  wire [119:8]p_0_in1_in;
  wire [15:14]p_2_in;
  wire [1:0]payloadmuxed_0;
  wire rrq_rdy_nn1;
  wire rrq_vld_new;
  wire user_clk;
  wire [1:0]NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_30_35_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair1145" *) 
  LUT4 #(
    .INIT(16'h8778)) 
    \FifoCntrRd[0]_i_1 
       (.I0(rrq_rdy_nn1),
        .I1(out),
        .I2(empty_ff_reg_1),
        .I3(FifoCntrRd[0]),
        .O(\FifoCntrRd[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1145" *) 
  LUT5 #(
    .INIT(32'hEA7F1580)) 
    \FifoCntrRd[1]_i_1 
       (.I0(FifoCntrRd[0]),
        .I1(rrq_rdy_nn1),
        .I2(out),
        .I3(empty_ff_reg_1),
        .I4(FifoCntrRd[1]),
        .O(\FifoCntrRd[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFEEE7FFF01118000)) 
    \FifoCntrRd[2]_i_1 
       (.I0(FifoCntrRd[0]),
        .I1(FifoCntrRd[1]),
        .I2(rrq_rdy_nn1),
        .I3(out),
        .I4(empty_ff_reg_1),
        .I5(FifoCntrRd[2]),
        .O(\FifoCntrRd[2]_i_1_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[0]_i_1_n_0 ),
        .Q(FifoCntrRd[0]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[1]_i_1_n_0 ),
        .Q(FifoCntrRd[1]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[2]_i_1_n_0 ),
        .Q(FifoCntrRd[2]),
        .R(\FifoCntrRd_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1146" *) 
  LUT4 #(
    .INIT(16'h956A)) 
    \FifoCntrWr[0]_i_1 
       (.I0(empty_ff_reg_1),
        .I1(out),
        .I2(rrq_rdy_nn1),
        .I3(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1146" *) 
  LUT5 #(
    .INIT(32'hDBBB2444)) 
    \FifoCntrWr[1]_i_1 
       (.I0(FifoCntrWr[0]),
        .I1(empty_ff_reg_1),
        .I2(out),
        .I3(rrq_rdy_nn1),
        .I4(FifoCntrWr[1]),
        .O(\FifoCntrWr[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF7EFEFEF08101010)) 
    \FifoCntrWr[2]_i_1 
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(empty_ff_reg_1),
        .I3(out),
        .I4(rrq_rdy_nn1),
        .I5(FifoCntrWr[2]),
        .O(\FifoCntrWr[2]_i_1_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[0]_i_1_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[1]_i_1_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[2]_i_1_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(\FifoCntrRd_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1180" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[100]_i_1 
       (.I0(DataIn[39]),
        .I1(Head0[100]),
        .I2(Head1),
        .O(p_0_in1_in[100]));
  (* SOFT_HLUTNM = "soft_lutpair1180" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[101]_i_1 
       (.I0(DataIn[40]),
        .I1(Head0[101]),
        .I2(Head1),
        .O(p_0_in1_in[101]));
  (* SOFT_HLUTNM = "soft_lutpair1181" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[102]_i_1 
       (.I0(DataIn[41]),
        .I1(Head0[102]),
        .I2(Head1),
        .O(p_0_in1_in[102]));
  (* SOFT_HLUTNM = "soft_lutpair1181" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[103]_i_1 
       (.I0(DataIn[42]),
        .I1(Head0[103]),
        .I2(Head1),
        .O(p_0_in1_in[103]));
  (* SOFT_HLUTNM = "soft_lutpair1182" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[104]_i_1 
       (.I0(DataIn[43]),
        .I1(Head0[104]),
        .I2(Head1),
        .O(p_0_in1_in[104]));
  (* SOFT_HLUTNM = "soft_lutpair1182" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[105]_i_1 
       (.I0(DataIn[44]),
        .I1(Head0[105]),
        .I2(Head1),
        .O(p_0_in1_in[105]));
  (* SOFT_HLUTNM = "soft_lutpair1183" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[106]_i_1 
       (.I0(DataIn[45]),
        .I1(Head0[106]),
        .I2(Head1),
        .O(p_0_in1_in[106]));
  (* SOFT_HLUTNM = "soft_lutpair1183" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[107]_i_1 
       (.I0(DataIn[46]),
        .I1(Head0[107]),
        .I2(Head1),
        .O(p_0_in1_in[107]));
  (* SOFT_HLUTNM = "soft_lutpair1184" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[108]_i_1 
       (.I0(DataIn[47]),
        .I1(Head0[108]),
        .I2(Head1),
        .O(p_0_in1_in[108]));
  (* SOFT_HLUTNM = "soft_lutpair1184" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[109]_i_1 
       (.I0(DataIn[48]),
        .I1(Head0[109]),
        .I2(Head1),
        .O(p_0_in1_in[109]));
  (* SOFT_HLUTNM = "soft_lutpair1150" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[10]_i_1 
       (.I0(\Head_reg[15]_0 [2]),
        .I1(Head0[10]),
        .I2(Head1),
        .O(p_0_in1_in[10]));
  (* SOFT_HLUTNM = "soft_lutpair1185" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[110]_i_1 
       (.I0(DataIn[49]),
        .I1(Head0[110]),
        .I2(Head1),
        .O(p_0_in1_in[110]));
  (* SOFT_HLUTNM = "soft_lutpair1185" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[111]_i_1 
       (.I0(DataIn[50]),
        .I1(Head0[111]),
        .I2(Head1),
        .O(p_0_in1_in[111]));
  (* SOFT_HLUTNM = "soft_lutpair1186" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[112]_i_1 
       (.I0(DataIn[51]),
        .I1(Head0[112]),
        .I2(Head1),
        .O(p_0_in1_in[112]));
  (* SOFT_HLUTNM = "soft_lutpair1186" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[113]_i_1 
       (.I0(DataIn[52]),
        .I1(Head0[113]),
        .I2(Head1),
        .O(p_0_in1_in[113]));
  (* SOFT_HLUTNM = "soft_lutpair1187" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[114]_i_1 
       (.I0(DataIn[53]),
        .I1(Head0[114]),
        .I2(Head1),
        .O(p_0_in1_in[114]));
  (* SOFT_HLUTNM = "soft_lutpair1187" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[115]_i_1 
       (.I0(DataIn[54]),
        .I1(Head0[115]),
        .I2(Head1),
        .O(p_0_in1_in[115]));
  (* SOFT_HLUTNM = "soft_lutpair1188" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[116]_i_1 
       (.I0(DataIn[55]),
        .I1(Head0[116]),
        .I2(Head1),
        .O(p_0_in1_in[116]));
  (* SOFT_HLUTNM = "soft_lutpair1188" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[117]_i_1 
       (.I0(DataIn[56]),
        .I1(Head0[117]),
        .I2(Head1),
        .O(p_0_in1_in[117]));
  (* SOFT_HLUTNM = "soft_lutpair1189" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[118]_i_1 
       (.I0(DataIn[57]),
        .I1(Head0[118]),
        .I2(Head1),
        .O(p_0_in1_in[118]));
  LUT5 #(
    .INIT(32'hEEEEEEEF)) 
    \Head[119]_i_1 
       (.I0(Head1),
        .I1(empty_ff_reg_1),
        .I2(FifoCntrRd[2]),
        .I3(FifoCntrRd[1]),
        .I4(FifoCntrRd[0]),
        .O(\Head[119]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1189" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[119]_i_2 
       (.I0(DataIn[58]),
        .I1(Head0[119]),
        .I2(Head1),
        .O(p_0_in1_in[119]));
  (* SOFT_HLUTNM = "soft_lutpair1151" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[11]_i_1 
       (.I0(\Head_reg[15]_0 [3]),
        .I1(Head0[11]),
        .I2(Head1),
        .O(p_0_in1_in[11]));
  (* SOFT_HLUTNM = "soft_lutpair1151" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[12]_i_1 
       (.I0(\Head_reg[15]_0 [4]),
        .I1(Head0[12]),
        .I2(Head1),
        .O(p_0_in1_in[12]));
  (* SOFT_HLUTNM = "soft_lutpair1152" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[13]_i_1 
       (.I0(\Head_reg[15]_0 [5]),
        .I1(Head0[13]),
        .I2(Head1),
        .O(p_0_in1_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair1152" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[14]_i_1 
       (.I0(\Head_reg[15]_0 [6]),
        .I1(Head0[14]),
        .I2(Head1),
        .O(p_0_in1_in[14]));
  (* SOFT_HLUTNM = "soft_lutpair1153" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[15]_i_1 
       (.I0(\Head_reg[15]_0 [7]),
        .I1(Head0[15]),
        .I2(Head1),
        .O(p_0_in1_in[15]));
  (* SOFT_HLUTNM = "soft_lutpair1153" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[20]_i_1 
       (.I0(\Head_reg[32]_0 [0]),
        .I1(Head0[20]),
        .I2(Head1),
        .O(p_0_in1_in[20]));
  (* SOFT_HLUTNM = "soft_lutpair1154" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[21]_i_1 
       (.I0(\Head_reg[32]_0 [1]),
        .I1(Head0[21]),
        .I2(Head1),
        .O(p_0_in1_in[21]));
  (* SOFT_HLUTNM = "soft_lutpair1154" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[22]_i_1 
       (.I0(\Head_reg[32]_0 [2]),
        .I1(Head0[22]),
        .I2(Head1),
        .O(p_0_in1_in[22]));
  (* SOFT_HLUTNM = "soft_lutpair1155" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[23]_i_1 
       (.I0(\Head_reg[32]_0 [3]),
        .I1(Head0[23]),
        .I2(Head1),
        .O(p_0_in1_in[23]));
  (* SOFT_HLUTNM = "soft_lutpair1155" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[24]_i_1 
       (.I0(\Head_reg[32]_0 [4]),
        .I1(Head0[24]),
        .I2(Head1),
        .O(p_0_in1_in[24]));
  (* SOFT_HLUTNM = "soft_lutpair1156" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[25]_i_1 
       (.I0(\Head_reg[32]_0 [5]),
        .I1(Head0[25]),
        .I2(Head1),
        .O(p_0_in1_in[25]));
  (* SOFT_HLUTNM = "soft_lutpair1156" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[26]_i_1 
       (.I0(\Head_reg[32]_0 [6]),
        .I1(Head0[26]),
        .I2(Head1),
        .O(p_0_in1_in[26]));
  (* SOFT_HLUTNM = "soft_lutpair1157" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[27]_i_1 
       (.I0(\Head_reg[32]_0 [7]),
        .I1(Head0[27]),
        .I2(Head1),
        .O(p_0_in1_in[27]));
  (* SOFT_HLUTNM = "soft_lutpair1157" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[28]_i_1 
       (.I0(\Head_reg[32]_0 [8]),
        .I1(Head0[28]),
        .I2(Head1),
        .O(p_0_in1_in[28]));
  (* SOFT_HLUTNM = "soft_lutpair1158" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[29]_i_1 
       (.I0(\Head_reg[32]_0 [9]),
        .I1(Head0[29]),
        .I2(Head1),
        .O(p_0_in1_in[29]));
  (* SOFT_HLUTNM = "soft_lutpair1158" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[30]_i_1 
       (.I0(\Head_reg[32]_0 [10]),
        .I1(Head0[30]),
        .I2(Head1),
        .O(p_0_in1_in[30]));
  (* SOFT_HLUTNM = "soft_lutpair1159" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[31]_i_1 
       (.I0(\Head_reg[32]_0 [11]),
        .I1(Head0[31]),
        .I2(Head1),
        .O(p_0_in1_in[31]));
  (* SOFT_HLUTNM = "soft_lutpair1159" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[32]_i_1 
       (.I0(\Head_reg[32]_0 [12]),
        .I1(Head0[32]),
        .I2(Head1),
        .O(p_0_in1_in[32]));
  (* SOFT_HLUTNM = "soft_lutpair1148" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[33]_i_1__1 
       (.I0(Head0[33]),
        .I1(Head1),
        .O(\Head[33]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1160" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[46]_i_1 
       (.I0(\Head_reg[46]_0 ),
        .I1(Head0[46]),
        .I2(Head1),
        .O(p_0_in1_in[46]));
  (* SOFT_HLUTNM = "soft_lutpair1149" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[47]_i_1__4 
       (.I0(Head0[47]),
        .I1(Head1),
        .O(\Head[47]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1150" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[60]_i_1__5 
       (.I0(Head0[60]),
        .I1(Head1),
        .O(\Head[60]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1160" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[61]_i_1 
       (.I0(DataIn[0]),
        .I1(Head0[61]),
        .I2(Head1),
        .O(p_0_in1_in[61]));
  (* SOFT_HLUTNM = "soft_lutpair1161" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[62]_i_1 
       (.I0(DataIn[1]),
        .I1(Head0[62]),
        .I2(Head1),
        .O(p_0_in1_in[62]));
  (* SOFT_HLUTNM = "soft_lutpair1161" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[63]_i_1 
       (.I0(DataIn[2]),
        .I1(Head0[63]),
        .I2(Head1),
        .O(p_0_in1_in[63]));
  (* SOFT_HLUTNM = "soft_lutpair1162" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[64]_i_1 
       (.I0(DataIn[3]),
        .I1(Head0[64]),
        .I2(Head1),
        .O(p_0_in1_in[64]));
  (* SOFT_HLUTNM = "soft_lutpair1162" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[65]_i_1 
       (.I0(DataIn[4]),
        .I1(Head0[65]),
        .I2(Head1),
        .O(p_0_in1_in[65]));
  (* SOFT_HLUTNM = "soft_lutpair1163" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[66]_i_1 
       (.I0(DataIn[5]),
        .I1(Head0[66]),
        .I2(Head1),
        .O(p_0_in1_in[66]));
  (* SOFT_HLUTNM = "soft_lutpair1163" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[67]_i_1 
       (.I0(DataIn[6]),
        .I1(Head0[67]),
        .I2(Head1),
        .O(p_0_in1_in[67]));
  (* SOFT_HLUTNM = "soft_lutpair1164" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[68]_i_1 
       (.I0(DataIn[7]),
        .I1(Head0[68]),
        .I2(Head1),
        .O(p_0_in1_in[68]));
  (* SOFT_HLUTNM = "soft_lutpair1164" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[69]_i_1 
       (.I0(DataIn[8]),
        .I1(Head0[69]),
        .I2(Head1),
        .O(p_0_in1_in[69]));
  (* SOFT_HLUTNM = "soft_lutpair1165" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[70]_i_1 
       (.I0(DataIn[9]),
        .I1(Head0[70]),
        .I2(Head1),
        .O(p_0_in1_in[70]));
  (* SOFT_HLUTNM = "soft_lutpair1165" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[71]_i_1 
       (.I0(DataIn[10]),
        .I1(Head0[71]),
        .I2(Head1),
        .O(p_0_in1_in[71]));
  (* SOFT_HLUTNM = "soft_lutpair1166" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[72]_i_1 
       (.I0(DataIn[11]),
        .I1(Head0[72]),
        .I2(Head1),
        .O(p_0_in1_in[72]));
  (* SOFT_HLUTNM = "soft_lutpair1166" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[73]_i_1 
       (.I0(DataIn[12]),
        .I1(Head0[73]),
        .I2(Head1),
        .O(p_0_in1_in[73]));
  (* SOFT_HLUTNM = "soft_lutpair1167" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[74]_i_1 
       (.I0(DataIn[13]),
        .I1(Head0[74]),
        .I2(Head1),
        .O(p_0_in1_in[74]));
  (* SOFT_HLUTNM = "soft_lutpair1167" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[75]_i_1 
       (.I0(DataIn[14]),
        .I1(Head0[75]),
        .I2(Head1),
        .O(p_0_in1_in[75]));
  (* SOFT_HLUTNM = "soft_lutpair1168" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[76]_i_1 
       (.I0(DataIn[15]),
        .I1(Head0[76]),
        .I2(Head1),
        .O(p_0_in1_in[76]));
  (* SOFT_HLUTNM = "soft_lutpair1168" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[77]_i_1 
       (.I0(DataIn[16]),
        .I1(Head0[77]),
        .I2(Head1),
        .O(p_0_in1_in[77]));
  (* SOFT_HLUTNM = "soft_lutpair1169" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[78]_i_1 
       (.I0(DataIn[17]),
        .I1(Head0[78]),
        .I2(Head1),
        .O(p_0_in1_in[78]));
  (* SOFT_HLUTNM = "soft_lutpair1169" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[79]_i_1 
       (.I0(DataIn[18]),
        .I1(Head0[79]),
        .I2(Head1),
        .O(p_0_in1_in[79]));
  (* SOFT_HLUTNM = "soft_lutpair1170" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[80]_i_1 
       (.I0(DataIn[19]),
        .I1(Head0[80]),
        .I2(Head1),
        .O(p_0_in1_in[80]));
  (* SOFT_HLUTNM = "soft_lutpair1170" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[81]_i_1 
       (.I0(DataIn[20]),
        .I1(Head0[81]),
        .I2(Head1),
        .O(p_0_in1_in[81]));
  (* SOFT_HLUTNM = "soft_lutpair1171" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[82]_i_1 
       (.I0(DataIn[21]),
        .I1(Head0[82]),
        .I2(Head1),
        .O(p_0_in1_in[82]));
  (* SOFT_HLUTNM = "soft_lutpair1171" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[83]_i_1 
       (.I0(DataIn[22]),
        .I1(Head0[83]),
        .I2(Head1),
        .O(p_0_in1_in[83]));
  (* SOFT_HLUTNM = "soft_lutpair1172" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[84]_i_1 
       (.I0(DataIn[23]),
        .I1(Head0[84]),
        .I2(Head1),
        .O(p_0_in1_in[84]));
  (* SOFT_HLUTNM = "soft_lutpair1172" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[85]_i_1 
       (.I0(DataIn[24]),
        .I1(Head0[85]),
        .I2(Head1),
        .O(p_0_in1_in[85]));
  (* SOFT_HLUTNM = "soft_lutpair1173" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[86]_i_1 
       (.I0(DataIn[25]),
        .I1(Head0[86]),
        .I2(Head1),
        .O(p_0_in1_in[86]));
  (* SOFT_HLUTNM = "soft_lutpair1173" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[87]_i_1 
       (.I0(DataIn[26]),
        .I1(Head0[87]),
        .I2(Head1),
        .O(p_0_in1_in[87]));
  (* SOFT_HLUTNM = "soft_lutpair1174" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[88]_i_1 
       (.I0(DataIn[27]),
        .I1(Head0[88]),
        .I2(Head1),
        .O(p_0_in1_in[88]));
  (* SOFT_HLUTNM = "soft_lutpair1174" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[89]_i_1 
       (.I0(DataIn[28]),
        .I1(Head0[89]),
        .I2(Head1),
        .O(p_0_in1_in[89]));
  (* SOFT_HLUTNM = "soft_lutpair1148" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[8]_i_1 
       (.I0(\Head_reg[15]_0 [0]),
        .I1(Head0[8]),
        .I2(Head1),
        .O(p_0_in1_in[8]));
  (* SOFT_HLUTNM = "soft_lutpair1175" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[90]_i_1 
       (.I0(DataIn[29]),
        .I1(Head0[90]),
        .I2(Head1),
        .O(p_0_in1_in[90]));
  (* SOFT_HLUTNM = "soft_lutpair1175" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[91]_i_1 
       (.I0(DataIn[30]),
        .I1(Head0[91]),
        .I2(Head1),
        .O(p_0_in1_in[91]));
  (* SOFT_HLUTNM = "soft_lutpair1176" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[92]_i_1 
       (.I0(DataIn[31]),
        .I1(Head0[92]),
        .I2(Head1),
        .O(p_0_in1_in[92]));
  (* SOFT_HLUTNM = "soft_lutpair1176" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[93]_i_1 
       (.I0(DataIn[32]),
        .I1(Head0[93]),
        .I2(Head1),
        .O(p_0_in1_in[93]));
  (* SOFT_HLUTNM = "soft_lutpair1177" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[94]_i_1 
       (.I0(DataIn[33]),
        .I1(Head0[94]),
        .I2(Head1),
        .O(p_0_in1_in[94]));
  (* SOFT_HLUTNM = "soft_lutpair1177" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[95]_i_1 
       (.I0(DataIn[34]),
        .I1(Head0[95]),
        .I2(Head1),
        .O(p_0_in1_in[95]));
  (* SOFT_HLUTNM = "soft_lutpair1178" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[96]_i_1 
       (.I0(DataIn[35]),
        .I1(Head0[96]),
        .I2(Head1),
        .O(p_0_in1_in[96]));
  (* SOFT_HLUTNM = "soft_lutpair1178" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[97]_i_1 
       (.I0(DataIn[36]),
        .I1(Head0[97]),
        .I2(Head1),
        .O(p_0_in1_in[97]));
  (* SOFT_HLUTNM = "soft_lutpair1179" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[98]_i_1 
       (.I0(DataIn[37]),
        .I1(Head0[98]),
        .I2(Head1),
        .O(p_0_in1_in[98]));
  (* SOFT_HLUTNM = "soft_lutpair1179" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[99]_i_1 
       (.I0(DataIn[38]),
        .I1(Head0[99]),
        .I2(Head1),
        .O(p_0_in1_in[99]));
  (* SOFT_HLUTNM = "soft_lutpair1149" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[9]_i_1 
       (.I0(\Head_reg[15]_0 [1]),
        .I1(Head0[9]),
        .I2(Head1),
        .O(p_0_in1_in[9]));
  FDRE \Head_reg[100] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[100]),
        .Q(DataOut[62]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[101] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[101]),
        .Q(DataOut[63]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[102] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[102]),
        .Q(DataOut[64]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[103] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[103]),
        .Q(DataOut[65]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[104] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[104]),
        .Q(DataOut[66]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[105] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[105]),
        .Q(DataOut[67]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[106] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[106]),
        .Q(DataOut[68]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[107] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[107]),
        .Q(DataOut[69]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[108] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[108]),
        .Q(DataOut[70]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[109] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[109]),
        .Q(DataOut[71]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[10]),
        .Q(DataOut[2]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[110] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[110]),
        .Q(DataOut[72]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[111] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[111]),
        .Q(DataOut[73]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[112] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[112]),
        .Q(DataOut[74]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[113] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[113]),
        .Q(DataOut[75]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[114] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[114]),
        .Q(DataOut[76]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[115] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[115]),
        .Q(DataOut[77]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[116] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[116]),
        .Q(DataOut[78]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[117] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[117]),
        .Q(DataOut[79]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[118] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[118]),
        .Q(DataOut[80]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[119] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[119]),
        .Q(DataOut[81]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[11]),
        .Q(DataOut[3]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[12]),
        .Q(DataOut[4]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[13]),
        .Q(DataOut[5]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[14]),
        .Q(DataOut[6]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[15]),
        .Q(DataOut[7]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[20]),
        .Q(DataOut[8]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[21]),
        .Q(DataOut[9]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[22] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[22]),
        .Q(DataOut[10]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[23] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[23]),
        .Q(DataOut[11]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[24] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[24]),
        .Q(DataOut[12]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[25] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[25]),
        .Q(DataOut[13]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[26] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[26]),
        .Q(DataOut[14]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[27] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[27]),
        .Q(DataOut[15]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[28] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[28]),
        .Q(DataOut[16]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[29] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[29]),
        .Q(DataOut[17]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[30] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[30]),
        .Q(DataOut[18]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[31] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[31]),
        .Q(DataOut[19]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[32] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[32]),
        .Q(p_2_in[14]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[33] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(\Head[33]_i_1__1_n_0 ),
        .Q(p_2_in[15]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[46] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[46]),
        .Q(DataOut[20]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[47] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(\Head[47]_i_1__4_n_0 ),
        .Q(DataOut[21]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(\Head[60]_i_1__5_n_0 ),
        .Q(DataOut[22]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[61]),
        .Q(DataOut[23]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[62]),
        .Q(DataOut[24]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[63]),
        .Q(DataOut[25]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[64] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[64]),
        .Q(DataOut[26]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[65] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[65]),
        .Q(DataOut[27]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[66]),
        .Q(DataOut[28]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[67]),
        .Q(DataOut[29]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[68]),
        .Q(DataOut[30]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[69]),
        .Q(DataOut[31]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[70]),
        .Q(DataOut[32]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[71]),
        .Q(DataOut[33]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[72]),
        .Q(DataOut[34]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[73]),
        .Q(DataOut[35]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[74] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[74]),
        .Q(DataOut[36]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[75] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[75]),
        .Q(DataOut[37]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[76] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[76]),
        .Q(DataOut[38]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[77] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[77]),
        .Q(DataOut[39]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[78] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[78]),
        .Q(DataOut[40]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[79] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[79]),
        .Q(DataOut[41]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[80] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[80]),
        .Q(DataOut[42]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[81] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[81]),
        .Q(DataOut[43]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[82] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[82]),
        .Q(DataOut[44]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[83] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[83]),
        .Q(DataOut[45]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[84] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[84]),
        .Q(DataOut[46]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[85] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[85]),
        .Q(DataOut[47]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[86] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[86]),
        .Q(DataOut[48]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[87] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[87]),
        .Q(DataOut[49]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[88] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[88]),
        .Q(DataOut[50]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[89] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[89]),
        .Q(DataOut[51]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[8] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[8]),
        .Q(DataOut[0]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[90]),
        .Q(DataOut[52]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[91]),
        .Q(DataOut[53]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[92]),
        .Q(DataOut[54]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[93]),
        .Q(DataOut[55]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[94] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[94]),
        .Q(DataOut[56]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[95] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[95]),
        .Q(DataOut[57]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[96] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[96]),
        .Q(DataOut[58]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[97] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[97]),
        .Q(DataOut[59]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[98] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[98]),
        .Q(DataOut[60]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[99] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[99]),
        .Q(DataOut[61]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[9] 
       (.C(user_clk),
        .CE(\Head[119]_i_1_n_0 ),
        .D(p_0_in1_in[9]),
        .Q(DataOut[1]),
        .R(\FifoCntrRd_reg[2]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_102_107" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "102" *) 
  (* ram_slice_end = "107" *) 
  RAM32M MemArray_reg_0_3_102_107
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[42:41]),
        .DIB(DataIn[44:43]),
        .DIC(DataIn[46:45]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[103:102]),
        .DOB(Head0[105:104]),
        .DOC(Head0[107:106]),
        .DOD(NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_108_113" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "108" *) 
  (* ram_slice_end = "113" *) 
  RAM32M MemArray_reg_0_3_108_113
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[48:47]),
        .DIB(DataIn[50:49]),
        .DIC(DataIn[52:51]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[109:108]),
        .DOB(Head0[111:110]),
        .DOC(Head0[113:112]),
        .DOD(NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_114_119" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "114" *) 
  (* ram_slice_end = "119" *) 
  RAM32M MemArray_reg_0_3_114_119
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[54:53]),
        .DIB(DataIn[56:55]),
        .DIC(DataIn[58:57]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[115:114]),
        .DOB(Head0[117:116]),
        .DOC(Head0[119:118]),
        .DOD(NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\Head_reg[32]_0 [1:0]),
        .DIB(\Head_reg[32]_0 [3:2]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[21:20]),
        .DOB(Head0[23:22]),
        .DOC(NLW_MemArray_reg_0_3_18_23_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_24_29" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M MemArray_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\Head_reg[32]_0 [5:4]),
        .DIB(\Head_reg[32]_0 [7:6]),
        .DIC(\Head_reg[32]_0 [9:8]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[25:24]),
        .DOB(Head0[27:26]),
        .DOC(Head0[29:28]),
        .DOD(NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_30_35" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M MemArray_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\Head_reg[32]_0 [11:10]),
        .DIB({1'b0,\Head_reg[32]_0 [12]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[31:30]),
        .DOB(Head0[33:32]),
        .DOC(NLW_MemArray_reg_0_3_30_35_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  LUT5 #(
    .INIT(32'h00230000)) 
    MemArray_reg_0_3_30_35_i_3
       (.I0(\axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35 ),
        .I1(empty_ff_reg_0),
        .I2(\axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35_0 ),
        .I3(almost_full_ff_2),
        .I4(p_2_in[15]),
        .O(payloadmuxed_0[1]));
  LUT5 #(
    .INIT(32'h00230000)) 
    MemArray_reg_0_3_30_35_i_4
       (.I0(\axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35 ),
        .I1(empty_ff_reg_0),
        .I2(\axidma_rrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_30_35_0 ),
        .I3(almost_full_ff_2),
        .I4(p_2_in[14]),
        .O(payloadmuxed_0[0]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_42_47" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M MemArray_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({1'b0,\Head_reg[46]_0 }),
        .DIB(\Head_reg[15]_0 [5:4]),
        .DIC(\Head_reg[15]_0 [7:6]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[47:46]),
        .DOB(Head0[13:12]),
        .DOC(Head0[15:14]),
        .DOD(NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_60_65" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M MemArray_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({DataIn[0],1'b0}),
        .DIB(DataIn[2:1]),
        .DIC(DataIn[4:3]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[61:60]),
        .DOB(Head0[63:62]),
        .DOC(Head0[65:64]),
        .DOD(NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_66_71" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M MemArray_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[6:5]),
        .DIB(DataIn[8:7]),
        .DIC(DataIn[10:9]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[67:66]),
        .DOB(Head0[69:68]),
        .DOC(Head0[71:70]),
        .DOD(NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\Head_reg[15]_0 [1:0]),
        .DIB(\Head_reg[15]_0 [3:2]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[9:8]),
        .DOB(Head0[11:10]),
        .DOC(NLW_MemArray_reg_0_3_6_11_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  LUT2 #(
    .INIT(4'h8)) 
    MemArray_reg_0_3_6_11_i_1
       (.I0(rrq_rdy_nn1),
        .I1(out),
        .O(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_72_77" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M MemArray_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[12:11]),
        .DIB(DataIn[14:13]),
        .DIC(DataIn[16:15]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[73:72]),
        .DOB(Head0[75:74]),
        .DOC(Head0[77:76]),
        .DOD(NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_78_83" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "83" *) 
  RAM32M MemArray_reg_0_3_78_83
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[18:17]),
        .DIB(DataIn[20:19]),
        .DIC(DataIn[22:21]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[79:78]),
        .DOB(Head0[81:80]),
        .DOC(Head0[83:82]),
        .DOD(NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_84_89" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "84" *) 
  (* ram_slice_end = "89" *) 
  RAM32M MemArray_reg_0_3_84_89
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[24:23]),
        .DIB(DataIn[26:25]),
        .DIC(DataIn[28:27]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[85:84]),
        .DOB(Head0[87:86]),
        .DOC(Head0[89:88]),
        .DOD(NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_90_95" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "90" *) 
  (* ram_slice_end = "95" *) 
  RAM32M MemArray_reg_0_3_90_95
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[30:29]),
        .DIB(DataIn[32:31]),
        .DIC(DataIn[34:33]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[91:90]),
        .DOB(Head0[93:92]),
        .DOC(Head0[95:94]),
        .DOD(NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_96_101" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "96" *) 
  (* ram_slice_end = "101" *) 
  RAM32M MemArray_reg_0_3_96_101
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[36:35]),
        .DIB(DataIn[38:37]),
        .DIC(DataIn[40:39]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[97:96]),
        .DOB(Head0[99:98]),
        .DOC(Head0[101:100]),
        .DOD(NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_new));
  LUT5 #(
    .INIT(32'h5555666A)) 
    \RdPtr[0]_i_1 
       (.I0(RdPtr[0]),
        .I1(empty_ff_reg_1),
        .I2(FifoCntrRd[2]),
        .I3(FifoCntrRd[1]),
        .I4(Head1),
        .O(RdPtr__0[0]));
  LUT6 #(
    .INIT(64'h55577777AAA88888)) 
    \RdPtr[1]_i_1 
       (.I0(RdPtr[0]),
        .I1(Head1),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[2]),
        .I4(empty_ff_reg_1),
        .I5(RdPtr[1]),
        .O(RdPtr__0[1]));
  LUT6 #(
    .INIT(64'h0301000000000000)) 
    \RdPtr[1]_i_2 
       (.I0(FifoCntrRd[0]),
        .I1(FifoCntrRd[2]),
        .I2(FifoCntrRd[1]),
        .I3(empty_ff_reg_1),
        .I4(out),
        .I5(rrq_rdy_nn1),
        .O(Head1));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[0]),
        .Q(RdPtr[0]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(RdPtr[1]),
        .R(\FifoCntrRd_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1147" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \WrPtr[0]_i_1 
       (.I0(WrPtr[0]),
        .I1(out),
        .I2(rrq_rdy_nn1),
        .O(WrPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1147" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \WrPtr[1]_i_1 
       (.I0(WrPtr[0]),
        .I1(rrq_rdy_nn1),
        .I2(out),
        .I3(WrPtr[1]),
        .O(WrPtr__0[1]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[0]),
        .Q(WrPtr[0]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[1]),
        .Q(WrPtr[1]),
        .R(\FifoCntrRd_reg[2]_0 ));
  LUT5 #(
    .INIT(32'hFFFF000B)) 
    empty_ff_i_1
       (.I0(empty_ff_reg_1),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[2]),
        .I4(empty_ff_reg_2),
        .O(empty_ff_i_1_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1_n_0),
        .Q(empty_ff_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFF800011118000)) 
    full_ff_i_1
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(out),
        .I3(rrq_rdy_nn1),
        .I4(FifoCntrWr[2]),
        .I5(full_ff_reg_0),
        .O(full_ff_i_1_n_0));
  FDRE full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(full_ff_i_1_n_0),
        .Q(full_ff_reg_0),
        .R(\FifoCntrRd_reg[2]_0 ));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOHead" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOHead__parameterized1_42
   (empty_ff_reg_0,
    \dat_fifo_hd_nxt_nn1_reg[0] ,
    \dat_fifo_hd_nxt_nn1_reg[1] ,
    \dat_fifo_hd_nxt_nn1_reg[2] ,
    \dat_fifo_hd_nxt_nn1_reg[3] ,
    ctl_rst_nn1_reg,
    ctl_rst_nn1_reg_0,
    ctl_rst_nn1_reg_1,
    ctl_rst_nn1_reg_2,
    ctl_rst_nn1_reg_3,
    D,
    rrq_ld_90022_out,
    \rrq_sm_cur_900_reg[2] ,
    payloadOut,
    empty_ff_reg_1,
    \Head_reg[119]_0 ,
    rrq_vld_902,
    \rrq_sm_cur_900_reg[2]_0 ,
    \rrq_sm_cur_900_reg[3] ,
    \dat_fifo_hd_nn1_reg[9] ,
    cfg_linkdown_nn1,
    Q,
    dat_fifo_hd_nn1,
    ctl_run_re,
    \rrq_sm_cur_900_reg[3]_0 ,
    rrq_vld_903,
    almost_full_ff,
    rrq_ld_901_reg_rep__5,
    rrq_vld_903_reg,
    reg_sts_hlt_nn1,
    ctl_rst,
    \rrq_sm_cur_900_reg[3]_1 ,
    \rrq_sm_cur_900_reg[3]_2 ,
    \rrq_sm_cur_900_reg[4] ,
    rrq_eod_903,
    dsc_ep_nn0,
    rrq_dsc_vld_902,
    rrq_stall_902,
    rrq_dsc_rem0_902,
    rrq_fl_nn1,
    \FifoCntrRd_reg[2]_0 ,
    user_clk,
    DataIn,
    \Head_reg[57]_0 );
  output empty_ff_reg_0;
  output \dat_fifo_hd_nxt_nn1_reg[0] ;
  output \dat_fifo_hd_nxt_nn1_reg[1] ;
  output \dat_fifo_hd_nxt_nn1_reg[2] ;
  output \dat_fifo_hd_nxt_nn1_reg[3] ;
  output ctl_rst_nn1_reg;
  output ctl_rst_nn1_reg_0;
  output ctl_rst_nn1_reg_1;
  output ctl_rst_nn1_reg_2;
  output ctl_rst_nn1_reg_3;
  output [0:0]D;
  output rrq_ld_90022_out;
  output \rrq_sm_cur_900_reg[2] ;
  output [75:0]payloadOut;
  output empty_ff_reg_1;
  output [75:0]\Head_reg[119]_0 ;
  output rrq_vld_902;
  output [1:0]\rrq_sm_cur_900_reg[2]_0 ;
  output \rrq_sm_cur_900_reg[3] ;
  input \dat_fifo_hd_nn1_reg[9] ;
  input cfg_linkdown_nn1;
  input [9:0]Q;
  input [9:0]dat_fifo_hd_nn1;
  input ctl_run_re;
  input [3:0]\rrq_sm_cur_900_reg[3]_0 ;
  input rrq_vld_903;
  input almost_full_ff;
  input rrq_ld_901_reg_rep__5;
  input [1:0]rrq_vld_903_reg;
  input reg_sts_hlt_nn1;
  input ctl_rst;
  input \rrq_sm_cur_900_reg[3]_1 ;
  input \rrq_sm_cur_900_reg[3]_2 ;
  input \rrq_sm_cur_900_reg[4] ;
  input rrq_eod_903;
  input dsc_ep_nn0;
  input rrq_dsc_vld_902;
  input rrq_stall_902;
  input rrq_dsc_rem0_902;
  input rrq_fl_nn1;
  input \FifoCntrRd_reg[2]_0 ;
  input user_clk;
  input [73:0]DataIn;
  input [1:0]\Head_reg[57]_0 ;

  wire [0:0]D;
  wire [73:0]DataIn;
  wire [2:0]FifoCntrRd;
  wire \FifoCntrRd[0]_i_1__2_n_0 ;
  wire \FifoCntrRd[1]_i_1__2_n_0 ;
  wire \FifoCntrRd[2]_i_1__1_n_0 ;
  wire \FifoCntrRd_reg[2]_0 ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__2_n_0 ;
  wire \FifoCntrWr[1]_i_1__2_n_0 ;
  wire \FifoCntrWr[2]_i_1__2_n_0 ;
  wire [119:18]Head0;
  wire Head1;
  wire \Head[119]_i_1__1_n_0 ;
  wire [75:0]\Head_reg[119]_0 ;
  wire [1:0]\Head_reg[57]_0 ;
  wire [9:0]Q;
  wire [1:0]RdPtr;
  wire [1:0]RdPtr__0;
  wire [1:0]WrPtr;
  wire [1:0]WrPtr__0;
  wire almost_full_ff;
  wire cfg_linkdown_nn1;
  wire ctl_rst;
  wire ctl_rst_nn1_reg;
  wire ctl_rst_nn1_reg_0;
  wire ctl_rst_nn1_reg_1;
  wire ctl_rst_nn1_reg_2;
  wire ctl_rst_nn1_reg_3;
  wire ctl_run_re;
  wire [9:0]dat_fifo_hd_nn1;
  wire \dat_fifo_hd_nn1[9]_i_2_n_0 ;
  wire \dat_fifo_hd_nn1_reg[9] ;
  wire \dat_fifo_hd_nxt_nn1_reg[0] ;
  wire \dat_fifo_hd_nxt_nn1_reg[1] ;
  wire \dat_fifo_hd_nxt_nn1_reg[2] ;
  wire \dat_fifo_hd_nxt_nn1_reg[3] ;
  wire dsc_ep_nn0;
  wire empty_ff_i_1__2_n_0;
  wire empty_ff_i_2__2_n_0;
  wire empty_ff_reg_0;
  wire empty_ff_reg_1;
  wire full_ff_i_1__1_n_0;
  wire full_ff_reg_n_0;
  wire [119:18]p_0_in1_in;
  wire [75:0]payloadOut;
  wire reg_sts_hlt_nn1;
  wire rrq_dsc_rem0_902;
  wire rrq_dsc_vld_902;
  wire rrq_eod_903;
  wire rrq_fl_nn1;
  wire rrq_ld_90022_out;
  wire rrq_ld_901_reg_rep__5;
  wire \rrq_sm_cur_900_reg[2] ;
  wire [1:0]\rrq_sm_cur_900_reg[2]_0 ;
  wire \rrq_sm_cur_900_reg[3] ;
  wire [3:0]\rrq_sm_cur_900_reg[3]_0 ;
  wire \rrq_sm_cur_900_reg[3]_1 ;
  wire \rrq_sm_cur_900_reg[3]_2 ;
  wire \rrq_sm_cur_900_reg[4] ;
  wire rrq_stall_902;
  wire rrq_vld_902;
  wire rrq_vld_903;
  wire rrq_vld_903_i_2_n_0;
  wire [1:0]rrq_vld_903_reg;
  wire user_clk;
  wire [1:0]NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_54_59_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair923" *) 
  LUT3 #(
    .INIT(8'h96)) 
    \FifoCntrRd[0]_i_1__2 
       (.I0(rrq_vld_903),
        .I1(empty_ff_reg_0),
        .I2(FifoCntrRd[0]),
        .O(\FifoCntrRd[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair882" *) 
  LUT4 #(
    .INIT(16'hE718)) 
    \FifoCntrRd[1]_i_1__2 
       (.I0(FifoCntrRd[0]),
        .I1(rrq_vld_903),
        .I2(empty_ff_reg_0),
        .I3(FifoCntrRd[1]),
        .O(\FifoCntrRd[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair882" *) 
  LUT5 #(
    .INIT(32'hFE7F0180)) 
    \FifoCntrRd[2]_i_1__1 
       (.I0(FifoCntrRd[0]),
        .I1(FifoCntrRd[1]),
        .I2(rrq_vld_903),
        .I3(empty_ff_reg_0),
        .I4(FifoCntrRd[2]),
        .O(\FifoCntrRd[2]_i_1__1_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[0]_i_1__2_n_0 ),
        .Q(FifoCntrRd[0]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[1]_i_1__2_n_0 ),
        .Q(FifoCntrRd[1]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[2]_i_1__1_n_0 ),
        .Q(FifoCntrRd[2]),
        .R(\FifoCntrRd_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair923" *) 
  LUT3 #(
    .INIT(8'h96)) 
    \FifoCntrWr[0]_i_1__2 
       (.I0(empty_ff_reg_0),
        .I1(rrq_vld_903),
        .I2(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair883" *) 
  LUT4 #(
    .INIT(16'hDB24)) 
    \FifoCntrWr[1]_i_1__2 
       (.I0(FifoCntrWr[0]),
        .I1(empty_ff_reg_0),
        .I2(rrq_vld_903),
        .I3(FifoCntrWr[1]),
        .O(\FifoCntrWr[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair883" *) 
  LUT5 #(
    .INIT(32'hF7EF0810)) 
    \FifoCntrWr[2]_i_1__2 
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(empty_ff_reg_0),
        .I3(rrq_vld_903),
        .I4(FifoCntrWr[2]),
        .O(\FifoCntrWr[2]_i_1__2_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[0]_i_1__2_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[1]_i_1__2_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[2]_i_1__2_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(\FifoCntrRd_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair913" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[100]_i_1__2 
       (.I0(DataIn[54]),
        .I1(Head0[100]),
        .I2(Head1),
        .O(p_0_in1_in[100]));
  (* SOFT_HLUTNM = "soft_lutpair913" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[101]_i_1__2 
       (.I0(DataIn[55]),
        .I1(Head0[101]),
        .I2(Head1),
        .O(p_0_in1_in[101]));
  (* SOFT_HLUTNM = "soft_lutpair914" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[102]_i_1__2 
       (.I0(DataIn[56]),
        .I1(Head0[102]),
        .I2(Head1),
        .O(p_0_in1_in[102]));
  (* SOFT_HLUTNM = "soft_lutpair914" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[103]_i_1__2 
       (.I0(DataIn[57]),
        .I1(Head0[103]),
        .I2(Head1),
        .O(p_0_in1_in[103]));
  (* SOFT_HLUTNM = "soft_lutpair915" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[104]_i_1__2 
       (.I0(DataIn[58]),
        .I1(Head0[104]),
        .I2(Head1),
        .O(p_0_in1_in[104]));
  (* SOFT_HLUTNM = "soft_lutpair915" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[105]_i_1__2 
       (.I0(DataIn[59]),
        .I1(Head0[105]),
        .I2(Head1),
        .O(p_0_in1_in[105]));
  (* SOFT_HLUTNM = "soft_lutpair916" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[106]_i_1__2 
       (.I0(DataIn[60]),
        .I1(Head0[106]),
        .I2(Head1),
        .O(p_0_in1_in[106]));
  (* SOFT_HLUTNM = "soft_lutpair916" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[107]_i_1__2 
       (.I0(DataIn[61]),
        .I1(Head0[107]),
        .I2(Head1),
        .O(p_0_in1_in[107]));
  (* SOFT_HLUTNM = "soft_lutpair917" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[108]_i_1__2 
       (.I0(DataIn[62]),
        .I1(Head0[108]),
        .I2(Head1),
        .O(p_0_in1_in[108]));
  (* SOFT_HLUTNM = "soft_lutpair917" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[109]_i_1__2 
       (.I0(DataIn[63]),
        .I1(Head0[109]),
        .I2(Head1),
        .O(p_0_in1_in[109]));
  (* SOFT_HLUTNM = "soft_lutpair918" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[110]_i_1__2 
       (.I0(DataIn[64]),
        .I1(Head0[110]),
        .I2(Head1),
        .O(p_0_in1_in[110]));
  (* SOFT_HLUTNM = "soft_lutpair918" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[111]_i_1__2 
       (.I0(DataIn[65]),
        .I1(Head0[111]),
        .I2(Head1),
        .O(p_0_in1_in[111]));
  (* SOFT_HLUTNM = "soft_lutpair919" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[112]_i_1__1 
       (.I0(DataIn[66]),
        .I1(Head0[112]),
        .I2(Head1),
        .O(p_0_in1_in[112]));
  (* SOFT_HLUTNM = "soft_lutpair919" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[113]_i_1__1 
       (.I0(DataIn[67]),
        .I1(Head0[113]),
        .I2(Head1),
        .O(p_0_in1_in[113]));
  (* SOFT_HLUTNM = "soft_lutpair920" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[114]_i_1__1 
       (.I0(DataIn[68]),
        .I1(Head0[114]),
        .I2(Head1),
        .O(p_0_in1_in[114]));
  (* SOFT_HLUTNM = "soft_lutpair920" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[115]_i_1__1 
       (.I0(DataIn[69]),
        .I1(Head0[115]),
        .I2(Head1),
        .O(p_0_in1_in[115]));
  (* SOFT_HLUTNM = "soft_lutpair921" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[116]_i_1__1 
       (.I0(DataIn[70]),
        .I1(Head0[116]),
        .I2(Head1),
        .O(p_0_in1_in[116]));
  (* SOFT_HLUTNM = "soft_lutpair921" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[117]_i_1__1 
       (.I0(DataIn[71]),
        .I1(Head0[117]),
        .I2(Head1),
        .O(p_0_in1_in[117]));
  (* SOFT_HLUTNM = "soft_lutpair922" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[118]_i_1__1 
       (.I0(DataIn[72]),
        .I1(Head0[118]),
        .I2(Head1),
        .O(p_0_in1_in[118]));
  LUT5 #(
    .INIT(32'hEEEEEEEF)) 
    \Head[119]_i_1__1 
       (.I0(Head1),
        .I1(empty_ff_reg_0),
        .I2(FifoCntrRd[2]),
        .I3(FifoCntrRd[1]),
        .I4(FifoCntrRd[0]),
        .O(\Head[119]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair922" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[119]_i_2__0 
       (.I0(DataIn[73]),
        .I1(Head0[119]),
        .I2(Head1),
        .O(p_0_in1_in[119]));
  (* SOFT_HLUTNM = "soft_lutpair885" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[18]_i_1__1 
       (.I0(DataIn[0]),
        .I1(Head0[18]),
        .I2(Head1),
        .O(p_0_in1_in[18]));
  (* SOFT_HLUTNM = "soft_lutpair885" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[19]_i_1__1 
       (.I0(DataIn[1]),
        .I1(Head0[19]),
        .I2(Head1),
        .O(p_0_in1_in[19]));
  (* SOFT_HLUTNM = "soft_lutpair886" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[20]_i_1__2 
       (.I0(DataIn[2]),
        .I1(Head0[20]),
        .I2(Head1),
        .O(p_0_in1_in[20]));
  (* SOFT_HLUTNM = "soft_lutpair886" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[21]_i_1__2 
       (.I0(DataIn[3]),
        .I1(Head0[21]),
        .I2(Head1),
        .O(p_0_in1_in[21]));
  (* SOFT_HLUTNM = "soft_lutpair887" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[22]_i_1__1 
       (.I0(DataIn[4]),
        .I1(Head0[22]),
        .I2(Head1),
        .O(p_0_in1_in[22]));
  (* SOFT_HLUTNM = "soft_lutpair887" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[23]_i_1__1 
       (.I0(DataIn[5]),
        .I1(Head0[23]),
        .I2(Head1),
        .O(p_0_in1_in[23]));
  (* SOFT_HLUTNM = "soft_lutpair888" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[24]_i_1__1 
       (.I0(DataIn[6]),
        .I1(Head0[24]),
        .I2(Head1),
        .O(p_0_in1_in[24]));
  (* SOFT_HLUTNM = "soft_lutpair888" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[25]_i_1__1 
       (.I0(DataIn[7]),
        .I1(Head0[25]),
        .I2(Head1),
        .O(p_0_in1_in[25]));
  (* SOFT_HLUTNM = "soft_lutpair889" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[26]_i_1__1 
       (.I0(DataIn[8]),
        .I1(Head0[26]),
        .I2(Head1),
        .O(p_0_in1_in[26]));
  (* SOFT_HLUTNM = "soft_lutpair889" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[27]_i_1__1 
       (.I0(DataIn[9]),
        .I1(Head0[27]),
        .I2(Head1),
        .O(p_0_in1_in[27]));
  (* SOFT_HLUTNM = "soft_lutpair890" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[28]_i_1__1 
       (.I0(DataIn[10]),
        .I1(Head0[28]),
        .I2(Head1),
        .O(p_0_in1_in[28]));
  (* SOFT_HLUTNM = "soft_lutpair890" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[29]_i_1__1 
       (.I0(DataIn[11]),
        .I1(Head0[29]),
        .I2(Head1),
        .O(p_0_in1_in[29]));
  (* SOFT_HLUTNM = "soft_lutpair891" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[56]_i_1__1 
       (.I0(\Head_reg[57]_0 [0]),
        .I1(Head0[56]),
        .I2(Head1),
        .O(p_0_in1_in[56]));
  (* SOFT_HLUTNM = "soft_lutpair891" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[57]_i_1__1 
       (.I0(\Head_reg[57]_0 [1]),
        .I1(Head0[57]),
        .I2(Head1),
        .O(p_0_in1_in[57]));
  (* SOFT_HLUTNM = "soft_lutpair892" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[58]_i_1__1 
       (.I0(DataIn[12]),
        .I1(Head0[58]),
        .I2(Head1),
        .O(p_0_in1_in[58]));
  (* SOFT_HLUTNM = "soft_lutpair892" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[59]_i_1__1 
       (.I0(DataIn[13]),
        .I1(Head0[59]),
        .I2(Head1),
        .O(p_0_in1_in[59]));
  (* SOFT_HLUTNM = "soft_lutpair893" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[60]_i_1__1 
       (.I0(DataIn[14]),
        .I1(Head0[60]),
        .I2(Head1),
        .O(p_0_in1_in[60]));
  (* SOFT_HLUTNM = "soft_lutpair893" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[61]_i_1__2 
       (.I0(DataIn[15]),
        .I1(Head0[61]),
        .I2(Head1),
        .O(p_0_in1_in[61]));
  (* SOFT_HLUTNM = "soft_lutpair894" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[62]_i_1__2 
       (.I0(DataIn[16]),
        .I1(Head0[62]),
        .I2(Head1),
        .O(p_0_in1_in[62]));
  (* SOFT_HLUTNM = "soft_lutpair894" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[63]_i_1__2 
       (.I0(DataIn[17]),
        .I1(Head0[63]),
        .I2(Head1),
        .O(p_0_in1_in[63]));
  (* SOFT_HLUTNM = "soft_lutpair895" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[64]_i_1__2 
       (.I0(DataIn[18]),
        .I1(Head0[64]),
        .I2(Head1),
        .O(p_0_in1_in[64]));
  (* SOFT_HLUTNM = "soft_lutpair895" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[65]_i_1__2 
       (.I0(DataIn[19]),
        .I1(Head0[65]),
        .I2(Head1),
        .O(p_0_in1_in[65]));
  (* SOFT_HLUTNM = "soft_lutpair896" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[66]_i_1__2 
       (.I0(DataIn[20]),
        .I1(Head0[66]),
        .I2(Head1),
        .O(p_0_in1_in[66]));
  (* SOFT_HLUTNM = "soft_lutpair896" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[67]_i_1__2 
       (.I0(DataIn[21]),
        .I1(Head0[67]),
        .I2(Head1),
        .O(p_0_in1_in[67]));
  (* SOFT_HLUTNM = "soft_lutpair897" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[68]_i_1__2 
       (.I0(DataIn[22]),
        .I1(Head0[68]),
        .I2(Head1),
        .O(p_0_in1_in[68]));
  (* SOFT_HLUTNM = "soft_lutpair897" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[69]_i_1__2 
       (.I0(DataIn[23]),
        .I1(Head0[69]),
        .I2(Head1),
        .O(p_0_in1_in[69]));
  (* SOFT_HLUTNM = "soft_lutpair898" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[70]_i_1__2 
       (.I0(DataIn[24]),
        .I1(Head0[70]),
        .I2(Head1),
        .O(p_0_in1_in[70]));
  (* SOFT_HLUTNM = "soft_lutpair898" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[71]_i_1__2 
       (.I0(DataIn[25]),
        .I1(Head0[71]),
        .I2(Head1),
        .O(p_0_in1_in[71]));
  (* SOFT_HLUTNM = "soft_lutpair899" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[72]_i_1__2 
       (.I0(DataIn[26]),
        .I1(Head0[72]),
        .I2(Head1),
        .O(p_0_in1_in[72]));
  (* SOFT_HLUTNM = "soft_lutpair899" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[73]_i_1__2 
       (.I0(DataIn[27]),
        .I1(Head0[73]),
        .I2(Head1),
        .O(p_0_in1_in[73]));
  (* SOFT_HLUTNM = "soft_lutpair900" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[74]_i_1__2 
       (.I0(DataIn[28]),
        .I1(Head0[74]),
        .I2(Head1),
        .O(p_0_in1_in[74]));
  (* SOFT_HLUTNM = "soft_lutpair900" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[75]_i_1__2 
       (.I0(DataIn[29]),
        .I1(Head0[75]),
        .I2(Head1),
        .O(p_0_in1_in[75]));
  (* SOFT_HLUTNM = "soft_lutpair901" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[76]_i_1__2 
       (.I0(DataIn[30]),
        .I1(Head0[76]),
        .I2(Head1),
        .O(p_0_in1_in[76]));
  (* SOFT_HLUTNM = "soft_lutpair901" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[77]_i_1__2 
       (.I0(DataIn[31]),
        .I1(Head0[77]),
        .I2(Head1),
        .O(p_0_in1_in[77]));
  (* SOFT_HLUTNM = "soft_lutpair902" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[78]_i_1__2 
       (.I0(DataIn[32]),
        .I1(Head0[78]),
        .I2(Head1),
        .O(p_0_in1_in[78]));
  (* SOFT_HLUTNM = "soft_lutpair902" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[79]_i_1__2 
       (.I0(DataIn[33]),
        .I1(Head0[79]),
        .I2(Head1),
        .O(p_0_in1_in[79]));
  (* SOFT_HLUTNM = "soft_lutpair903" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[80]_i_1__2 
       (.I0(DataIn[34]),
        .I1(Head0[80]),
        .I2(Head1),
        .O(p_0_in1_in[80]));
  (* SOFT_HLUTNM = "soft_lutpair903" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[81]_i_1__2 
       (.I0(DataIn[35]),
        .I1(Head0[81]),
        .I2(Head1),
        .O(p_0_in1_in[81]));
  (* SOFT_HLUTNM = "soft_lutpair904" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[82]_i_1__2 
       (.I0(DataIn[36]),
        .I1(Head0[82]),
        .I2(Head1),
        .O(p_0_in1_in[82]));
  (* SOFT_HLUTNM = "soft_lutpair904" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[83]_i_1__2 
       (.I0(DataIn[37]),
        .I1(Head0[83]),
        .I2(Head1),
        .O(p_0_in1_in[83]));
  (* SOFT_HLUTNM = "soft_lutpair905" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[84]_i_1__2 
       (.I0(DataIn[38]),
        .I1(Head0[84]),
        .I2(Head1),
        .O(p_0_in1_in[84]));
  (* SOFT_HLUTNM = "soft_lutpair905" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[85]_i_1__2 
       (.I0(DataIn[39]),
        .I1(Head0[85]),
        .I2(Head1),
        .O(p_0_in1_in[85]));
  (* SOFT_HLUTNM = "soft_lutpair906" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[86]_i_1__2 
       (.I0(DataIn[40]),
        .I1(Head0[86]),
        .I2(Head1),
        .O(p_0_in1_in[86]));
  (* SOFT_HLUTNM = "soft_lutpair906" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[87]_i_1__2 
       (.I0(DataIn[41]),
        .I1(Head0[87]),
        .I2(Head1),
        .O(p_0_in1_in[87]));
  (* SOFT_HLUTNM = "soft_lutpair907" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[88]_i_1__2 
       (.I0(DataIn[42]),
        .I1(Head0[88]),
        .I2(Head1),
        .O(p_0_in1_in[88]));
  (* SOFT_HLUTNM = "soft_lutpair907" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[89]_i_1__2 
       (.I0(DataIn[43]),
        .I1(Head0[89]),
        .I2(Head1),
        .O(p_0_in1_in[89]));
  (* SOFT_HLUTNM = "soft_lutpair908" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[90]_i_1__2 
       (.I0(DataIn[44]),
        .I1(Head0[90]),
        .I2(Head1),
        .O(p_0_in1_in[90]));
  (* SOFT_HLUTNM = "soft_lutpair908" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[91]_i_1__2 
       (.I0(DataIn[45]),
        .I1(Head0[91]),
        .I2(Head1),
        .O(p_0_in1_in[91]));
  (* SOFT_HLUTNM = "soft_lutpair909" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[92]_i_1__2 
       (.I0(DataIn[46]),
        .I1(Head0[92]),
        .I2(Head1),
        .O(p_0_in1_in[92]));
  (* SOFT_HLUTNM = "soft_lutpair909" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[93]_i_1__2 
       (.I0(DataIn[47]),
        .I1(Head0[93]),
        .I2(Head1),
        .O(p_0_in1_in[93]));
  (* SOFT_HLUTNM = "soft_lutpair910" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[94]_i_1__2 
       (.I0(DataIn[48]),
        .I1(Head0[94]),
        .I2(Head1),
        .O(p_0_in1_in[94]));
  (* SOFT_HLUTNM = "soft_lutpair910" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[95]_i_1__2 
       (.I0(DataIn[49]),
        .I1(Head0[95]),
        .I2(Head1),
        .O(p_0_in1_in[95]));
  (* SOFT_HLUTNM = "soft_lutpair911" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[96]_i_1__2 
       (.I0(DataIn[50]),
        .I1(Head0[96]),
        .I2(Head1),
        .O(p_0_in1_in[96]));
  (* SOFT_HLUTNM = "soft_lutpair911" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[97]_i_1__2 
       (.I0(DataIn[51]),
        .I1(Head0[97]),
        .I2(Head1),
        .O(p_0_in1_in[97]));
  (* SOFT_HLUTNM = "soft_lutpair912" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[98]_i_1__2 
       (.I0(DataIn[52]),
        .I1(Head0[98]),
        .I2(Head1),
        .O(p_0_in1_in[98]));
  (* SOFT_HLUTNM = "soft_lutpair912" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[99]_i_1__2 
       (.I0(DataIn[53]),
        .I1(Head0[99]),
        .I2(Head1),
        .O(p_0_in1_in[99]));
  FDRE \Head_reg[100] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[100]),
        .Q(\Head_reg[119]_0 [56]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[101] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[101]),
        .Q(\Head_reg[119]_0 [57]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[102] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[102]),
        .Q(\Head_reg[119]_0 [58]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[103] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[103]),
        .Q(\Head_reg[119]_0 [59]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[104] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[104]),
        .Q(\Head_reg[119]_0 [60]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[105] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[105]),
        .Q(\Head_reg[119]_0 [61]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[106] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[106]),
        .Q(\Head_reg[119]_0 [62]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[107] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[107]),
        .Q(\Head_reg[119]_0 [63]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[108] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[108]),
        .Q(\Head_reg[119]_0 [64]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[109] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[109]),
        .Q(\Head_reg[119]_0 [65]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[110] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[110]),
        .Q(\Head_reg[119]_0 [66]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[111] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[111]),
        .Q(\Head_reg[119]_0 [67]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[112] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[112]),
        .Q(\Head_reg[119]_0 [68]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[113] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[113]),
        .Q(\Head_reg[119]_0 [69]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[114] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[114]),
        .Q(\Head_reg[119]_0 [70]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[115] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[115]),
        .Q(\Head_reg[119]_0 [71]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[116] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[116]),
        .Q(\Head_reg[119]_0 [72]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[117] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[117]),
        .Q(\Head_reg[119]_0 [73]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[118] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[118]),
        .Q(\Head_reg[119]_0 [74]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[119] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[119]),
        .Q(\Head_reg[119]_0 [75]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[18]),
        .Q(\Head_reg[119]_0 [0]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[19]),
        .Q(\Head_reg[119]_0 [1]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[20]),
        .Q(\Head_reg[119]_0 [2]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[21]),
        .Q(\Head_reg[119]_0 [3]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[22] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[22]),
        .Q(\Head_reg[119]_0 [4]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[23] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[23]),
        .Q(\Head_reg[119]_0 [5]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[24] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[24]),
        .Q(\Head_reg[119]_0 [6]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[25] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[25]),
        .Q(\Head_reg[119]_0 [7]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[26] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[26]),
        .Q(\Head_reg[119]_0 [8]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[27] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[27]),
        .Q(\Head_reg[119]_0 [9]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[28] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[28]),
        .Q(\Head_reg[119]_0 [10]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[29] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[29]),
        .Q(\Head_reg[119]_0 [11]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[56] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[56]),
        .Q(\Head_reg[119]_0 [12]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[57] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[57]),
        .Q(\Head_reg[119]_0 [13]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[58] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[58]),
        .Q(\Head_reg[119]_0 [14]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[59] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[59]),
        .Q(\Head_reg[119]_0 [15]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[60]),
        .Q(\Head_reg[119]_0 [16]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[61]),
        .Q(\Head_reg[119]_0 [17]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[62]),
        .Q(\Head_reg[119]_0 [18]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[63]),
        .Q(\Head_reg[119]_0 [19]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[64] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[64]),
        .Q(\Head_reg[119]_0 [20]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[65] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[65]),
        .Q(\Head_reg[119]_0 [21]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[66]),
        .Q(\Head_reg[119]_0 [22]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[67]),
        .Q(\Head_reg[119]_0 [23]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[68]),
        .Q(\Head_reg[119]_0 [24]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[69]),
        .Q(\Head_reg[119]_0 [25]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[70]),
        .Q(\Head_reg[119]_0 [26]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[71]),
        .Q(\Head_reg[119]_0 [27]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[72]),
        .Q(\Head_reg[119]_0 [28]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[73]),
        .Q(\Head_reg[119]_0 [29]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[74] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[74]),
        .Q(\Head_reg[119]_0 [30]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[75] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[75]),
        .Q(\Head_reg[119]_0 [31]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[76] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[76]),
        .Q(\Head_reg[119]_0 [32]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[77] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[77]),
        .Q(\Head_reg[119]_0 [33]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[78] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[78]),
        .Q(\Head_reg[119]_0 [34]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[79] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[79]),
        .Q(\Head_reg[119]_0 [35]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[80] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[80]),
        .Q(\Head_reg[119]_0 [36]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[81] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[81]),
        .Q(\Head_reg[119]_0 [37]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[82] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[82]),
        .Q(\Head_reg[119]_0 [38]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[83] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[83]),
        .Q(\Head_reg[119]_0 [39]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[84] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[84]),
        .Q(\Head_reg[119]_0 [40]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[85] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[85]),
        .Q(\Head_reg[119]_0 [41]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[86] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[86]),
        .Q(\Head_reg[119]_0 [42]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[87] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[87]),
        .Q(\Head_reg[119]_0 [43]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[88] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[88]),
        .Q(\Head_reg[119]_0 [44]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[89] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[89]),
        .Q(\Head_reg[119]_0 [45]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[90]),
        .Q(\Head_reg[119]_0 [46]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[91]),
        .Q(\Head_reg[119]_0 [47]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[92]),
        .Q(\Head_reg[119]_0 [48]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[93]),
        .Q(\Head_reg[119]_0 [49]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[94] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[94]),
        .Q(\Head_reg[119]_0 [50]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[95] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[95]),
        .Q(\Head_reg[119]_0 [51]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[96] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[96]),
        .Q(\Head_reg[119]_0 [52]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[97] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[97]),
        .Q(\Head_reg[119]_0 [53]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[98] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[98]),
        .Q(\Head_reg[119]_0 [54]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \Head_reg[99] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__1_n_0 ),
        .D(p_0_in1_in[99]),
        .Q(\Head_reg[119]_0 [55]),
        .R(\FifoCntrRd_reg[2]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_102_107" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "102" *) 
  (* ram_slice_end = "107" *) 
  RAM32M MemArray_reg_0_3_102_107
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[57:56]),
        .DIB(DataIn[59:58]),
        .DIC(DataIn[61:60]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[103:102]),
        .DOB(Head0[105:104]),
        .DOC(Head0[107:106]),
        .DOD(NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_1__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [59]),
        .O(payloadOut[59]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_2__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [58]),
        .O(payloadOut[58]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_3__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [61]),
        .O(payloadOut[61]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_4__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [60]),
        .O(payloadOut[60]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_5__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [63]),
        .O(payloadOut[63]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_6__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [62]),
        .O(payloadOut[62]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_108_113" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "108" *) 
  (* ram_slice_end = "113" *) 
  RAM32M MemArray_reg_0_3_108_113
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[63:62]),
        .DIB(DataIn[65:64]),
        .DIC(DataIn[67:66]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[109:108]),
        .DOB(Head0[111:110]),
        .DOC(Head0[113:112]),
        .DOD(NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_108_113_i_1__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [65]),
        .O(payloadOut[65]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_108_113_i_2__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [64]),
        .O(payloadOut[64]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_108_113_i_3__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [67]),
        .O(payloadOut[67]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_108_113_i_4__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [66]),
        .O(payloadOut[66]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_108_113_i_5__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [69]),
        .O(payloadOut[69]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_108_113_i_6__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [68]),
        .O(payloadOut[68]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_114_119" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "114" *) 
  (* ram_slice_end = "119" *) 
  RAM32M MemArray_reg_0_3_114_119
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[69:68]),
        .DIB(DataIn[71:70]),
        .DIC(DataIn[73:72]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[115:114]),
        .DOB(Head0[117:116]),
        .DOC(Head0[119:118]),
        .DOD(NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_114_119_i_1__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [71]),
        .O(payloadOut[71]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_114_119_i_2__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [70]),
        .O(payloadOut[70]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_114_119_i_3__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [73]),
        .O(payloadOut[73]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_114_119_i_4__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [72]),
        .O(payloadOut[72]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_114_119_i_5__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [75]),
        .O(payloadOut[75]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_114_119_i_6__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [74]),
        .O(payloadOut[74]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[1:0]),
        .DIB(DataIn[3:2]),
        .DIC(DataIn[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[19:18]),
        .DOB(Head0[21:20]),
        .DOC(Head0[23:22]),
        .DOD(NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT2 #(
    .INIT(4'h1)) 
    MemArray_reg_0_3_18_23_i_1__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .O(empty_ff_reg_0));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_18_23_i_2__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [1]),
        .O(payloadOut[1]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_18_23_i_3__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [0]),
        .O(payloadOut[0]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_18_23_i_4__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [3]),
        .O(payloadOut[3]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_18_23_i_5__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [2]),
        .O(payloadOut[2]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_18_23_i_6__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [5]),
        .O(payloadOut[5]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_18_23_i_7
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [4]),
        .O(payloadOut[4]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_24_29" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M MemArray_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[7:6]),
        .DIB(DataIn[9:8]),
        .DIC(DataIn[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[25:24]),
        .DOB(Head0[27:26]),
        .DOC(Head0[29:28]),
        .DOD(NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_24_29_i_1__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [7]),
        .O(payloadOut[7]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_24_29_i_2__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [6]),
        .O(payloadOut[6]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_24_29_i_3__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [9]),
        .O(payloadOut[9]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_24_29_i_4__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [8]),
        .O(payloadOut[8]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_24_29_i_5__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [11]),
        .O(payloadOut[11]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_24_29_i_6__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [10]),
        .O(payloadOut[10]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_54_59" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M MemArray_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\Head_reg[57]_0 ),
        .DIB(DataIn[13:12]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[57:56]),
        .DOB(Head0[59:58]),
        .DOC(NLW_MemArray_reg_0_3_54_59_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_54_59_i_1__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [13]),
        .O(payloadOut[13]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_54_59_i_2__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [12]),
        .O(payloadOut[12]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_54_59_i_3__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [15]),
        .O(payloadOut[15]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_54_59_i_4__0
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [14]),
        .O(payloadOut[14]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_60_65" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M MemArray_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[15:14]),
        .DIB(DataIn[17:16]),
        .DIC(DataIn[19:18]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[61:60]),
        .DOB(Head0[63:62]),
        .DOC(Head0[65:64]),
        .DOD(NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_1__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [17]),
        .O(payloadOut[17]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_2__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [16]),
        .O(payloadOut[16]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_3__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [19]),
        .O(payloadOut[19]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_4__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [18]),
        .O(payloadOut[18]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_5__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [21]),
        .O(payloadOut[21]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_6__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [20]),
        .O(payloadOut[20]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_66_71" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M MemArray_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[21:20]),
        .DIB(DataIn[23:22]),
        .DIC(DataIn[25:24]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[67:66]),
        .DOB(Head0[69:68]),
        .DOC(Head0[71:70]),
        .DOD(NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_1__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [23]),
        .O(payloadOut[23]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_2__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [22]),
        .O(payloadOut[22]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_3__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [25]),
        .O(payloadOut[25]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_4__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [24]),
        .O(payloadOut[24]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_5__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [27]),
        .O(payloadOut[27]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_6__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [26]),
        .O(payloadOut[26]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_72_77" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M MemArray_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[27:26]),
        .DIB(DataIn[29:28]),
        .DIC(DataIn[31:30]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[73:72]),
        .DOB(Head0[75:74]),
        .DOC(Head0[77:76]),
        .DOD(NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_1__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [29]),
        .O(payloadOut[29]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_2__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [28]),
        .O(payloadOut[28]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_3__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [31]),
        .O(payloadOut[31]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_4__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [30]),
        .O(payloadOut[30]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_5__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [33]),
        .O(payloadOut[33]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_6__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [32]),
        .O(payloadOut[32]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_78_83" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "83" *) 
  RAM32M MemArray_reg_0_3_78_83
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[33:32]),
        .DIB(DataIn[35:34]),
        .DIC(DataIn[37:36]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[79:78]),
        .DOB(Head0[81:80]),
        .DOC(Head0[83:82]),
        .DOD(NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_1__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [35]),
        .O(payloadOut[35]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_2__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [34]),
        .O(payloadOut[34]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_3__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [37]),
        .O(payloadOut[37]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_4__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [36]),
        .O(payloadOut[36]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_5__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [39]),
        .O(payloadOut[39]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_6__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [38]),
        .O(payloadOut[38]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_84_89" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "84" *) 
  (* ram_slice_end = "89" *) 
  RAM32M MemArray_reg_0_3_84_89
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[39:38]),
        .DIB(DataIn[41:40]),
        .DIC(DataIn[43:42]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[85:84]),
        .DOB(Head0[87:86]),
        .DOC(Head0[89:88]),
        .DOD(NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_1__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [41]),
        .O(payloadOut[41]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_2__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [40]),
        .O(payloadOut[40]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_3__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [43]),
        .O(payloadOut[43]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_4__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [42]),
        .O(payloadOut[42]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_5__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [45]),
        .O(payloadOut[45]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_6__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [44]),
        .O(payloadOut[44]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_90_95" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "90" *) 
  (* ram_slice_end = "95" *) 
  RAM32M MemArray_reg_0_3_90_95
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[45:44]),
        .DIB(DataIn[47:46]),
        .DIC(DataIn[49:48]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[91:90]),
        .DOB(Head0[93:92]),
        .DOC(Head0[95:94]),
        .DOD(NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_1__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [47]),
        .O(payloadOut[47]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_2__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [46]),
        .O(payloadOut[46]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_3__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [49]),
        .O(payloadOut[49]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_4__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [48]),
        .O(payloadOut[48]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_5__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [51]),
        .O(payloadOut[51]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_6__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [50]),
        .O(payloadOut[50]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_96_101" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "96" *) 
  (* ram_slice_end = "101" *) 
  RAM32M MemArray_reg_0_3_96_101
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[51:50]),
        .DIB(DataIn[53:52]),
        .DIC(DataIn[55:54]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[97:96]),
        .DOB(Head0[99:98]),
        .DOC(Head0[101:100]),
        .DOD(NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_1__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [53]),
        .O(payloadOut[53]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_2__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [52]),
        .O(payloadOut[52]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_3__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [55]),
        .O(payloadOut[55]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_4__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [54]),
        .O(payloadOut[54]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_5__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [57]),
        .O(payloadOut[57]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_6__1
       (.I0(empty_ff_reg_1),
        .I1(almost_full_ff),
        .I2(\Head_reg[119]_0 [56]),
        .O(payloadOut[56]));
  LUT5 #(
    .INIT(32'h5555666A)) 
    \RdPtr[0]_i_1__2 
       (.I0(RdPtr[0]),
        .I1(empty_ff_reg_0),
        .I2(FifoCntrRd[2]),
        .I3(FifoCntrRd[1]),
        .I4(Head1),
        .O(RdPtr__0[0]));
  LUT6 #(
    .INIT(64'h55577777AAA88888)) 
    \RdPtr[1]_i_1__2 
       (.I0(RdPtr[0]),
        .I1(Head1),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[2]),
        .I4(empty_ff_reg_0),
        .I5(RdPtr[1]),
        .O(RdPtr__0[1]));
  LUT5 #(
    .INIT(32'h03010000)) 
    \RdPtr[1]_i_2__1 
       (.I0(FifoCntrRd[0]),
        .I1(FifoCntrRd[2]),
        .I2(FifoCntrRd[1]),
        .I3(empty_ff_reg_0),
        .I4(rrq_vld_903),
        .O(Head1));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[0]),
        .Q(RdPtr[0]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(RdPtr[1]),
        .R(\FifoCntrRd_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair924" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \WrPtr[0]_i_1__2 
       (.I0(WrPtr[0]),
        .I1(rrq_vld_903),
        .O(WrPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair924" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \WrPtr[1]_i_1__2 
       (.I0(WrPtr[0]),
        .I1(rrq_vld_903),
        .I2(WrPtr[1]),
        .O(WrPtr__0[1]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[0]),
        .Q(WrPtr[0]),
        .R(\FifoCntrRd_reg[2]_0 ));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[1]),
        .Q(WrPtr[1]),
        .R(\FifoCntrRd_reg[2]_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \dat_fifo_hd_nn1[0]_i_1__0 
       (.I0(Q[0]),
        .I1(\dat_fifo_hd_nn1[9]_i_2_n_0 ),
        .I2(dat_fifo_hd_nn1[0]),
        .I3(ctl_run_re),
        .O(\dat_fifo_hd_nxt_nn1_reg[0] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \dat_fifo_hd_nn1[1]_i_1__0 
       (.I0(Q[1]),
        .I1(\dat_fifo_hd_nn1[9]_i_2_n_0 ),
        .I2(dat_fifo_hd_nn1[1]),
        .I3(ctl_run_re),
        .O(\dat_fifo_hd_nxt_nn1_reg[1] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \dat_fifo_hd_nn1[2]_i_1__0 
       (.I0(Q[2]),
        .I1(\dat_fifo_hd_nn1[9]_i_2_n_0 ),
        .I2(dat_fifo_hd_nn1[2]),
        .I3(ctl_run_re),
        .O(\dat_fifo_hd_nxt_nn1_reg[2] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \dat_fifo_hd_nn1[3]_i_1__0 
       (.I0(Q[3]),
        .I1(\dat_fifo_hd_nn1[9]_i_2_n_0 ),
        .I2(dat_fifo_hd_nn1[3]),
        .I3(ctl_run_re),
        .O(\dat_fifo_hd_nxt_nn1_reg[3] ));
  LUT4 #(
    .INIT(16'hFEAE)) 
    \dat_fifo_hd_nn1[4]_i_1 
       (.I0(ctl_run_re),
        .I1(Q[4]),
        .I2(\dat_fifo_hd_nn1[9]_i_2_n_0 ),
        .I3(dat_fifo_hd_nn1[4]),
        .O(ctl_rst_nn1_reg));
  LUT4 #(
    .INIT(16'hFEAE)) 
    \dat_fifo_hd_nn1[5]_i_1 
       (.I0(ctl_run_re),
        .I1(Q[5]),
        .I2(\dat_fifo_hd_nn1[9]_i_2_n_0 ),
        .I3(dat_fifo_hd_nn1[5]),
        .O(ctl_rst_nn1_reg_0));
  LUT4 #(
    .INIT(16'hFEAE)) 
    \dat_fifo_hd_nn1[6]_i_1 
       (.I0(ctl_run_re),
        .I1(Q[6]),
        .I2(\dat_fifo_hd_nn1[9]_i_2_n_0 ),
        .I3(dat_fifo_hd_nn1[6]),
        .O(ctl_rst_nn1_reg_1));
  LUT4 #(
    .INIT(16'hFEAE)) 
    \dat_fifo_hd_nn1[7]_i_1 
       (.I0(ctl_run_re),
        .I1(Q[7]),
        .I2(\dat_fifo_hd_nn1[9]_i_2_n_0 ),
        .I3(dat_fifo_hd_nn1[7]),
        .O(ctl_rst_nn1_reg_2));
  LUT4 #(
    .INIT(16'hFEAE)) 
    \dat_fifo_hd_nn1[8]_i_1 
       (.I0(ctl_run_re),
        .I1(Q[8]),
        .I2(\dat_fifo_hd_nn1[9]_i_2_n_0 ),
        .I3(dat_fifo_hd_nn1[8]),
        .O(ctl_rst_nn1_reg_3));
  LUT6 #(
    .INIT(64'h00000000000022F2)) 
    \dat_fifo_hd_nn1[9]_i_1__0 
       (.I0(Q[9]),
        .I1(\dat_fifo_hd_nn1[9]_i_2_n_0 ),
        .I2(dat_fifo_hd_nn1[9]),
        .I3(rrq_ld_90022_out),
        .I4(ctl_run_re),
        .I5(\dat_fifo_hd_nn1_reg[9] ),
        .O(D));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF7FF)) 
    \dat_fifo_hd_nn1[9]_i_2 
       (.I0(rrq_ld_901_reg_rep__5),
        .I1(\rrq_sm_cur_900_reg[3]_0 [2]),
        .I2(full_ff_reg_n_0),
        .I3(rrq_vld_903),
        .I4(\rrq_sm_cur_900_reg[3]_0 [0]),
        .I5(\rrq_sm_cur_900_reg[3]_0 [1]),
        .O(\dat_fifo_hd_nn1[9]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0100)) 
    empty_ff_i_1__2
       (.I0(FifoCntrRd[1]),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[2]),
        .I3(empty_ff_reg_1),
        .I4(empty_ff_i_2__2_n_0),
        .O(empty_ff_i_1__2_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAAEF)) 
    empty_ff_i_2__2
       (.I0(\dat_fifo_hd_nn1_reg[9] ),
        .I1(empty_ff_reg_0),
        .I2(FifoCntrRd[0]),
        .I3(FifoCntrRd[1]),
        .I4(FifoCntrRd[2]),
        .I5(cfg_linkdown_nn1),
        .O(empty_ff_i_2__2_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__2_n_0),
        .Q(empty_ff_reg_1),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFF801180)) 
    full_ff_i_1__1
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(rrq_vld_903),
        .I3(FifoCntrWr[2]),
        .I4(full_ff_reg_n_0),
        .O(full_ff_i_1__1_n_0));
  FDRE full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(full_ff_i_1__1_n_0),
        .Q(full_ff_reg_n_0),
        .R(\FifoCntrRd_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair884" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    rrq_dsc_ld_901_i_3
       (.I0(\rrq_sm_cur_900_reg[3]_0 [1]),
        .I1(rrq_vld_903),
        .I2(full_ff_reg_n_0),
        .I3(\rrq_sm_cur_900_reg[3]_0 [2]),
        .O(\rrq_sm_cur_900_reg[2] ));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    rrq_ld_901_i_1
       (.I0(\rrq_sm_cur_900_reg[3]_0 [0]),
        .I1(rrq_ld_901_reg_rep__5),
        .I2(\rrq_sm_cur_900_reg[3]_0 [2]),
        .I3(full_ff_reg_n_0),
        .I4(rrq_vld_903),
        .I5(\rrq_sm_cur_900_reg[3]_0 [1]),
        .O(rrq_ld_90022_out));
  LUT6 #(
    .INIT(64'h0000000000100000)) 
    \rrq_sm_cur_900[3]_i_1 
       (.I0(reg_sts_hlt_nn1),
        .I1(ctl_rst),
        .I2(\rrq_sm_cur_900_reg[3] ),
        .I3(\rrq_sm_cur_900_reg[3]_0 [3]),
        .I4(\rrq_sm_cur_900_reg[3]_1 ),
        .I5(\rrq_sm_cur_900_reg[3]_2 ),
        .O(\rrq_sm_cur_900_reg[2]_0 [0]));
  LUT6 #(
    .INIT(64'h000202020002A2A2)) 
    \rrq_sm_cur_900[4]_i_1 
       (.I0(\rrq_sm_cur_900_reg[4] ),
        .I1(\rrq_sm_cur_900_reg[3] ),
        .I2(\rrq_sm_cur_900_reg[3]_0 [1]),
        .I3(rrq_eod_903),
        .I4(dsc_ep_nn0),
        .I5(\rrq_sm_cur_900_reg[3]_0 [2]),
        .O(\rrq_sm_cur_900_reg[2]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair884" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \rrq_sm_cur_900[4]_i_3 
       (.I0(\rrq_sm_cur_900_reg[3]_0 [2]),
        .I1(full_ff_reg_n_0),
        .I2(rrq_vld_903),
        .O(\rrq_sm_cur_900_reg[3] ));
  LUT4 #(
    .INIT(16'h0002)) 
    rrq_vld_903_i_1
       (.I0(\rrq_sm_cur_900_reg[2]_0 [0]),
        .I1(rrq_vld_903_reg[1]),
        .I2(rrq_vld_903_i_2_n_0),
        .I3(rrq_vld_903_reg[0]),
        .O(rrq_vld_902));
  LUT5 #(
    .INIT(32'hFFFFFFFD)) 
    rrq_vld_903_i_2
       (.I0(rrq_dsc_vld_902),
        .I1(rrq_stall_902),
        .I2(full_ff_reg_n_0),
        .I3(rrq_dsc_rem0_902),
        .I4(rrq_fl_nn1),
        .O(rrq_vld_903_i_2_n_0));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOHead" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOHead__parameterized1_44
   (empty_ff_reg_0,
    \dat_fifo_hd_nxt_nn1_reg[4] ,
    rrq_ld_9008_out,
    \dat_fifo_hd_nxt_nn1_reg[5] ,
    \dat_fifo_hd_nxt_nn1_reg[6] ,
    \dat_fifo_hd_nxt_nn1_reg[7] ,
    \dat_fifo_hd_nxt_nn1_reg[8] ,
    full_ff_reg_0,
    full_ff_reg_1,
    \pcie_h2c_rst_3ff_reg[0]_rep__4 ,
    empty_ff_reg_1,
    empty_ff_reg_2,
    payloadmuxed_0,
    empty_ff_reg_3,
    D,
    rrq_vld_902,
    \dat_fifo_hd_nxt_nn1_reg[9] ,
    \Head_reg[119]_0 ,
    \FifoCntrRd_reg[1]_0 ,
    \FifoCntrWr_reg[0]_0 ,
    \dat_fifo_hd_out_nn1_reg[0] ,
    cfg_linkdown_nn1,
    Q,
    \dat_fifo_hd_out_nn1_reg[0]_0 ,
    dat_fifo_hd_nn1,
    rrq_vld_903,
    \rrq_sm_cur_900_reg[2] ,
    \Head_reg[8]_0 ,
    almost_full_ff_2,
    arbhist_ff,
    \Head_reg[8]_1 ,
    \rrq_sm_cur_900_reg[2]_0 ,
    \rrq_sm_cur_900_reg[2]_1 ,
    dsc_ep_nn0,
    rrq_eod_903,
    \rrq_sm_cur_900[2]_i_2_0 ,
    rrq_vld_903_reg,
    rrq_ld_901_reg_rep__5,
    ctl_rst,
    reg_sts_hlt_nn1,
    \rrq_sm_cur_900_reg[3] ,
    \rrq_sm_cur_900_reg[3]_0 ,
    rrq_dsc_rem0_902,
    rrq_stall_902,
    rrq_fl_nn1,
    rrq_dsc_vld_902,
    Head0_4,
    \Head_reg[119]_1 ,
    Head1__2_5,
    \FifoCntrRd_reg[1]_1 ,
    \FifoCntrWr_reg[1]_0 ,
    user_clk,
    out,
    DataIn,
    \Head_reg[50]_0 ,
    \Head_reg[57]_0 );
  output empty_ff_reg_0;
  output \dat_fifo_hd_nxt_nn1_reg[4] ;
  output rrq_ld_9008_out;
  output \dat_fifo_hd_nxt_nn1_reg[5] ;
  output \dat_fifo_hd_nxt_nn1_reg[6] ;
  output \dat_fifo_hd_nxt_nn1_reg[7] ;
  output \dat_fifo_hd_nxt_nn1_reg[8] ;
  output full_ff_reg_0;
  output full_ff_reg_1;
  output \pcie_h2c_rst_3ff_reg[0]_rep__4 ;
  output empty_ff_reg_1;
  output empty_ff_reg_2;
  output [93:0]payloadmuxed_0;
  output empty_ff_reg_3;
  output [1:0]D;
  output rrq_vld_902;
  output [4:0]\dat_fifo_hd_nxt_nn1_reg[9] ;
  output [91:0]\Head_reg[119]_0 ;
  output [0:0]\FifoCntrRd_reg[1]_0 ;
  output [0:0]\FifoCntrWr_reg[0]_0 ;
  input \dat_fifo_hd_out_nn1_reg[0] ;
  input cfg_linkdown_nn1;
  input [9:0]Q;
  input \dat_fifo_hd_out_nn1_reg[0]_0 ;
  input [9:0]dat_fifo_hd_nn1;
  input rrq_vld_903;
  input [6:0]\rrq_sm_cur_900_reg[2] ;
  input \Head_reg[8]_0 ;
  input almost_full_ff_2;
  input [0:0]arbhist_ff;
  input \Head_reg[8]_1 ;
  input \rrq_sm_cur_900_reg[2]_0 ;
  input \rrq_sm_cur_900_reg[2]_1 ;
  input dsc_ep_nn0;
  input rrq_eod_903;
  input \rrq_sm_cur_900[2]_i_2_0 ;
  input [0:0]rrq_vld_903_reg;
  input rrq_ld_901_reg_rep__5;
  input ctl_rst;
  input reg_sts_hlt_nn1;
  input \rrq_sm_cur_900_reg[3] ;
  input \rrq_sm_cur_900_reg[3]_0 ;
  input rrq_dsc_rem0_902;
  input rrq_stall_902;
  input rrq_fl_nn1;
  input rrq_dsc_vld_902;
  input [91:0]Head0_4;
  input [81:0]\Head_reg[119]_1 ;
  input Head1__2_5;
  input [1:0]\FifoCntrRd_reg[1]_1 ;
  input [1:0]\FifoCntrWr_reg[1]_0 ;
  input user_clk;
  input [9:0]out;
  input [74:0]DataIn;
  input [4:0]\Head_reg[50]_0 ;
  input [1:0]\Head_reg[57]_0 ;

  wire [1:0]D;
  wire [74:0]DataIn;
  wire [2:0]FifoCntrRd;
  wire \FifoCntrRd[0]_i_1__4_n_0 ;
  wire \FifoCntrRd[1]_i_1__4_n_0 ;
  wire \FifoCntrRd[2]_i_1__3_n_0 ;
  wire [0:0]\FifoCntrRd_reg[1]_0 ;
  wire [1:0]\FifoCntrRd_reg[1]_1 ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__4_n_0 ;
  wire \FifoCntrWr[1]_i_1__4_n_0 ;
  wire \FifoCntrWr[2]_i_1__4_n_0 ;
  wire [0:0]\FifoCntrWr_reg[0]_0 ;
  wire [1:0]\FifoCntrWr_reg[1]_0 ;
  wire [119:8]Head0;
  wire [91:0]Head0_4;
  wire Head1;
  wire Head1__2_5;
  wire \Head[119]_i_1__3_n_0 ;
  wire \Head[31]_i_1__2_n_0 ;
  wire \Head[51]_i_1__3_n_0 ;
  wire [91:0]\Head_reg[119]_0 ;
  wire [81:0]\Head_reg[119]_1 ;
  wire [4:0]\Head_reg[50]_0 ;
  wire [1:0]\Head_reg[57]_0 ;
  wire \Head_reg[8]_0 ;
  wire \Head_reg[8]_1 ;
  wire [9:0]Q;
  wire [1:0]RdPtr;
  wire [1:0]RdPtr__0;
  wire [1:0]WrPtr;
  wire [1:0]WrPtr__0;
  wire almost_full_ff_2;
  wire [0:0]arbhist_ff;
  wire cfg_linkdown_nn1;
  wire ctl_rst;
  wire [9:0]dat_fifo_hd_nn1;
  wire \dat_fifo_hd_nxt_nn1_reg[4] ;
  wire \dat_fifo_hd_nxt_nn1_reg[5] ;
  wire \dat_fifo_hd_nxt_nn1_reg[6] ;
  wire \dat_fifo_hd_nxt_nn1_reg[7] ;
  wire \dat_fifo_hd_nxt_nn1_reg[8] ;
  wire [4:0]\dat_fifo_hd_nxt_nn1_reg[9] ;
  wire \dat_fifo_hd_out_nn1_reg[0] ;
  wire \dat_fifo_hd_out_nn1_reg[0]_0 ;
  wire dsc_ep_nn0;
  wire empty_ff_i_1__5_n_0;
  wire empty_ff_i_2__3_n_0;
  wire empty_ff_reg_0;
  wire empty_ff_reg_1;
  wire empty_ff_reg_2;
  wire empty_ff_reg_3;
  wire full_ff_i_1__3_n_0;
  wire full_ff_reg_0;
  wire full_ff_reg_1;
  wire [63:0]\h2c_xdma_rrq_req[0][adr] ;
  wire [13:0]\h2c_xdma_rrq_req[0][byte_len] ;
  wire [9:0]\h2c_xdma_rrq_req[0][did] ;
  wire [5:0]\h2c_xdma_rrq_req[0][rid] ;
  wire [9:0]out;
  wire [119:8]p_0_in1_in;
  wire [93:0]payloadmuxed_0;
  wire \pcie_h2c_rst_3ff_reg[0]_rep__4 ;
  wire reg_sts_hlt_nn1;
  wire rrq_dsc_rem0_902;
  wire rrq_dsc_vld_902;
  wire rrq_eod_903;
  wire rrq_fl_nn1;
  wire rrq_ld_9008_out;
  wire rrq_ld_901_reg_rep__5;
  wire \rrq_sm_cur_900[2]_i_2_0 ;
  wire \rrq_sm_cur_900[2]_i_2_n_0 ;
  wire \rrq_sm_cur_900[2]_i_4_n_0 ;
  wire [6:0]\rrq_sm_cur_900_reg[2] ;
  wire \rrq_sm_cur_900_reg[2]_0 ;
  wire \rrq_sm_cur_900_reg[2]_1 ;
  wire \rrq_sm_cur_900_reg[3] ;
  wire \rrq_sm_cur_900_reg[3]_0 ;
  wire rrq_stall_902;
  wire rrq_vld_902;
  wire rrq_vld_903;
  wire rrq_vld_903_i_2__0_n_0;
  wire [0:0]rrq_vld_903_reg;
  wire user_clk;
  wire [1:0]NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair595" *) 
  LUT3 #(
    .INIT(8'h96)) 
    \FifoCntrRd[0]_i_1__4 
       (.I0(rrq_vld_903),
        .I1(empty_ff_reg_0),
        .I2(FifoCntrRd[0]),
        .O(\FifoCntrRd[0]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair546" *) 
  LUT4 #(
    .INIT(16'hE718)) 
    \FifoCntrRd[1]_i_1__4 
       (.I0(FifoCntrRd[0]),
        .I1(rrq_vld_903),
        .I2(empty_ff_reg_0),
        .I3(FifoCntrRd[1]),
        .O(\FifoCntrRd[1]_i_1__4_n_0 ));
  LUT4 #(
    .INIT(16'h1EE1)) 
    \FifoCntrRd[1]_i_1__8 
       (.I0(empty_ff_reg_0),
        .I1(empty_ff_reg_3),
        .I2(\FifoCntrRd_reg[1]_1 [1]),
        .I3(\FifoCntrRd_reg[1]_1 [0]),
        .O(\FifoCntrRd_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair546" *) 
  LUT5 #(
    .INIT(32'hFE7F0180)) 
    \FifoCntrRd[2]_i_1__3 
       (.I0(FifoCntrRd[0]),
        .I1(FifoCntrRd[1]),
        .I2(rrq_vld_903),
        .I3(empty_ff_reg_0),
        .I4(FifoCntrRd[2]),
        .O(\FifoCntrRd[2]_i_1__3_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FifoCntrRd[2]_i_1__5 
       (.I0(\dat_fifo_hd_out_nn1_reg[0] ),
        .I1(cfg_linkdown_nn1),
        .O(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  LUT4 #(
    .INIT(16'h0405)) 
    \FifoCntrRd[2]_i_2__11 
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(almost_full_ff_2),
        .I3(arbhist_ff),
        .O(empty_ff_reg_0));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[0]_i_1__4_n_0 ),
        .Q(FifoCntrRd[0]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[1]_i_1__4_n_0 ),
        .Q(FifoCntrRd[1]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[2]_i_1__3_n_0 ),
        .Q(FifoCntrRd[2]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  (* SOFT_HLUTNM = "soft_lutpair596" *) 
  LUT3 #(
    .INIT(8'h96)) 
    \FifoCntrWr[0]_i_1__4 
       (.I0(empty_ff_reg_1),
        .I1(rrq_vld_903),
        .I2(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair547" *) 
  LUT4 #(
    .INIT(16'hDB24)) 
    \FifoCntrWr[1]_i_1__4 
       (.I0(FifoCntrWr[0]),
        .I1(empty_ff_reg_1),
        .I2(rrq_vld_903),
        .I3(FifoCntrWr[1]),
        .O(\FifoCntrWr[1]_i_1__4_n_0 ));
  LUT4 #(
    .INIT(16'h1EE1)) 
    \FifoCntrWr[1]_i_1__9 
       (.I0(empty_ff_reg_0),
        .I1(empty_ff_reg_3),
        .I2(\FifoCntrWr_reg[1]_0 [0]),
        .I3(\FifoCntrWr_reg[1]_0 [1]),
        .O(\FifoCntrWr_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair547" *) 
  LUT5 #(
    .INIT(32'hF7EF0810)) 
    \FifoCntrWr[2]_i_1__4 
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(empty_ff_reg_1),
        .I3(rrq_vld_903),
        .I4(FifoCntrWr[2]),
        .O(\FifoCntrWr[2]_i_1__4_n_0 ));
  LUT4 #(
    .INIT(16'h0405)) 
    \FifoCntrWr[2]_i_2 
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(almost_full_ff_2),
        .I3(arbhist_ff),
        .O(empty_ff_reg_1));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[0]_i_1__4_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[1]_i_1__4_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[2]_i_1__4_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  (* SOFT_HLUTNM = "soft_lutpair585" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[100]_i_1__5 
       (.I0(DataIn[55]),
        .I1(Head0[100]),
        .I2(Head1),
        .O(p_0_in1_in[100]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[100]_i_1__6 
       (.I0(Head0_4[72]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [44]),
        .I3(\Head_reg[119]_1 [62]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [72]));
  (* SOFT_HLUTNM = "soft_lutpair585" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[101]_i_1__5 
       (.I0(DataIn[56]),
        .I1(Head0[101]),
        .I2(Head1),
        .O(p_0_in1_in[101]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[101]_i_1__6 
       (.I0(Head0_4[73]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [45]),
        .I3(\Head_reg[119]_1 [63]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [73]));
  (* SOFT_HLUTNM = "soft_lutpair586" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[102]_i_1__5 
       (.I0(DataIn[57]),
        .I1(Head0[102]),
        .I2(Head1),
        .O(p_0_in1_in[102]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[102]_i_1__6 
       (.I0(Head0_4[74]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [46]),
        .I3(\Head_reg[119]_1 [64]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [74]));
  (* SOFT_HLUTNM = "soft_lutpair586" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[103]_i_1__5 
       (.I0(DataIn[58]),
        .I1(Head0[103]),
        .I2(Head1),
        .O(p_0_in1_in[103]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[103]_i_1__6 
       (.I0(Head0_4[75]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [47]),
        .I3(\Head_reg[119]_1 [65]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [75]));
  (* SOFT_HLUTNM = "soft_lutpair587" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[104]_i_1__5 
       (.I0(DataIn[59]),
        .I1(Head0[104]),
        .I2(Head1),
        .O(p_0_in1_in[104]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[104]_i_1__6 
       (.I0(Head0_4[76]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [48]),
        .I3(\Head_reg[119]_1 [66]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [76]));
  (* SOFT_HLUTNM = "soft_lutpair587" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[105]_i_1__5 
       (.I0(DataIn[60]),
        .I1(Head0[105]),
        .I2(Head1),
        .O(p_0_in1_in[105]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[105]_i_1__6 
       (.I0(Head0_4[77]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [49]),
        .I3(\Head_reg[119]_1 [67]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [77]));
  (* SOFT_HLUTNM = "soft_lutpair588" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[106]_i_1__5 
       (.I0(DataIn[61]),
        .I1(Head0[106]),
        .I2(Head1),
        .O(p_0_in1_in[106]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[106]_i_1__6 
       (.I0(Head0_4[78]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [50]),
        .I3(\Head_reg[119]_1 [68]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [78]));
  (* SOFT_HLUTNM = "soft_lutpair588" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[107]_i_1__5 
       (.I0(DataIn[62]),
        .I1(Head0[107]),
        .I2(Head1),
        .O(p_0_in1_in[107]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[107]_i_1__6 
       (.I0(Head0_4[79]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [51]),
        .I3(\Head_reg[119]_1 [69]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [79]));
  (* SOFT_HLUTNM = "soft_lutpair589" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[108]_i_1__5 
       (.I0(DataIn[63]),
        .I1(Head0[108]),
        .I2(Head1),
        .O(p_0_in1_in[108]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[108]_i_1__6 
       (.I0(Head0_4[80]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [52]),
        .I3(\Head_reg[119]_1 [70]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [80]));
  (* SOFT_HLUTNM = "soft_lutpair589" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[109]_i_1__5 
       (.I0(DataIn[64]),
        .I1(Head0[109]),
        .I2(Head1),
        .O(p_0_in1_in[109]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[109]_i_1__6 
       (.I0(Head0_4[81]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [53]),
        .I3(\Head_reg[119]_1 [71]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [81]));
  (* SOFT_HLUTNM = "soft_lutpair550" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[10]_i_1__4 
       (.I0(out[2]),
        .I1(Head0[10]),
        .I2(Head1),
        .O(p_0_in1_in[10]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[10]_i_1__6 
       (.I0(Head0_4[2]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][did] [2]),
        .I3(\Head_reg[119]_1 [2]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair590" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[110]_i_1__5 
       (.I0(DataIn[65]),
        .I1(Head0[110]),
        .I2(Head1),
        .O(p_0_in1_in[110]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[110]_i_1__6 
       (.I0(Head0_4[82]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [54]),
        .I3(\Head_reg[119]_1 [72]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [82]));
  (* SOFT_HLUTNM = "soft_lutpair590" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[111]_i_1__4 
       (.I0(DataIn[66]),
        .I1(Head0[111]),
        .I2(Head1),
        .O(p_0_in1_in[111]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[111]_i_1__5 
       (.I0(Head0_4[83]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [55]),
        .I3(\Head_reg[119]_1 [73]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [83]));
  (* SOFT_HLUTNM = "soft_lutpair591" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[112]_i_1__3 
       (.I0(DataIn[67]),
        .I1(Head0[112]),
        .I2(Head1),
        .O(p_0_in1_in[112]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[112]_i_1__4 
       (.I0(Head0_4[84]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [56]),
        .I3(\Head_reg[119]_1 [74]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [84]));
  (* SOFT_HLUTNM = "soft_lutpair591" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[113]_i_1__3 
       (.I0(DataIn[68]),
        .I1(Head0[113]),
        .I2(Head1),
        .O(p_0_in1_in[113]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[113]_i_1__4 
       (.I0(Head0_4[85]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [57]),
        .I3(\Head_reg[119]_1 [75]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [85]));
  (* SOFT_HLUTNM = "soft_lutpair592" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[114]_i_1__3 
       (.I0(DataIn[69]),
        .I1(Head0[114]),
        .I2(Head1),
        .O(p_0_in1_in[114]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[114]_i_1__4 
       (.I0(Head0_4[86]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [58]),
        .I3(\Head_reg[119]_1 [76]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [86]));
  (* SOFT_HLUTNM = "soft_lutpair592" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[115]_i_1__3 
       (.I0(DataIn[70]),
        .I1(Head0[115]),
        .I2(Head1),
        .O(p_0_in1_in[115]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[115]_i_1__4 
       (.I0(Head0_4[87]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [59]),
        .I3(\Head_reg[119]_1 [77]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [87]));
  (* SOFT_HLUTNM = "soft_lutpair593" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[116]_i_1__3 
       (.I0(DataIn[71]),
        .I1(Head0[116]),
        .I2(Head1),
        .O(p_0_in1_in[116]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[116]_i_1__4 
       (.I0(Head0_4[88]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [60]),
        .I3(\Head_reg[119]_1 [78]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [88]));
  (* SOFT_HLUTNM = "soft_lutpair593" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[117]_i_1__3 
       (.I0(DataIn[72]),
        .I1(Head0[117]),
        .I2(Head1),
        .O(p_0_in1_in[117]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[117]_i_1__4 
       (.I0(Head0_4[89]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [61]),
        .I3(\Head_reg[119]_1 [79]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [89]));
  (* SOFT_HLUTNM = "soft_lutpair594" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[118]_i_1__3 
       (.I0(DataIn[73]),
        .I1(Head0[118]),
        .I2(Head1),
        .O(p_0_in1_in[118]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[118]_i_1__4 
       (.I0(Head0_4[90]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [62]),
        .I3(\Head_reg[119]_1 [80]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [90]));
  LUT5 #(
    .INIT(32'hEEEEEEEF)) 
    \Head[119]_i_1__3 
       (.I0(Head1),
        .I1(empty_ff_reg_0),
        .I2(FifoCntrRd[2]),
        .I3(FifoCntrRd[1]),
        .I4(FifoCntrRd[0]),
        .O(\Head[119]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[119]_i_1__4 
       (.I0(Head0_4[91]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [63]),
        .I3(\Head_reg[119]_1 [81]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [91]));
  (* SOFT_HLUTNM = "soft_lutpair594" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[119]_i_2__1 
       (.I0(DataIn[74]),
        .I1(Head0[119]),
        .I2(Head1),
        .O(p_0_in1_in[119]));
  (* SOFT_HLUTNM = "soft_lutpair550" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[11]_i_1__4 
       (.I0(out[3]),
        .I1(Head0[11]),
        .I2(Head1),
        .O(p_0_in1_in[11]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[11]_i_1__6 
       (.I0(Head0_4[3]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][did] [3]),
        .I3(\Head_reg[119]_1 [3]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair551" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[12]_i_1__4 
       (.I0(out[4]),
        .I1(Head0[12]),
        .I2(Head1),
        .O(p_0_in1_in[12]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[12]_i_1__6 
       (.I0(Head0_4[4]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][did] [4]),
        .I3(\Head_reg[119]_1 [4]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair551" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[13]_i_1__4 
       (.I0(out[5]),
        .I1(Head0[13]),
        .I2(Head1),
        .O(p_0_in1_in[13]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[13]_i_1__6 
       (.I0(Head0_4[5]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][did] [5]),
        .I3(\Head_reg[119]_1 [5]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair552" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[14]_i_1__4 
       (.I0(out[6]),
        .I1(Head0[14]),
        .I2(Head1),
        .O(p_0_in1_in[14]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[14]_i_1__6 
       (.I0(Head0_4[6]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][did] [6]),
        .I3(\Head_reg[119]_1 [6]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair552" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[15]_i_1__4 
       (.I0(out[7]),
        .I1(Head0[15]),
        .I2(Head1),
        .O(p_0_in1_in[15]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[15]_i_1__6 
       (.I0(Head0_4[7]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][did] [7]),
        .I3(\Head_reg[119]_1 [7]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair553" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[16]_i_1__3 
       (.I0(out[8]),
        .I1(Head0[16]),
        .I2(Head1),
        .O(p_0_in1_in[16]));
  LUT4 #(
    .INIT(16'h8F80)) 
    \Head[16]_i_1__5 
       (.I0(\h2c_xdma_rrq_req[0][did] [8]),
        .I1(empty_ff_reg_0),
        .I2(Head1__2_5),
        .I3(Head0_4[8]),
        .O(\Head_reg[119]_0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair553" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[17]_i_1__3 
       (.I0(out[9]),
        .I1(Head0[17]),
        .I2(Head1),
        .O(p_0_in1_in[17]));
  (* SOFT_HLUTNM = "soft_lutpair554" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[18]_i_1__4 
       (.I0(DataIn[0]),
        .I1(Head0[18]),
        .I2(Head1),
        .O(p_0_in1_in[18]));
  LUT4 #(
    .INIT(16'h8F80)) 
    \Head[18]_i_1__6 
       (.I0(\h2c_xdma_rrq_req[0][byte_len] [0]),
        .I1(empty_ff_reg_0),
        .I2(Head1__2_5),
        .I3(Head0_4[9]),
        .O(\Head_reg[119]_0 [9]));
  (* SOFT_HLUTNM = "soft_lutpair554" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[19]_i_1__4 
       (.I0(DataIn[1]),
        .I1(Head0[19]),
        .I2(Head1),
        .O(p_0_in1_in[19]));
  LUT4 #(
    .INIT(16'h8F80)) 
    \Head[19]_i_1__6 
       (.I0(\h2c_xdma_rrq_req[0][byte_len] [1]),
        .I1(empty_ff_reg_0),
        .I2(Head1__2_5),
        .I3(Head0_4[10]),
        .O(\Head_reg[119]_0 [10]));
  (* SOFT_HLUTNM = "soft_lutpair555" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[20]_i_1__5 
       (.I0(DataIn[2]),
        .I1(Head0[20]),
        .I2(Head1),
        .O(p_0_in1_in[20]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[20]_i_1__7 
       (.I0(Head0_4[11]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [2]),
        .I3(\Head_reg[119]_1 [8]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [11]));
  (* SOFT_HLUTNM = "soft_lutpair555" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[21]_i_1__5 
       (.I0(DataIn[3]),
        .I1(Head0[21]),
        .I2(Head1),
        .O(p_0_in1_in[21]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[21]_i_1__7 
       (.I0(Head0_4[12]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [3]),
        .I3(\Head_reg[119]_1 [9]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [12]));
  (* SOFT_HLUTNM = "soft_lutpair556" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[22]_i_1__3 
       (.I0(DataIn[4]),
        .I1(Head0[22]),
        .I2(Head1),
        .O(p_0_in1_in[22]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[22]_i_1__5 
       (.I0(Head0_4[13]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [4]),
        .I3(\Head_reg[119]_1 [10]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [13]));
  (* SOFT_HLUTNM = "soft_lutpair556" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[23]_i_1__3 
       (.I0(DataIn[5]),
        .I1(Head0[23]),
        .I2(Head1),
        .O(p_0_in1_in[23]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[23]_i_1__5 
       (.I0(Head0_4[14]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [5]),
        .I3(\Head_reg[119]_1 [11]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [14]));
  (* SOFT_HLUTNM = "soft_lutpair557" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[24]_i_1__3 
       (.I0(DataIn[6]),
        .I1(Head0[24]),
        .I2(Head1),
        .O(p_0_in1_in[24]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[24]_i_1__5 
       (.I0(Head0_4[15]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [6]),
        .I3(\Head_reg[119]_1 [12]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [15]));
  (* SOFT_HLUTNM = "soft_lutpair557" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[25]_i_1__3 
       (.I0(DataIn[7]),
        .I1(Head0[25]),
        .I2(Head1),
        .O(p_0_in1_in[25]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[25]_i_1__5 
       (.I0(Head0_4[16]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [7]),
        .I3(\Head_reg[119]_1 [13]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [16]));
  (* SOFT_HLUTNM = "soft_lutpair558" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[26]_i_1__3 
       (.I0(DataIn[8]),
        .I1(Head0[26]),
        .I2(Head1),
        .O(p_0_in1_in[26]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[26]_i_1__5 
       (.I0(Head0_4[17]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [8]),
        .I3(\Head_reg[119]_1 [14]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [17]));
  (* SOFT_HLUTNM = "soft_lutpair558" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[27]_i_1__3 
       (.I0(DataIn[9]),
        .I1(Head0[27]),
        .I2(Head1),
        .O(p_0_in1_in[27]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[27]_i_1__5 
       (.I0(Head0_4[18]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [9]),
        .I3(\Head_reg[119]_1 [15]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [18]));
  (* SOFT_HLUTNM = "soft_lutpair559" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[28]_i_1__3 
       (.I0(DataIn[10]),
        .I1(Head0[28]),
        .I2(Head1),
        .O(p_0_in1_in[28]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[28]_i_1__5 
       (.I0(Head0_4[19]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [10]),
        .I3(\Head_reg[119]_1 [16]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [19]));
  (* SOFT_HLUTNM = "soft_lutpair559" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[29]_i_1__3 
       (.I0(DataIn[11]),
        .I1(Head0[29]),
        .I2(Head1),
        .O(p_0_in1_in[29]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[29]_i_1__5 
       (.I0(Head0_4[20]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [11]),
        .I3(\Head_reg[119]_1 [17]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [20]));
  (* SOFT_HLUTNM = "soft_lutpair560" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[30]_i_1__2 
       (.I0(DataIn[12]),
        .I1(Head0[30]),
        .I2(Head1),
        .O(p_0_in1_in[30]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[30]_i_1__4 
       (.I0(Head0_4[21]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [12]),
        .I3(\Head_reg[119]_1 [18]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [21]));
  (* SOFT_HLUTNM = "soft_lutpair548" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[31]_i_1__2 
       (.I0(Head0[31]),
        .I1(Head1),
        .O(\Head[31]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair560" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[46]_i_1__2 
       (.I0(\Head_reg[50]_0 [0]),
        .I1(Head0[46]),
        .I2(Head1),
        .O(p_0_in1_in[46]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[46]_i_1__6 
       (.I0(Head0_4[22]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][rid] [0]),
        .I3(\Head_reg[119]_1 [20]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [22]));
  (* SOFT_HLUTNM = "soft_lutpair561" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[47]_i_1__3 
       (.I0(\Head_reg[50]_0 [1]),
        .I1(Head0[47]),
        .I2(Head1),
        .O(p_0_in1_in[47]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[47]_i_1__6 
       (.I0(Head0_4[23]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][rid] [1]),
        .I3(\Head_reg[119]_1 [21]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [23]));
  (* SOFT_HLUTNM = "soft_lutpair561" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[48]_i_1__3 
       (.I0(\Head_reg[50]_0 [2]),
        .I1(Head0[48]),
        .I2(Head1),
        .O(p_0_in1_in[48]));
  LUT4 #(
    .INIT(16'h8F80)) 
    \Head[48]_i_1__5 
       (.I0(\h2c_xdma_rrq_req[0][rid] [2]),
        .I1(empty_ff_reg_0),
        .I2(Head1__2_5),
        .I3(Head0_4[24]),
        .O(\Head_reg[119]_0 [24]));
  (* SOFT_HLUTNM = "soft_lutpair562" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[49]_i_1__3 
       (.I0(\Head_reg[50]_0 [3]),
        .I1(Head0[49]),
        .I2(Head1),
        .O(p_0_in1_in[49]));
  LUT4 #(
    .INIT(16'h8F80)) 
    \Head[49]_i_1__5 
       (.I0(\h2c_xdma_rrq_req[0][rid] [3]),
        .I1(empty_ff_reg_0),
        .I2(Head1__2_5),
        .I3(Head0_4[25]),
        .O(\Head_reg[119]_0 [25]));
  (* SOFT_HLUTNM = "soft_lutpair562" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[50]_i_1__3 
       (.I0(\Head_reg[50]_0 [4]),
        .I1(Head0[50]),
        .I2(Head1),
        .O(p_0_in1_in[50]));
  LUT4 #(
    .INIT(16'h8F80)) 
    \Head[50]_i_1__5 
       (.I0(\h2c_xdma_rrq_req[0][rid] [4]),
        .I1(empty_ff_reg_0),
        .I2(Head1__2_5),
        .I3(Head0_4[26]),
        .O(\Head_reg[119]_0 [26]));
  (* SOFT_HLUTNM = "soft_lutpair549" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[51]_i_1__3 
       (.I0(Head0[51]),
        .I1(Head1),
        .O(\Head[51]_i_1__3_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \Head[51]_i_1__5 
       (.I0(\h2c_xdma_rrq_req[0][rid] [5]),
        .I1(empty_ff_reg_0),
        .I2(Head1__2_5),
        .I3(Head0_4[27]),
        .O(\Head_reg[119]_0 [27]));
  (* SOFT_HLUTNM = "soft_lutpair563" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[56]_i_1__4 
       (.I0(\Head_reg[57]_0 [0]),
        .I1(Head0[56]),
        .I2(Head1),
        .O(p_0_in1_in[56]));
  LUT4 #(
    .INIT(16'h8F80)) 
    \Head[56]_i_1__6 
       (.I0(\h2c_xdma_rrq_req[0][adr] [0]),
        .I1(empty_ff_reg_0),
        .I2(Head1__2_5),
        .I3(Head0_4[28]),
        .O(\Head_reg[119]_0 [28]));
  (* SOFT_HLUTNM = "soft_lutpair563" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[57]_i_1__4 
       (.I0(\Head_reg[57]_0 [1]),
        .I1(Head0[57]),
        .I2(Head1),
        .O(p_0_in1_in[57]));
  LUT4 #(
    .INIT(16'h8F80)) 
    \Head[57]_i_1__6 
       (.I0(\h2c_xdma_rrq_req[0][adr] [1]),
        .I1(empty_ff_reg_0),
        .I2(Head1__2_5),
        .I3(Head0_4[29]),
        .O(\Head_reg[119]_0 [29]));
  (* SOFT_HLUTNM = "soft_lutpair564" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[58]_i_1__4 
       (.I0(DataIn[13]),
        .I1(Head0[58]),
        .I2(Head1),
        .O(p_0_in1_in[58]));
  LUT4 #(
    .INIT(16'h8F80)) 
    \Head[58]_i_1__6 
       (.I0(\h2c_xdma_rrq_req[0][adr] [2]),
        .I1(empty_ff_reg_0),
        .I2(Head1__2_5),
        .I3(Head0_4[30]),
        .O(\Head_reg[119]_0 [30]));
  (* SOFT_HLUTNM = "soft_lutpair564" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[59]_i_1__4 
       (.I0(DataIn[14]),
        .I1(Head0[59]),
        .I2(Head1),
        .O(p_0_in1_in[59]));
  LUT4 #(
    .INIT(16'h8F80)) 
    \Head[59]_i_1__6 
       (.I0(\h2c_xdma_rrq_req[0][adr] [3]),
        .I1(empty_ff_reg_0),
        .I2(Head1__2_5),
        .I3(Head0_4[31]),
        .O(\Head_reg[119]_0 [31]));
  (* SOFT_HLUTNM = "soft_lutpair565" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[60]_i_1__4 
       (.I0(DataIn[15]),
        .I1(Head0[60]),
        .I2(Head1),
        .O(p_0_in1_in[60]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[60]_i_1__7 
       (.I0(Head0_4[32]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [4]),
        .I3(\Head_reg[119]_1 [22]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [32]));
  (* SOFT_HLUTNM = "soft_lutpair565" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[61]_i_1__5 
       (.I0(DataIn[16]),
        .I1(Head0[61]),
        .I2(Head1),
        .O(p_0_in1_in[61]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[61]_i_1__7 
       (.I0(Head0_4[33]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [5]),
        .I3(\Head_reg[119]_1 [23]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [33]));
  (* SOFT_HLUTNM = "soft_lutpair566" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[62]_i_1__5 
       (.I0(DataIn[17]),
        .I1(Head0[62]),
        .I2(Head1),
        .O(p_0_in1_in[62]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[62]_i_1__7 
       (.I0(Head0_4[34]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [6]),
        .I3(\Head_reg[119]_1 [24]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [34]));
  (* SOFT_HLUTNM = "soft_lutpair566" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[63]_i_1__5 
       (.I0(DataIn[18]),
        .I1(Head0[63]),
        .I2(Head1),
        .O(p_0_in1_in[63]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[63]_i_1__6 
       (.I0(Head0_4[35]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [7]),
        .I3(\Head_reg[119]_1 [25]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [35]));
  (* SOFT_HLUTNM = "soft_lutpair567" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[64]_i_1__5 
       (.I0(DataIn[19]),
        .I1(Head0[64]),
        .I2(Head1),
        .O(p_0_in1_in[64]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[64]_i_1__6 
       (.I0(Head0_4[36]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [8]),
        .I3(\Head_reg[119]_1 [26]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [36]));
  (* SOFT_HLUTNM = "soft_lutpair567" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[65]_i_1__5 
       (.I0(DataIn[20]),
        .I1(Head0[65]),
        .I2(Head1),
        .O(p_0_in1_in[65]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[65]_i_1__6 
       (.I0(Head0_4[37]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [9]),
        .I3(\Head_reg[119]_1 [27]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [37]));
  (* SOFT_HLUTNM = "soft_lutpair568" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[66]_i_1__5 
       (.I0(DataIn[21]),
        .I1(Head0[66]),
        .I2(Head1),
        .O(p_0_in1_in[66]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[66]_i_1__7 
       (.I0(Head0_4[38]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [10]),
        .I3(\Head_reg[119]_1 [28]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [38]));
  (* SOFT_HLUTNM = "soft_lutpair568" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[67]_i_1__5 
       (.I0(DataIn[22]),
        .I1(Head0[67]),
        .I2(Head1),
        .O(p_0_in1_in[67]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[67]_i_1__7 
       (.I0(Head0_4[39]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [11]),
        .I3(\Head_reg[119]_1 [29]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [39]));
  (* SOFT_HLUTNM = "soft_lutpair569" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[68]_i_1__5 
       (.I0(DataIn[23]),
        .I1(Head0[68]),
        .I2(Head1),
        .O(p_0_in1_in[68]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[68]_i_1__7 
       (.I0(Head0_4[40]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [12]),
        .I3(\Head_reg[119]_1 [30]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [40]));
  (* SOFT_HLUTNM = "soft_lutpair569" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[69]_i_1__5 
       (.I0(DataIn[24]),
        .I1(Head0[69]),
        .I2(Head1),
        .O(p_0_in1_in[69]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[69]_i_1__7 
       (.I0(Head0_4[41]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [13]),
        .I3(\Head_reg[119]_1 [31]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [41]));
  (* SOFT_HLUTNM = "soft_lutpair570" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[70]_i_1__5 
       (.I0(DataIn[25]),
        .I1(Head0[70]),
        .I2(Head1),
        .O(p_0_in1_in[70]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[70]_i_1__7 
       (.I0(Head0_4[42]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [14]),
        .I3(\Head_reg[119]_1 [32]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [42]));
  (* SOFT_HLUTNM = "soft_lutpair570" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[71]_i_1__5 
       (.I0(DataIn[26]),
        .I1(Head0[71]),
        .I2(Head1),
        .O(p_0_in1_in[71]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[71]_i_1__7 
       (.I0(Head0_4[43]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [15]),
        .I3(\Head_reg[119]_1 [33]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [43]));
  (* SOFT_HLUTNM = "soft_lutpair571" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[72]_i_1__5 
       (.I0(DataIn[27]),
        .I1(Head0[72]),
        .I2(Head1),
        .O(p_0_in1_in[72]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[72]_i_1__7 
       (.I0(Head0_4[44]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [16]),
        .I3(\Head_reg[119]_1 [34]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [44]));
  (* SOFT_HLUTNM = "soft_lutpair571" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[73]_i_1__5 
       (.I0(DataIn[28]),
        .I1(Head0[73]),
        .I2(Head1),
        .O(p_0_in1_in[73]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[73]_i_1__7 
       (.I0(Head0_4[45]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [17]),
        .I3(\Head_reg[119]_1 [35]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [45]));
  (* SOFT_HLUTNM = "soft_lutpair572" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[74]_i_1__5 
       (.I0(DataIn[29]),
        .I1(Head0[74]),
        .I2(Head1),
        .O(p_0_in1_in[74]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[74]_i_1__6 
       (.I0(Head0_4[46]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [18]),
        .I3(\Head_reg[119]_1 [36]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [46]));
  (* SOFT_HLUTNM = "soft_lutpair572" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[75]_i_1__5 
       (.I0(DataIn[30]),
        .I1(Head0[75]),
        .I2(Head1),
        .O(p_0_in1_in[75]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[75]_i_1__6 
       (.I0(Head0_4[47]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [19]),
        .I3(\Head_reg[119]_1 [37]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [47]));
  (* SOFT_HLUTNM = "soft_lutpair573" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[76]_i_1__5 
       (.I0(DataIn[31]),
        .I1(Head0[76]),
        .I2(Head1),
        .O(p_0_in1_in[76]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[76]_i_1__6 
       (.I0(Head0_4[48]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [20]),
        .I3(\Head_reg[119]_1 [38]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [48]));
  (* SOFT_HLUTNM = "soft_lutpair573" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[77]_i_1__5 
       (.I0(DataIn[32]),
        .I1(Head0[77]),
        .I2(Head1),
        .O(p_0_in1_in[77]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[77]_i_1__6 
       (.I0(Head0_4[49]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [21]),
        .I3(\Head_reg[119]_1 [39]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [49]));
  (* SOFT_HLUTNM = "soft_lutpair574" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[78]_i_1__5 
       (.I0(DataIn[33]),
        .I1(Head0[78]),
        .I2(Head1),
        .O(p_0_in1_in[78]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[78]_i_1__6 
       (.I0(Head0_4[50]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [22]),
        .I3(\Head_reg[119]_1 [40]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [50]));
  (* SOFT_HLUTNM = "soft_lutpair574" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[79]_i_1__5 
       (.I0(DataIn[34]),
        .I1(Head0[79]),
        .I2(Head1),
        .O(p_0_in1_in[79]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[79]_i_1__6 
       (.I0(Head0_4[51]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [23]),
        .I3(\Head_reg[119]_1 [41]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [51]));
  (* SOFT_HLUTNM = "soft_lutpair575" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[80]_i_1__5 
       (.I0(DataIn[35]),
        .I1(Head0[80]),
        .I2(Head1),
        .O(p_0_in1_in[80]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[80]_i_1__6 
       (.I0(Head0_4[52]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [24]),
        .I3(\Head_reg[119]_1 [42]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [52]));
  (* SOFT_HLUTNM = "soft_lutpair575" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[81]_i_1__5 
       (.I0(DataIn[36]),
        .I1(Head0[81]),
        .I2(Head1),
        .O(p_0_in1_in[81]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[81]_i_1__6 
       (.I0(Head0_4[53]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [25]),
        .I3(\Head_reg[119]_1 [43]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [53]));
  (* SOFT_HLUTNM = "soft_lutpair576" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[82]_i_1__5 
       (.I0(DataIn[37]),
        .I1(Head0[82]),
        .I2(Head1),
        .O(p_0_in1_in[82]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[82]_i_1__6 
       (.I0(Head0_4[54]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [26]),
        .I3(\Head_reg[119]_1 [44]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [54]));
  (* SOFT_HLUTNM = "soft_lutpair576" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[83]_i_1__5 
       (.I0(DataIn[38]),
        .I1(Head0[83]),
        .I2(Head1),
        .O(p_0_in1_in[83]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[83]_i_1__6 
       (.I0(Head0_4[55]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [27]),
        .I3(\Head_reg[119]_1 [45]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [55]));
  (* SOFT_HLUTNM = "soft_lutpair577" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[84]_i_1__5 
       (.I0(DataIn[39]),
        .I1(Head0[84]),
        .I2(Head1),
        .O(p_0_in1_in[84]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[84]_i_1__6 
       (.I0(Head0_4[56]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [28]),
        .I3(\Head_reg[119]_1 [46]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [56]));
  (* SOFT_HLUTNM = "soft_lutpair577" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[85]_i_1__5 
       (.I0(DataIn[40]),
        .I1(Head0[85]),
        .I2(Head1),
        .O(p_0_in1_in[85]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[85]_i_1__6 
       (.I0(Head0_4[57]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [29]),
        .I3(\Head_reg[119]_1 [47]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [57]));
  (* SOFT_HLUTNM = "soft_lutpair578" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[86]_i_1__5 
       (.I0(DataIn[41]),
        .I1(Head0[86]),
        .I2(Head1),
        .O(p_0_in1_in[86]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[86]_i_1__6 
       (.I0(Head0_4[58]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [30]),
        .I3(\Head_reg[119]_1 [48]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [58]));
  (* SOFT_HLUTNM = "soft_lutpair578" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[87]_i_1__5 
       (.I0(DataIn[42]),
        .I1(Head0[87]),
        .I2(Head1),
        .O(p_0_in1_in[87]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[87]_i_1__6 
       (.I0(Head0_4[59]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [31]),
        .I3(\Head_reg[119]_1 [49]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [59]));
  (* SOFT_HLUTNM = "soft_lutpair579" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[88]_i_1__5 
       (.I0(DataIn[43]),
        .I1(Head0[88]),
        .I2(Head1),
        .O(p_0_in1_in[88]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[88]_i_1__6 
       (.I0(Head0_4[60]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [32]),
        .I3(\Head_reg[119]_1 [50]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [60]));
  (* SOFT_HLUTNM = "soft_lutpair579" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[89]_i_1__5 
       (.I0(DataIn[44]),
        .I1(Head0[89]),
        .I2(Head1),
        .O(p_0_in1_in[89]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[89]_i_1__6 
       (.I0(Head0_4[61]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [33]),
        .I3(\Head_reg[119]_1 [51]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [61]));
  (* SOFT_HLUTNM = "soft_lutpair548" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[8]_i_1__2 
       (.I0(out[0]),
        .I1(Head0[8]),
        .I2(Head1),
        .O(p_0_in1_in[8]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[8]_i_1__6 
       (.I0(Head0_4[0]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][did] [0]),
        .I3(\Head_reg[119]_1 [0]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair580" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[90]_i_1__5 
       (.I0(DataIn[45]),
        .I1(Head0[90]),
        .I2(Head1),
        .O(p_0_in1_in[90]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[90]_i_1__7 
       (.I0(Head0_4[62]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [34]),
        .I3(\Head_reg[119]_1 [52]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [62]));
  (* SOFT_HLUTNM = "soft_lutpair580" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[91]_i_1__5 
       (.I0(DataIn[46]),
        .I1(Head0[91]),
        .I2(Head1),
        .O(p_0_in1_in[91]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[91]_i_1__7 
       (.I0(Head0_4[63]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [35]),
        .I3(\Head_reg[119]_1 [53]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [63]));
  (* SOFT_HLUTNM = "soft_lutpair581" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[92]_i_1__5 
       (.I0(DataIn[47]),
        .I1(Head0[92]),
        .I2(Head1),
        .O(p_0_in1_in[92]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[92]_i_1__7 
       (.I0(Head0_4[64]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [36]),
        .I3(\Head_reg[119]_1 [54]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [64]));
  (* SOFT_HLUTNM = "soft_lutpair581" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[93]_i_1__5 
       (.I0(DataIn[48]),
        .I1(Head0[93]),
        .I2(Head1),
        .O(p_0_in1_in[93]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[93]_i_1__7 
       (.I0(Head0_4[65]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [37]),
        .I3(\Head_reg[119]_1 [55]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [65]));
  (* SOFT_HLUTNM = "soft_lutpair582" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[94]_i_1__5 
       (.I0(DataIn[49]),
        .I1(Head0[94]),
        .I2(Head1),
        .O(p_0_in1_in[94]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[94]_i_1__6 
       (.I0(Head0_4[66]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [38]),
        .I3(\Head_reg[119]_1 [56]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [66]));
  (* SOFT_HLUTNM = "soft_lutpair582" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[95]_i_1__5 
       (.I0(DataIn[50]),
        .I1(Head0[95]),
        .I2(Head1),
        .O(p_0_in1_in[95]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[95]_i_1__6 
       (.I0(Head0_4[67]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [39]),
        .I3(\Head_reg[119]_1 [57]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [67]));
  (* SOFT_HLUTNM = "soft_lutpair583" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[96]_i_1__5 
       (.I0(DataIn[51]),
        .I1(Head0[96]),
        .I2(Head1),
        .O(p_0_in1_in[96]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[96]_i_1__6 
       (.I0(Head0_4[68]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [40]),
        .I3(\Head_reg[119]_1 [58]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [68]));
  (* SOFT_HLUTNM = "soft_lutpair583" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[97]_i_1__5 
       (.I0(DataIn[52]),
        .I1(Head0[97]),
        .I2(Head1),
        .O(p_0_in1_in[97]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[97]_i_1__6 
       (.I0(Head0_4[69]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [41]),
        .I3(\Head_reg[119]_1 [59]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [69]));
  (* SOFT_HLUTNM = "soft_lutpair584" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[98]_i_1__5 
       (.I0(DataIn[53]),
        .I1(Head0[98]),
        .I2(Head1),
        .O(p_0_in1_in[98]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[98]_i_1__6 
       (.I0(Head0_4[70]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [42]),
        .I3(\Head_reg[119]_1 [60]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [70]));
  (* SOFT_HLUTNM = "soft_lutpair584" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[99]_i_1__5 
       (.I0(DataIn[54]),
        .I1(Head0[99]),
        .I2(Head1),
        .O(p_0_in1_in[99]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[99]_i_1__6 
       (.I0(Head0_4[71]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][adr] [43]),
        .I3(\Head_reg[119]_1 [61]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [71]));
  (* SOFT_HLUTNM = "soft_lutpair549" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[9]_i_1__4 
       (.I0(out[1]),
        .I1(Head0[9]),
        .I2(Head1),
        .O(p_0_in1_in[9]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[9]_i_1__6 
       (.I0(Head0_4[1]),
        .I1(empty_ff_reg_0),
        .I2(\h2c_xdma_rrq_req[0][did] [1]),
        .I3(\Head_reg[119]_1 [1]),
        .I4(Head1__2_5),
        .I5(empty_ff_reg_3),
        .O(\Head_reg[119]_0 [1]));
  FDRE \Head_reg[100] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[100]),
        .Q(\h2c_xdma_rrq_req[0][adr] [44]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[101] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[101]),
        .Q(\h2c_xdma_rrq_req[0][adr] [45]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[102] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[102]),
        .Q(\h2c_xdma_rrq_req[0][adr] [46]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[103] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[103]),
        .Q(\h2c_xdma_rrq_req[0][adr] [47]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[104] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[104]),
        .Q(\h2c_xdma_rrq_req[0][adr] [48]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[105] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[105]),
        .Q(\h2c_xdma_rrq_req[0][adr] [49]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[106] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[106]),
        .Q(\h2c_xdma_rrq_req[0][adr] [50]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[107] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[107]),
        .Q(\h2c_xdma_rrq_req[0][adr] [51]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[108] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[108]),
        .Q(\h2c_xdma_rrq_req[0][adr] [52]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[109] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[109]),
        .Q(\h2c_xdma_rrq_req[0][adr] [53]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[10]),
        .Q(\h2c_xdma_rrq_req[0][did] [2]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[110] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[110]),
        .Q(\h2c_xdma_rrq_req[0][adr] [54]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[111] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[111]),
        .Q(\h2c_xdma_rrq_req[0][adr] [55]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[112] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[112]),
        .Q(\h2c_xdma_rrq_req[0][adr] [56]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[113] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[113]),
        .Q(\h2c_xdma_rrq_req[0][adr] [57]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[114] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[114]),
        .Q(\h2c_xdma_rrq_req[0][adr] [58]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[115] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[115]),
        .Q(\h2c_xdma_rrq_req[0][adr] [59]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[116] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[116]),
        .Q(\h2c_xdma_rrq_req[0][adr] [60]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[117] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[117]),
        .Q(\h2c_xdma_rrq_req[0][adr] [61]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[118] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[118]),
        .Q(\h2c_xdma_rrq_req[0][adr] [62]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[119] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[119]),
        .Q(\h2c_xdma_rrq_req[0][adr] [63]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[11]),
        .Q(\h2c_xdma_rrq_req[0][did] [3]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[12]),
        .Q(\h2c_xdma_rrq_req[0][did] [4]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[13]),
        .Q(\h2c_xdma_rrq_req[0][did] [5]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[14]),
        .Q(\h2c_xdma_rrq_req[0][did] [6]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[15]),
        .Q(\h2c_xdma_rrq_req[0][did] [7]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[16] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[16]),
        .Q(\h2c_xdma_rrq_req[0][did] [8]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[17] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[17]),
        .Q(\h2c_xdma_rrq_req[0][did] [9]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[18]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [0]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[19]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [1]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[20]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [2]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[21]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [3]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[22] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[22]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [4]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[23] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[23]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [5]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[24] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[24]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [6]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[25] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[25]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [7]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[26] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[26]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [8]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[27] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[27]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [9]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[28] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[28]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [10]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[29] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[29]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [11]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[30] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[30]),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [12]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[31] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(\Head[31]_i_1__2_n_0 ),
        .Q(\h2c_xdma_rrq_req[0][byte_len] [13]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[46] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[46]),
        .Q(\h2c_xdma_rrq_req[0][rid] [0]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[47] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[47]),
        .Q(\h2c_xdma_rrq_req[0][rid] [1]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[48] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[48]),
        .Q(\h2c_xdma_rrq_req[0][rid] [2]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[49] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[49]),
        .Q(\h2c_xdma_rrq_req[0][rid] [3]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[50] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[50]),
        .Q(\h2c_xdma_rrq_req[0][rid] [4]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[51] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(\Head[51]_i_1__3_n_0 ),
        .Q(\h2c_xdma_rrq_req[0][rid] [5]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[56] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[56]),
        .Q(\h2c_xdma_rrq_req[0][adr] [0]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[57] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[57]),
        .Q(\h2c_xdma_rrq_req[0][adr] [1]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[58] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[58]),
        .Q(\h2c_xdma_rrq_req[0][adr] [2]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[59] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[59]),
        .Q(\h2c_xdma_rrq_req[0][adr] [3]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[60]),
        .Q(\h2c_xdma_rrq_req[0][adr] [4]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[61]),
        .Q(\h2c_xdma_rrq_req[0][adr] [5]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[62]),
        .Q(\h2c_xdma_rrq_req[0][adr] [6]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[63]),
        .Q(\h2c_xdma_rrq_req[0][adr] [7]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[64] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[64]),
        .Q(\h2c_xdma_rrq_req[0][adr] [8]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[65] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[65]),
        .Q(\h2c_xdma_rrq_req[0][adr] [9]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[66]),
        .Q(\h2c_xdma_rrq_req[0][adr] [10]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[67]),
        .Q(\h2c_xdma_rrq_req[0][adr] [11]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[68]),
        .Q(\h2c_xdma_rrq_req[0][adr] [12]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[69]),
        .Q(\h2c_xdma_rrq_req[0][adr] [13]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[70]),
        .Q(\h2c_xdma_rrq_req[0][adr] [14]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[71]),
        .Q(\h2c_xdma_rrq_req[0][adr] [15]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[72]),
        .Q(\h2c_xdma_rrq_req[0][adr] [16]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[73]),
        .Q(\h2c_xdma_rrq_req[0][adr] [17]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[74] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[74]),
        .Q(\h2c_xdma_rrq_req[0][adr] [18]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[75] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[75]),
        .Q(\h2c_xdma_rrq_req[0][adr] [19]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[76] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[76]),
        .Q(\h2c_xdma_rrq_req[0][adr] [20]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[77] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[77]),
        .Q(\h2c_xdma_rrq_req[0][adr] [21]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[78] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[78]),
        .Q(\h2c_xdma_rrq_req[0][adr] [22]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[79] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[79]),
        .Q(\h2c_xdma_rrq_req[0][adr] [23]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[80] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[80]),
        .Q(\h2c_xdma_rrq_req[0][adr] [24]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[81] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[81]),
        .Q(\h2c_xdma_rrq_req[0][adr] [25]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[82] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[82]),
        .Q(\h2c_xdma_rrq_req[0][adr] [26]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[83] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[83]),
        .Q(\h2c_xdma_rrq_req[0][adr] [27]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[84] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[84]),
        .Q(\h2c_xdma_rrq_req[0][adr] [28]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[85] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[85]),
        .Q(\h2c_xdma_rrq_req[0][adr] [29]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[86] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[86]),
        .Q(\h2c_xdma_rrq_req[0][adr] [30]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[87] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[87]),
        .Q(\h2c_xdma_rrq_req[0][adr] [31]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[88] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[88]),
        .Q(\h2c_xdma_rrq_req[0][adr] [32]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[89] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[89]),
        .Q(\h2c_xdma_rrq_req[0][adr] [33]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[8] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[8]),
        .Q(\h2c_xdma_rrq_req[0][did] [0]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[90]),
        .Q(\h2c_xdma_rrq_req[0][adr] [34]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[91]),
        .Q(\h2c_xdma_rrq_req[0][adr] [35]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[92]),
        .Q(\h2c_xdma_rrq_req[0][adr] [36]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[93]),
        .Q(\h2c_xdma_rrq_req[0][adr] [37]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[94] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[94]),
        .Q(\h2c_xdma_rrq_req[0][adr] [38]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[95] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[95]),
        .Q(\h2c_xdma_rrq_req[0][adr] [39]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[96] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[96]),
        .Q(\h2c_xdma_rrq_req[0][adr] [40]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[97] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[97]),
        .Q(\h2c_xdma_rrq_req[0][adr] [41]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[98] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[98]),
        .Q(\h2c_xdma_rrq_req[0][adr] [42]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[99] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[99]),
        .Q(\h2c_xdma_rrq_req[0][adr] [43]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[9] 
       (.C(user_clk),
        .CE(\Head[119]_i_1__3_n_0 ),
        .D(p_0_in1_in[9]),
        .Q(\h2c_xdma_rrq_req[0][did] [1]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_102_107" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "102" *) 
  (* ram_slice_end = "107" *) 
  RAM32M MemArray_reg_0_3_102_107
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[58:57]),
        .DIB(DataIn[60:59]),
        .DIC(DataIn[62:61]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[103:102]),
        .DOB(Head0[105:104]),
        .DOC(Head0[107:106]),
        .DOD(NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_102_107_i_1
       (.I0(\Head_reg[119]_1 [65]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [47]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[77]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_102_107_i_2
       (.I0(\Head_reg[119]_1 [64]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [46]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[76]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_102_107_i_3
       (.I0(\Head_reg[119]_1 [67]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [49]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[79]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_102_107_i_4
       (.I0(\Head_reg[119]_1 [66]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [48]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[78]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_102_107_i_5
       (.I0(\Head_reg[119]_1 [69]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [51]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[81]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_102_107_i_6
       (.I0(\Head_reg[119]_1 [68]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [50]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[80]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_108_113" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "108" *) 
  (* ram_slice_end = "113" *) 
  RAM32M MemArray_reg_0_3_108_113
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[64:63]),
        .DIB(DataIn[66:65]),
        .DIC(DataIn[68:67]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[109:108]),
        .DOB(Head0[111:110]),
        .DOC(Head0[113:112]),
        .DOD(NLW_MemArray_reg_0_3_108_113_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_108_113_i_1
       (.I0(\Head_reg[119]_1 [71]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [53]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[83]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_108_113_i_2
       (.I0(\Head_reg[119]_1 [70]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [52]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[82]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_108_113_i_3
       (.I0(\Head_reg[119]_1 [73]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [55]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[85]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_108_113_i_4
       (.I0(\Head_reg[119]_1 [72]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [54]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[84]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_108_113_i_5
       (.I0(\Head_reg[119]_1 [75]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [57]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[87]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_108_113_i_6
       (.I0(\Head_reg[119]_1 [74]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [56]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[86]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_114_119" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "114" *) 
  (* ram_slice_end = "119" *) 
  RAM32M MemArray_reg_0_3_114_119
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[70:69]),
        .DIB(DataIn[72:71]),
        .DIC(DataIn[74:73]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[115:114]),
        .DOB(Head0[117:116]),
        .DOC(Head0[119:118]),
        .DOD(NLW_MemArray_reg_0_3_114_119_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_114_119_i_1
       (.I0(\Head_reg[119]_1 [77]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [59]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[89]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_114_119_i_2
       (.I0(\Head_reg[119]_1 [76]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [58]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[88]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_114_119_i_3
       (.I0(\Head_reg[119]_1 [79]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [61]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[91]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_114_119_i_4
       (.I0(\Head_reg[119]_1 [78]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [60]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[90]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_114_119_i_5
       (.I0(\Head_reg[119]_1 [81]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [63]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[93]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_114_119_i_6
       (.I0(\Head_reg[119]_1 [80]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [62]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[92]));
  LUT4 #(
    .INIT(16'h0203)) 
    MemArray_reg_0_3_120_121_i_1
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(almost_full_ff_2),
        .I3(\Head_reg[8]_1 ),
        .O(empty_ff_reg_3));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_120_121_i_2
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][rid] [3]),
        .O(payloadmuxed_0[27]));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_120_121_i_3
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][rid] [2]),
        .O(payloadmuxed_0[26]));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_120_121_i_4
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][rid] [5]),
        .O(payloadmuxed_0[29]));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_120_121_i_5
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][rid] [4]),
        .O(payloadmuxed_0[28]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(out[5:4]),
        .DIB(out[7:6]),
        .DIC(out[9:8]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[13:12]),
        .DOB(Head0[15:14]),
        .DOC(Head0[17:16]),
        .DOD(NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_12_17_i_1__1
       (.I0(\Head_reg[119]_1 [5]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][did] [5]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[5]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_12_17_i_2__1
       (.I0(\Head_reg[119]_1 [4]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][did] [4]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[4]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_12_17_i_3__1
       (.I0(\Head_reg[119]_1 [7]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][did] [7]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[7]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_12_17_i_4__1
       (.I0(\Head_reg[119]_1 [6]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][did] [6]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[6]));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_12_17_i_5__3
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][did] [9]),
        .O(payloadmuxed_0[9]));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_12_17_i_6__3
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][did] [8]),
        .O(payloadmuxed_0[8]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[1:0]),
        .DIB(DataIn[3:2]),
        .DIC(DataIn[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[19:18]),
        .DOB(Head0[21:20]),
        .DOC(Head0[23:22]),
        .DOD(NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_18_23_i_1__2
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][byte_len] [1]),
        .O(payloadmuxed_0[11]));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_18_23_i_2__2
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][byte_len] [0]),
        .O(payloadmuxed_0[10]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_18_23_i_3
       (.I0(\Head_reg[119]_1 [9]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [3]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[13]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_18_23_i_4
       (.I0(\Head_reg[119]_1 [8]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [2]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[12]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_18_23_i_5
       (.I0(\Head_reg[119]_1 [11]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [5]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[15]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_18_23_i_6
       (.I0(\Head_reg[119]_1 [10]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [4]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[14]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_24_29" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M MemArray_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[7:6]),
        .DIB(DataIn[9:8]),
        .DIC(DataIn[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[25:24]),
        .DOB(Head0[27:26]),
        .DOC(Head0[29:28]),
        .DOD(NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_24_29_i_1
       (.I0(\Head_reg[119]_1 [13]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [7]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[17]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_24_29_i_2
       (.I0(\Head_reg[119]_1 [12]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [6]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[16]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_24_29_i_3
       (.I0(\Head_reg[119]_1 [15]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [9]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[19]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_24_29_i_4
       (.I0(\Head_reg[119]_1 [14]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [8]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[18]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_24_29_i_5
       (.I0(\Head_reg[119]_1 [17]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [11]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[21]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_24_29_i_6
       (.I0(\Head_reg[119]_1 [16]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [10]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[20]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_30_35" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M MemArray_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({1'b0,DataIn[12]}),
        .DIB(\Head_reg[50]_0 [3:2]),
        .DIC({1'b0,\Head_reg[50]_0 [4]}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[31:30]),
        .DOB(Head0[49:48]),
        .DOC(Head0[51:50]),
        .DOD(NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_30_35_i_1
       (.I0(\Head_reg[119]_1 [19]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [13]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[23]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_30_35_i_2
       (.I0(\Head_reg[119]_1 [18]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][byte_len] [12]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[22]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_42_47" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M MemArray_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\Head_reg[50]_0 [1:0]),
        .DIB(\Head_reg[57]_0 ),
        .DIC(DataIn[14:13]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[47:46]),
        .DOB(Head0[57:56]),
        .DOC(Head0[59:58]),
        .DOD(NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_42_47_i_1
       (.I0(\Head_reg[119]_1 [21]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][rid] [1]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[25]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_42_47_i_2
       (.I0(\Head_reg[119]_1 [20]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][rid] [0]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[24]));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_54_59_i_1__1
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][adr] [1]),
        .O(payloadmuxed_0[31]));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_54_59_i_2__1
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][adr] [0]),
        .O(payloadmuxed_0[30]));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_54_59_i_3__1
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][adr] [3]),
        .O(payloadmuxed_0[33]));
  LUT5 #(
    .INIT(32'h00450000)) 
    MemArray_reg_0_3_54_59_i_4__1
       (.I0(empty_ff_reg_2),
        .I1(\Head_reg[8]_0 ),
        .I2(arbhist_ff),
        .I3(almost_full_ff_2),
        .I4(\h2c_xdma_rrq_req[0][adr] [2]),
        .O(payloadmuxed_0[32]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_60_65" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M MemArray_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[16:15]),
        .DIB(DataIn[18:17]),
        .DIC(DataIn[20:19]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[61:60]),
        .DOB(Head0[63:62]),
        .DOC(Head0[65:64]),
        .DOD(NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_60_65_i_1
       (.I0(\Head_reg[119]_1 [23]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [5]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[35]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_60_65_i_2
       (.I0(\Head_reg[119]_1 [22]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [4]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[34]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_60_65_i_3
       (.I0(\Head_reg[119]_1 [25]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [7]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[37]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_60_65_i_4
       (.I0(\Head_reg[119]_1 [24]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [6]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[36]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_60_65_i_5
       (.I0(\Head_reg[119]_1 [27]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [9]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[39]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_60_65_i_6
       (.I0(\Head_reg[119]_1 [26]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [8]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[38]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_66_71" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M MemArray_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[22:21]),
        .DIB(DataIn[24:23]),
        .DIC(DataIn[26:25]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[67:66]),
        .DOB(Head0[69:68]),
        .DOC(Head0[71:70]),
        .DOD(NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_66_71_i_1
       (.I0(\Head_reg[119]_1 [29]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [11]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[41]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_66_71_i_2
       (.I0(\Head_reg[119]_1 [28]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [10]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[40]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_66_71_i_3
       (.I0(\Head_reg[119]_1 [31]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [13]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[43]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_66_71_i_4
       (.I0(\Head_reg[119]_1 [30]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [12]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[42]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_66_71_i_5
       (.I0(\Head_reg[119]_1 [33]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [15]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[45]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_66_71_i_6
       (.I0(\Head_reg[119]_1 [32]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [14]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[44]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(out[1:0]),
        .DIB(out[3:2]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[9:8]),
        .DOB(Head0[11:10]),
        .DOC(NLW_MemArray_reg_0_3_6_11_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_6_11_i_2__1
       (.I0(\Head_reg[119]_1 [1]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][did] [1]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[1]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_6_11_i_3__1
       (.I0(\Head_reg[119]_1 [0]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][did] [0]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[0]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_6_11_i_4__1
       (.I0(\Head_reg[119]_1 [3]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][did] [3]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[3]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_6_11_i_5__1
       (.I0(\Head_reg[119]_1 [2]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][did] [2]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[2]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_72_77" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M MemArray_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[28:27]),
        .DIB(DataIn[30:29]),
        .DIC(DataIn[32:31]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[73:72]),
        .DOB(Head0[75:74]),
        .DOC(Head0[77:76]),
        .DOD(NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_72_77_i_1
       (.I0(\Head_reg[119]_1 [35]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [17]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[47]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_72_77_i_2
       (.I0(\Head_reg[119]_1 [34]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [16]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[46]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_72_77_i_3
       (.I0(\Head_reg[119]_1 [37]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [19]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[49]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_72_77_i_4
       (.I0(\Head_reg[119]_1 [36]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [18]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[48]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_72_77_i_5
       (.I0(\Head_reg[119]_1 [39]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [21]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[51]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_72_77_i_6
       (.I0(\Head_reg[119]_1 [38]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [20]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[50]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_78_83" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "83" *) 
  RAM32M MemArray_reg_0_3_78_83
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[34:33]),
        .DIB(DataIn[36:35]),
        .DIC(DataIn[38:37]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[79:78]),
        .DOB(Head0[81:80]),
        .DOC(Head0[83:82]),
        .DOD(NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_78_83_i_1
       (.I0(\Head_reg[119]_1 [41]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [23]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[53]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_78_83_i_2
       (.I0(\Head_reg[119]_1 [40]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [22]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[52]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_78_83_i_3
       (.I0(\Head_reg[119]_1 [43]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [25]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[55]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_78_83_i_4
       (.I0(\Head_reg[119]_1 [42]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [24]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[54]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_78_83_i_5
       (.I0(\Head_reg[119]_1 [45]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [27]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[57]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_78_83_i_6
       (.I0(\Head_reg[119]_1 [44]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [26]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[56]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_84_89" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "84" *) 
  (* ram_slice_end = "89" *) 
  RAM32M MemArray_reg_0_3_84_89
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[40:39]),
        .DIB(DataIn[42:41]),
        .DIC(DataIn[44:43]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[85:84]),
        .DOB(Head0[87:86]),
        .DOC(Head0[89:88]),
        .DOD(NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_84_89_i_1
       (.I0(\Head_reg[119]_1 [47]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [29]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[59]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_84_89_i_2
       (.I0(\Head_reg[119]_1 [46]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [28]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[58]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_84_89_i_3
       (.I0(\Head_reg[119]_1 [49]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [31]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[61]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_84_89_i_4
       (.I0(\Head_reg[119]_1 [48]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [30]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[60]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_84_89_i_5
       (.I0(\Head_reg[119]_1 [51]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [33]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[63]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_84_89_i_6
       (.I0(\Head_reg[119]_1 [50]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [32]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[62]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_90_95" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "90" *) 
  (* ram_slice_end = "95" *) 
  RAM32M MemArray_reg_0_3_90_95
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[46:45]),
        .DIB(DataIn[48:47]),
        .DIC(DataIn[50:49]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[91:90]),
        .DOB(Head0[93:92]),
        .DOC(Head0[95:94]),
        .DOD(NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_90_95_i_1
       (.I0(\Head_reg[119]_1 [53]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [35]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[65]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_90_95_i_2
       (.I0(\Head_reg[119]_1 [52]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [34]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[64]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_90_95_i_3
       (.I0(\Head_reg[119]_1 [55]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [37]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[67]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_90_95_i_4
       (.I0(\Head_reg[119]_1 [54]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [36]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[66]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_90_95_i_5
       (.I0(\Head_reg[119]_1 [57]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [39]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[69]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_90_95_i_6
       (.I0(\Head_reg[119]_1 [56]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [38]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[68]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "484" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_96_101" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "96" *) 
  (* ram_slice_end = "101" *) 
  RAM32M MemArray_reg_0_3_96_101
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[52:51]),
        .DIB(DataIn[54:53]),
        .DIC(DataIn[56:55]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[97:96]),
        .DOB(Head0[99:98]),
        .DOC(Head0[101:100]),
        .DOD(NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(rrq_vld_903));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_96_101_i_1
       (.I0(\Head_reg[119]_1 [59]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [41]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[71]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_96_101_i_2
       (.I0(\Head_reg[119]_1 [58]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [40]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[70]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_96_101_i_3
       (.I0(\Head_reg[119]_1 [61]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [43]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[73]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_96_101_i_4
       (.I0(\Head_reg[119]_1 [60]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [42]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[72]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_96_101_i_5
       (.I0(\Head_reg[119]_1 [63]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [45]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[75]));
  LUT4 #(
    .INIT(16'hF888)) 
    MemArray_reg_0_3_96_101_i_6
       (.I0(\Head_reg[119]_1 [62]),
        .I1(empty_ff_reg_3),
        .I2(\h2c_xdma_rrq_req[0][adr] [44]),
        .I3(empty_ff_reg_0),
        .O(payloadmuxed_0[74]));
  LUT5 #(
    .INIT(32'h5555666A)) 
    \RdPtr[0]_i_1__4 
       (.I0(RdPtr[0]),
        .I1(empty_ff_reg_0),
        .I2(FifoCntrRd[2]),
        .I3(FifoCntrRd[1]),
        .I4(Head1),
        .O(RdPtr__0[0]));
  LUT6 #(
    .INIT(64'h55577777AAA88888)) 
    \RdPtr[1]_i_1__5 
       (.I0(RdPtr[0]),
        .I1(Head1),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[2]),
        .I4(empty_ff_reg_0),
        .I5(RdPtr[1]),
        .O(RdPtr__0[1]));
  LUT5 #(
    .INIT(32'h03010000)) 
    \RdPtr[1]_i_2__2 
       (.I0(FifoCntrRd[0]),
        .I1(FifoCntrRd[2]),
        .I2(FifoCntrRd[1]),
        .I3(empty_ff_reg_0),
        .I4(rrq_vld_903),
        .O(Head1));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[0]),
        .Q(RdPtr[0]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(RdPtr[1]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  (* SOFT_HLUTNM = "soft_lutpair596" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \WrPtr[0]_i_1__5 
       (.I0(WrPtr[0]),
        .I1(rrq_vld_903),
        .O(WrPtr__0[0]));
  LUT3 #(
    .INIT(8'h78)) 
    \WrPtr[1]_i_1__5 
       (.I0(WrPtr[0]),
        .I1(rrq_vld_903),
        .I2(WrPtr[1]),
        .O(WrPtr__0[1]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[0]),
        .Q(WrPtr[0]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[1]),
        .Q(WrPtr[1]),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  LUT5 #(
    .INIT(32'h03000202)) 
    \dat_fifo_hd_nn1[0]_i_1 
       (.I0(dat_fifo_hd_nn1[0]),
        .I1(\dat_fifo_hd_out_nn1_reg[0] ),
        .I2(\dat_fifo_hd_out_nn1_reg[0]_0 ),
        .I3(Q[0]),
        .I4(rrq_ld_9008_out),
        .O(\dat_fifo_hd_nxt_nn1_reg[9] [0]));
  LUT5 #(
    .INIT(32'h000000AC)) 
    \dat_fifo_hd_nn1[1]_i_1 
       (.I0(Q[1]),
        .I1(dat_fifo_hd_nn1[1]),
        .I2(rrq_ld_9008_out),
        .I3(\dat_fifo_hd_out_nn1_reg[0] ),
        .I4(\dat_fifo_hd_out_nn1_reg[0]_0 ),
        .O(\dat_fifo_hd_nxt_nn1_reg[9] [1]));
  LUT5 #(
    .INIT(32'h000000AC)) 
    \dat_fifo_hd_nn1[2]_i_1 
       (.I0(Q[2]),
        .I1(dat_fifo_hd_nn1[2]),
        .I2(rrq_ld_9008_out),
        .I3(\dat_fifo_hd_out_nn1_reg[0] ),
        .I4(\dat_fifo_hd_out_nn1_reg[0]_0 ),
        .O(\dat_fifo_hd_nxt_nn1_reg[9] [2]));
  LUT5 #(
    .INIT(32'h000000AC)) 
    \dat_fifo_hd_nn1[3]_i_1 
       (.I0(Q[3]),
        .I1(dat_fifo_hd_nn1[3]),
        .I2(rrq_ld_9008_out),
        .I3(\dat_fifo_hd_out_nn1_reg[0] ),
        .I4(\dat_fifo_hd_out_nn1_reg[0]_0 ),
        .O(\dat_fifo_hd_nxt_nn1_reg[9] [3]));
  LUT4 #(
    .INIT(16'hEEFC)) 
    \dat_fifo_hd_nn1[4]_i_1__0 
       (.I0(Q[4]),
        .I1(\dat_fifo_hd_out_nn1_reg[0]_0 ),
        .I2(dat_fifo_hd_nn1[4]),
        .I3(rrq_ld_9008_out),
        .O(\dat_fifo_hd_nxt_nn1_reg[4] ));
  LUT4 #(
    .INIT(16'hEEFC)) 
    \dat_fifo_hd_nn1[5]_i_1__0 
       (.I0(Q[5]),
        .I1(\dat_fifo_hd_out_nn1_reg[0]_0 ),
        .I2(dat_fifo_hd_nn1[5]),
        .I3(rrq_ld_9008_out),
        .O(\dat_fifo_hd_nxt_nn1_reg[5] ));
  LUT4 #(
    .INIT(16'hEEFC)) 
    \dat_fifo_hd_nn1[6]_i_1__0 
       (.I0(Q[6]),
        .I1(\dat_fifo_hd_out_nn1_reg[0]_0 ),
        .I2(dat_fifo_hd_nn1[6]),
        .I3(rrq_ld_9008_out),
        .O(\dat_fifo_hd_nxt_nn1_reg[6] ));
  LUT4 #(
    .INIT(16'hEEFC)) 
    \dat_fifo_hd_nn1[7]_i_1__0 
       (.I0(Q[7]),
        .I1(\dat_fifo_hd_out_nn1_reg[0]_0 ),
        .I2(dat_fifo_hd_nn1[7]),
        .I3(rrq_ld_9008_out),
        .O(\dat_fifo_hd_nxt_nn1_reg[7] ));
  LUT4 #(
    .INIT(16'hEEFC)) 
    \dat_fifo_hd_nn1[8]_i_1__0 
       (.I0(Q[8]),
        .I1(\dat_fifo_hd_out_nn1_reg[0]_0 ),
        .I2(dat_fifo_hd_nn1[8]),
        .I3(rrq_ld_9008_out),
        .O(\dat_fifo_hd_nxt_nn1_reg[8] ));
  LUT5 #(
    .INIT(32'h000000AC)) 
    \dat_fifo_hd_nn1[9]_i_1 
       (.I0(Q[9]),
        .I1(dat_fifo_hd_nn1[9]),
        .I2(rrq_ld_9008_out),
        .I3(\dat_fifo_hd_out_nn1_reg[0] ),
        .I4(\dat_fifo_hd_out_nn1_reg[0]_0 ),
        .O(\dat_fifo_hd_nxt_nn1_reg[9] [4]));
  LUT5 #(
    .INIT(32'hFFFF0100)) 
    empty_ff_i_1__5
       (.I0(FifoCntrRd[1]),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[2]),
        .I3(empty_ff_reg_2),
        .I4(empty_ff_i_2__3_n_0),
        .O(empty_ff_i_1__5_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAAEF)) 
    empty_ff_i_2__3
       (.I0(\dat_fifo_hd_out_nn1_reg[0] ),
        .I1(empty_ff_reg_0),
        .I2(FifoCntrRd[0]),
        .I3(FifoCntrRd[1]),
        .I4(FifoCntrRd[2]),
        .I5(cfg_linkdown_nn1),
        .O(empty_ff_i_2__3_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__5_n_0),
        .Q(empty_ff_reg_2),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFF801180)) 
    full_ff_i_1__3
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(rrq_vld_903),
        .I3(FifoCntrWr[2]),
        .I4(full_ff_reg_1),
        .O(full_ff_i_1__3_n_0));
  FDRE full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(full_ff_i_1__3_n_0),
        .Q(full_ff_reg_1),
        .R(\pcie_h2c_rst_3ff_reg[0]_rep__4 ));
  LUT6 #(
    .INIT(64'h0000000200000000)) 
    rrq_ld_901_i_1__0
       (.I0(rrq_ld_901_reg_rep__5),
        .I1(ctl_rst),
        .I2(reg_sts_hlt_nn1),
        .I3(\rrq_sm_cur_900_reg[2] [2]),
        .I4(\rrq_sm_cur_900_reg[2] [1]),
        .I5(full_ff_reg_0),
        .O(rrq_ld_9008_out));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    \rrq_sm_cur_900[2]_i_1__0 
       (.I0(\rrq_sm_cur_900[2]_i_2_n_0 ),
        .I1(\rrq_sm_cur_900_reg[2]_0 ),
        .I2(\rrq_sm_cur_900_reg[2] [0]),
        .I3(\rrq_sm_cur_900_reg[2] [4]),
        .I4(\rrq_sm_cur_900_reg[2] [5]),
        .I5(\rrq_sm_cur_900_reg[2] [6]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAABAAEAE)) 
    \rrq_sm_cur_900[2]_i_2 
       (.I0(\rrq_sm_cur_900[2]_i_4_n_0 ),
        .I1(\rrq_sm_cur_900_reg[2] [1]),
        .I2(\rrq_sm_cur_900_reg[2] [2]),
        .I3(\rrq_sm_cur_900_reg[2]_1 ),
        .I4(dsc_ep_nn0),
        .I5(\rrq_sm_cur_900_reg[2] [3]),
        .O(\rrq_sm_cur_900[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000008000000)) 
    \rrq_sm_cur_900[2]_i_4 
       (.I0(\rrq_sm_cur_900_reg[2] [3]),
        .I1(rrq_vld_903),
        .I2(full_ff_reg_1),
        .I3(rrq_eod_903),
        .I4(dsc_ep_nn0),
        .I5(\rrq_sm_cur_900[2]_i_2_0 ),
        .O(\rrq_sm_cur_900[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FF8A)) 
    \rrq_sm_cur_900[3]_i_1__0 
       (.I0(\rrq_sm_cur_900_reg[2] [3]),
        .I1(full_ff_reg_1),
        .I2(rrq_vld_903),
        .I3(\rrq_sm_cur_900_reg[2] [5]),
        .I4(\rrq_sm_cur_900_reg[3] ),
        .I5(\rrq_sm_cur_900_reg[3]_0 ),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair595" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rrq_sm_cur_900[4]_i_3__0 
       (.I0(full_ff_reg_1),
        .I1(rrq_vld_903),
        .I2(\rrq_sm_cur_900_reg[2] [3]),
        .O(full_ff_reg_0));
  LUT3 #(
    .INIT(8'h02)) 
    rrq_vld_903_i_1__0
       (.I0(D[1]),
        .I1(rrq_vld_903_i_2__0_n_0),
        .I2(rrq_vld_903_reg),
        .O(rrq_vld_902));
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    rrq_vld_903_i_2__0
       (.I0(rrq_dsc_rem0_902),
        .I1(rrq_stall_902),
        .I2(rrq_fl_nn1),
        .I3(rrq_dsc_vld_902),
        .I4(full_ff_reg_1),
        .O(rrq_vld_903_i_2__0_n_0));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOHead" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOHead__parameterized2
   (almost_full_ff_reg_0,
    dsc_ep_nn0,
    ctl_non_inc_nn1_reg,
    \Head_reg[158]_0 ,
    D,
    empty_ff_reg_0,
    empty_ff_reg_1,
    empty_ff_reg_2,
    empty_ff_reg_3,
    empty_ff_reg_4,
    empty_ff_reg_5,
    \cfg_mrs_nn1_reg[11] ,
    \FifoCntrWr_reg[1]_0 ,
    \FifoCntrRd_reg[1]_0 ,
    \WrPtr_reg[1]_0 ,
    user_clk,
    out,
    rrq_dsc_ld_901_reg_rep__3,
    ctl_rst,
    evt_idl_stp_vld_nn1,
    Q,
    \rrq_sm_cur_900_reg[2] ,
    \rrq_sm_cur_900_reg[2]_0 ,
    rrq_eod_903,
    \rrq_sm_cur_900_reg[2]_1 ,
    reg_sts_hlt_nn1,
    \rrq_sm_cur_900_reg[6] ,
    \rrq_sm_cur_900_reg[1] ,
    rrq_dsc_ld_901_reg,
    rrq_dsc_ld_901_reg_0,
    \rrq_sm_cur_900_reg[1]_0 ,
    \rrq_sm_cur_900_reg[1]_1 ,
    cfg_mrs_nn1,
    S,
    \dsc_mrs_dst_nn1_reg[12] ,
    dsc_ch_evld,
    DataIn,
    empty_ff_reg_6,
    dsc_ch_vld,
    \FifoCntrRd_reg[2]_0 ,
    dsc_acc_mgc_nn1,
    dsc_acc_done_nn1,
    \WrPtr_reg[1]_1 ,
    \FifoCntrRd_reg[3]_0 ,
    \FifoCntrRd_reg[1]_1 ,
    \FifoCntrWr_reg[3]_0 ,
    \FifoCntrWr_reg[1]_1 );
  output almost_full_ff_reg_0;
  output dsc_ep_nn0;
  output ctl_non_inc_nn1_reg;
  output [157:0]\Head_reg[158]_0 ;
  output [2:0]D;
  output empty_ff_reg_0;
  output empty_ff_reg_1;
  output empty_ff_reg_2;
  output empty_ff_reg_3;
  output empty_ff_reg_4;
  output empty_ff_reg_5;
  output [11:0]\cfg_mrs_nn1_reg[11] ;
  output [1:0]\FifoCntrWr_reg[1]_0 ;
  output [1:0]\FifoCntrRd_reg[1]_0 ;
  output [1:0]\WrPtr_reg[1]_0 ;
  input user_clk;
  input out;
  input rrq_dsc_ld_901_reg_rep__3;
  input ctl_rst;
  input evt_idl_stp_vld_nn1;
  input [3:0]Q;
  input \rrq_sm_cur_900_reg[2] ;
  input \rrq_sm_cur_900_reg[2]_0 ;
  input rrq_eod_903;
  input \rrq_sm_cur_900_reg[2]_1 ;
  input reg_sts_hlt_nn1;
  input \rrq_sm_cur_900_reg[6] ;
  input \rrq_sm_cur_900_reg[1] ;
  input rrq_dsc_ld_901_reg;
  input rrq_dsc_ld_901_reg_0;
  input \rrq_sm_cur_900_reg[1]_0 ;
  input \rrq_sm_cur_900_reg[1]_1 ;
  input [4:0]cfg_mrs_nn1;
  input [0:0]S;
  input [4:0]\dsc_mrs_dst_nn1_reg[12] ;
  input [0:0]dsc_ch_evld;
  input [158:0]DataIn;
  input empty_ff_reg_6;
  input [0:0]dsc_ch_vld;
  input [0:0]\FifoCntrRd_reg[2]_0 ;
  input dsc_acc_mgc_nn1;
  input dsc_acc_done_nn1;
  input [1:0]\WrPtr_reg[1]_1 ;
  input [0:0]\FifoCntrRd_reg[3]_0 ;
  input [0:0]\FifoCntrRd_reg[1]_1 ;
  input [0:0]\FifoCntrWr_reg[3]_0 ;
  input [0:0]\FifoCntrWr_reg[1]_1 ;

  wire [2:0]D;
  wire [158:0]DataIn;
  wire \FifoCntrRd[0]_i_1__0_n_0 ;
  wire \FifoCntrRd[2]_i_1__0_n_0 ;
  wire \FifoCntrRd[3]_i_2_n_0 ;
  wire [3:2]FifoCntrRd_reg;
  wire [1:0]\FifoCntrRd_reg[1]_0 ;
  wire [0:0]\FifoCntrRd_reg[1]_1 ;
  wire [0:0]\FifoCntrRd_reg[2]_0 ;
  wire [0:0]\FifoCntrRd_reg[3]_0 ;
  wire \FifoCntrWr[0]_i_1__0_n_0 ;
  wire \FifoCntrWr[2]_i_1__0_n_0 ;
  wire \FifoCntrWr[3]_i_2_n_0 ;
  wire [3:2]FifoCntrWr_reg;
  wire [1:0]\FifoCntrWr_reg[1]_0 ;
  wire [0:0]\FifoCntrWr_reg[1]_1 ;
  wire [0:0]\FifoCntrWr_reg[3]_0 ;
  wire [158:0]Head0;
  wire Head1;
  wire \Head[158]_i_1_n_0 ;
  wire [157:0]\Head_reg[158]_0 ;
  wire MemArray_reg_0_7_0_5_n_3;
  wire [3:0]Q;
  wire [2:0]RdPtr;
  wire \RdPtr[2]_i_1_n_0 ;
  wire \RdPtr[2]_i_4_n_0 ;
  wire [2:0]RdPtr__0;
  wire [0:0]S;
  wire [2:2]WrPtr;
  wire [2:2]WrPtr__0;
  wire [1:0]\WrPtr_reg[1]_0 ;
  wire [1:0]\WrPtr_reg[1]_1 ;
  wire almost_full_ff_i_1_n_0;
  wire almost_full_ff_reg_0;
  wire [4:0]cfg_mrs_nn1;
  wire [11:0]\cfg_mrs_nn1_reg[11] ;
  wire ctl_non_inc_nn1_reg;
  wire ctl_rst;
  wire dsc_acc_done_nn1;
  wire dsc_acc_mgc_nn1;
  wire dsc_aln_nn1_i_2_n_0;
  wire [0:0]dsc_ch_evld;
  wire [0:0]dsc_ch_vld;
  wire dsc_ep_nn0;
  wire \dsc_mrs_dst_nn1[12]_i_3_n_0 ;
  wire \dsc_mrs_dst_nn1[12]_i_4_n_0 ;
  wire \dsc_mrs_dst_nn1[12]_i_5_n_0 ;
  wire \dsc_mrs_dst_nn1[4]_i_2_n_0 ;
  wire \dsc_mrs_dst_nn1[4]_i_3_n_0 ;
  wire \dsc_mrs_dst_nn1[4]_i_4_n_0 ;
  wire \dsc_mrs_dst_nn1[4]_i_5_n_0 ;
  wire \dsc_mrs_dst_nn1[4]_i_6_n_0 ;
  wire \dsc_mrs_dst_nn1[8]_i_2_n_0 ;
  wire \dsc_mrs_dst_nn1[8]_i_3_n_0 ;
  wire \dsc_mrs_dst_nn1[8]_i_4_n_0 ;
  wire \dsc_mrs_dst_nn1[8]_i_5_n_0 ;
  wire [4:0]\dsc_mrs_dst_nn1_reg[12] ;
  wire \dsc_mrs_dst_nn1_reg[12]_i_1_n_1 ;
  wire \dsc_mrs_dst_nn1_reg[12]_i_1_n_2 ;
  wire \dsc_mrs_dst_nn1_reg[12]_i_1_n_3 ;
  wire \dsc_mrs_dst_nn1_reg[4]_i_1_n_0 ;
  wire \dsc_mrs_dst_nn1_reg[4]_i_1_n_1 ;
  wire \dsc_mrs_dst_nn1_reg[4]_i_1_n_2 ;
  wire \dsc_mrs_dst_nn1_reg[4]_i_1_n_3 ;
  wire \dsc_mrs_dst_nn1_reg[8]_i_1_n_0 ;
  wire \dsc_mrs_dst_nn1_reg[8]_i_1_n_1 ;
  wire \dsc_mrs_dst_nn1_reg[8]_i_1_n_2 ;
  wire \dsc_mrs_dst_nn1_reg[8]_i_1_n_3 ;
  wire empty_ff_i_1__0_n_0;
  wire empty_ff_i_2_n_0;
  wire empty_ff_reg_0;
  wire empty_ff_reg_1;
  wire empty_ff_reg_2;
  wire empty_ff_reg_3;
  wire empty_ff_reg_4;
  wire empty_ff_reg_5;
  wire empty_ff_reg_6;
  wire evt_idl_stp_vld_nn1;
  wire out;
  wire [158:0]p_0_in1_in;
  wire reg_sts_hlt_nn1;
  wire rrq_dsc_ld_901_i_2__0_n_0;
  wire rrq_dsc_ld_901_reg;
  wire rrq_dsc_ld_901_reg_0;
  wire rrq_dsc_ld_901_reg_rep__3;
  wire rrq_eod_903;
  wire \rrq_sm_cur_900[2]_i_3_n_0 ;
  wire \rrq_sm_cur_900[6]_i_3_n_0 ;
  wire \rrq_sm_cur_900_reg[1] ;
  wire \rrq_sm_cur_900_reg[1]_0 ;
  wire \rrq_sm_cur_900_reg[1]_1 ;
  wire \rrq_sm_cur_900_reg[2] ;
  wire \rrq_sm_cur_900_reg[2]_0 ;
  wire \rrq_sm_cur_900_reg[2]_1 ;
  wire \rrq_sm_cur_900_reg[6] ;
  wire user_clk;
  wire [1:0]NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_102_107_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_108_113_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_114_119_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_120_125_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_126_131_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_132_137_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_138_143_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_144_149_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_150_155_DOD_UNCONNECTED;
  wire [1:1]NLW_MemArray_reg_0_7_156_158_DOB_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_156_158_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_156_158_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED;
  wire [3:3]\NLW_dsc_mrs_dst_nn1_reg[12]_i_1_CO_UNCONNECTED ;

  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__0 
       (.I0(\FifoCntrRd_reg[1]_0 [0]),
        .O(\FifoCntrRd[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAA9555)) 
    \FifoCntrRd[2]_i_1__0 
       (.I0(FifoCntrRd_reg[2]),
        .I1(\FifoCntrRd_reg[2]_0 ),
        .I2(dsc_acc_mgc_nn1),
        .I3(dsc_acc_done_nn1),
        .I4(\FifoCntrRd_reg[1]_0 [1]),
        .I5(\FifoCntrRd_reg[1]_0 [0]),
        .O(\FifoCntrRd[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair802" *) 
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \FifoCntrRd[3]_i_2 
       (.I0(FifoCntrRd_reg[3]),
        .I1(dsc_ch_vld),
        .I2(\FifoCntrRd_reg[1]_0 [1]),
        .I3(\FifoCntrRd_reg[1]_0 [0]),
        .I4(FifoCntrRd_reg[2]),
        .O(\FifoCntrRd[3]_i_2_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd_reg[3]_0 ),
        .D(\FifoCntrRd[0]_i_1__0_n_0 ),
        .Q(\FifoCntrRd_reg[1]_0 [0]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd_reg[3]_0 ),
        .D(\FifoCntrRd_reg[1]_1 ),
        .Q(\FifoCntrRd_reg[1]_0 [1]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd_reg[3]_0 ),
        .D(\FifoCntrRd[2]_i_1__0_n_0 ),
        .Q(FifoCntrRd_reg[2]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \FifoCntrRd_reg[3] 
       (.C(user_clk),
        .CE(\FifoCntrRd_reg[3]_0 ),
        .D(\FifoCntrRd[3]_i_2_n_0 ),
        .Q(FifoCntrRd_reg[3]),
        .R(\RdPtr[2]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__0 
       (.I0(\FifoCntrWr_reg[1]_0 [0]),
        .O(\FifoCntrWr[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair801" *) 
  LUT4 #(
    .INIT(16'h6AA9)) 
    \FifoCntrWr[2]_i_1__0 
       (.I0(FifoCntrWr_reg[2]),
        .I1(dsc_ch_evld),
        .I2(\FifoCntrWr_reg[1]_0 [1]),
        .I3(\FifoCntrWr_reg[1]_0 [0]),
        .O(\FifoCntrWr[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair801" *) 
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \FifoCntrWr[3]_i_2 
       (.I0(FifoCntrWr_reg[3]),
        .I1(dsc_ch_evld),
        .I2(\FifoCntrWr_reg[1]_0 [1]),
        .I3(\FifoCntrWr_reg[1]_0 [0]),
        .I4(FifoCntrWr_reg[2]),
        .O(\FifoCntrWr[3]_i_2_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[3]_0 ),
        .D(\FifoCntrWr[0]_i_1__0_n_0 ),
        .Q(\FifoCntrWr_reg[1]_0 [0]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[3]_0 ),
        .D(\FifoCntrWr_reg[1]_1 ),
        .Q(\FifoCntrWr_reg[1]_0 [1]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[3]_0 ),
        .D(\FifoCntrWr[2]_i_1__0_n_0 ),
        .Q(FifoCntrWr_reg[2]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \FifoCntrWr_reg[3] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[3]_0 ),
        .D(\FifoCntrWr[3]_i_2_n_0 ),
        .Q(FifoCntrWr_reg[3]),
        .R(\RdPtr[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair803" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[0]_i_1 
       (.I0(DataIn[0]),
        .I1(Head1),
        .I2(Head0[0]),
        .O(p_0_in1_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair852" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[100]_i_1__0 
       (.I0(DataIn[100]),
        .I1(Head1),
        .I2(Head0[100]),
        .O(p_0_in1_in[100]));
  (* SOFT_HLUTNM = "soft_lutpair853" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[101]_i_1__0 
       (.I0(DataIn[101]),
        .I1(Head1),
        .I2(Head0[101]),
        .O(p_0_in1_in[101]));
  (* SOFT_HLUTNM = "soft_lutpair853" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[102]_i_1__0 
       (.I0(DataIn[102]),
        .I1(Head1),
        .I2(Head0[102]),
        .O(p_0_in1_in[102]));
  (* SOFT_HLUTNM = "soft_lutpair854" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[103]_i_1__0 
       (.I0(DataIn[103]),
        .I1(Head1),
        .I2(Head0[103]),
        .O(p_0_in1_in[103]));
  (* SOFT_HLUTNM = "soft_lutpair854" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[104]_i_1__0 
       (.I0(DataIn[104]),
        .I1(Head1),
        .I2(Head0[104]),
        .O(p_0_in1_in[104]));
  (* SOFT_HLUTNM = "soft_lutpair855" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[105]_i_1__0 
       (.I0(DataIn[105]),
        .I1(Head1),
        .I2(Head0[105]),
        .O(p_0_in1_in[105]));
  (* SOFT_HLUTNM = "soft_lutpair855" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[106]_i_1__0 
       (.I0(DataIn[106]),
        .I1(Head1),
        .I2(Head0[106]),
        .O(p_0_in1_in[106]));
  (* SOFT_HLUTNM = "soft_lutpair856" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[107]_i_1__0 
       (.I0(DataIn[107]),
        .I1(Head1),
        .I2(Head0[107]),
        .O(p_0_in1_in[107]));
  (* SOFT_HLUTNM = "soft_lutpair856" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[108]_i_1__0 
       (.I0(DataIn[108]),
        .I1(Head1),
        .I2(Head0[108]),
        .O(p_0_in1_in[108]));
  (* SOFT_HLUTNM = "soft_lutpair857" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[109]_i_1__0 
       (.I0(DataIn[109]),
        .I1(Head1),
        .I2(Head0[109]),
        .O(p_0_in1_in[109]));
  (* SOFT_HLUTNM = "soft_lutpair807" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[10]_i_1__0 
       (.I0(DataIn[10]),
        .I1(Head1),
        .I2(Head0[10]),
        .O(p_0_in1_in[10]));
  (* SOFT_HLUTNM = "soft_lutpair857" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[110]_i_1__0 
       (.I0(DataIn[110]),
        .I1(Head1),
        .I2(Head0[110]),
        .O(p_0_in1_in[110]));
  (* SOFT_HLUTNM = "soft_lutpair858" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[111]_i_1__0 
       (.I0(DataIn[111]),
        .I1(Head1),
        .I2(Head0[111]),
        .O(p_0_in1_in[111]));
  (* SOFT_HLUTNM = "soft_lutpair858" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[112]_i_1__0 
       (.I0(DataIn[112]),
        .I1(Head1),
        .I2(Head0[112]),
        .O(p_0_in1_in[112]));
  (* SOFT_HLUTNM = "soft_lutpair859" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[113]_i_1__0 
       (.I0(DataIn[113]),
        .I1(Head1),
        .I2(Head0[113]),
        .O(p_0_in1_in[113]));
  (* SOFT_HLUTNM = "soft_lutpair859" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[114]_i_1__0 
       (.I0(DataIn[114]),
        .I1(Head1),
        .I2(Head0[114]),
        .O(p_0_in1_in[114]));
  (* SOFT_HLUTNM = "soft_lutpair860" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[115]_i_1__0 
       (.I0(DataIn[115]),
        .I1(Head1),
        .I2(Head0[115]),
        .O(p_0_in1_in[115]));
  (* SOFT_HLUTNM = "soft_lutpair860" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[116]_i_1__0 
       (.I0(DataIn[116]),
        .I1(Head1),
        .I2(Head0[116]),
        .O(p_0_in1_in[116]));
  (* SOFT_HLUTNM = "soft_lutpair861" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[117]_i_1__0 
       (.I0(DataIn[117]),
        .I1(Head1),
        .I2(Head0[117]),
        .O(p_0_in1_in[117]));
  (* SOFT_HLUTNM = "soft_lutpair861" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[118]_i_1__0 
       (.I0(DataIn[118]),
        .I1(Head1),
        .I2(Head0[118]),
        .O(p_0_in1_in[118]));
  (* SOFT_HLUTNM = "soft_lutpair862" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[119]_i_1__0 
       (.I0(DataIn[119]),
        .I1(Head1),
        .I2(Head0[119]),
        .O(p_0_in1_in[119]));
  (* SOFT_HLUTNM = "soft_lutpair808" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[11]_i_1__0 
       (.I0(DataIn[11]),
        .I1(Head1),
        .I2(Head0[11]),
        .O(p_0_in1_in[11]));
  (* SOFT_HLUTNM = "soft_lutpair862" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[120]_i_1 
       (.I0(DataIn[120]),
        .I1(Head1),
        .I2(Head0[120]),
        .O(p_0_in1_in[120]));
  (* SOFT_HLUTNM = "soft_lutpair863" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[121]_i_1 
       (.I0(DataIn[121]),
        .I1(Head1),
        .I2(Head0[121]),
        .O(p_0_in1_in[121]));
  (* SOFT_HLUTNM = "soft_lutpair863" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[122]_i_1 
       (.I0(DataIn[122]),
        .I1(Head1),
        .I2(Head0[122]),
        .O(p_0_in1_in[122]));
  (* SOFT_HLUTNM = "soft_lutpair864" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[123]_i_1 
       (.I0(DataIn[123]),
        .I1(Head1),
        .I2(Head0[123]),
        .O(p_0_in1_in[123]));
  (* SOFT_HLUTNM = "soft_lutpair864" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[124]_i_1 
       (.I0(DataIn[124]),
        .I1(Head1),
        .I2(Head0[124]),
        .O(p_0_in1_in[124]));
  (* SOFT_HLUTNM = "soft_lutpair865" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[125]_i_1 
       (.I0(DataIn[125]),
        .I1(Head1),
        .I2(Head0[125]),
        .O(p_0_in1_in[125]));
  (* SOFT_HLUTNM = "soft_lutpair865" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[126]_i_1 
       (.I0(DataIn[126]),
        .I1(Head1),
        .I2(Head0[126]),
        .O(p_0_in1_in[126]));
  (* SOFT_HLUTNM = "soft_lutpair866" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[127]_i_1 
       (.I0(DataIn[127]),
        .I1(Head1),
        .I2(Head0[127]),
        .O(p_0_in1_in[127]));
  (* SOFT_HLUTNM = "soft_lutpair866" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[128]_i_1 
       (.I0(DataIn[128]),
        .I1(Head1),
        .I2(Head0[128]),
        .O(p_0_in1_in[128]));
  (* SOFT_HLUTNM = "soft_lutpair867" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[129]_i_1 
       (.I0(DataIn[129]),
        .I1(Head1),
        .I2(Head0[129]),
        .O(p_0_in1_in[129]));
  (* SOFT_HLUTNM = "soft_lutpair808" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[12]_i_1__0 
       (.I0(DataIn[12]),
        .I1(Head1),
        .I2(Head0[12]),
        .O(p_0_in1_in[12]));
  (* SOFT_HLUTNM = "soft_lutpair867" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[130]_i_1 
       (.I0(DataIn[130]),
        .I1(Head1),
        .I2(Head0[130]),
        .O(p_0_in1_in[130]));
  (* SOFT_HLUTNM = "soft_lutpair868" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[131]_i_1 
       (.I0(DataIn[131]),
        .I1(Head1),
        .I2(Head0[131]),
        .O(p_0_in1_in[131]));
  (* SOFT_HLUTNM = "soft_lutpair868" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[132]_i_1 
       (.I0(DataIn[132]),
        .I1(Head1),
        .I2(Head0[132]),
        .O(p_0_in1_in[132]));
  (* SOFT_HLUTNM = "soft_lutpair869" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[133]_i_1 
       (.I0(DataIn[133]),
        .I1(Head1),
        .I2(Head0[133]),
        .O(p_0_in1_in[133]));
  (* SOFT_HLUTNM = "soft_lutpair869" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[134]_i_1 
       (.I0(DataIn[134]),
        .I1(Head1),
        .I2(Head0[134]),
        .O(p_0_in1_in[134]));
  (* SOFT_HLUTNM = "soft_lutpair870" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[135]_i_1 
       (.I0(DataIn[135]),
        .I1(Head1),
        .I2(Head0[135]),
        .O(p_0_in1_in[135]));
  (* SOFT_HLUTNM = "soft_lutpair870" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[136]_i_1 
       (.I0(DataIn[136]),
        .I1(Head1),
        .I2(Head0[136]),
        .O(p_0_in1_in[136]));
  (* SOFT_HLUTNM = "soft_lutpair871" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[137]_i_1 
       (.I0(DataIn[137]),
        .I1(Head1),
        .I2(Head0[137]),
        .O(p_0_in1_in[137]));
  (* SOFT_HLUTNM = "soft_lutpair871" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[138]_i_1 
       (.I0(DataIn[138]),
        .I1(Head1),
        .I2(Head0[138]),
        .O(p_0_in1_in[138]));
  (* SOFT_HLUTNM = "soft_lutpair872" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[139]_i_1 
       (.I0(DataIn[139]),
        .I1(Head1),
        .I2(Head0[139]),
        .O(p_0_in1_in[139]));
  (* SOFT_HLUTNM = "soft_lutpair809" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[13]_i_1__0 
       (.I0(DataIn[13]),
        .I1(Head1),
        .I2(Head0[13]),
        .O(p_0_in1_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair872" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[140]_i_1 
       (.I0(DataIn[140]),
        .I1(Head1),
        .I2(Head0[140]),
        .O(p_0_in1_in[140]));
  (* SOFT_HLUTNM = "soft_lutpair873" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[141]_i_1 
       (.I0(DataIn[141]),
        .I1(Head1),
        .I2(Head0[141]),
        .O(p_0_in1_in[141]));
  (* SOFT_HLUTNM = "soft_lutpair873" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[142]_i_1 
       (.I0(DataIn[142]),
        .I1(Head1),
        .I2(Head0[142]),
        .O(p_0_in1_in[142]));
  (* SOFT_HLUTNM = "soft_lutpair874" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[143]_i_1 
       (.I0(DataIn[143]),
        .I1(Head1),
        .I2(Head0[143]),
        .O(p_0_in1_in[143]));
  (* SOFT_HLUTNM = "soft_lutpair874" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[144]_i_1 
       (.I0(DataIn[144]),
        .I1(Head1),
        .I2(Head0[144]),
        .O(p_0_in1_in[144]));
  (* SOFT_HLUTNM = "soft_lutpair875" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[145]_i_1 
       (.I0(DataIn[145]),
        .I1(Head1),
        .I2(Head0[145]),
        .O(p_0_in1_in[145]));
  (* SOFT_HLUTNM = "soft_lutpair875" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[146]_i_1 
       (.I0(DataIn[146]),
        .I1(Head1),
        .I2(Head0[146]),
        .O(p_0_in1_in[146]));
  (* SOFT_HLUTNM = "soft_lutpair876" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[147]_i_1 
       (.I0(DataIn[147]),
        .I1(Head1),
        .I2(Head0[147]),
        .O(p_0_in1_in[147]));
  (* SOFT_HLUTNM = "soft_lutpair876" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[148]_i_1 
       (.I0(DataIn[148]),
        .I1(Head1),
        .I2(Head0[148]),
        .O(p_0_in1_in[148]));
  (* SOFT_HLUTNM = "soft_lutpair877" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[149]_i_1 
       (.I0(DataIn[149]),
        .I1(Head1),
        .I2(Head0[149]),
        .O(p_0_in1_in[149]));
  (* SOFT_HLUTNM = "soft_lutpair809" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[14]_i_1__0 
       (.I0(DataIn[14]),
        .I1(Head1),
        .I2(Head0[14]),
        .O(p_0_in1_in[14]));
  (* SOFT_HLUTNM = "soft_lutpair877" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[150]_i_1 
       (.I0(DataIn[150]),
        .I1(Head1),
        .I2(Head0[150]),
        .O(p_0_in1_in[150]));
  (* SOFT_HLUTNM = "soft_lutpair878" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[151]_i_1 
       (.I0(DataIn[151]),
        .I1(Head1),
        .I2(Head0[151]),
        .O(p_0_in1_in[151]));
  (* SOFT_HLUTNM = "soft_lutpair878" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[152]_i_1 
       (.I0(DataIn[152]),
        .I1(Head1),
        .I2(Head0[152]),
        .O(p_0_in1_in[152]));
  (* SOFT_HLUTNM = "soft_lutpair879" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[153]_i_1 
       (.I0(DataIn[153]),
        .I1(Head1),
        .I2(Head0[153]),
        .O(p_0_in1_in[153]));
  (* SOFT_HLUTNM = "soft_lutpair879" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[154]_i_1 
       (.I0(DataIn[154]),
        .I1(Head1),
        .I2(Head0[154]),
        .O(p_0_in1_in[154]));
  (* SOFT_HLUTNM = "soft_lutpair880" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[155]_i_1 
       (.I0(DataIn[155]),
        .I1(Head1),
        .I2(Head0[155]),
        .O(p_0_in1_in[155]));
  (* SOFT_HLUTNM = "soft_lutpair880" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[156]_i_1 
       (.I0(DataIn[156]),
        .I1(Head1),
        .I2(Head0[156]),
        .O(p_0_in1_in[156]));
  (* SOFT_HLUTNM = "soft_lutpair881" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[157]_i_1 
       (.I0(DataIn[157]),
        .I1(Head1),
        .I2(Head0[157]),
        .O(p_0_in1_in[157]));
  LUT6 #(
    .INIT(64'hEEEEEEEEEEEEEEEF)) 
    \Head[158]_i_1 
       (.I0(empty_ff_reg_6),
        .I1(Head1),
        .I2(\FifoCntrRd_reg[1]_0 [0]),
        .I3(FifoCntrRd_reg[3]),
        .I4(FifoCntrRd_reg[2]),
        .I5(\FifoCntrRd_reg[1]_0 [1]),
        .O(\Head[158]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair881" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[158]_i_2 
       (.I0(DataIn[158]),
        .I1(Head1),
        .I2(Head0[158]),
        .O(p_0_in1_in[158]));
  (* SOFT_HLUTNM = "soft_lutpair810" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[15]_i_1__0 
       (.I0(DataIn[15]),
        .I1(Head1),
        .I2(Head0[15]),
        .O(p_0_in1_in[15]));
  (* SOFT_HLUTNM = "soft_lutpair810" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[16]_i_1 
       (.I0(DataIn[16]),
        .I1(Head1),
        .I2(Head0[16]),
        .O(p_0_in1_in[16]));
  (* SOFT_HLUTNM = "soft_lutpair811" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[17]_i_1 
       (.I0(DataIn[17]),
        .I1(Head1),
        .I2(Head0[17]),
        .O(p_0_in1_in[17]));
  (* SOFT_HLUTNM = "soft_lutpair811" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[18]_i_1 
       (.I0(DataIn[18]),
        .I1(Head1),
        .I2(Head0[18]),
        .O(p_0_in1_in[18]));
  (* SOFT_HLUTNM = "soft_lutpair812" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[19]_i_1 
       (.I0(DataIn[19]),
        .I1(Head1),
        .I2(Head0[19]),
        .O(p_0_in1_in[19]));
  (* SOFT_HLUTNM = "soft_lutpair803" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[1]_i_1 
       (.I0(DataIn[1]),
        .I1(Head1),
        .I2(Head0[1]),
        .O(p_0_in1_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair812" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[20]_i_1__0 
       (.I0(DataIn[20]),
        .I1(Head1),
        .I2(Head0[20]),
        .O(p_0_in1_in[20]));
  (* SOFT_HLUTNM = "soft_lutpair813" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[21]_i_1__0 
       (.I0(DataIn[21]),
        .I1(Head1),
        .I2(Head0[21]),
        .O(p_0_in1_in[21]));
  (* SOFT_HLUTNM = "soft_lutpair813" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[22]_i_1__0 
       (.I0(DataIn[22]),
        .I1(Head1),
        .I2(Head0[22]),
        .O(p_0_in1_in[22]));
  (* SOFT_HLUTNM = "soft_lutpair814" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[23]_i_1__0 
       (.I0(DataIn[23]),
        .I1(Head1),
        .I2(Head0[23]),
        .O(p_0_in1_in[23]));
  (* SOFT_HLUTNM = "soft_lutpair814" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[24]_i_1__0 
       (.I0(DataIn[24]),
        .I1(Head1),
        .I2(Head0[24]),
        .O(p_0_in1_in[24]));
  (* SOFT_HLUTNM = "soft_lutpair815" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[25]_i_1__0 
       (.I0(DataIn[25]),
        .I1(Head1),
        .I2(Head0[25]),
        .O(p_0_in1_in[25]));
  (* SOFT_HLUTNM = "soft_lutpair815" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[26]_i_1__0 
       (.I0(DataIn[26]),
        .I1(Head1),
        .I2(Head0[26]),
        .O(p_0_in1_in[26]));
  (* SOFT_HLUTNM = "soft_lutpair816" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[27]_i_1__0 
       (.I0(DataIn[27]),
        .I1(Head1),
        .I2(Head0[27]),
        .O(p_0_in1_in[27]));
  (* SOFT_HLUTNM = "soft_lutpair816" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[28]_i_1__0 
       (.I0(DataIn[28]),
        .I1(Head1),
        .I2(Head0[28]),
        .O(p_0_in1_in[28]));
  (* SOFT_HLUTNM = "soft_lutpair817" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[29]_i_1__0 
       (.I0(DataIn[29]),
        .I1(Head1),
        .I2(Head0[29]),
        .O(p_0_in1_in[29]));
  (* SOFT_HLUTNM = "soft_lutpair817" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[30]_i_1__0 
       (.I0(DataIn[30]),
        .I1(Head1),
        .I2(Head0[30]),
        .O(p_0_in1_in[30]));
  (* SOFT_HLUTNM = "soft_lutpair818" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[31]_i_1__0 
       (.I0(DataIn[31]),
        .I1(Head1),
        .I2(Head0[31]),
        .O(p_0_in1_in[31]));
  (* SOFT_HLUTNM = "soft_lutpair818" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[32]_i_1__0 
       (.I0(DataIn[32]),
        .I1(Head1),
        .I2(Head0[32]),
        .O(p_0_in1_in[32]));
  (* SOFT_HLUTNM = "soft_lutpair819" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[33]_i_1 
       (.I0(DataIn[33]),
        .I1(Head1),
        .I2(Head0[33]),
        .O(p_0_in1_in[33]));
  (* SOFT_HLUTNM = "soft_lutpair819" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[34]_i_1 
       (.I0(DataIn[34]),
        .I1(Head1),
        .I2(Head0[34]),
        .O(p_0_in1_in[34]));
  (* SOFT_HLUTNM = "soft_lutpair820" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[35]_i_1 
       (.I0(DataIn[35]),
        .I1(Head1),
        .I2(Head0[35]),
        .O(p_0_in1_in[35]));
  (* SOFT_HLUTNM = "soft_lutpair820" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[36]_i_1 
       (.I0(DataIn[36]),
        .I1(Head1),
        .I2(Head0[36]),
        .O(p_0_in1_in[36]));
  (* SOFT_HLUTNM = "soft_lutpair821" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[37]_i_1 
       (.I0(DataIn[37]),
        .I1(Head1),
        .I2(Head0[37]),
        .O(p_0_in1_in[37]));
  (* SOFT_HLUTNM = "soft_lutpair821" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[38]_i_1 
       (.I0(DataIn[38]),
        .I1(Head1),
        .I2(Head0[38]),
        .O(p_0_in1_in[38]));
  (* SOFT_HLUTNM = "soft_lutpair822" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[39]_i_1 
       (.I0(DataIn[39]),
        .I1(Head1),
        .I2(Head0[39]),
        .O(p_0_in1_in[39]));
  (* SOFT_HLUTNM = "soft_lutpair804" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[3]_i_1 
       (.I0(DataIn[3]),
        .I1(Head1),
        .I2(Head0[3]),
        .O(p_0_in1_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair822" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[40]_i_1 
       (.I0(DataIn[40]),
        .I1(Head1),
        .I2(Head0[40]),
        .O(p_0_in1_in[40]));
  (* SOFT_HLUTNM = "soft_lutpair823" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[41]_i_1 
       (.I0(DataIn[41]),
        .I1(Head1),
        .I2(Head0[41]),
        .O(p_0_in1_in[41]));
  (* SOFT_HLUTNM = "soft_lutpair823" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[42]_i_1 
       (.I0(DataIn[42]),
        .I1(Head1),
        .I2(Head0[42]),
        .O(p_0_in1_in[42]));
  (* SOFT_HLUTNM = "soft_lutpair824" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[43]_i_1 
       (.I0(DataIn[43]),
        .I1(Head1),
        .I2(Head0[43]),
        .O(p_0_in1_in[43]));
  (* SOFT_HLUTNM = "soft_lutpair824" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[44]_i_1 
       (.I0(DataIn[44]),
        .I1(Head1),
        .I2(Head0[44]),
        .O(p_0_in1_in[44]));
  (* SOFT_HLUTNM = "soft_lutpair825" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[45]_i_1 
       (.I0(DataIn[45]),
        .I1(Head1),
        .I2(Head0[45]),
        .O(p_0_in1_in[45]));
  (* SOFT_HLUTNM = "soft_lutpair825" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[46]_i_1__0 
       (.I0(DataIn[46]),
        .I1(Head1),
        .I2(Head0[46]),
        .O(p_0_in1_in[46]));
  (* SOFT_HLUTNM = "soft_lutpair826" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[47]_i_1 
       (.I0(DataIn[47]),
        .I1(Head1),
        .I2(Head0[47]),
        .O(p_0_in1_in[47]));
  (* SOFT_HLUTNM = "soft_lutpair826" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[48]_i_1 
       (.I0(DataIn[48]),
        .I1(Head1),
        .I2(Head0[48]),
        .O(p_0_in1_in[48]));
  (* SOFT_HLUTNM = "soft_lutpair827" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[49]_i_1 
       (.I0(DataIn[49]),
        .I1(Head1),
        .I2(Head0[49]),
        .O(p_0_in1_in[49]));
  (* SOFT_HLUTNM = "soft_lutpair804" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[4]_i_1 
       (.I0(DataIn[4]),
        .I1(Head1),
        .I2(Head0[4]),
        .O(p_0_in1_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair827" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[50]_i_1 
       (.I0(DataIn[50]),
        .I1(Head1),
        .I2(Head0[50]),
        .O(p_0_in1_in[50]));
  (* SOFT_HLUTNM = "soft_lutpair828" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[51]_i_1 
       (.I0(DataIn[51]),
        .I1(Head1),
        .I2(Head0[51]),
        .O(p_0_in1_in[51]));
  (* SOFT_HLUTNM = "soft_lutpair828" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[52]_i_1 
       (.I0(DataIn[52]),
        .I1(Head1),
        .I2(Head0[52]),
        .O(p_0_in1_in[52]));
  (* SOFT_HLUTNM = "soft_lutpair829" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[53]_i_1 
       (.I0(DataIn[53]),
        .I1(Head1),
        .I2(Head0[53]),
        .O(p_0_in1_in[53]));
  (* SOFT_HLUTNM = "soft_lutpair829" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[54]_i_1 
       (.I0(DataIn[54]),
        .I1(Head1),
        .I2(Head0[54]),
        .O(p_0_in1_in[54]));
  (* SOFT_HLUTNM = "soft_lutpair830" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[55]_i_1 
       (.I0(DataIn[55]),
        .I1(Head1),
        .I2(Head0[55]),
        .O(p_0_in1_in[55]));
  (* SOFT_HLUTNM = "soft_lutpair830" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[56]_i_1 
       (.I0(DataIn[56]),
        .I1(Head1),
        .I2(Head0[56]),
        .O(p_0_in1_in[56]));
  (* SOFT_HLUTNM = "soft_lutpair831" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[57]_i_1 
       (.I0(DataIn[57]),
        .I1(Head1),
        .I2(Head0[57]),
        .O(p_0_in1_in[57]));
  (* SOFT_HLUTNM = "soft_lutpair831" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[58]_i_1 
       (.I0(DataIn[58]),
        .I1(Head1),
        .I2(Head0[58]),
        .O(p_0_in1_in[58]));
  (* SOFT_HLUTNM = "soft_lutpair832" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[59]_i_1 
       (.I0(DataIn[59]),
        .I1(Head1),
        .I2(Head0[59]),
        .O(p_0_in1_in[59]));
  (* SOFT_HLUTNM = "soft_lutpair805" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[5]_i_1 
       (.I0(DataIn[5]),
        .I1(Head1),
        .I2(Head0[5]),
        .O(p_0_in1_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair832" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[60]_i_1 
       (.I0(DataIn[60]),
        .I1(Head1),
        .I2(Head0[60]),
        .O(p_0_in1_in[60]));
  (* SOFT_HLUTNM = "soft_lutpair833" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[61]_i_1__0 
       (.I0(DataIn[61]),
        .I1(Head1),
        .I2(Head0[61]),
        .O(p_0_in1_in[61]));
  (* SOFT_HLUTNM = "soft_lutpair833" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[62]_i_1__0 
       (.I0(DataIn[62]),
        .I1(Head1),
        .I2(Head0[62]),
        .O(p_0_in1_in[62]));
  (* SOFT_HLUTNM = "soft_lutpair834" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[63]_i_1__0 
       (.I0(DataIn[63]),
        .I1(Head1),
        .I2(Head0[63]),
        .O(p_0_in1_in[63]));
  (* SOFT_HLUTNM = "soft_lutpair834" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[64]_i_1__0 
       (.I0(DataIn[64]),
        .I1(Head1),
        .I2(Head0[64]),
        .O(p_0_in1_in[64]));
  (* SOFT_HLUTNM = "soft_lutpair835" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[65]_i_1__0 
       (.I0(DataIn[65]),
        .I1(Head1),
        .I2(Head0[65]),
        .O(p_0_in1_in[65]));
  (* SOFT_HLUTNM = "soft_lutpair835" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[66]_i_1__0 
       (.I0(DataIn[66]),
        .I1(Head1),
        .I2(Head0[66]),
        .O(p_0_in1_in[66]));
  (* SOFT_HLUTNM = "soft_lutpair836" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[67]_i_1__0 
       (.I0(DataIn[67]),
        .I1(Head1),
        .I2(Head0[67]),
        .O(p_0_in1_in[67]));
  (* SOFT_HLUTNM = "soft_lutpair836" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[68]_i_1__0 
       (.I0(DataIn[68]),
        .I1(Head1),
        .I2(Head0[68]),
        .O(p_0_in1_in[68]));
  (* SOFT_HLUTNM = "soft_lutpair837" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[69]_i_1__0 
       (.I0(DataIn[69]),
        .I1(Head1),
        .I2(Head0[69]),
        .O(p_0_in1_in[69]));
  (* SOFT_HLUTNM = "soft_lutpair805" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[6]_i_1 
       (.I0(DataIn[6]),
        .I1(Head1),
        .I2(Head0[6]),
        .O(p_0_in1_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair837" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[70]_i_1__0 
       (.I0(DataIn[70]),
        .I1(Head1),
        .I2(Head0[70]),
        .O(p_0_in1_in[70]));
  (* SOFT_HLUTNM = "soft_lutpair838" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[71]_i_1__0 
       (.I0(DataIn[71]),
        .I1(Head1),
        .I2(Head0[71]),
        .O(p_0_in1_in[71]));
  (* SOFT_HLUTNM = "soft_lutpair838" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[72]_i_1__0 
       (.I0(DataIn[72]),
        .I1(Head1),
        .I2(Head0[72]),
        .O(p_0_in1_in[72]));
  (* SOFT_HLUTNM = "soft_lutpair839" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[73]_i_1__0 
       (.I0(DataIn[73]),
        .I1(Head1),
        .I2(Head0[73]),
        .O(p_0_in1_in[73]));
  (* SOFT_HLUTNM = "soft_lutpair839" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[74]_i_1__0 
       (.I0(DataIn[74]),
        .I1(Head1),
        .I2(Head0[74]),
        .O(p_0_in1_in[74]));
  (* SOFT_HLUTNM = "soft_lutpair840" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[75]_i_1__0 
       (.I0(DataIn[75]),
        .I1(Head1),
        .I2(Head0[75]),
        .O(p_0_in1_in[75]));
  (* SOFT_HLUTNM = "soft_lutpair840" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[76]_i_1__0 
       (.I0(DataIn[76]),
        .I1(Head1),
        .I2(Head0[76]),
        .O(p_0_in1_in[76]));
  (* SOFT_HLUTNM = "soft_lutpair841" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[77]_i_1__0 
       (.I0(DataIn[77]),
        .I1(Head1),
        .I2(Head0[77]),
        .O(p_0_in1_in[77]));
  (* SOFT_HLUTNM = "soft_lutpair841" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[78]_i_1__0 
       (.I0(DataIn[78]),
        .I1(Head1),
        .I2(Head0[78]),
        .O(p_0_in1_in[78]));
  (* SOFT_HLUTNM = "soft_lutpair842" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[79]_i_1__0 
       (.I0(DataIn[79]),
        .I1(Head1),
        .I2(Head0[79]),
        .O(p_0_in1_in[79]));
  (* SOFT_HLUTNM = "soft_lutpair806" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[7]_i_1 
       (.I0(DataIn[7]),
        .I1(Head1),
        .I2(Head0[7]),
        .O(p_0_in1_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair842" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[80]_i_1__0 
       (.I0(DataIn[80]),
        .I1(Head1),
        .I2(Head0[80]),
        .O(p_0_in1_in[80]));
  (* SOFT_HLUTNM = "soft_lutpair843" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[81]_i_1__0 
       (.I0(DataIn[81]),
        .I1(Head1),
        .I2(Head0[81]),
        .O(p_0_in1_in[81]));
  (* SOFT_HLUTNM = "soft_lutpair843" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[82]_i_1__0 
       (.I0(DataIn[82]),
        .I1(Head1),
        .I2(Head0[82]),
        .O(p_0_in1_in[82]));
  (* SOFT_HLUTNM = "soft_lutpair844" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[83]_i_1__0 
       (.I0(DataIn[83]),
        .I1(Head1),
        .I2(Head0[83]),
        .O(p_0_in1_in[83]));
  (* SOFT_HLUTNM = "soft_lutpair844" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[84]_i_1__0 
       (.I0(DataIn[84]),
        .I1(Head1),
        .I2(Head0[84]),
        .O(p_0_in1_in[84]));
  (* SOFT_HLUTNM = "soft_lutpair845" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[85]_i_1__0 
       (.I0(DataIn[85]),
        .I1(Head1),
        .I2(Head0[85]),
        .O(p_0_in1_in[85]));
  (* SOFT_HLUTNM = "soft_lutpair845" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[86]_i_1__0 
       (.I0(DataIn[86]),
        .I1(Head1),
        .I2(Head0[86]),
        .O(p_0_in1_in[86]));
  (* SOFT_HLUTNM = "soft_lutpair846" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[87]_i_1__0 
       (.I0(DataIn[87]),
        .I1(Head1),
        .I2(Head0[87]),
        .O(p_0_in1_in[87]));
  (* SOFT_HLUTNM = "soft_lutpair846" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[88]_i_1__0 
       (.I0(DataIn[88]),
        .I1(Head1),
        .I2(Head0[88]),
        .O(p_0_in1_in[88]));
  (* SOFT_HLUTNM = "soft_lutpair847" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[89]_i_1__0 
       (.I0(DataIn[89]),
        .I1(Head1),
        .I2(Head0[89]),
        .O(p_0_in1_in[89]));
  (* SOFT_HLUTNM = "soft_lutpair806" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[8]_i_1__0 
       (.I0(DataIn[8]),
        .I1(Head1),
        .I2(Head0[8]),
        .O(p_0_in1_in[8]));
  (* SOFT_HLUTNM = "soft_lutpair847" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[90]_i_1__0 
       (.I0(DataIn[90]),
        .I1(Head1),
        .I2(Head0[90]),
        .O(p_0_in1_in[90]));
  (* SOFT_HLUTNM = "soft_lutpair848" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[91]_i_1__0 
       (.I0(DataIn[91]),
        .I1(Head1),
        .I2(Head0[91]),
        .O(p_0_in1_in[91]));
  (* SOFT_HLUTNM = "soft_lutpair848" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[92]_i_1__0 
       (.I0(DataIn[92]),
        .I1(Head1),
        .I2(Head0[92]),
        .O(p_0_in1_in[92]));
  (* SOFT_HLUTNM = "soft_lutpair849" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[93]_i_1__0 
       (.I0(DataIn[93]),
        .I1(Head1),
        .I2(Head0[93]),
        .O(p_0_in1_in[93]));
  (* SOFT_HLUTNM = "soft_lutpair849" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[94]_i_1__0 
       (.I0(DataIn[94]),
        .I1(Head1),
        .I2(Head0[94]),
        .O(p_0_in1_in[94]));
  (* SOFT_HLUTNM = "soft_lutpair850" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[95]_i_1__0 
       (.I0(DataIn[95]),
        .I1(Head1),
        .I2(Head0[95]),
        .O(p_0_in1_in[95]));
  (* SOFT_HLUTNM = "soft_lutpair850" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[96]_i_1__0 
       (.I0(DataIn[96]),
        .I1(Head1),
        .I2(Head0[96]),
        .O(p_0_in1_in[96]));
  (* SOFT_HLUTNM = "soft_lutpair851" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[97]_i_1__0 
       (.I0(DataIn[97]),
        .I1(Head1),
        .I2(Head0[97]),
        .O(p_0_in1_in[97]));
  (* SOFT_HLUTNM = "soft_lutpair851" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[98]_i_1__0 
       (.I0(DataIn[98]),
        .I1(Head1),
        .I2(Head0[98]),
        .O(p_0_in1_in[98]));
  (* SOFT_HLUTNM = "soft_lutpair852" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[99]_i_1__0 
       (.I0(DataIn[99]),
        .I1(Head1),
        .I2(Head0[99]),
        .O(p_0_in1_in[99]));
  (* SOFT_HLUTNM = "soft_lutpair807" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[9]_i_1__0 
       (.I0(DataIn[9]),
        .I1(Head1),
        .I2(Head0[9]),
        .O(p_0_in1_in[9]));
  FDRE \Head_reg[0] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[0]),
        .Q(\Head_reg[158]_0 [0]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[100] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[100]),
        .Q(\Head_reg[158]_0 [99]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[101] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[101]),
        .Q(\Head_reg[158]_0 [100]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[102] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[102]),
        .Q(\Head_reg[158]_0 [101]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[103] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[103]),
        .Q(\Head_reg[158]_0 [102]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[104] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[104]),
        .Q(\Head_reg[158]_0 [103]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[105] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[105]),
        .Q(\Head_reg[158]_0 [104]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[106] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[106]),
        .Q(\Head_reg[158]_0 [105]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[107] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[107]),
        .Q(\Head_reg[158]_0 [106]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[108] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[108]),
        .Q(\Head_reg[158]_0 [107]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[109] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[109]),
        .Q(\Head_reg[158]_0 [108]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[10]),
        .Q(\Head_reg[158]_0 [9]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[110] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[110]),
        .Q(\Head_reg[158]_0 [109]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[111] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[111]),
        .Q(\Head_reg[158]_0 [110]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[112] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[112]),
        .Q(\Head_reg[158]_0 [111]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[113] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[113]),
        .Q(\Head_reg[158]_0 [112]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[114] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[114]),
        .Q(\Head_reg[158]_0 [113]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[115] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[115]),
        .Q(\Head_reg[158]_0 [114]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[116] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[116]),
        .Q(\Head_reg[158]_0 [115]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[117] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[117]),
        .Q(\Head_reg[158]_0 [116]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[118] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[118]),
        .Q(\Head_reg[158]_0 [117]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[119] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[119]),
        .Q(\Head_reg[158]_0 [118]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[11]),
        .Q(\Head_reg[158]_0 [10]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[120] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[120]),
        .Q(\Head_reg[158]_0 [119]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[121] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[121]),
        .Q(\Head_reg[158]_0 [120]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[122] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[122]),
        .Q(\Head_reg[158]_0 [121]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[123] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[123]),
        .Q(\Head_reg[158]_0 [122]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[124] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[124]),
        .Q(\Head_reg[158]_0 [123]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[125] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[125]),
        .Q(\Head_reg[158]_0 [124]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[126] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[126]),
        .Q(\Head_reg[158]_0 [125]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[127] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[127]),
        .Q(\Head_reg[158]_0 [126]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[128] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[128]),
        .Q(\Head_reg[158]_0 [127]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[129] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[129]),
        .Q(\Head_reg[158]_0 [128]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[12]),
        .Q(\Head_reg[158]_0 [11]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[130] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[130]),
        .Q(\Head_reg[158]_0 [129]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[131] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[131]),
        .Q(\Head_reg[158]_0 [130]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[132] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[132]),
        .Q(\Head_reg[158]_0 [131]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[133] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[133]),
        .Q(\Head_reg[158]_0 [132]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[134] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[134]),
        .Q(\Head_reg[158]_0 [133]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[135] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[135]),
        .Q(\Head_reg[158]_0 [134]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[136] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[136]),
        .Q(\Head_reg[158]_0 [135]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[137] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[137]),
        .Q(\Head_reg[158]_0 [136]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[138] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[138]),
        .Q(\Head_reg[158]_0 [137]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[139] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[139]),
        .Q(\Head_reg[158]_0 [138]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[13]),
        .Q(\Head_reg[158]_0 [12]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[140] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[140]),
        .Q(\Head_reg[158]_0 [139]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[141] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[141]),
        .Q(\Head_reg[158]_0 [140]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[142] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[142]),
        .Q(\Head_reg[158]_0 [141]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[143] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[143]),
        .Q(\Head_reg[158]_0 [142]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[144] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[144]),
        .Q(\Head_reg[158]_0 [143]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[145] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[145]),
        .Q(\Head_reg[158]_0 [144]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[146] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[146]),
        .Q(\Head_reg[158]_0 [145]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[147] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[147]),
        .Q(\Head_reg[158]_0 [146]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[148] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[148]),
        .Q(\Head_reg[158]_0 [147]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[149] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[149]),
        .Q(\Head_reg[158]_0 [148]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[14]),
        .Q(\Head_reg[158]_0 [13]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[150] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[150]),
        .Q(\Head_reg[158]_0 [149]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[151] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[151]),
        .Q(\Head_reg[158]_0 [150]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[152] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[152]),
        .Q(\Head_reg[158]_0 [151]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[153] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[153]),
        .Q(\Head_reg[158]_0 [152]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[154] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[154]),
        .Q(\Head_reg[158]_0 [153]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[155] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[155]),
        .Q(\Head_reg[158]_0 [154]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[156] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[156]),
        .Q(\Head_reg[158]_0 [155]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[157] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[157]),
        .Q(\Head_reg[158]_0 [156]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[158] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[158]),
        .Q(\Head_reg[158]_0 [157]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[15]),
        .Q(\Head_reg[158]_0 [14]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[16] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[16]),
        .Q(\Head_reg[158]_0 [15]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[17] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[17]),
        .Q(\Head_reg[158]_0 [16]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[18]),
        .Q(\Head_reg[158]_0 [17]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[19]),
        .Q(\Head_reg[158]_0 [18]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[1] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[1]),
        .Q(\Head_reg[158]_0 [1]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[20]),
        .Q(\Head_reg[158]_0 [19]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[21]),
        .Q(\Head_reg[158]_0 [20]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[22] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[22]),
        .Q(\Head_reg[158]_0 [21]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[23] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[23]),
        .Q(\Head_reg[158]_0 [22]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[24] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[24]),
        .Q(\Head_reg[158]_0 [23]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[25] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[25]),
        .Q(\Head_reg[158]_0 [24]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[26] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[26]),
        .Q(\Head_reg[158]_0 [25]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[27] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[27]),
        .Q(\Head_reg[158]_0 [26]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[28] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[28]),
        .Q(\Head_reg[158]_0 [27]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[29] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[29]),
        .Q(\Head_reg[158]_0 [28]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[30] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[30]),
        .Q(\Head_reg[158]_0 [29]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[31] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[31]),
        .Q(\Head_reg[158]_0 [30]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[32] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[32]),
        .Q(\Head_reg[158]_0 [31]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[33] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[33]),
        .Q(\Head_reg[158]_0 [32]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[34] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[34]),
        .Q(\Head_reg[158]_0 [33]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[35] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[35]),
        .Q(\Head_reg[158]_0 [34]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[36] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[36]),
        .Q(\Head_reg[158]_0 [35]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[37] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[37]),
        .Q(\Head_reg[158]_0 [36]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[38] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[38]),
        .Q(\Head_reg[158]_0 [37]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[39] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[39]),
        .Q(\Head_reg[158]_0 [38]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[3] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[3]),
        .Q(\Head_reg[158]_0 [2]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[40] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[40]),
        .Q(\Head_reg[158]_0 [39]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[41] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[41]),
        .Q(\Head_reg[158]_0 [40]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[42] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[42]),
        .Q(\Head_reg[158]_0 [41]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[43] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[43]),
        .Q(\Head_reg[158]_0 [42]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[44] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[44]),
        .Q(\Head_reg[158]_0 [43]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[45] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[45]),
        .Q(\Head_reg[158]_0 [44]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[46] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[46]),
        .Q(\Head_reg[158]_0 [45]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[47] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[47]),
        .Q(\Head_reg[158]_0 [46]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[48] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[48]),
        .Q(\Head_reg[158]_0 [47]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[49] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[49]),
        .Q(\Head_reg[158]_0 [48]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[4] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[4]),
        .Q(\Head_reg[158]_0 [3]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[50] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[50]),
        .Q(\Head_reg[158]_0 [49]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[51] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[51]),
        .Q(\Head_reg[158]_0 [50]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[52] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[52]),
        .Q(\Head_reg[158]_0 [51]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[53] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[53]),
        .Q(\Head_reg[158]_0 [52]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[54] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[54]),
        .Q(\Head_reg[158]_0 [53]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[55] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[55]),
        .Q(\Head_reg[158]_0 [54]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[56] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[56]),
        .Q(\Head_reg[158]_0 [55]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[57] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[57]),
        .Q(\Head_reg[158]_0 [56]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[58] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[58]),
        .Q(\Head_reg[158]_0 [57]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[59] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[59]),
        .Q(\Head_reg[158]_0 [58]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[5] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[5]),
        .Q(\Head_reg[158]_0 [4]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[60]),
        .Q(\Head_reg[158]_0 [59]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[61]),
        .Q(\Head_reg[158]_0 [60]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[62]),
        .Q(\Head_reg[158]_0 [61]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[63]),
        .Q(\Head_reg[158]_0 [62]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[64] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[64]),
        .Q(\Head_reg[158]_0 [63]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[65] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[65]),
        .Q(\Head_reg[158]_0 [64]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[66]),
        .Q(\Head_reg[158]_0 [65]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[67]),
        .Q(\Head_reg[158]_0 [66]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[68]),
        .Q(\Head_reg[158]_0 [67]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[69]),
        .Q(\Head_reg[158]_0 [68]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[6] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[6]),
        .Q(\Head_reg[158]_0 [5]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[70]),
        .Q(\Head_reg[158]_0 [69]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[71]),
        .Q(\Head_reg[158]_0 [70]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[72]),
        .Q(\Head_reg[158]_0 [71]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[73]),
        .Q(\Head_reg[158]_0 [72]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[74] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[74]),
        .Q(\Head_reg[158]_0 [73]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[75] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[75]),
        .Q(\Head_reg[158]_0 [74]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[76] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[76]),
        .Q(\Head_reg[158]_0 [75]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[77] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[77]),
        .Q(\Head_reg[158]_0 [76]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[78] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[78]),
        .Q(\Head_reg[158]_0 [77]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[79] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[79]),
        .Q(\Head_reg[158]_0 [78]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[7] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[7]),
        .Q(\Head_reg[158]_0 [6]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[80] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[80]),
        .Q(\Head_reg[158]_0 [79]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[81] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[81]),
        .Q(\Head_reg[158]_0 [80]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[82] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[82]),
        .Q(\Head_reg[158]_0 [81]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[83] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[83]),
        .Q(\Head_reg[158]_0 [82]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[84] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[84]),
        .Q(\Head_reg[158]_0 [83]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[85] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[85]),
        .Q(\Head_reg[158]_0 [84]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[86] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[86]),
        .Q(\Head_reg[158]_0 [85]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[87] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[87]),
        .Q(\Head_reg[158]_0 [86]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[88] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[88]),
        .Q(\Head_reg[158]_0 [87]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[89] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[89]),
        .Q(\Head_reg[158]_0 [88]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[8] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[8]),
        .Q(\Head_reg[158]_0 [7]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[90]),
        .Q(\Head_reg[158]_0 [89]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[91]),
        .Q(\Head_reg[158]_0 [90]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[92]),
        .Q(\Head_reg[158]_0 [91]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[93]),
        .Q(\Head_reg[158]_0 [92]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[94] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[94]),
        .Q(\Head_reg[158]_0 [93]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[95] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[95]),
        .Q(\Head_reg[158]_0 [94]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[96] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[96]),
        .Q(\Head_reg[158]_0 [95]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[97] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[97]),
        .Q(\Head_reg[158]_0 [96]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[98] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[98]),
        .Q(\Head_reg[158]_0 [97]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[99] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[99]),
        .Q(\Head_reg[158]_0 [98]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \Head_reg[9] 
       (.C(user_clk),
        .CE(\Head[158]_i_1_n_0 ),
        .D(p_0_in1_in[9]),
        .Q(\Head_reg[158]_0 [8]),
        .R(\RdPtr[2]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_7_0_5
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[1:0]),
        .DIB(DataIn[3:2]),
        .DIC(DataIn[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[1:0]),
        .DOB({Head0[3],MemArray_reg_0_7_0_5_n_3}),
        .DOC(Head0[5:4]),
        .DOD(NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_102_107" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "102" *) 
  (* ram_slice_end = "107" *) 
  RAM32M MemArray_reg_0_7_102_107
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[103:102]),
        .DIB(DataIn[105:104]),
        .DIC(DataIn[107:106]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[103:102]),
        .DOB(Head0[105:104]),
        .DOC(Head0[107:106]),
        .DOD(NLW_MemArray_reg_0_7_102_107_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_108_113" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "108" *) 
  (* ram_slice_end = "113" *) 
  RAM32M MemArray_reg_0_7_108_113
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[109:108]),
        .DIB(DataIn[111:110]),
        .DIC(DataIn[113:112]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[109:108]),
        .DOB(Head0[111:110]),
        .DOC(Head0[113:112]),
        .DOD(NLW_MemArray_reg_0_7_108_113_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_114_119" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "114" *) 
  (* ram_slice_end = "119" *) 
  RAM32M MemArray_reg_0_7_114_119
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[115:114]),
        .DIB(DataIn[117:116]),
        .DIC(DataIn[119:118]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[115:114]),
        .DOB(Head0[117:116]),
        .DOC(Head0[119:118]),
        .DOD(NLW_MemArray_reg_0_7_114_119_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_120_125" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "120" *) 
  (* ram_slice_end = "125" *) 
  RAM32M MemArray_reg_0_7_120_125
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[121:120]),
        .DIB(DataIn[123:122]),
        .DIC(DataIn[125:124]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[121:120]),
        .DOB(Head0[123:122]),
        .DOC(Head0[125:124]),
        .DOD(NLW_MemArray_reg_0_7_120_125_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_126_131" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "126" *) 
  (* ram_slice_end = "131" *) 
  RAM32M MemArray_reg_0_7_126_131
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[127:126]),
        .DIB(DataIn[129:128]),
        .DIC(DataIn[131:130]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[127:126]),
        .DOB(Head0[129:128]),
        .DOC(Head0[131:130]),
        .DOD(NLW_MemArray_reg_0_7_126_131_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_7_12_17
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[13:12]),
        .DIB(DataIn[15:14]),
        .DIC(DataIn[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[13:12]),
        .DOB(Head0[15:14]),
        .DOC(Head0[17:16]),
        .DOD(NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_132_137" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "132" *) 
  (* ram_slice_end = "137" *) 
  RAM32M MemArray_reg_0_7_132_137
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[133:132]),
        .DIB(DataIn[135:134]),
        .DIC(DataIn[137:136]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[133:132]),
        .DOB(Head0[135:134]),
        .DOC(Head0[137:136]),
        .DOD(NLW_MemArray_reg_0_7_132_137_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_138_143" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "138" *) 
  (* ram_slice_end = "143" *) 
  RAM32M MemArray_reg_0_7_138_143
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[139:138]),
        .DIB(DataIn[141:140]),
        .DIC(DataIn[143:142]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[139:138]),
        .DOB(Head0[141:140]),
        .DOC(Head0[143:142]),
        .DOD(NLW_MemArray_reg_0_7_138_143_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_144_149" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "144" *) 
  (* ram_slice_end = "149" *) 
  RAM32M MemArray_reg_0_7_144_149
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[145:144]),
        .DIB(DataIn[147:146]),
        .DIC(DataIn[149:148]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[145:144]),
        .DOB(Head0[147:146]),
        .DOC(Head0[149:148]),
        .DOD(NLW_MemArray_reg_0_7_144_149_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_150_155" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "150" *) 
  (* ram_slice_end = "155" *) 
  RAM32M MemArray_reg_0_7_150_155
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[151:150]),
        .DIB(DataIn[153:152]),
        .DIC(DataIn[155:154]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[151:150]),
        .DOB(Head0[153:152]),
        .DOC(Head0[155:154]),
        .DOD(NLW_MemArray_reg_0_7_150_155_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_156_158" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "156" *) 
  (* ram_slice_end = "158" *) 
  RAM32M MemArray_reg_0_7_156_158
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[157:156]),
        .DIB({1'b0,DataIn[158]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[157:156]),
        .DOB({NLW_MemArray_reg_0_7_156_158_DOB_UNCONNECTED[1],Head0[158]}),
        .DOC(NLW_MemArray_reg_0_7_156_158_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_7_156_158_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_7_18_23
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[19:18]),
        .DIB(DataIn[21:20]),
        .DIC(DataIn[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[19:18]),
        .DOB(Head0[21:20]),
        .DOC(Head0[23:22]),
        .DOD(NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_24_29" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M MemArray_reg_0_7_24_29
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[25:24]),
        .DIB(DataIn[27:26]),
        .DIC(DataIn[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[25:24]),
        .DOB(Head0[27:26]),
        .DOC(Head0[29:28]),
        .DOD(NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_30_35" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M MemArray_reg_0_7_30_35
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[31:30]),
        .DIB(DataIn[33:32]),
        .DIC(DataIn[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[31:30]),
        .DOB(Head0[33:32]),
        .DOC(Head0[35:34]),
        .DOD(NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_36_41" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M MemArray_reg_0_7_36_41
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[37:36]),
        .DIB(DataIn[39:38]),
        .DIC(DataIn[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[37:36]),
        .DOB(Head0[39:38]),
        .DOC(Head0[41:40]),
        .DOD(NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_42_47" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M MemArray_reg_0_7_42_47
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[43:42]),
        .DIB(DataIn[45:44]),
        .DIC(DataIn[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[43:42]),
        .DOB(Head0[45:44]),
        .DOC(Head0[47:46]),
        .DOD(NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_48_53" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M MemArray_reg_0_7_48_53
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[49:48]),
        .DIB(DataIn[51:50]),
        .DIC(DataIn[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[49:48]),
        .DOB(Head0[51:50]),
        .DOC(Head0[53:52]),
        .DOD(NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_54_59" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M MemArray_reg_0_7_54_59
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[55:54]),
        .DIB(DataIn[57:56]),
        .DIC(DataIn[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[55:54]),
        .DOB(Head0[57:56]),
        .DOC(Head0[59:58]),
        .DOD(NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_60_65" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M MemArray_reg_0_7_60_65
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[61:60]),
        .DIB(DataIn[63:62]),
        .DIC(DataIn[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[61:60]),
        .DOB(Head0[63:62]),
        .DOC(Head0[65:64]),
        .DOD(NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_66_71" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M MemArray_reg_0_7_66_71
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[67:66]),
        .DIB(DataIn[69:68]),
        .DIC(DataIn[71:70]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[67:66]),
        .DOB(Head0[69:68]),
        .DOC(Head0[71:70]),
        .DOD(NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_7_6_11
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[7:6]),
        .DIB(DataIn[9:8]),
        .DIC(DataIn[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[7:6]),
        .DOB(Head0[9:8]),
        .DOC(Head0[11:10]),
        .DOD(NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_72_77" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M MemArray_reg_0_7_72_77
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[73:72]),
        .DIB(DataIn[75:74]),
        .DIC(DataIn[77:76]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[73:72]),
        .DOB(Head0[75:74]),
        .DOC(Head0[77:76]),
        .DOD(NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_78_83" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "83" *) 
  RAM32M MemArray_reg_0_7_78_83
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[79:78]),
        .DIB(DataIn[81:80]),
        .DIC(DataIn[83:82]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[79:78]),
        .DOB(Head0[81:80]),
        .DOC(Head0[83:82]),
        .DOD(NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_84_89" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "84" *) 
  (* ram_slice_end = "89" *) 
  RAM32M MemArray_reg_0_7_84_89
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[85:84]),
        .DIB(DataIn[87:86]),
        .DIC(DataIn[89:88]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[85:84]),
        .DOB(Head0[87:86]),
        .DOC(Head0[89:88]),
        .DOD(NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_90_95" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "90" *) 
  (* ram_slice_end = "95" *) 
  RAM32M MemArray_reg_0_7_90_95
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[91:90]),
        .DIB(DataIn[93:92]),
        .DIC(DataIn[95:94]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[91:90]),
        .DOB(Head0[93:92]),
        .DOC(Head0[95:94]),
        .DOD(NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_96_101" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "96" *) 
  (* ram_slice_end = "101" *) 
  RAM32M MemArray_reg_0_7_96_101
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[97:96]),
        .DIB(DataIn[99:98]),
        .DIC(DataIn[101:100]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[97:96]),
        .DOB(Head0[99:98]),
        .DOC(Head0[101:100]),
        .DOD(NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  LUT6 #(
    .INIT(64'h5656565656565666)) 
    \RdPtr[0]_i_1__0 
       (.I0(RdPtr[0]),
        .I1(Head1),
        .I2(empty_ff_reg_6),
        .I3(\FifoCntrRd_reg[1]_0 [1]),
        .I4(FifoCntrRd_reg[2]),
        .I5(FifoCntrRd_reg[3]),
        .O(RdPtr__0[0]));
  LUT5 #(
    .INIT(32'h557FAA80)) 
    \RdPtr[1]_i_1__0 
       (.I0(RdPtr[0]),
        .I1(\RdPtr[2]_i_4_n_0 ),
        .I2(empty_ff_reg_6),
        .I3(Head1),
        .I4(RdPtr[1]),
        .O(RdPtr__0[1]));
  LUT3 #(
    .INIT(8'hFE)) 
    \RdPtr[2]_i_1 
       (.I0(rrq_dsc_ld_901_reg_rep__3),
        .I1(ctl_rst),
        .I2(evt_idl_stp_vld_nn1),
        .O(\RdPtr[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5777FFFFA8880000)) 
    \RdPtr[2]_i_2 
       (.I0(RdPtr[1]),
        .I1(Head1),
        .I2(empty_ff_reg_6),
        .I3(\RdPtr[2]_i_4_n_0 ),
        .I4(RdPtr[0]),
        .I5(RdPtr[2]),
        .O(RdPtr__0[2]));
  LUT6 #(
    .INIT(64'h000000000000008A)) 
    \RdPtr[2]_i_3 
       (.I0(dsc_ch_vld),
        .I1(empty_ff_reg_6),
        .I2(\FifoCntrRd_reg[1]_0 [0]),
        .I3(\FifoCntrRd_reg[1]_0 [1]),
        .I4(FifoCntrRd_reg[2]),
        .I5(FifoCntrRd_reg[3]),
        .O(Head1));
  (* SOFT_HLUTNM = "soft_lutpair802" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \RdPtr[2]_i_4 
       (.I0(FifoCntrRd_reg[3]),
        .I1(FifoCntrRd_reg[2]),
        .I2(\FifoCntrRd_reg[1]_0 [1]),
        .O(\RdPtr[2]_i_4_n_0 ));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[0]),
        .Q(RdPtr[0]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(RdPtr[1]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \RdPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[2]),
        .Q(RdPtr[2]),
        .R(\RdPtr[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \WrPtr[2]_i_1 
       (.I0(\WrPtr_reg[1]_0 [1]),
        .I1(\WrPtr_reg[1]_0 [0]),
        .I2(\FifoCntrRd_reg[2]_0 ),
        .I3(dsc_acc_mgc_nn1),
        .I4(dsc_acc_done_nn1),
        .I5(WrPtr),
        .O(WrPtr__0));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr_reg[1]_1 [0]),
        .Q(\WrPtr_reg[1]_0 [0]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr_reg[1]_1 [1]),
        .Q(\WrPtr_reg[1]_0 [1]),
        .R(\RdPtr[2]_i_1_n_0 ));
  FDRE \WrPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0),
        .Q(WrPtr),
        .R(\RdPtr[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FAFAFAF8)) 
    almost_full_ff_i_1
       (.I0(FifoCntrWr_reg[2]),
        .I1(\FifoCntrWr_reg[1]_0 [1]),
        .I2(FifoCntrWr_reg[3]),
        .I3(dsc_ch_vld),
        .I4(\FifoCntrWr_reg[1]_0 [0]),
        .I5(\RdPtr[2]_i_1_n_0 ),
        .O(almost_full_ff_i_1_n_0));
  FDRE almost_full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(almost_full_ff_i_1_n_0),
        .Q(almost_full_ff_reg_0),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hB)) 
    dsc_aln_nn1_i_1__0
       (.I0(dsc_aln_nn1_i_2_n_0),
        .I1(out),
        .O(ctl_non_inc_nn1_reg));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    dsc_aln_nn1_i_2
       (.I0(\Head_reg[158]_0 [95]),
        .I1(\Head_reg[158]_0 [30]),
        .I2(\Head_reg[158]_0 [31]),
        .I3(\Head_reg[158]_0 [94]),
        .I4(\Head_reg[158]_0 [32]),
        .I5(\Head_reg[158]_0 [96]),
        .O(dsc_aln_nn1_i_2_n_0));
  LUT3 #(
    .INIT(8'h95)) 
    \dsc_mrs_dst_nn1[12]_i_3 
       (.I0(cfg_mrs_nn1[4]),
        .I1(\Head_reg[158]_0 [41]),
        .I2(\dsc_mrs_dst_nn1_reg[12] [4]),
        .O(\dsc_mrs_dst_nn1[12]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \dsc_mrs_dst_nn1[12]_i_4 
       (.I0(cfg_mrs_nn1[3]),
        .I1(\Head_reg[158]_0 [40]),
        .I2(\dsc_mrs_dst_nn1_reg[12] [3]),
        .O(\dsc_mrs_dst_nn1[12]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \dsc_mrs_dst_nn1[12]_i_5 
       (.I0(cfg_mrs_nn1[2]),
        .I1(\Head_reg[158]_0 [39]),
        .I2(\dsc_mrs_dst_nn1_reg[12] [2]),
        .O(\dsc_mrs_dst_nn1[12]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[4]_i_2 
       (.I0(\Head_reg[158]_0 [30]),
        .O(\dsc_mrs_dst_nn1[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[4]_i_3 
       (.I0(\Head_reg[158]_0 [34]),
        .O(\dsc_mrs_dst_nn1[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[4]_i_4 
       (.I0(\Head_reg[158]_0 [33]),
        .O(\dsc_mrs_dst_nn1[4]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[4]_i_5 
       (.I0(\Head_reg[158]_0 [32]),
        .O(\dsc_mrs_dst_nn1[4]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[4]_i_6 
       (.I0(\Head_reg[158]_0 [31]),
        .O(\dsc_mrs_dst_nn1[4]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \dsc_mrs_dst_nn1[8]_i_2 
       (.I0(cfg_mrs_nn1[1]),
        .I1(\Head_reg[158]_0 [38]),
        .I2(\dsc_mrs_dst_nn1_reg[12] [1]),
        .O(\dsc_mrs_dst_nn1[8]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \dsc_mrs_dst_nn1[8]_i_3 
       (.I0(cfg_mrs_nn1[0]),
        .I1(\Head_reg[158]_0 [37]),
        .I2(\dsc_mrs_dst_nn1_reg[12] [0]),
        .O(\dsc_mrs_dst_nn1[8]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[8]_i_4 
       (.I0(\Head_reg[158]_0 [36]),
        .O(\dsc_mrs_dst_nn1[8]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[8]_i_5 
       (.I0(\Head_reg[158]_0 [35]),
        .O(\dsc_mrs_dst_nn1[8]_i_5_n_0 ));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \dsc_mrs_dst_nn1_reg[12]_i_1 
       (.CI(\dsc_mrs_dst_nn1_reg[8]_i_1_n_0 ),
        .CO({\NLW_dsc_mrs_dst_nn1_reg[12]_i_1_CO_UNCONNECTED [3],\dsc_mrs_dst_nn1_reg[12]_i_1_n_1 ,\dsc_mrs_dst_nn1_reg[12]_i_1_n_2 ,\dsc_mrs_dst_nn1_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,cfg_mrs_nn1[4:2]}),
        .O(\cfg_mrs_nn1_reg[11] [11:8]),
        .S({S,\dsc_mrs_dst_nn1[12]_i_3_n_0 ,\dsc_mrs_dst_nn1[12]_i_4_n_0 ,\dsc_mrs_dst_nn1[12]_i_5_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \dsc_mrs_dst_nn1_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\dsc_mrs_dst_nn1_reg[4]_i_1_n_0 ,\dsc_mrs_dst_nn1_reg[4]_i_1_n_1 ,\dsc_mrs_dst_nn1_reg[4]_i_1_n_2 ,\dsc_mrs_dst_nn1_reg[4]_i_1_n_3 }),
        .CYINIT(\dsc_mrs_dst_nn1[4]_i_2_n_0 ),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\cfg_mrs_nn1_reg[11] [3:0]),
        .S({\dsc_mrs_dst_nn1[4]_i_3_n_0 ,\dsc_mrs_dst_nn1[4]_i_4_n_0 ,\dsc_mrs_dst_nn1[4]_i_5_n_0 ,\dsc_mrs_dst_nn1[4]_i_6_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \dsc_mrs_dst_nn1_reg[8]_i_1 
       (.CI(\dsc_mrs_dst_nn1_reg[4]_i_1_n_0 ),
        .CO({\dsc_mrs_dst_nn1_reg[8]_i_1_n_0 ,\dsc_mrs_dst_nn1_reg[8]_i_1_n_1 ,\dsc_mrs_dst_nn1_reg[8]_i_1_n_2 ,\dsc_mrs_dst_nn1_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({cfg_mrs_nn1[1:0],1'b0,1'b0}),
        .O(\cfg_mrs_nn1_reg[11] [7:4]),
        .S({\dsc_mrs_dst_nn1[8]_i_2_n_0 ,\dsc_mrs_dst_nn1[8]_i_3_n_0 ,\dsc_mrs_dst_nn1[8]_i_4_n_0 ,\dsc_mrs_dst_nn1[8]_i_5_n_0 }));
  LUT6 #(
    .INIT(64'hAAABAAAAAAABAAAB)) 
    empty_ff_i_1__0
       (.I0(empty_ff_i_2_n_0),
        .I1(FifoCntrRd_reg[3]),
        .I2(FifoCntrRd_reg[2]),
        .I3(\FifoCntrRd_reg[1]_0 [1]),
        .I4(empty_ff_reg_6),
        .I5(\FifoCntrRd_reg[1]_0 [0]),
        .O(empty_ff_i_1__0_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010000)) 
    empty_ff_i_2
       (.I0(\FifoCntrRd_reg[1]_0 [0]),
        .I1(FifoCntrRd_reg[3]),
        .I2(FifoCntrRd_reg[2]),
        .I3(\FifoCntrRd_reg[1]_0 [1]),
        .I4(dsc_ep_nn0),
        .I5(\RdPtr[2]_i_1_n_0 ),
        .O(empty_ff_i_2_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__0_n_0),
        .Q(dsc_ep_nn0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000002A222222)) 
    rrq_dsc_ld_901_i_1
       (.I0(rrq_dsc_ld_901_reg),
        .I1(rrq_dsc_ld_901_i_2__0_n_0),
        .I2(dsc_ep_nn0),
        .I3(rrq_eod_903),
        .I4(rrq_dsc_ld_901_reg_0),
        .I5(rrq_dsc_ld_901_reg_rep__3),
        .O(empty_ff_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair800" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    rrq_dsc_ld_901_i_2__0
       (.I0(dsc_ep_nn0),
        .I1(Q[2]),
        .I2(Q[1]),
        .O(rrq_dsc_ld_901_i_2__0_n_0));
  LUT6 #(
    .INIT(64'h000000002A222222)) 
    rrq_dsc_ld_901_rep_i_1
       (.I0(rrq_dsc_ld_901_reg),
        .I1(rrq_dsc_ld_901_i_2__0_n_0),
        .I2(dsc_ep_nn0),
        .I3(rrq_eod_903),
        .I4(rrq_dsc_ld_901_reg_0),
        .I5(rrq_dsc_ld_901_reg_rep__3),
        .O(empty_ff_reg_1));
  LUT6 #(
    .INIT(64'h000000002A222222)) 
    rrq_dsc_ld_901_rep_i_1__0
       (.I0(rrq_dsc_ld_901_reg),
        .I1(rrq_dsc_ld_901_i_2__0_n_0),
        .I2(dsc_ep_nn0),
        .I3(rrq_eod_903),
        .I4(rrq_dsc_ld_901_reg_0),
        .I5(rrq_dsc_ld_901_reg_rep__3),
        .O(empty_ff_reg_2));
  LUT6 #(
    .INIT(64'h000000002A222222)) 
    rrq_dsc_ld_901_rep_i_1__1
       (.I0(rrq_dsc_ld_901_reg),
        .I1(rrq_dsc_ld_901_i_2__0_n_0),
        .I2(dsc_ep_nn0),
        .I3(rrq_eod_903),
        .I4(rrq_dsc_ld_901_reg_0),
        .I5(rrq_dsc_ld_901_reg_rep__3),
        .O(empty_ff_reg_3));
  LUT6 #(
    .INIT(64'h000000002A222222)) 
    rrq_dsc_ld_901_rep_i_1__2
       (.I0(rrq_dsc_ld_901_reg),
        .I1(rrq_dsc_ld_901_i_2__0_n_0),
        .I2(dsc_ep_nn0),
        .I3(rrq_eod_903),
        .I4(rrq_dsc_ld_901_reg_0),
        .I5(rrq_dsc_ld_901_reg_rep__3),
        .O(empty_ff_reg_4));
  LUT6 #(
    .INIT(64'h000000002A222222)) 
    rrq_dsc_ld_901_rep_i_1__3
       (.I0(rrq_dsc_ld_901_reg),
        .I1(rrq_dsc_ld_901_i_2__0_n_0),
        .I2(dsc_ep_nn0),
        .I3(rrq_eod_903),
        .I4(rrq_dsc_ld_901_reg_0),
        .I5(rrq_dsc_ld_901_reg_rep__3),
        .O(empty_ff_reg_5));
  LUT6 #(
    .INIT(64'hAAAAAAAAAABAAAAA)) 
    \rrq_sm_cur_900[1]_i_1 
       (.I0(ctl_rst),
        .I1(\rrq_sm_cur_900_reg[1] ),
        .I2(dsc_ep_nn0),
        .I3(Q[2]),
        .I4(\rrq_sm_cur_900_reg[1]_0 ),
        .I5(\rrq_sm_cur_900_reg[1]_1 ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h8A88888888888888)) 
    \rrq_sm_cur_900[2]_i_1 
       (.I0(\rrq_sm_cur_900_reg[2] ),
        .I1(\rrq_sm_cur_900[2]_i_3_n_0 ),
        .I2(\rrq_sm_cur_900_reg[2]_0 ),
        .I3(dsc_ep_nn0),
        .I4(rrq_eod_903),
        .I5(\rrq_sm_cur_900_reg[2]_1 ),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair800" *) 
  LUT5 #(
    .INIT(32'h00110400)) 
    \rrq_sm_cur_900[2]_i_3 
       (.I0(Q[2]),
        .I1(dsc_ep_nn0),
        .I2(\rrq_sm_cur_900_reg[1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\rrq_sm_cur_900[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00AA00BF00AA00AA)) 
    \rrq_sm_cur_900[6]_i_1 
       (.I0(reg_sts_hlt_nn1),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(ctl_rst),
        .I4(\rrq_sm_cur_900_reg[6] ),
        .I5(\rrq_sm_cur_900[6]_i_3_n_0 ),
        .O(D[2]));
  LUT5 #(
    .INIT(32'h1111F111)) 
    \rrq_sm_cur_900[6]_i_3 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(\rrq_sm_cur_900_reg[1] ),
        .I3(dsc_ep_nn0),
        .I4(Q[3]),
        .O(\rrq_sm_cur_900[6]_i_3_n_0 ));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOHead" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOHead__parameterized2_43
   (almost_full_ff_reg_0,
    dsc_ep_nn0,
    D,
    dsc_aln_nn0,
    Q,
    \rrq_sm_cur_900_reg[1] ,
    \rrq_sm_cur_900_reg[1]_0 ,
    \rrq_sm_cur_900_reg[1]_1 ,
    \rrq_sm_cur_900_reg[1]_2 ,
    \rrq_sm_cur_900_reg[1]_3 ,
    \cfg_mrs_nn1_reg[11] ,
    \FifoCntrWr_reg[1]_0 ,
    \FifoCntrRd_reg[1]_0 ,
    \WrPtr_reg[1]_0 ,
    user_clk,
    ctl_rst,
    reg_sts_hlt_nn1,
    \rrq_sm_cur_900_reg[6] ,
    rrq_dsc_ld_901_reg_rep__2,
    evt_idl_stp_vld_nn1,
    out,
    \rrq_sm_cur_900_reg[6]_0 ,
    rrq_dsc_ld_901_reg,
    \rrq_sm_cur_900_reg[4] ,
    rrq_eod_903,
    \rrq_sm_cur_900_reg[4]_0 ,
    rrq_vld_903,
    rrq_dsc_ld_901_reg_rep__2_0,
    \rrq_sm_cur_900_reg[6]_1 ,
    \rrq_sm_cur_900_reg[6]_2 ,
    \rrq_sm_cur_900_reg[1]_4 ,
    \dsc_mrs_dst_nn1_reg[8] ,
    \dsc_mrs_dst_nn1_reg[8]_0 ,
    \dsc_mrs_dst_nn1_reg[12] ,
    \dsc_mrs_dst_nn1_reg[12]_0 ,
    \dsc_mrs_dst_nn1_reg[12]_1 ,
    S,
    \dsc_mrs_dst_nn1_reg[12]_2 ,
    dsc_ch_evld,
    DataIn,
    empty_ff_reg_0,
    dsc_ch_vld,
    \FifoCntrRd_reg[2]_0 ,
    dsc_acc_mgc_nn1,
    dsc_acc_done_nn1,
    \WrPtr_reg[1]_1 ,
    \FifoCntrRd_reg[3]_0 ,
    \FifoCntrRd_reg[1]_1 ,
    \FifoCntrWr_reg[3]_0 ,
    \FifoCntrWr_reg[1]_1 );
  output almost_full_ff_reg_0;
  output dsc_ep_nn0;
  output [2:0]D;
  output dsc_aln_nn0;
  output [157:0]Q;
  output \rrq_sm_cur_900_reg[1] ;
  output \rrq_sm_cur_900_reg[1]_0 ;
  output \rrq_sm_cur_900_reg[1]_1 ;
  output \rrq_sm_cur_900_reg[1]_2 ;
  output \rrq_sm_cur_900_reg[1]_3 ;
  output [11:0]\cfg_mrs_nn1_reg[11] ;
  output [1:0]\FifoCntrWr_reg[1]_0 ;
  output [1:0]\FifoCntrRd_reg[1]_0 ;
  output [1:0]\WrPtr_reg[1]_0 ;
  input user_clk;
  input ctl_rst;
  input reg_sts_hlt_nn1;
  input \rrq_sm_cur_900_reg[6] ;
  input rrq_dsc_ld_901_reg_rep__2;
  input evt_idl_stp_vld_nn1;
  input out;
  input [5:0]\rrq_sm_cur_900_reg[6]_0 ;
  input rrq_dsc_ld_901_reg;
  input \rrq_sm_cur_900_reg[4] ;
  input rrq_eod_903;
  input \rrq_sm_cur_900_reg[4]_0 ;
  input rrq_vld_903;
  input rrq_dsc_ld_901_reg_rep__2_0;
  input \rrq_sm_cur_900_reg[6]_1 ;
  input \rrq_sm_cur_900_reg[6]_2 ;
  input \rrq_sm_cur_900_reg[1]_4 ;
  input \dsc_mrs_dst_nn1_reg[8] ;
  input \dsc_mrs_dst_nn1_reg[8]_0 ;
  input \dsc_mrs_dst_nn1_reg[12] ;
  input \dsc_mrs_dst_nn1_reg[12]_0 ;
  input \dsc_mrs_dst_nn1_reg[12]_1 ;
  input [0:0]S;
  input [4:0]\dsc_mrs_dst_nn1_reg[12]_2 ;
  input [0:0]dsc_ch_evld;
  input [158:0]DataIn;
  input empty_ff_reg_0;
  input [0:0]dsc_ch_vld;
  input [0:0]\FifoCntrRd_reg[2]_0 ;
  input dsc_acc_mgc_nn1;
  input dsc_acc_done_nn1;
  input [1:0]\WrPtr_reg[1]_1 ;
  input [0:0]\FifoCntrRd_reg[3]_0 ;
  input [0:0]\FifoCntrRd_reg[1]_1 ;
  input [0:0]\FifoCntrWr_reg[3]_0 ;
  input [0:0]\FifoCntrWr_reg[1]_1 ;

  wire [2:0]D;
  wire [158:0]DataIn;
  wire \FifoCntrRd[0]_i_1__3_n_0 ;
  wire \FifoCntrRd[2]_i_1__2_n_0 ;
  wire \FifoCntrRd[3]_i_2__0_n_0 ;
  wire [3:2]FifoCntrRd_reg;
  wire [1:0]\FifoCntrRd_reg[1]_0 ;
  wire [0:0]\FifoCntrRd_reg[1]_1 ;
  wire [0:0]\FifoCntrRd_reg[2]_0 ;
  wire [0:0]\FifoCntrRd_reg[3]_0 ;
  wire \FifoCntrWr[0]_i_1__3_n_0 ;
  wire \FifoCntrWr[2]_i_1__3_n_0 ;
  wire \FifoCntrWr[3]_i_2__0_n_0 ;
  wire [3:2]FifoCntrWr_reg;
  wire [1:0]\FifoCntrWr_reg[1]_0 ;
  wire [0:0]\FifoCntrWr_reg[1]_1 ;
  wire [0:0]\FifoCntrWr_reg[3]_0 ;
  wire [158:0]Head0;
  wire Head1;
  wire \Head[158]_i_1__0_n_0 ;
  wire MemArray_reg_0_7_0_5_n_3;
  wire [157:0]Q;
  wire [2:0]RdPtr;
  wire \RdPtr[2]_i_1__0_n_0 ;
  wire \RdPtr[2]_i_4__0_n_0 ;
  wire [2:0]RdPtr__0;
  wire [0:0]S;
  wire [2:2]WrPtr;
  wire [2:2]WrPtr__0;
  wire [1:0]\WrPtr_reg[1]_0 ;
  wire [1:0]\WrPtr_reg[1]_1 ;
  wire almost_full_ff_i_1__0_n_0;
  wire almost_full_ff_reg_0;
  wire [11:0]\cfg_mrs_nn1_reg[11] ;
  wire ctl_rst;
  wire dsc_acc_done_nn1;
  wire dsc_acc_mgc_nn1;
  wire dsc_aln_nn0;
  wire dsc_aln_nn1_i_2__0_n_0;
  wire [0:0]dsc_ch_evld;
  wire [0:0]dsc_ch_vld;
  wire dsc_ep_nn0;
  wire \dsc_mrs_dst_nn1[12]_i_3__0_n_0 ;
  wire \dsc_mrs_dst_nn1[12]_i_4__0_n_0 ;
  wire \dsc_mrs_dst_nn1[12]_i_5__0_n_0 ;
  wire \dsc_mrs_dst_nn1[4]_i_2__0_n_0 ;
  wire \dsc_mrs_dst_nn1[4]_i_3__0_n_0 ;
  wire \dsc_mrs_dst_nn1[4]_i_4__0_n_0 ;
  wire \dsc_mrs_dst_nn1[4]_i_5__0_n_0 ;
  wire \dsc_mrs_dst_nn1[4]_i_6__0_n_0 ;
  wire \dsc_mrs_dst_nn1[8]_i_2__0_n_0 ;
  wire \dsc_mrs_dst_nn1[8]_i_3__0_n_0 ;
  wire \dsc_mrs_dst_nn1[8]_i_4__0_n_0 ;
  wire \dsc_mrs_dst_nn1[8]_i_5__0_n_0 ;
  wire \dsc_mrs_dst_nn1_reg[12] ;
  wire \dsc_mrs_dst_nn1_reg[12]_0 ;
  wire \dsc_mrs_dst_nn1_reg[12]_1 ;
  wire [4:0]\dsc_mrs_dst_nn1_reg[12]_2 ;
  wire \dsc_mrs_dst_nn1_reg[12]_i_1__0_n_1 ;
  wire \dsc_mrs_dst_nn1_reg[12]_i_1__0_n_2 ;
  wire \dsc_mrs_dst_nn1_reg[12]_i_1__0_n_3 ;
  wire \dsc_mrs_dst_nn1_reg[4]_i_1__0_n_0 ;
  wire \dsc_mrs_dst_nn1_reg[4]_i_1__0_n_1 ;
  wire \dsc_mrs_dst_nn1_reg[4]_i_1__0_n_2 ;
  wire \dsc_mrs_dst_nn1_reg[4]_i_1__0_n_3 ;
  wire \dsc_mrs_dst_nn1_reg[8] ;
  wire \dsc_mrs_dst_nn1_reg[8]_0 ;
  wire \dsc_mrs_dst_nn1_reg[8]_i_1__0_n_0 ;
  wire \dsc_mrs_dst_nn1_reg[8]_i_1__0_n_1 ;
  wire \dsc_mrs_dst_nn1_reg[8]_i_1__0_n_2 ;
  wire \dsc_mrs_dst_nn1_reg[8]_i_1__0_n_3 ;
  wire empty_ff_i_1__3_n_0;
  wire empty_ff_i_2__0_n_0;
  wire empty_ff_reg_0;
  wire evt_idl_stp_vld_nn1;
  wire out;
  wire [158:0]p_0_in1_in;
  wire reg_sts_hlt_nn1;
  wire rrq_dsc_ld_901_i_2_n_0;
  wire rrq_dsc_ld_901_reg;
  wire rrq_dsc_ld_901_reg_rep__2;
  wire rrq_dsc_ld_901_reg_rep__2_0;
  wire rrq_eod_903;
  wire \rrq_sm_cur_900[1]_i_2__0_n_0 ;
  wire \rrq_sm_cur_900[6]_i_3__0_n_0 ;
  wire \rrq_sm_cur_900_reg[1] ;
  wire \rrq_sm_cur_900_reg[1]_0 ;
  wire \rrq_sm_cur_900_reg[1]_1 ;
  wire \rrq_sm_cur_900_reg[1]_2 ;
  wire \rrq_sm_cur_900_reg[1]_3 ;
  wire \rrq_sm_cur_900_reg[1]_4 ;
  wire \rrq_sm_cur_900_reg[4] ;
  wire \rrq_sm_cur_900_reg[4]_0 ;
  wire \rrq_sm_cur_900_reg[6] ;
  wire [5:0]\rrq_sm_cur_900_reg[6]_0 ;
  wire \rrq_sm_cur_900_reg[6]_1 ;
  wire \rrq_sm_cur_900_reg[6]_2 ;
  wire rrq_vld_903;
  wire user_clk;
  wire [1:0]NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_102_107_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_108_113_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_114_119_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_120_125_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_126_131_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_132_137_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_138_143_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_144_149_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_150_155_DOD_UNCONNECTED;
  wire [1:1]NLW_MemArray_reg_0_7_156_158_DOB_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_156_158_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_156_158_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED;
  wire [3:3]\NLW_dsc_mrs_dst_nn1_reg[12]_i_1__0_CO_UNCONNECTED ;

  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__3 
       (.I0(\FifoCntrRd_reg[1]_0 [0]),
        .O(\FifoCntrRd[0]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAA9555)) 
    \FifoCntrRd[2]_i_1__2 
       (.I0(FifoCntrRd_reg[2]),
        .I1(\FifoCntrRd_reg[2]_0 ),
        .I2(dsc_acc_mgc_nn1),
        .I3(dsc_acc_done_nn1),
        .I4(\FifoCntrRd_reg[1]_0 [1]),
        .I5(\FifoCntrRd_reg[1]_0 [0]),
        .O(\FifoCntrRd[2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair466" *) 
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \FifoCntrRd[3]_i_2__0 
       (.I0(FifoCntrRd_reg[3]),
        .I1(dsc_ch_vld),
        .I2(\FifoCntrRd_reg[1]_0 [1]),
        .I3(\FifoCntrRd_reg[1]_0 [0]),
        .I4(FifoCntrRd_reg[2]),
        .O(\FifoCntrRd[3]_i_2__0_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd_reg[3]_0 ),
        .D(\FifoCntrRd[0]_i_1__3_n_0 ),
        .Q(\FifoCntrRd_reg[1]_0 [0]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd_reg[3]_0 ),
        .D(\FifoCntrRd_reg[1]_1 ),
        .Q(\FifoCntrRd_reg[1]_0 [1]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd_reg[3]_0 ),
        .D(\FifoCntrRd[2]_i_1__2_n_0 ),
        .Q(FifoCntrRd_reg[2]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \FifoCntrRd_reg[3] 
       (.C(user_clk),
        .CE(\FifoCntrRd_reg[3]_0 ),
        .D(\FifoCntrRd[3]_i_2__0_n_0 ),
        .Q(FifoCntrRd_reg[3]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__3 
       (.I0(\FifoCntrWr_reg[1]_0 [0]),
        .O(\FifoCntrWr[0]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair465" *) 
  LUT4 #(
    .INIT(16'h6AA9)) 
    \FifoCntrWr[2]_i_1__3 
       (.I0(FifoCntrWr_reg[2]),
        .I1(dsc_ch_evld),
        .I2(\FifoCntrWr_reg[1]_0 [1]),
        .I3(\FifoCntrWr_reg[1]_0 [0]),
        .O(\FifoCntrWr[2]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair465" *) 
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \FifoCntrWr[3]_i_2__0 
       (.I0(FifoCntrWr_reg[3]),
        .I1(dsc_ch_evld),
        .I2(\FifoCntrWr_reg[1]_0 [1]),
        .I3(\FifoCntrWr_reg[1]_0 [0]),
        .I4(FifoCntrWr_reg[2]),
        .O(\FifoCntrWr[3]_i_2__0_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[3]_0 ),
        .D(\FifoCntrWr[0]_i_1__3_n_0 ),
        .Q(\FifoCntrWr_reg[1]_0 [0]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[3]_0 ),
        .D(\FifoCntrWr_reg[1]_1 ),
        .Q(\FifoCntrWr_reg[1]_0 [1]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[3]_0 ),
        .D(\FifoCntrWr[2]_i_1__3_n_0 ),
        .Q(FifoCntrWr_reg[2]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \FifoCntrWr_reg[3] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[3]_0 ),
        .D(\FifoCntrWr[3]_i_2__0_n_0 ),
        .Q(FifoCntrWr_reg[3]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair467" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[0]_i_1__1 
       (.I0(DataIn[0]),
        .I1(Head1),
        .I2(Head0[0]),
        .O(p_0_in1_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair516" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[100]_i_1__3 
       (.I0(DataIn[100]),
        .I1(Head1),
        .I2(Head0[100]),
        .O(p_0_in1_in[100]));
  (* SOFT_HLUTNM = "soft_lutpair517" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[101]_i_1__3 
       (.I0(DataIn[101]),
        .I1(Head1),
        .I2(Head0[101]),
        .O(p_0_in1_in[101]));
  (* SOFT_HLUTNM = "soft_lutpair517" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[102]_i_1__3 
       (.I0(DataIn[102]),
        .I1(Head1),
        .I2(Head0[102]),
        .O(p_0_in1_in[102]));
  (* SOFT_HLUTNM = "soft_lutpair518" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[103]_i_1__3 
       (.I0(DataIn[103]),
        .I1(Head1),
        .I2(Head0[103]),
        .O(p_0_in1_in[103]));
  (* SOFT_HLUTNM = "soft_lutpair518" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[104]_i_1__3 
       (.I0(DataIn[104]),
        .I1(Head1),
        .I2(Head0[104]),
        .O(p_0_in1_in[104]));
  (* SOFT_HLUTNM = "soft_lutpair519" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[105]_i_1__3 
       (.I0(DataIn[105]),
        .I1(Head1),
        .I2(Head0[105]),
        .O(p_0_in1_in[105]));
  (* SOFT_HLUTNM = "soft_lutpair519" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[106]_i_1__3 
       (.I0(DataIn[106]),
        .I1(Head1),
        .I2(Head0[106]),
        .O(p_0_in1_in[106]));
  (* SOFT_HLUTNM = "soft_lutpair520" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[107]_i_1__3 
       (.I0(DataIn[107]),
        .I1(Head1),
        .I2(Head0[107]),
        .O(p_0_in1_in[107]));
  (* SOFT_HLUTNM = "soft_lutpair520" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[108]_i_1__3 
       (.I0(DataIn[108]),
        .I1(Head1),
        .I2(Head0[108]),
        .O(p_0_in1_in[108]));
  (* SOFT_HLUTNM = "soft_lutpair521" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[109]_i_1__3 
       (.I0(DataIn[109]),
        .I1(Head1),
        .I2(Head0[109]),
        .O(p_0_in1_in[109]));
  (* SOFT_HLUTNM = "soft_lutpair471" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[10]_i_1__2 
       (.I0(DataIn[10]),
        .I1(Head1),
        .I2(Head0[10]),
        .O(p_0_in1_in[10]));
  (* SOFT_HLUTNM = "soft_lutpair521" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[110]_i_1__3 
       (.I0(DataIn[110]),
        .I1(Head1),
        .I2(Head0[110]),
        .O(p_0_in1_in[110]));
  (* SOFT_HLUTNM = "soft_lutpair522" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[111]_i_1__3 
       (.I0(DataIn[111]),
        .I1(Head1),
        .I2(Head0[111]),
        .O(p_0_in1_in[111]));
  (* SOFT_HLUTNM = "soft_lutpair522" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[112]_i_1__2 
       (.I0(DataIn[112]),
        .I1(Head1),
        .I2(Head0[112]),
        .O(p_0_in1_in[112]));
  (* SOFT_HLUTNM = "soft_lutpair523" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[113]_i_1__2 
       (.I0(DataIn[113]),
        .I1(Head1),
        .I2(Head0[113]),
        .O(p_0_in1_in[113]));
  (* SOFT_HLUTNM = "soft_lutpair523" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[114]_i_1__2 
       (.I0(DataIn[114]),
        .I1(Head1),
        .I2(Head0[114]),
        .O(p_0_in1_in[114]));
  (* SOFT_HLUTNM = "soft_lutpair524" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[115]_i_1__2 
       (.I0(DataIn[115]),
        .I1(Head1),
        .I2(Head0[115]),
        .O(p_0_in1_in[115]));
  (* SOFT_HLUTNM = "soft_lutpair524" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[116]_i_1__2 
       (.I0(DataIn[116]),
        .I1(Head1),
        .I2(Head0[116]),
        .O(p_0_in1_in[116]));
  (* SOFT_HLUTNM = "soft_lutpair525" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[117]_i_1__2 
       (.I0(DataIn[117]),
        .I1(Head1),
        .I2(Head0[117]),
        .O(p_0_in1_in[117]));
  (* SOFT_HLUTNM = "soft_lutpair525" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[118]_i_1__2 
       (.I0(DataIn[118]),
        .I1(Head1),
        .I2(Head0[118]),
        .O(p_0_in1_in[118]));
  (* SOFT_HLUTNM = "soft_lutpair526" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[119]_i_1__2 
       (.I0(DataIn[119]),
        .I1(Head1),
        .I2(Head0[119]),
        .O(p_0_in1_in[119]));
  (* SOFT_HLUTNM = "soft_lutpair472" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[11]_i_1__2 
       (.I0(DataIn[11]),
        .I1(Head1),
        .I2(Head0[11]),
        .O(p_0_in1_in[11]));
  (* SOFT_HLUTNM = "soft_lutpair526" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[120]_i_1__0 
       (.I0(DataIn[120]),
        .I1(Head1),
        .I2(Head0[120]),
        .O(p_0_in1_in[120]));
  (* SOFT_HLUTNM = "soft_lutpair527" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[121]_i_1__0 
       (.I0(DataIn[121]),
        .I1(Head1),
        .I2(Head0[121]),
        .O(p_0_in1_in[121]));
  (* SOFT_HLUTNM = "soft_lutpair527" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[122]_i_1__0 
       (.I0(DataIn[122]),
        .I1(Head1),
        .I2(Head0[122]),
        .O(p_0_in1_in[122]));
  (* SOFT_HLUTNM = "soft_lutpair528" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[123]_i_1__0 
       (.I0(DataIn[123]),
        .I1(Head1),
        .I2(Head0[123]),
        .O(p_0_in1_in[123]));
  (* SOFT_HLUTNM = "soft_lutpair528" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[124]_i_1__0 
       (.I0(DataIn[124]),
        .I1(Head1),
        .I2(Head0[124]),
        .O(p_0_in1_in[124]));
  (* SOFT_HLUTNM = "soft_lutpair529" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[125]_i_1__0 
       (.I0(DataIn[125]),
        .I1(Head1),
        .I2(Head0[125]),
        .O(p_0_in1_in[125]));
  (* SOFT_HLUTNM = "soft_lutpair529" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[126]_i_1__0 
       (.I0(DataIn[126]),
        .I1(Head1),
        .I2(Head0[126]),
        .O(p_0_in1_in[126]));
  (* SOFT_HLUTNM = "soft_lutpair530" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[127]_i_1__0 
       (.I0(DataIn[127]),
        .I1(Head1),
        .I2(Head0[127]),
        .O(p_0_in1_in[127]));
  (* SOFT_HLUTNM = "soft_lutpair530" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[128]_i_1__0 
       (.I0(DataIn[128]),
        .I1(Head1),
        .I2(Head0[128]),
        .O(p_0_in1_in[128]));
  (* SOFT_HLUTNM = "soft_lutpair531" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[129]_i_1__0 
       (.I0(DataIn[129]),
        .I1(Head1),
        .I2(Head0[129]),
        .O(p_0_in1_in[129]));
  (* SOFT_HLUTNM = "soft_lutpair472" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[12]_i_1__2 
       (.I0(DataIn[12]),
        .I1(Head1),
        .I2(Head0[12]),
        .O(p_0_in1_in[12]));
  (* SOFT_HLUTNM = "soft_lutpair531" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[130]_i_1__0 
       (.I0(DataIn[130]),
        .I1(Head1),
        .I2(Head0[130]),
        .O(p_0_in1_in[130]));
  (* SOFT_HLUTNM = "soft_lutpair532" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[131]_i_1__0 
       (.I0(DataIn[131]),
        .I1(Head1),
        .I2(Head0[131]),
        .O(p_0_in1_in[131]));
  (* SOFT_HLUTNM = "soft_lutpair532" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[132]_i_1__0 
       (.I0(DataIn[132]),
        .I1(Head1),
        .I2(Head0[132]),
        .O(p_0_in1_in[132]));
  (* SOFT_HLUTNM = "soft_lutpair533" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[133]_i_1__0 
       (.I0(DataIn[133]),
        .I1(Head1),
        .I2(Head0[133]),
        .O(p_0_in1_in[133]));
  (* SOFT_HLUTNM = "soft_lutpair533" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[134]_i_1__0 
       (.I0(DataIn[134]),
        .I1(Head1),
        .I2(Head0[134]),
        .O(p_0_in1_in[134]));
  (* SOFT_HLUTNM = "soft_lutpair534" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[135]_i_1__0 
       (.I0(DataIn[135]),
        .I1(Head1),
        .I2(Head0[135]),
        .O(p_0_in1_in[135]));
  (* SOFT_HLUTNM = "soft_lutpair534" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[136]_i_1__0 
       (.I0(DataIn[136]),
        .I1(Head1),
        .I2(Head0[136]),
        .O(p_0_in1_in[136]));
  (* SOFT_HLUTNM = "soft_lutpair535" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[137]_i_1__0 
       (.I0(DataIn[137]),
        .I1(Head1),
        .I2(Head0[137]),
        .O(p_0_in1_in[137]));
  (* SOFT_HLUTNM = "soft_lutpair535" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[138]_i_1__0 
       (.I0(DataIn[138]),
        .I1(Head1),
        .I2(Head0[138]),
        .O(p_0_in1_in[138]));
  (* SOFT_HLUTNM = "soft_lutpair536" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[139]_i_1__0 
       (.I0(DataIn[139]),
        .I1(Head1),
        .I2(Head0[139]),
        .O(p_0_in1_in[139]));
  (* SOFT_HLUTNM = "soft_lutpair473" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[13]_i_1__2 
       (.I0(DataIn[13]),
        .I1(Head1),
        .I2(Head0[13]),
        .O(p_0_in1_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair536" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[140]_i_1__0 
       (.I0(DataIn[140]),
        .I1(Head1),
        .I2(Head0[140]),
        .O(p_0_in1_in[140]));
  (* SOFT_HLUTNM = "soft_lutpair537" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[141]_i_1__0 
       (.I0(DataIn[141]),
        .I1(Head1),
        .I2(Head0[141]),
        .O(p_0_in1_in[141]));
  (* SOFT_HLUTNM = "soft_lutpair537" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[142]_i_1__0 
       (.I0(DataIn[142]),
        .I1(Head1),
        .I2(Head0[142]),
        .O(p_0_in1_in[142]));
  (* SOFT_HLUTNM = "soft_lutpair538" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[143]_i_1__0 
       (.I0(DataIn[143]),
        .I1(Head1),
        .I2(Head0[143]),
        .O(p_0_in1_in[143]));
  (* SOFT_HLUTNM = "soft_lutpair538" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[144]_i_1__0 
       (.I0(DataIn[144]),
        .I1(Head1),
        .I2(Head0[144]),
        .O(p_0_in1_in[144]));
  (* SOFT_HLUTNM = "soft_lutpair539" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[145]_i_1__0 
       (.I0(DataIn[145]),
        .I1(Head1),
        .I2(Head0[145]),
        .O(p_0_in1_in[145]));
  (* SOFT_HLUTNM = "soft_lutpair539" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[146]_i_1__0 
       (.I0(DataIn[146]),
        .I1(Head1),
        .I2(Head0[146]),
        .O(p_0_in1_in[146]));
  (* SOFT_HLUTNM = "soft_lutpair540" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[147]_i_1__0 
       (.I0(DataIn[147]),
        .I1(Head1),
        .I2(Head0[147]),
        .O(p_0_in1_in[147]));
  (* SOFT_HLUTNM = "soft_lutpair540" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[148]_i_1__0 
       (.I0(DataIn[148]),
        .I1(Head1),
        .I2(Head0[148]),
        .O(p_0_in1_in[148]));
  (* SOFT_HLUTNM = "soft_lutpair541" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[149]_i_1__0 
       (.I0(DataIn[149]),
        .I1(Head1),
        .I2(Head0[149]),
        .O(p_0_in1_in[149]));
  (* SOFT_HLUTNM = "soft_lutpair473" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[14]_i_1__2 
       (.I0(DataIn[14]),
        .I1(Head1),
        .I2(Head0[14]),
        .O(p_0_in1_in[14]));
  (* SOFT_HLUTNM = "soft_lutpair541" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[150]_i_1__0 
       (.I0(DataIn[150]),
        .I1(Head1),
        .I2(Head0[150]),
        .O(p_0_in1_in[150]));
  (* SOFT_HLUTNM = "soft_lutpair542" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[151]_i_1__0 
       (.I0(DataIn[151]),
        .I1(Head1),
        .I2(Head0[151]),
        .O(p_0_in1_in[151]));
  (* SOFT_HLUTNM = "soft_lutpair542" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[152]_i_1__0 
       (.I0(DataIn[152]),
        .I1(Head1),
        .I2(Head0[152]),
        .O(p_0_in1_in[152]));
  (* SOFT_HLUTNM = "soft_lutpair543" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[153]_i_1__0 
       (.I0(DataIn[153]),
        .I1(Head1),
        .I2(Head0[153]),
        .O(p_0_in1_in[153]));
  (* SOFT_HLUTNM = "soft_lutpair543" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[154]_i_1__0 
       (.I0(DataIn[154]),
        .I1(Head1),
        .I2(Head0[154]),
        .O(p_0_in1_in[154]));
  (* SOFT_HLUTNM = "soft_lutpair544" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[155]_i_1__0 
       (.I0(DataIn[155]),
        .I1(Head1),
        .I2(Head0[155]),
        .O(p_0_in1_in[155]));
  (* SOFT_HLUTNM = "soft_lutpair544" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[156]_i_1__0 
       (.I0(DataIn[156]),
        .I1(Head1),
        .I2(Head0[156]),
        .O(p_0_in1_in[156]));
  (* SOFT_HLUTNM = "soft_lutpair545" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[157]_i_1__0 
       (.I0(DataIn[157]),
        .I1(Head1),
        .I2(Head0[157]),
        .O(p_0_in1_in[157]));
  LUT6 #(
    .INIT(64'hEEEEEEEEEEEEEEEF)) 
    \Head[158]_i_1__0 
       (.I0(empty_ff_reg_0),
        .I1(Head1),
        .I2(\FifoCntrRd_reg[1]_0 [0]),
        .I3(FifoCntrRd_reg[3]),
        .I4(FifoCntrRd_reg[2]),
        .I5(\FifoCntrRd_reg[1]_0 [1]),
        .O(\Head[158]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair545" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[158]_i_2__0 
       (.I0(DataIn[158]),
        .I1(Head1),
        .I2(Head0[158]),
        .O(p_0_in1_in[158]));
  (* SOFT_HLUTNM = "soft_lutpair474" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[15]_i_1__2 
       (.I0(DataIn[15]),
        .I1(Head1),
        .I2(Head0[15]),
        .O(p_0_in1_in[15]));
  (* SOFT_HLUTNM = "soft_lutpair474" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[16]_i_1__1 
       (.I0(DataIn[16]),
        .I1(Head1),
        .I2(Head0[16]),
        .O(p_0_in1_in[16]));
  (* SOFT_HLUTNM = "soft_lutpair475" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[17]_i_1__1 
       (.I0(DataIn[17]),
        .I1(Head1),
        .I2(Head0[17]),
        .O(p_0_in1_in[17]));
  (* SOFT_HLUTNM = "soft_lutpair475" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[18]_i_1__2 
       (.I0(DataIn[18]),
        .I1(Head1),
        .I2(Head0[18]),
        .O(p_0_in1_in[18]));
  (* SOFT_HLUTNM = "soft_lutpair476" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[19]_i_1__2 
       (.I0(DataIn[19]),
        .I1(Head1),
        .I2(Head0[19]),
        .O(p_0_in1_in[19]));
  (* SOFT_HLUTNM = "soft_lutpair467" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[1]_i_1__1 
       (.I0(DataIn[1]),
        .I1(Head1),
        .I2(Head0[1]),
        .O(p_0_in1_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair476" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[20]_i_1__3 
       (.I0(DataIn[20]),
        .I1(Head1),
        .I2(Head0[20]),
        .O(p_0_in1_in[20]));
  (* SOFT_HLUTNM = "soft_lutpair477" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[21]_i_1__3 
       (.I0(DataIn[21]),
        .I1(Head1),
        .I2(Head0[21]),
        .O(p_0_in1_in[21]));
  (* SOFT_HLUTNM = "soft_lutpair477" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[22]_i_1__2 
       (.I0(DataIn[22]),
        .I1(Head1),
        .I2(Head0[22]),
        .O(p_0_in1_in[22]));
  (* SOFT_HLUTNM = "soft_lutpair478" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[23]_i_1__2 
       (.I0(DataIn[23]),
        .I1(Head1),
        .I2(Head0[23]),
        .O(p_0_in1_in[23]));
  (* SOFT_HLUTNM = "soft_lutpair478" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[24]_i_1__2 
       (.I0(DataIn[24]),
        .I1(Head1),
        .I2(Head0[24]),
        .O(p_0_in1_in[24]));
  (* SOFT_HLUTNM = "soft_lutpair479" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[25]_i_1__2 
       (.I0(DataIn[25]),
        .I1(Head1),
        .I2(Head0[25]),
        .O(p_0_in1_in[25]));
  (* SOFT_HLUTNM = "soft_lutpair479" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[26]_i_1__2 
       (.I0(DataIn[26]),
        .I1(Head1),
        .I2(Head0[26]),
        .O(p_0_in1_in[26]));
  (* SOFT_HLUTNM = "soft_lutpair480" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[27]_i_1__2 
       (.I0(DataIn[27]),
        .I1(Head1),
        .I2(Head0[27]),
        .O(p_0_in1_in[27]));
  (* SOFT_HLUTNM = "soft_lutpair480" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[28]_i_1__2 
       (.I0(DataIn[28]),
        .I1(Head1),
        .I2(Head0[28]),
        .O(p_0_in1_in[28]));
  (* SOFT_HLUTNM = "soft_lutpair481" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[29]_i_1__2 
       (.I0(DataIn[29]),
        .I1(Head1),
        .I2(Head0[29]),
        .O(p_0_in1_in[29]));
  (* SOFT_HLUTNM = "soft_lutpair481" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[30]_i_1__1 
       (.I0(DataIn[30]),
        .I1(Head1),
        .I2(Head0[30]),
        .O(p_0_in1_in[30]));
  (* SOFT_HLUTNM = "soft_lutpair482" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[31]_i_1__1 
       (.I0(DataIn[31]),
        .I1(Head1),
        .I2(Head0[31]),
        .O(p_0_in1_in[31]));
  (* SOFT_HLUTNM = "soft_lutpair482" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[32]_i_1__1 
       (.I0(DataIn[32]),
        .I1(Head1),
        .I2(Head0[32]),
        .O(p_0_in1_in[32]));
  (* SOFT_HLUTNM = "soft_lutpair483" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[33]_i_1__0 
       (.I0(DataIn[33]),
        .I1(Head1),
        .I2(Head0[33]),
        .O(p_0_in1_in[33]));
  (* SOFT_HLUTNM = "soft_lutpair483" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[34]_i_1__0 
       (.I0(DataIn[34]),
        .I1(Head1),
        .I2(Head0[34]),
        .O(p_0_in1_in[34]));
  (* SOFT_HLUTNM = "soft_lutpair484" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[35]_i_1__0 
       (.I0(DataIn[35]),
        .I1(Head1),
        .I2(Head0[35]),
        .O(p_0_in1_in[35]));
  (* SOFT_HLUTNM = "soft_lutpair484" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[36]_i_1__0 
       (.I0(DataIn[36]),
        .I1(Head1),
        .I2(Head0[36]),
        .O(p_0_in1_in[36]));
  (* SOFT_HLUTNM = "soft_lutpair485" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[37]_i_1__1 
       (.I0(DataIn[37]),
        .I1(Head1),
        .I2(Head0[37]),
        .O(p_0_in1_in[37]));
  (* SOFT_HLUTNM = "soft_lutpair485" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[38]_i_1__1 
       (.I0(DataIn[38]),
        .I1(Head1),
        .I2(Head0[38]),
        .O(p_0_in1_in[38]));
  (* SOFT_HLUTNM = "soft_lutpair486" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[39]_i_1__1 
       (.I0(DataIn[39]),
        .I1(Head1),
        .I2(Head0[39]),
        .O(p_0_in1_in[39]));
  (* SOFT_HLUTNM = "soft_lutpair468" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[3]_i_1__1 
       (.I0(DataIn[3]),
        .I1(Head1),
        .I2(Head0[3]),
        .O(p_0_in1_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair486" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[40]_i_1__1 
       (.I0(DataIn[40]),
        .I1(Head1),
        .I2(Head0[40]),
        .O(p_0_in1_in[40]));
  (* SOFT_HLUTNM = "soft_lutpair487" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[41]_i_1__0 
       (.I0(DataIn[41]),
        .I1(Head1),
        .I2(Head0[41]),
        .O(p_0_in1_in[41]));
  (* SOFT_HLUTNM = "soft_lutpair487" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[42]_i_1__0 
       (.I0(DataIn[42]),
        .I1(Head1),
        .I2(Head0[42]),
        .O(p_0_in1_in[42]));
  (* SOFT_HLUTNM = "soft_lutpair488" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[43]_i_1__0 
       (.I0(DataIn[43]),
        .I1(Head1),
        .I2(Head0[43]),
        .O(p_0_in1_in[43]));
  (* SOFT_HLUTNM = "soft_lutpair488" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[44]_i_1__0 
       (.I0(DataIn[44]),
        .I1(Head1),
        .I2(Head0[44]),
        .O(p_0_in1_in[44]));
  (* SOFT_HLUTNM = "soft_lutpair489" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[45]_i_1__0 
       (.I0(DataIn[45]),
        .I1(Head1),
        .I2(Head0[45]),
        .O(p_0_in1_in[45]));
  (* SOFT_HLUTNM = "soft_lutpair489" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[46]_i_1__1 
       (.I0(DataIn[46]),
        .I1(Head1),
        .I2(Head0[46]),
        .O(p_0_in1_in[46]));
  (* SOFT_HLUTNM = "soft_lutpair490" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[47]_i_1__1 
       (.I0(DataIn[47]),
        .I1(Head1),
        .I2(Head0[47]),
        .O(p_0_in1_in[47]));
  (* SOFT_HLUTNM = "soft_lutpair490" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[48]_i_1__1 
       (.I0(DataIn[48]),
        .I1(Head1),
        .I2(Head0[48]),
        .O(p_0_in1_in[48]));
  (* SOFT_HLUTNM = "soft_lutpair491" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[49]_i_1__1 
       (.I0(DataIn[49]),
        .I1(Head1),
        .I2(Head0[49]),
        .O(p_0_in1_in[49]));
  (* SOFT_HLUTNM = "soft_lutpair468" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[4]_i_1__1 
       (.I0(DataIn[4]),
        .I1(Head1),
        .I2(Head0[4]),
        .O(p_0_in1_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair491" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[50]_i_1__1 
       (.I0(DataIn[50]),
        .I1(Head1),
        .I2(Head0[50]),
        .O(p_0_in1_in[50]));
  (* SOFT_HLUTNM = "soft_lutpair492" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[51]_i_1__1 
       (.I0(DataIn[51]),
        .I1(Head1),
        .I2(Head0[51]),
        .O(p_0_in1_in[51]));
  (* SOFT_HLUTNM = "soft_lutpair492" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[52]_i_1__1 
       (.I0(DataIn[52]),
        .I1(Head1),
        .I2(Head0[52]),
        .O(p_0_in1_in[52]));
  (* SOFT_HLUTNM = "soft_lutpair493" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[53]_i_1__1 
       (.I0(DataIn[53]),
        .I1(Head1),
        .I2(Head0[53]),
        .O(p_0_in1_in[53]));
  (* SOFT_HLUTNM = "soft_lutpair493" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[54]_i_1__1 
       (.I0(DataIn[54]),
        .I1(Head1),
        .I2(Head0[54]),
        .O(p_0_in1_in[54]));
  (* SOFT_HLUTNM = "soft_lutpair494" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[55]_i_1__1 
       (.I0(DataIn[55]),
        .I1(Head1),
        .I2(Head0[55]),
        .O(p_0_in1_in[55]));
  (* SOFT_HLUTNM = "soft_lutpair494" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[56]_i_1__2 
       (.I0(DataIn[56]),
        .I1(Head1),
        .I2(Head0[56]),
        .O(p_0_in1_in[56]));
  (* SOFT_HLUTNM = "soft_lutpair495" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[57]_i_1__2 
       (.I0(DataIn[57]),
        .I1(Head1),
        .I2(Head0[57]),
        .O(p_0_in1_in[57]));
  (* SOFT_HLUTNM = "soft_lutpair495" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[58]_i_1__2 
       (.I0(DataIn[58]),
        .I1(Head1),
        .I2(Head0[58]),
        .O(p_0_in1_in[58]));
  (* SOFT_HLUTNM = "soft_lutpair496" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[59]_i_1__2 
       (.I0(DataIn[59]),
        .I1(Head1),
        .I2(Head0[59]),
        .O(p_0_in1_in[59]));
  (* SOFT_HLUTNM = "soft_lutpair469" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[5]_i_1__1 
       (.I0(DataIn[5]),
        .I1(Head1),
        .I2(Head0[5]),
        .O(p_0_in1_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair496" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[60]_i_1__2 
       (.I0(DataIn[60]),
        .I1(Head1),
        .I2(Head0[60]),
        .O(p_0_in1_in[60]));
  (* SOFT_HLUTNM = "soft_lutpair497" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[61]_i_1__3 
       (.I0(DataIn[61]),
        .I1(Head1),
        .I2(Head0[61]),
        .O(p_0_in1_in[61]));
  (* SOFT_HLUTNM = "soft_lutpair497" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[62]_i_1__3 
       (.I0(DataIn[62]),
        .I1(Head1),
        .I2(Head0[62]),
        .O(p_0_in1_in[62]));
  (* SOFT_HLUTNM = "soft_lutpair498" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[63]_i_1__3 
       (.I0(DataIn[63]),
        .I1(Head1),
        .I2(Head0[63]),
        .O(p_0_in1_in[63]));
  (* SOFT_HLUTNM = "soft_lutpair498" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[64]_i_1__3 
       (.I0(DataIn[64]),
        .I1(Head1),
        .I2(Head0[64]),
        .O(p_0_in1_in[64]));
  (* SOFT_HLUTNM = "soft_lutpair499" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[65]_i_1__3 
       (.I0(DataIn[65]),
        .I1(Head1),
        .I2(Head0[65]),
        .O(p_0_in1_in[65]));
  (* SOFT_HLUTNM = "soft_lutpair499" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[66]_i_1__3 
       (.I0(DataIn[66]),
        .I1(Head1),
        .I2(Head0[66]),
        .O(p_0_in1_in[66]));
  (* SOFT_HLUTNM = "soft_lutpair500" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[67]_i_1__3 
       (.I0(DataIn[67]),
        .I1(Head1),
        .I2(Head0[67]),
        .O(p_0_in1_in[67]));
  (* SOFT_HLUTNM = "soft_lutpair500" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[68]_i_1__3 
       (.I0(DataIn[68]),
        .I1(Head1),
        .I2(Head0[68]),
        .O(p_0_in1_in[68]));
  (* SOFT_HLUTNM = "soft_lutpair501" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[69]_i_1__3 
       (.I0(DataIn[69]),
        .I1(Head1),
        .I2(Head0[69]),
        .O(p_0_in1_in[69]));
  (* SOFT_HLUTNM = "soft_lutpair469" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[6]_i_1__0 
       (.I0(DataIn[6]),
        .I1(Head1),
        .I2(Head0[6]),
        .O(p_0_in1_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair501" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[70]_i_1__3 
       (.I0(DataIn[70]),
        .I1(Head1),
        .I2(Head0[70]),
        .O(p_0_in1_in[70]));
  (* SOFT_HLUTNM = "soft_lutpair502" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[71]_i_1__3 
       (.I0(DataIn[71]),
        .I1(Head1),
        .I2(Head0[71]),
        .O(p_0_in1_in[71]));
  (* SOFT_HLUTNM = "soft_lutpair502" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[72]_i_1__3 
       (.I0(DataIn[72]),
        .I1(Head1),
        .I2(Head0[72]),
        .O(p_0_in1_in[72]));
  (* SOFT_HLUTNM = "soft_lutpair503" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[73]_i_1__3 
       (.I0(DataIn[73]),
        .I1(Head1),
        .I2(Head0[73]),
        .O(p_0_in1_in[73]));
  (* SOFT_HLUTNM = "soft_lutpair503" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[74]_i_1__3 
       (.I0(DataIn[74]),
        .I1(Head1),
        .I2(Head0[74]),
        .O(p_0_in1_in[74]));
  (* SOFT_HLUTNM = "soft_lutpair504" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[75]_i_1__3 
       (.I0(DataIn[75]),
        .I1(Head1),
        .I2(Head0[75]),
        .O(p_0_in1_in[75]));
  (* SOFT_HLUTNM = "soft_lutpair504" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[76]_i_1__3 
       (.I0(DataIn[76]),
        .I1(Head1),
        .I2(Head0[76]),
        .O(p_0_in1_in[76]));
  (* SOFT_HLUTNM = "soft_lutpair505" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[77]_i_1__3 
       (.I0(DataIn[77]),
        .I1(Head1),
        .I2(Head0[77]),
        .O(p_0_in1_in[77]));
  (* SOFT_HLUTNM = "soft_lutpair505" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[78]_i_1__3 
       (.I0(DataIn[78]),
        .I1(Head1),
        .I2(Head0[78]),
        .O(p_0_in1_in[78]));
  (* SOFT_HLUTNM = "soft_lutpair506" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[79]_i_1__3 
       (.I0(DataIn[79]),
        .I1(Head1),
        .I2(Head0[79]),
        .O(p_0_in1_in[79]));
  (* SOFT_HLUTNM = "soft_lutpair470" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[7]_i_1__0 
       (.I0(DataIn[7]),
        .I1(Head1),
        .I2(Head0[7]),
        .O(p_0_in1_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair506" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[80]_i_1__3 
       (.I0(DataIn[80]),
        .I1(Head1),
        .I2(Head0[80]),
        .O(p_0_in1_in[80]));
  (* SOFT_HLUTNM = "soft_lutpair507" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[81]_i_1__3 
       (.I0(DataIn[81]),
        .I1(Head1),
        .I2(Head0[81]),
        .O(p_0_in1_in[81]));
  (* SOFT_HLUTNM = "soft_lutpair507" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[82]_i_1__3 
       (.I0(DataIn[82]),
        .I1(Head1),
        .I2(Head0[82]),
        .O(p_0_in1_in[82]));
  (* SOFT_HLUTNM = "soft_lutpair508" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[83]_i_1__3 
       (.I0(DataIn[83]),
        .I1(Head1),
        .I2(Head0[83]),
        .O(p_0_in1_in[83]));
  (* SOFT_HLUTNM = "soft_lutpair508" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[84]_i_1__3 
       (.I0(DataIn[84]),
        .I1(Head1),
        .I2(Head0[84]),
        .O(p_0_in1_in[84]));
  (* SOFT_HLUTNM = "soft_lutpair509" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[85]_i_1__3 
       (.I0(DataIn[85]),
        .I1(Head1),
        .I2(Head0[85]),
        .O(p_0_in1_in[85]));
  (* SOFT_HLUTNM = "soft_lutpair509" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[86]_i_1__3 
       (.I0(DataIn[86]),
        .I1(Head1),
        .I2(Head0[86]),
        .O(p_0_in1_in[86]));
  (* SOFT_HLUTNM = "soft_lutpair510" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[87]_i_1__3 
       (.I0(DataIn[87]),
        .I1(Head1),
        .I2(Head0[87]),
        .O(p_0_in1_in[87]));
  (* SOFT_HLUTNM = "soft_lutpair510" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[88]_i_1__3 
       (.I0(DataIn[88]),
        .I1(Head1),
        .I2(Head0[88]),
        .O(p_0_in1_in[88]));
  (* SOFT_HLUTNM = "soft_lutpair511" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[89]_i_1__3 
       (.I0(DataIn[89]),
        .I1(Head1),
        .I2(Head0[89]),
        .O(p_0_in1_in[89]));
  (* SOFT_HLUTNM = "soft_lutpair470" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[8]_i_1__1 
       (.I0(DataIn[8]),
        .I1(Head1),
        .I2(Head0[8]),
        .O(p_0_in1_in[8]));
  (* SOFT_HLUTNM = "soft_lutpair511" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[90]_i_1__3 
       (.I0(DataIn[90]),
        .I1(Head1),
        .I2(Head0[90]),
        .O(p_0_in1_in[90]));
  (* SOFT_HLUTNM = "soft_lutpair512" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[91]_i_1__3 
       (.I0(DataIn[91]),
        .I1(Head1),
        .I2(Head0[91]),
        .O(p_0_in1_in[91]));
  (* SOFT_HLUTNM = "soft_lutpair512" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[92]_i_1__3 
       (.I0(DataIn[92]),
        .I1(Head1),
        .I2(Head0[92]),
        .O(p_0_in1_in[92]));
  (* SOFT_HLUTNM = "soft_lutpair513" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[93]_i_1__3 
       (.I0(DataIn[93]),
        .I1(Head1),
        .I2(Head0[93]),
        .O(p_0_in1_in[93]));
  (* SOFT_HLUTNM = "soft_lutpair513" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[94]_i_1__3 
       (.I0(DataIn[94]),
        .I1(Head1),
        .I2(Head0[94]),
        .O(p_0_in1_in[94]));
  (* SOFT_HLUTNM = "soft_lutpair514" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[95]_i_1__3 
       (.I0(DataIn[95]),
        .I1(Head1),
        .I2(Head0[95]),
        .O(p_0_in1_in[95]));
  (* SOFT_HLUTNM = "soft_lutpair514" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[96]_i_1__3 
       (.I0(DataIn[96]),
        .I1(Head1),
        .I2(Head0[96]),
        .O(p_0_in1_in[96]));
  (* SOFT_HLUTNM = "soft_lutpair515" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[97]_i_1__3 
       (.I0(DataIn[97]),
        .I1(Head1),
        .I2(Head0[97]),
        .O(p_0_in1_in[97]));
  (* SOFT_HLUTNM = "soft_lutpair515" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[98]_i_1__3 
       (.I0(DataIn[98]),
        .I1(Head1),
        .I2(Head0[98]),
        .O(p_0_in1_in[98]));
  (* SOFT_HLUTNM = "soft_lutpair516" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[99]_i_1__3 
       (.I0(DataIn[99]),
        .I1(Head1),
        .I2(Head0[99]),
        .O(p_0_in1_in[99]));
  (* SOFT_HLUTNM = "soft_lutpair471" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Head[9]_i_1__2 
       (.I0(DataIn[9]),
        .I1(Head1),
        .I2(Head0[9]),
        .O(p_0_in1_in[9]));
  FDRE \Head_reg[0] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[0]),
        .Q(Q[0]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[100] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[100]),
        .Q(Q[99]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[101] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[101]),
        .Q(Q[100]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[102] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[102]),
        .Q(Q[101]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[103] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[103]),
        .Q(Q[102]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[104] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[104]),
        .Q(Q[103]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[105] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[105]),
        .Q(Q[104]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[106] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[106]),
        .Q(Q[105]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[107] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[107]),
        .Q(Q[106]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[108] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[108]),
        .Q(Q[107]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[109] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[109]),
        .Q(Q[108]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[10]),
        .Q(Q[9]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[110] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[110]),
        .Q(Q[109]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[111] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[111]),
        .Q(Q[110]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[112] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[112]),
        .Q(Q[111]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[113] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[113]),
        .Q(Q[112]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[114] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[114]),
        .Q(Q[113]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[115] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[115]),
        .Q(Q[114]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[116] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[116]),
        .Q(Q[115]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[117] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[117]),
        .Q(Q[116]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[118] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[118]),
        .Q(Q[117]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[119] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[119]),
        .Q(Q[118]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[11]),
        .Q(Q[10]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[120] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[120]),
        .Q(Q[119]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[121] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[121]),
        .Q(Q[120]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[122] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[122]),
        .Q(Q[121]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[123] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[123]),
        .Q(Q[122]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[124] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[124]),
        .Q(Q[123]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[125] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[125]),
        .Q(Q[124]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[126] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[126]),
        .Q(Q[125]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[127] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[127]),
        .Q(Q[126]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[128] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[128]),
        .Q(Q[127]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[129] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[129]),
        .Q(Q[128]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[12]),
        .Q(Q[11]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[130] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[130]),
        .Q(Q[129]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[131] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[131]),
        .Q(Q[130]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[132] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[132]),
        .Q(Q[131]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[133] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[133]),
        .Q(Q[132]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[134] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[134]),
        .Q(Q[133]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[135] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[135]),
        .Q(Q[134]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[136] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[136]),
        .Q(Q[135]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[137] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[137]),
        .Q(Q[136]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[138] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[138]),
        .Q(Q[137]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[139] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[139]),
        .Q(Q[138]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[13]),
        .Q(Q[12]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[140] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[140]),
        .Q(Q[139]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[141] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[141]),
        .Q(Q[140]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[142] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[142]),
        .Q(Q[141]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[143] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[143]),
        .Q(Q[142]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[144] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[144]),
        .Q(Q[143]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[145] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[145]),
        .Q(Q[144]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[146] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[146]),
        .Q(Q[145]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[147] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[147]),
        .Q(Q[146]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[148] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[148]),
        .Q(Q[147]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[149] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[149]),
        .Q(Q[148]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[14]),
        .Q(Q[13]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[150] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[150]),
        .Q(Q[149]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[151] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[151]),
        .Q(Q[150]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[152] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[152]),
        .Q(Q[151]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[153] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[153]),
        .Q(Q[152]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[154] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[154]),
        .Q(Q[153]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[155] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[155]),
        .Q(Q[154]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[156] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[156]),
        .Q(Q[155]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[157] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[157]),
        .Q(Q[156]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[158] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[158]),
        .Q(Q[157]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[15]),
        .Q(Q[14]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[16] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[16]),
        .Q(Q[15]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[17] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[17]),
        .Q(Q[16]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[18]),
        .Q(Q[17]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[19]),
        .Q(Q[18]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[1] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[1]),
        .Q(Q[1]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[20]),
        .Q(Q[19]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[21]),
        .Q(Q[20]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[22] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[22]),
        .Q(Q[21]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[23] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[23]),
        .Q(Q[22]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[24] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[24]),
        .Q(Q[23]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[25] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[25]),
        .Q(Q[24]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[26] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[26]),
        .Q(Q[25]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[27] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[27]),
        .Q(Q[26]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[28] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[28]),
        .Q(Q[27]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[29] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[29]),
        .Q(Q[28]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[30] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[30]),
        .Q(Q[29]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[31] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[31]),
        .Q(Q[30]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[32] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[32]),
        .Q(Q[31]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[33] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[33]),
        .Q(Q[32]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[34] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[34]),
        .Q(Q[33]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[35] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[35]),
        .Q(Q[34]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[36] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[36]),
        .Q(Q[35]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[37] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[37]),
        .Q(Q[36]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[38] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[38]),
        .Q(Q[37]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[39] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[39]),
        .Q(Q[38]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[3] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[3]),
        .Q(Q[2]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[40] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[40]),
        .Q(Q[39]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[41] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[41]),
        .Q(Q[40]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[42] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[42]),
        .Q(Q[41]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[43] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[43]),
        .Q(Q[42]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[44] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[44]),
        .Q(Q[43]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[45] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[45]),
        .Q(Q[44]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[46] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[46]),
        .Q(Q[45]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[47] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[47]),
        .Q(Q[46]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[48] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[48]),
        .Q(Q[47]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[49] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[49]),
        .Q(Q[48]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[4] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[4]),
        .Q(Q[3]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[50] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[50]),
        .Q(Q[49]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[51] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[51]),
        .Q(Q[50]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[52] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[52]),
        .Q(Q[51]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[53] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[53]),
        .Q(Q[52]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[54] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[54]),
        .Q(Q[53]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[55] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[55]),
        .Q(Q[54]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[56] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[56]),
        .Q(Q[55]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[57] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[57]),
        .Q(Q[56]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[58] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[58]),
        .Q(Q[57]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[59] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[59]),
        .Q(Q[58]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[5] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[5]),
        .Q(Q[4]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[60]),
        .Q(Q[59]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[61]),
        .Q(Q[60]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[62]),
        .Q(Q[61]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[63]),
        .Q(Q[62]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[64] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[64]),
        .Q(Q[63]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[65] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[65]),
        .Q(Q[64]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[66]),
        .Q(Q[65]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[67]),
        .Q(Q[66]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[68]),
        .Q(Q[67]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[69]),
        .Q(Q[68]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[6] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[6]),
        .Q(Q[5]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[70]),
        .Q(Q[69]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[71]),
        .Q(Q[70]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[72]),
        .Q(Q[71]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[73]),
        .Q(Q[72]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[74] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[74]),
        .Q(Q[73]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[75] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[75]),
        .Q(Q[74]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[76] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[76]),
        .Q(Q[75]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[77] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[77]),
        .Q(Q[76]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[78] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[78]),
        .Q(Q[77]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[79] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[79]),
        .Q(Q[78]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[7] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[7]),
        .Q(Q[6]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[80] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[80]),
        .Q(Q[79]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[81] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[81]),
        .Q(Q[80]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[82] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[82]),
        .Q(Q[81]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[83] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[83]),
        .Q(Q[82]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[84] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[84]),
        .Q(Q[83]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[85] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[85]),
        .Q(Q[84]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[86] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[86]),
        .Q(Q[85]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[87] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[87]),
        .Q(Q[86]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[88] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[88]),
        .Q(Q[87]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[89] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[89]),
        .Q(Q[88]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[8] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[8]),
        .Q(Q[7]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[90]),
        .Q(Q[89]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[91]),
        .Q(Q[90]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[92]),
        .Q(Q[91]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[93]),
        .Q(Q[92]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[94] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[94]),
        .Q(Q[93]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[95] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[95]),
        .Q(Q[94]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[96] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[96]),
        .Q(Q[95]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[97] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[97]),
        .Q(Q[96]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[98] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[98]),
        .Q(Q[97]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[99] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[99]),
        .Q(Q[98]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \Head_reg[9] 
       (.C(user_clk),
        .CE(\Head[158]_i_1__0_n_0 ),
        .D(p_0_in1_in[9]),
        .Q(Q[8]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_7_0_5
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[1:0]),
        .DIB(DataIn[3:2]),
        .DIC(DataIn[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[1:0]),
        .DOB({Head0[3],MemArray_reg_0_7_0_5_n_3}),
        .DOC(Head0[5:4]),
        .DOD(NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_102_107" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "102" *) 
  (* ram_slice_end = "107" *) 
  RAM32M MemArray_reg_0_7_102_107
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[103:102]),
        .DIB(DataIn[105:104]),
        .DIC(DataIn[107:106]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[103:102]),
        .DOB(Head0[105:104]),
        .DOC(Head0[107:106]),
        .DOD(NLW_MemArray_reg_0_7_102_107_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_108_113" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "108" *) 
  (* ram_slice_end = "113" *) 
  RAM32M MemArray_reg_0_7_108_113
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[109:108]),
        .DIB(DataIn[111:110]),
        .DIC(DataIn[113:112]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[109:108]),
        .DOB(Head0[111:110]),
        .DOC(Head0[113:112]),
        .DOD(NLW_MemArray_reg_0_7_108_113_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_114_119" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "114" *) 
  (* ram_slice_end = "119" *) 
  RAM32M MemArray_reg_0_7_114_119
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[115:114]),
        .DIB(DataIn[117:116]),
        .DIC(DataIn[119:118]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[115:114]),
        .DOB(Head0[117:116]),
        .DOC(Head0[119:118]),
        .DOD(NLW_MemArray_reg_0_7_114_119_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_120_125" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "120" *) 
  (* ram_slice_end = "125" *) 
  RAM32M MemArray_reg_0_7_120_125
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[121:120]),
        .DIB(DataIn[123:122]),
        .DIC(DataIn[125:124]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[121:120]),
        .DOB(Head0[123:122]),
        .DOC(Head0[125:124]),
        .DOD(NLW_MemArray_reg_0_7_120_125_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_126_131" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "126" *) 
  (* ram_slice_end = "131" *) 
  RAM32M MemArray_reg_0_7_126_131
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[127:126]),
        .DIB(DataIn[129:128]),
        .DIC(DataIn[131:130]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[127:126]),
        .DOB(Head0[129:128]),
        .DOC(Head0[131:130]),
        .DOD(NLW_MemArray_reg_0_7_126_131_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_7_12_17
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[13:12]),
        .DIB(DataIn[15:14]),
        .DIC(DataIn[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[13:12]),
        .DOB(Head0[15:14]),
        .DOC(Head0[17:16]),
        .DOD(NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_132_137" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "132" *) 
  (* ram_slice_end = "137" *) 
  RAM32M MemArray_reg_0_7_132_137
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[133:132]),
        .DIB(DataIn[135:134]),
        .DIC(DataIn[137:136]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[133:132]),
        .DOB(Head0[135:134]),
        .DOC(Head0[137:136]),
        .DOD(NLW_MemArray_reg_0_7_132_137_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_138_143" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "138" *) 
  (* ram_slice_end = "143" *) 
  RAM32M MemArray_reg_0_7_138_143
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[139:138]),
        .DIB(DataIn[141:140]),
        .DIC(DataIn[143:142]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[139:138]),
        .DOB(Head0[141:140]),
        .DOC(Head0[143:142]),
        .DOD(NLW_MemArray_reg_0_7_138_143_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_144_149" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "144" *) 
  (* ram_slice_end = "149" *) 
  RAM32M MemArray_reg_0_7_144_149
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[145:144]),
        .DIB(DataIn[147:146]),
        .DIC(DataIn[149:148]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[145:144]),
        .DOB(Head0[147:146]),
        .DOC(Head0[149:148]),
        .DOD(NLW_MemArray_reg_0_7_144_149_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_150_155" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "150" *) 
  (* ram_slice_end = "155" *) 
  RAM32M MemArray_reg_0_7_150_155
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[151:150]),
        .DIB(DataIn[153:152]),
        .DIC(DataIn[155:154]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[151:150]),
        .DOB(Head0[153:152]),
        .DOC(Head0[155:154]),
        .DOD(NLW_MemArray_reg_0_7_150_155_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_156_158" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "156" *) 
  (* ram_slice_end = "158" *) 
  RAM32M MemArray_reg_0_7_156_158
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[157:156]),
        .DIB({1'b0,DataIn[158]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[157:156]),
        .DOB({NLW_MemArray_reg_0_7_156_158_DOB_UNCONNECTED[1],Head0[158]}),
        .DOC(NLW_MemArray_reg_0_7_156_158_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_7_156_158_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_7_18_23
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[19:18]),
        .DIB(DataIn[21:20]),
        .DIC(DataIn[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[19:18]),
        .DOB(Head0[21:20]),
        .DOC(Head0[23:22]),
        .DOD(NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_24_29" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M MemArray_reg_0_7_24_29
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[25:24]),
        .DIB(DataIn[27:26]),
        .DIC(DataIn[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[25:24]),
        .DOB(Head0[27:26]),
        .DOC(Head0[29:28]),
        .DOD(NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_30_35" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M MemArray_reg_0_7_30_35
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[31:30]),
        .DIB(DataIn[33:32]),
        .DIC(DataIn[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[31:30]),
        .DOB(Head0[33:32]),
        .DOC(Head0[35:34]),
        .DOD(NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_36_41" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M MemArray_reg_0_7_36_41
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[37:36]),
        .DIB(DataIn[39:38]),
        .DIC(DataIn[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[37:36]),
        .DOB(Head0[39:38]),
        .DOC(Head0[41:40]),
        .DOD(NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_42_47" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M MemArray_reg_0_7_42_47
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[43:42]),
        .DIB(DataIn[45:44]),
        .DIC(DataIn[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[43:42]),
        .DOB(Head0[45:44]),
        .DOC(Head0[47:46]),
        .DOD(NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_48_53" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M MemArray_reg_0_7_48_53
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[49:48]),
        .DIB(DataIn[51:50]),
        .DIC(DataIn[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[49:48]),
        .DOB(Head0[51:50]),
        .DOC(Head0[53:52]),
        .DOD(NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_54_59" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M MemArray_reg_0_7_54_59
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[55:54]),
        .DIB(DataIn[57:56]),
        .DIC(DataIn[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[55:54]),
        .DOB(Head0[57:56]),
        .DOC(Head0[59:58]),
        .DOD(NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_60_65" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M MemArray_reg_0_7_60_65
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[61:60]),
        .DIB(DataIn[63:62]),
        .DIC(DataIn[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[61:60]),
        .DOB(Head0[63:62]),
        .DOC(Head0[65:64]),
        .DOD(NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_66_71" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M MemArray_reg_0_7_66_71
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[67:66]),
        .DIB(DataIn[69:68]),
        .DIC(DataIn[71:70]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[67:66]),
        .DOB(Head0[69:68]),
        .DOC(Head0[71:70]),
        .DOD(NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_7_6_11
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[7:6]),
        .DIB(DataIn[9:8]),
        .DIC(DataIn[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[7:6]),
        .DOB(Head0[9:8]),
        .DOC(Head0[11:10]),
        .DOD(NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_72_77" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M MemArray_reg_0_7_72_77
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[73:72]),
        .DIB(DataIn[75:74]),
        .DIC(DataIn[77:76]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[73:72]),
        .DOB(Head0[75:74]),
        .DOC(Head0[77:76]),
        .DOD(NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_78_83" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "83" *) 
  RAM32M MemArray_reg_0_7_78_83
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[79:78]),
        .DIB(DataIn[81:80]),
        .DIC(DataIn[83:82]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[79:78]),
        .DOB(Head0[81:80]),
        .DOC(Head0[83:82]),
        .DOD(NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_84_89" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "84" *) 
  (* ram_slice_end = "89" *) 
  RAM32M MemArray_reg_0_7_84_89
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[85:84]),
        .DIB(DataIn[87:86]),
        .DIC(DataIn[89:88]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[85:84]),
        .DOB(Head0[87:86]),
        .DOC(Head0[89:88]),
        .DOD(NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_90_95" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "90" *) 
  (* ram_slice_end = "95" *) 
  RAM32M MemArray_reg_0_7_90_95
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[91:90]),
        .DIB(DataIn[93:92]),
        .DIC(DataIn[95:94]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[91:90]),
        .DOB(Head0[93:92]),
        .DOC(Head0[95:94]),
        .DOD(NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "1272" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_96_101" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "96" *) 
  (* ram_slice_end = "101" *) 
  RAM32M MemArray_reg_0_7_96_101
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr,\WrPtr_reg[1]_0 }),
        .DIA(DataIn[97:96]),
        .DIB(DataIn[99:98]),
        .DIC(DataIn[101:100]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[97:96]),
        .DOB(Head0[99:98]),
        .DOC(Head0[101:100]),
        .DOD(NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dsc_ch_vld));
  LUT6 #(
    .INIT(64'h5656565656565666)) 
    \RdPtr[0]_i_1__3 
       (.I0(RdPtr[0]),
        .I1(Head1),
        .I2(empty_ff_reg_0),
        .I3(\FifoCntrRd_reg[1]_0 [1]),
        .I4(FifoCntrRd_reg[2]),
        .I5(FifoCntrRd_reg[3]),
        .O(RdPtr__0[0]));
  LUT5 #(
    .INIT(32'h557FAA80)) 
    \RdPtr[1]_i_1__3 
       (.I0(RdPtr[0]),
        .I1(\RdPtr[2]_i_4__0_n_0 ),
        .I2(empty_ff_reg_0),
        .I3(Head1),
        .I4(RdPtr[1]),
        .O(RdPtr__0[1]));
  LUT3 #(
    .INIT(8'hFE)) 
    \RdPtr[2]_i_1__0 
       (.I0(rrq_dsc_ld_901_reg_rep__2),
        .I1(evt_idl_stp_vld_nn1),
        .I2(ctl_rst),
        .O(\RdPtr[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h5777FFFFA8880000)) 
    \RdPtr[2]_i_2__0 
       (.I0(RdPtr[1]),
        .I1(Head1),
        .I2(empty_ff_reg_0),
        .I3(\RdPtr[2]_i_4__0_n_0 ),
        .I4(RdPtr[0]),
        .I5(RdPtr[2]),
        .O(RdPtr__0[2]));
  LUT6 #(
    .INIT(64'h000000000000008A)) 
    \RdPtr[2]_i_3__0 
       (.I0(dsc_ch_vld),
        .I1(empty_ff_reg_0),
        .I2(\FifoCntrRd_reg[1]_0 [0]),
        .I3(\FifoCntrRd_reg[1]_0 [1]),
        .I4(FifoCntrRd_reg[2]),
        .I5(FifoCntrRd_reg[3]),
        .O(Head1));
  (* SOFT_HLUTNM = "soft_lutpair466" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \RdPtr[2]_i_4__0 
       (.I0(FifoCntrRd_reg[3]),
        .I1(FifoCntrRd_reg[2]),
        .I2(\FifoCntrRd_reg[1]_0 [1]),
        .O(\RdPtr[2]_i_4__0_n_0 ));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[0]),
        .Q(RdPtr[0]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(RdPtr[1]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \RdPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[2]),
        .Q(RdPtr[2]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \WrPtr[2]_i_1__0 
       (.I0(\WrPtr_reg[1]_0 [1]),
        .I1(\WrPtr_reg[1]_0 [0]),
        .I2(\FifoCntrRd_reg[2]_0 ),
        .I3(dsc_acc_mgc_nn1),
        .I4(dsc_acc_done_nn1),
        .I5(WrPtr),
        .O(WrPtr__0));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr_reg[1]_1 [0]),
        .Q(\WrPtr_reg[1]_0 [0]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr_reg[1]_1 [1]),
        .Q(\WrPtr_reg[1]_0 [1]),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  FDRE \WrPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0),
        .Q(WrPtr),
        .R(\RdPtr[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FAFAFAF8)) 
    almost_full_ff_i_1__0
       (.I0(FifoCntrWr_reg[2]),
        .I1(\FifoCntrWr_reg[1]_0 [1]),
        .I2(FifoCntrWr_reg[3]),
        .I3(dsc_ch_vld),
        .I4(\FifoCntrWr_reg[1]_0 [0]),
        .I5(\RdPtr[2]_i_1__0_n_0 ),
        .O(almost_full_ff_i_1__0_n_0));
  FDRE almost_full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(almost_full_ff_i_1__0_n_0),
        .Q(almost_full_ff_reg_0),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h7)) 
    dsc_aln_nn1_i_1
       (.I0(out),
        .I1(dsc_aln_nn1_i_2__0_n_0),
        .O(dsc_aln_nn0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    dsc_aln_nn1_i_2__0
       (.I0(Q[31]),
        .I1(Q[96]),
        .I2(Q[32]),
        .I3(Q[94]),
        .I4(Q[95]),
        .I5(Q[30]),
        .O(dsc_aln_nn1_i_2__0_n_0));
  LUT3 #(
    .INIT(8'h95)) 
    \dsc_mrs_dst_nn1[12]_i_3__0 
       (.I0(\dsc_mrs_dst_nn1_reg[12] ),
        .I1(Q[41]),
        .I2(\dsc_mrs_dst_nn1_reg[12]_2 [4]),
        .O(\dsc_mrs_dst_nn1[12]_i_3__0_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \dsc_mrs_dst_nn1[12]_i_4__0 
       (.I0(\dsc_mrs_dst_nn1_reg[12]_0 ),
        .I1(Q[40]),
        .I2(\dsc_mrs_dst_nn1_reg[12]_2 [3]),
        .O(\dsc_mrs_dst_nn1[12]_i_4__0_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \dsc_mrs_dst_nn1[12]_i_5__0 
       (.I0(\dsc_mrs_dst_nn1_reg[12]_1 ),
        .I1(Q[39]),
        .I2(\dsc_mrs_dst_nn1_reg[12]_2 [2]),
        .O(\dsc_mrs_dst_nn1[12]_i_5__0_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[4]_i_2__0 
       (.I0(Q[30]),
        .O(\dsc_mrs_dst_nn1[4]_i_2__0_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[4]_i_3__0 
       (.I0(Q[34]),
        .O(\dsc_mrs_dst_nn1[4]_i_3__0_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[4]_i_4__0 
       (.I0(Q[33]),
        .O(\dsc_mrs_dst_nn1[4]_i_4__0_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[4]_i_5__0 
       (.I0(Q[32]),
        .O(\dsc_mrs_dst_nn1[4]_i_5__0_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[4]_i_6__0 
       (.I0(Q[31]),
        .O(\dsc_mrs_dst_nn1[4]_i_6__0_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \dsc_mrs_dst_nn1[8]_i_2__0 
       (.I0(\dsc_mrs_dst_nn1_reg[8] ),
        .I1(Q[38]),
        .I2(\dsc_mrs_dst_nn1_reg[12]_2 [1]),
        .O(\dsc_mrs_dst_nn1[8]_i_2__0_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \dsc_mrs_dst_nn1[8]_i_3__0 
       (.I0(\dsc_mrs_dst_nn1_reg[8]_0 ),
        .I1(Q[37]),
        .I2(\dsc_mrs_dst_nn1_reg[12]_2 [0]),
        .O(\dsc_mrs_dst_nn1[8]_i_3__0_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[8]_i_4__0 
       (.I0(Q[36]),
        .O(\dsc_mrs_dst_nn1[8]_i_4__0_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \dsc_mrs_dst_nn1[8]_i_5__0 
       (.I0(Q[35]),
        .O(\dsc_mrs_dst_nn1[8]_i_5__0_n_0 ));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \dsc_mrs_dst_nn1_reg[12]_i_1__0 
       (.CI(\dsc_mrs_dst_nn1_reg[8]_i_1__0_n_0 ),
        .CO({\NLW_dsc_mrs_dst_nn1_reg[12]_i_1__0_CO_UNCONNECTED [3],\dsc_mrs_dst_nn1_reg[12]_i_1__0_n_1 ,\dsc_mrs_dst_nn1_reg[12]_i_1__0_n_2 ,\dsc_mrs_dst_nn1_reg[12]_i_1__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,\dsc_mrs_dst_nn1_reg[12] ,\dsc_mrs_dst_nn1_reg[12]_0 ,\dsc_mrs_dst_nn1_reg[12]_1 }),
        .O(\cfg_mrs_nn1_reg[11] [11:8]),
        .S({S,\dsc_mrs_dst_nn1[12]_i_3__0_n_0 ,\dsc_mrs_dst_nn1[12]_i_4__0_n_0 ,\dsc_mrs_dst_nn1[12]_i_5__0_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \dsc_mrs_dst_nn1_reg[4]_i_1__0 
       (.CI(1'b0),
        .CO({\dsc_mrs_dst_nn1_reg[4]_i_1__0_n_0 ,\dsc_mrs_dst_nn1_reg[4]_i_1__0_n_1 ,\dsc_mrs_dst_nn1_reg[4]_i_1__0_n_2 ,\dsc_mrs_dst_nn1_reg[4]_i_1__0_n_3 }),
        .CYINIT(\dsc_mrs_dst_nn1[4]_i_2__0_n_0 ),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\cfg_mrs_nn1_reg[11] [3:0]),
        .S({\dsc_mrs_dst_nn1[4]_i_3__0_n_0 ,\dsc_mrs_dst_nn1[4]_i_4__0_n_0 ,\dsc_mrs_dst_nn1[4]_i_5__0_n_0 ,\dsc_mrs_dst_nn1[4]_i_6__0_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \dsc_mrs_dst_nn1_reg[8]_i_1__0 
       (.CI(\dsc_mrs_dst_nn1_reg[4]_i_1__0_n_0 ),
        .CO({\dsc_mrs_dst_nn1_reg[8]_i_1__0_n_0 ,\dsc_mrs_dst_nn1_reg[8]_i_1__0_n_1 ,\dsc_mrs_dst_nn1_reg[8]_i_1__0_n_2 ,\dsc_mrs_dst_nn1_reg[8]_i_1__0_n_3 }),
        .CYINIT(1'b0),
        .DI({\dsc_mrs_dst_nn1_reg[8] ,\dsc_mrs_dst_nn1_reg[8]_0 ,1'b0,1'b0}),
        .O(\cfg_mrs_nn1_reg[11] [7:4]),
        .S({\dsc_mrs_dst_nn1[8]_i_2__0_n_0 ,\dsc_mrs_dst_nn1[8]_i_3__0_n_0 ,\dsc_mrs_dst_nn1[8]_i_4__0_n_0 ,\dsc_mrs_dst_nn1[8]_i_5__0_n_0 }));
  LUT6 #(
    .INIT(64'hAAABAAAAAAABAAAB)) 
    empty_ff_i_1__3
       (.I0(empty_ff_i_2__0_n_0),
        .I1(FifoCntrRd_reg[3]),
        .I2(FifoCntrRd_reg[2]),
        .I3(\FifoCntrRd_reg[1]_0 [1]),
        .I4(empty_ff_reg_0),
        .I5(\FifoCntrRd_reg[1]_0 [0]),
        .O(empty_ff_i_1__3_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010000)) 
    empty_ff_i_2__0
       (.I0(\FifoCntrRd_reg[1]_0 [0]),
        .I1(FifoCntrRd_reg[3]),
        .I2(FifoCntrRd_reg[2]),
        .I3(\FifoCntrRd_reg[1]_0 [1]),
        .I4(dsc_ep_nn0),
        .I5(\RdPtr[2]_i_1__0_n_0 ),
        .O(empty_ff_i_2__0_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__3_n_0),
        .Q(dsc_ep_nn0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    rrq_dsc_ld_901_i_1__0
       (.I0(rrq_dsc_ld_901_i_2_n_0),
        .I1(\rrq_sm_cur_900_reg[6]_0 [1]),
        .I2(\rrq_sm_cur_900_reg[6]_0 [0]),
        .I3(\rrq_sm_cur_900_reg[6]_0 [4]),
        .I4(rrq_dsc_ld_901_reg),
        .I5(rrq_dsc_ld_901_reg_rep__2),
        .O(\rrq_sm_cur_900_reg[1] ));
  LUT6 #(
    .INIT(64'h0505050500004000)) 
    rrq_dsc_ld_901_i_2
       (.I0(dsc_ep_nn0),
        .I1(rrq_eod_903),
        .I2(\rrq_sm_cur_900_reg[6]_0 [3]),
        .I3(rrq_vld_903),
        .I4(rrq_dsc_ld_901_reg_rep__2_0),
        .I5(\rrq_sm_cur_900_reg[6]_0 [2]),
        .O(rrq_dsc_ld_901_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    rrq_dsc_ld_901_rep__0_i_1
       (.I0(rrq_dsc_ld_901_i_2_n_0),
        .I1(\rrq_sm_cur_900_reg[6]_0 [1]),
        .I2(\rrq_sm_cur_900_reg[6]_0 [0]),
        .I3(\rrq_sm_cur_900_reg[6]_0 [4]),
        .I4(rrq_dsc_ld_901_reg),
        .I5(rrq_dsc_ld_901_reg_rep__2),
        .O(\rrq_sm_cur_900_reg[1]_1 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    rrq_dsc_ld_901_rep__1_i_1
       (.I0(rrq_dsc_ld_901_i_2_n_0),
        .I1(\rrq_sm_cur_900_reg[6]_0 [1]),
        .I2(\rrq_sm_cur_900_reg[6]_0 [0]),
        .I3(\rrq_sm_cur_900_reg[6]_0 [4]),
        .I4(rrq_dsc_ld_901_reg),
        .I5(rrq_dsc_ld_901_reg_rep__2),
        .O(\rrq_sm_cur_900_reg[1]_2 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    rrq_dsc_ld_901_rep__2_i_1
       (.I0(rrq_dsc_ld_901_i_2_n_0),
        .I1(\rrq_sm_cur_900_reg[6]_0 [1]),
        .I2(\rrq_sm_cur_900_reg[6]_0 [0]),
        .I3(\rrq_sm_cur_900_reg[6]_0 [4]),
        .I4(rrq_dsc_ld_901_reg),
        .I5(rrq_dsc_ld_901_reg_rep__2),
        .O(\rrq_sm_cur_900_reg[1]_3 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    rrq_dsc_ld_901_rep_i_1__4
       (.I0(rrq_dsc_ld_901_i_2_n_0),
        .I1(\rrq_sm_cur_900_reg[6]_0 [1]),
        .I2(\rrq_sm_cur_900_reg[6]_0 [0]),
        .I3(\rrq_sm_cur_900_reg[6]_0 [4]),
        .I4(rrq_dsc_ld_901_reg),
        .I5(rrq_dsc_ld_901_reg_rep__2),
        .O(\rrq_sm_cur_900_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAAAAAABAAAAAAAAA)) 
    \rrq_sm_cur_900[1]_i_1__0 
       (.I0(ctl_rst),
        .I1(\rrq_sm_cur_900[1]_i_2__0_n_0 ),
        .I2(\rrq_sm_cur_900_reg[6]_0 [1]),
        .I3(\rrq_sm_cur_900_reg[6]_0 [2]),
        .I4(reg_sts_hlt_nn1),
        .I5(\rrq_sm_cur_900_reg[1]_4 ),
        .O(D[0]));
  LUT3 #(
    .INIT(8'hFB)) 
    \rrq_sm_cur_900[1]_i_2__0 
       (.I0(\rrq_sm_cur_900_reg[6]_0 [3]),
        .I1(dsc_ep_nn0),
        .I2(\rrq_sm_cur_900_reg[6]_2 ),
        .O(\rrq_sm_cur_900[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h002A222A00080008)) 
    \rrq_sm_cur_900[4]_i_1__0 
       (.I0(\rrq_sm_cur_900_reg[4] ),
        .I1(\rrq_sm_cur_900_reg[6]_0 [2]),
        .I2(\rrq_sm_cur_900_reg[6]_0 [3]),
        .I3(dsc_ep_nn0),
        .I4(rrq_eod_903),
        .I5(\rrq_sm_cur_900_reg[4]_0 ),
        .O(D[1]));
  LUT4 #(
    .INIT(16'h5455)) 
    \rrq_sm_cur_900[6]_i_1__0 
       (.I0(ctl_rst),
        .I1(reg_sts_hlt_nn1),
        .I2(\rrq_sm_cur_900_reg[6] ),
        .I3(\rrq_sm_cur_900[6]_i_3__0_n_0 ),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hFFFFEFFFEFFFFFFF)) 
    \rrq_sm_cur_900[6]_i_3__0 
       (.I0(\rrq_sm_cur_900_reg[6]_1 ),
        .I1(\rrq_sm_cur_900_reg[6]_0 [5]),
        .I2(dsc_ep_nn0),
        .I3(\rrq_sm_cur_900_reg[6]_2 ),
        .I4(\rrq_sm_cur_900_reg[6]_0 [1]),
        .I5(\rrq_sm_cur_900_reg[6]_0 [2]),
        .O(\rrq_sm_cur_900[6]_i_3__0_n_0 ));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOHead" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOHead__parameterized3
   (empty_ff_reg_0,
    empty_ff_reg_1,
    \pcie_c2h_rst_3ff_reg[0]_rep__4 ,
    empty_ff_reg_2,
    empty_ff_reg_3,
    payloadmuxed,
    wrq_vld_302,
    cfg_linkdown_nn1,
    wrq_stall_302,
    wrq_vld_303,
    wrq_vld_303_reg,
    CO,
    wrq_vld_303_reg_0,
    empty_ff_reg_4,
    Head0,
    Head1__2,
    arbstall,
    \Head_reg[111]_0 ,
    \wbk_xdma_wrq_req[rid] ,
    \Head_reg[110]_0 ,
    p_8_in,
    Q,
    \axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 ,
    D,
    wrq_vld_303_reg_1,
    user_clk,
    DataIn,
    \Head_reg[10]_0 ,
    \Head_reg[110]_1 );
  output empty_ff_reg_0;
  output empty_ff_reg_1;
  output \pcie_c2h_rst_3ff_reg[0]_rep__4 ;
  output [88:0]empty_ff_reg_2;
  output empty_ff_reg_3;
  output [91:0]payloadmuxed;
  output wrq_vld_302;
  input cfg_linkdown_nn1;
  input wrq_stall_302;
  input wrq_vld_303;
  input wrq_vld_303_reg;
  input [0:0]CO;
  input [0:0]wrq_vld_303_reg_0;
  input empty_ff_reg_4;
  input [88:0]Head0;
  input Head1__2;
  input arbstall;
  input \Head_reg[111]_0 ;
  input [0:0]\wbk_xdma_wrq_req[rid] ;
  input \Head_reg[110]_0 ;
  input [61:0]p_8_in;
  input [61:0]Q;
  input [61:0]\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 ;
  input [3:0]D;
  input wrq_vld_303_reg_1;
  input user_clk;
  input [80:0]DataIn;
  input [1:0]\Head_reg[10]_0 ;
  input [3:0]\Head_reg[110]_1 ;

  wire [0:0]CO;
  wire [3:0]D;
  wire [80:0]DataIn;
  wire [2:0]FifoCntrRd;
  wire \FifoCntrRd[0]_i_1__1_n_0 ;
  wire \FifoCntrRd[1]_i_1__1_n_0 ;
  wire \FifoCntrRd[2]_i_2_n_0 ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__1_n_0 ;
  wire \FifoCntrWr[1]_i_1__1_n_0 ;
  wire \FifoCntrWr[2]_i_1__1_n_0 ;
  wire [88:0]Head0;
  wire [111:0]Head0_0;
  wire Head1;
  wire Head1__2;
  wire \Head[111]_i_1__1_n_0 ;
  wire \Head[111]_i_2_n_0 ;
  wire \Head[36]_i_1__1_n_0 ;
  wire \Head[41]_i_1__2_n_0 ;
  wire \Head[46]_i_1__3_n_0 ;
  wire \Head[8]_i_1__3_n_0 ;
  wire [1:0]\Head_reg[10]_0 ;
  wire \Head_reg[110]_0 ;
  wire [3:0]\Head_reg[110]_1 ;
  wire \Head_reg[111]_0 ;
  wire [61:0]Q;
  wire [1:0]RdPtr;
  wire \RdPtr[1]_i_3_n_0 ;
  wire [1:0]RdPtr__0;
  wire [1:0]WrPtr;
  wire [1:0]WrPtr__0;
  wire arbstall;
  wire [61:0]\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 ;
  wire [5:0]\c2h_xdma_wrq_req[0][aln] ;
  wire [27:0]\c2h_xdma_wrq_req[0][byte_len] ;
  wire \c2h_xdma_wrq_req[0][eod] ;
  wire \c2h_xdma_wrq_req[0][eop] ;
  wire \c2h_xdma_wrq_req[0][eor] ;
  wire [9:0]\c2h_xdma_wrq_req[0][rid] ;
  wire cfg_linkdown_nn1;
  wire empty_ff_i_1__1_n_0;
  wire empty_ff_i_2__1_n_0;
  wire empty_ff_reg_0;
  wire empty_ff_reg_1;
  wire [88:0]empty_ff_reg_2;
  wire empty_ff_reg_3;
  wire empty_ff_reg_4;
  wire full_ff_i_1__0_n_0;
  wire full_ff_reg_n_0;
  wire [110:0]p_0_in1_in;
  wire [63:0]p_10_in;
  wire p_11_in__0;
  wire [61:0]p_8_in;
  wire [91:0]payloadmuxed;
  wire \pcie_c2h_rst_3ff_reg[0]_rep__4 ;
  wire user_clk;
  wire [0:0]\wbk_xdma_wrq_req[rid] ;
  wire wrq_stall_302;
  wire wrq_vld_302;
  wire wrq_vld_303;
  wire wrq_vld_303_i_3__0_n_0;
  wire wrq_vld_303_reg;
  wire [0:0]wrq_vld_303_reg_0;
  wire wrq_vld_303_reg_1;
  wire [1:0]NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair925" *) 
  LUT4 #(
    .INIT(16'h59A6)) 
    \FifoCntrRd[0]_i_1__1 
       (.I0(wrq_vld_303),
        .I1(empty_ff_reg_1),
        .I2(empty_ff_reg_0),
        .I3(FifoCntrRd[0]),
        .O(\FifoCntrRd[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair925" *) 
  LUT5 #(
    .INIT(32'h77E78818)) 
    \FifoCntrRd[1]_i_1__1 
       (.I0(FifoCntrRd[0]),
        .I1(wrq_vld_303),
        .I2(empty_ff_reg_1),
        .I3(empty_ff_reg_0),
        .I4(FifoCntrRd[1]),
        .O(\FifoCntrRd[1]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FifoCntrRd[2]_i_1__4 
       (.I0(empty_ff_reg_4),
        .I1(cfg_linkdown_nn1),
        .O(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  LUT6 #(
    .INIT(64'h7F7FFE7F80800180)) 
    \FifoCntrRd[2]_i_2 
       (.I0(FifoCntrRd[0]),
        .I1(FifoCntrRd[1]),
        .I2(wrq_vld_303),
        .I3(empty_ff_reg_1),
        .I4(empty_ff_reg_0),
        .I5(FifoCntrRd[2]),
        .O(\FifoCntrRd[2]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \FifoCntrRd[2]_i_3__4 
       (.I0(empty_ff_reg_0),
        .I1(\Head_reg[111]_0 ),
        .I2(arbstall),
        .O(empty_ff_reg_1));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[0]_i_1__1_n_0 ),
        .Q(FifoCntrRd[0]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[1]_i_1__1_n_0 ),
        .Q(FifoCntrRd[1]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[2]_i_2_n_0 ),
        .Q(FifoCntrRd[2]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  (* SOFT_HLUTNM = "soft_lutpair926" *) 
  LUT4 #(
    .INIT(16'h4BB4)) 
    \FifoCntrWr[0]_i_1__1 
       (.I0(empty_ff_reg_0),
        .I1(empty_ff_reg_1),
        .I2(wrq_vld_303),
        .I3(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair926" *) 
  LUT5 #(
    .INIT(32'h75EF8A10)) 
    \FifoCntrWr[1]_i_1__1 
       (.I0(FifoCntrWr[0]),
        .I1(empty_ff_reg_0),
        .I2(empty_ff_reg_1),
        .I3(wrq_vld_303),
        .I4(FifoCntrWr[1]),
        .O(\FifoCntrWr[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h7F77FEFF80880100)) 
    \FifoCntrWr[2]_i_1__1 
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(empty_ff_reg_0),
        .I3(empty_ff_reg_1),
        .I4(wrq_vld_303),
        .I5(FifoCntrWr[2]),
        .O(\FifoCntrWr[2]_i_1__1_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[0]_i_1__1_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[1]_i_1__1_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[2]_i_1__1_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  (* SOFT_HLUTNM = "soft_lutpair927" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[0]_i_1__0 
       (.I0(DataIn[0]),
        .I1(Head0_0[0]),
        .I2(Head1),
        .O(p_0_in1_in[0]));
  LUT6 #(
    .INIT(64'h00CC50CC00CCFFCC)) 
    \Head[0]_i_1__7 
       (.I0(empty_ff_reg_0),
        .I1(Head0[0]),
        .I2(\c2h_xdma_wrq_req[0][eor] ),
        .I3(Head1__2),
        .I4(arbstall),
        .I5(\Head_reg[111]_0 ),
        .O(empty_ff_reg_2[0]));
  (* SOFT_HLUTNM = "soft_lutpair967" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[100]_i_1__1 
       (.I0(DataIn[73]),
        .I1(Head0_0[100]),
        .I2(Head1),
        .O(p_0_in1_in[100]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[100]_i_1__7 
       (.I0(Head0[77]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[53]),
        .I3(p_8_in[51]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[77]));
  (* SOFT_HLUTNM = "soft_lutpair968" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[101]_i_1__1 
       (.I0(DataIn[74]),
        .I1(Head0_0[101]),
        .I2(Head1),
        .O(p_0_in1_in[101]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[101]_i_1__7 
       (.I0(Head0[78]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[54]),
        .I3(p_8_in[52]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[78]));
  (* SOFT_HLUTNM = "soft_lutpair968" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[102]_i_1__1 
       (.I0(DataIn[75]),
        .I1(Head0_0[102]),
        .I2(Head1),
        .O(p_0_in1_in[102]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[102]_i_1__7 
       (.I0(Head0[79]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[55]),
        .I3(p_8_in[53]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[79]));
  (* SOFT_HLUTNM = "soft_lutpair969" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[103]_i_1__1 
       (.I0(DataIn[76]),
        .I1(Head0_0[103]),
        .I2(Head1),
        .O(p_0_in1_in[103]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[103]_i_1__7 
       (.I0(Head0[80]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[56]),
        .I3(p_8_in[54]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[80]));
  (* SOFT_HLUTNM = "soft_lutpair969" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[104]_i_1__1 
       (.I0(DataIn[77]),
        .I1(Head0_0[104]),
        .I2(Head1),
        .O(p_0_in1_in[104]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[104]_i_1__7 
       (.I0(Head0[81]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[57]),
        .I3(p_8_in[55]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[81]));
  (* SOFT_HLUTNM = "soft_lutpair970" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[105]_i_1__1 
       (.I0(DataIn[78]),
        .I1(Head0_0[105]),
        .I2(Head1),
        .O(p_0_in1_in[105]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[105]_i_1__7 
       (.I0(Head0[82]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[58]),
        .I3(p_8_in[56]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[82]));
  (* SOFT_HLUTNM = "soft_lutpair970" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[106]_i_1__1 
       (.I0(DataIn[79]),
        .I1(Head0_0[106]),
        .I2(Head1),
        .O(p_0_in1_in[106]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[106]_i_1__7 
       (.I0(Head0[83]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[59]),
        .I3(p_8_in[57]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[83]));
  (* SOFT_HLUTNM = "soft_lutpair971" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[107]_i_1__1 
       (.I0(DataIn[80]),
        .I1(Head0_0[107]),
        .I2(Head1),
        .O(p_0_in1_in[107]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[107]_i_1__7 
       (.I0(Head0[84]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[60]),
        .I3(p_8_in[58]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[84]));
  (* SOFT_HLUTNM = "soft_lutpair971" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[108]_i_1__1 
       (.I0(\Head_reg[110]_1 [1]),
        .I1(Head0_0[108]),
        .I2(Head1),
        .O(p_0_in1_in[108]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[108]_i_1__7 
       (.I0(Head0[85]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[61]),
        .I3(p_8_in[59]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[85]));
  (* SOFT_HLUTNM = "soft_lutpair972" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[109]_i_1__1 
       (.I0(\Head_reg[110]_1 [2]),
        .I1(Head0_0[109]),
        .I2(Head1),
        .O(p_0_in1_in[109]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[109]_i_1__7 
       (.I0(Head0[86]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[62]),
        .I3(p_8_in[60]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[86]));
  (* SOFT_HLUTNM = "soft_lutpair933" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[10]_i_1__1 
       (.I0(\Head_reg[10]_0 [1]),
        .I1(Head0_0[10]),
        .I2(Head1),
        .O(p_0_in1_in[10]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[10]_i_1__9 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [1]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[7]),
        .O(empty_ff_reg_2[7]));
  (* SOFT_HLUTNM = "soft_lutpair972" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[110]_i_1__1 
       (.I0(\Head_reg[110]_1 [3]),
        .I1(Head0_0[110]),
        .I2(Head1),
        .O(p_0_in1_in[110]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[110]_i_1__7 
       (.I0(Head0[87]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[63]),
        .I3(p_8_in[61]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[87]));
  LUT6 #(
    .INIT(64'hAEAEAEAEAEAEAEFF)) 
    \Head[111]_i_1__1 
       (.I0(Head1),
        .I1(empty_ff_reg_1),
        .I2(empty_ff_reg_0),
        .I3(FifoCntrRd[2]),
        .I4(FifoCntrRd[1]),
        .I5(FifoCntrRd[0]),
        .O(\Head[111]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[111]_i_1__7 
       (.I0(empty_ff_reg_0),
        .I1(p_11_in__0),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[88]),
        .O(empty_ff_reg_2[88]));
  (* SOFT_HLUTNM = "soft_lutpair931" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[111]_i_2 
       (.I0(Head0_0[111]),
        .I1(Head1),
        .O(\Head[111]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair933" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[11]_i_1__1 
       (.I0(DataIn[6]),
        .I1(Head0_0[11]),
        .I2(Head1),
        .O(p_0_in1_in[11]));
  LUT6 #(
    .INIT(64'h00CC50CC00CCFFCC)) 
    \Head[11]_i_1__9 
       (.I0(empty_ff_reg_0),
        .I1(Head0[8]),
        .I2(\c2h_xdma_wrq_req[0][byte_len] [2]),
        .I3(Head1__2),
        .I4(arbstall),
        .I5(\Head_reg[111]_0 ),
        .O(empty_ff_reg_2[8]));
  (* SOFT_HLUTNM = "soft_lutpair934" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[12]_i_1__1 
       (.I0(DataIn[7]),
        .I1(Head0_0[12]),
        .I2(Head1),
        .O(p_0_in1_in[12]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[12]_i_1__9 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [3]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[9]),
        .O(empty_ff_reg_2[9]));
  (* SOFT_HLUTNM = "soft_lutpair934" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[13]_i_1__1 
       (.I0(DataIn[8]),
        .I1(Head0_0[13]),
        .I2(Head1),
        .O(p_0_in1_in[13]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[13]_i_1__9 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [4]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[10]),
        .O(empty_ff_reg_2[10]));
  (* SOFT_HLUTNM = "soft_lutpair935" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[14]_i_1__1 
       (.I0(DataIn[9]),
        .I1(Head0_0[14]),
        .I2(Head1),
        .O(p_0_in1_in[14]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[14]_i_1__9 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [5]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[11]),
        .O(empty_ff_reg_2[11]));
  (* SOFT_HLUTNM = "soft_lutpair935" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[15]_i_1__1 
       (.I0(DataIn[10]),
        .I1(Head0_0[15]),
        .I2(Head1),
        .O(p_0_in1_in[15]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[15]_i_1__9 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [6]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[12]),
        .O(empty_ff_reg_2[12]));
  (* SOFT_HLUTNM = "soft_lutpair936" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[16]_i_1__0 
       (.I0(DataIn[11]),
        .I1(Head0_0[16]),
        .I2(Head1),
        .O(p_0_in1_in[16]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[16]_i_1__8 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [7]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[13]),
        .O(empty_ff_reg_2[13]));
  (* SOFT_HLUTNM = "soft_lutpair936" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[17]_i_1__0 
       (.I0(DataIn[12]),
        .I1(Head0_0[17]),
        .I2(Head1),
        .O(p_0_in1_in[17]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[17]_i_1__7 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [8]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[14]),
        .O(empty_ff_reg_2[14]));
  (* SOFT_HLUTNM = "soft_lutpair937" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[18]_i_1__0 
       (.I0(DataIn[13]),
        .I1(Head0_0[18]),
        .I2(Head1),
        .O(p_0_in1_in[18]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[18]_i_1__10 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [9]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[15]),
        .O(empty_ff_reg_2[15]));
  (* SOFT_HLUTNM = "soft_lutpair937" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[19]_i_1__0 
       (.I0(DataIn[14]),
        .I1(Head0_0[19]),
        .I2(Head1),
        .O(p_0_in1_in[19]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[19]_i_1__10 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [10]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[16]),
        .O(empty_ff_reg_2[16]));
  (* SOFT_HLUTNM = "soft_lutpair928" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[1]_i_1__0 
       (.I0(DataIn[1]),
        .I1(Head0_0[1]),
        .I2(Head1),
        .O(p_0_in1_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair938" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[20]_i_1__1 
       (.I0(DataIn[15]),
        .I1(Head0_0[20]),
        .I2(Head1),
        .O(p_0_in1_in[20]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[20]_i_1__11 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [11]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[17]),
        .O(empty_ff_reg_2[17]));
  (* SOFT_HLUTNM = "soft_lutpair938" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[21]_i_1__1 
       (.I0(DataIn[16]),
        .I1(Head0_0[21]),
        .I2(Head1),
        .O(p_0_in1_in[21]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[21]_i_1__11 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [12]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[18]),
        .O(empty_ff_reg_2[18]));
  (* SOFT_HLUTNM = "soft_lutpair929" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[2]_i_1 
       (.I0(DataIn[2]),
        .I1(Head0_0[2]),
        .I2(Head1),
        .O(p_0_in1_in[2]));
  LUT6 #(
    .INIT(64'h00CC50CC00CCFFCC)) 
    \Head[2]_i_1__3 
       (.I0(empty_ff_reg_0),
        .I1(Head0[1]),
        .I2(\c2h_xdma_wrq_req[0][eop] ),
        .I3(Head1__2),
        .I4(arbstall),
        .I5(\Head_reg[111]_0 ),
        .O(empty_ff_reg_2[1]));
  (* SOFT_HLUTNM = "soft_lutpair928" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[36]_i_1__1 
       (.I0(Head0_0[36]),
        .I1(Head1),
        .O(\Head[36]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair939" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[37]_i_1__0 
       (.I0(DataIn[17]),
        .I1(Head0_0[37]),
        .I2(Head1),
        .O(p_0_in1_in[37]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[37]_i_1__4 
       (.I0(Head0[19]),
        .I1(empty_ff_reg_1),
        .I2(\c2h_xdma_wrq_req[0][rid] [0]),
        .I3(\wbk_xdma_wrq_req[rid] ),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[19]));
  (* SOFT_HLUTNM = "soft_lutpair939" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[38]_i_1__0 
       (.I0(DataIn[18]),
        .I1(Head0_0[38]),
        .I2(Head1),
        .O(p_0_in1_in[38]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[38]_i_1__4 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][rid] [1]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[20]),
        .O(empty_ff_reg_2[20]));
  (* SOFT_HLUTNM = "soft_lutpair940" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[39]_i_1__0 
       (.I0(DataIn[19]),
        .I1(Head0_0[39]),
        .I2(Head1),
        .O(p_0_in1_in[39]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[39]_i_1__4 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][rid] [2]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[21]),
        .O(empty_ff_reg_2[21]));
  (* SOFT_HLUTNM = "soft_lutpair930" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[3]_i_1__0 
       (.I0(DataIn[3]),
        .I1(Head0_0[3]),
        .I2(Head1),
        .O(p_0_in1_in[3]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[3]_i_1__5 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][aln] [0]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[2]),
        .O(empty_ff_reg_2[2]));
  (* SOFT_HLUTNM = "soft_lutpair940" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[40]_i_1__0 
       (.I0(DataIn[20]),
        .I1(Head0_0[40]),
        .I2(Head1),
        .O(p_0_in1_in[40]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[40]_i_1__4 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][rid] [3]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[22]),
        .O(empty_ff_reg_2[22]));
  (* SOFT_HLUTNM = "soft_lutpair929" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[41]_i_1__2 
       (.I0(Head0_0[41]),
        .I1(Head1),
        .O(\Head[41]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[41]_i_1__4 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][rid] [4]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[23]),
        .O(empty_ff_reg_2[23]));
  (* SOFT_HLUTNM = "soft_lutpair930" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[46]_i_1__3 
       (.I0(Head0_0[46]),
        .I1(Head1),
        .O(\Head[46]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair941" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[47]_i_1__0 
       (.I0(\Head_reg[110]_1 [0]),
        .I1(Head0_0[47]),
        .I2(Head1),
        .O(p_0_in1_in[47]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[47]_i_1__7 
       (.I0(empty_ff_reg_0),
        .I1(p_10_in[0]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[24]),
        .O(empty_ff_reg_2[24]));
  (* SOFT_HLUTNM = "soft_lutpair941" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[48]_i_1__0 
       (.I0(DataIn[21]),
        .I1(Head0_0[48]),
        .I2(Head1),
        .O(p_0_in1_in[48]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[48]_i_1__6 
       (.I0(empty_ff_reg_0),
        .I1(p_10_in[1]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[25]),
        .O(empty_ff_reg_2[25]));
  (* SOFT_HLUTNM = "soft_lutpair942" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[49]_i_1__0 
       (.I0(DataIn[22]),
        .I1(Head0_0[49]),
        .I2(Head1),
        .O(p_0_in1_in[49]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[49]_i_1__6 
       (.I0(Head0[26]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[2]),
        .I3(p_8_in[0]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[26]));
  (* SOFT_HLUTNM = "soft_lutpair931" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[4]_i_1__0 
       (.I0(DataIn[4]),
        .I1(Head0_0[4]),
        .I2(Head1),
        .O(p_0_in1_in[4]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[4]_i_1__5 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][aln] [1]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[3]),
        .O(empty_ff_reg_2[3]));
  (* SOFT_HLUTNM = "soft_lutpair942" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[50]_i_1__0 
       (.I0(DataIn[23]),
        .I1(Head0_0[50]),
        .I2(Head1),
        .O(p_0_in1_in[50]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[50]_i_1__6 
       (.I0(Head0[27]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[3]),
        .I3(p_8_in[1]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[27]));
  (* SOFT_HLUTNM = "soft_lutpair943" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[51]_i_1__0 
       (.I0(DataIn[24]),
        .I1(Head0_0[51]),
        .I2(Head1),
        .O(p_0_in1_in[51]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[51]_i_1__6 
       (.I0(Head0[28]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[4]),
        .I3(p_8_in[2]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[28]));
  (* SOFT_HLUTNM = "soft_lutpair943" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[52]_i_1__0 
       (.I0(DataIn[25]),
        .I1(Head0_0[52]),
        .I2(Head1),
        .O(p_0_in1_in[52]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[52]_i_1__4 
       (.I0(Head0[29]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[5]),
        .I3(p_8_in[3]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[29]));
  (* SOFT_HLUTNM = "soft_lutpair944" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[53]_i_1__0 
       (.I0(DataIn[26]),
        .I1(Head0_0[53]),
        .I2(Head1),
        .O(p_0_in1_in[53]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[53]_i_1__4 
       (.I0(Head0[30]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[6]),
        .I3(p_8_in[4]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[30]));
  (* SOFT_HLUTNM = "soft_lutpair944" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[54]_i_1__0 
       (.I0(DataIn[27]),
        .I1(Head0_0[54]),
        .I2(Head1),
        .O(p_0_in1_in[54]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[54]_i_1__4 
       (.I0(Head0[31]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[7]),
        .I3(p_8_in[5]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[31]));
  (* SOFT_HLUTNM = "soft_lutpair945" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[55]_i_1__0 
       (.I0(DataIn[28]),
        .I1(Head0_0[55]),
        .I2(Head1),
        .O(p_0_in1_in[55]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[55]_i_1__4 
       (.I0(Head0[32]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[8]),
        .I3(p_8_in[6]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[32]));
  (* SOFT_HLUTNM = "soft_lutpair945" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[56]_i_1__0 
       (.I0(DataIn[29]),
        .I1(Head0_0[56]),
        .I2(Head1),
        .O(p_0_in1_in[56]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[56]_i_1__7 
       (.I0(Head0[33]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[9]),
        .I3(p_8_in[7]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[33]));
  (* SOFT_HLUTNM = "soft_lutpair946" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[57]_i_1__0 
       (.I0(DataIn[30]),
        .I1(Head0_0[57]),
        .I2(Head1),
        .O(p_0_in1_in[57]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[57]_i_1__7 
       (.I0(Head0[34]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[10]),
        .I3(p_8_in[8]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[34]));
  (* SOFT_HLUTNM = "soft_lutpair946" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[58]_i_1__0 
       (.I0(DataIn[31]),
        .I1(Head0_0[58]),
        .I2(Head1),
        .O(p_0_in1_in[58]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[58]_i_1__7 
       (.I0(Head0[35]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[11]),
        .I3(p_8_in[9]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[35]));
  (* SOFT_HLUTNM = "soft_lutpair947" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[59]_i_1__0 
       (.I0(DataIn[32]),
        .I1(Head0_0[59]),
        .I2(Head1),
        .O(p_0_in1_in[59]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[59]_i_1__7 
       (.I0(Head0[36]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[12]),
        .I3(p_8_in[10]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[36]));
  (* SOFT_HLUTNM = "soft_lutpair932" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[5]_i_1__0 
       (.I0(DataIn[5]),
        .I1(Head0_0[5]),
        .I2(Head1),
        .O(p_0_in1_in[5]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[5]_i_1__5 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][aln] [2]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[4]),
        .O(empty_ff_reg_2[4]));
  (* SOFT_HLUTNM = "soft_lutpair947" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[60]_i_1__0 
       (.I0(DataIn[33]),
        .I1(Head0_0[60]),
        .I2(Head1),
        .O(p_0_in1_in[60]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[60]_i_1__8 
       (.I0(Head0[37]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[13]),
        .I3(p_8_in[11]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[37]));
  (* SOFT_HLUTNM = "soft_lutpair948" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[61]_i_1__1 
       (.I0(DataIn[34]),
        .I1(Head0_0[61]),
        .I2(Head1),
        .O(p_0_in1_in[61]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[61]_i_1__8 
       (.I0(Head0[38]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[14]),
        .I3(p_8_in[12]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[38]));
  (* SOFT_HLUTNM = "soft_lutpair948" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[62]_i_1__1 
       (.I0(DataIn[35]),
        .I1(Head0_0[62]),
        .I2(Head1),
        .O(p_0_in1_in[62]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[62]_i_1__8 
       (.I0(Head0[39]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[15]),
        .I3(p_8_in[13]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[39]));
  (* SOFT_HLUTNM = "soft_lutpair949" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[63]_i_1__1 
       (.I0(DataIn[36]),
        .I1(Head0_0[63]),
        .I2(Head1),
        .O(p_0_in1_in[63]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[63]_i_1__7 
       (.I0(Head0[40]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[16]),
        .I3(p_8_in[14]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[40]));
  (* SOFT_HLUTNM = "soft_lutpair949" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[64]_i_1__1 
       (.I0(DataIn[37]),
        .I1(Head0_0[64]),
        .I2(Head1),
        .O(p_0_in1_in[64]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[64]_i_1__7 
       (.I0(Head0[41]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[17]),
        .I3(p_8_in[15]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[41]));
  (* SOFT_HLUTNM = "soft_lutpair950" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[65]_i_1__1 
       (.I0(DataIn[38]),
        .I1(Head0_0[65]),
        .I2(Head1),
        .O(p_0_in1_in[65]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[65]_i_1__7 
       (.I0(Head0[42]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[18]),
        .I3(p_8_in[16]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[42]));
  (* SOFT_HLUTNM = "soft_lutpair950" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[66]_i_1__1 
       (.I0(DataIn[39]),
        .I1(Head0_0[66]),
        .I2(Head1),
        .O(p_0_in1_in[66]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[66]_i_1__8 
       (.I0(Head0[43]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[19]),
        .I3(p_8_in[17]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[43]));
  (* SOFT_HLUTNM = "soft_lutpair951" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[67]_i_1__1 
       (.I0(DataIn[40]),
        .I1(Head0_0[67]),
        .I2(Head1),
        .O(p_0_in1_in[67]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[67]_i_1__8 
       (.I0(Head0[44]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[20]),
        .I3(p_8_in[18]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[44]));
  (* SOFT_HLUTNM = "soft_lutpair951" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[68]_i_1__1 
       (.I0(DataIn[41]),
        .I1(Head0_0[68]),
        .I2(Head1),
        .O(p_0_in1_in[68]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[68]_i_1__8 
       (.I0(Head0[45]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[21]),
        .I3(p_8_in[19]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[45]));
  (* SOFT_HLUTNM = "soft_lutpair952" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[69]_i_1__1 
       (.I0(DataIn[42]),
        .I1(Head0_0[69]),
        .I2(Head1),
        .O(p_0_in1_in[69]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[69]_i_1__8 
       (.I0(Head0[46]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[22]),
        .I3(p_8_in[20]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[46]));
  (* SOFT_HLUTNM = "soft_lutpair952" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[70]_i_1__1 
       (.I0(DataIn[43]),
        .I1(Head0_0[70]),
        .I2(Head1),
        .O(p_0_in1_in[70]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[70]_i_1__8 
       (.I0(Head0[47]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[23]),
        .I3(p_8_in[21]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[47]));
  (* SOFT_HLUTNM = "soft_lutpair953" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[71]_i_1__1 
       (.I0(DataIn[44]),
        .I1(Head0_0[71]),
        .I2(Head1),
        .O(p_0_in1_in[71]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[71]_i_1__8 
       (.I0(Head0[48]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[24]),
        .I3(p_8_in[22]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[48]));
  (* SOFT_HLUTNM = "soft_lutpair953" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[72]_i_1__1 
       (.I0(DataIn[45]),
        .I1(Head0_0[72]),
        .I2(Head1),
        .O(p_0_in1_in[72]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[72]_i_1__8 
       (.I0(Head0[49]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[25]),
        .I3(p_8_in[23]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[49]));
  (* SOFT_HLUTNM = "soft_lutpair954" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[73]_i_1__1 
       (.I0(DataIn[46]),
        .I1(Head0_0[73]),
        .I2(Head1),
        .O(p_0_in1_in[73]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[73]_i_1__8 
       (.I0(Head0[50]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[26]),
        .I3(p_8_in[24]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[50]));
  (* SOFT_HLUTNM = "soft_lutpair954" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[74]_i_1__1 
       (.I0(DataIn[47]),
        .I1(Head0_0[74]),
        .I2(Head1),
        .O(p_0_in1_in[74]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[74]_i_1__7 
       (.I0(Head0[51]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[27]),
        .I3(p_8_in[25]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[51]));
  (* SOFT_HLUTNM = "soft_lutpair955" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[75]_i_1__1 
       (.I0(DataIn[48]),
        .I1(Head0_0[75]),
        .I2(Head1),
        .O(p_0_in1_in[75]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[75]_i_1__7 
       (.I0(Head0[52]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[28]),
        .I3(p_8_in[26]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[52]));
  (* SOFT_HLUTNM = "soft_lutpair955" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[76]_i_1__1 
       (.I0(DataIn[49]),
        .I1(Head0_0[76]),
        .I2(Head1),
        .O(p_0_in1_in[76]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[76]_i_1__7 
       (.I0(Head0[53]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[29]),
        .I3(p_8_in[27]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[53]));
  (* SOFT_HLUTNM = "soft_lutpair956" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[77]_i_1__1 
       (.I0(DataIn[50]),
        .I1(Head0_0[77]),
        .I2(Head1),
        .O(p_0_in1_in[77]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[77]_i_1__7 
       (.I0(Head0[54]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[30]),
        .I3(p_8_in[28]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[54]));
  (* SOFT_HLUTNM = "soft_lutpair956" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[78]_i_1__1 
       (.I0(DataIn[51]),
        .I1(Head0_0[78]),
        .I2(Head1),
        .O(p_0_in1_in[78]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[78]_i_1__7 
       (.I0(Head0[55]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[31]),
        .I3(p_8_in[29]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[55]));
  (* SOFT_HLUTNM = "soft_lutpair957" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[79]_i_1__1 
       (.I0(DataIn[52]),
        .I1(Head0_0[79]),
        .I2(Head1),
        .O(p_0_in1_in[79]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[79]_i_1__7 
       (.I0(Head0[56]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[32]),
        .I3(p_8_in[30]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[56]));
  (* SOFT_HLUTNM = "soft_lutpair957" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[80]_i_1__1 
       (.I0(DataIn[53]),
        .I1(Head0_0[80]),
        .I2(Head1),
        .O(p_0_in1_in[80]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[80]_i_1__7 
       (.I0(Head0[57]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[33]),
        .I3(p_8_in[31]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[57]));
  (* SOFT_HLUTNM = "soft_lutpair958" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[81]_i_1__1 
       (.I0(DataIn[54]),
        .I1(Head0_0[81]),
        .I2(Head1),
        .O(p_0_in1_in[81]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[81]_i_1__7 
       (.I0(Head0[58]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[34]),
        .I3(p_8_in[32]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[58]));
  (* SOFT_HLUTNM = "soft_lutpair958" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[82]_i_1__1 
       (.I0(DataIn[55]),
        .I1(Head0_0[82]),
        .I2(Head1),
        .O(p_0_in1_in[82]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[82]_i_1__7 
       (.I0(Head0[59]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[35]),
        .I3(p_8_in[33]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[59]));
  (* SOFT_HLUTNM = "soft_lutpair959" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[83]_i_1__1 
       (.I0(DataIn[56]),
        .I1(Head0_0[83]),
        .I2(Head1),
        .O(p_0_in1_in[83]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[83]_i_1__7 
       (.I0(Head0[60]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[36]),
        .I3(p_8_in[34]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[60]));
  (* SOFT_HLUTNM = "soft_lutpair959" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[84]_i_1__1 
       (.I0(DataIn[57]),
        .I1(Head0_0[84]),
        .I2(Head1),
        .O(p_0_in1_in[84]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[84]_i_1__7 
       (.I0(Head0[61]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[37]),
        .I3(p_8_in[35]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[61]));
  (* SOFT_HLUTNM = "soft_lutpair960" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[85]_i_1__1 
       (.I0(DataIn[58]),
        .I1(Head0_0[85]),
        .I2(Head1),
        .O(p_0_in1_in[85]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[85]_i_1__7 
       (.I0(Head0[62]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[38]),
        .I3(p_8_in[36]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[62]));
  (* SOFT_HLUTNM = "soft_lutpair960" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[86]_i_1__1 
       (.I0(DataIn[59]),
        .I1(Head0_0[86]),
        .I2(Head1),
        .O(p_0_in1_in[86]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[86]_i_1__7 
       (.I0(Head0[63]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[39]),
        .I3(p_8_in[37]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[63]));
  (* SOFT_HLUTNM = "soft_lutpair961" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[87]_i_1__1 
       (.I0(DataIn[60]),
        .I1(Head0_0[87]),
        .I2(Head1),
        .O(p_0_in1_in[87]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[87]_i_1__7 
       (.I0(Head0[64]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[40]),
        .I3(p_8_in[38]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[64]));
  (* SOFT_HLUTNM = "soft_lutpair961" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[88]_i_1__1 
       (.I0(DataIn[61]),
        .I1(Head0_0[88]),
        .I2(Head1),
        .O(p_0_in1_in[88]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[88]_i_1__7 
       (.I0(Head0[65]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[41]),
        .I3(p_8_in[39]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[65]));
  (* SOFT_HLUTNM = "soft_lutpair962" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[89]_i_1__1 
       (.I0(DataIn[62]),
        .I1(Head0_0[89]),
        .I2(Head1),
        .O(p_0_in1_in[89]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[89]_i_1__7 
       (.I0(Head0[66]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[42]),
        .I3(p_8_in[40]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[66]));
  (* SOFT_HLUTNM = "soft_lutpair927" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[8]_i_1__3 
       (.I0(Head0_0[8]),
        .I1(Head1),
        .O(\Head[8]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[8]_i_1__8 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][aln] [5]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[5]),
        .O(empty_ff_reg_2[5]));
  (* SOFT_HLUTNM = "soft_lutpair962" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[90]_i_1__1 
       (.I0(DataIn[63]),
        .I1(Head0_0[90]),
        .I2(Head1),
        .O(p_0_in1_in[90]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[90]_i_1__8 
       (.I0(Head0[67]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[43]),
        .I3(p_8_in[41]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[67]));
  (* SOFT_HLUTNM = "soft_lutpair963" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[91]_i_1__1 
       (.I0(DataIn[64]),
        .I1(Head0_0[91]),
        .I2(Head1),
        .O(p_0_in1_in[91]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[91]_i_1__8 
       (.I0(Head0[68]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[44]),
        .I3(p_8_in[42]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[68]));
  (* SOFT_HLUTNM = "soft_lutpair963" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[92]_i_1__1 
       (.I0(DataIn[65]),
        .I1(Head0_0[92]),
        .I2(Head1),
        .O(p_0_in1_in[92]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[92]_i_1__8 
       (.I0(Head0[69]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[45]),
        .I3(p_8_in[43]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[69]));
  (* SOFT_HLUTNM = "soft_lutpair964" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[93]_i_1__1 
       (.I0(DataIn[66]),
        .I1(Head0_0[93]),
        .I2(Head1),
        .O(p_0_in1_in[93]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[93]_i_1__8 
       (.I0(Head0[70]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[46]),
        .I3(p_8_in[44]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[70]));
  (* SOFT_HLUTNM = "soft_lutpair964" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[94]_i_1__1 
       (.I0(DataIn[67]),
        .I1(Head0_0[94]),
        .I2(Head1),
        .O(p_0_in1_in[94]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[94]_i_1__7 
       (.I0(Head0[71]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[47]),
        .I3(p_8_in[45]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[71]));
  (* SOFT_HLUTNM = "soft_lutpair965" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[95]_i_1__1 
       (.I0(DataIn[68]),
        .I1(Head0_0[95]),
        .I2(Head1),
        .O(p_0_in1_in[95]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[95]_i_1__7 
       (.I0(Head0[72]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[48]),
        .I3(p_8_in[46]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[72]));
  (* SOFT_HLUTNM = "soft_lutpair965" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[96]_i_1__1 
       (.I0(DataIn[69]),
        .I1(Head0_0[96]),
        .I2(Head1),
        .O(p_0_in1_in[96]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[96]_i_1__7 
       (.I0(Head0[73]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[49]),
        .I3(p_8_in[47]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[73]));
  (* SOFT_HLUTNM = "soft_lutpair966" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[97]_i_1__1 
       (.I0(DataIn[70]),
        .I1(Head0_0[97]),
        .I2(Head1),
        .O(p_0_in1_in[97]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[97]_i_1__7 
       (.I0(Head0[74]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[50]),
        .I3(p_8_in[48]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[74]));
  (* SOFT_HLUTNM = "soft_lutpair966" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[98]_i_1__1 
       (.I0(DataIn[71]),
        .I1(Head0_0[98]),
        .I2(Head1),
        .O(p_0_in1_in[98]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[98]_i_1__7 
       (.I0(Head0[75]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[51]),
        .I3(p_8_in[49]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[75]));
  (* SOFT_HLUTNM = "soft_lutpair967" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[99]_i_1__1 
       (.I0(DataIn[72]),
        .I1(Head0_0[99]),
        .I2(Head1),
        .O(p_0_in1_in[99]));
  LUT6 #(
    .INIT(64'hFFC0AAAAC0C0AAAA)) 
    \Head[99]_i_1__7 
       (.I0(Head0[76]),
        .I1(empty_ff_reg_1),
        .I2(p_10_in[52]),
        .I3(p_8_in[50]),
        .I4(Head1__2),
        .I5(\Head_reg[110]_0 ),
        .O(empty_ff_reg_2[76]));
  (* SOFT_HLUTNM = "soft_lutpair932" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[9]_i_1__1 
       (.I0(\Head_reg[10]_0 [0]),
        .I1(Head0_0[9]),
        .I2(Head1),
        .O(p_0_in1_in[9]));
  LUT6 #(
    .INIT(64'h0400FFFF04000000)) 
    \Head[9]_i_1__8 
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [0]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .I4(Head1__2),
        .I5(Head0[6]),
        .O(empty_ff_reg_2[6]));
  FDRE \Head_reg[0] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[0]),
        .Q(\c2h_xdma_wrq_req[0][eor] ),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[100] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[100]),
        .Q(p_10_in[53]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[101] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[101]),
        .Q(p_10_in[54]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[102] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[102]),
        .Q(p_10_in[55]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[103] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[103]),
        .Q(p_10_in[56]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[104] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[104]),
        .Q(p_10_in[57]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[105] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[105]),
        .Q(p_10_in[58]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[106] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[106]),
        .Q(p_10_in[59]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[107] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[107]),
        .Q(p_10_in[60]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[108] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[108]),
        .Q(p_10_in[61]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[109] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[109]),
        .Q(p_10_in[62]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[10]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [1]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[110] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[110]),
        .Q(p_10_in[63]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[111] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(\Head[111]_i_2_n_0 ),
        .Q(p_11_in__0),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[11]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [2]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[12]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [3]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[13]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [4]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[14]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [5]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[15]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [6]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[16] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[16]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [7]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[17] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[17]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [8]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[18]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [9]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[19]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [10]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[1] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[1]),
        .Q(\c2h_xdma_wrq_req[0][eod] ),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[20]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [11]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[21]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [12]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[2] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[2]),
        .Q(\c2h_xdma_wrq_req[0][eop] ),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[36] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(\Head[36]_i_1__1_n_0 ),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [27]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[37] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[37]),
        .Q(\c2h_xdma_wrq_req[0][rid] [0]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[38] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[38]),
        .Q(\c2h_xdma_wrq_req[0][rid] [1]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[39] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[39]),
        .Q(\c2h_xdma_wrq_req[0][rid] [2]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[3] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[3]),
        .Q(\c2h_xdma_wrq_req[0][aln] [0]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[40] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[40]),
        .Q(\c2h_xdma_wrq_req[0][rid] [3]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[41] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(\Head[41]_i_1__2_n_0 ),
        .Q(\c2h_xdma_wrq_req[0][rid] [4]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[46] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(\Head[46]_i_1__3_n_0 ),
        .Q(\c2h_xdma_wrq_req[0][rid] [9]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[47] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[47]),
        .Q(p_10_in[0]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[48] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[48]),
        .Q(p_10_in[1]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[49] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[49]),
        .Q(p_10_in[2]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[4] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[4]),
        .Q(\c2h_xdma_wrq_req[0][aln] [1]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[50] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[50]),
        .Q(p_10_in[3]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[51] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[51]),
        .Q(p_10_in[4]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[52] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[52]),
        .Q(p_10_in[5]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[53] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[53]),
        .Q(p_10_in[6]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[54] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[54]),
        .Q(p_10_in[7]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[55] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[55]),
        .Q(p_10_in[8]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[56] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[56]),
        .Q(p_10_in[9]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[57] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[57]),
        .Q(p_10_in[10]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[58] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[58]),
        .Q(p_10_in[11]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[59] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[59]),
        .Q(p_10_in[12]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[5] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[5]),
        .Q(\c2h_xdma_wrq_req[0][aln] [2]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[60]),
        .Q(p_10_in[13]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[61]),
        .Q(p_10_in[14]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[62]),
        .Q(p_10_in[15]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[63]),
        .Q(p_10_in[16]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[64] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[64]),
        .Q(p_10_in[17]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[65] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[65]),
        .Q(p_10_in[18]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[66]),
        .Q(p_10_in[19]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[67]),
        .Q(p_10_in[20]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[68]),
        .Q(p_10_in[21]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[69]),
        .Q(p_10_in[22]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[70]),
        .Q(p_10_in[23]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[71]),
        .Q(p_10_in[24]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[72]),
        .Q(p_10_in[25]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[73]),
        .Q(p_10_in[26]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[74] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[74]),
        .Q(p_10_in[27]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[75] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[75]),
        .Q(p_10_in[28]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[76] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[76]),
        .Q(p_10_in[29]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[77] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[77]),
        .Q(p_10_in[30]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[78] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[78]),
        .Q(p_10_in[31]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[79] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[79]),
        .Q(p_10_in[32]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[80] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[80]),
        .Q(p_10_in[33]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[81] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[81]),
        .Q(p_10_in[34]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[82] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[82]),
        .Q(p_10_in[35]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[83] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[83]),
        .Q(p_10_in[36]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[84] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[84]),
        .Q(p_10_in[37]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[85] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[85]),
        .Q(p_10_in[38]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[86] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[86]),
        .Q(p_10_in[39]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[87] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[87]),
        .Q(p_10_in[40]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[88] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[88]),
        .Q(p_10_in[41]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[89] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[89]),
        .Q(p_10_in[42]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[8] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(\Head[8]_i_1__3_n_0 ),
        .Q(\c2h_xdma_wrq_req[0][aln] [5]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[90]),
        .Q(p_10_in[43]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[91]),
        .Q(p_10_in[44]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[92]),
        .Q(p_10_in[45]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[93]),
        .Q(p_10_in[46]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[94] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[94]),
        .Q(p_10_in[47]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[95] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[95]),
        .Q(p_10_in[48]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[96] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[96]),
        .Q(p_10_in[49]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[97] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[97]),
        .Q(p_10_in[50]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[98] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[98]),
        .Q(p_10_in[51]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[99] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[99]),
        .Q(p_10_in[52]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \Head_reg[9] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__1_n_0 ),
        .D(p_0_in1_in[9]),
        .Q(\c2h_xdma_wrq_req[0][byte_len] [0]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_3_0_5
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[1:0]),
        .DIB(DataIn[3:2]),
        .DIC(DataIn[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[1:0]),
        .DOB(Head0_0[3:2]),
        .DOC(Head0_0[5:4]),
        .DOD(NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h13)) 
    MemArray_reg_0_3_0_5_i_1__3
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .O(empty_ff_reg_3));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_0_5_i_2__2
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][eod] ),
        .O(payloadmuxed[1]));
  LUT4 #(
    .INIT(16'h040F)) 
    MemArray_reg_0_3_0_5_i_3__2
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][eor] ),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .O(payloadmuxed[0]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_0_5_i_4__2
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][aln] [0]),
        .O(payloadmuxed[3]));
  LUT4 #(
    .INIT(16'h040F)) 
    MemArray_reg_0_3_0_5_i_5__2
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][eop] ),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .O(payloadmuxed[2]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_0_5_i_6__2
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][aln] [2]),
        .O(payloadmuxed[5]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_0_5_i_7__2
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][aln] [1]),
        .O(payloadmuxed[4]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_102_107" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "102" *) 
  (* ram_slice_end = "107" *) 
  RAM32M MemArray_reg_0_3_102_107
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[76:75]),
        .DIB(DataIn[78:77]),
        .DIC(DataIn[80:79]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[103:102]),
        .DOB(Head0_0[105:104]),
        .DOC(Head0_0[107:106]),
        .DOD(NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_102_107_i_1__0
       (.I0(Q[54]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [54]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[56]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[83]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_102_107_i_2__0
       (.I0(Q[53]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [53]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[55]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[82]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_102_107_i_3__0
       (.I0(Q[56]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [56]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[58]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[85]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_102_107_i_4__0
       (.I0(Q[55]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [55]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[57]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[84]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_102_107_i_5__0
       (.I0(Q[58]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [58]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[60]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[87]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_102_107_i_6__0
       (.I0(Q[57]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [57]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[59]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[86]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_108_112_i_1
       (.I0(Q[60]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [60]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[62]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[89]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_108_112_i_2
       (.I0(Q[59]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [59]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[61]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[88]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_108_112_i_3
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(p_11_in__0),
        .O(payloadmuxed[91]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_108_112_i_4
       (.I0(Q[61]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [61]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[63]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[90]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[8:7]),
        .DIB(DataIn[10:9]),
        .DIC(DataIn[12:11]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[13:12]),
        .DOB(Head0_0[15:14]),
        .DOC(Head0_0[17:16]),
        .DOD(NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_12_17_i_1__3
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [4]),
        .O(payloadmuxed[11]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_12_17_i_2__3
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [3]),
        .O(payloadmuxed[10]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_12_17_i_3__3
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [6]),
        .O(payloadmuxed[13]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_12_17_i_4__3
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [5]),
        .O(payloadmuxed[12]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_12_17_i_5__2
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [8]),
        .O(payloadmuxed[15]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_12_17_i_6__2
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [7]),
        .O(payloadmuxed[14]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[14:13]),
        .DIB(DataIn[16:15]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[19:18]),
        .DOB(Head0_0[21:20]),
        .DOC(NLW_MemArray_reg_0_3_18_23_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_18_23_i_1__1
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [10]),
        .O(payloadmuxed[17]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_18_23_i_2__1
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [9]),
        .O(payloadmuxed[16]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_18_23_i_3__2
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [12]),
        .O(payloadmuxed[19]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_18_23_i_4__2
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [11]),
        .O(payloadmuxed[18]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_36_41" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M MemArray_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({DataIn[17],1'b0}),
        .DIB(DataIn[19:18]),
        .DIC({1'b0,DataIn[20]}),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[37:36]),
        .DOB(Head0_0[39:38]),
        .DOC(Head0_0[41:40]),
        .DOD(NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT5 #(
    .INIT(32'h000050CC)) 
    MemArray_reg_0_3_36_41_i_1
       (.I0(empty_ff_reg_0),
        .I1(\wbk_xdma_wrq_req[rid] ),
        .I2(\c2h_xdma_wrq_req[0][rid] [0]),
        .I3(\Head_reg[111]_0 ),
        .I4(arbstall),
        .O(payloadmuxed[21]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_36_41_i_2
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [27]),
        .O(payloadmuxed[20]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_36_41_i_3
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][rid] [2]),
        .O(payloadmuxed[23]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_36_41_i_4
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][rid] [1]),
        .O(payloadmuxed[22]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_36_41_i_5
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][rid] [4]),
        .O(payloadmuxed[25]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_36_41_i_6
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][rid] [3]),
        .O(payloadmuxed[24]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_42_47" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M MemArray_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({\Head_reg[110]_1 [0],1'b0}),
        .DIB(\Head_reg[110]_1 [2:1]),
        .DIC({1'b0,\Head_reg[110]_1 [3]}),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[47:46]),
        .DOB(Head0_0[109:108]),
        .DOC(Head0_0[111:110]),
        .DOD(NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_42_47_i_1__0
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(p_10_in[0]),
        .O(payloadmuxed[27]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_42_47_i_2__0
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][rid] [9]),
        .O(payloadmuxed[26]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_48_53" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M MemArray_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[22:21]),
        .DIB(DataIn[24:23]),
        .DIC(DataIn[26:25]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[49:48]),
        .DOB(Head0_0[51:50]),
        .DOC(Head0_0[53:52]),
        .DOD(NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_48_53_i_1
       (.I0(Q[0]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [0]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[2]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[29]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_48_53_i_2
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(p_10_in[1]),
        .O(payloadmuxed[28]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_48_53_i_3
       (.I0(Q[2]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [2]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[4]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[31]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_48_53_i_4
       (.I0(Q[1]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [1]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[3]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[30]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_48_53_i_5
       (.I0(Q[4]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [4]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[6]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[33]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_48_53_i_6
       (.I0(Q[3]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [3]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[5]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[32]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_54_59" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M MemArray_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[28:27]),
        .DIB(DataIn[30:29]),
        .DIC(DataIn[32:31]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[55:54]),
        .DOB(Head0_0[57:56]),
        .DOC(Head0_0[59:58]),
        .DOD(NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_54_59_i_1
       (.I0(Q[6]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [6]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[8]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[35]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_54_59_i_2
       (.I0(Q[5]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [5]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[7]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[34]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_54_59_i_3
       (.I0(Q[8]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [8]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[10]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[37]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_54_59_i_4
       (.I0(Q[7]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [7]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[9]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[36]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_54_59_i_5
       (.I0(Q[10]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [10]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[12]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[39]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_54_59_i_6
       (.I0(Q[9]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [9]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[11]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[38]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_60_65" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M MemArray_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[34:33]),
        .DIB(DataIn[36:35]),
        .DIC(DataIn[38:37]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[61:60]),
        .DOB(Head0_0[63:62]),
        .DOC(Head0_0[65:64]),
        .DOD(NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_60_65_i_1__0
       (.I0(Q[12]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [12]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[14]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[41]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_60_65_i_2__0
       (.I0(Q[11]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [11]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[13]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[40]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_60_65_i_3__0
       (.I0(Q[14]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [14]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[16]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[43]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_60_65_i_4__0
       (.I0(Q[13]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [13]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[15]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[42]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_60_65_i_5__0
       (.I0(Q[16]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [16]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[18]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[45]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_60_65_i_6__0
       (.I0(Q[15]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [15]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[17]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[44]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_66_71" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M MemArray_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[40:39]),
        .DIB(DataIn[42:41]),
        .DIC(DataIn[44:43]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[67:66]),
        .DOB(Head0_0[69:68]),
        .DOC(Head0_0[71:70]),
        .DOD(NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_66_71_i_1__0
       (.I0(Q[18]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [18]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[20]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[47]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_66_71_i_2__0
       (.I0(Q[17]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [17]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[19]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[46]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_66_71_i_3__0
       (.I0(Q[20]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [20]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[22]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[49]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_66_71_i_4__0
       (.I0(Q[19]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [19]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[21]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[48]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_66_71_i_5__0
       (.I0(Q[22]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [22]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[24]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[51]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_66_71_i_6__0
       (.I0(Q[21]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [21]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[23]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[50]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({\Head_reg[10]_0 [0],1'b0}),
        .DIB({DataIn[6],\Head_reg[10]_0 [1]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[9:8]),
        .DOB(Head0_0[11:10]),
        .DOC(NLW_MemArray_reg_0_3_6_11_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_6_11_i_1__3
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [0]),
        .O(payloadmuxed[7]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_6_11_i_2__3
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][aln] [5]),
        .O(payloadmuxed[6]));
  LUT4 #(
    .INIT(16'h040F)) 
    MemArray_reg_0_3_6_11_i_3__3
       (.I0(empty_ff_reg_0),
        .I1(\c2h_xdma_wrq_req[0][byte_len] [2]),
        .I2(arbstall),
        .I3(\Head_reg[111]_0 ),
        .O(payloadmuxed[9]));
  LUT4 #(
    .INIT(16'h1000)) 
    MemArray_reg_0_3_6_11_i_4__3
       (.I0(empty_ff_reg_0),
        .I1(arbstall),
        .I2(\Head_reg[111]_0 ),
        .I3(\c2h_xdma_wrq_req[0][byte_len] [1]),
        .O(payloadmuxed[8]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_72_77" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M MemArray_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[46:45]),
        .DIB(DataIn[48:47]),
        .DIC(DataIn[50:49]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[73:72]),
        .DOB(Head0_0[75:74]),
        .DOC(Head0_0[77:76]),
        .DOD(NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_72_77_i_1__0
       (.I0(Q[24]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [24]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[26]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[53]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_72_77_i_2__0
       (.I0(Q[23]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [23]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[25]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[52]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_72_77_i_3__0
       (.I0(Q[26]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [26]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[28]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[55]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_72_77_i_4__0
       (.I0(Q[25]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [25]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[27]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[54]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_72_77_i_5__0
       (.I0(Q[28]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [28]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[30]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[57]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_72_77_i_6__0
       (.I0(Q[27]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [27]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[29]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[56]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_78_83" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "83" *) 
  RAM32M MemArray_reg_0_3_78_83
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[52:51]),
        .DIB(DataIn[54:53]),
        .DIC(DataIn[56:55]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[79:78]),
        .DOB(Head0_0[81:80]),
        .DOC(Head0_0[83:82]),
        .DOD(NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_78_83_i_1__0
       (.I0(Q[30]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [30]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[32]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[59]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_78_83_i_2__0
       (.I0(Q[29]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [29]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[31]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[58]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_78_83_i_3__0
       (.I0(Q[32]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [32]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[34]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[61]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_78_83_i_4__0
       (.I0(Q[31]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [31]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[33]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[60]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_78_83_i_5__0
       (.I0(Q[34]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [34]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[36]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[63]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_78_83_i_6__0
       (.I0(Q[33]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [33]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[35]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[62]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_84_89" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "84" *) 
  (* ram_slice_end = "89" *) 
  RAM32M MemArray_reg_0_3_84_89
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[58:57]),
        .DIB(DataIn[60:59]),
        .DIC(DataIn[62:61]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[85:84]),
        .DOB(Head0_0[87:86]),
        .DOC(Head0_0[89:88]),
        .DOD(NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_84_89_i_1__0
       (.I0(Q[36]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [36]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[38]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[65]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_84_89_i_2__0
       (.I0(Q[35]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [35]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[37]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[64]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_84_89_i_3__0
       (.I0(Q[38]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [38]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[40]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[67]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_84_89_i_4__0
       (.I0(Q[37]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [37]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[39]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[66]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_84_89_i_5__0
       (.I0(Q[40]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [40]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[42]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[69]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_84_89_i_6__0
       (.I0(Q[39]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [39]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[41]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[68]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_90_95" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "90" *) 
  (* ram_slice_end = "95" *) 
  RAM32M MemArray_reg_0_3_90_95
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[64:63]),
        .DIB(DataIn[66:65]),
        .DIC(DataIn[68:67]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[91:90]),
        .DOB(Head0_0[93:92]),
        .DOC(Head0_0[95:94]),
        .DOD(NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_90_95_i_1__0
       (.I0(Q[42]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [42]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[44]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[71]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_90_95_i_2__0
       (.I0(Q[41]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [41]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[43]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[70]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_90_95_i_3__0
       (.I0(Q[44]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [44]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[46]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[73]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_90_95_i_4__0
       (.I0(Q[43]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [43]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[45]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[72]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_90_95_i_5__0
       (.I0(Q[46]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [46]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[48]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[75]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_90_95_i_6__0
       (.I0(Q[45]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [45]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[47]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[74]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_96_101" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "96" *) 
  (* ram_slice_end = "101" *) 
  RAM32M MemArray_reg_0_3_96_101
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[70:69]),
        .DIB(DataIn[72:71]),
        .DIC(DataIn[74:73]),
        .DID({1'b0,1'b0}),
        .DOA(Head0_0[97:96]),
        .DOB(Head0_0[99:98]),
        .DOC(Head0_0[101:100]),
        .DOD(NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_96_101_i_1__0
       (.I0(Q[48]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [48]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[50]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[77]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_96_101_i_2__0
       (.I0(Q[47]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [47]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[49]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[76]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_96_101_i_3__0
       (.I0(Q[50]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [50]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[52]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[79]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_96_101_i_4__0
       (.I0(Q[49]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [49]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[51]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[78]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_96_101_i_5__0
       (.I0(Q[52]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [52]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[54]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[81]));
  LUT6 #(
    .INIT(64'hFFFFAC00AC00AC00)) 
    MemArray_reg_0_3_96_101_i_6__0
       (.I0(Q[51]),
        .I1(\axidma_wrq_arb/Fifowhead.fifoInfo/MemArray_reg_0_3_108_112 [51]),
        .I2(\wbk_xdma_wrq_req[rid] ),
        .I3(\Head_reg[110]_0 ),
        .I4(p_10_in[53]),
        .I5(empty_ff_reg_1),
        .O(payloadmuxed[80]));
  LUT6 #(
    .INIT(64'h555555559A9A9AAA)) 
    \RdPtr[0]_i_1__1 
       (.I0(RdPtr[0]),
        .I1(empty_ff_reg_0),
        .I2(empty_ff_reg_1),
        .I3(FifoCntrRd[2]),
        .I4(FifoCntrRd[1]),
        .I5(Head1),
        .O(RdPtr__0[0]));
  LUT6 #(
    .INIT(64'h55577777AAA88888)) 
    \RdPtr[1]_i_1__1 
       (.I0(RdPtr[0]),
        .I1(Head1),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[2]),
        .I4(\RdPtr[1]_i_3_n_0 ),
        .I5(RdPtr[1]),
        .O(RdPtr__0[1]));
  LUT6 #(
    .INIT(64'h0103010100000000)) 
    \RdPtr[1]_i_2__0 
       (.I0(FifoCntrRd[0]),
        .I1(FifoCntrRd[2]),
        .I2(FifoCntrRd[1]),
        .I3(empty_ff_reg_0),
        .I4(empty_ff_reg_1),
        .I5(wrq_vld_303),
        .O(Head1));
  LUT2 #(
    .INIT(4'h2)) 
    \RdPtr[1]_i_3 
       (.I0(empty_ff_reg_1),
        .I1(empty_ff_reg_0),
        .O(\RdPtr[1]_i_3_n_0 ));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[0]),
        .Q(RdPtr[0]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(RdPtr[1]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  (* SOFT_HLUTNM = "soft_lutpair973" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \WrPtr[0]_i_1__1 
       (.I0(WrPtr[0]),
        .I1(wrq_vld_303),
        .O(WrPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair973" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \WrPtr[1]_i_1__1 
       (.I0(WrPtr[0]),
        .I1(wrq_vld_303),
        .I2(WrPtr[1]),
        .O(WrPtr__0[1]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[0]),
        .Q(WrPtr[0]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[1]),
        .Q(WrPtr[1]),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0100)) 
    empty_ff_i_1__1
       (.I0(FifoCntrRd[1]),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[2]),
        .I3(empty_ff_reg_0),
        .I4(empty_ff_i_2__1_n_0),
        .I5(empty_ff_reg_4),
        .O(empty_ff_i_1__1_n_0));
  LUT6 #(
    .INIT(64'hAAABABABAAABAAAB)) 
    empty_ff_i_2__1
       (.I0(cfg_linkdown_nn1),
        .I1(FifoCntrRd[2]),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[0]),
        .I4(empty_ff_reg_0),
        .I5(empty_ff_reg_1),
        .O(empty_ff_i_2__1_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__1_n_0),
        .Q(empty_ff_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFF801180)) 
    full_ff_i_1__0
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(wrq_vld_303),
        .I3(FifoCntrWr[2]),
        .I4(full_ff_reg_n_0),
        .O(full_ff_i_1__0_n_0));
  FDRE full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(full_ff_i_1__0_n_0),
        .Q(full_ff_reg_n_0),
        .R(\pcie_c2h_rst_3ff_reg[0]_rep__4 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    wrq_vld_303_i_1
       (.I0(D[3]),
        .I1(D[1]),
        .I2(wrq_vld_303_reg_1),
        .I3(D[0]),
        .I4(D[2]),
        .I5(wrq_vld_303_i_3__0_n_0),
        .O(wrq_vld_302));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFEFFFF)) 
    wrq_vld_303_i_3__0
       (.I0(full_ff_reg_n_0),
        .I1(wrq_stall_302),
        .I2(wrq_vld_303),
        .I3(wrq_vld_303_reg),
        .I4(CO),
        .I5(wrq_vld_303_reg_0),
        .O(wrq_vld_303_i_3__0_n_0));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFOHead" *) 
module xdma_0_xdma_v4_1_29_GenericFIFOHead__parameterized3_45
   (payloadmuxed_1,
    empty_ff_reg_rep_0,
    \Head_reg[110]_0 ,
    empty_ff_reg_rep__0_0,
    p_15_in,
    empty_ff_reg_0,
    wrq_vld_302,
    \Head_reg[0]_0 ,
    wrq_vld_303,
    cfg_linkdown_nn1,
    D,
    wrq_vld_303_reg,
    Q,
    ctl_rst,
    wcp_vlderr_401,
    wrq_rcp_dat_err_302,
    CO,
    wrq_vld_303_i_2__0_0,
    wrq_stall_302,
    full_ff_reg_0,
    user_clk,
    DataIn,
    \Head_reg[10]_0 ,
    \Head_reg[110]_1 ,
    empty_ff_reg_1);
  output [91:0]payloadmuxed_1;
  output empty_ff_reg_rep_0;
  output [86:0]\Head_reg[110]_0 ;
  output empty_ff_reg_rep__0_0;
  output p_15_in;
  output empty_ff_reg_0;
  output wrq_vld_302;
  input \Head_reg[0]_0 ;
  input wrq_vld_303;
  input cfg_linkdown_nn1;
  input [4:0]D;
  input wrq_vld_303_reg;
  input [1:0]Q;
  input ctl_rst;
  input wcp_vlderr_401;
  input wrq_rcp_dat_err_302;
  input [0:0]CO;
  input [0:0]wrq_vld_303_i_2__0_0;
  input wrq_stall_302;
  input full_ff_reg_0;
  input user_clk;
  input [81:0]DataIn;
  input [1:0]\Head_reg[10]_0 ;
  input [3:0]\Head_reg[110]_1 ;
  input empty_ff_reg_1;

  wire [0:0]CO;
  wire [4:0]D;
  wire [81:0]DataIn;
  wire [2:0]FifoCntrRd;
  wire \FifoCntrRd[0]_i_1__15_n_0 ;
  wire \FifoCntrRd[1]_i_1__15_n_0 ;
  wire \FifoCntrRd[2]_i_2__10_n_0 ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__17_n_0 ;
  wire \FifoCntrWr[1]_i_1__17_n_0 ;
  wire \FifoCntrWr[2]_i_1__16_n_0 ;
  wire [111:0]Head0;
  wire Head1;
  wire \Head[111]_i_1__8_n_0 ;
  wire \Head[111]_i_2__0_n_0 ;
  wire \Head[36]_i_1__2_n_0 ;
  wire \Head[46]_i_1__4_n_0 ;
  wire \Head[8]_i_1__4_n_0 ;
  wire \Head_reg[0]_0 ;
  wire [1:0]\Head_reg[10]_0 ;
  wire [86:0]\Head_reg[110]_0 ;
  wire [3:0]\Head_reg[110]_1 ;
  wire [1:0]Q;
  wire [1:0]RdPtr;
  wire \RdPtr[1]_i_3__1_n_0 ;
  wire [1:0]RdPtr__0;
  wire [1:0]WrPtr;
  wire [1:0]WrPtr__0;
  wire cfg_linkdown_nn1;
  wire ctl_rst;
  wire empty_ff_i_1__4_n_0;
  wire empty_ff_i_2__9_n_0;
  wire empty_ff_reg_0;
  wire empty_ff_reg_1;
  wire empty_ff_reg_rep_0;
  wire empty_ff_reg_rep__0_0;
  wire empty_ff_rep__0_i_1_n_0;
  wire empty_ff_rep_i_1_n_0;
  wire full_ff_i_1__2_n_0;
  wire full_ff_reg_0;
  wire full_ff_reg_n_0;
  wire [27:27]\h2c_xdma_wrq_req[0][byte_len] ;
  wire \h2c_xdma_wrq_req[0][eod] ;
  wire \h2c_xdma_wrq_req[0][eop] ;
  wire \h2c_xdma_wrq_req[0][err] ;
  wire [9:9]\h2c_xdma_wrq_req[0][rid] ;
  wire [110:0]p_0_in1_in;
  wire p_15_in;
  wire [91:0]payloadmuxed_1;
  wire user_clk;
  wire wcp_vlderr_401;
  wire wrq_rcp_dat_err_302;
  wire wrq_stall_302;
  wire wrq_vld_302;
  wire wrq_vld_303;
  wire [0:0]wrq_vld_303_i_2__0_0;
  wire wrq_vld_303_i_2__0_n_0;
  wire wrq_vld_303_i_3_n_0;
  wire wrq_vld_303_reg;
  wire [1:0]NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOC_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair597" *) 
  LUT4 #(
    .INIT(16'h1EE1)) 
    \FifoCntrRd[0]_i_1__15 
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(wrq_vld_303),
        .I3(FifoCntrRd[0]),
        .O(\FifoCntrRd[0]_i_1__15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair597" *) 
  LUT5 #(
    .INIT(32'h1FFEE001)) 
    \FifoCntrRd[1]_i_1__15 
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(FifoCntrRd[0]),
        .I3(wrq_vld_303),
        .I4(FifoCntrRd[1]),
        .O(\FifoCntrRd[1]_i_1__15_n_0 ));
  LUT6 #(
    .INIT(64'h1FFFFFFEE0000001)) 
    \FifoCntrRd[2]_i_2__10 
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(FifoCntrRd[0]),
        .I3(FifoCntrRd[1]),
        .I4(wrq_vld_303),
        .I5(FifoCntrRd[2]),
        .O(\FifoCntrRd[2]_i_2__10_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[0]_i_1__15_n_0 ),
        .Q(FifoCntrRd[0]),
        .R(full_ff_reg_0));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[1]_i_1__15_n_0 ),
        .Q(FifoCntrRd[1]),
        .R(full_ff_reg_0));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[2]_i_2__10_n_0 ),
        .Q(FifoCntrRd[2]),
        .R(full_ff_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair598" *) 
  LUT4 #(
    .INIT(16'h1EE1)) 
    \FifoCntrWr[0]_i_1__17 
       (.I0(empty_ff_reg_0),
        .I1(\Head_reg[0]_0 ),
        .I2(wrq_vld_303),
        .I3(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair598" *) 
  LUT5 #(
    .INIT(32'h1FFEE001)) 
    \FifoCntrWr[1]_i_1__17 
       (.I0(empty_ff_reg_0),
        .I1(\Head_reg[0]_0 ),
        .I2(FifoCntrWr[0]),
        .I3(wrq_vld_303),
        .I4(FifoCntrWr[1]),
        .O(\FifoCntrWr[1]_i_1__17_n_0 ));
  LUT6 #(
    .INIT(64'h1FFFFFFEE0000001)) 
    \FifoCntrWr[2]_i_1__16 
       (.I0(empty_ff_reg_0),
        .I1(\Head_reg[0]_0 ),
        .I2(FifoCntrWr[0]),
        .I3(FifoCntrWr[1]),
        .I4(wrq_vld_303),
        .I5(FifoCntrWr[2]),
        .O(\FifoCntrWr[2]_i_1__16_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[0]_i_1__17_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(full_ff_reg_0));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[1]_i_1__17_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(full_ff_reg_0));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[2]_i_1__16_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(full_ff_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair607" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[0]_i_1__2 
       (.I0(DataIn[0]),
        .I1(Head0[0]),
        .I2(Head1),
        .O(p_0_in1_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair620" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[100]_i_1__4 
       (.I0(DataIn[74]),
        .I1(Head0[100]),
        .I2(Head1),
        .O(p_0_in1_in[100]));
  (* SOFT_HLUTNM = "soft_lutpair643" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[101]_i_1__4 
       (.I0(DataIn[75]),
        .I1(Head0[101]),
        .I2(Head1),
        .O(p_0_in1_in[101]));
  (* SOFT_HLUTNM = "soft_lutpair614" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[102]_i_1__4 
       (.I0(DataIn[76]),
        .I1(Head0[102]),
        .I2(Head1),
        .O(p_0_in1_in[102]));
  (* SOFT_HLUTNM = "soft_lutpair644" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[103]_i_1__4 
       (.I0(DataIn[77]),
        .I1(Head0[103]),
        .I2(Head1),
        .O(p_0_in1_in[103]));
  (* SOFT_HLUTNM = "soft_lutpair606" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[104]_i_1__4 
       (.I0(DataIn[78]),
        .I1(Head0[104]),
        .I2(Head1),
        .O(p_0_in1_in[104]));
  (* SOFT_HLUTNM = "soft_lutpair629" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[105]_i_1__4 
       (.I0(DataIn[79]),
        .I1(Head0[105]),
        .I2(Head1),
        .O(p_0_in1_in[105]));
  (* SOFT_HLUTNM = "soft_lutpair621" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[106]_i_1__4 
       (.I0(DataIn[80]),
        .I1(Head0[106]),
        .I2(Head1),
        .O(p_0_in1_in[106]));
  (* SOFT_HLUTNM = "soft_lutpair644" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[107]_i_1__4 
       (.I0(DataIn[81]),
        .I1(Head0[107]),
        .I2(Head1),
        .O(p_0_in1_in[107]));
  (* SOFT_HLUTNM = "soft_lutpair606" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[108]_i_1__4 
       (.I0(\Head_reg[110]_1 [1]),
        .I1(Head0[108]),
        .I2(Head1),
        .O(p_0_in1_in[108]));
  (* SOFT_HLUTNM = "soft_lutpair629" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[109]_i_1__4 
       (.I0(\Head_reg[110]_1 [2]),
        .I1(Head0[109]),
        .I2(Head1),
        .O(p_0_in1_in[109]));
  (* SOFT_HLUTNM = "soft_lutpair599" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[10]_i_1__3 
       (.I0(\Head_reg[10]_0 [1]),
        .I1(Head0[10]),
        .I2(Head1),
        .O(p_0_in1_in[10]));
  (* SOFT_HLUTNM = "soft_lutpair621" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[110]_i_1__4 
       (.I0(\Head_reg[110]_1 [3]),
        .I1(Head0[110]),
        .I2(Head1),
        .O(p_0_in1_in[110]));
  LUT6 #(
    .INIT(64'hF1F1F1F1F1F1F1FF)) 
    \Head[111]_i_1__8 
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(Head1),
        .I3(FifoCntrRd[2]),
        .I4(FifoCntrRd[1]),
        .I5(FifoCntrRd[0]),
        .O(\Head[111]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair630" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[111]_i_2__0 
       (.I0(Head0[111]),
        .I1(Head1),
        .O(\Head[111]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair622" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[11]_i_1__3 
       (.I0(DataIn[6]),
        .I1(Head0[11]),
        .I2(Head1),
        .O(p_0_in1_in[11]));
  (* SOFT_HLUTNM = "soft_lutpair608" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[12]_i_1__3 
       (.I0(DataIn[7]),
        .I1(Head0[12]),
        .I2(Head1),
        .O(p_0_in1_in[12]));
  (* SOFT_HLUTNM = "soft_lutpair632" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[13]_i_1__3 
       (.I0(DataIn[8]),
        .I1(Head0[13]),
        .I2(Head1),
        .O(p_0_in1_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair600" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[14]_i_1__3 
       (.I0(DataIn[9]),
        .I1(Head0[14]),
        .I2(Head1),
        .O(p_0_in1_in[14]));
  (* SOFT_HLUTNM = "soft_lutpair623" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[15]_i_1__3 
       (.I0(DataIn[10]),
        .I1(Head0[15]),
        .I2(Head1),
        .O(p_0_in1_in[15]));
  (* SOFT_HLUTNM = "soft_lutpair615" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[16]_i_1__2 
       (.I0(DataIn[11]),
        .I1(Head0[16]),
        .I2(Head1),
        .O(p_0_in1_in[16]));
  (* SOFT_HLUTNM = "soft_lutpair632" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[17]_i_1__2 
       (.I0(DataIn[12]),
        .I1(Head0[17]),
        .I2(Head1),
        .O(p_0_in1_in[17]));
  (* SOFT_HLUTNM = "soft_lutpair609" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[18]_i_1__3 
       (.I0(DataIn[13]),
        .I1(Head0[18]),
        .I2(Head1),
        .O(p_0_in1_in[18]));
  (* SOFT_HLUTNM = "soft_lutpair633" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[19]_i_1__3 
       (.I0(DataIn[14]),
        .I1(Head0[19]),
        .I2(Head1),
        .O(p_0_in1_in[19]));
  (* SOFT_HLUTNM = "soft_lutpair630" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[1]_i_1__2 
       (.I0(DataIn[1]),
        .I1(Head0[1]),
        .I2(Head1),
        .O(p_0_in1_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair600" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[20]_i_1__4 
       (.I0(DataIn[15]),
        .I1(Head0[20]),
        .I2(Head1),
        .O(p_0_in1_in[20]));
  (* SOFT_HLUTNM = "soft_lutpair623" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[21]_i_1__4 
       (.I0(DataIn[16]),
        .I1(Head0[21]),
        .I2(Head1),
        .O(p_0_in1_in[21]));
  (* SOFT_HLUTNM = "soft_lutpair599" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[2]_i_1__0 
       (.I0(DataIn[2]),
        .I1(Head0[2]),
        .I2(Head1),
        .O(p_0_in1_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair608" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[36]_i_1__2 
       (.I0(Head0[36]),
        .I1(Head1),
        .O(\Head[36]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair633" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[37]_i_1__2 
       (.I0(DataIn[17]),
        .I1(Head0[37]),
        .I2(Head1),
        .O(p_0_in1_in[37]));
  (* SOFT_HLUTNM = "soft_lutpair601" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[38]_i_1__2 
       (.I0(DataIn[18]),
        .I1(Head0[38]),
        .I2(Head1),
        .O(p_0_in1_in[38]));
  (* SOFT_HLUTNM = "soft_lutpair624" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[39]_i_1__2 
       (.I0(DataIn[19]),
        .I1(Head0[39]),
        .I2(Head1),
        .O(p_0_in1_in[39]));
  (* SOFT_HLUTNM = "soft_lutpair622" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[3]_i_1__2 
       (.I0(DataIn[3]),
        .I1(Head0[3]),
        .I2(Head1),
        .O(p_0_in1_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair616" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[40]_i_1__2 
       (.I0(DataIn[20]),
        .I1(Head0[40]),
        .I2(Head1),
        .O(p_0_in1_in[40]));
  (* SOFT_HLUTNM = "soft_lutpair634" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[41]_i_1__1 
       (.I0(DataIn[21]),
        .I1(Head0[41]),
        .I2(Head1),
        .O(p_0_in1_in[41]));
  (* SOFT_HLUTNM = "soft_lutpair609" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[46]_i_1__4 
       (.I0(Head0[46]),
        .I1(Head1),
        .O(\Head[46]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair634" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[47]_i_1__2 
       (.I0(\Head_reg[110]_1 [0]),
        .I1(Head0[47]),
        .I2(Head1),
        .O(p_0_in1_in[47]));
  (* SOFT_HLUTNM = "soft_lutpair610" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[48]_i_1__2 
       (.I0(DataIn[22]),
        .I1(Head0[48]),
        .I2(Head1),
        .O(p_0_in1_in[48]));
  (* SOFT_HLUTNM = "soft_lutpair635" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[49]_i_1__2 
       (.I0(DataIn[23]),
        .I1(Head0[49]),
        .I2(Head1),
        .O(p_0_in1_in[49]));
  (* SOFT_HLUTNM = "soft_lutpair615" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[4]_i_1__2 
       (.I0(DataIn[4]),
        .I1(Head0[4]),
        .I2(Head1),
        .O(p_0_in1_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair601" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[50]_i_1__2 
       (.I0(DataIn[24]),
        .I1(Head0[50]),
        .I2(Head1),
        .O(p_0_in1_in[50]));
  (* SOFT_HLUTNM = "soft_lutpair624" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[51]_i_1__2 
       (.I0(DataIn[25]),
        .I1(Head0[51]),
        .I2(Head1),
        .O(p_0_in1_in[51]));
  (* SOFT_HLUTNM = "soft_lutpair616" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[52]_i_1__2 
       (.I0(DataIn[26]),
        .I1(Head0[52]),
        .I2(Head1),
        .O(p_0_in1_in[52]));
  (* SOFT_HLUTNM = "soft_lutpair635" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[53]_i_1__2 
       (.I0(DataIn[27]),
        .I1(Head0[53]),
        .I2(Head1),
        .O(p_0_in1_in[53]));
  (* SOFT_HLUTNM = "soft_lutpair610" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[54]_i_1__2 
       (.I0(DataIn[28]),
        .I1(Head0[54]),
        .I2(Head1),
        .O(p_0_in1_in[54]));
  (* SOFT_HLUTNM = "soft_lutpair636" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[55]_i_1__2 
       (.I0(DataIn[29]),
        .I1(Head0[55]),
        .I2(Head1),
        .O(p_0_in1_in[55]));
  (* SOFT_HLUTNM = "soft_lutpair602" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[56]_i_1__3 
       (.I0(DataIn[30]),
        .I1(Head0[56]),
        .I2(Head1),
        .O(p_0_in1_in[56]));
  (* SOFT_HLUTNM = "soft_lutpair625" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[57]_i_1__3 
       (.I0(DataIn[31]),
        .I1(Head0[57]),
        .I2(Head1),
        .O(p_0_in1_in[57]));
  (* SOFT_HLUTNM = "soft_lutpair617" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[58]_i_1__3 
       (.I0(DataIn[32]),
        .I1(Head0[58]),
        .I2(Head1),
        .O(p_0_in1_in[58]));
  (* SOFT_HLUTNM = "soft_lutpair636" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[59]_i_1__3 
       (.I0(DataIn[33]),
        .I1(Head0[59]),
        .I2(Head1),
        .O(p_0_in1_in[59]));
  (* SOFT_HLUTNM = "soft_lutpair631" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[5]_i_1__2 
       (.I0(DataIn[5]),
        .I1(Head0[5]),
        .I2(Head1),
        .O(p_0_in1_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair611" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[60]_i_1__3 
       (.I0(DataIn[34]),
        .I1(Head0[60]),
        .I2(Head1),
        .O(p_0_in1_in[60]));
  (* SOFT_HLUTNM = "soft_lutpair637" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[61]_i_1__4 
       (.I0(DataIn[35]),
        .I1(Head0[61]),
        .I2(Head1),
        .O(p_0_in1_in[61]));
  (* SOFT_HLUTNM = "soft_lutpair602" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[62]_i_1__4 
       (.I0(DataIn[36]),
        .I1(Head0[62]),
        .I2(Head1),
        .O(p_0_in1_in[62]));
  (* SOFT_HLUTNM = "soft_lutpair625" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[63]_i_1__4 
       (.I0(DataIn[37]),
        .I1(Head0[63]),
        .I2(Head1),
        .O(p_0_in1_in[63]));
  (* SOFT_HLUTNM = "soft_lutpair617" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[64]_i_1__4 
       (.I0(DataIn[38]),
        .I1(Head0[64]),
        .I2(Head1),
        .O(p_0_in1_in[64]));
  (* SOFT_HLUTNM = "soft_lutpair637" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[65]_i_1__4 
       (.I0(DataIn[39]),
        .I1(Head0[65]),
        .I2(Head1),
        .O(p_0_in1_in[65]));
  (* SOFT_HLUTNM = "soft_lutpair611" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[66]_i_1__4 
       (.I0(DataIn[40]),
        .I1(Head0[66]),
        .I2(Head1),
        .O(p_0_in1_in[66]));
  (* SOFT_HLUTNM = "soft_lutpair638" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[67]_i_1__4 
       (.I0(DataIn[41]),
        .I1(Head0[67]),
        .I2(Head1),
        .O(p_0_in1_in[67]));
  (* SOFT_HLUTNM = "soft_lutpair603" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[68]_i_1__4 
       (.I0(DataIn[42]),
        .I1(Head0[68]),
        .I2(Head1),
        .O(p_0_in1_in[68]));
  (* SOFT_HLUTNM = "soft_lutpair626" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[69]_i_1__4 
       (.I0(DataIn[43]),
        .I1(Head0[69]),
        .I2(Head1),
        .O(p_0_in1_in[69]));
  (* SOFT_HLUTNM = "soft_lutpair618" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[70]_i_1__4 
       (.I0(DataIn[44]),
        .I1(Head0[70]),
        .I2(Head1),
        .O(p_0_in1_in[70]));
  (* SOFT_HLUTNM = "soft_lutpair638" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[71]_i_1__4 
       (.I0(DataIn[45]),
        .I1(Head0[71]),
        .I2(Head1),
        .O(p_0_in1_in[71]));
  (* SOFT_HLUTNM = "soft_lutpair612" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[72]_i_1__4 
       (.I0(DataIn[46]),
        .I1(Head0[72]),
        .I2(Head1),
        .O(p_0_in1_in[72]));
  (* SOFT_HLUTNM = "soft_lutpair639" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[73]_i_1__4 
       (.I0(DataIn[47]),
        .I1(Head0[73]),
        .I2(Head1),
        .O(p_0_in1_in[73]));
  (* SOFT_HLUTNM = "soft_lutpair603" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[74]_i_1__4 
       (.I0(DataIn[48]),
        .I1(Head0[74]),
        .I2(Head1),
        .O(p_0_in1_in[74]));
  (* SOFT_HLUTNM = "soft_lutpair626" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[75]_i_1__4 
       (.I0(DataIn[49]),
        .I1(Head0[75]),
        .I2(Head1),
        .O(p_0_in1_in[75]));
  (* SOFT_HLUTNM = "soft_lutpair618" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[76]_i_1__4 
       (.I0(DataIn[50]),
        .I1(Head0[76]),
        .I2(Head1),
        .O(p_0_in1_in[76]));
  (* SOFT_HLUTNM = "soft_lutpair639" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[77]_i_1__4 
       (.I0(DataIn[51]),
        .I1(Head0[77]),
        .I2(Head1),
        .O(p_0_in1_in[77]));
  (* SOFT_HLUTNM = "soft_lutpair612" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[78]_i_1__4 
       (.I0(DataIn[52]),
        .I1(Head0[78]),
        .I2(Head1),
        .O(p_0_in1_in[78]));
  (* SOFT_HLUTNM = "soft_lutpair640" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[79]_i_1__4 
       (.I0(DataIn[53]),
        .I1(Head0[79]),
        .I2(Head1),
        .O(p_0_in1_in[79]));
  (* SOFT_HLUTNM = "soft_lutpair604" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[80]_i_1__4 
       (.I0(DataIn[54]),
        .I1(Head0[80]),
        .I2(Head1),
        .O(p_0_in1_in[80]));
  (* SOFT_HLUTNM = "soft_lutpair627" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[81]_i_1__4 
       (.I0(DataIn[55]),
        .I1(Head0[81]),
        .I2(Head1),
        .O(p_0_in1_in[81]));
  (* SOFT_HLUTNM = "soft_lutpair619" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[82]_i_1__4 
       (.I0(DataIn[56]),
        .I1(Head0[82]),
        .I2(Head1),
        .O(p_0_in1_in[82]));
  (* SOFT_HLUTNM = "soft_lutpair640" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[83]_i_1__4 
       (.I0(DataIn[57]),
        .I1(Head0[83]),
        .I2(Head1),
        .O(p_0_in1_in[83]));
  (* SOFT_HLUTNM = "soft_lutpair613" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[84]_i_1__4 
       (.I0(DataIn[58]),
        .I1(Head0[84]),
        .I2(Head1),
        .O(p_0_in1_in[84]));
  (* SOFT_HLUTNM = "soft_lutpair641" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[85]_i_1__4 
       (.I0(DataIn[59]),
        .I1(Head0[85]),
        .I2(Head1),
        .O(p_0_in1_in[85]));
  (* SOFT_HLUTNM = "soft_lutpair604" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[86]_i_1__4 
       (.I0(DataIn[60]),
        .I1(Head0[86]),
        .I2(Head1),
        .O(p_0_in1_in[86]));
  (* SOFT_HLUTNM = "soft_lutpair627" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[87]_i_1__4 
       (.I0(DataIn[61]),
        .I1(Head0[87]),
        .I2(Head1),
        .O(p_0_in1_in[87]));
  (* SOFT_HLUTNM = "soft_lutpair619" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[88]_i_1__4 
       (.I0(DataIn[62]),
        .I1(Head0[88]),
        .I2(Head1),
        .O(p_0_in1_in[88]));
  (* SOFT_HLUTNM = "soft_lutpair641" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[89]_i_1__4 
       (.I0(DataIn[63]),
        .I1(Head0[89]),
        .I2(Head1),
        .O(p_0_in1_in[89]));
  (* SOFT_HLUTNM = "soft_lutpair607" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Head[8]_i_1__4 
       (.I0(Head0[8]),
        .I1(Head1),
        .O(\Head[8]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair613" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[90]_i_1__4 
       (.I0(DataIn[64]),
        .I1(Head0[90]),
        .I2(Head1),
        .O(p_0_in1_in[90]));
  (* SOFT_HLUTNM = "soft_lutpair642" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[91]_i_1__4 
       (.I0(DataIn[65]),
        .I1(Head0[91]),
        .I2(Head1),
        .O(p_0_in1_in[91]));
  (* SOFT_HLUTNM = "soft_lutpair605" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[92]_i_1__4 
       (.I0(DataIn[66]),
        .I1(Head0[92]),
        .I2(Head1),
        .O(p_0_in1_in[92]));
  (* SOFT_HLUTNM = "soft_lutpair628" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[93]_i_1__4 
       (.I0(DataIn[67]),
        .I1(Head0[93]),
        .I2(Head1),
        .O(p_0_in1_in[93]));
  (* SOFT_HLUTNM = "soft_lutpair620" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[94]_i_1__4 
       (.I0(DataIn[68]),
        .I1(Head0[94]),
        .I2(Head1),
        .O(p_0_in1_in[94]));
  (* SOFT_HLUTNM = "soft_lutpair642" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[95]_i_1__4 
       (.I0(DataIn[69]),
        .I1(Head0[95]),
        .I2(Head1),
        .O(p_0_in1_in[95]));
  (* SOFT_HLUTNM = "soft_lutpair614" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[96]_i_1__4 
       (.I0(DataIn[70]),
        .I1(Head0[96]),
        .I2(Head1),
        .O(p_0_in1_in[96]));
  (* SOFT_HLUTNM = "soft_lutpair643" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[97]_i_1__4 
       (.I0(DataIn[71]),
        .I1(Head0[97]),
        .I2(Head1),
        .O(p_0_in1_in[97]));
  (* SOFT_HLUTNM = "soft_lutpair605" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[98]_i_1__4 
       (.I0(DataIn[72]),
        .I1(Head0[98]),
        .I2(Head1),
        .O(p_0_in1_in[98]));
  (* SOFT_HLUTNM = "soft_lutpair628" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[99]_i_1__4 
       (.I0(DataIn[73]),
        .I1(Head0[99]),
        .I2(Head1),
        .O(p_0_in1_in[99]));
  (* SOFT_HLUTNM = "soft_lutpair631" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \Head[9]_i_1__3 
       (.I0(\Head_reg[10]_0 [0]),
        .I1(Head0[9]),
        .I2(Head1),
        .O(p_0_in1_in[9]));
  FDRE \Head_reg[0] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[0]),
        .Q(\Head_reg[110]_0 [0]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[100] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[100]),
        .Q(\Head_reg[110]_0 [76]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[101] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[101]),
        .Q(\Head_reg[110]_0 [77]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[102] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[102]),
        .Q(\Head_reg[110]_0 [78]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[103] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[103]),
        .Q(\Head_reg[110]_0 [79]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[104] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[104]),
        .Q(\Head_reg[110]_0 [80]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[105] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[105]),
        .Q(\Head_reg[110]_0 [81]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[106] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[106]),
        .Q(\Head_reg[110]_0 [82]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[107] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[107]),
        .Q(\Head_reg[110]_0 [83]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[108] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[108]),
        .Q(\Head_reg[110]_0 [84]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[109] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[109]),
        .Q(\Head_reg[110]_0 [85]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[10] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[10]),
        .Q(\Head_reg[110]_0 [6]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[110] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[110]),
        .Q(\Head_reg[110]_0 [86]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[111] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(\Head[111]_i_2__0_n_0 ),
        .Q(\h2c_xdma_wrq_req[0][err] ),
        .R(full_ff_reg_0));
  FDRE \Head_reg[11] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[11]),
        .Q(\Head_reg[110]_0 [7]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[12] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[12]),
        .Q(\Head_reg[110]_0 [8]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[13] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[13]),
        .Q(\Head_reg[110]_0 [9]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[14] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[14]),
        .Q(\Head_reg[110]_0 [10]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[15] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[15]),
        .Q(\Head_reg[110]_0 [11]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[16] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[16]),
        .Q(\Head_reg[110]_0 [12]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[17] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[17]),
        .Q(\Head_reg[110]_0 [13]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[18] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[18]),
        .Q(\Head_reg[110]_0 [14]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[19] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[19]),
        .Q(\Head_reg[110]_0 [15]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[1] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[1]),
        .Q(\h2c_xdma_wrq_req[0][eod] ),
        .R(full_ff_reg_0));
  FDRE \Head_reg[20] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[20]),
        .Q(\Head_reg[110]_0 [16]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[21] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[21]),
        .Q(\Head_reg[110]_0 [17]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[2] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[2]),
        .Q(\h2c_xdma_wrq_req[0][eop] ),
        .R(full_ff_reg_0));
  FDRE \Head_reg[36] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(\Head[36]_i_1__2_n_0 ),
        .Q(\h2c_xdma_wrq_req[0][byte_len] ),
        .R(full_ff_reg_0));
  FDRE \Head_reg[37] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[37]),
        .Q(\Head_reg[110]_0 [18]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[38] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[38]),
        .Q(\Head_reg[110]_0 [19]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[39] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[39]),
        .Q(\Head_reg[110]_0 [20]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[3] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[3]),
        .Q(\Head_reg[110]_0 [1]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[40] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[40]),
        .Q(\Head_reg[110]_0 [21]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[41] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[41]),
        .Q(\Head_reg[110]_0 [22]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[46] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(\Head[46]_i_1__4_n_0 ),
        .Q(\h2c_xdma_wrq_req[0][rid] ),
        .R(full_ff_reg_0));
  FDRE \Head_reg[47] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[47]),
        .Q(\Head_reg[110]_0 [23]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[48] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[48]),
        .Q(\Head_reg[110]_0 [24]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[49] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[49]),
        .Q(\Head_reg[110]_0 [25]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[4] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[4]),
        .Q(\Head_reg[110]_0 [2]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[50] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[50]),
        .Q(\Head_reg[110]_0 [26]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[51] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[51]),
        .Q(\Head_reg[110]_0 [27]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[52] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[52]),
        .Q(\Head_reg[110]_0 [28]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[53] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[53]),
        .Q(\Head_reg[110]_0 [29]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[54] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[54]),
        .Q(\Head_reg[110]_0 [30]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[55] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[55]),
        .Q(\Head_reg[110]_0 [31]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[56] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[56]),
        .Q(\Head_reg[110]_0 [32]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[57] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[57]),
        .Q(\Head_reg[110]_0 [33]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[58] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[58]),
        .Q(\Head_reg[110]_0 [34]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[59] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[59]),
        .Q(\Head_reg[110]_0 [35]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[5] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[5]),
        .Q(\Head_reg[110]_0 [3]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[60] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[60]),
        .Q(\Head_reg[110]_0 [36]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[61] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[61]),
        .Q(\Head_reg[110]_0 [37]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[62] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[62]),
        .Q(\Head_reg[110]_0 [38]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[63] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[63]),
        .Q(\Head_reg[110]_0 [39]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[64] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[64]),
        .Q(\Head_reg[110]_0 [40]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[65] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[65]),
        .Q(\Head_reg[110]_0 [41]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[66] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[66]),
        .Q(\Head_reg[110]_0 [42]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[67] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[67]),
        .Q(\Head_reg[110]_0 [43]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[68] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[68]),
        .Q(\Head_reg[110]_0 [44]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[69] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[69]),
        .Q(\Head_reg[110]_0 [45]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[70] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[70]),
        .Q(\Head_reg[110]_0 [46]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[71] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[71]),
        .Q(\Head_reg[110]_0 [47]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[72] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[72]),
        .Q(\Head_reg[110]_0 [48]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[73] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[73]),
        .Q(\Head_reg[110]_0 [49]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[74] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[74]),
        .Q(\Head_reg[110]_0 [50]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[75] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[75]),
        .Q(\Head_reg[110]_0 [51]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[76] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[76]),
        .Q(\Head_reg[110]_0 [52]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[77] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[77]),
        .Q(\Head_reg[110]_0 [53]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[78] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[78]),
        .Q(\Head_reg[110]_0 [54]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[79] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[79]),
        .Q(\Head_reg[110]_0 [55]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[80] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[80]),
        .Q(\Head_reg[110]_0 [56]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[81] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[81]),
        .Q(\Head_reg[110]_0 [57]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[82] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[82]),
        .Q(\Head_reg[110]_0 [58]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[83] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[83]),
        .Q(\Head_reg[110]_0 [59]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[84] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[84]),
        .Q(\Head_reg[110]_0 [60]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[85] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[85]),
        .Q(\Head_reg[110]_0 [61]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[86] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[86]),
        .Q(\Head_reg[110]_0 [62]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[87] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[87]),
        .Q(\Head_reg[110]_0 [63]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[88] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[88]),
        .Q(\Head_reg[110]_0 [64]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[89] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[89]),
        .Q(\Head_reg[110]_0 [65]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[8] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(\Head[8]_i_1__4_n_0 ),
        .Q(\Head_reg[110]_0 [4]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[90] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[90]),
        .Q(\Head_reg[110]_0 [66]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[91] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[91]),
        .Q(\Head_reg[110]_0 [67]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[92] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[92]),
        .Q(\Head_reg[110]_0 [68]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[93] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[93]),
        .Q(\Head_reg[110]_0 [69]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[94] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[94]),
        .Q(\Head_reg[110]_0 [70]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[95] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[95]),
        .Q(\Head_reg[110]_0 [71]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[96] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[96]),
        .Q(\Head_reg[110]_0 [72]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[97] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[97]),
        .Q(\Head_reg[110]_0 [73]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[98] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[98]),
        .Q(\Head_reg[110]_0 [74]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[99] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[99]),
        .Q(\Head_reg[110]_0 [75]),
        .R(full_ff_reg_0));
  FDRE \Head_reg[9] 
       (.C(user_clk),
        .CE(\Head[111]_i_1__8_n_0 ),
        .D(p_0_in1_in[9]),
        .Q(\Head_reg[110]_0 [5]),
        .R(full_ff_reg_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_3_0_5
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[1:0]),
        .DIB(DataIn[3:2]),
        .DIC(DataIn[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[1:0]),
        .DOB(Head0[3:2]),
        .DOC(Head0[5:4]),
        .DOD(NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT2 #(
    .INIT(4'h1)) 
    MemArray_reg_0_3_0_5_i_1__4
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .O(p_15_in));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_0_5_i_2__3
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\h2c_xdma_wrq_req[0][eod] ),
        .O(payloadmuxed_1[1]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_0_5_i_3__3
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [0]),
        .O(payloadmuxed_1[0]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_0_5_i_4__3
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [1]),
        .O(payloadmuxed_1[3]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_0_5_i_5__3
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\h2c_xdma_wrq_req[0][eop] ),
        .O(payloadmuxed_1[2]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_0_5_i_6__3
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [3]),
        .O(payloadmuxed_1[5]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_0_5_i_7__3
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [2]),
        .O(payloadmuxed_1[4]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_102_107" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "102" *) 
  (* ram_slice_end = "107" *) 
  RAM32M MemArray_reg_0_3_102_107
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[77:76]),
        .DIB(DataIn[79:78]),
        .DIC(DataIn[81:80]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[103:102]),
        .DOB(Head0[105:104]),
        .DOC(Head0[107:106]),
        .DOD(NLW_MemArray_reg_0_3_102_107_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_1__2
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [79]),
        .O(payloadmuxed_1[83]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_2__2
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [78]),
        .O(payloadmuxed_1[82]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_3__2
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [81]),
        .O(payloadmuxed_1[85]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_4__2
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [80]),
        .O(payloadmuxed_1[84]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_5__2
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [83]),
        .O(payloadmuxed_1[87]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_102_107_i_6__2
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [82]),
        .O(payloadmuxed_1[86]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_108_112_i_1__0
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [85]),
        .O(payloadmuxed_1[89]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_108_112_i_2__0
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [84]),
        .O(payloadmuxed_1[88]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_108_112_i_3__0
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\h2c_xdma_wrq_req[0][err] ),
        .O(payloadmuxed_1[91]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_108_112_i_4__0
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [86]),
        .O(payloadmuxed_1[90]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[8:7]),
        .DIB(DataIn[10:9]),
        .DIC(DataIn[12:11]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[13:12]),
        .DOB(Head0[15:14]),
        .DOC(Head0[17:16]),
        .DOD(NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_12_17_i_1__4
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [9]),
        .O(payloadmuxed_1[11]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_12_17_i_2__4
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [8]),
        .O(payloadmuxed_1[10]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_12_17_i_3__4
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [11]),
        .O(payloadmuxed_1[13]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_12_17_i_4__4
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [10]),
        .O(payloadmuxed_1[12]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_12_17_i_5__4
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [13]),
        .O(payloadmuxed_1[15]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_12_17_i_6__4
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [12]),
        .O(payloadmuxed_1[14]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[14:13]),
        .DIB(DataIn[16:15]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[19:18]),
        .DOB(Head0[21:20]),
        .DOC(NLW_MemArray_reg_0_3_18_23_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_18_23_i_1__3
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [15]),
        .O(payloadmuxed_1[17]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_18_23_i_2__3
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [14]),
        .O(payloadmuxed_1[16]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_18_23_i_3__3
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [17]),
        .O(payloadmuxed_1[19]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_18_23_i_4__3
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [16]),
        .O(payloadmuxed_1[18]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_36_41" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M MemArray_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({DataIn[17],1'b0}),
        .DIB(DataIn[19:18]),
        .DIC(DataIn[21:20]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[37:36]),
        .DOB(Head0[39:38]),
        .DOC(Head0[41:40]),
        .DOD(NLW_MemArray_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_36_41_i_1__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [18]),
        .O(payloadmuxed_1[21]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_36_41_i_2__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\h2c_xdma_wrq_req[0][byte_len] ),
        .O(payloadmuxed_1[20]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_36_41_i_3__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [20]),
        .O(payloadmuxed_1[23]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_36_41_i_4__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [19]),
        .O(payloadmuxed_1[22]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_36_41_i_5__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [22]),
        .O(payloadmuxed_1[25]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_36_41_i_6__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [21]),
        .O(payloadmuxed_1[24]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_42_47" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M MemArray_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({\Head_reg[110]_1 [0],1'b0}),
        .DIB(\Head_reg[110]_1 [2:1]),
        .DIC({1'b0,\Head_reg[110]_1 [3]}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[47:46]),
        .DOB(Head0[109:108]),
        .DOC(Head0[111:110]),
        .DOD(NLW_MemArray_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_42_47_i_1__1
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [23]),
        .O(payloadmuxed_1[27]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_42_47_i_2__1
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\h2c_xdma_wrq_req[0][rid] ),
        .O(payloadmuxed_1[26]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_48_53" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M MemArray_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[23:22]),
        .DIB(DataIn[25:24]),
        .DIC(DataIn[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[49:48]),
        .DOB(Head0[51:50]),
        .DOC(Head0[53:52]),
        .DOD(NLW_MemArray_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_48_53_i_1__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [25]),
        .O(payloadmuxed_1[29]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_48_53_i_2__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [24]),
        .O(payloadmuxed_1[28]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_48_53_i_3__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [27]),
        .O(payloadmuxed_1[31]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_48_53_i_4__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [26]),
        .O(payloadmuxed_1[30]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_48_53_i_5__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [29]),
        .O(payloadmuxed_1[33]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_48_53_i_6__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [28]),
        .O(payloadmuxed_1[32]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_54_59" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M MemArray_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[29:28]),
        .DIB(DataIn[31:30]),
        .DIC(DataIn[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[55:54]),
        .DOB(Head0[57:56]),
        .DOC(Head0[59:58]),
        .DOD(NLW_MemArray_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_54_59_i_1__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [31]),
        .O(payloadmuxed_1[35]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_54_59_i_2__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [30]),
        .O(payloadmuxed_1[34]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_54_59_i_3__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [33]),
        .O(payloadmuxed_1[37]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_54_59_i_4__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [32]),
        .O(payloadmuxed_1[36]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_54_59_i_5__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [35]),
        .O(payloadmuxed_1[39]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_54_59_i_6__0
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [34]),
        .O(payloadmuxed_1[38]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_60_65" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M MemArray_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[35:34]),
        .DIB(DataIn[37:36]),
        .DIC(DataIn[39:38]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[61:60]),
        .DOB(Head0[63:62]),
        .DOC(Head0[65:64]),
        .DOD(NLW_MemArray_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_1__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [37]),
        .O(payloadmuxed_1[41]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_2__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [36]),
        .O(payloadmuxed_1[40]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_3__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [39]),
        .O(payloadmuxed_1[43]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_4__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [38]),
        .O(payloadmuxed_1[42]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_5__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [41]),
        .O(payloadmuxed_1[45]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_60_65_i_6__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [40]),
        .O(payloadmuxed_1[44]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_66_71" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M MemArray_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[41:40]),
        .DIB(DataIn[43:42]),
        .DIC(DataIn[45:44]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[67:66]),
        .DOB(Head0[69:68]),
        .DOC(Head0[71:70]),
        .DOD(NLW_MemArray_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_1__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [43]),
        .O(payloadmuxed_1[47]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_2__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [42]),
        .O(payloadmuxed_1[46]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_3__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [45]),
        .O(payloadmuxed_1[49]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_4__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [44]),
        .O(payloadmuxed_1[48]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_5__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [47]),
        .O(payloadmuxed_1[51]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_66_71_i_6__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [46]),
        .O(payloadmuxed_1[50]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA({\Head_reg[10]_0 [0],1'b0}),
        .DIB({DataIn[6],\Head_reg[10]_0 [1]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(Head0[9:8]),
        .DOB(Head0[11:10]),
        .DOC(NLW_MemArray_reg_0_3_6_11_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_6_11_i_1__5
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [5]),
        .O(payloadmuxed_1[7]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_6_11_i_2__4
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [4]),
        .O(payloadmuxed_1[6]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_6_11_i_3__4
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [7]),
        .O(payloadmuxed_1[9]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_6_11_i_4__4
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [6]),
        .O(payloadmuxed_1[8]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_72_77" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M MemArray_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[47:46]),
        .DIB(DataIn[49:48]),
        .DIC(DataIn[51:50]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[73:72]),
        .DOB(Head0[75:74]),
        .DOC(Head0[77:76]),
        .DOD(NLW_MemArray_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_1__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [49]),
        .O(payloadmuxed_1[53]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_2__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [48]),
        .O(payloadmuxed_1[52]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_3__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [51]),
        .O(payloadmuxed_1[55]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_4__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [50]),
        .O(payloadmuxed_1[54]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_5__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [53]),
        .O(payloadmuxed_1[57]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_72_77_i_6__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [52]),
        .O(payloadmuxed_1[56]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_78_83" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "83" *) 
  RAM32M MemArray_reg_0_3_78_83
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[53:52]),
        .DIB(DataIn[55:54]),
        .DIC(DataIn[57:56]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[79:78]),
        .DOB(Head0[81:80]),
        .DOC(Head0[83:82]),
        .DOD(NLW_MemArray_reg_0_3_78_83_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_1__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [55]),
        .O(payloadmuxed_1[59]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_2__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [54]),
        .O(payloadmuxed_1[58]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_3__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [57]),
        .O(payloadmuxed_1[61]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_4__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [56]),
        .O(payloadmuxed_1[60]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_5__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [59]),
        .O(payloadmuxed_1[63]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_78_83_i_6__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [58]),
        .O(payloadmuxed_1[62]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_84_89" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "84" *) 
  (* ram_slice_end = "89" *) 
  RAM32M MemArray_reg_0_3_84_89
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[59:58]),
        .DIB(DataIn[61:60]),
        .DIC(DataIn[63:62]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[85:84]),
        .DOB(Head0[87:86]),
        .DOC(Head0[89:88]),
        .DOD(NLW_MemArray_reg_0_3_84_89_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_1__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [61]),
        .O(payloadmuxed_1[65]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_2__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [60]),
        .O(payloadmuxed_1[64]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_3__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [63]),
        .O(payloadmuxed_1[67]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_4__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [62]),
        .O(payloadmuxed_1[66]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_5__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [65]),
        .O(payloadmuxed_1[69]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_84_89_i_6__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [64]),
        .O(payloadmuxed_1[68]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_90_95" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "90" *) 
  (* ram_slice_end = "95" *) 
  RAM32M MemArray_reg_0_3_90_95
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[65:64]),
        .DIB(DataIn[67:66]),
        .DIC(DataIn[69:68]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[91:90]),
        .DOB(Head0[93:92]),
        .DOC(Head0[95:94]),
        .DOD(NLW_MemArray_reg_0_3_90_95_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_1__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [67]),
        .O(payloadmuxed_1[71]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_2__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [66]),
        .O(payloadmuxed_1[70]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_3__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [69]),
        .O(payloadmuxed_1[73]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_4__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [68]),
        .O(payloadmuxed_1[72]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_5__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [71]),
        .O(payloadmuxed_1[75]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_90_95_i_6__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [70]),
        .O(payloadmuxed_1[74]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "448" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_3_96_101" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "96" *) 
  (* ram_slice_end = "101" *) 
  RAM32M MemArray_reg_0_3_96_101
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[71:70]),
        .DIB(DataIn[73:72]),
        .DIC(DataIn[75:74]),
        .DID({1'b0,1'b0}),
        .DOA(Head0[97:96]),
        .DOB(Head0[99:98]),
        .DOC(Head0[101:100]),
        .DOD(NLW_MemArray_reg_0_3_96_101_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wrq_vld_303));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_1__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [73]),
        .O(payloadmuxed_1[77]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_2__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [72]),
        .O(payloadmuxed_1[76]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_3__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [75]),
        .O(payloadmuxed_1[79]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_4__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [74]),
        .O(payloadmuxed_1[78]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_5__2
       (.I0(empty_ff_reg_rep__0_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [77]),
        .O(payloadmuxed_1[81]));
  LUT3 #(
    .INIT(8'h10)) 
    MemArray_reg_0_3_96_101_i_6__2
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(\Head_reg[110]_0 [76]),
        .O(payloadmuxed_1[80]));
  LUT6 #(
    .INIT(64'h0F0F0F0FE1E1E1F0)) 
    \RdPtr[0]_i_1__17 
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(RdPtr[0]),
        .I3(FifoCntrRd[2]),
        .I4(FifoCntrRd[1]),
        .I5(Head1),
        .O(RdPtr__0[0]));
  LUT6 #(
    .INIT(64'h55577777AAA88888)) 
    \RdPtr[1]_i_1__4 
       (.I0(RdPtr[0]),
        .I1(Head1),
        .I2(FifoCntrRd[1]),
        .I3(FifoCntrRd[2]),
        .I4(\RdPtr[1]_i_3__1_n_0 ),
        .I5(RdPtr[1]),
        .O(RdPtr__0[1]));
  LUT6 #(
    .INIT(64'h0000001F00000000)) 
    \RdPtr[1]_i_2__9 
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(FifoCntrRd[0]),
        .I3(FifoCntrRd[2]),
        .I4(FifoCntrRd[1]),
        .I5(wrq_vld_303),
        .O(Head1));
  LUT2 #(
    .INIT(4'h1)) 
    \RdPtr[1]_i_3__1 
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .O(\RdPtr[1]_i_3__1_n_0 ));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[0]),
        .Q(RdPtr[0]),
        .R(full_ff_reg_0));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(RdPtr[1]),
        .R(full_ff_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair645" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \WrPtr[0]_i_1__4 
       (.I0(WrPtr[0]),
        .I1(wrq_vld_303),
        .O(WrPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair645" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \WrPtr[1]_i_1__4 
       (.I0(WrPtr[0]),
        .I1(wrq_vld_303),
        .I2(WrPtr[1]),
        .O(WrPtr__0[1]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[0]),
        .Q(WrPtr[0]),
        .R(full_ff_reg_0));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[1]),
        .Q(WrPtr[1]),
        .R(full_ff_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0100)) 
    empty_ff_i_1__4
       (.I0(FifoCntrRd[1]),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[2]),
        .I3(empty_ff_reg_0),
        .I4(empty_ff_i_2__9_n_0),
        .I5(empty_ff_reg_1),
        .O(empty_ff_i_1__4_n_0));
  LUT6 #(
    .INIT(64'hF0F0F0F1F0F0F0FF)) 
    empty_ff_i_2__9
       (.I0(empty_ff_reg_rep_0),
        .I1(\Head_reg[0]_0 ),
        .I2(cfg_linkdown_nn1),
        .I3(FifoCntrRd[2]),
        .I4(FifoCntrRd[1]),
        .I5(FifoCntrRd[0]),
        .O(empty_ff_i_2__9_n_0));
  (* ORIG_CELL_NAME = "empty_ff_reg" *) 
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__4_n_0),
        .Q(empty_ff_reg_0),
        .R(1'b0));
  (* ORIG_CELL_NAME = "empty_ff_reg" *) 
  FDRE empty_ff_reg_rep
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_rep_i_1_n_0),
        .Q(empty_ff_reg_rep_0),
        .R(1'b0));
  (* ORIG_CELL_NAME = "empty_ff_reg" *) 
  FDRE empty_ff_reg_rep__0
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_rep__0_i_1_n_0),
        .Q(empty_ff_reg_rep__0_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0100)) 
    empty_ff_rep__0_i_1
       (.I0(FifoCntrRd[1]),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[2]),
        .I3(empty_ff_reg_0),
        .I4(empty_ff_i_2__9_n_0),
        .I5(empty_ff_reg_1),
        .O(empty_ff_rep__0_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0100)) 
    empty_ff_rep_i_1
       (.I0(FifoCntrRd[1]),
        .I1(FifoCntrRd[0]),
        .I2(FifoCntrRd[2]),
        .I3(empty_ff_reg_0),
        .I4(empty_ff_i_2__9_n_0),
        .I5(empty_ff_reg_1),
        .O(empty_ff_rep_i_1_n_0));
  LUT5 #(
    .INIT(32'hFF801180)) 
    full_ff_i_1__2
       (.I0(FifoCntrWr[0]),
        .I1(FifoCntrWr[1]),
        .I2(wrq_vld_303),
        .I3(FifoCntrWr[2]),
        .I4(full_ff_reg_n_0),
        .O(full_ff_i_1__2_n_0));
  FDRE full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(full_ff_i_1__2_n_0),
        .Q(full_ff_reg_n_0),
        .R(full_ff_reg_0));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    wrq_vld_303_i_1__0
       (.I0(D[0]),
        .I1(D[2]),
        .I2(wrq_vld_303_i_2__0_n_0),
        .I3(D[3]),
        .I4(D[1]),
        .I5(D[4]),
        .O(wrq_vld_302));
  LUT6 #(
    .INIT(64'h00000000FFFFFFF2)) 
    wrq_vld_303_i_2__0
       (.I0(wrq_vld_303_reg),
        .I1(Q[0]),
        .I2(ctl_rst),
        .I3(wcp_vlderr_401),
        .I4(wrq_rcp_dat_err_302),
        .I5(wrq_vld_303_i_3_n_0),
        .O(wrq_vld_303_i_2__0_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF1)) 
    wrq_vld_303_i_3
       (.I0(CO),
        .I1(wrq_vld_303_i_2__0_0),
        .I2(wrq_vld_303),
        .I3(wrq_stall_302),
        .I4(Q[1]),
        .I5(full_ff_reg_n_0),
        .O(wrq_vld_303_i_3_n_0));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFO" *) 
module xdma_0_xdma_v4_1_29_GenericFIFO_48
   (Q,
    data_pop,
    \WrPtr_reg[2]_0 ,
    m_axi_wready,
    m_axi_wvalid_ff,
    \RdPtr_reg[0]_0 ,
    SR,
    user_clk,
    \WrPtr_reg[1]_0 );
  output [2:0]Q;
  output data_pop;
  output [2:0]\WrPtr_reg[2]_0 ;
  input m_axi_wready;
  input m_axi_wvalid_ff;
  input [3:0]\RdPtr_reg[0]_0 ;
  input [0:0]SR;
  input user_clk;
  input \WrPtr_reg[1]_0 ;

  wire [2:0]Q;
  wire [2:0]RdPtr__0;
  wire [3:0]\RdPtr_reg[0]_0 ;
  wire [0:0]SR;
  wire [2:0]WrPtr__0;
  wire \WrPtr_reg[1]_0 ;
  wire [2:0]\WrPtr_reg[2]_0 ;
  wire data_pop;
  wire m_axi_wready;
  wire m_axi_wvalid_ff;
  wire user_clk;

  LUT2 #(
    .INIT(4'h6)) 
    \RdPtr[0]_i_1__16 
       (.I0(Q[0]),
        .I1(data_pop),
        .O(RdPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair390" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \RdPtr[1]_i_1__16 
       (.I0(data_pop),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(RdPtr__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair390" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \RdPtr[2]_i_1__5 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(data_pop),
        .I3(Q[2]),
        .O(RdPtr__0[2]));
  LUT6 #(
    .INIT(64'h8888888888888880)) 
    \RdPtr[2]_i_2__3 
       (.I0(m_axi_wready),
        .I1(m_axi_wvalid_ff),
        .I2(\RdPtr_reg[0]_0 [2]),
        .I3(\RdPtr_reg[0]_0 [3]),
        .I4(\RdPtr_reg[0]_0 [1]),
        .I5(\RdPtr_reg[0]_0 [0]),
        .O(data_pop));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE \RdPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[2]),
        .Q(Q[2]),
        .R(SR));
  LUT2 #(
    .INIT(4'h6)) 
    \WrPtr[0]_i_1 
       (.I0(\WrPtr_reg[2]_0 [0]),
        .I1(\WrPtr_reg[1]_0 ),
        .O(WrPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair391" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \WrPtr[1]_i_1 
       (.I0(\WrPtr_reg[2]_0 [0]),
        .I1(\WrPtr_reg[1]_0 ),
        .I2(\WrPtr_reg[2]_0 [1]),
        .O(WrPtr__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair391" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \WrPtr[2]_i_1 
       (.I0(\WrPtr_reg[1]_0 ),
        .I1(\WrPtr_reg[2]_0 [0]),
        .I2(\WrPtr_reg[2]_0 [1]),
        .I3(\WrPtr_reg[2]_0 [2]),
        .O(WrPtr__0[2]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[0]),
        .Q(\WrPtr_reg[2]_0 [0]),
        .R(SR));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[1]),
        .Q(\WrPtr_reg[2]_0 [1]),
        .R(SR));
  FDRE \WrPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[2]),
        .Q(\WrPtr_reg[2]_0 [2]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFO" *) 
module xdma_0_xdma_v4_1_29_GenericFIFO__parameterized0
   (\WrPtr_reg[0]_0 ,
    wb_dat_fl,
    dat_fifo_vld_102_reg,
    dat_fifo_vld_102_reg_0,
    dat_fifo_vld_102_reg_1,
    dat_fifo_vld_102_reg_2,
    dat_fifo_vld_102_reg_3,
    dat_fifo_vld_102_reg_4,
    dat_fifo_vld_102_reg_5,
    dat_fifo_vld_102_reg_6,
    dat_fifo_vld_102_reg_7,
    dat_fifo_vld_102_reg_8,
    dat_fifo_vld_102_reg_9,
    dat_fifo_vld_102_reg_10,
    dat_fifo_vld_102_reg_11,
    dat_fifo_vld_102_reg_12,
    dat_fifo_vld_102_reg_13,
    dat_fifo_vld_102_reg_14,
    dat_fifo_vld_102_reg_15,
    dat_fifo_vld_102_reg_16,
    dat_fifo_vld_102_reg_17,
    dat_fifo_vld_102_reg_18,
    dat_fifo_vld_102_reg_19,
    dat_fifo_vld_102_reg_20,
    dat_fifo_vld_102_reg_21,
    dat_fifo_vld_102_reg_22,
    dat_fifo_vld_102_reg_23,
    dat_fifo_vld_102_reg_24,
    user_clk,
    Q,
    wb_win_vld,
    O52,
    dat_fifo_vld_102,
    \mi_c2h0_dat\.rdat ,
    wbk_xdma_wpl_vld,
    wpl_ren_ff,
    empty_ff,
    D);
  output [0:0]\WrPtr_reg[0]_0 ;
  output wb_dat_fl;
  output dat_fifo_vld_102_reg;
  output dat_fifo_vld_102_reg_0;
  output dat_fifo_vld_102_reg_1;
  output dat_fifo_vld_102_reg_2;
  output dat_fifo_vld_102_reg_3;
  output dat_fifo_vld_102_reg_4;
  output dat_fifo_vld_102_reg_5;
  output dat_fifo_vld_102_reg_6;
  output dat_fifo_vld_102_reg_7;
  output dat_fifo_vld_102_reg_8;
  output dat_fifo_vld_102_reg_9;
  output dat_fifo_vld_102_reg_10;
  output dat_fifo_vld_102_reg_11;
  output dat_fifo_vld_102_reg_12;
  output dat_fifo_vld_102_reg_13;
  output dat_fifo_vld_102_reg_14;
  output dat_fifo_vld_102_reg_15;
  output dat_fifo_vld_102_reg_16;
  output dat_fifo_vld_102_reg_17;
  output dat_fifo_vld_102_reg_18;
  output dat_fifo_vld_102_reg_19;
  output dat_fifo_vld_102_reg_20;
  output dat_fifo_vld_102_reg_21;
  output dat_fifo_vld_102_reg_22;
  output dat_fifo_vld_102_reg_23;
  output dat_fifo_vld_102_reg_24;
  input user_clk;
  input [25:0]Q;
  input wb_win_vld;
  input O52;
  input dat_fifo_vld_102;
  input [25:0]\mi_c2h0_dat\.rdat ;
  input wbk_xdma_wpl_vld;
  input wpl_ren_ff;
  input empty_ff;
  input [0:0]D;

  wire [0:0]D;
  wire [31:0]DataOut;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1_n_0 ;
  wire \FifoCntrWr[1]_i_1_n_0 ;
  wire \FifoCntrWr[2]_i_1_n_0 ;
  wire O52;
  wire [25:0]Q;
  wire [1:0]RdPtr;
  wire \RdPtr[0]_i_1__13_n_0 ;
  wire \RdPtr[1]_i_1__14_n_0 ;
  wire [1:1]WrPtr;
  wire \WrPtr[1]_i_1__14_n_0 ;
  wire [0:0]\WrPtr_reg[0]_0 ;
  wire dat_fifo_vld_102;
  wire dat_fifo_vld_102_reg;
  wire dat_fifo_vld_102_reg_0;
  wire dat_fifo_vld_102_reg_1;
  wire dat_fifo_vld_102_reg_10;
  wire dat_fifo_vld_102_reg_11;
  wire dat_fifo_vld_102_reg_12;
  wire dat_fifo_vld_102_reg_13;
  wire dat_fifo_vld_102_reg_14;
  wire dat_fifo_vld_102_reg_15;
  wire dat_fifo_vld_102_reg_16;
  wire dat_fifo_vld_102_reg_17;
  wire dat_fifo_vld_102_reg_18;
  wire dat_fifo_vld_102_reg_19;
  wire dat_fifo_vld_102_reg_2;
  wire dat_fifo_vld_102_reg_20;
  wire dat_fifo_vld_102_reg_21;
  wire dat_fifo_vld_102_reg_22;
  wire dat_fifo_vld_102_reg_23;
  wire dat_fifo_vld_102_reg_24;
  wire dat_fifo_vld_102_reg_3;
  wire dat_fifo_vld_102_reg_4;
  wire dat_fifo_vld_102_reg_5;
  wire dat_fifo_vld_102_reg_6;
  wire dat_fifo_vld_102_reg_7;
  wire dat_fifo_vld_102_reg_8;
  wire dat_fifo_vld_102_reg_9;
  wire empty_ff;
  wire [25:0]\mi_c2h0_dat\.rdat ;
  wire user_clk;
  wire wb_dat_fl;
  wire wb_win_vld;
  wire [31:0]\wbk_xdma_wpl_dat[dat] ;
  wire wbk_xdma_wpl_vld;
  wire wpl_ren_ff;
  wire [1:0]NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED;
  wire NLW_MemArray_reg_0_3_30_35_SPO_UNCONNECTED;
  wire NLW_MemArray_reg_0_3_30_35__0_SPO_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED;

  FDRE \DataOut_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[0]),
        .Q(\wbk_xdma_wpl_dat[dat] [0]),
        .R(1'b0));
  FDRE \DataOut_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[10]),
        .Q(\wbk_xdma_wpl_dat[dat] [10]),
        .R(1'b0));
  FDRE \DataOut_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[11]),
        .Q(\wbk_xdma_wpl_dat[dat] [11]),
        .R(1'b0));
  FDRE \DataOut_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[12]),
        .Q(\wbk_xdma_wpl_dat[dat] [12]),
        .R(1'b0));
  FDRE \DataOut_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[13]),
        .Q(\wbk_xdma_wpl_dat[dat] [13]),
        .R(1'b0));
  FDRE \DataOut_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[14]),
        .Q(\wbk_xdma_wpl_dat[dat] [14]),
        .R(1'b0));
  FDRE \DataOut_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[15]),
        .Q(\wbk_xdma_wpl_dat[dat] [15]),
        .R(1'b0));
  FDRE \DataOut_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[16]),
        .Q(\wbk_xdma_wpl_dat[dat] [16]),
        .R(1'b0));
  FDRE \DataOut_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[17]),
        .Q(\wbk_xdma_wpl_dat[dat] [17]),
        .R(1'b0));
  FDRE \DataOut_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[18]),
        .Q(\wbk_xdma_wpl_dat[dat] [18]),
        .R(1'b0));
  FDRE \DataOut_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[19]),
        .Q(\wbk_xdma_wpl_dat[dat] [19]),
        .R(1'b0));
  FDRE \DataOut_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[1]),
        .Q(\wbk_xdma_wpl_dat[dat] [1]),
        .R(1'b0));
  FDRE \DataOut_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[20]),
        .Q(\wbk_xdma_wpl_dat[dat] [20]),
        .R(1'b0));
  FDRE \DataOut_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[21]),
        .Q(\wbk_xdma_wpl_dat[dat] [21]),
        .R(1'b0));
  FDRE \DataOut_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[22]),
        .Q(\wbk_xdma_wpl_dat[dat] [22]),
        .R(1'b0));
  FDRE \DataOut_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[23]),
        .Q(\wbk_xdma_wpl_dat[dat] [23]),
        .R(1'b0));
  FDRE \DataOut_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[2]),
        .Q(\wbk_xdma_wpl_dat[dat] [2]),
        .R(1'b0));
  FDRE \DataOut_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[30]),
        .Q(\wbk_xdma_wpl_dat[dat] [30]),
        .R(1'b0));
  FDRE \DataOut_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[31]),
        .Q(\wbk_xdma_wpl_dat[dat] [31]),
        .R(1'b0));
  FDRE \DataOut_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[3]),
        .Q(\wbk_xdma_wpl_dat[dat] [3]),
        .R(1'b0));
  FDRE \DataOut_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[4]),
        .Q(\wbk_xdma_wpl_dat[dat] [4]),
        .R(1'b0));
  FDRE \DataOut_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[5]),
        .Q(\wbk_xdma_wpl_dat[dat] [5]),
        .R(1'b0));
  FDRE \DataOut_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[6]),
        .Q(\wbk_xdma_wpl_dat[dat] [6]),
        .R(1'b0));
  FDRE \DataOut_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[7]),
        .Q(\wbk_xdma_wpl_dat[dat] [7]),
        .R(1'b0));
  FDRE \DataOut_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[8]),
        .Q(\wbk_xdma_wpl_dat[dat] [8]),
        .R(1'b0));
  FDRE \DataOut_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(DataOut[9]),
        .Q(\wbk_xdma_wpl_dat[dat] [9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1334" *) 
  LUT3 #(
    .INIT(8'h69)) 
    \FifoCntrWr[0]_i_1 
       (.I0(wpl_ren_ff),
        .I1(empty_ff),
        .I2(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1332" *) 
  LUT4 #(
    .INIT(16'hBD42)) 
    \FifoCntrWr[1]_i_1 
       (.I0(FifoCntrWr[0]),
        .I1(wpl_ren_ff),
        .I2(empty_ff),
        .I3(FifoCntrWr[1]),
        .O(\FifoCntrWr[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1332" *) 
  LUT5 #(
    .INIT(32'hEFF71008)) 
    \FifoCntrWr[2]_i_1 
       (.I0(FifoCntrWr[1]),
        .I1(FifoCntrWr[0]),
        .I2(wpl_ren_ff),
        .I3(empty_ff),
        .I4(FifoCntrWr[2]),
        .O(\FifoCntrWr[2]_i_1_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[0]_i_1_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(O52));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[1]_i_1_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(O52));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrWr[2]_i_1_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(O52));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "WB_DAT_FIFO/MemArray_reg_0_3_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_3_0_5
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr,\WrPtr_reg[0]_0 }),
        .DIA(Q[1:0]),
        .DIB(Q[3:2]),
        .DIC(Q[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut[1:0]),
        .DOB(DataOut[3:2]),
        .DOC(DataOut[5:4]),
        .DOD(NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wb_win_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "WB_DAT_FIFO/MemArray_reg_0_3_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr,\WrPtr_reg[0]_0 }),
        .DIA(Q[13:12]),
        .DIB(Q[15:14]),
        .DIC(Q[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut[13:12]),
        .DOB(DataOut[15:14]),
        .DOC(DataOut[17:16]),
        .DOD(NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wb_win_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "WB_DAT_FIFO/MemArray_reg_0_3_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr,\WrPtr_reg[0]_0 }),
        .DIA(Q[19:18]),
        .DIB(Q[21:20]),
        .DIC(Q[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut[19:18]),
        .DOB(DataOut[21:20]),
        .DOC(DataOut[23:22]),
        .DOD(NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wb_win_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "dma_top/dma_enable.wb_eng.dma_pcie_wb_eng/WB_DAT_FIFO/MemArray_reg_0_3_30_35" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32X1D MemArray_reg_0_3_30_35
       (.A0(\WrPtr_reg[0]_0 ),
        .A1(WrPtr),
        .A2(1'b0),
        .A3(1'b0),
        .A4(1'b0),
        .D(Q[24]),
        .DPO(DataOut[30]),
        .DPRA0(RdPtr[0]),
        .DPRA1(RdPtr[1]),
        .DPRA2(1'b0),
        .DPRA3(1'b0),
        .DPRA4(1'b0),
        .SPO(NLW_MemArray_reg_0_3_30_35_SPO_UNCONNECTED),
        .WCLK(user_clk),
        .WE(wb_win_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "dma_top/dma_enable.wb_eng.dma_pcie_wb_eng/WB_DAT_FIFO/MemArray_reg_0_3_30_35" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32X1D MemArray_reg_0_3_30_35__0
       (.A0(\WrPtr_reg[0]_0 ),
        .A1(WrPtr),
        .A2(1'b0),
        .A3(1'b0),
        .A4(1'b0),
        .D(Q[25]),
        .DPO(DataOut[31]),
        .DPRA0(RdPtr[0]),
        .DPRA1(RdPtr[1]),
        .DPRA2(1'b0),
        .DPRA3(1'b0),
        .DPRA4(1'b0),
        .SPO(NLW_MemArray_reg_0_3_30_35__0_SPO_UNCONNECTED),
        .WCLK(user_clk),
        .WE(wb_win_vld));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "WB_DAT_FIFO/MemArray_reg_0_3_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr,\WrPtr_reg[0]_0 }),
        .DIA(Q[7:6]),
        .DIB(Q[9:8]),
        .DIC(Q[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut[7:6]),
        .DOB(DataOut[9:8]),
        .DOC(DataOut[11:10]),
        .DOD(NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wb_win_vld));
  (* SOFT_HLUTNM = "soft_lutpair1333" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \RdPtr[0]_i_1__13 
       (.I0(wpl_ren_ff),
        .I1(RdPtr[0]),
        .O(\RdPtr[0]_i_1__13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1333" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \RdPtr[1]_i_1__14 
       (.I0(RdPtr[1]),
        .I1(RdPtr[0]),
        .I2(wpl_ren_ff),
        .O(\RdPtr[1]_i_1__14_n_0 ));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1__13_n_0 ),
        .Q(RdPtr[0]),
        .R(O52));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[1]_i_1__14_n_0 ),
        .Q(RdPtr[1]),
        .R(O52));
  (* SOFT_HLUTNM = "soft_lutpair1334" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \WrPtr[1]_i_1__14 
       (.I0(WrPtr),
        .I1(empty_ff),
        .I2(\WrPtr_reg[0]_0 ),
        .O(\WrPtr[1]_i_1__14_n_0 ));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D),
        .Q(\WrPtr_reg[0]_0 ),
        .R(O52));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[1]_i_1__14_n_0 ),
        .Q(WrPtr),
        .R(O52));
  FDRE almost_full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(FifoCntrWr[2]),
        .Q(wb_dat_fl),
        .R(O52));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[0]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [0]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [0]),
        .O(dat_fifo_vld_102_reg));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[10]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [10]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [10]),
        .O(dat_fifo_vld_102_reg_9));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[11]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [11]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [11]),
        .O(dat_fifo_vld_102_reg_10));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[12]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [12]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [12]),
        .O(dat_fifo_vld_102_reg_11));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[13]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [13]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [13]),
        .O(dat_fifo_vld_102_reg_12));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[14]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [14]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [14]),
        .O(dat_fifo_vld_102_reg_13));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[15]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [15]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [15]),
        .O(dat_fifo_vld_102_reg_14));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[16]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [16]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [16]),
        .O(dat_fifo_vld_102_reg_15));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[17]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [17]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [17]),
        .O(dat_fifo_vld_102_reg_16));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[18]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [18]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [18]),
        .O(dat_fifo_vld_102_reg_17));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[19]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [19]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [19]),
        .O(dat_fifo_vld_102_reg_18));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[1]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [1]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [1]),
        .O(dat_fifo_vld_102_reg_0));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[20]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [20]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [20]),
        .O(dat_fifo_vld_102_reg_19));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[21]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [21]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [21]),
        .O(dat_fifo_vld_102_reg_20));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[22]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [22]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [22]),
        .O(dat_fifo_vld_102_reg_21));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[23]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [23]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [23]),
        .O(dat_fifo_vld_102_reg_22));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[2]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [2]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [2]),
        .O(dat_fifo_vld_102_reg_1));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[30]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [24]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [30]),
        .O(dat_fifo_vld_102_reg_23));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[31]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [25]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [31]),
        .O(dat_fifo_vld_102_reg_24));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[3]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [3]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [3]),
        .O(dat_fifo_vld_102_reg_2));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[4]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [4]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [4]),
        .O(dat_fifo_vld_102_reg_3));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[5]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [5]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [5]),
        .O(dat_fifo_vld_102_reg_4));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[6]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [6]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [6]),
        .O(dat_fifo_vld_102_reg_5));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[7]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [7]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [7]),
        .O(dat_fifo_vld_102_reg_6));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[8]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [8]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [8]),
        .O(dat_fifo_vld_102_reg_7));
  LUT4 #(
    .INIT(16'hF888)) 
    \wpl_dat_ff[9]_i_1 
       (.I0(dat_fifo_vld_102),
        .I1(\mi_c2h0_dat\.rdat [9]),
        .I2(wbk_xdma_wpl_vld),
        .I3(\wbk_xdma_wpl_dat[dat] [9]),
        .O(dat_fifo_vld_102_reg_8));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFO" *) 
module xdma_0_xdma_v4_1_29_GenericFIFO__parameterized1
   (tag_ep_0,
    Q,
    \FifoCntrWr_reg[1]_0 ,
    \WrPtr_reg[4]_0 ,
    rreq_active0,
    user_clk,
    tag_sel_ff,
    tag_sel_ff0,
    tag_rd,
    SR,
    init_tag_ld_nn1,
    rclp_tlp_tagdone,
    \FifoCntrWr_reg[2]_0 ,
    \WrPtr_reg[4]_1 ,
    D,
    tag_ep_1,
    empty_ff,
    E,
    \FifoCntrWr_reg[1]_1 );
  output tag_ep_0;
  output [4:0]Q;
  output [1:0]\FifoCntrWr_reg[1]_0 ;
  output [4:0]\WrPtr_reg[4]_0 ;
  output rreq_active0;
  input user_clk;
  input tag_sel_ff;
  input tag_sel_ff0;
  input [0:0]tag_rd;
  input [0:0]SR;
  input init_tag_ld_nn1;
  input rclp_tlp_tagdone;
  input [0:0]\FifoCntrWr_reg[2]_0 ;
  input \WrPtr_reg[4]_1 ;
  input [1:0]D;
  input tag_ep_1;
  input empty_ff;
  input [0:0]E;
  input [0:0]\FifoCntrWr_reg[1]_1 ;

  wire [1:0]D;
  wire [0:0]E;
  wire [5:2]FifoCntrRd_reg;
  wire \FifoCntrWr[0]_i_1__9_n_0 ;
  wire \FifoCntrWr[2]_i_1__8_n_0 ;
  wire \FifoCntrWr[3]_i_1__1_n_0 ;
  wire \FifoCntrWr[4]_i_1_n_0 ;
  wire \FifoCntrWr[5]_i_2_n_0 ;
  wire \FifoCntrWr[5]_i_3_n_0 ;
  wire [1:0]\FifoCntrWr_reg[1]_0 ;
  wire [0:0]\FifoCntrWr_reg[1]_1 ;
  wire [0:0]\FifoCntrWr_reg[2]_0 ;
  wire [4:0]Q;
  wire [4:0]RdPtr__0;
  wire [0:0]SR;
  wire [4:2]WrPtr__0;
  wire [4:0]\WrPtr_reg[4]_0 ;
  wire \WrPtr_reg[4]_1 ;
  wire empty_ff;
  wire empty_ff_i_1__12_n_0;
  wire empty_ff_i_3__0_n_0;
  wire init_tag_ld_nn1;
  wire p_0_in__0;
  wire rclp_tlp_tagdone;
  wire rreq_active0;
  wire tag_ep_0;
  wire tag_ep_1;
  wire [0:0]tag_rd;
  wire tag_sel_ff;
  wire tag_sel_ff0;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair1372" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__9 
       (.I0(\FifoCntrWr_reg[1]_0 [0]),
        .O(\FifoCntrWr[0]_i_1__9_n_0 ));
  LUT6 #(
    .INIT(64'h6656AAAAAAAA99A9)) 
    \FifoCntrWr[2]_i_1__8 
       (.I0(FifoCntrRd_reg[2]),
        .I1(init_tag_ld_nn1),
        .I2(rclp_tlp_tagdone),
        .I3(\FifoCntrWr_reg[2]_0 ),
        .I4(\FifoCntrWr_reg[1]_0 [1]),
        .I5(\FifoCntrWr_reg[1]_0 [0]),
        .O(\FifoCntrWr[2]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1372" *) 
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \FifoCntrWr[3]_i_1__1 
       (.I0(FifoCntrRd_reg[3]),
        .I1(\WrPtr_reg[4]_1 ),
        .I2(\FifoCntrWr_reg[1]_0 [1]),
        .I3(\FifoCntrWr_reg[1]_0 [0]),
        .I4(FifoCntrRd_reg[2]),
        .O(\FifoCntrWr[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \FifoCntrWr[4]_i_1 
       (.I0(FifoCntrRd_reg[4]),
        .I1(\WrPtr_reg[4]_1 ),
        .I2(\FifoCntrWr_reg[1]_0 [1]),
        .I3(\FifoCntrWr_reg[1]_0 [0]),
        .I4(FifoCntrRd_reg[2]),
        .I5(FifoCntrRd_reg[3]),
        .O(\FifoCntrWr[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \FifoCntrWr[5]_i_2 
       (.I0(FifoCntrRd_reg[5]),
        .I1(FifoCntrRd_reg[2]),
        .I2(\FifoCntrWr[5]_i_3_n_0 ),
        .I3(FifoCntrRd_reg[3]),
        .I4(FifoCntrRd_reg[4]),
        .O(\FifoCntrWr[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hD5D5D5D554D55454)) 
    \FifoCntrWr[5]_i_3 
       (.I0(FifoCntrRd_reg[2]),
        .I1(\FifoCntrWr_reg[1]_0 [0]),
        .I2(\FifoCntrWr_reg[1]_0 [1]),
        .I3(\FifoCntrWr_reg[2]_0 ),
        .I4(rclp_tlp_tagdone),
        .I5(init_tag_ld_nn1),
        .O(\FifoCntrWr[5]_i_3_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[0]_i_1__9_n_0 ),
        .Q(\FifoCntrWr_reg[1]_0 [0]),
        .R(SR));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr_reg[1]_1 ),
        .Q(\FifoCntrWr_reg[1]_0 [1]),
        .R(SR));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[2]_i_1__8_n_0 ),
        .Q(FifoCntrRd_reg[2]),
        .R(SR));
  FDRE \FifoCntrWr_reg[3] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[3]_i_1__1_n_0 ),
        .Q(FifoCntrRd_reg[3]),
        .R(SR));
  FDRE \FifoCntrWr_reg[4] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[4]_i_1_n_0 ),
        .Q(FifoCntrRd_reg[4]),
        .R(SR));
  FDRE \FifoCntrWr_reg[5] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[5]_i_2_n_0 ),
        .Q(FifoCntrRd_reg[5]),
        .R(SR));
  LUT3 #(
    .INIT(8'h9A)) 
    \RdPtr[0]_i_1__10 
       (.I0(Q[0]),
        .I1(tag_sel_ff),
        .I2(tag_sel_ff0),
        .O(RdPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1371" *) 
  LUT4 #(
    .INIT(16'hDF20)) 
    \RdPtr[1]_i_1__11 
       (.I0(tag_sel_ff0),
        .I1(tag_sel_ff),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(RdPtr__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1371" *) 
  LUT5 #(
    .INIT(32'hDFFF2000)) 
    \RdPtr[2]_i_1__2 
       (.I0(Q[0]),
        .I1(tag_sel_ff),
        .I2(tag_sel_ff0),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(RdPtr__0[2]));
  LUT6 #(
    .INIT(64'hF7FFFFFF08000000)) 
    \RdPtr[3]_i_1 
       (.I0(Q[1]),
        .I1(tag_sel_ff0),
        .I2(tag_sel_ff),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[3]),
        .O(RdPtr__0[3]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \RdPtr[4]_i_2 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(tag_rd),
        .I4(Q[1]),
        .I5(Q[4]),
        .O(RdPtr__0[4]));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE \RdPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE \RdPtr_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE \RdPtr_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[4]),
        .Q(Q[4]),
        .R(SR));
  LUT6 #(
    .INIT(64'h7757FFFF88A80000)) 
    \WrPtr[2]_i_1__2 
       (.I0(\WrPtr_reg[4]_0 [0]),
        .I1(init_tag_ld_nn1),
        .I2(rclp_tlp_tagdone),
        .I3(\FifoCntrWr_reg[2]_0 ),
        .I4(\WrPtr_reg[4]_0 [1]),
        .I5(\WrPtr_reg[4]_0 [2]),
        .O(WrPtr__0[2]));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \WrPtr[3]_i_1 
       (.I0(\WrPtr_reg[4]_0 [1]),
        .I1(\WrPtr_reg[4]_1 ),
        .I2(\WrPtr_reg[4]_0 [0]),
        .I3(\WrPtr_reg[4]_0 [2]),
        .I4(\WrPtr_reg[4]_0 [3]),
        .O(WrPtr__0[3]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \WrPtr[4]_i_1 
       (.I0(\WrPtr_reg[4]_0 [3]),
        .I1(\WrPtr_reg[4]_0 [2]),
        .I2(\WrPtr_reg[4]_0 [0]),
        .I3(\WrPtr_reg[4]_1 ),
        .I4(\WrPtr_reg[4]_0 [1]),
        .I5(\WrPtr_reg[4]_0 [4]),
        .O(WrPtr__0[4]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(\WrPtr_reg[4]_0 [0]),
        .R(SR));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(\WrPtr_reg[4]_0 [1]),
        .R(SR));
  FDRE \WrPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[2]),
        .Q(\WrPtr_reg[4]_0 [2]),
        .R(SR));
  FDRE \WrPtr_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[3]),
        .Q(\WrPtr_reg[4]_0 [3]),
        .R(SR));
  FDRE \WrPtr_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[4]),
        .Q(\WrPtr_reg[4]_0 [4]),
        .R(SR));
  LUT6 #(
    .INIT(64'hFFAEFFFFAEAEAEAE)) 
    empty_ff_i_1__12
       (.I0(SR),
        .I1(tag_ep_0),
        .I2(p_0_in__0),
        .I3(tag_rd),
        .I4(\FifoCntrWr_reg[1]_0 [0]),
        .I5(empty_ff_i_3__0_n_0),
        .O(empty_ff_i_1__12_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    empty_ff_i_2__5
       (.I0(\FifoCntrWr_reg[1]_0 [1]),
        .I1(FifoCntrRd_reg[2]),
        .I2(FifoCntrRd_reg[3]),
        .I3(FifoCntrRd_reg[4]),
        .I4(\FifoCntrWr_reg[1]_0 [0]),
        .I5(FifoCntrRd_reg[5]),
        .O(p_0_in__0));
  LUT5 #(
    .INIT(32'h00000001)) 
    empty_ff_i_3__0
       (.I0(\FifoCntrWr_reg[1]_0 [1]),
        .I1(FifoCntrRd_reg[2]),
        .I2(FifoCntrRd_reg[3]),
        .I3(FifoCntrRd_reg[5]),
        .I4(FifoCntrRd_reg[4]),
        .O(empty_ff_i_3__0_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__12_n_0),
        .Q(tag_ep_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h001D)) 
    \rreq_head_vld_ff[1]_i_2 
       (.I0(tag_ep_0),
        .I1(tag_sel_ff),
        .I2(tag_ep_1),
        .I3(empty_ff),
        .O(rreq_active0));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFO" *) 
module xdma_0_xdma_v4_1_29_GenericFIFO__parameterized1_38
   (tag_ep_1,
    Q,
    \FifoCntrWr_reg[1]_0 ,
    \WrPtr_reg[4]_0 ,
    tag_sel_ff_reg,
    user_clk,
    tag_sel_ff,
    tag_sel_ff0,
    tag_rd,
    SR,
    init_tag_ld_nn1,
    rclp_tlp_tagdone,
    \FifoCntrWr_reg[2]_0 ,
    \WrPtr_reg[4]_1 ,
    D,
    \tag_dout[1]_1 ,
    \tag_dout[0]_0 ,
    E,
    \FifoCntrWr_reg[1]_1 );
  output tag_ep_1;
  output [4:0]Q;
  output [1:0]\FifoCntrWr_reg[1]_0 ;
  output [4:0]\WrPtr_reg[4]_0 ;
  output [4:0]tag_sel_ff_reg;
  input user_clk;
  input tag_sel_ff;
  input tag_sel_ff0;
  input [0:0]tag_rd;
  input [0:0]SR;
  input init_tag_ld_nn1;
  input rclp_tlp_tagdone;
  input [0:0]\FifoCntrWr_reg[2]_0 ;
  input \WrPtr_reg[4]_1 ;
  input [1:0]D;
  input [4:0]\tag_dout[1]_1 ;
  input [4:0]\tag_dout[0]_0 ;
  input [0:0]E;
  input [0:0]\FifoCntrWr_reg[1]_1 ;

  wire [1:0]D;
  wire [0:0]E;
  wire [5:2]FifoCntrRd_reg;
  wire \FifoCntrWr[0]_i_1__10_n_0 ;
  wire \FifoCntrWr[2]_i_1__9_n_0 ;
  wire \FifoCntrWr[3]_i_1__2_n_0 ;
  wire \FifoCntrWr[4]_i_1__0_n_0 ;
  wire \FifoCntrWr[5]_i_2__0_n_0 ;
  wire \FifoCntrWr[5]_i_3__0_n_0 ;
  wire [1:0]\FifoCntrWr_reg[1]_0 ;
  wire [0:0]\FifoCntrWr_reg[1]_1 ;
  wire [0:0]\FifoCntrWr_reg[2]_0 ;
  wire [4:0]Q;
  wire [4:0]RdPtr__0;
  wire [0:0]SR;
  wire [4:2]WrPtr__0;
  wire [4:0]\WrPtr_reg[4]_0 ;
  wire \WrPtr_reg[4]_1 ;
  wire empty_ff_i_1__13_n_0;
  wire empty_ff_i_3__1_n_0;
  wire init_tag_ld_nn1;
  wire p_0_in__0;
  wire rclp_tlp_tagdone;
  wire [4:0]\tag_dout[0]_0 ;
  wire [4:0]\tag_dout[1]_1 ;
  wire tag_ep_1;
  wire [0:0]tag_rd;
  wire tag_sel_ff;
  wire tag_sel_ff0;
  wire [4:0]tag_sel_ff_reg;
  wire user_clk;

  (* SOFT_HLUTNM = "soft_lutpair1374" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__10 
       (.I0(\FifoCntrWr_reg[1]_0 [0]),
        .O(\FifoCntrWr[0]_i_1__10_n_0 ));
  LUT6 #(
    .INIT(64'h5666AAAAAAAAA999)) 
    \FifoCntrWr[2]_i_1__9 
       (.I0(FifoCntrRd_reg[2]),
        .I1(init_tag_ld_nn1),
        .I2(rclp_tlp_tagdone),
        .I3(\FifoCntrWr_reg[2]_0 ),
        .I4(\FifoCntrWr_reg[1]_0 [1]),
        .I5(\FifoCntrWr_reg[1]_0 [0]),
        .O(\FifoCntrWr[2]_i_1__9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1374" *) 
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \FifoCntrWr[3]_i_1__2 
       (.I0(FifoCntrRd_reg[3]),
        .I1(\WrPtr_reg[4]_1 ),
        .I2(\FifoCntrWr_reg[1]_0 [1]),
        .I3(\FifoCntrWr_reg[1]_0 [0]),
        .I4(FifoCntrRd_reg[2]),
        .O(\FifoCntrWr[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \FifoCntrWr[4]_i_1__0 
       (.I0(FifoCntrRd_reg[4]),
        .I1(\WrPtr_reg[4]_1 ),
        .I2(\FifoCntrWr_reg[1]_0 [1]),
        .I3(\FifoCntrWr_reg[1]_0 [0]),
        .I4(FifoCntrRd_reg[2]),
        .I5(FifoCntrRd_reg[3]),
        .O(\FifoCntrWr[4]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \FifoCntrWr[5]_i_2__0 
       (.I0(FifoCntrRd_reg[5]),
        .I1(FifoCntrRd_reg[2]),
        .I2(\FifoCntrWr[5]_i_3__0_n_0 ),
        .I3(FifoCntrRd_reg[3]),
        .I4(FifoCntrRd_reg[4]),
        .O(\FifoCntrWr[5]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hD5D5D5D5D5545454)) 
    \FifoCntrWr[5]_i_3__0 
       (.I0(FifoCntrRd_reg[2]),
        .I1(\FifoCntrWr_reg[1]_0 [0]),
        .I2(\FifoCntrWr_reg[1]_0 [1]),
        .I3(\FifoCntrWr_reg[2]_0 ),
        .I4(rclp_tlp_tagdone),
        .I5(init_tag_ld_nn1),
        .O(\FifoCntrWr[5]_i_3__0_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[0]_i_1__10_n_0 ),
        .Q(\FifoCntrWr_reg[1]_0 [0]),
        .R(SR));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr_reg[1]_1 ),
        .Q(\FifoCntrWr_reg[1]_0 [1]),
        .R(SR));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[2]_i_1__9_n_0 ),
        .Q(FifoCntrRd_reg[2]),
        .R(SR));
  FDRE \FifoCntrWr_reg[3] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[3]_i_1__2_n_0 ),
        .Q(FifoCntrRd_reg[3]),
        .R(SR));
  FDRE \FifoCntrWr_reg[4] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[4]_i_1__0_n_0 ),
        .Q(FifoCntrRd_reg[4]),
        .R(SR));
  FDRE \FifoCntrWr_reg[5] 
       (.C(user_clk),
        .CE(E),
        .D(\FifoCntrWr[5]_i_2__0_n_0 ),
        .Q(FifoCntrRd_reg[5]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair1375" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \RdPtr[0]_i_1__11 
       (.I0(Q[0]),
        .I1(tag_sel_ff),
        .I2(tag_sel_ff0),
        .O(RdPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1373" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \RdPtr[1]_i_1__12 
       (.I0(tag_sel_ff0),
        .I1(tag_sel_ff),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(RdPtr__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1373" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \RdPtr[2]_i_1__3 
       (.I0(Q[0]),
        .I1(tag_sel_ff),
        .I2(tag_sel_ff0),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(RdPtr__0[2]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \RdPtr[3]_i_1__0 
       (.I0(Q[1]),
        .I1(tag_sel_ff0),
        .I2(tag_sel_ff),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[3]),
        .O(RdPtr__0[3]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \RdPtr[4]_i_1 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(tag_rd),
        .I4(Q[1]),
        .I5(Q[4]),
        .O(RdPtr__0[4]));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(Q[1]),
        .R(SR));
  FDRE \RdPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[2]),
        .Q(Q[2]),
        .R(SR));
  FDRE \RdPtr_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[3]),
        .Q(Q[3]),
        .R(SR));
  FDRE \RdPtr_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[4]),
        .Q(Q[4]),
        .R(SR));
  LUT6 #(
    .INIT(64'h5777FFFFA8880000)) 
    \WrPtr[2]_i_1__3 
       (.I0(\WrPtr_reg[4]_0 [0]),
        .I1(init_tag_ld_nn1),
        .I2(rclp_tlp_tagdone),
        .I3(\FifoCntrWr_reg[2]_0 ),
        .I4(\WrPtr_reg[4]_0 [1]),
        .I5(\WrPtr_reg[4]_0 [2]),
        .O(WrPtr__0[2]));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \WrPtr[3]_i_1__0 
       (.I0(\WrPtr_reg[4]_0 [1]),
        .I1(\WrPtr_reg[4]_1 ),
        .I2(\WrPtr_reg[4]_0 [0]),
        .I3(\WrPtr_reg[4]_0 [2]),
        .I4(\WrPtr_reg[4]_0 [3]),
        .O(WrPtr__0[3]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \WrPtr[4]_i_1__0 
       (.I0(\WrPtr_reg[4]_0 [3]),
        .I1(\WrPtr_reg[4]_0 [2]),
        .I2(\WrPtr_reg[4]_0 [0]),
        .I3(\WrPtr_reg[4]_1 ),
        .I4(\WrPtr_reg[4]_0 [1]),
        .I5(\WrPtr_reg[4]_0 [4]),
        .O(WrPtr__0[4]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(\WrPtr_reg[4]_0 [0]),
        .R(SR));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(\WrPtr_reg[4]_0 [1]),
        .R(SR));
  FDRE \WrPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[2]),
        .Q(\WrPtr_reg[4]_0 [2]),
        .R(SR));
  FDRE \WrPtr_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[3]),
        .Q(\WrPtr_reg[4]_0 [3]),
        .R(SR));
  FDRE \WrPtr_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[4]),
        .Q(\WrPtr_reg[4]_0 [4]),
        .R(SR));
  LUT6 #(
    .INIT(64'hFFAEFFFFAEAEAEAE)) 
    empty_ff_i_1__13
       (.I0(SR),
        .I1(tag_ep_1),
        .I2(p_0_in__0),
        .I3(tag_rd),
        .I4(\FifoCntrWr_reg[1]_0 [0]),
        .I5(empty_ff_i_3__1_n_0),
        .O(empty_ff_i_1__13_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    empty_ff_i_2__6
       (.I0(\FifoCntrWr_reg[1]_0 [1]),
        .I1(FifoCntrRd_reg[2]),
        .I2(FifoCntrRd_reg[3]),
        .I3(FifoCntrRd_reg[4]),
        .I4(\FifoCntrWr_reg[1]_0 [0]),
        .I5(FifoCntrRd_reg[5]),
        .O(p_0_in__0));
  LUT5 #(
    .INIT(32'h00000001)) 
    empty_ff_i_3__1
       (.I0(\FifoCntrWr_reg[1]_0 [1]),
        .I1(FifoCntrRd_reg[2]),
        .I2(FifoCntrRd_reg[3]),
        .I3(FifoCntrRd_reg[5]),
        .I4(FifoCntrRd_reg[4]),
        .O(empty_ff_i_3__1_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__13_n_0),
        .Q(tag_ep_1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1376" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[1][tag][1]_i_1 
       (.I0(\tag_dout[1]_1 [0]),
        .I1(tag_sel_ff),
        .I2(\tag_dout[0]_0 [0]),
        .O(tag_sel_ff_reg[0]));
  (* SOFT_HLUTNM = "soft_lutpair1377" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[1][tag][2]_i_1 
       (.I0(\tag_dout[1]_1 [1]),
        .I1(tag_sel_ff),
        .I2(\tag_dout[0]_0 [1]),
        .O(tag_sel_ff_reg[1]));
  (* SOFT_HLUTNM = "soft_lutpair1375" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[1][tag][3]_i_1 
       (.I0(\tag_dout[1]_1 [2]),
        .I1(tag_sel_ff),
        .I2(\tag_dout[0]_0 [2]),
        .O(tag_sel_ff_reg[2]));
  (* SOFT_HLUTNM = "soft_lutpair1377" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[1][tag][4]_i_1 
       (.I0(\tag_dout[1]_1 [3]),
        .I1(tag_sel_ff),
        .I2(\tag_dout[0]_0 [3]),
        .O(tag_sel_ff_reg[3]));
  (* SOFT_HLUTNM = "soft_lutpair1376" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rreq_head_info_ff[1][tag][5]_i_1 
       (.I0(\tag_dout[1]_1 [4]),
        .I1(tag_sel_ff),
        .I2(\tag_dout[0]_0 [4]),
        .O(tag_sel_ff_reg[4]));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFO" *) 
module xdma_0_xdma_v4_1_29_GenericFIFO__parameterized2
   (\userclk1_i1.usrclk1_i1 ,
    empty_ff_reg_0,
    E,
    D,
    \reqdtlpSm_cs_reg[1] ,
    \userclk1_i1.usrclk1_i1_0 ,
    \userclk1_i1.usrclk1_i1_1 ,
    user_clk,
    Q,
    wtlp_hdr_ld_500,
    wtlp_hdr_pop00_out,
    \wtlp_hdr_wr_cnt_nn1_reg[3] ,
    reqdtlpSm_cs,
    reqdtlpSm512_cs,
    SR,
    \FifoCntrWr_reg[0]_0 ,
    user_rst_n_3ff_reg);
  output [87:0]\userclk1_i1.usrclk1_i1 ;
  output empty_ff_reg_0;
  output [0:0]E;
  output [2:0]D;
  output \reqdtlpSm_cs_reg[1] ;
  output [9:0]\userclk1_i1.usrclk1_i1_0 ;
  output \userclk1_i1.usrclk1_i1_1 ;
  input user_clk;
  input [98:0]Q;
  input wtlp_hdr_ld_500;
  input wtlp_hdr_pop00_out;
  input [3:0]\wtlp_hdr_wr_cnt_nn1_reg[3] ;
  input [0:0]reqdtlpSm_cs;
  input [0:0]reqdtlpSm512_cs;
  input [0:0]SR;
  input [0:0]\FifoCntrWr_reg[0]_0 ;
  input [0:0]user_rst_n_3ff_reg;

  wire [2:0]D;
  wire [0:0]E;
  wire [3:0]FifoCntrRd_reg;
  wire \FifoCntrWr[0]_i_1__7_n_0 ;
  wire \FifoCntrWr[1]_i_1__13_n_0 ;
  wire \FifoCntrWr[2]_i_1__7_n_0 ;
  wire \FifoCntrWr[3]_i_2__1_n_0 ;
  wire [0:0]\FifoCntrWr_reg[0]_0 ;
  wire MemArray_reg_0_7_72_77_n_1;
  wire MemArray_reg_0_7_78_83_n_4;
  wire MemArray_reg_0_7_96_101_n_2;
  wire MemArray_reg_0_7_96_101_n_5;
  wire [98:0]Q;
  wire [2:0]RdPtr;
  wire \RdPtr[0]_i_1__14_n_0 ;
  wire [2:1]RdPtr__0;
  wire [0:0]SR;
  wire [2:0]WrPtr;
  wire [2:0]WrPtr__0;
  wire empty_ff_i_1__10_n_0;
  wire empty_ff_i_2__8_n_0;
  wire empty_ff_i_3_n_0;
  wire empty_ff_i_4_n_0;
  wire empty_ff_reg_0;
  wire [0:0]reqdtlpSm512_cs;
  wire [0:0]reqdtlpSm_cs;
  wire \reqdtlpSm_cs_reg[1] ;
  wire user_clk;
  wire [0:0]user_rst_n_3ff_reg;
  wire [87:0]\userclk1_i1.usrclk1_i1 ;
  wire [9:0]\userclk1_i1.usrclk1_i1_0 ;
  wire \userclk1_i1.usrclk1_i1_1 ;
  wire \wpl_hdr_btlenm1_ff[6]_i_2_n_0 ;
  wire \wpl_hdr_btlenm1_ff[9]_i_2_n_0 ;
  wire wtlp_hdr_ld_500;
  wire [71:62]wtlp_hdr_out;
  wire wtlp_hdr_pop00_out;
  wire [3:0]\wtlp_hdr_wr_cnt_nn1_reg[3] ;
  wire [1:0]NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED;
  wire NLW_MemArray_reg_0_7_102_102_SPO_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED;
  wire [0:0]NLW_MemArray_reg_0_7_96_101_DOB_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair1659" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__7 
       (.I0(FifoCntrRd_reg[0]),
        .O(\FifoCntrWr[0]_i_1__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1659" *) 
  LUT3 #(
    .INIT(8'h69)) 
    \FifoCntrWr[1]_i_1__13 
       (.I0(FifoCntrRd_reg[0]),
        .I1(wtlp_hdr_ld_500),
        .I2(FifoCntrRd_reg[1]),
        .O(\FifoCntrWr[1]_i_1__13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1654" *) 
  LUT4 #(
    .INIT(16'h78E1)) 
    \FifoCntrWr[2]_i_1__7 
       (.I0(FifoCntrRd_reg[0]),
        .I1(wtlp_hdr_ld_500),
        .I2(FifoCntrRd_reg[2]),
        .I3(FifoCntrRd_reg[1]),
        .O(\FifoCntrWr[2]_i_1__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1654" *) 
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \FifoCntrWr[3]_i_2__1 
       (.I0(wtlp_hdr_ld_500),
        .I1(FifoCntrRd_reg[0]),
        .I2(FifoCntrRd_reg[1]),
        .I3(FifoCntrRd_reg[3]),
        .I4(FifoCntrRd_reg[2]),
        .O(\FifoCntrWr[3]_i_2__1_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[0]_0 ),
        .D(\FifoCntrWr[0]_i_1__7_n_0 ),
        .Q(FifoCntrRd_reg[0]),
        .R(SR));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[0]_0 ),
        .D(\FifoCntrWr[1]_i_1__13_n_0 ),
        .Q(FifoCntrRd_reg[1]),
        .R(SR));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[0]_0 ),
        .D(\FifoCntrWr[2]_i_1__7_n_0 ),
        .Q(FifoCntrRd_reg[2]),
        .R(SR));
  FDRE \FifoCntrWr_reg[3] 
       (.C(user_clk),
        .CE(\FifoCntrWr_reg[0]_0 ),
        .D(\FifoCntrWr[3]_i_2__1_n_0 ),
        .Q(FifoCntrRd_reg[3]),
        .R(SR));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_7_0_5
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[1:0]),
        .DIB(Q[3:2]),
        .DIC(Q[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [1:0]),
        .DOB(\userclk1_i1.usrclk1_i1 [3:2]),
        .DOC(\userclk1_i1.usrclk1_i1 [5:4]),
        .DOD(NLW_MemArray_reg_0_7_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "dma_top/dma_pcie_req/dma_pcie_rq/WTLP_HDR_FIFO/MemArray_reg_0_7_102_102" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "102" *) 
  (* ram_slice_end = "102" *) 
  RAM32X1D MemArray_reg_0_7_102_102
       (.A0(WrPtr[0]),
        .A1(WrPtr[1]),
        .A2(WrPtr[2]),
        .A3(1'b0),
        .A4(1'b0),
        .D(Q[98]),
        .DPO(\userclk1_i1.usrclk1_i1 [87]),
        .DPRA0(RdPtr[0]),
        .DPRA1(RdPtr[1]),
        .DPRA2(RdPtr[2]),
        .DPRA3(1'b0),
        .DPRA4(1'b0),
        .SPO(NLW_MemArray_reg_0_7_102_102_SPO_UNCONNECTED),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_7_12_17
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[13:12]),
        .DIB(Q[15:14]),
        .DIC(Q[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [13:12]),
        .DOB(\userclk1_i1.usrclk1_i1 [15:14]),
        .DOC(\userclk1_i1.usrclk1_i1 [17:16]),
        .DOD(NLW_MemArray_reg_0_7_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_7_18_23
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[19:18]),
        .DIB(Q[21:20]),
        .DIC(Q[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [19:18]),
        .DOB(\userclk1_i1.usrclk1_i1 [21:20]),
        .DOC(\userclk1_i1.usrclk1_i1 [23:22]),
        .DOD(NLW_MemArray_reg_0_7_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_24_29" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M MemArray_reg_0_7_24_29
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[25:24]),
        .DIB(Q[27:26]),
        .DIC(Q[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [25:24]),
        .DOB(\userclk1_i1.usrclk1_i1 [27:26]),
        .DOC(\userclk1_i1.usrclk1_i1 [29:28]),
        .DOD(NLW_MemArray_reg_0_7_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_30_35" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M MemArray_reg_0_7_30_35
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[31:30]),
        .DIB(Q[33:32]),
        .DIC(Q[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [31:30]),
        .DOB(\userclk1_i1.usrclk1_i1 [33:32]),
        .DOC(\userclk1_i1.usrclk1_i1 [35:34]),
        .DOD(NLW_MemArray_reg_0_7_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_36_41" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M MemArray_reg_0_7_36_41
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[37:36]),
        .DIB(Q[39:38]),
        .DIC(Q[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [37:36]),
        .DOB(\userclk1_i1.usrclk1_i1 [39:38]),
        .DOC(\userclk1_i1.usrclk1_i1 [41:40]),
        .DOD(NLW_MemArray_reg_0_7_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_42_47" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M MemArray_reg_0_7_42_47
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[43:42]),
        .DIB(Q[45:44]),
        .DIC(Q[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [43:42]),
        .DOB(\userclk1_i1.usrclk1_i1 [45:44]),
        .DOC(\userclk1_i1.usrclk1_i1 [47:46]),
        .DOD(NLW_MemArray_reg_0_7_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_48_53" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M MemArray_reg_0_7_48_53
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[49:48]),
        .DIB(Q[51:50]),
        .DIC(Q[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [49:48]),
        .DOB(\userclk1_i1.usrclk1_i1 [51:50]),
        .DOC(\userclk1_i1.usrclk1_i1 [53:52]),
        .DOD(NLW_MemArray_reg_0_7_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_54_59" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M MemArray_reg_0_7_54_59
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[55:54]),
        .DIB(Q[57:56]),
        .DIC(Q[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [55:54]),
        .DOB(\userclk1_i1.usrclk1_i1 [57:56]),
        .DOC(\userclk1_i1.usrclk1_i1 [59:58]),
        .DOD(NLW_MemArray_reg_0_7_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_60_65" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M MemArray_reg_0_7_60_65
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[61:60]),
        .DIB(Q[63:62]),
        .DIC(Q[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [61:60]),
        .DOB(wtlp_hdr_out[63:62]),
        .DOC(wtlp_hdr_out[65:64]),
        .DOD(NLW_MemArray_reg_0_7_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_66_71" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M MemArray_reg_0_7_66_71
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[67:66]),
        .DIB(Q[69:68]),
        .DIC({1'b0,Q[70]}),
        .DID({1'b0,1'b0}),
        .DOA(wtlp_hdr_out[67:66]),
        .DOB(wtlp_hdr_out[69:68]),
        .DOC(wtlp_hdr_out[71:70]),
        .DOD(NLW_MemArray_reg_0_7_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_7_6_11
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[7:6]),
        .DIB(Q[9:8]),
        .DIC(Q[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [7:6]),
        .DOB(\userclk1_i1.usrclk1_i1 [9:8]),
        .DOC(\userclk1_i1.usrclk1_i1 [11:10]),
        .DOD(NLW_MemArray_reg_0_7_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_72_77" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M MemArray_reg_0_7_72_77
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[72:71]),
        .DIB(Q[74:73]),
        .DIC(Q[76:75]),
        .DID({1'b0,1'b0}),
        .DOA({\userclk1_i1.usrclk1_i1 [62],MemArray_reg_0_7_72_77_n_1}),
        .DOB(\userclk1_i1.usrclk1_i1 [64:63]),
        .DOC(\userclk1_i1.usrclk1_i1 [66:65]),
        .DOD(NLW_MemArray_reg_0_7_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_78_83" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "83" *) 
  RAM32M MemArray_reg_0_7_78_83
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[78:77]),
        .DIB(Q[80:79]),
        .DIC(Q[82:81]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [68:67]),
        .DOB(\userclk1_i1.usrclk1_i1 [70:69]),
        .DOC({MemArray_reg_0_7_78_83_n_4,\userclk1_i1.usrclk1_i1 [71]}),
        .DOD(NLW_MemArray_reg_0_7_78_83_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_84_89" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "84" *) 
  (* ram_slice_end = "89" *) 
  RAM32M MemArray_reg_0_7_84_89
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[84:83]),
        .DIB(Q[86:85]),
        .DIC(Q[88:87]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [73:72]),
        .DOB(\userclk1_i1.usrclk1_i1 [75:74]),
        .DOC(\userclk1_i1.usrclk1_i1 [77:76]),
        .DOD(NLW_MemArray_reg_0_7_84_89_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_90_95" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "90" *) 
  (* ram_slice_end = "95" *) 
  RAM32M MemArray_reg_0_7_90_95
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[90:89]),
        .DIB(Q[92:91]),
        .DIC(Q[94:93]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [79:78]),
        .DOB(\userclk1_i1.usrclk1_i1 [81:80]),
        .DOC(\userclk1_i1.usrclk1_i1 [83:82]),
        .DOD(NLW_MemArray_reg_0_7_90_95_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "824" *) 
  (* RTL_RAM_NAME = "MemArray_reg_0_7_96_101" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "7" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "96" *) 
  (* ram_slice_end = "101" *) 
  RAM32M MemArray_reg_0_7_96_101
       (.ADDRA({1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,WrPtr}),
        .DIA(Q[96:95]),
        .DIB({1'b0,1'b0}),
        .DIC({Q[97],1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [85:84]),
        .DOB({MemArray_reg_0_7_96_101_n_2,NLW_MemArray_reg_0_7_96_101_DOB_UNCONNECTED[0]}),
        .DOC({\userclk1_i1.usrclk1_i1 [86],MemArray_reg_0_7_96_101_n_5}),
        .DOD(NLW_MemArray_reg_0_7_96_101_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(wtlp_hdr_ld_500));
  (* SOFT_HLUTNM = "soft_lutpair1657" *) 
  LUT3 #(
    .INIT(8'hA6)) 
    \RdPtr[0]_i_1__14 
       (.I0(RdPtr[0]),
        .I1(wtlp_hdr_pop00_out),
        .I2(empty_ff_reg_0),
        .O(\RdPtr[0]_i_1__14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1650" *) 
  LUT4 #(
    .INIT(16'hBF40)) 
    \RdPtr[1]_i_1__10 
       (.I0(empty_ff_reg_0),
        .I1(wtlp_hdr_pop00_out),
        .I2(RdPtr[0]),
        .I3(RdPtr[1]),
        .O(RdPtr__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1650" *) 
  LUT5 #(
    .INIT(32'hF7FF0800)) 
    \RdPtr[2]_i_1__1 
       (.I0(RdPtr[0]),
        .I1(wtlp_hdr_pop00_out),
        .I2(empty_ff_reg_0),
        .I3(RdPtr[1]),
        .I4(RdPtr[2]),
        .O(RdPtr__0[2]));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1__14_n_0 ),
        .Q(RdPtr[0]),
        .R(SR));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[1]),
        .Q(RdPtr[1]),
        .R(SR));
  FDRE \RdPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr__0[2]),
        .Q(RdPtr[2]),
        .R(SR));
  LUT2 #(
    .INIT(4'h6)) 
    \WrPtr[0]_i_1__10 
       (.I0(WrPtr[0]),
        .I1(wtlp_hdr_ld_500),
        .O(WrPtr__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1656" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \WrPtr[1]_i_1__10 
       (.I0(WrPtr[0]),
        .I1(wtlp_hdr_ld_500),
        .I2(WrPtr[1]),
        .O(WrPtr__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1656" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \WrPtr[2]_i_1__1 
       (.I0(wtlp_hdr_ld_500),
        .I1(WrPtr[0]),
        .I2(WrPtr[1]),
        .I3(WrPtr[2]),
        .O(WrPtr__0[2]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[0]),
        .Q(WrPtr[0]),
        .R(SR));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[1]),
        .Q(WrPtr[1]),
        .R(SR));
  FDRE \WrPtr_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr__0[2]),
        .Q(WrPtr[2]),
        .R(SR));
  LUT6 #(
    .INIT(64'hBBBBBBBBBBBFBBFF)) 
    empty_ff_i_1__10
       (.I0(empty_ff_i_2__8_n_0),
        .I1(user_rst_n_3ff_reg),
        .I2(empty_ff_i_3_n_0),
        .I3(empty_ff_i_4_n_0),
        .I4(FifoCntrRd_reg[0]),
        .I5(FifoCntrRd_reg[1]),
        .O(empty_ff_i_1__10_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1653" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    empty_ff_i_2__8
       (.I0(empty_ff_reg_0),
        .I1(FifoCntrRd_reg[3]),
        .I2(FifoCntrRd_reg[0]),
        .I3(FifoCntrRd_reg[1]),
        .I4(FifoCntrRd_reg[2]),
        .O(empty_ff_i_2__8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1657" *) 
  LUT2 #(
    .INIT(4'hB)) 
    empty_ff_i_3
       (.I0(empty_ff_reg_0),
        .I1(wtlp_hdr_pop00_out),
        .O(empty_ff_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1653" *) 
  LUT2 #(
    .INIT(4'hE)) 
    empty_ff_i_4
       (.I0(FifoCntrRd_reg[2]),
        .I1(FifoCntrRd_reg[3]),
        .O(empty_ff_i_4_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__10_n_0),
        .Q(empty_ff_reg_0),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \m_axis_rq_thead_d_ff[0][63]_i_6 
       (.I0(reqdtlpSm_cs),
        .I1(reqdtlpSm512_cs),
        .O(\reqdtlpSm_cs_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair1651" *) 
  LUT5 #(
    .INIT(32'h00000004)) 
    wpl_hdr_btlene1_ff_i_1
       (.I0(wtlp_hdr_out[71]),
        .I1(wtlp_hdr_out[62]),
        .I2(wtlp_hdr_out[70]),
        .I3(\wpl_hdr_btlenm1_ff[9]_i_2_n_0 ),
        .I4(wtlp_hdr_out[69]),
        .O(\userclk1_i1.usrclk1_i1_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1660" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wpl_hdr_btlenm1_ff[0]_i_1 
       (.I0(wtlp_hdr_out[62]),
        .O(\userclk1_i1.usrclk1_i1_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1660" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wpl_hdr_btlenm1_ff[1]_i_1 
       (.I0(wtlp_hdr_out[63]),
        .I1(wtlp_hdr_out[62]),
        .O(\userclk1_i1.usrclk1_i1_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1658" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \wpl_hdr_btlenm1_ff[2]_i_1 
       (.I0(wtlp_hdr_out[62]),
        .I1(wtlp_hdr_out[63]),
        .I2(wtlp_hdr_out[64]),
        .O(\userclk1_i1.usrclk1_i1_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1652" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \wpl_hdr_btlenm1_ff[3]_i_1 
       (.I0(wtlp_hdr_out[62]),
        .I1(wtlp_hdr_out[64]),
        .I2(wtlp_hdr_out[63]),
        .I3(wtlp_hdr_out[65]),
        .O(\userclk1_i1.usrclk1_i1_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair1652" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \wpl_hdr_btlenm1_ff[4]_i_1 
       (.I0(wtlp_hdr_out[62]),
        .I1(wtlp_hdr_out[65]),
        .I2(wtlp_hdr_out[63]),
        .I3(wtlp_hdr_out[64]),
        .I4(wtlp_hdr_out[66]),
        .O(\userclk1_i1.usrclk1_i1_0 [4]));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \wpl_hdr_btlenm1_ff[5]_i_1 
       (.I0(wtlp_hdr_out[62]),
        .I1(wtlp_hdr_out[66]),
        .I2(wtlp_hdr_out[64]),
        .I3(wtlp_hdr_out[63]),
        .I4(wtlp_hdr_out[65]),
        .I5(wtlp_hdr_out[67]),
        .O(\userclk1_i1.usrclk1_i1_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair1658" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \wpl_hdr_btlenm1_ff[6]_i_1 
       (.I0(wtlp_hdr_out[62]),
        .I1(\wpl_hdr_btlenm1_ff[6]_i_2_n_0 ),
        .I2(wtlp_hdr_out[68]),
        .O(\userclk1_i1.usrclk1_i1_0 [6]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \wpl_hdr_btlenm1_ff[6]_i_2 
       (.I0(wtlp_hdr_out[66]),
        .I1(wtlp_hdr_out[64]),
        .I2(wtlp_hdr_out[63]),
        .I3(wtlp_hdr_out[65]),
        .I4(wtlp_hdr_out[67]),
        .O(\wpl_hdr_btlenm1_ff[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1655" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \wpl_hdr_btlenm1_ff[7]_i_1 
       (.I0(wtlp_hdr_out[62]),
        .I1(\wpl_hdr_btlenm1_ff[9]_i_2_n_0 ),
        .I2(wtlp_hdr_out[69]),
        .O(\userclk1_i1.usrclk1_i1_0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair1655" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \wpl_hdr_btlenm1_ff[8]_i_1 
       (.I0(wtlp_hdr_out[62]),
        .I1(wtlp_hdr_out[69]),
        .I2(\wpl_hdr_btlenm1_ff[9]_i_2_n_0 ),
        .I3(wtlp_hdr_out[70]),
        .O(\userclk1_i1.usrclk1_i1_0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair1651" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \wpl_hdr_btlenm1_ff[9]_i_1 
       (.I0(wtlp_hdr_out[62]),
        .I1(wtlp_hdr_out[69]),
        .I2(\wpl_hdr_btlenm1_ff[9]_i_2_n_0 ),
        .I3(wtlp_hdr_out[70]),
        .I4(wtlp_hdr_out[71]),
        .O(\userclk1_i1.usrclk1_i1_0 [9]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \wpl_hdr_btlenm1_ff[9]_i_2 
       (.I0(wtlp_hdr_out[67]),
        .I1(wtlp_hdr_out[65]),
        .I2(wtlp_hdr_out[63]),
        .I3(wtlp_hdr_out[64]),
        .I4(wtlp_hdr_out[66]),
        .I5(wtlp_hdr_out[68]),
        .O(\wpl_hdr_btlenm1_ff[9]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1649" *) 
  LUT5 #(
    .INIT(32'h758A8A75)) 
    \wtlp_hdr_wr_cnt_nn1[1]_i_1 
       (.I0(wtlp_hdr_ld_500),
        .I1(empty_ff_reg_0),
        .I2(wtlp_hdr_pop00_out),
        .I3(\wtlp_hdr_wr_cnt_nn1_reg[3] [1]),
        .I4(\wtlp_hdr_wr_cnt_nn1_reg[3] [0]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h6A66AAAAAAAA9599)) 
    \wtlp_hdr_wr_cnt_nn1[2]_i_1 
       (.I0(\wtlp_hdr_wr_cnt_nn1_reg[3] [2]),
        .I1(wtlp_hdr_ld_500),
        .I2(empty_ff_reg_0),
        .I3(wtlp_hdr_pop00_out),
        .I4(\wtlp_hdr_wr_cnt_nn1_reg[3] [1]),
        .I5(\wtlp_hdr_wr_cnt_nn1_reg[3] [0]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair1649" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wtlp_hdr_wr_cnt_nn1[3]_i_2 
       (.I0(wtlp_hdr_ld_500),
        .I1(empty_ff_reg_0),
        .I2(wtlp_hdr_pop00_out),
        .O(E));
  LUT6 #(
    .INIT(64'h78F0F0F0F0E1E1E1)) 
    \wtlp_hdr_wr_cnt_nn1[3]_i_3 
       (.I0(\wtlp_hdr_wr_cnt_nn1_reg[3] [2]),
        .I1(\wtlp_hdr_wr_cnt_nn1_reg[3] [1]),
        .I2(\wtlp_hdr_wr_cnt_nn1_reg[3] [3]),
        .I3(wtlp_hdr_ld_500),
        .I4(empty_ff_i_3_n_0),
        .I5(\wtlp_hdr_wr_cnt_nn1_reg[3] [0]),
        .O(D[2]));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFO" *) 
module xdma_0_xdma_v4_1_29_GenericFIFO__parameterized3
   (req_fifo_sl_nn0,
    req_fifo_wr_nn0,
    empty_ff_reg_0,
    \arb_pri_nn1_reg[0] ,
    empty_ff_reg_1,
    arb_win_nn14__1,
    DataOut,
    full_ff_reg_0,
    user_clk,
    dat_fifo_ep,
    req_fifo_wr_nn1,
    s_axil_awvalid,
    s_axil_arvalid,
    empty_ff_reg_2,
    s_axil_awaddr,
    arb_pri_nn1_0,
    s_axil_araddr,
    empty_ff_reg_3,
    arb_pri_nn1,
    \arb_win_nn1_reg[1] ,
    Q,
    tar_row_nn1_reg);
  output req_fifo_sl_nn0;
  output req_fifo_wr_nn0;
  output empty_ff_reg_0;
  output [0:0]\arb_pri_nn1_reg[0] ;
  output empty_ff_reg_1;
  output [0:0]arb_win_nn14__1;
  output [15:0]DataOut;
  input full_ff_reg_0;
  input user_clk;
  input dat_fifo_ep;
  input req_fifo_wr_nn1;
  input s_axil_awvalid;
  input s_axil_arvalid;
  input [0:0]empty_ff_reg_2;
  input [17:0]s_axil_awaddr;
  input arb_pri_nn1_0;
  input [17:0]s_axil_araddr;
  input empty_ff_reg_3;
  input [1:0]arb_pri_nn1;
  input [0:0]\arb_win_nn1_reg[1] ;
  input [1:0]Q;
  input tar_row_nn1_reg;

  wire [15:0]DataOut;
  wire \FifoCntrRd[0]_i_1__5_n_0 ;
  wire \FifoCntrRd[1]_i_1__5_n_0 ;
  wire \FifoCntrRd[2]_i_1__6_n_0 ;
  wire \FifoCntrRd[2]_i_2__0_n_0 ;
  wire \FifoCntrRd[2]_i_3_n_0 ;
  wire \FifoCntrRd_reg_n_0_[0] ;
  wire \FifoCntrRd_reg_n_0_[1] ;
  wire \FifoCntrRd_reg_n_0_[2] ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__5_n_0 ;
  wire \FifoCntrWr[1]_i_1__5_n_0 ;
  wire \FifoCntrWr[2]_i_1__5_n_0 ;
  wire MemArray_reg_0_3_0_5_i_2_n_0;
  wire MemArray_reg_0_3_0_5_i_3_n_0;
  wire MemArray_reg_0_3_0_5_i_4_n_0;
  wire MemArray_reg_0_3_0_5_i_5_n_0;
  wire MemArray_reg_0_3_0_5_i_6_n_0;
  wire MemArray_reg_0_3_0_5_i_7_n_0;
  wire MemArray_reg_0_3_12_17_i_1_n_0;
  wire MemArray_reg_0_3_12_17_i_2_n_0;
  wire MemArray_reg_0_3_12_17_i_3_n_0;
  wire MemArray_reg_0_3_12_17_i_4_n_0;
  wire MemArray_reg_0_3_12_17_i_5_n_0;
  wire MemArray_reg_0_3_12_17_i_6_n_0;
  wire MemArray_reg_0_3_12_17_n_4;
  wire MemArray_reg_0_3_12_17_n_5;
  wire MemArray_reg_0_3_6_11_i_1__0_n_0;
  wire MemArray_reg_0_3_6_11_i_2_n_0;
  wire MemArray_reg_0_3_6_11_i_3_n_0;
  wire MemArray_reg_0_3_6_11_i_4_n_0;
  wire MemArray_reg_0_3_6_11_i_5_n_0;
  wire MemArray_reg_0_3_6_11_i_6_n_0;
  wire [1:0]Q;
  wire [1:0]RdPtr;
  wire [1:0]RdPtr_0;
  wire [1:0]WrPtr;
  wire [1:0]WrPtr_1;
  wire [1:0]arb_pri_nn1;
  wire arb_pri_nn1_0;
  wire [0:0]\arb_pri_nn1_reg[0] ;
  wire [0:0]arb_win_nn14__1;
  wire [0:0]\arb_win_nn1_reg[1] ;
  wire dat_fifo_ep;
  wire empty_ff;
  wire empty_ff_i_1__6_n_0;
  wire empty_ff_reg_0;
  wire empty_ff_reg_1;
  wire [0:0]empty_ff_reg_2;
  wire empty_ff_reg_3;
  wire full_ff_i_1__4_n_0;
  wire full_ff_reg_0;
  wire [40:40]req_fifo_dout;
  wire req_fifo_fl;
  wire req_fifo_sl_nn0;
  wire req_fifo_wr_nn0;
  wire req_fifo_wr_nn1;
  wire [17:0]s_axil_araddr;
  wire s_axil_arvalid;
  wire [17:0]s_axil_awaddr;
  wire s_axil_awvalid;
  wire tar_row_nn1_reg;
  wire user_clk;
  wire [1:0]NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED;
  wire NLW_MemArray_reg_0_3_36_40_SPO_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair358" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__5 
       (.I0(\FifoCntrRd_reg_n_0_[0] ),
        .O(\FifoCntrRd[0]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9AA56565655)) 
    \FifoCntrRd[1]_i_1__5 
       (.I0(\FifoCntrRd_reg_n_0_[1] ),
        .I1(req_fifo_wr_nn1),
        .I2(req_fifo_fl),
        .I3(s_axil_awvalid),
        .I4(s_axil_arvalid),
        .I5(\FifoCntrRd_reg_n_0_[0] ),
        .O(\FifoCntrRd[1]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFF1000E)) 
    \FifoCntrRd[2]_i_1__6 
       (.I0(s_axil_arvalid),
        .I1(s_axil_awvalid),
        .I2(req_fifo_fl),
        .I3(req_fifo_wr_nn1),
        .I4(empty_ff_reg_2),
        .O(\FifoCntrRd[2]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair358" *) 
  LUT4 #(
    .INIT(16'hBD42)) 
    \FifoCntrRd[2]_i_2__0 
       (.I0(\FifoCntrRd[2]_i_3_n_0 ),
        .I1(\FifoCntrRd_reg_n_0_[0] ),
        .I2(\FifoCntrRd_reg_n_0_[1] ),
        .I3(\FifoCntrRd_reg_n_0_[2] ),
        .O(\FifoCntrRd[2]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair356" *) 
  LUT4 #(
    .INIT(16'hEEEF)) 
    \FifoCntrRd[2]_i_3 
       (.I0(req_fifo_wr_nn1),
        .I1(req_fifo_fl),
        .I2(s_axil_awvalid),
        .I3(s_axil_arvalid),
        .O(\FifoCntrRd[2]_i_3_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__6_n_0 ),
        .D(\FifoCntrRd[0]_i_1__5_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[0] ),
        .R(full_ff_reg_0));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__6_n_0 ),
        .D(\FifoCntrRd[1]_i_1__5_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[1] ),
        .R(full_ff_reg_0));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__6_n_0 ),
        .D(\FifoCntrRd[2]_i_2__0_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[2] ),
        .R(full_ff_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair357" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__5 
       (.I0(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9AA56565655)) 
    \FifoCntrWr[1]_i_1__5 
       (.I0(FifoCntrWr[1]),
        .I1(req_fifo_wr_nn1),
        .I2(req_fifo_fl),
        .I3(s_axil_awvalid),
        .I4(s_axil_arvalid),
        .I5(FifoCntrWr[0]),
        .O(\FifoCntrWr[1]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair357" *) 
  LUT4 #(
    .INIT(16'hA96A)) 
    \FifoCntrWr[2]_i_1__5 
       (.I0(FifoCntrWr[2]),
        .I1(FifoCntrWr[0]),
        .I2(FifoCntrWr[1]),
        .I3(\FifoCntrRd[2]_i_3_n_0 ),
        .O(\FifoCntrWr[2]_i_1__5_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__6_n_0 ),
        .D(\FifoCntrWr[0]_i_1__5_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(full_ff_reg_0));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__6_n_0 ),
        .D(\FifoCntrWr[1]_i_1__5_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(full_ff_reg_0));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__6_n_0 ),
        .D(\FifoCntrWr[2]_i_1__5_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(full_ff_reg_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "164" *) 
  (* RTL_RAM_NAME = "usr_axilt_slv/REQ_FIFO/MemArray_reg_0_3_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_3_0_5
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr_0}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr_0}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr_0}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr_1}),
        .DIA({MemArray_reg_0_3_0_5_i_2_n_0,MemArray_reg_0_3_0_5_i_3_n_0}),
        .DIB({MemArray_reg_0_3_0_5_i_4_n_0,MemArray_reg_0_3_0_5_i_5_n_0}),
        .DIC({MemArray_reg_0_3_0_5_i_6_n_0,MemArray_reg_0_3_0_5_i_7_n_0}),
        .DID({1'b0,1'b0}),
        .DOA(DataOut[1:0]),
        .DOB(DataOut[3:2]),
        .DOC(DataOut[5:4]),
        .DOD(NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(req_fifo_wr_nn0));
  LUT4 #(
    .INIT(16'h000E)) 
    MemArray_reg_0_3_0_5_i_1
       (.I0(s_axil_arvalid),
        .I1(s_axil_awvalid),
        .I2(req_fifo_fl),
        .I3(req_fifo_wr_nn1),
        .O(req_fifo_wr_nn0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_0_5_i_2
       (.I0(s_axil_awaddr[1]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[1]),
        .O(MemArray_reg_0_3_0_5_i_2_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_0_5_i_3
       (.I0(s_axil_awaddr[0]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[0]),
        .O(MemArray_reg_0_3_0_5_i_3_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_0_5_i_4
       (.I0(s_axil_awaddr[3]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[3]),
        .O(MemArray_reg_0_3_0_5_i_4_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_0_5_i_5
       (.I0(s_axil_awaddr[2]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[2]),
        .O(MemArray_reg_0_3_0_5_i_5_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_0_5_i_6
       (.I0(s_axil_awaddr[5]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[5]),
        .O(MemArray_reg_0_3_0_5_i_6_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_0_5_i_7
       (.I0(s_axil_awaddr[4]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[4]),
        .O(MemArray_reg_0_3_0_5_i_7_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "164" *) 
  (* RTL_RAM_NAME = "usr_axilt_slv/REQ_FIFO/MemArray_reg_0_3_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr_0}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr_0}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr_0}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr_1}),
        .DIA({MemArray_reg_0_3_12_17_i_1_n_0,MemArray_reg_0_3_12_17_i_2_n_0}),
        .DIB({MemArray_reg_0_3_12_17_i_3_n_0,MemArray_reg_0_3_12_17_i_4_n_0}),
        .DIC({MemArray_reg_0_3_12_17_i_5_n_0,MemArray_reg_0_3_12_17_i_6_n_0}),
        .DID({1'b0,1'b0}),
        .DOA(DataOut[13:12]),
        .DOB(DataOut[15:14]),
        .DOC({MemArray_reg_0_3_12_17_n_4,MemArray_reg_0_3_12_17_n_5}),
        .DOD(NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(req_fifo_wr_nn0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_12_17_i_1
       (.I0(s_axil_awaddr[13]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[13]),
        .O(MemArray_reg_0_3_12_17_i_1_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_12_17_i_2
       (.I0(s_axil_awaddr[12]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[12]),
        .O(MemArray_reg_0_3_12_17_i_2_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_12_17_i_3
       (.I0(s_axil_awaddr[15]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[15]),
        .O(MemArray_reg_0_3_12_17_i_3_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_12_17_i_4
       (.I0(s_axil_awaddr[14]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[14]),
        .O(MemArray_reg_0_3_12_17_i_4_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_12_17_i_5
       (.I0(s_axil_awaddr[17]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[17]),
        .O(MemArray_reg_0_3_12_17_i_5_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_12_17_i_6
       (.I0(s_axil_awaddr[16]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[16]),
        .O(MemArray_reg_0_3_12_17_i_6_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "164" *) 
  (* RTL_RAM_NAME = "dma_top/base/usr_axilt_slv/REQ_FIFO/MemArray_reg_0_3_36_40" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "40" *) 
  RAM32X1D MemArray_reg_0_3_36_40
       (.A0(WrPtr_1[0]),
        .A1(WrPtr_1[1]),
        .A2(1'b0),
        .A3(1'b0),
        .A4(1'b0),
        .D(req_fifo_sl_nn0),
        .DPO(req_fifo_dout),
        .DPRA0(RdPtr_0[0]),
        .DPRA1(RdPtr_0[1]),
        .DPRA2(1'b0),
        .DPRA3(1'b0),
        .DPRA4(1'b0),
        .SPO(NLW_MemArray_reg_0_3_36_40_SPO_UNCONNECTED),
        .WCLK(user_clk),
        .WE(req_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "164" *) 
  (* RTL_RAM_NAME = "usr_axilt_slv/REQ_FIFO/MemArray_reg_0_3_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr_0}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr_0}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr_0}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr_1}),
        .DIA({MemArray_reg_0_3_6_11_i_1__0_n_0,MemArray_reg_0_3_6_11_i_2_n_0}),
        .DIB({MemArray_reg_0_3_6_11_i_3_n_0,MemArray_reg_0_3_6_11_i_4_n_0}),
        .DIC({MemArray_reg_0_3_6_11_i_5_n_0,MemArray_reg_0_3_6_11_i_6_n_0}),
        .DID({1'b0,1'b0}),
        .DOA(DataOut[7:6]),
        .DOB(DataOut[9:8]),
        .DOC(DataOut[11:10]),
        .DOD(NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(req_fifo_wr_nn0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_6_11_i_1__0
       (.I0(s_axil_awaddr[7]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[7]),
        .O(MemArray_reg_0_3_6_11_i_1__0_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_6_11_i_2
       (.I0(s_axil_awaddr[6]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[6]),
        .O(MemArray_reg_0_3_6_11_i_2_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_6_11_i_3
       (.I0(s_axil_awaddr[9]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[9]),
        .O(MemArray_reg_0_3_6_11_i_3_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_6_11_i_4
       (.I0(s_axil_awaddr[8]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[8]),
        .O(MemArray_reg_0_3_6_11_i_4_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_6_11_i_5
       (.I0(s_axil_awaddr[11]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[11]),
        .O(MemArray_reg_0_3_6_11_i_5_n_0));
  LUT5 #(
    .INIT(32'hBFAA80AA)) 
    MemArray_reg_0_3_6_11_i_6
       (.I0(s_axil_awaddr[10]),
        .I1(s_axil_awvalid),
        .I2(arb_pri_nn1_0),
        .I3(s_axil_arvalid),
        .I4(s_axil_araddr[10]),
        .O(MemArray_reg_0_3_6_11_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair360" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \RdPtr[0]_i_1__7 
       (.I0(RdPtr_0[0]),
        .I1(empty_ff_reg_2),
        .O(RdPtr[0]));
  (* SOFT_HLUTNM = "soft_lutpair360" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \RdPtr[1]_i_1__8 
       (.I0(empty_ff_reg_2),
        .I1(RdPtr_0[0]),
        .I2(RdPtr_0[1]),
        .O(RdPtr[1]));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr[0]),
        .Q(RdPtr_0[0]),
        .R(full_ff_reg_0));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(RdPtr[1]),
        .Q(RdPtr_0[1]),
        .R(full_ff_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair356" *) 
  LUT5 #(
    .INIT(32'hFFF1000E)) 
    \WrPtr[0]_i_1__6 
       (.I0(s_axil_arvalid),
        .I1(s_axil_awvalid),
        .I2(req_fifo_fl),
        .I3(req_fifo_wr_nn1),
        .I4(WrPtr_1[0]),
        .O(WrPtr[0]));
  LUT6 #(
    .INIT(64'hFDFDFDFF02020200)) 
    \WrPtr[1]_i_1__6 
       (.I0(WrPtr_1[0]),
        .I1(req_fifo_wr_nn1),
        .I2(req_fifo_fl),
        .I3(s_axil_awvalid),
        .I4(s_axil_arvalid),
        .I5(WrPtr_1[1]),
        .O(WrPtr[1]));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr[0]),
        .Q(WrPtr_1[0]),
        .R(full_ff_reg_0));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(WrPtr[1]),
        .Q(WrPtr_1[1]),
        .R(full_ff_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair359" *) 
  LUT3 #(
    .INIT(8'h15)) 
    \arb_win_nn1[0]_i_2 
       (.I0(empty_ff),
        .I1(req_fifo_dout),
        .I2(dat_fifo_ep),
        .O(arb_win_nn14__1));
  LUT6 #(
    .INIT(64'hFFFFFDDD02220000)) 
    \arb_win_nn1[1]_i_1 
       (.I0(arb_pri_nn1[0]),
        .I1(empty_ff),
        .I2(req_fifo_dout),
        .I3(dat_fifo_ep),
        .I4(arb_pri_nn1[1]),
        .I5(\arb_win_nn1_reg[1] ),
        .O(\arb_pri_nn1_reg[0] ));
  LUT5 #(
    .INIT(32'hCCCCCCEF)) 
    empty_ff_i_1__6
       (.I0(empty_ff_reg_2),
        .I1(empty_ff_reg_3),
        .I2(\FifoCntrRd_reg_n_0_[0] ),
        .I3(\FifoCntrRd_reg_n_0_[1] ),
        .I4(\FifoCntrRd_reg_n_0_[2] ),
        .O(empty_ff_i_1__6_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__6_n_0),
        .Q(empty_ff),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFF400340)) 
    full_ff_i_1__4
       (.I0(\FifoCntrRd[2]_i_3_n_0 ),
        .I1(FifoCntrWr[1]),
        .I2(FifoCntrWr[0]),
        .I3(FifoCntrWr[2]),
        .I4(req_fifo_fl),
        .O(full_ff_i_1__4_n_0));
  FDRE full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(full_ff_i_1__4_n_0),
        .Q(req_fifo_fl),
        .R(full_ff_reg_0));
  LUT3 #(
    .INIT(8'h8F)) 
    req_fifo_sl_nn1_i_1
       (.I0(s_axil_awvalid),
        .I1(arb_pri_nn1_0),
        .I2(s_axil_arvalid),
        .O(req_fifo_sl_nn0));
  (* SOFT_HLUTNM = "soft_lutpair359" *) 
  LUT3 #(
    .INIT(8'h04)) 
    req_wvld_nn1_i_1
       (.I0(dat_fifo_ep),
        .I1(req_fifo_dout),
        .I2(empty_ff),
        .O(empty_ff_reg_0));
  LUT6 #(
    .INIT(64'hFFFF040004000400)) 
    tar_row_nn1_i_1
       (.I0(dat_fifo_ep),
        .I1(req_fifo_dout),
        .I2(empty_ff),
        .I3(Q[0]),
        .I4(tar_row_nn1_reg),
        .I5(Q[1]),
        .O(empty_ff_reg_1));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFO" *) 
module xdma_0_xdma_v4_1_29_GenericFIFO__parameterized3_51
   (full_ff_reg_0,
    empty_ff_reg_0,
    \arb_pri_nn1_reg[0] ,
    empty_ff_reg_1,
    \arb_win_nn2_reg[1] ,
    \arb_win_nn2_reg[1]_0 ,
    \arb_win_nn2_reg[1]_1 ,
    \arb_win_nn2_reg[1]_2 ,
    \arb_win_nn2_reg[1]_3 ,
    \arb_win_nn2_reg[1]_4 ,
    \arb_win_nn2_reg[1]_5 ,
    \arb_win_nn2_reg[1]_6 ,
    \arb_win_nn2_reg[1]_7 ,
    \userclk1_i1.usrclk1_i1 ,
    \arb_win_nn2_reg[1]_8 ,
    \arb_win_nn2_reg[1]_9 ,
    \arb_win_nn2_reg[1]_10 ,
    \arb_win_nn2_reg[1]_11 ,
    \arb_win_nn2_reg[1]_12 ,
    \arb_win_nn2_reg[1]_13 ,
    \arb_win_nn2_reg[1]_14 ,
    full_ff_reg_1,
    user_clk,
    req_fifo_sl_nn0,
    req_fifo_wr_nn0,
    dat_fifo_ep,
    \FifoCntrWr_reg[1]_0 ,
    s_axilp_awvalid,
    s_axilp_arvalid,
    empty_ff_reg_2,
    empty_ff_reg_3,
    arb_pri_nn1_0,
    arb_win_nn14__1,
    Q,
    \tar_adr_nn1_reg[15] ,
    DataIn);
  output full_ff_reg_0;
  output empty_ff_reg_0;
  output [0:0]\arb_pri_nn1_reg[0] ;
  output [0:0]empty_ff_reg_1;
  output \arb_win_nn2_reg[1] ;
  output \arb_win_nn2_reg[1]_0 ;
  output \arb_win_nn2_reg[1]_1 ;
  output \arb_win_nn2_reg[1]_2 ;
  output \arb_win_nn2_reg[1]_3 ;
  output \arb_win_nn2_reg[1]_4 ;
  output \arb_win_nn2_reg[1]_5 ;
  output \arb_win_nn2_reg[1]_6 ;
  output \arb_win_nn2_reg[1]_7 ;
  output [6:0]\userclk1_i1.usrclk1_i1 ;
  output \arb_win_nn2_reg[1]_8 ;
  output \arb_win_nn2_reg[1]_9 ;
  output \arb_win_nn2_reg[1]_10 ;
  output \arb_win_nn2_reg[1]_11 ;
  output \arb_win_nn2_reg[1]_12 ;
  output \arb_win_nn2_reg[1]_13 ;
  output \arb_win_nn2_reg[1]_14 ;
  input full_ff_reg_1;
  input user_clk;
  input req_fifo_sl_nn0;
  input req_fifo_wr_nn0;
  input dat_fifo_ep;
  input \FifoCntrWr_reg[1]_0 ;
  input s_axilp_awvalid;
  input s_axilp_arvalid;
  input [0:0]empty_ff_reg_2;
  input empty_ff_reg_3;
  input [1:0]arb_pri_nn1_0;
  input [0:0]arb_win_nn14__1;
  input [0:0]Q;
  input [15:0]\tar_adr_nn1_reg[15] ;
  input [17:0]DataIn;

  wire [17:0]DataIn;
  wire [9:0]DataOut0_out;
  wire \FifoCntrRd[0]_i_1__6_n_0 ;
  wire \FifoCntrRd[1]_i_1__6_n_0 ;
  wire \FifoCntrRd[2]_i_1__7_n_0 ;
  wire \FifoCntrRd[2]_i_2__2_n_0 ;
  wire \FifoCntrRd[2]_i_3__0_n_0 ;
  wire \FifoCntrRd_reg_n_0_[0] ;
  wire \FifoCntrRd_reg_n_0_[1] ;
  wire \FifoCntrRd_reg_n_0_[2] ;
  wire [2:0]FifoCntrWr;
  wire \FifoCntrWr[0]_i_1__6_n_0 ;
  wire \FifoCntrWr[1]_i_1__6_n_0 ;
  wire \FifoCntrWr[2]_i_1__6_n_0 ;
  wire \FifoCntrWr_reg[1]_0 ;
  wire MemArray_reg_0_3_12_17_n_4;
  wire MemArray_reg_0_3_12_17_n_5;
  wire [0:0]Q;
  wire [1:0]RdPtr;
  wire \RdPtr[0]_i_1__8_n_0 ;
  wire \RdPtr[1]_i_1__9_n_0 ;
  wire [1:0]WrPtr;
  wire \WrPtr[0]_i_1__8_n_0 ;
  wire \WrPtr[1]_i_1__8_n_0 ;
  wire [1:0]arb_pri_nn1_0;
  wire [0:0]\arb_pri_nn1_reg[0] ;
  wire [0:0]arb_win_nn14__1;
  wire \arb_win_nn2_reg[1] ;
  wire \arb_win_nn2_reg[1]_0 ;
  wire \arb_win_nn2_reg[1]_1 ;
  wire \arb_win_nn2_reg[1]_10 ;
  wire \arb_win_nn2_reg[1]_11 ;
  wire \arb_win_nn2_reg[1]_12 ;
  wire \arb_win_nn2_reg[1]_13 ;
  wire \arb_win_nn2_reg[1]_14 ;
  wire \arb_win_nn2_reg[1]_2 ;
  wire \arb_win_nn2_reg[1]_3 ;
  wire \arb_win_nn2_reg[1]_4 ;
  wire \arb_win_nn2_reg[1]_5 ;
  wire \arb_win_nn2_reg[1]_6 ;
  wire \arb_win_nn2_reg[1]_7 ;
  wire \arb_win_nn2_reg[1]_8 ;
  wire \arb_win_nn2_reg[1]_9 ;
  wire dat_fifo_ep;
  wire empty_ff_i_1__7_n_0;
  wire empty_ff_reg_0;
  wire [0:0]empty_ff_reg_1;
  wire [0:0]empty_ff_reg_2;
  wire empty_ff_reg_3;
  wire empty_ff_reg_n_0;
  wire full_ff_i_1__5_n_0;
  wire full_ff_reg_0;
  wire full_ff_reg_1;
  wire [40:40]req_fifo_dout;
  wire req_fifo_sl_nn0;
  wire req_fifo_wr_nn0;
  wire s_axilp_arvalid;
  wire s_axilp_awvalid;
  wire [15:0]\tar_adr_nn1_reg[15] ;
  wire user_clk;
  wire [6:0]\userclk1_i1.usrclk1_i1 ;
  wire [1:0]NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED;
  wire NLW_MemArray_reg_0_3_36_40_SPO_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair341" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrRd[0]_i_1__6 
       (.I0(\FifoCntrRd_reg_n_0_[0] ),
        .O(\FifoCntrRd[0]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9AA56565655)) 
    \FifoCntrRd[1]_i_1__6 
       (.I0(\FifoCntrRd_reg_n_0_[1] ),
        .I1(\FifoCntrWr_reg[1]_0 ),
        .I2(full_ff_reg_0),
        .I3(s_axilp_awvalid),
        .I4(s_axilp_arvalid),
        .I5(\FifoCntrRd_reg_n_0_[0] ),
        .O(\FifoCntrRd[1]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFF1000E)) 
    \FifoCntrRd[2]_i_1__7 
       (.I0(s_axilp_arvalid),
        .I1(s_axilp_awvalid),
        .I2(full_ff_reg_0),
        .I3(\FifoCntrWr_reg[1]_0 ),
        .I4(empty_ff_reg_2),
        .O(\FifoCntrRd[2]_i_1__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair341" *) 
  LUT4 #(
    .INIT(16'hBD42)) 
    \FifoCntrRd[2]_i_2__2 
       (.I0(\FifoCntrRd[2]_i_3__0_n_0 ),
        .I1(\FifoCntrRd_reg_n_0_[0] ),
        .I2(\FifoCntrRd_reg_n_0_[1] ),
        .I3(\FifoCntrRd_reg_n_0_[2] ),
        .O(\FifoCntrRd[2]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair339" *) 
  LUT4 #(
    .INIT(16'hEEEF)) 
    \FifoCntrRd[2]_i_3__0 
       (.I0(\FifoCntrWr_reg[1]_0 ),
        .I1(full_ff_reg_0),
        .I2(s_axilp_awvalid),
        .I3(s_axilp_arvalid),
        .O(\FifoCntrRd[2]_i_3__0_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__7_n_0 ),
        .D(\FifoCntrRd[0]_i_1__6_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[0] ),
        .R(full_ff_reg_1));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__7_n_0 ),
        .D(\FifoCntrRd[1]_i_1__6_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[1] ),
        .R(full_ff_reg_1));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__7_n_0 ),
        .D(\FifoCntrRd[2]_i_2__2_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[2] ),
        .R(full_ff_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair340" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \FifoCntrWr[0]_i_1__6 
       (.I0(FifoCntrWr[0]),
        .O(\FifoCntrWr[0]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9AA56565655)) 
    \FifoCntrWr[1]_i_1__6 
       (.I0(FifoCntrWr[1]),
        .I1(\FifoCntrWr_reg[1]_0 ),
        .I2(full_ff_reg_0),
        .I3(s_axilp_awvalid),
        .I4(s_axilp_arvalid),
        .I5(FifoCntrWr[0]),
        .O(\FifoCntrWr[1]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair340" *) 
  LUT4 #(
    .INIT(16'hA96A)) 
    \FifoCntrWr[2]_i_1__6 
       (.I0(FifoCntrWr[2]),
        .I1(FifoCntrWr[0]),
        .I2(FifoCntrWr[1]),
        .I3(\FifoCntrRd[2]_i_3__0_n_0 ),
        .O(\FifoCntrWr[2]_i_1__6_n_0 ));
  FDRE \FifoCntrWr_reg[0] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__7_n_0 ),
        .D(\FifoCntrWr[0]_i_1__6_n_0 ),
        .Q(FifoCntrWr[0]),
        .R(full_ff_reg_1));
  FDRE \FifoCntrWr_reg[1] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__7_n_0 ),
        .D(\FifoCntrWr[1]_i_1__6_n_0 ),
        .Q(FifoCntrWr[1]),
        .R(full_ff_reg_1));
  FDRE \FifoCntrWr_reg[2] 
       (.C(user_clk),
        .CE(\FifoCntrRd[2]_i_1__7_n_0 ),
        .D(\FifoCntrWr[2]_i_1__6_n_0 ),
        .Q(FifoCntrWr[2]),
        .R(full_ff_reg_1));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "164" *) 
  (* RTL_RAM_NAME = "cq_axilt_slv/REQ_FIFO/MemArray_reg_0_3_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_3_0_5
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[1:0]),
        .DIB(DataIn[3:2]),
        .DIC(DataIn[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut0_out[1:0]),
        .DOB(DataOut0_out[3:2]),
        .DOC(DataOut0_out[5:4]),
        .DOD(NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(req_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "164" *) 
  (* RTL_RAM_NAME = "cq_axilt_slv/REQ_FIFO/MemArray_reg_0_3_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[13:12]),
        .DIB(DataIn[15:14]),
        .DIC(DataIn[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [4:3]),
        .DOB(\userclk1_i1.usrclk1_i1 [6:5]),
        .DOC({MemArray_reg_0_3_12_17_n_4,MemArray_reg_0_3_12_17_n_5}),
        .DOD(NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(req_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "164" *) 
  (* RTL_RAM_NAME = "dma_top/base/cq_axilt_slv/REQ_FIFO/MemArray_reg_0_3_36_40" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "40" *) 
  RAM32X1D MemArray_reg_0_3_36_40
       (.A0(WrPtr[0]),
        .A1(WrPtr[1]),
        .A2(1'b0),
        .A3(1'b0),
        .A4(1'b0),
        .D(req_fifo_sl_nn0),
        .DPO(req_fifo_dout),
        .DPRA0(RdPtr[0]),
        .DPRA1(RdPtr[1]),
        .DPRA2(1'b0),
        .DPRA3(1'b0),
        .DPRA4(1'b0),
        .SPO(NLW_MemArray_reg_0_3_36_40_SPO_UNCONNECTED),
        .WCLK(user_clk),
        .WE(req_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "164" *) 
  (* RTL_RAM_NAME = "cq_axilt_slv/REQ_FIFO/MemArray_reg_0_3_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(DataIn[7:6]),
        .DIB(DataIn[9:8]),
        .DIC(DataIn[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut0_out[7:6]),
        .DOB({DataOut0_out[9],\userclk1_i1.usrclk1_i1 [0]}),
        .DOC(\userclk1_i1.usrclk1_i1 [2:1]),
        .DOD(NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(req_fifo_wr_nn0));
  (* SOFT_HLUTNM = "soft_lutpair351" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \RdPtr[0]_i_1__8 
       (.I0(RdPtr[0]),
        .I1(empty_ff_reg_2),
        .O(\RdPtr[0]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair351" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \RdPtr[1]_i_1__9 
       (.I0(empty_ff_reg_2),
        .I1(RdPtr[0]),
        .I2(RdPtr[1]),
        .O(\RdPtr[1]_i_1__9_n_0 ));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1__8_n_0 ),
        .Q(RdPtr[0]),
        .R(full_ff_reg_1));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[1]_i_1__9_n_0 ),
        .Q(RdPtr[1]),
        .R(full_ff_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair339" *) 
  LUT5 #(
    .INIT(32'hFFF1000E)) 
    \WrPtr[0]_i_1__8 
       (.I0(s_axilp_arvalid),
        .I1(s_axilp_awvalid),
        .I2(full_ff_reg_0),
        .I3(\FifoCntrWr_reg[1]_0 ),
        .I4(WrPtr[0]),
        .O(\WrPtr[0]_i_1__8_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFF02020200)) 
    \WrPtr[1]_i_1__8 
       (.I0(WrPtr[0]),
        .I1(\FifoCntrWr_reg[1]_0 ),
        .I2(full_ff_reg_0),
        .I3(s_axilp_awvalid),
        .I4(s_axilp_arvalid),
        .I5(WrPtr[1]),
        .O(\WrPtr[1]_i_1__8_n_0 ));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[0]_i_1__8_n_0 ),
        .Q(WrPtr[0]),
        .R(full_ff_reg_1));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[1]_i_1__8_n_0 ),
        .Q(WrPtr[1]),
        .R(full_ff_reg_1));
  LUT6 #(
    .INIT(64'hCCCCCCACCCACCCAC)) 
    \arb_win_nn1[0]_i_1 
       (.I0(arb_pri_nn1_0[0]),
        .I1(arb_win_nn14__1),
        .I2(arb_pri_nn1_0[1]),
        .I3(empty_ff_reg_n_0),
        .I4(req_fifo_dout),
        .I5(dat_fifo_ep),
        .O(\arb_pri_nn1_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair342" *) 
  LUT3 #(
    .INIT(8'h15)) 
    \arb_win_nn1[1]_i_2 
       (.I0(empty_ff_reg_n_0),
        .I1(req_fifo_dout),
        .I2(dat_fifo_ep),
        .O(empty_ff_reg_1));
  LUT5 #(
    .INIT(32'hCCCCCCEF)) 
    empty_ff_i_1__7
       (.I0(empty_ff_reg_2),
        .I1(empty_ff_reg_3),
        .I2(\FifoCntrRd_reg_n_0_[0] ),
        .I3(\FifoCntrRd_reg_n_0_[1] ),
        .I4(\FifoCntrRd_reg_n_0_[2] ),
        .O(empty_ff_i_1__7_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__7_n_0),
        .Q(empty_ff_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFF400340)) 
    full_ff_i_1__5
       (.I0(\FifoCntrRd[2]_i_3__0_n_0 ),
        .I1(FifoCntrWr[1]),
        .I2(FifoCntrWr[0]),
        .I3(FifoCntrWr[2]),
        .I4(full_ff_reg_0),
        .O(full_ff_i_1__5_n_0));
  FDRE full_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(full_ff_i_1__5_n_0),
        .Q(full_ff_reg_0),
        .R(full_ff_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair342" *) 
  LUT3 #(
    .INIT(8'h04)) 
    req_wvld_nn1_i_1__0
       (.I0(dat_fifo_ep),
        .I1(req_fifo_dout),
        .I2(empty_ff_reg_n_0),
        .O(empty_ff_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair345" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[0]_i_1 
       (.I0(DataOut0_out[0]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [0]),
        .O(\arb_win_nn2_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair347" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[10]_i_1 
       (.I0(\userclk1_i1.usrclk1_i1 [1]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [10]),
        .O(\arb_win_nn2_reg[1]_9 ));
  (* SOFT_HLUTNM = "soft_lutpair350" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[11]_i_1 
       (.I0(\userclk1_i1.usrclk1_i1 [2]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [11]),
        .O(\arb_win_nn2_reg[1]_10 ));
  (* SOFT_HLUTNM = "soft_lutpair346" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[12]_i_1 
       (.I0(\userclk1_i1.usrclk1_i1 [3]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [12]),
        .O(\arb_win_nn2_reg[1]_11 ));
  (* SOFT_HLUTNM = "soft_lutpair350" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[13]_i_1 
       (.I0(\userclk1_i1.usrclk1_i1 [4]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [13]),
        .O(\arb_win_nn2_reg[1]_12 ));
  (* SOFT_HLUTNM = "soft_lutpair344" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[14]_i_1 
       (.I0(\userclk1_i1.usrclk1_i1 [5]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [14]),
        .O(\arb_win_nn2_reg[1]_13 ));
  (* SOFT_HLUTNM = "soft_lutpair348" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[15]_i_1 
       (.I0(\userclk1_i1.usrclk1_i1 [6]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [15]),
        .O(\arb_win_nn2_reg[1]_14 ));
  (* SOFT_HLUTNM = "soft_lutpair348" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[1]_i_1 
       (.I0(DataOut0_out[1]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [1]),
        .O(\arb_win_nn2_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair343" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[2]_i_1 
       (.I0(DataOut0_out[2]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [2]),
        .O(\arb_win_nn2_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair347" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[3]_i_1 
       (.I0(DataOut0_out[3]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [3]),
        .O(\arb_win_nn2_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair346" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[4]_i_1 
       (.I0(DataOut0_out[4]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [4]),
        .O(\arb_win_nn2_reg[1]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair349" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[5]_i_1 
       (.I0(DataOut0_out[5]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [5]),
        .O(\arb_win_nn2_reg[1]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair345" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[6]_i_1 
       (.I0(DataOut0_out[6]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [6]),
        .O(\arb_win_nn2_reg[1]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair349" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[7]_i_1 
       (.I0(DataOut0_out[7]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [7]),
        .O(\arb_win_nn2_reg[1]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair344" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[8]_i_1 
       (.I0(\userclk1_i1.usrclk1_i1 [0]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [8]),
        .O(\arb_win_nn2_reg[1]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair343" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_adr_nn1[9]_i_1 
       (.I0(DataOut0_out[9]),
        .I1(Q),
        .I2(\tar_adr_nn1_reg[15] [9]),
        .O(\arb_win_nn2_reg[1]_8 ));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFO" *) 
module xdma_0_xdma_v4_1_29_GenericFIFO__parameterized4
   (dat_fifo_ep,
    dat_fifo_wr_nn0,
    \userclk1_i1.usrclk1_i1 ,
    user_clk,
    req_wvld_nn1,
    empty_ff_reg_0,
    empty_ff_reg_1,
    s_axi_wvld_nn1,
    dat_exp_nn1,
    \tar_dat_nn1_reg[31] ,
    \FifoCntrRd_reg[0]_0 );
  output dat_fifo_ep;
  output dat_fifo_wr_nn0;
  output [35:0]\userclk1_i1.usrclk1_i1 ;
  input user_clk;
  input req_wvld_nn1;
  input [0:0]empty_ff_reg_0;
  input empty_ff_reg_1;
  input s_axi_wvld_nn1;
  input [2:0]dat_exp_nn1;
  input [35:0]\tar_dat_nn1_reg[31] ;
  input \FifoCntrRd_reg[0]_0 ;

  wire \FifoCntrRd[0]_i_1_n_0 ;
  wire \FifoCntrRd[1]_i_1_n_0 ;
  wire \FifoCntrRd[2]_i_1_n_0 ;
  wire \FifoCntrRd[2]_i_2__1_n_0 ;
  wire \FifoCntrRd_reg[0]_0 ;
  wire \FifoCntrRd_reg_n_0_[0] ;
  wire \FifoCntrRd_reg_n_0_[1] ;
  wire \FifoCntrRd_reg_n_0_[2] ;
  wire [1:0]RdPtr;
  wire \RdPtr[0]_i_1__5_n_0 ;
  wire \RdPtr[1]_i_1__6_n_0 ;
  wire [1:0]WrPtr;
  wire \WrPtr[0]_i_1__7_n_0 ;
  wire \WrPtr[1]_i_1__7_n_0 ;
  wire [2:0]dat_exp_nn1;
  wire dat_fifo_ep;
  wire dat_fifo_wr_nn0;
  wire empty_ff_i_1__8_n_0;
  wire [0:0]empty_ff_reg_0;
  wire empty_ff_reg_1;
  wire req_wvld_nn1;
  wire s_axi_wvld_nn1;
  wire [35:0]\tar_dat_nn1_reg[31] ;
  wire user_clk;
  wire [35:0]\userclk1_i1.usrclk1_i1 ;
  wire [1:0]NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair353" *) 
  LUT4 #(
    .INIT(16'h7887)) 
    \FifoCntrRd[0]_i_1 
       (.I0(empty_ff_reg_0),
        .I1(req_wvld_nn1),
        .I2(\FifoCntrRd[2]_i_2__1_n_0 ),
        .I3(\FifoCntrRd_reg_n_0_[0] ),
        .O(\FifoCntrRd[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair353" *) 
  LUT5 #(
    .INIT(32'hBFD5402A)) 
    \FifoCntrRd[1]_i_1 
       (.I0(\FifoCntrRd_reg_n_0_[0] ),
        .I1(empty_ff_reg_0),
        .I2(req_wvld_nn1),
        .I3(\FifoCntrRd[2]_i_2__1_n_0 ),
        .I4(\FifoCntrRd_reg_n_0_[1] ),
        .O(\FifoCntrRd[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEFFFF77710000888)) 
    \FifoCntrRd[2]_i_1 
       (.I0(\FifoCntrRd_reg_n_0_[1] ),
        .I1(\FifoCntrRd_reg_n_0_[0] ),
        .I2(empty_ff_reg_0),
        .I3(req_wvld_nn1),
        .I4(\FifoCntrRd[2]_i_2__1_n_0 ),
        .I5(\FifoCntrRd_reg_n_0_[2] ),
        .O(\FifoCntrRd[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair354" *) 
  LUT4 #(
    .INIT(16'h01FF)) 
    \FifoCntrRd[2]_i_2__1 
       (.I0(dat_exp_nn1[2]),
        .I1(dat_exp_nn1[0]),
        .I2(dat_exp_nn1[1]),
        .I3(s_axi_wvld_nn1),
        .O(\FifoCntrRd[2]_i_2__1_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[0]_i_1_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[0] ),
        .R(\FifoCntrRd_reg[0]_0 ));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[1]_i_1_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[1] ),
        .R(\FifoCntrRd_reg[0]_0 ));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[2]_i_1_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[2] ),
        .R(\FifoCntrRd_reg[0]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "usr_axilt_slv/DAT_FIFO/MemArray_reg_0_3_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_3_0_5
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\tar_dat_nn1_reg[31] [1:0]),
        .DIB(\tar_dat_nn1_reg[31] [3:2]),
        .DIC(\tar_dat_nn1_reg[31] [5:4]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [1:0]),
        .DOB(\userclk1_i1.usrclk1_i1 [3:2]),
        .DOC(\userclk1_i1.usrclk1_i1 [5:4]),
        .DOD(NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "usr_axilt_slv/DAT_FIFO/MemArray_reg_0_3_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\tar_dat_nn1_reg[31] [13:12]),
        .DIB(\tar_dat_nn1_reg[31] [15:14]),
        .DIC(\tar_dat_nn1_reg[31] [17:16]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [13:12]),
        .DOB(\userclk1_i1.usrclk1_i1 [15:14]),
        .DOC(\userclk1_i1.usrclk1_i1 [17:16]),
        .DOD(NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "usr_axilt_slv/DAT_FIFO/MemArray_reg_0_3_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\tar_dat_nn1_reg[31] [19:18]),
        .DIB(\tar_dat_nn1_reg[31] [21:20]),
        .DIC(\tar_dat_nn1_reg[31] [23:22]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [19:18]),
        .DOB(\userclk1_i1.usrclk1_i1 [21:20]),
        .DOC(\userclk1_i1.usrclk1_i1 [23:22]),
        .DOD(NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "usr_axilt_slv/DAT_FIFO/MemArray_reg_0_3_24_29" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M MemArray_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\tar_dat_nn1_reg[31] [25:24]),
        .DIB(\tar_dat_nn1_reg[31] [27:26]),
        .DIC(\tar_dat_nn1_reg[31] [29:28]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [25:24]),
        .DOB(\userclk1_i1.usrclk1_i1 [27:26]),
        .DOC(\userclk1_i1.usrclk1_i1 [29:28]),
        .DOD(NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "usr_axilt_slv/DAT_FIFO/MemArray_reg_0_3_30_35" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M MemArray_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\tar_dat_nn1_reg[31] [31:30]),
        .DIB(\tar_dat_nn1_reg[31] [33:32]),
        .DIC(\tar_dat_nn1_reg[31] [35:34]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [31:30]),
        .DOB(\userclk1_i1.usrclk1_i1 [33:32]),
        .DOC(\userclk1_i1.usrclk1_i1 [35:34]),
        .DOD(NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "usr_axilt_slv/DAT_FIFO/MemArray_reg_0_3_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(\tar_dat_nn1_reg[31] [7:6]),
        .DIB(\tar_dat_nn1_reg[31] [9:8]),
        .DIC(\tar_dat_nn1_reg[31] [11:10]),
        .DID({1'b0,1'b0}),
        .DOA(\userclk1_i1.usrclk1_i1 [7:6]),
        .DOB(\userclk1_i1.usrclk1_i1 [9:8]),
        .DOC(\userclk1_i1.usrclk1_i1 [11:10]),
        .DOD(NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  (* SOFT_HLUTNM = "soft_lutpair355" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \RdPtr[0]_i_1__5 
       (.I0(empty_ff_reg_0),
        .I1(req_wvld_nn1),
        .I2(RdPtr[0]),
        .O(\RdPtr[0]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair355" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \RdPtr[1]_i_1__6 
       (.I0(RdPtr[0]),
        .I1(req_wvld_nn1),
        .I2(empty_ff_reg_0),
        .I3(RdPtr[1]),
        .O(\RdPtr[1]_i_1__6_n_0 ));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1__5_n_0 ),
        .Q(RdPtr[0]),
        .R(\FifoCntrRd_reg[0]_0 ));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[1]_i_1__6_n_0 ),
        .Q(RdPtr[1]),
        .R(\FifoCntrRd_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair354" *) 
  LUT5 #(
    .INIT(32'h5557AAA8)) 
    \WrPtr[0]_i_1__7 
       (.I0(s_axi_wvld_nn1),
        .I1(dat_exp_nn1[1]),
        .I2(dat_exp_nn1[0]),
        .I3(dat_exp_nn1[2]),
        .I4(WrPtr[0]),
        .O(\WrPtr[0]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'h5557FFFFAAA80000)) 
    \WrPtr[1]_i_1__7 
       (.I0(WrPtr[0]),
        .I1(dat_exp_nn1[2]),
        .I2(dat_exp_nn1[0]),
        .I3(dat_exp_nn1[1]),
        .I4(s_axi_wvld_nn1),
        .I5(WrPtr[1]),
        .O(\WrPtr[1]_i_1__7_n_0 ));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[0]_i_1__7_n_0 ),
        .Q(WrPtr[0]),
        .R(\FifoCntrRd_reg[0]_0 ));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[1]_i_1__7_n_0 ),
        .Q(WrPtr[1]),
        .R(\FifoCntrRd_reg[0]_0 ));
  LUT4 #(
    .INIT(16'hAAA8)) 
    dat_fifo_wr_nn1_i_1
       (.I0(s_axi_wvld_nn1),
        .I1(dat_exp_nn1[1]),
        .I2(dat_exp_nn1[0]),
        .I3(dat_exp_nn1[2]),
        .O(dat_fifo_wr_nn0));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000008F)) 
    empty_ff_i_1__8
       (.I0(req_wvld_nn1),
        .I1(empty_ff_reg_0),
        .I2(\FifoCntrRd_reg_n_0_[0] ),
        .I3(\FifoCntrRd_reg_n_0_[1] ),
        .I4(\FifoCntrRd_reg_n_0_[2] ),
        .I5(empty_ff_reg_1),
        .O(empty_ff_i_1__8_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__8_n_0),
        .Q(dat_fifo_ep),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xdma_v4_1_29_GenericFIFO" *) 
module xdma_0_xdma_v4_1_29_GenericFIFO__parameterized4_50
   (dat_fifo_ep,
    dat_fifo_wr_nn0,
    \arb_win_nn2_reg[1] ,
    \arb_win_nn2_reg[1]_0 ,
    user_clk,
    req_wvld_nn1,
    empty_ff_reg_0,
    empty_ff_reg_1,
    s_axi_wvld_nn1,
    \WrPtr_reg[0]_0 ,
    \WrPtr_reg[0]_1 ,
    \WrPtr_reg[0]_2 ,
    Q,
    DataOut,
    I140,
    \FifoCntrRd_reg[0]_0 );
  output dat_fifo_ep;
  output dat_fifo_wr_nn0;
  output [3:0]\arb_win_nn2_reg[1] ;
  output [31:0]\arb_win_nn2_reg[1]_0 ;
  input user_clk;
  input req_wvld_nn1;
  input [0:0]empty_ff_reg_0;
  input empty_ff_reg_1;
  input s_axi_wvld_nn1;
  input \WrPtr_reg[0]_0 ;
  input \WrPtr_reg[0]_1 ;
  input \WrPtr_reg[0]_2 ;
  input [0:0]Q;
  input [35:0]DataOut;
  input [35:0]I140;
  input \FifoCntrRd_reg[0]_0 ;

  wire [35:0]DataOut;
  wire [31:0]DataOut0_out__0;
  wire \FifoCntrRd[0]_i_1_n_0 ;
  wire \FifoCntrRd[1]_i_1_n_0 ;
  wire \FifoCntrRd[2]_i_1_n_0 ;
  wire \FifoCntrRd[2]_i_2__3_n_0 ;
  wire \FifoCntrRd_reg[0]_0 ;
  wire \FifoCntrRd_reg_n_0_[0] ;
  wire \FifoCntrRd_reg_n_0_[1] ;
  wire \FifoCntrRd_reg_n_0_[2] ;
  wire [35:0]I140;
  wire [0:0]Q;
  wire [1:0]RdPtr;
  wire \RdPtr[0]_i_1__6_n_0 ;
  wire \RdPtr[1]_i_1__7_n_0 ;
  wire [1:0]WrPtr;
  wire \WrPtr[0]_i_1__9_n_0 ;
  wire \WrPtr[1]_i_1__9_n_0 ;
  wire \WrPtr_reg[0]_0 ;
  wire \WrPtr_reg[0]_1 ;
  wire \WrPtr_reg[0]_2 ;
  wire [3:0]\arb_win_nn2_reg[1] ;
  wire [31:0]\arb_win_nn2_reg[1]_0 ;
  wire dat_fifo_ep;
  wire dat_fifo_wr_nn0;
  wire empty_ff_i_1__9_n_0;
  wire [0:0]empty_ff_reg_0;
  wire empty_ff_reg_1;
  wire req_wvld_nn1;
  wire s_axi_wvld_nn1;
  wire [3:0]\tar_cq_be[1]_7 ;
  wire user_clk;
  wire [1:0]NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair318" *) 
  LUT4 #(
    .INIT(16'h7887)) 
    \FifoCntrRd[0]_i_1 
       (.I0(empty_ff_reg_0),
        .I1(req_wvld_nn1),
        .I2(\FifoCntrRd[2]_i_2__3_n_0 ),
        .I3(\FifoCntrRd_reg_n_0_[0] ),
        .O(\FifoCntrRd[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair318" *) 
  LUT5 #(
    .INIT(32'hBFD5402A)) 
    \FifoCntrRd[1]_i_1 
       (.I0(\FifoCntrRd_reg_n_0_[0] ),
        .I1(empty_ff_reg_0),
        .I2(req_wvld_nn1),
        .I3(\FifoCntrRd[2]_i_2__3_n_0 ),
        .I4(\FifoCntrRd_reg_n_0_[1] ),
        .O(\FifoCntrRd[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEFFFF77710000888)) 
    \FifoCntrRd[2]_i_1 
       (.I0(\FifoCntrRd_reg_n_0_[1] ),
        .I1(\FifoCntrRd_reg_n_0_[0] ),
        .I2(empty_ff_reg_0),
        .I3(req_wvld_nn1),
        .I4(\FifoCntrRd[2]_i_2__3_n_0 ),
        .I5(\FifoCntrRd_reg_n_0_[2] ),
        .O(\FifoCntrRd[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair319" *) 
  LUT4 #(
    .INIT(16'h01FF)) 
    \FifoCntrRd[2]_i_2__3 
       (.I0(\WrPtr_reg[0]_2 ),
        .I1(\WrPtr_reg[0]_1 ),
        .I2(\WrPtr_reg[0]_0 ),
        .I3(s_axi_wvld_nn1),
        .O(\FifoCntrRd[2]_i_2__3_n_0 ));
  FDRE \FifoCntrRd_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[0]_i_1_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[0] ),
        .R(\FifoCntrRd_reg[0]_0 ));
  FDRE \FifoCntrRd_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[1]_i_1_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[1] ),
        .R(\FifoCntrRd_reg[0]_0 ));
  FDRE \FifoCntrRd_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\FifoCntrRd[2]_i_1_n_0 ),
        .Q(\FifoCntrRd_reg_n_0_[2] ),
        .R(\FifoCntrRd_reg[0]_0 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "cq_axilt_slv/DAT_FIFO/MemArray_reg_0_3_0_5" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M MemArray_reg_0_3_0_5
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(I140[1:0]),
        .DIB(I140[3:2]),
        .DIC(I140[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut0_out__0[1:0]),
        .DOB(DataOut0_out__0[3:2]),
        .DOC(DataOut0_out__0[5:4]),
        .DOD(NLW_MemArray_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  LUT4 #(
    .INIT(16'hAAA8)) 
    MemArray_reg_0_3_0_5_i_1__1
       (.I0(s_axi_wvld_nn1),
        .I1(\WrPtr_reg[0]_0 ),
        .I2(\WrPtr_reg[0]_1 ),
        .I3(\WrPtr_reg[0]_2 ),
        .O(dat_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "cq_axilt_slv/DAT_FIFO/MemArray_reg_0_3_12_17" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M MemArray_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(I140[13:12]),
        .DIB(I140[15:14]),
        .DIC(I140[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut0_out__0[13:12]),
        .DOB(DataOut0_out__0[15:14]),
        .DOC(DataOut0_out__0[17:16]),
        .DOD(NLW_MemArray_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "cq_axilt_slv/DAT_FIFO/MemArray_reg_0_3_18_23" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M MemArray_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(I140[19:18]),
        .DIB(I140[21:20]),
        .DIC(I140[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut0_out__0[19:18]),
        .DOB(DataOut0_out__0[21:20]),
        .DOC(DataOut0_out__0[23:22]),
        .DOD(NLW_MemArray_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "cq_axilt_slv/DAT_FIFO/MemArray_reg_0_3_24_29" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M MemArray_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(I140[25:24]),
        .DIB(I140[27:26]),
        .DIC(I140[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut0_out__0[25:24]),
        .DOB(DataOut0_out__0[27:26]),
        .DOC(DataOut0_out__0[29:28]),
        .DOD(NLW_MemArray_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "cq_axilt_slv/DAT_FIFO/MemArray_reg_0_3_30_35" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M MemArray_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(I140[31:30]),
        .DIB(I140[33:32]),
        .DIC(I140[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut0_out__0[31:30]),
        .DOB(\tar_cq_be[1]_7 [1:0]),
        .DOC(\tar_cq_be[1]_7 [3:2]),
        .DOD(NLW_MemArray_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "144" *) 
  (* RTL_RAM_NAME = "cq_axilt_slv/DAT_FIFO/MemArray_reg_0_3_6_11" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M MemArray_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRB({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRC({1'b0,1'b0,1'b0,RdPtr}),
        .ADDRD({1'b0,1'b0,1'b0,WrPtr}),
        .DIA(I140[7:6]),
        .DIB(I140[9:8]),
        .DIC(I140[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(DataOut0_out__0[7:6]),
        .DOB(DataOut0_out__0[9:8]),
        .DOC(DataOut0_out__0[11:10]),
        .DOD(NLW_MemArray_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(user_clk),
        .WE(dat_fifo_wr_nn0));
  (* SOFT_HLUTNM = "soft_lutpair320" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \RdPtr[0]_i_1__6 
       (.I0(empty_ff_reg_0),
        .I1(req_wvld_nn1),
        .I2(RdPtr[0]),
        .O(\RdPtr[0]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair320" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \RdPtr[1]_i_1__7 
       (.I0(RdPtr[0]),
        .I1(req_wvld_nn1),
        .I2(empty_ff_reg_0),
        .I3(RdPtr[1]),
        .O(\RdPtr[1]_i_1__7_n_0 ));
  FDRE \RdPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[0]_i_1__6_n_0 ),
        .Q(RdPtr[0]),
        .R(\FifoCntrRd_reg[0]_0 ));
  FDRE \RdPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\RdPtr[1]_i_1__7_n_0 ),
        .Q(RdPtr[1]),
        .R(\FifoCntrRd_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair319" *) 
  LUT5 #(
    .INIT(32'h5557AAA8)) 
    \WrPtr[0]_i_1__9 
       (.I0(s_axi_wvld_nn1),
        .I1(\WrPtr_reg[0]_0 ),
        .I2(\WrPtr_reg[0]_1 ),
        .I3(\WrPtr_reg[0]_2 ),
        .I4(WrPtr[0]),
        .O(\WrPtr[0]_i_1__9_n_0 ));
  LUT6 #(
    .INIT(64'h5557FFFFAAA80000)) 
    \WrPtr[1]_i_1__9 
       (.I0(WrPtr[0]),
        .I1(\WrPtr_reg[0]_2 ),
        .I2(\WrPtr_reg[0]_1 ),
        .I3(\WrPtr_reg[0]_0 ),
        .I4(s_axi_wvld_nn1),
        .I5(WrPtr[1]),
        .O(\WrPtr[1]_i_1__9_n_0 ));
  FDRE \WrPtr_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[0]_i_1__9_n_0 ),
        .Q(WrPtr[0]),
        .R(\FifoCntrRd_reg[0]_0 ));
  FDRE \WrPtr_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\WrPtr[1]_i_1__9_n_0 ),
        .Q(WrPtr[1]),
        .R(\FifoCntrRd_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hF0F0F0F0F0F0F8FF)) 
    empty_ff_i_1__9
       (.I0(req_wvld_nn1),
        .I1(empty_ff_reg_0),
        .I2(empty_ff_reg_1),
        .I3(\FifoCntrRd_reg_n_0_[0] ),
        .I4(\FifoCntrRd_reg_n_0_[1] ),
        .I5(\FifoCntrRd_reg_n_0_[2] ),
        .O(empty_ff_i_1__9_n_0));
  FDRE empty_ff_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(empty_ff_i_1__9_n_0),
        .Q(dat_fifo_ep),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair321" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_be_nn1[0]_i_1 
       (.I0(\tar_cq_be[1]_7 [0]),
        .I1(Q),
        .I2(DataOut[32]),
        .O(\arb_win_nn2_reg[1] [0]));
  (* SOFT_HLUTNM = "soft_lutpair330" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_be_nn1[1]_i_1 
       (.I0(\tar_cq_be[1]_7 [1]),
        .I1(Q),
        .I2(DataOut[33]),
        .O(\arb_win_nn2_reg[1] [1]));
  (* SOFT_HLUTNM = "soft_lutpair327" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_be_nn1[2]_i_1 
       (.I0(\tar_cq_be[1]_7 [2]),
        .I1(Q),
        .I2(DataOut[34]),
        .O(\arb_win_nn2_reg[1] [2]));
  (* SOFT_HLUTNM = "soft_lutpair333" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \tar_be_nn1[3]_i_1 
       (.I0(\tar_cq_be[1]_7 [3]),
        .I1(Q),
        .I2(DataOut[35]),
        .O(\arb_win_nn2_reg[1] [3]));
  (* SOFT_HLUTNM = "soft_lutpair324" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[0]_i_1 
       (.I0(DataOut0_out__0[0]),
        .I1(DataOut[0]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair328" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[10]_i_1 
       (.I0(DataOut0_out__0[10]),
        .I1(DataOut[10]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [10]));
  (* SOFT_HLUTNM = "soft_lutpair335" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[11]_i_1 
       (.I0(DataOut0_out__0[11]),
        .I1(DataOut[11]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [11]));
  (* SOFT_HLUTNM = "soft_lutpair325" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[12]_i_1 
       (.I0(DataOut0_out__0[12]),
        .I1(DataOut[12]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [12]));
  (* SOFT_HLUTNM = "soft_lutpair335" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[13]_i_1 
       (.I0(DataOut0_out__0[13]),
        .I1(DataOut[13]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [13]));
  (* SOFT_HLUTNM = "soft_lutpair322" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[14]_i_1 
       (.I0(DataOut0_out__0[14]),
        .I1(DataOut[14]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [14]));
  (* SOFT_HLUTNM = "soft_lutpair331" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[15]_i_1 
       (.I0(DataOut0_out__0[15]),
        .I1(DataOut[15]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [15]));
  (* SOFT_HLUTNM = "soft_lutpair328" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[16]_i_1 
       (.I0(DataOut0_out__0[16]),
        .I1(DataOut[16]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [16]));
  (* SOFT_HLUTNM = "soft_lutpair336" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[17]_i_1 
       (.I0(DataOut0_out__0[17]),
        .I1(DataOut[17]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [17]));
  (* SOFT_HLUTNM = "soft_lutpair325" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[18]_i_1 
       (.I0(DataOut0_out__0[18]),
        .I1(DataOut[18]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [18]));
  (* SOFT_HLUTNM = "soft_lutpair336" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[19]_i_1 
       (.I0(DataOut0_out__0[19]),
        .I1(DataOut[19]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [19]));
  (* SOFT_HLUTNM = "soft_lutpair333" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[1]_i_1 
       (.I0(DataOut0_out__0[1]),
        .I1(DataOut[1]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair323" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[20]_i_1 
       (.I0(DataOut0_out__0[20]),
        .I1(DataOut[20]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [20]));
  (* SOFT_HLUTNM = "soft_lutpair332" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[21]_i_1 
       (.I0(DataOut0_out__0[21]),
        .I1(DataOut[21]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [21]));
  (* SOFT_HLUTNM = "soft_lutpair329" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[22]_i_1 
       (.I0(DataOut0_out__0[22]),
        .I1(DataOut[22]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [22]));
  (* SOFT_HLUTNM = "soft_lutpair337" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[23]_i_1 
       (.I0(DataOut0_out__0[23]),
        .I1(DataOut[23]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [23]));
  (* SOFT_HLUTNM = "soft_lutpair326" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[24]_i_1 
       (.I0(DataOut0_out__0[24]),
        .I1(DataOut[24]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [24]));
  (* SOFT_HLUTNM = "soft_lutpair337" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[25]_i_1 
       (.I0(DataOut0_out__0[25]),
        .I1(DataOut[25]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [25]));
  (* SOFT_HLUTNM = "soft_lutpair323" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[26]_i_1 
       (.I0(DataOut0_out__0[26]),
        .I1(DataOut[26]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [26]));
  (* SOFT_HLUTNM = "soft_lutpair332" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[27]_i_1 
       (.I0(DataOut0_out__0[27]),
        .I1(DataOut[27]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [27]));
  (* SOFT_HLUTNM = "soft_lutpair329" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[28]_i_1 
       (.I0(DataOut0_out__0[28]),
        .I1(DataOut[28]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [28]));
  (* SOFT_HLUTNM = "soft_lutpair338" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[29]_i_1 
       (.I0(DataOut0_out__0[29]),
        .I1(DataOut[29]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [29]));
  (* SOFT_HLUTNM = "soft_lutpair321" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[2]_i_1 
       (.I0(DataOut0_out__0[2]),
        .I1(DataOut[2]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair326" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[30]_i_1 
       (.I0(DataOut0_out__0[30]),
        .I1(DataOut[30]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [30]));
  (* SOFT_HLUTNM = "soft_lutpair338" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[31]_i_1 
       (.I0(DataOut0_out__0[31]),
        .I1(DataOut[31]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [31]));
  (* SOFT_HLUTNM = "soft_lutpair330" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[3]_i_1 
       (.I0(DataOut0_out__0[3]),
        .I1(DataOut[3]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair327" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[4]_i_1 
       (.I0(DataOut0_out__0[4]),
        .I1(DataOut[4]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair334" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[5]_i_1 
       (.I0(DataOut0_out__0[5]),
        .I1(DataOut[5]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair324" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[6]_i_1 
       (.I0(DataOut0_out__0[6]),
        .I1(DataOut[6]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair334" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[7]_i_1 
       (.I0(DataOut0_out__0[7]),
        .I1(DataOut[7]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair322" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[8]_i_1 
       (.I0(DataOut0_out__0[8]),
        .I1(DataOut[8]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair331" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \tar_dat_nn1[9]_i_1 
       (.I0(DataOut0_out__0[9]),
        .I1(DataOut[9]),
        .I2(Q),
        .O(\arb_win_nn2_reg[1]_0 [9]));
endmodule

(* ORIG_REF_NAME = "xil_internal_svlib_BRAM_TDP_MACRO" *) 
module xdma_0_xil_internal_svlib_BRAM_TDP_MACRO
   (rdata,
    CLK,
    mim_tx_wen,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [14:0]rdata;
  input CLK;
  input mim_tx_wen;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [14:0]wdata;

  wire CLK;
  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_52 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_53 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_74 ;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [14:0]rdata;
  wire [14:0]wdata;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl 
       (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(CLK),
        .CLKBWRCLK(CLK),
        .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
        .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:16],1'b0,1'b0,wdata[14:9],wdata[7:0]}),
        .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:16],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
        .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_52 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_53 ,rdata[14:9],rdata[7:0]}),
        .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
        .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_74 ,rdata[8]}),
        .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_tx_wen),
        .ENBWREN(mim_tx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "xil_internal_svlib_BRAM_TDP_MACRO" *) 
module xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_19
   (rdata,
    CLK,
    mim_tx_wen,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input CLK;
  input mim_tx_wen;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire CLK;
  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [17:0]rdata;
  wire [17:0]wdata;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl 
       (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(CLK),
        .CLKBWRCLK(CLK),
        .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
        .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:16],wdata[16:9],wdata[7:0]}),
        .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:16],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,wdata[17],wdata[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
        .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:16],rdata[16:9],rdata[7:0]}),
        .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
        .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:2],rdata[17],rdata[8]}),
        .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_tx_wen),
        .ENBWREN(mim_tx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "xil_internal_svlib_BRAM_TDP_MACRO" *) 
module xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_20
   (rdata,
    CLK,
    mim_tx_wen,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input CLK;
  input mim_tx_wen;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire CLK;
  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [17:0]rdata;
  wire [17:0]wdata;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl 
       (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(CLK),
        .CLKBWRCLK(CLK),
        .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
        .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:16],wdata[16:9],wdata[7:0]}),
        .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:16],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,wdata[17],wdata[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
        .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:16],rdata[16:9],rdata[7:0]}),
        .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
        .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:2],rdata[17],rdata[8]}),
        .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_tx_wen),
        .ENBWREN(mim_tx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "xil_internal_svlib_BRAM_TDP_MACRO" *) 
module xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_21
   (rdata,
    CLK,
    mim_tx_wen,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input CLK;
  input mim_tx_wen;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire CLK;
  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [17:0]rdata;
  wire [17:0]wdata;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl 
       (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(CLK),
        .CLKBWRCLK(CLK),
        .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
        .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:16],wdata[16:9],wdata[7:0]}),
        .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:16],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,wdata[17],wdata[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
        .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:16],rdata[16:9],rdata[7:0]}),
        .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
        .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:2],rdata[17],rdata[8]}),
        .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_tx_wen),
        .ENBWREN(mim_tx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "xil_internal_svlib_BRAM_TDP_MACRO" *) 
module xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_26
   (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
    CLK,
    mim_rx_wen,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
  output [13:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  input CLK;
  input mim_rx_wen;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [13:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;

  wire CLK;
  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire [13:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  wire [13:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_52 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_53 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_54 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_74 ;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl 
       (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(CLK),
        .CLKBWRCLK(CLK),
        .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
        .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:16],1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [13:9],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}),
        .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:16],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
        .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_52 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_53 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_54 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [13:9],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}),
        .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
        .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_74 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}),
        .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_rx_wen),
        .ENBWREN(mim_rx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "xil_internal_svlib_BRAM_TDP_MACRO" *) 
module xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_27
   (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
    CLK,
    mim_rx_wen,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
  output [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  input CLK;
  input mim_rx_wen;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;

  wire CLK;
  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl 
       (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(CLK),
        .CLKBWRCLK(CLK),
        .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
        .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [16:9],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}),
        .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:16],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [17],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
        .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [16:9],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}),
        .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
        .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [17],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}),
        .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_rx_wen),
        .ENBWREN(mim_rx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "xil_internal_svlib_BRAM_TDP_MACRO" *) 
module xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_28
   (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
    CLK,
    mim_rx_wen,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
  output [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  input CLK;
  input mim_rx_wen;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;

  wire CLK;
  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl 
       (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(CLK),
        .CLKBWRCLK(CLK),
        .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
        .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [16:9],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}),
        .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:16],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [17],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
        .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [16:9],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}),
        .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
        .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [17],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}),
        .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_rx_wen),
        .ENBWREN(mim_rx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "xil_internal_svlib_BRAM_TDP_MACRO" *) 
module xdma_0_xil_internal_svlib_BRAM_TDP_MACRO_29
   (\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ,
    CLK,
    mim_rx_wen,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 );
  output [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  input CLK;
  input mim_rx_wen;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;

  wire CLK;
  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 ;
  wire [17:0]\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ;
  wire \genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 ;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ;
  wire \NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \genblk5_0.bram36_tdp_bl.bram36_tdp_bl 
       (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(CLK),
        .CLKBWRCLK(CLK),
        .DBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DBITERR_UNCONNECTED ),
        .DIADI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIADI_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [16:9],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [7:0]}),
        .DIBDI({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DIBDI_UNCONNECTED [31:16],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [17],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_1 [8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOADO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_20 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_21 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_22 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_23 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_24 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_25 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_26 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_27 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_28 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_29 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_30 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_31 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_32 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_33 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_34 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_35 }),
        .DOBDO({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOBDO_UNCONNECTED [31:16],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [16:9],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [7:0]}),
        .DOPADOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPADOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_70 ,\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_n_71 }),
        .DOPBDOP({\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_DOPBDOP_UNCONNECTED [3:2],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [17],\genblk5_0.bram36_tdp_bl.bram36_tdp_bl_0 [8]}),
        .ECCPARITY(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_rx_wen),
        .ENBWREN(mim_rx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_genblk5_0.bram36_tdp_bl.bram36_tdp_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* DEST_SYNC_FF = "4" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) 
(* SIM_ASSERT_CHK = "0" *) (* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) 
(* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) (* keep_hierarchy = "true" *) 
(* xpm_cdc = "SINGLE" *) 
module xdma_0_xpm_cdc_single
   (src_clk,
    src_in,
    dest_clk,
    dest_out);
  input src_clk;
  input src_in;
  input dest_clk;
  output dest_out;

  wire dest_clk;
  wire src_in;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [3:0]syncstages_ff;

  assign dest_out = syncstages_ff[3];
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "SINGLE" *) 
  FDRE \syncstages_ff_reg[0] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(src_in),
        .Q(syncstages_ff[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "SINGLE" *) 
  FDRE \syncstages_ff_reg[1] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(syncstages_ff[0]),
        .Q(syncstages_ff[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "SINGLE" *) 
  FDRE \syncstages_ff_reg[2] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(syncstages_ff[1]),
        .Q(syncstages_ff[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "SINGLE" *) 
  FDRE \syncstages_ff_reg[3] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(syncstages_ff[2]),
        .Q(syncstages_ff[3]),
        .R(1'b0));
endmodule

(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) 
(* SIM_ASSERT_CHK = "0" *) (* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) 
(* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SINGLE" *) 
module xdma_0_xpm_cdc_single__parameterized0
   (src_clk,
    src_in,
    dest_clk,
    dest_out);
  input src_clk;
  input src_in;
  input dest_clk;
  output dest_out;

  wire dest_clk;
  wire src_in;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;

  assign dest_out = syncstages_ff[1];
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "SINGLE" *) 
  FDRE \syncstages_ff_reg[0] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(src_in),
        .Q(syncstages_ff[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "SINGLE" *) 
  FDRE \syncstages_ff_reg[1] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(syncstages_ff[0]),
        .Q(syncstages_ff[1]),
        .R(1'b0));
endmodule

(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) 
(* SIM_ASSERT_CHK = "0" *) (* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) 
(* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SINGLE" *) 
module xdma_0_xpm_cdc_single__parameterized0__2
   (src_clk,
    src_in,
    dest_clk,
    dest_out);
  input src_clk;
  input src_in;
  input dest_clk;
  output dest_out;

  wire dest_clk;
  wire src_in;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;

  assign dest_out = syncstages_ff[1];
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "SINGLE" *) 
  FDRE \syncstages_ff_reg[0] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(src_in),
        .Q(syncstages_ff[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "SINGLE" *) 
  FDRE \syncstages_ff_reg[1] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(syncstages_ff[0]),
        .Q(syncstages_ff[1]),
        .R(1'b0));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "36" *) (* BYTE_WRITE_WIDTH_B = "36" *) (* CASCADE_HEIGHT = "0" *) 
(* CLOCKING_MODE = "0" *) (* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "0" *) 
(* ECC_TYPE = "NONE" *) (* IGNORE_INIT_SYNTH = "0" *) (* MAX_NUM_CHAR = "0" *) 
(* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) 
(* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "18432" *) (* MEMORY_TYPE = "1" *) 
(* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) 
(* P_ECC_MODE = "0" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) 
(* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "0" *) 
(* P_MIN_WIDTH_DATA = "36" *) (* P_MIN_WIDTH_DATA_A = "36" *) (* P_MIN_WIDTH_DATA_B = "36" *) 
(* P_MIN_WIDTH_DATA_ECC = "36" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "36" *) 
(* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) 
(* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) 
(* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) 
(* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) 
(* P_WIDTH_COL_WRITE_A = "36" *) (* P_WIDTH_COL_WRITE_B = "36" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_A = "36" *) (* READ_DATA_WIDTH_B = "36" *) (* READ_LATENCY_A = "2" *) 
(* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "36" *) 
(* WRITE_DATA_WIDTH_B = "36" *) (* WRITE_MODE_A = "1" *) (* WRITE_MODE_B = "1" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) 
(* rsta_loop_iter = "36" *) (* rstb_loop_iter = "36" *) 
module xdma_0_xpm_memory_base
   (sleep,
    clka,
    rsta,
    ena,
    regcea,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    douta,
    sbiterra,
    dbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    web,
    addrb,
    dinb,
    injectsbiterrb,
    injectdbiterrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input rsta;
  input ena;
  input regcea;
  input [0:0]wea;
  input [8:0]addra;
  input [35:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  output [35:0]douta;
  output sbiterra;
  output dbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [0:0]web;
  input [8:0]addrb;
  input [35:0]dinb;
  input injectsbiterrb;
  input injectdbiterrb;
  output [35:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [35:0]dina;
  wire [31:0]\^doutb ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_32 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_33 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_34 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_35 ;
  wire regceb;
  wire [0:0]wea;

  assign dbiterra = \<const0> ;
  assign dbiterrb = \<const0> ;
  assign douta[35] = \<const0> ;
  assign douta[34] = \<const0> ;
  assign douta[33] = \<const0> ;
  assign douta[32] = \<const0> ;
  assign douta[31] = \<const0> ;
  assign douta[30] = \<const0> ;
  assign douta[29] = \<const0> ;
  assign douta[28] = \<const0> ;
  assign douta[27] = \<const0> ;
  assign douta[26] = \<const0> ;
  assign douta[25] = \<const0> ;
  assign douta[24] = \<const0> ;
  assign douta[23] = \<const0> ;
  assign douta[22] = \<const0> ;
  assign douta[21] = \<const0> ;
  assign douta[20] = \<const0> ;
  assign douta[19] = \<const0> ;
  assign douta[18] = \<const0> ;
  assign douta[17] = \<const0> ;
  assign douta[16] = \<const0> ;
  assign douta[15] = \<const0> ;
  assign douta[14] = \<const0> ;
  assign douta[13] = \<const0> ;
  assign douta[12] = \<const0> ;
  assign douta[11] = \<const0> ;
  assign douta[10] = \<const0> ;
  assign douta[9] = \<const0> ;
  assign douta[8] = \<const0> ;
  assign douta[7] = \<const0> ;
  assign douta[6] = \<const0> ;
  assign douta[5] = \<const0> ;
  assign douta[4] = \<const0> ;
  assign douta[3] = \<const0> ;
  assign douta[2] = \<const0> ;
  assign douta[1] = \<const0> ;
  assign douta[0] = \<const0> ;
  assign doutb[35] = \<const0> ;
  assign doutb[34] = \<const0> ;
  assign doutb[33] = \<const0> ;
  assign doutb[32] = \<const0> ;
  assign doutb[31:0] = \^doutb [31:0];
  assign sbiterra = \<const0> ;
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* \MEM.PORTA.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTA.ADDRESS_END  = "511" *) 
  (* \MEM.PORTA.DATA_BIT_LAYOUT  = "p4_d32" *) 
  (* \MEM.PORTA.DATA_LSB  = "0" *) 
  (* \MEM.PORTA.DATA_MSB  = "35" *) 
  (* \MEM.PORTB.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTB.ADDRESS_END  = "511" *) 
  (* \MEM.PORTB.DATA_BIT_LAYOUT  = "p4_d32" *) 
  (* \MEM.PORTB.DATA_LSB  = "0" *) 
  (* \MEM.PORTB.DATA_MSB  = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "18432" *) 
  (* RTL_RAM_NAME = "inst/ram_top/gen_h2c_bram.H2C_DAT0_FIFO/xpm_memory_sdpram_inst_loop[1].xpm_memory_sdpram_inst/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "511" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "35" *) 
  RAMB18E1 #(
    .DOA_REG(1),
    .DOB_REG(1),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(18'h00000),
    .INIT_B(18'h00000),
    .RAM_MODE("SDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(36),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(18'h00000),
    .SRVAL_B(18'h00000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(0),
    .WRITE_WIDTH_B(36)) 
    \gen_wr_a.gen_word_narrow.mem_reg 
       (.ADDRARDADDR({addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CLKARDCLK(clka),
        .CLKBWRCLK(clka),
        .DIADI(dina[15:0]),
        .DIBDI(dina[31:16]),
        .DIPADIP(dina[33:32]),
        .DIPBDIP(dina[35:34]),
        .DOADO(\^doutb [15:0]),
        .DOBDO(\^doutb [31:16]),
        .DOPADOP({\gen_wr_a.gen_word_narrow.mem_reg_n_32 ,\gen_wr_a.gen_word_narrow.mem_reg_n_33 }),
        .DOPBDOP({\gen_wr_a.gen_word_narrow.mem_reg_n_34 ,\gen_wr_a.gen_word_narrow.mem_reg_n_35 }),
        .ENARDEN(1'b1),
        .ENBWREN(1'b1),
        .REGCEAREGCE(regceb),
        .REGCEB(1'b0),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .WEA({1'b0,1'b0}),
        .WEBWE({wea,wea,wea,wea}));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "36" *) (* BYTE_WRITE_WIDTH_B = "36" *) (* CASCADE_HEIGHT = "0" *) 
(* CLOCKING_MODE = "0" *) (* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "0" *) 
(* ECC_TYPE = "NONE" *) (* IGNORE_INIT_SYNTH = "0" *) (* MAX_NUM_CHAR = "0" *) 
(* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) 
(* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "18432" *) (* MEMORY_TYPE = "1" *) 
(* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) 
(* P_ECC_MODE = "0" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) 
(* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "0" *) 
(* P_MIN_WIDTH_DATA = "36" *) (* P_MIN_WIDTH_DATA_A = "36" *) (* P_MIN_WIDTH_DATA_B = "36" *) 
(* P_MIN_WIDTH_DATA_ECC = "36" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "36" *) 
(* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) 
(* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) 
(* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) 
(* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) 
(* P_WIDTH_COL_WRITE_A = "36" *) (* P_WIDTH_COL_WRITE_B = "36" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_A = "36" *) (* READ_DATA_WIDTH_B = "36" *) (* READ_LATENCY_A = "2" *) 
(* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "36" *) 
(* WRITE_DATA_WIDTH_B = "36" *) (* WRITE_MODE_A = "1" *) (* WRITE_MODE_B = "1" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) 
(* rsta_loop_iter = "36" *) (* rstb_loop_iter = "36" *) 
module xdma_0_xpm_memory_base__14
   (sleep,
    clka,
    rsta,
    ena,
    regcea,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    douta,
    sbiterra,
    dbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    web,
    addrb,
    dinb,
    injectsbiterrb,
    injectdbiterrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input rsta;
  input ena;
  input regcea;
  input [0:0]wea;
  input [8:0]addra;
  input [35:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  output [35:0]douta;
  output sbiterra;
  output dbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [0:0]web;
  input [8:0]addrb;
  input [35:0]dinb;
  input injectsbiterrb;
  input injectdbiterrb;
  output [35:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [35:0]dina;
  wire [31:0]\^doutb ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_32 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_33 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_34 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_35 ;
  wire regceb;
  wire [0:0]wea;

  assign dbiterra = \<const0> ;
  assign dbiterrb = \<const0> ;
  assign douta[35] = \<const0> ;
  assign douta[34] = \<const0> ;
  assign douta[33] = \<const0> ;
  assign douta[32] = \<const0> ;
  assign douta[31] = \<const0> ;
  assign douta[30] = \<const0> ;
  assign douta[29] = \<const0> ;
  assign douta[28] = \<const0> ;
  assign douta[27] = \<const0> ;
  assign douta[26] = \<const0> ;
  assign douta[25] = \<const0> ;
  assign douta[24] = \<const0> ;
  assign douta[23] = \<const0> ;
  assign douta[22] = \<const0> ;
  assign douta[21] = \<const0> ;
  assign douta[20] = \<const0> ;
  assign douta[19] = \<const0> ;
  assign douta[18] = \<const0> ;
  assign douta[17] = \<const0> ;
  assign douta[16] = \<const0> ;
  assign douta[15] = \<const0> ;
  assign douta[14] = \<const0> ;
  assign douta[13] = \<const0> ;
  assign douta[12] = \<const0> ;
  assign douta[11] = \<const0> ;
  assign douta[10] = \<const0> ;
  assign douta[9] = \<const0> ;
  assign douta[8] = \<const0> ;
  assign douta[7] = \<const0> ;
  assign douta[6] = \<const0> ;
  assign douta[5] = \<const0> ;
  assign douta[4] = \<const0> ;
  assign douta[3] = \<const0> ;
  assign douta[2] = \<const0> ;
  assign douta[1] = \<const0> ;
  assign douta[0] = \<const0> ;
  assign doutb[35] = \<const0> ;
  assign doutb[34] = \<const0> ;
  assign doutb[33] = \<const0> ;
  assign doutb[32] = \<const0> ;
  assign doutb[31:0] = \^doutb [31:0];
  assign sbiterra = \<const0> ;
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* \MEM.PORTA.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTA.ADDRESS_END  = "511" *) 
  (* \MEM.PORTA.DATA_BIT_LAYOUT  = "p4_d32" *) 
  (* \MEM.PORTA.DATA_LSB  = "0" *) 
  (* \MEM.PORTA.DATA_MSB  = "35" *) 
  (* \MEM.PORTB.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTB.ADDRESS_END  = "511" *) 
  (* \MEM.PORTB.DATA_BIT_LAYOUT  = "p4_d32" *) 
  (* \MEM.PORTB.DATA_LSB  = "0" *) 
  (* \MEM.PORTB.DATA_MSB  = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "18432" *) 
  (* RTL_RAM_NAME = "inst/ram_top/gen_c2h_bram.C2H_DAT0_FIFO/xpm_memory_sdpram_inst_loop[0].xpm_memory_sdpram_inst/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "511" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "35" *) 
  RAMB18E1 #(
    .DOA_REG(1),
    .DOB_REG(1),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(18'h00000),
    .INIT_B(18'h00000),
    .RAM_MODE("SDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(36),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(18'h00000),
    .SRVAL_B(18'h00000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(0),
    .WRITE_WIDTH_B(36)) 
    \gen_wr_a.gen_word_narrow.mem_reg 
       (.ADDRARDADDR({addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CLKARDCLK(clka),
        .CLKBWRCLK(clka),
        .DIADI(dina[15:0]),
        .DIBDI(dina[31:16]),
        .DIPADIP({1'b0,1'b0}),
        .DIPBDIP({1'b0,1'b0}),
        .DOADO(\^doutb [15:0]),
        .DOBDO(\^doutb [31:16]),
        .DOPADOP({\gen_wr_a.gen_word_narrow.mem_reg_n_32 ,\gen_wr_a.gen_word_narrow.mem_reg_n_33 }),
        .DOPBDOP({\gen_wr_a.gen_word_narrow.mem_reg_n_34 ,\gen_wr_a.gen_word_narrow.mem_reg_n_35 }),
        .ENARDEN(1'b1),
        .ENBWREN(1'b1),
        .REGCEAREGCE(regceb),
        .REGCEB(1'b0),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .WEA({1'b0,1'b0}),
        .WEBWE({wea,wea,wea,wea}));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "36" *) (* BYTE_WRITE_WIDTH_B = "36" *) (* CASCADE_HEIGHT = "0" *) 
(* CLOCKING_MODE = "0" *) (* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "0" *) 
(* ECC_TYPE = "NONE" *) (* IGNORE_INIT_SYNTH = "0" *) (* MAX_NUM_CHAR = "0" *) 
(* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) 
(* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "18432" *) (* MEMORY_TYPE = "1" *) 
(* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) 
(* P_ECC_MODE = "0" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) 
(* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "0" *) 
(* P_MIN_WIDTH_DATA = "36" *) (* P_MIN_WIDTH_DATA_A = "36" *) (* P_MIN_WIDTH_DATA_B = "36" *) 
(* P_MIN_WIDTH_DATA_ECC = "36" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "36" *) 
(* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) 
(* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) 
(* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) 
(* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) 
(* P_WIDTH_COL_WRITE_A = "36" *) (* P_WIDTH_COL_WRITE_B = "36" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_A = "36" *) (* READ_DATA_WIDTH_B = "36" *) (* READ_LATENCY_A = "2" *) 
(* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "36" *) 
(* WRITE_DATA_WIDTH_B = "36" *) (* WRITE_MODE_A = "1" *) (* WRITE_MODE_B = "1" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) 
(* rsta_loop_iter = "36" *) (* rstb_loop_iter = "36" *) 
module xdma_0_xpm_memory_base__15
   (sleep,
    clka,
    rsta,
    ena,
    regcea,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    douta,
    sbiterra,
    dbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    web,
    addrb,
    dinb,
    injectsbiterrb,
    injectdbiterrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input rsta;
  input ena;
  input regcea;
  input [0:0]wea;
  input [8:0]addra;
  input [35:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  output [35:0]douta;
  output sbiterra;
  output dbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [0:0]web;
  input [8:0]addrb;
  input [35:0]dinb;
  input injectsbiterrb;
  input injectdbiterrb;
  output [35:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [35:0]dina;
  wire [31:0]\^doutb ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_32 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_33 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_34 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_35 ;
  wire regceb;
  wire [0:0]wea;

  assign dbiterra = \<const0> ;
  assign dbiterrb = \<const0> ;
  assign douta[35] = \<const0> ;
  assign douta[34] = \<const0> ;
  assign douta[33] = \<const0> ;
  assign douta[32] = \<const0> ;
  assign douta[31] = \<const0> ;
  assign douta[30] = \<const0> ;
  assign douta[29] = \<const0> ;
  assign douta[28] = \<const0> ;
  assign douta[27] = \<const0> ;
  assign douta[26] = \<const0> ;
  assign douta[25] = \<const0> ;
  assign douta[24] = \<const0> ;
  assign douta[23] = \<const0> ;
  assign douta[22] = \<const0> ;
  assign douta[21] = \<const0> ;
  assign douta[20] = \<const0> ;
  assign douta[19] = \<const0> ;
  assign douta[18] = \<const0> ;
  assign douta[17] = \<const0> ;
  assign douta[16] = \<const0> ;
  assign douta[15] = \<const0> ;
  assign douta[14] = \<const0> ;
  assign douta[13] = \<const0> ;
  assign douta[12] = \<const0> ;
  assign douta[11] = \<const0> ;
  assign douta[10] = \<const0> ;
  assign douta[9] = \<const0> ;
  assign douta[8] = \<const0> ;
  assign douta[7] = \<const0> ;
  assign douta[6] = \<const0> ;
  assign douta[5] = \<const0> ;
  assign douta[4] = \<const0> ;
  assign douta[3] = \<const0> ;
  assign douta[2] = \<const0> ;
  assign douta[1] = \<const0> ;
  assign douta[0] = \<const0> ;
  assign doutb[35] = \<const0> ;
  assign doutb[34] = \<const0> ;
  assign doutb[33] = \<const0> ;
  assign doutb[32] = \<const0> ;
  assign doutb[31:0] = \^doutb [31:0];
  assign sbiterra = \<const0> ;
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* \MEM.PORTA.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTA.ADDRESS_END  = "511" *) 
  (* \MEM.PORTA.DATA_BIT_LAYOUT  = "p4_d32" *) 
  (* \MEM.PORTA.DATA_LSB  = "0" *) 
  (* \MEM.PORTA.DATA_MSB  = "35" *) 
  (* \MEM.PORTB.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTB.ADDRESS_END  = "511" *) 
  (* \MEM.PORTB.DATA_BIT_LAYOUT  = "p4_d32" *) 
  (* \MEM.PORTB.DATA_LSB  = "0" *) 
  (* \MEM.PORTB.DATA_MSB  = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "18432" *) 
  (* RTL_RAM_NAME = "inst/ram_top/gen_c2h_bram.C2H_DAT0_FIFO/xpm_memory_sdpram_inst_loop[1].xpm_memory_sdpram_inst/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "511" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "35" *) 
  RAMB18E1 #(
    .DOA_REG(1),
    .DOB_REG(1),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(18'h00000),
    .INIT_B(18'h00000),
    .RAM_MODE("SDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(36),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(18'h00000),
    .SRVAL_B(18'h00000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(0),
    .WRITE_WIDTH_B(36)) 
    \gen_wr_a.gen_word_narrow.mem_reg 
       (.ADDRARDADDR({addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CLKARDCLK(clka),
        .CLKBWRCLK(clka),
        .DIADI(dina[15:0]),
        .DIBDI(dina[31:16]),
        .DIPADIP({1'b0,1'b0}),
        .DIPBDIP({1'b0,1'b0}),
        .DOADO(\^doutb [15:0]),
        .DOBDO(\^doutb [31:16]),
        .DOPADOP({\gen_wr_a.gen_word_narrow.mem_reg_n_32 ,\gen_wr_a.gen_word_narrow.mem_reg_n_33 }),
        .DOPBDOP({\gen_wr_a.gen_word_narrow.mem_reg_n_34 ,\gen_wr_a.gen_word_narrow.mem_reg_n_35 }),
        .ENARDEN(1'b1),
        .ENBWREN(1'b1),
        .REGCEAREGCE(regceb),
        .REGCEB(1'b0),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .WEA({1'b0,1'b0}),
        .WEBWE({wea,wea,wea,wea}));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "36" *) (* BYTE_WRITE_WIDTH_B = "36" *) (* CASCADE_HEIGHT = "0" *) 
(* CLOCKING_MODE = "0" *) (* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "0" *) 
(* ECC_TYPE = "NONE" *) (* IGNORE_INIT_SYNTH = "0" *) (* MAX_NUM_CHAR = "0" *) 
(* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) 
(* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "18432" *) (* MEMORY_TYPE = "1" *) 
(* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) 
(* P_ECC_MODE = "0" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) 
(* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "0" *) 
(* P_MIN_WIDTH_DATA = "36" *) (* P_MIN_WIDTH_DATA_A = "36" *) (* P_MIN_WIDTH_DATA_B = "36" *) 
(* P_MIN_WIDTH_DATA_ECC = "36" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "36" *) 
(* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) 
(* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) 
(* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) 
(* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) 
(* P_WIDTH_COL_WRITE_A = "36" *) (* P_WIDTH_COL_WRITE_B = "36" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_A = "36" *) (* READ_DATA_WIDTH_B = "36" *) (* READ_LATENCY_A = "2" *) 
(* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "36" *) 
(* WRITE_DATA_WIDTH_B = "36" *) (* WRITE_MODE_A = "1" *) (* WRITE_MODE_B = "1" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) 
(* rsta_loop_iter = "36" *) (* rstb_loop_iter = "36" *) 
module xdma_0_xpm_memory_base__22
   (sleep,
    clka,
    rsta,
    ena,
    regcea,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    douta,
    sbiterra,
    dbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    web,
    addrb,
    dinb,
    injectsbiterrb,
    injectdbiterrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input rsta;
  input ena;
  input regcea;
  input [0:0]wea;
  input [8:0]addra;
  input [35:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  output [35:0]douta;
  output sbiterra;
  output dbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [0:0]web;
  input [8:0]addrb;
  input [35:0]dinb;
  input injectsbiterrb;
  input injectdbiterrb;
  output [35:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [35:0]dina;
  wire [31:0]\^doutb ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_32 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_33 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_34 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_35 ;
  wire regceb;
  wire [0:0]wea;

  assign dbiterra = \<const0> ;
  assign dbiterrb = \<const0> ;
  assign douta[35] = \<const0> ;
  assign douta[34] = \<const0> ;
  assign douta[33] = \<const0> ;
  assign douta[32] = \<const0> ;
  assign douta[31] = \<const0> ;
  assign douta[30] = \<const0> ;
  assign douta[29] = \<const0> ;
  assign douta[28] = \<const0> ;
  assign douta[27] = \<const0> ;
  assign douta[26] = \<const0> ;
  assign douta[25] = \<const0> ;
  assign douta[24] = \<const0> ;
  assign douta[23] = \<const0> ;
  assign douta[22] = \<const0> ;
  assign douta[21] = \<const0> ;
  assign douta[20] = \<const0> ;
  assign douta[19] = \<const0> ;
  assign douta[18] = \<const0> ;
  assign douta[17] = \<const0> ;
  assign douta[16] = \<const0> ;
  assign douta[15] = \<const0> ;
  assign douta[14] = \<const0> ;
  assign douta[13] = \<const0> ;
  assign douta[12] = \<const0> ;
  assign douta[11] = \<const0> ;
  assign douta[10] = \<const0> ;
  assign douta[9] = \<const0> ;
  assign douta[8] = \<const0> ;
  assign douta[7] = \<const0> ;
  assign douta[6] = \<const0> ;
  assign douta[5] = \<const0> ;
  assign douta[4] = \<const0> ;
  assign douta[3] = \<const0> ;
  assign douta[2] = \<const0> ;
  assign douta[1] = \<const0> ;
  assign douta[0] = \<const0> ;
  assign doutb[35] = \<const0> ;
  assign doutb[34] = \<const0> ;
  assign doutb[33] = \<const0> ;
  assign doutb[32] = \<const0> ;
  assign doutb[31:0] = \^doutb [31:0];
  assign sbiterra = \<const0> ;
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* \MEM.PORTA.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTA.ADDRESS_END  = "511" *) 
  (* \MEM.PORTA.DATA_BIT_LAYOUT  = "p4_d32" *) 
  (* \MEM.PORTA.DATA_LSB  = "0" *) 
  (* \MEM.PORTA.DATA_MSB  = "35" *) 
  (* \MEM.PORTB.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTB.ADDRESS_END  = "511" *) 
  (* \MEM.PORTB.DATA_BIT_LAYOUT  = "p4_d32" *) 
  (* \MEM.PORTB.DATA_LSB  = "0" *) 
  (* \MEM.PORTB.DATA_MSB  = "35" *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "18432" *) 
  (* RTL_RAM_NAME = "inst/ram_top/gen_h2c_bram.H2C_DAT0_FIFO/xpm_memory_sdpram_inst_loop[0].xpm_memory_sdpram_inst/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "511" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "35" *) 
  RAMB18E1 #(
    .DOA_REG(1),
    .DOB_REG(1),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(18'h00000),
    .INIT_B(18'h00000),
    .RAM_MODE("SDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(36),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(18'h00000),
    .SRVAL_B(18'h00000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(0),
    .WRITE_WIDTH_B(36)) 
    \gen_wr_a.gen_word_narrow.mem_reg 
       (.ADDRARDADDR({addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CLKARDCLK(clka),
        .CLKBWRCLK(clka),
        .DIADI(dina[15:0]),
        .DIBDI(dina[31:16]),
        .DIPADIP(dina[33:32]),
        .DIPBDIP(dina[35:34]),
        .DOADO(\^doutb [15:0]),
        .DOBDO(\^doutb [31:16]),
        .DOPADOP({\gen_wr_a.gen_word_narrow.mem_reg_n_32 ,\gen_wr_a.gen_word_narrow.mem_reg_n_33 }),
        .DOPBDOP({\gen_wr_a.gen_word_narrow.mem_reg_n_34 ,\gen_wr_a.gen_word_narrow.mem_reg_n_35 }),
        .ENARDEN(1'b1),
        .ENBWREN(1'b1),
        .REGCEAREGCE(regceb),
        .REGCEB(1'b0),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .WEA({1'b0,1'b0}),
        .WEBWE({wea,wea,wea,wea}));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "72" *) (* BYTE_WRITE_WIDTH_B = "72" *) (* CASCADE_HEIGHT = "0" *) 
(* CLOCKING_MODE = "0" *) (* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "0" *) 
(* ECC_TYPE = "NONE" *) (* IGNORE_INIT_SYNTH = "0" *) (* MAX_NUM_CHAR = "0" *) 
(* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) 
(* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "36864" *) (* MEMORY_TYPE = "1" *) 
(* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) 
(* P_ECC_MODE = "0" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) 
(* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "0" *) 
(* P_MIN_WIDTH_DATA = "72" *) (* P_MIN_WIDTH_DATA_A = "72" *) (* P_MIN_WIDTH_DATA_B = "72" *) 
(* P_MIN_WIDTH_DATA_ECC = "72" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "72" *) 
(* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) 
(* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) 
(* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) 
(* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) 
(* P_WIDTH_COL_WRITE_A = "72" *) (* P_WIDTH_COL_WRITE_B = "72" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_A = "72" *) (* READ_DATA_WIDTH_B = "72" *) (* READ_LATENCY_A = "2" *) 
(* READ_LATENCY_B = "1" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "72" *) 
(* WRITE_DATA_WIDTH_B = "72" *) (* WRITE_MODE_A = "1" *) (* WRITE_MODE_B = "1" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) 
(* rsta_loop_iter = "72" *) (* rstb_loop_iter = "72" *) 
module xdma_0_xpm_memory_base__parameterized0
   (sleep,
    clka,
    rsta,
    ena,
    regcea,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    douta,
    sbiterra,
    dbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    web,
    addrb,
    dinb,
    injectsbiterrb,
    injectdbiterrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input rsta;
  input ena;
  input regcea;
  input [0:0]wea;
  input [8:0]addra;
  input [71:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  output [71:0]douta;
  output sbiterra;
  output dbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [0:0]web;
  input [8:0]addrb;
  input [71:0]dinb;
  input injectsbiterrb;
  input injectdbiterrb;
  output [71:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [71:0]dina;
  wire [71:0]doutb;
  wire [0:0]wea;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ;
  wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ;

  assign dbiterra = \<const0> ;
  assign dbiterrb = \<const0> ;
  assign douta[71] = \<const0> ;
  assign douta[70] = \<const0> ;
  assign douta[69] = \<const0> ;
  assign douta[68] = \<const0> ;
  assign douta[67] = \<const0> ;
  assign douta[66] = \<const0> ;
  assign douta[65] = \<const0> ;
  assign douta[64] = \<const0> ;
  assign douta[63] = \<const0> ;
  assign douta[62] = \<const0> ;
  assign douta[61] = \<const0> ;
  assign douta[60] = \<const0> ;
  assign douta[59] = \<const0> ;
  assign douta[58] = \<const0> ;
  assign douta[57] = \<const0> ;
  assign douta[56] = \<const0> ;
  assign douta[55] = \<const0> ;
  assign douta[54] = \<const0> ;
  assign douta[53] = \<const0> ;
  assign douta[52] = \<const0> ;
  assign douta[51] = \<const0> ;
  assign douta[50] = \<const0> ;
  assign douta[49] = \<const0> ;
  assign douta[48] = \<const0> ;
  assign douta[47] = \<const0> ;
  assign douta[46] = \<const0> ;
  assign douta[45] = \<const0> ;
  assign douta[44] = \<const0> ;
  assign douta[43] = \<const0> ;
  assign douta[42] = \<const0> ;
  assign douta[41] = \<const0> ;
  assign douta[40] = \<const0> ;
  assign douta[39] = \<const0> ;
  assign douta[38] = \<const0> ;
  assign douta[37] = \<const0> ;
  assign douta[36] = \<const0> ;
  assign douta[35] = \<const0> ;
  assign douta[34] = \<const0> ;
  assign douta[33] = \<const0> ;
  assign douta[32] = \<const0> ;
  assign douta[31] = \<const0> ;
  assign douta[30] = \<const0> ;
  assign douta[29] = \<const0> ;
  assign douta[28] = \<const0> ;
  assign douta[27] = \<const0> ;
  assign douta[26] = \<const0> ;
  assign douta[25] = \<const0> ;
  assign douta[24] = \<const0> ;
  assign douta[23] = \<const0> ;
  assign douta[22] = \<const0> ;
  assign douta[21] = \<const0> ;
  assign douta[20] = \<const0> ;
  assign douta[19] = \<const0> ;
  assign douta[18] = \<const0> ;
  assign douta[17] = \<const0> ;
  assign douta[16] = \<const0> ;
  assign douta[15] = \<const0> ;
  assign douta[14] = \<const0> ;
  assign douta[13] = \<const0> ;
  assign douta[12] = \<const0> ;
  assign douta[11] = \<const0> ;
  assign douta[10] = \<const0> ;
  assign douta[9] = \<const0> ;
  assign douta[8] = \<const0> ;
  assign douta[7] = \<const0> ;
  assign douta[6] = \<const0> ;
  assign douta[5] = \<const0> ;
  assign douta[4] = \<const0> ;
  assign douta[3] = \<const0> ;
  assign douta[2] = \<const0> ;
  assign douta[1] = \<const0> ;
  assign douta[0] = \<const0> ;
  assign sbiterra = \<const0> ;
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* \MEM.PORTA.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTA.ADDRESS_END  = "511" *) 
  (* \MEM.PORTA.DATA_BIT_LAYOUT  = "p8_d64" *) 
  (* \MEM.PORTA.DATA_LSB  = "0" *) 
  (* \MEM.PORTA.DATA_MSB  = "71" *) 
  (* \MEM.PORTB.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTB.ADDRESS_END  = "511" *) 
  (* \MEM.PORTB.DATA_BIT_LAYOUT  = "p8_d64" *) 
  (* \MEM.PORTB.DATA_LSB  = "0" *) 
  (* \MEM.PORTB.DATA_MSB  = "71" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* RTL_RAM_BITS = "36864" *) 
  (* RTL_RAM_NAME = "inst/ram_top/mas_bridge_ram_write_512.MASTER_WRITE_FIFO/xpm_memory_sdpram_inst_loop[0].xpm_memory_sdpram_inst/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "511" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "71" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("SDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(72),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(0),
    .WRITE_WIDTH_B(72)) 
    \gen_wr_a.gen_word_narrow.mem_reg 
       (.ADDRARDADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(clka),
        .CLKBWRCLK(clka),
        .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ),
        .DIADI(dina[31:0]),
        .DIBDI(dina[63:32]),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO(doutb[31:0]),
        .DOBDO(doutb[63:32]),
        .DOPADOP(doutb[67:64]),
        .DOPBDOP(doutb[71:68]),
        .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(1'b1),
        .ENBWREN(1'b1),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b0),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ),
        .WEA({1'b0,1'b0,1'b0,1'b0}),
        .WEBWE({wea,wea,wea,wea,wea,wea,wea,wea}));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "72" *) (* BYTE_WRITE_WIDTH_B = "72" *) (* CASCADE_HEIGHT = "0" *) 
(* CLOCKING_MODE = "0" *) (* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "0" *) 
(* ECC_TYPE = "NONE" *) (* IGNORE_INIT_SYNTH = "0" *) (* MAX_NUM_CHAR = "0" *) 
(* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) 
(* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "36864" *) (* MEMORY_TYPE = "1" *) 
(* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) 
(* P_ECC_MODE = "0" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) 
(* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "0" *) 
(* P_MIN_WIDTH_DATA = "72" *) (* P_MIN_WIDTH_DATA_A = "72" *) (* P_MIN_WIDTH_DATA_B = "72" *) 
(* P_MIN_WIDTH_DATA_ECC = "72" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "72" *) 
(* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) 
(* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) 
(* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) 
(* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) 
(* P_WIDTH_COL_WRITE_A = "72" *) (* P_WIDTH_COL_WRITE_B = "72" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_A = "72" *) (* READ_DATA_WIDTH_B = "72" *) (* READ_LATENCY_A = "2" *) 
(* READ_LATENCY_B = "1" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "72" *) 
(* WRITE_DATA_WIDTH_B = "72" *) (* WRITE_MODE_A = "1" *) (* WRITE_MODE_B = "1" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) 
(* rsta_loop_iter = "72" *) (* rstb_loop_iter = "72" *) 
module xdma_0_xpm_memory_base__parameterized0__2
   (sleep,
    clka,
    rsta,
    ena,
    regcea,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    douta,
    sbiterra,
    dbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    web,
    addrb,
    dinb,
    injectsbiterrb,
    injectdbiterrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input rsta;
  input ena;
  input regcea;
  input [0:0]wea;
  input [8:0]addra;
  input [71:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  output [71:0]douta;
  output sbiterra;
  output dbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [0:0]web;
  input [8:0]addrb;
  input [71:0]dinb;
  input injectsbiterrb;
  input injectdbiterrb;
  output [71:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [71:0]dina;
  wire [63:0]\^doutb ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_68 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_69 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_70 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_71 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_72 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_73 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_74 ;
  wire \gen_wr_a.gen_word_narrow.mem_reg_n_75 ;
  wire [0:0]wea;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ;
  wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ;
  wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ;

  assign dbiterra = \<const0> ;
  assign dbiterrb = \<const0> ;
  assign douta[71] = \<const0> ;
  assign douta[70] = \<const0> ;
  assign douta[69] = \<const0> ;
  assign douta[68] = \<const0> ;
  assign douta[67] = \<const0> ;
  assign douta[66] = \<const0> ;
  assign douta[65] = \<const0> ;
  assign douta[64] = \<const0> ;
  assign douta[63] = \<const0> ;
  assign douta[62] = \<const0> ;
  assign douta[61] = \<const0> ;
  assign douta[60] = \<const0> ;
  assign douta[59] = \<const0> ;
  assign douta[58] = \<const0> ;
  assign douta[57] = \<const0> ;
  assign douta[56] = \<const0> ;
  assign douta[55] = \<const0> ;
  assign douta[54] = \<const0> ;
  assign douta[53] = \<const0> ;
  assign douta[52] = \<const0> ;
  assign douta[51] = \<const0> ;
  assign douta[50] = \<const0> ;
  assign douta[49] = \<const0> ;
  assign douta[48] = \<const0> ;
  assign douta[47] = \<const0> ;
  assign douta[46] = \<const0> ;
  assign douta[45] = \<const0> ;
  assign douta[44] = \<const0> ;
  assign douta[43] = \<const0> ;
  assign douta[42] = \<const0> ;
  assign douta[41] = \<const0> ;
  assign douta[40] = \<const0> ;
  assign douta[39] = \<const0> ;
  assign douta[38] = \<const0> ;
  assign douta[37] = \<const0> ;
  assign douta[36] = \<const0> ;
  assign douta[35] = \<const0> ;
  assign douta[34] = \<const0> ;
  assign douta[33] = \<const0> ;
  assign douta[32] = \<const0> ;
  assign douta[31] = \<const0> ;
  assign douta[30] = \<const0> ;
  assign douta[29] = \<const0> ;
  assign douta[28] = \<const0> ;
  assign douta[27] = \<const0> ;
  assign douta[26] = \<const0> ;
  assign douta[25] = \<const0> ;
  assign douta[24] = \<const0> ;
  assign douta[23] = \<const0> ;
  assign douta[22] = \<const0> ;
  assign douta[21] = \<const0> ;
  assign douta[20] = \<const0> ;
  assign douta[19] = \<const0> ;
  assign douta[18] = \<const0> ;
  assign douta[17] = \<const0> ;
  assign douta[16] = \<const0> ;
  assign douta[15] = \<const0> ;
  assign douta[14] = \<const0> ;
  assign douta[13] = \<const0> ;
  assign douta[12] = \<const0> ;
  assign douta[11] = \<const0> ;
  assign douta[10] = \<const0> ;
  assign douta[9] = \<const0> ;
  assign douta[8] = \<const0> ;
  assign douta[7] = \<const0> ;
  assign douta[6] = \<const0> ;
  assign douta[5] = \<const0> ;
  assign douta[4] = \<const0> ;
  assign douta[3] = \<const0> ;
  assign douta[2] = \<const0> ;
  assign douta[1] = \<const0> ;
  assign douta[0] = \<const0> ;
  assign doutb[71] = \<const0> ;
  assign doutb[70] = \<const0> ;
  assign doutb[69] = \<const0> ;
  assign doutb[68] = \<const0> ;
  assign doutb[67] = \<const0> ;
  assign doutb[66] = \<const0> ;
  assign doutb[65] = \<const0> ;
  assign doutb[64] = \<const0> ;
  assign doutb[63:0] = \^doutb [63:0];
  assign sbiterra = \<const0> ;
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* \MEM.PORTA.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTA.ADDRESS_END  = "511" *) 
  (* \MEM.PORTA.DATA_BIT_LAYOUT  = "p8_d64" *) 
  (* \MEM.PORTA.DATA_LSB  = "0" *) 
  (* \MEM.PORTA.DATA_MSB  = "71" *) 
  (* \MEM.PORTB.ADDRESS_BEGIN  = "0" *) 
  (* \MEM.PORTB.ADDRESS_END  = "511" *) 
  (* \MEM.PORTB.DATA_BIT_LAYOUT  = "p8_d64" *) 
  (* \MEM.PORTB.DATA_LSB  = "0" *) 
  (* \MEM.PORTB.DATA_MSB  = "71" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) 
  (* RTL_RAM_BITS = "36864" *) 
  (* RTL_RAM_NAME = "inst/ram_top/MASTER_READ_BRAM/xpm_memory_sdpram_inst_loop[0].xpm_memory_sdpram_inst/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "511" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "71" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(0),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("SDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(72),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(0),
    .WRITE_WIDTH_B(72)) 
    \gen_wr_a.gen_word_narrow.mem_reg 
       (.ADDRARDADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(clka),
        .CLKBWRCLK(clka),
        .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ),
        .DIADI(dina[31:0]),
        .DIBDI(dina[63:32]),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO(\^doutb [31:0]),
        .DOBDO(\^doutb [63:32]),
        .DOPADOP({\gen_wr_a.gen_word_narrow.mem_reg_n_68 ,\gen_wr_a.gen_word_narrow.mem_reg_n_69 ,\gen_wr_a.gen_word_narrow.mem_reg_n_70 ,\gen_wr_a.gen_word_narrow.mem_reg_n_71 }),
        .DOPBDOP({\gen_wr_a.gen_word_narrow.mem_reg_n_72 ,\gen_wr_a.gen_word_narrow.mem_reg_n_73 ,\gen_wr_a.gen_word_narrow.mem_reg_n_74 ,\gen_wr_a.gen_word_narrow.mem_reg_n_75 }),
        .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(1'b1),
        .ENBWREN(1'b1),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b0),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ),
        .WEA({1'b0,1'b0,1'b0,1'b0}),
        .WEBWE({wea,wea,wea,wea,wea,wea,wea,wea}));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "36" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "common_clock" *) 
(* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "no_ecc" *) (* ECC_TYPE = "NONE" *) 
(* IGNORE_INIT_SYNTH = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) 
(* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "block" *) (* MEMORY_SIZE = "18432" *) 
(* MESSAGE_CONTROL = "0" *) (* ORIG_REF_NAME = "xpm_memory_sdpram" *) (* P_CLOCKING_MODE = "0" *) 
(* P_ECC_MODE = "0" *) (* P_MEMORY_OPTIMIZATION = "1" *) (* P_MEMORY_PRIMITIVE = "2" *) 
(* P_WAKEUP_TIME = "0" *) (* P_WRITE_MODE_B = "1" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_B = "36" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* WAKEUP_TIME = "disable_sleep" *) (* WRITE_DATA_WIDTH_A = "36" *) (* WRITE_MODE_B = "read_first" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
module xdma_0_xpm_memory_sdpram
   (sleep,
    clka,
    ena,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    addrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input ena;
  input [0:0]wea;
  input [8:0]addra;
  input [35:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [8:0]addrb;
  output [35:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [35:0]dina;
  wire [31:0]\^doutb ;
  wire regceb;
  wire [0:0]wea;
  wire NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED;
  wire [35:0]NLW_xpm_memory_base_inst_douta_UNCONNECTED;
  wire [35:32]NLW_xpm_memory_base_inst_doutb_UNCONNECTED;

  assign dbiterrb = \<const0> ;
  assign doutb[35] = \<const0> ;
  assign doutb[34] = \<const0> ;
  assign doutb[33] = \<const0> ;
  assign doutb[32] = \<const0> ;
  assign doutb[31:0] = \^doutb [31:0];
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* ADDR_WIDTH_A = "9" *) 
  (* ADDR_WIDTH_B = "9" *) 
  (* AUTO_SLEEP_TIME = "0" *) 
  (* BYTE_WRITE_WIDTH_A = "36" *) 
  (* BYTE_WRITE_WIDTH_B = "36" *) 
  (* CASCADE_HEIGHT = "0" *) 
  (* CLOCKING_MODE = "0" *) 
  (* ECC_BIT_RANGE = "[7:0]" *) 
  (* ECC_MODE = "0" *) 
  (* ECC_TYPE = "NONE" *) 
  (* IGNORE_INIT_SYNTH = "0" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* MAX_NUM_CHAR = "0" *) 
  (* \MEM.ADDRESS_SPACE  *) 
  (* \MEM.ADDRESS_SPACE_BEGIN  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_LSB  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_MSB  = "35" *) 
  (* \MEM.ADDRESS_SPACE_END  = "511" *) 
  (* \MEM.CORE_MEMORY_WIDTH  = "36" *) 
  (* MEMORY_INIT_FILE = "none" *) 
  (* MEMORY_INIT_PARAM = "" *) 
  (* MEMORY_OPTIMIZATION = "true" *) 
  (* MEMORY_PRIMITIVE = "2" *) 
  (* MEMORY_SIZE = "18432" *) 
  (* MEMORY_TYPE = "1" *) 
  (* MESSAGE_CONTROL = "0" *) 
  (* NUM_CHAR_LOC = "0" *) 
  (* P_ECC_MODE = "no_ecc" *) 
  (* P_ENABLE_BYTE_WRITE_A = "0" *) 
  (* P_ENABLE_BYTE_WRITE_B = "0" *) 
  (* P_MAX_DEPTH_DATA = "512" *) 
  (* P_MEMORY_OPT = "yes" *) 
  (* P_MEMORY_PRIMITIVE = "block" *) 
  (* P_MIN_WIDTH_DATA = "36" *) 
  (* P_MIN_WIDTH_DATA_A = "36" *) 
  (* P_MIN_WIDTH_DATA_B = "36" *) 
  (* P_MIN_WIDTH_DATA_ECC = "36" *) 
  (* P_MIN_WIDTH_DATA_LDW = "4" *) 
  (* P_MIN_WIDTH_DATA_SHFT = "36" *) 
  (* P_NUM_COLS_WRITE_A = "1" *) 
  (* P_NUM_COLS_WRITE_B = "1" *) 
  (* P_NUM_ROWS_READ_A = "1" *) 
  (* P_NUM_ROWS_READ_B = "1" *) 
  (* P_NUM_ROWS_WRITE_A = "1" *) 
  (* P_NUM_ROWS_WRITE_B = "1" *) 
  (* P_SDP_WRITE_MODE = "yes" *) 
  (* P_WIDTH_ADDR_LSB_READ_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) 
  (* P_WIDTH_ADDR_READ_A = "9" *) 
  (* P_WIDTH_ADDR_READ_B = "9" *) 
  (* P_WIDTH_ADDR_WRITE_A = "9" *) 
  (* P_WIDTH_ADDR_WRITE_B = "9" *) 
  (* P_WIDTH_COL_WRITE_A = "36" *) 
  (* P_WIDTH_COL_WRITE_B = "36" *) 
  (* RAM_DECOMP = "auto" *) 
  (* READ_DATA_WIDTH_A = "36" *) 
  (* READ_DATA_WIDTH_B = "36" *) 
  (* READ_LATENCY_A = "2" *) 
  (* READ_LATENCY_B = "2" *) 
  (* READ_RESET_VALUE_A = "0" *) 
  (* READ_RESET_VALUE_B = "0" *) 
  (* RST_MODE_A = "SYNC" *) 
  (* RST_MODE_B = "SYNC" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_EMBEDDED_CONSTRAINT = "0" *) 
  (* USE_MEM_INIT = "1" *) 
  (* USE_MEM_INIT_MMI = "0" *) 
  (* VERSION = "0" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WRITE_DATA_WIDTH_A = "36" *) 
  (* WRITE_DATA_WIDTH_B = "36" *) 
  (* WRITE_MODE_A = "1" *) 
  (* WRITE_MODE_B = "1" *) 
  (* WRITE_PROTECT = "1" *) 
  (* XPM_MODULE = "TRUE" *) 
  (* rsta_loop_iter = "36" *) 
  (* rstb_loop_iter = "36" *) 
  xdma_0_xpm_memory_base xpm_memory_base_inst
       (.addra(addra),
        .addrb(addrb),
        .clka(clka),
        .clkb(1'b0),
        .dbiterra(NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED),
        .dbiterrb(NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED),
        .dina(dina),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(NLW_xpm_memory_base_inst_douta_UNCONNECTED[35:0]),
        .doutb({NLW_xpm_memory_base_inst_doutb_UNCONNECTED[35:32],\^doutb }),
        .ena(1'b0),
        .enb(1'b1),
        .injectdbiterra(1'b0),
        .injectdbiterrb(1'b0),
        .injectsbiterra(1'b0),
        .injectsbiterrb(1'b0),
        .regcea(1'b0),
        .regceb(regceb),
        .rsta(1'b0),
        .rstb(1'b0),
        .sbiterra(NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED),
        .sbiterrb(NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED),
        .sleep(1'b0),
        .wea(wea),
        .web(1'b0));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "36" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "common_clock" *) 
(* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "no_ecc" *) (* ECC_TYPE = "NONE" *) 
(* IGNORE_INIT_SYNTH = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) 
(* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "block" *) (* MEMORY_SIZE = "18432" *) 
(* MESSAGE_CONTROL = "0" *) (* ORIG_REF_NAME = "xpm_memory_sdpram" *) (* P_CLOCKING_MODE = "0" *) 
(* P_ECC_MODE = "0" *) (* P_MEMORY_OPTIMIZATION = "1" *) (* P_MEMORY_PRIMITIVE = "2" *) 
(* P_WAKEUP_TIME = "0" *) (* P_WRITE_MODE_B = "1" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_B = "36" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* WAKEUP_TIME = "disable_sleep" *) (* WRITE_DATA_WIDTH_A = "36" *) (* WRITE_MODE_B = "read_first" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
module xdma_0_xpm_memory_sdpram__14
   (sleep,
    clka,
    ena,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    addrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input ena;
  input [0:0]wea;
  input [8:0]addra;
  input [35:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [8:0]addrb;
  output [35:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [35:0]dina;
  wire [31:0]\^doutb ;
  wire regceb;
  wire [0:0]wea;
  wire NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED;
  wire [35:0]NLW_xpm_memory_base_inst_douta_UNCONNECTED;
  wire [35:32]NLW_xpm_memory_base_inst_doutb_UNCONNECTED;

  assign dbiterrb = \<const0> ;
  assign doutb[35] = \<const0> ;
  assign doutb[34] = \<const0> ;
  assign doutb[33] = \<const0> ;
  assign doutb[32] = \<const0> ;
  assign doutb[31:0] = \^doutb [31:0];
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* ADDR_WIDTH_A = "9" *) 
  (* ADDR_WIDTH_B = "9" *) 
  (* AUTO_SLEEP_TIME = "0" *) 
  (* BYTE_WRITE_WIDTH_A = "36" *) 
  (* BYTE_WRITE_WIDTH_B = "36" *) 
  (* CASCADE_HEIGHT = "0" *) 
  (* CLOCKING_MODE = "0" *) 
  (* ECC_BIT_RANGE = "[7:0]" *) 
  (* ECC_MODE = "0" *) 
  (* ECC_TYPE = "NONE" *) 
  (* IGNORE_INIT_SYNTH = "0" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* MAX_NUM_CHAR = "0" *) 
  (* \MEM.ADDRESS_SPACE  *) 
  (* \MEM.ADDRESS_SPACE_BEGIN  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_LSB  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_MSB  = "35" *) 
  (* \MEM.ADDRESS_SPACE_END  = "511" *) 
  (* \MEM.CORE_MEMORY_WIDTH  = "36" *) 
  (* MEMORY_INIT_FILE = "none" *) 
  (* MEMORY_INIT_PARAM = "" *) 
  (* MEMORY_OPTIMIZATION = "true" *) 
  (* MEMORY_PRIMITIVE = "2" *) 
  (* MEMORY_SIZE = "18432" *) 
  (* MEMORY_TYPE = "1" *) 
  (* MESSAGE_CONTROL = "0" *) 
  (* NUM_CHAR_LOC = "0" *) 
  (* P_ECC_MODE = "no_ecc" *) 
  (* P_ENABLE_BYTE_WRITE_A = "0" *) 
  (* P_ENABLE_BYTE_WRITE_B = "0" *) 
  (* P_MAX_DEPTH_DATA = "512" *) 
  (* P_MEMORY_OPT = "yes" *) 
  (* P_MEMORY_PRIMITIVE = "block" *) 
  (* P_MIN_WIDTH_DATA = "36" *) 
  (* P_MIN_WIDTH_DATA_A = "36" *) 
  (* P_MIN_WIDTH_DATA_B = "36" *) 
  (* P_MIN_WIDTH_DATA_ECC = "36" *) 
  (* P_MIN_WIDTH_DATA_LDW = "4" *) 
  (* P_MIN_WIDTH_DATA_SHFT = "36" *) 
  (* P_NUM_COLS_WRITE_A = "1" *) 
  (* P_NUM_COLS_WRITE_B = "1" *) 
  (* P_NUM_ROWS_READ_A = "1" *) 
  (* P_NUM_ROWS_READ_B = "1" *) 
  (* P_NUM_ROWS_WRITE_A = "1" *) 
  (* P_NUM_ROWS_WRITE_B = "1" *) 
  (* P_SDP_WRITE_MODE = "yes" *) 
  (* P_WIDTH_ADDR_LSB_READ_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) 
  (* P_WIDTH_ADDR_READ_A = "9" *) 
  (* P_WIDTH_ADDR_READ_B = "9" *) 
  (* P_WIDTH_ADDR_WRITE_A = "9" *) 
  (* P_WIDTH_ADDR_WRITE_B = "9" *) 
  (* P_WIDTH_COL_WRITE_A = "36" *) 
  (* P_WIDTH_COL_WRITE_B = "36" *) 
  (* RAM_DECOMP = "auto" *) 
  (* READ_DATA_WIDTH_A = "36" *) 
  (* READ_DATA_WIDTH_B = "36" *) 
  (* READ_LATENCY_A = "2" *) 
  (* READ_LATENCY_B = "2" *) 
  (* READ_RESET_VALUE_A = "0" *) 
  (* READ_RESET_VALUE_B = "0" *) 
  (* RST_MODE_A = "SYNC" *) 
  (* RST_MODE_B = "SYNC" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_EMBEDDED_CONSTRAINT = "0" *) 
  (* USE_MEM_INIT = "1" *) 
  (* USE_MEM_INIT_MMI = "0" *) 
  (* VERSION = "0" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WRITE_DATA_WIDTH_A = "36" *) 
  (* WRITE_DATA_WIDTH_B = "36" *) 
  (* WRITE_MODE_A = "1" *) 
  (* WRITE_MODE_B = "1" *) 
  (* WRITE_PROTECT = "1" *) 
  (* XPM_MODULE = "TRUE" *) 
  (* rsta_loop_iter = "36" *) 
  (* rstb_loop_iter = "36" *) 
  xdma_0_xpm_memory_base__14 xpm_memory_base_inst
       (.addra(addra),
        .addrb(addrb),
        .clka(clka),
        .clkb(1'b0),
        .dbiterra(NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED),
        .dbiterrb(NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED),
        .dina({1'b0,1'b0,1'b0,1'b0,dina[31:0]}),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(NLW_xpm_memory_base_inst_douta_UNCONNECTED[35:0]),
        .doutb({NLW_xpm_memory_base_inst_doutb_UNCONNECTED[35:32],\^doutb }),
        .ena(1'b0),
        .enb(1'b1),
        .injectdbiterra(1'b0),
        .injectdbiterrb(1'b0),
        .injectsbiterra(1'b0),
        .injectsbiterrb(1'b0),
        .regcea(1'b0),
        .regceb(regceb),
        .rsta(1'b0),
        .rstb(1'b0),
        .sbiterra(NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED),
        .sbiterrb(NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED),
        .sleep(1'b0),
        .wea(wea),
        .web(1'b0));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "36" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "common_clock" *) 
(* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "no_ecc" *) (* ECC_TYPE = "NONE" *) 
(* IGNORE_INIT_SYNTH = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) 
(* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "block" *) (* MEMORY_SIZE = "18432" *) 
(* MESSAGE_CONTROL = "0" *) (* ORIG_REF_NAME = "xpm_memory_sdpram" *) (* P_CLOCKING_MODE = "0" *) 
(* P_ECC_MODE = "0" *) (* P_MEMORY_OPTIMIZATION = "1" *) (* P_MEMORY_PRIMITIVE = "2" *) 
(* P_WAKEUP_TIME = "0" *) (* P_WRITE_MODE_B = "1" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_B = "36" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* WAKEUP_TIME = "disable_sleep" *) (* WRITE_DATA_WIDTH_A = "36" *) (* WRITE_MODE_B = "read_first" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
module xdma_0_xpm_memory_sdpram__15
   (sleep,
    clka,
    ena,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    addrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input ena;
  input [0:0]wea;
  input [8:0]addra;
  input [35:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [8:0]addrb;
  output [35:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [35:0]dina;
  wire [31:0]\^doutb ;
  wire regceb;
  wire [0:0]wea;
  wire NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED;
  wire [35:0]NLW_xpm_memory_base_inst_douta_UNCONNECTED;
  wire [35:32]NLW_xpm_memory_base_inst_doutb_UNCONNECTED;

  assign dbiterrb = \<const0> ;
  assign doutb[35] = \<const0> ;
  assign doutb[34] = \<const0> ;
  assign doutb[33] = \<const0> ;
  assign doutb[32] = \<const0> ;
  assign doutb[31:0] = \^doutb [31:0];
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* ADDR_WIDTH_A = "9" *) 
  (* ADDR_WIDTH_B = "9" *) 
  (* AUTO_SLEEP_TIME = "0" *) 
  (* BYTE_WRITE_WIDTH_A = "36" *) 
  (* BYTE_WRITE_WIDTH_B = "36" *) 
  (* CASCADE_HEIGHT = "0" *) 
  (* CLOCKING_MODE = "0" *) 
  (* ECC_BIT_RANGE = "[7:0]" *) 
  (* ECC_MODE = "0" *) 
  (* ECC_TYPE = "NONE" *) 
  (* IGNORE_INIT_SYNTH = "0" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* MAX_NUM_CHAR = "0" *) 
  (* \MEM.ADDRESS_SPACE  *) 
  (* \MEM.ADDRESS_SPACE_BEGIN  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_LSB  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_MSB  = "35" *) 
  (* \MEM.ADDRESS_SPACE_END  = "511" *) 
  (* \MEM.CORE_MEMORY_WIDTH  = "36" *) 
  (* MEMORY_INIT_FILE = "none" *) 
  (* MEMORY_INIT_PARAM = "" *) 
  (* MEMORY_OPTIMIZATION = "true" *) 
  (* MEMORY_PRIMITIVE = "2" *) 
  (* MEMORY_SIZE = "18432" *) 
  (* MEMORY_TYPE = "1" *) 
  (* MESSAGE_CONTROL = "0" *) 
  (* NUM_CHAR_LOC = "0" *) 
  (* P_ECC_MODE = "no_ecc" *) 
  (* P_ENABLE_BYTE_WRITE_A = "0" *) 
  (* P_ENABLE_BYTE_WRITE_B = "0" *) 
  (* P_MAX_DEPTH_DATA = "512" *) 
  (* P_MEMORY_OPT = "yes" *) 
  (* P_MEMORY_PRIMITIVE = "block" *) 
  (* P_MIN_WIDTH_DATA = "36" *) 
  (* P_MIN_WIDTH_DATA_A = "36" *) 
  (* P_MIN_WIDTH_DATA_B = "36" *) 
  (* P_MIN_WIDTH_DATA_ECC = "36" *) 
  (* P_MIN_WIDTH_DATA_LDW = "4" *) 
  (* P_MIN_WIDTH_DATA_SHFT = "36" *) 
  (* P_NUM_COLS_WRITE_A = "1" *) 
  (* P_NUM_COLS_WRITE_B = "1" *) 
  (* P_NUM_ROWS_READ_A = "1" *) 
  (* P_NUM_ROWS_READ_B = "1" *) 
  (* P_NUM_ROWS_WRITE_A = "1" *) 
  (* P_NUM_ROWS_WRITE_B = "1" *) 
  (* P_SDP_WRITE_MODE = "yes" *) 
  (* P_WIDTH_ADDR_LSB_READ_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) 
  (* P_WIDTH_ADDR_READ_A = "9" *) 
  (* P_WIDTH_ADDR_READ_B = "9" *) 
  (* P_WIDTH_ADDR_WRITE_A = "9" *) 
  (* P_WIDTH_ADDR_WRITE_B = "9" *) 
  (* P_WIDTH_COL_WRITE_A = "36" *) 
  (* P_WIDTH_COL_WRITE_B = "36" *) 
  (* RAM_DECOMP = "auto" *) 
  (* READ_DATA_WIDTH_A = "36" *) 
  (* READ_DATA_WIDTH_B = "36" *) 
  (* READ_LATENCY_A = "2" *) 
  (* READ_LATENCY_B = "2" *) 
  (* READ_RESET_VALUE_A = "0" *) 
  (* READ_RESET_VALUE_B = "0" *) 
  (* RST_MODE_A = "SYNC" *) 
  (* RST_MODE_B = "SYNC" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_EMBEDDED_CONSTRAINT = "0" *) 
  (* USE_MEM_INIT = "1" *) 
  (* USE_MEM_INIT_MMI = "0" *) 
  (* VERSION = "0" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WRITE_DATA_WIDTH_A = "36" *) 
  (* WRITE_DATA_WIDTH_B = "36" *) 
  (* WRITE_MODE_A = "1" *) 
  (* WRITE_MODE_B = "1" *) 
  (* WRITE_PROTECT = "1" *) 
  (* XPM_MODULE = "TRUE" *) 
  (* rsta_loop_iter = "36" *) 
  (* rstb_loop_iter = "36" *) 
  xdma_0_xpm_memory_base__15 xpm_memory_base_inst
       (.addra(addra),
        .addrb(addrb),
        .clka(clka),
        .clkb(1'b0),
        .dbiterra(NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED),
        .dbiterrb(NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED),
        .dina({1'b0,1'b0,1'b0,1'b0,dina[31:0]}),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(NLW_xpm_memory_base_inst_douta_UNCONNECTED[35:0]),
        .doutb({NLW_xpm_memory_base_inst_doutb_UNCONNECTED[35:32],\^doutb }),
        .ena(1'b0),
        .enb(1'b1),
        .injectdbiterra(1'b0),
        .injectdbiterrb(1'b0),
        .injectsbiterra(1'b0),
        .injectsbiterrb(1'b0),
        .regcea(1'b0),
        .regceb(regceb),
        .rsta(1'b0),
        .rstb(1'b0),
        .sbiterra(NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED),
        .sbiterrb(NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED),
        .sleep(1'b0),
        .wea(wea),
        .web(1'b0));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "36" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "common_clock" *) 
(* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "no_ecc" *) (* ECC_TYPE = "NONE" *) 
(* IGNORE_INIT_SYNTH = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) 
(* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "block" *) (* MEMORY_SIZE = "18432" *) 
(* MESSAGE_CONTROL = "0" *) (* ORIG_REF_NAME = "xpm_memory_sdpram" *) (* P_CLOCKING_MODE = "0" *) 
(* P_ECC_MODE = "0" *) (* P_MEMORY_OPTIMIZATION = "1" *) (* P_MEMORY_PRIMITIVE = "2" *) 
(* P_WAKEUP_TIME = "0" *) (* P_WRITE_MODE_B = "1" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_B = "36" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* WAKEUP_TIME = "disable_sleep" *) (* WRITE_DATA_WIDTH_A = "36" *) (* WRITE_MODE_B = "read_first" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
module xdma_0_xpm_memory_sdpram__22
   (sleep,
    clka,
    ena,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    addrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input ena;
  input [0:0]wea;
  input [8:0]addra;
  input [35:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [8:0]addrb;
  output [35:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [35:0]dina;
  wire [31:0]\^doutb ;
  wire regceb;
  wire [0:0]wea;
  wire NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED;
  wire [35:0]NLW_xpm_memory_base_inst_douta_UNCONNECTED;
  wire [35:32]NLW_xpm_memory_base_inst_doutb_UNCONNECTED;

  assign dbiterrb = \<const0> ;
  assign doutb[35] = \<const0> ;
  assign doutb[34] = \<const0> ;
  assign doutb[33] = \<const0> ;
  assign doutb[32] = \<const0> ;
  assign doutb[31:0] = \^doutb [31:0];
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* ADDR_WIDTH_A = "9" *) 
  (* ADDR_WIDTH_B = "9" *) 
  (* AUTO_SLEEP_TIME = "0" *) 
  (* BYTE_WRITE_WIDTH_A = "36" *) 
  (* BYTE_WRITE_WIDTH_B = "36" *) 
  (* CASCADE_HEIGHT = "0" *) 
  (* CLOCKING_MODE = "0" *) 
  (* ECC_BIT_RANGE = "[7:0]" *) 
  (* ECC_MODE = "0" *) 
  (* ECC_TYPE = "NONE" *) 
  (* IGNORE_INIT_SYNTH = "0" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* MAX_NUM_CHAR = "0" *) 
  (* \MEM.ADDRESS_SPACE  *) 
  (* \MEM.ADDRESS_SPACE_BEGIN  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_LSB  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_MSB  = "35" *) 
  (* \MEM.ADDRESS_SPACE_END  = "511" *) 
  (* \MEM.CORE_MEMORY_WIDTH  = "36" *) 
  (* MEMORY_INIT_FILE = "none" *) 
  (* MEMORY_INIT_PARAM = "" *) 
  (* MEMORY_OPTIMIZATION = "true" *) 
  (* MEMORY_PRIMITIVE = "2" *) 
  (* MEMORY_SIZE = "18432" *) 
  (* MEMORY_TYPE = "1" *) 
  (* MESSAGE_CONTROL = "0" *) 
  (* NUM_CHAR_LOC = "0" *) 
  (* P_ECC_MODE = "no_ecc" *) 
  (* P_ENABLE_BYTE_WRITE_A = "0" *) 
  (* P_ENABLE_BYTE_WRITE_B = "0" *) 
  (* P_MAX_DEPTH_DATA = "512" *) 
  (* P_MEMORY_OPT = "yes" *) 
  (* P_MEMORY_PRIMITIVE = "block" *) 
  (* P_MIN_WIDTH_DATA = "36" *) 
  (* P_MIN_WIDTH_DATA_A = "36" *) 
  (* P_MIN_WIDTH_DATA_B = "36" *) 
  (* P_MIN_WIDTH_DATA_ECC = "36" *) 
  (* P_MIN_WIDTH_DATA_LDW = "4" *) 
  (* P_MIN_WIDTH_DATA_SHFT = "36" *) 
  (* P_NUM_COLS_WRITE_A = "1" *) 
  (* P_NUM_COLS_WRITE_B = "1" *) 
  (* P_NUM_ROWS_READ_A = "1" *) 
  (* P_NUM_ROWS_READ_B = "1" *) 
  (* P_NUM_ROWS_WRITE_A = "1" *) 
  (* P_NUM_ROWS_WRITE_B = "1" *) 
  (* P_SDP_WRITE_MODE = "yes" *) 
  (* P_WIDTH_ADDR_LSB_READ_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) 
  (* P_WIDTH_ADDR_READ_A = "9" *) 
  (* P_WIDTH_ADDR_READ_B = "9" *) 
  (* P_WIDTH_ADDR_WRITE_A = "9" *) 
  (* P_WIDTH_ADDR_WRITE_B = "9" *) 
  (* P_WIDTH_COL_WRITE_A = "36" *) 
  (* P_WIDTH_COL_WRITE_B = "36" *) 
  (* RAM_DECOMP = "auto" *) 
  (* READ_DATA_WIDTH_A = "36" *) 
  (* READ_DATA_WIDTH_B = "36" *) 
  (* READ_LATENCY_A = "2" *) 
  (* READ_LATENCY_B = "2" *) 
  (* READ_RESET_VALUE_A = "0" *) 
  (* READ_RESET_VALUE_B = "0" *) 
  (* RST_MODE_A = "SYNC" *) 
  (* RST_MODE_B = "SYNC" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_EMBEDDED_CONSTRAINT = "0" *) 
  (* USE_MEM_INIT = "1" *) 
  (* USE_MEM_INIT_MMI = "0" *) 
  (* VERSION = "0" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WRITE_DATA_WIDTH_A = "36" *) 
  (* WRITE_DATA_WIDTH_B = "36" *) 
  (* WRITE_MODE_A = "1" *) 
  (* WRITE_MODE_B = "1" *) 
  (* WRITE_PROTECT = "1" *) 
  (* XPM_MODULE = "TRUE" *) 
  (* rsta_loop_iter = "36" *) 
  (* rstb_loop_iter = "36" *) 
  xdma_0_xpm_memory_base__22 xpm_memory_base_inst
       (.addra(addra),
        .addrb(addrb),
        .clka(clka),
        .clkb(1'b0),
        .dbiterra(NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED),
        .dbiterrb(NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED),
        .dina(dina),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(NLW_xpm_memory_base_inst_douta_UNCONNECTED[35:0]),
        .doutb({NLW_xpm_memory_base_inst_doutb_UNCONNECTED[35:32],\^doutb }),
        .ena(1'b0),
        .enb(1'b1),
        .injectdbiterra(1'b0),
        .injectdbiterrb(1'b0),
        .injectsbiterra(1'b0),
        .injectsbiterrb(1'b0),
        .regcea(1'b0),
        .regceb(regceb),
        .rsta(1'b0),
        .rstb(1'b0),
        .sbiterra(NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED),
        .sbiterrb(NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED),
        .sleep(1'b0),
        .wea(wea),
        .web(1'b0));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "72" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "common_clock" *) 
(* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "no_ecc" *) (* ECC_TYPE = "NONE" *) 
(* IGNORE_INIT_SYNTH = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) 
(* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "block" *) (* MEMORY_SIZE = "36864" *) 
(* MESSAGE_CONTROL = "0" *) (* ORIG_REF_NAME = "xpm_memory_sdpram" *) (* P_CLOCKING_MODE = "0" *) 
(* P_ECC_MODE = "0" *) (* P_MEMORY_OPTIMIZATION = "1" *) (* P_MEMORY_PRIMITIVE = "2" *) 
(* P_WAKEUP_TIME = "0" *) (* P_WRITE_MODE_B = "1" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_B = "72" *) (* READ_LATENCY_B = "1" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* WAKEUP_TIME = "disable_sleep" *) (* WRITE_DATA_WIDTH_A = "72" *) (* WRITE_MODE_B = "read_first" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
module xdma_0_xpm_memory_sdpram__parameterized0
   (sleep,
    clka,
    ena,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    addrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input ena;
  input [0:0]wea;
  input [8:0]addra;
  input [71:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [8:0]addrb;
  output [71:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [71:0]dina;
  wire [71:0]doutb;
  wire [0:0]wea;
  wire NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED;
  wire [71:0]NLW_xpm_memory_base_inst_douta_UNCONNECTED;

  assign dbiterrb = \<const0> ;
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* ADDR_WIDTH_A = "9" *) 
  (* ADDR_WIDTH_B = "9" *) 
  (* AUTO_SLEEP_TIME = "0" *) 
  (* BYTE_WRITE_WIDTH_A = "72" *) 
  (* BYTE_WRITE_WIDTH_B = "72" *) 
  (* CASCADE_HEIGHT = "0" *) 
  (* CLOCKING_MODE = "0" *) 
  (* ECC_BIT_RANGE = "[7:0]" *) 
  (* ECC_MODE = "0" *) 
  (* ECC_TYPE = "NONE" *) 
  (* IGNORE_INIT_SYNTH = "0" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* MAX_NUM_CHAR = "0" *) 
  (* \MEM.ADDRESS_SPACE  *) 
  (* \MEM.ADDRESS_SPACE_BEGIN  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_LSB  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_MSB  = "71" *) 
  (* \MEM.ADDRESS_SPACE_END  = "511" *) 
  (* \MEM.CORE_MEMORY_WIDTH  = "72" *) 
  (* MEMORY_INIT_FILE = "none" *) 
  (* MEMORY_INIT_PARAM = "" *) 
  (* MEMORY_OPTIMIZATION = "true" *) 
  (* MEMORY_PRIMITIVE = "2" *) 
  (* MEMORY_SIZE = "36864" *) 
  (* MEMORY_TYPE = "1" *) 
  (* MESSAGE_CONTROL = "0" *) 
  (* NUM_CHAR_LOC = "0" *) 
  (* P_ECC_MODE = "no_ecc" *) 
  (* P_ENABLE_BYTE_WRITE_A = "0" *) 
  (* P_ENABLE_BYTE_WRITE_B = "0" *) 
  (* P_MAX_DEPTH_DATA = "512" *) 
  (* P_MEMORY_OPT = "yes" *) 
  (* P_MEMORY_PRIMITIVE = "block" *) 
  (* P_MIN_WIDTH_DATA = "72" *) 
  (* P_MIN_WIDTH_DATA_A = "72" *) 
  (* P_MIN_WIDTH_DATA_B = "72" *) 
  (* P_MIN_WIDTH_DATA_ECC = "72" *) 
  (* P_MIN_WIDTH_DATA_LDW = "4" *) 
  (* P_MIN_WIDTH_DATA_SHFT = "72" *) 
  (* P_NUM_COLS_WRITE_A = "1" *) 
  (* P_NUM_COLS_WRITE_B = "1" *) 
  (* P_NUM_ROWS_READ_A = "1" *) 
  (* P_NUM_ROWS_READ_B = "1" *) 
  (* P_NUM_ROWS_WRITE_A = "1" *) 
  (* P_NUM_ROWS_WRITE_B = "1" *) 
  (* P_SDP_WRITE_MODE = "yes" *) 
  (* P_WIDTH_ADDR_LSB_READ_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) 
  (* P_WIDTH_ADDR_READ_A = "9" *) 
  (* P_WIDTH_ADDR_READ_B = "9" *) 
  (* P_WIDTH_ADDR_WRITE_A = "9" *) 
  (* P_WIDTH_ADDR_WRITE_B = "9" *) 
  (* P_WIDTH_COL_WRITE_A = "72" *) 
  (* P_WIDTH_COL_WRITE_B = "72" *) 
  (* RAM_DECOMP = "auto" *) 
  (* READ_DATA_WIDTH_A = "72" *) 
  (* READ_DATA_WIDTH_B = "72" *) 
  (* READ_LATENCY_A = "2" *) 
  (* READ_LATENCY_B = "1" *) 
  (* READ_RESET_VALUE_A = "0" *) 
  (* READ_RESET_VALUE_B = "0" *) 
  (* RST_MODE_A = "SYNC" *) 
  (* RST_MODE_B = "SYNC" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_EMBEDDED_CONSTRAINT = "0" *) 
  (* USE_MEM_INIT = "1" *) 
  (* USE_MEM_INIT_MMI = "0" *) 
  (* VERSION = "0" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WRITE_DATA_WIDTH_A = "72" *) 
  (* WRITE_DATA_WIDTH_B = "72" *) 
  (* WRITE_MODE_A = "1" *) 
  (* WRITE_MODE_B = "1" *) 
  (* WRITE_PROTECT = "1" *) 
  (* XPM_MODULE = "TRUE" *) 
  (* rsta_loop_iter = "72" *) 
  (* rstb_loop_iter = "72" *) 
  xdma_0_xpm_memory_base__parameterized0 xpm_memory_base_inst
       (.addra(addra),
        .addrb(addrb),
        .clka(clka),
        .clkb(1'b0),
        .dbiterra(NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED),
        .dbiterrb(NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED),
        .dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[63:0]}),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(NLW_xpm_memory_base_inst_douta_UNCONNECTED[71:0]),
        .doutb(doutb),
        .ena(1'b0),
        .enb(1'b1),
        .injectdbiterra(1'b0),
        .injectdbiterrb(1'b0),
        .injectsbiterra(1'b0),
        .injectsbiterrb(1'b0),
        .regcea(1'b0),
        .regceb(1'b0),
        .rsta(1'b0),
        .rstb(1'b0),
        .sbiterra(NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED),
        .sbiterrb(NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED),
        .sleep(1'b0),
        .wea(wea),
        .web(1'b0));
endmodule

(* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) 
(* BYTE_WRITE_WIDTH_A = "72" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "common_clock" *) 
(* ECC_BIT_RANGE = "[7:0]" *) (* ECC_MODE = "no_ecc" *) (* ECC_TYPE = "NONE" *) 
(* IGNORE_INIT_SYNTH = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) 
(* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "block" *) (* MEMORY_SIZE = "36864" *) 
(* MESSAGE_CONTROL = "0" *) (* ORIG_REF_NAME = "xpm_memory_sdpram" *) (* P_CLOCKING_MODE = "0" *) 
(* P_ECC_MODE = "0" *) (* P_MEMORY_OPTIMIZATION = "1" *) (* P_MEMORY_PRIMITIVE = "2" *) 
(* P_WAKEUP_TIME = "0" *) (* P_WRITE_MODE_B = "1" *) (* RAM_DECOMP = "auto" *) 
(* READ_DATA_WIDTH_B = "72" *) (* READ_LATENCY_B = "1" *) (* READ_RESET_VALUE_B = "0" *) 
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) 
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "1" *) (* USE_MEM_INIT_MMI = "0" *) 
(* WAKEUP_TIME = "disable_sleep" *) (* WRITE_DATA_WIDTH_A = "72" *) (* WRITE_MODE_B = "read_first" *) 
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
module xdma_0_xpm_memory_sdpram__parameterized0__2
   (sleep,
    clka,
    ena,
    wea,
    addra,
    dina,
    injectsbiterra,
    injectdbiterra,
    clkb,
    rstb,
    enb,
    regceb,
    addrb,
    doutb,
    sbiterrb,
    dbiterrb);
  input sleep;
  input clka;
  input ena;
  input [0:0]wea;
  input [8:0]addra;
  input [71:0]dina;
  input injectsbiterra;
  input injectdbiterra;
  input clkb;
  input rstb;
  input enb;
  input regceb;
  input [8:0]addrb;
  output [71:0]doutb;
  output sbiterrb;
  output dbiterrb;

  wire \<const0> ;
  wire [8:0]addra;
  wire [8:0]addrb;
  wire clka;
  wire [71:0]dina;
  wire [63:0]\^doutb ;
  wire [0:0]wea;
  wire NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED;
  wire NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED;
  wire [71:0]NLW_xpm_memory_base_inst_douta_UNCONNECTED;
  wire [71:64]NLW_xpm_memory_base_inst_doutb_UNCONNECTED;

  assign dbiterrb = \<const0> ;
  assign doutb[71] = \<const0> ;
  assign doutb[70] = \<const0> ;
  assign doutb[69] = \<const0> ;
  assign doutb[68] = \<const0> ;
  assign doutb[67] = \<const0> ;
  assign doutb[66] = \<const0> ;
  assign doutb[65] = \<const0> ;
  assign doutb[64] = \<const0> ;
  assign doutb[63:0] = \^doutb [63:0];
  assign sbiterrb = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* ADDR_WIDTH_A = "9" *) 
  (* ADDR_WIDTH_B = "9" *) 
  (* AUTO_SLEEP_TIME = "0" *) 
  (* BYTE_WRITE_WIDTH_A = "72" *) 
  (* BYTE_WRITE_WIDTH_B = "72" *) 
  (* CASCADE_HEIGHT = "0" *) 
  (* CLOCKING_MODE = "0" *) 
  (* ECC_BIT_RANGE = "[7:0]" *) 
  (* ECC_MODE = "0" *) 
  (* ECC_TYPE = "NONE" *) 
  (* IGNORE_INIT_SYNTH = "0" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* MAX_NUM_CHAR = "0" *) 
  (* \MEM.ADDRESS_SPACE  *) 
  (* \MEM.ADDRESS_SPACE_BEGIN  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_LSB  = "0" *) 
  (* \MEM.ADDRESS_SPACE_DATA_MSB  = "71" *) 
  (* \MEM.ADDRESS_SPACE_END  = "511" *) 
  (* \MEM.CORE_MEMORY_WIDTH  = "72" *) 
  (* MEMORY_INIT_FILE = "none" *) 
  (* MEMORY_INIT_PARAM = "" *) 
  (* MEMORY_OPTIMIZATION = "true" *) 
  (* MEMORY_PRIMITIVE = "2" *) 
  (* MEMORY_SIZE = "36864" *) 
  (* MEMORY_TYPE = "1" *) 
  (* MESSAGE_CONTROL = "0" *) 
  (* NUM_CHAR_LOC = "0" *) 
  (* P_ECC_MODE = "no_ecc" *) 
  (* P_ENABLE_BYTE_WRITE_A = "0" *) 
  (* P_ENABLE_BYTE_WRITE_B = "0" *) 
  (* P_MAX_DEPTH_DATA = "512" *) 
  (* P_MEMORY_OPT = "yes" *) 
  (* P_MEMORY_PRIMITIVE = "block" *) 
  (* P_MIN_WIDTH_DATA = "72" *) 
  (* P_MIN_WIDTH_DATA_A = "72" *) 
  (* P_MIN_WIDTH_DATA_B = "72" *) 
  (* P_MIN_WIDTH_DATA_ECC = "72" *) 
  (* P_MIN_WIDTH_DATA_LDW = "4" *) 
  (* P_MIN_WIDTH_DATA_SHFT = "72" *) 
  (* P_NUM_COLS_WRITE_A = "1" *) 
  (* P_NUM_COLS_WRITE_B = "1" *) 
  (* P_NUM_ROWS_READ_A = "1" *) 
  (* P_NUM_ROWS_READ_B = "1" *) 
  (* P_NUM_ROWS_WRITE_A = "1" *) 
  (* P_NUM_ROWS_WRITE_B = "1" *) 
  (* P_SDP_WRITE_MODE = "yes" *) 
  (* P_WIDTH_ADDR_LSB_READ_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_READ_B = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) 
  (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) 
  (* P_WIDTH_ADDR_READ_A = "9" *) 
  (* P_WIDTH_ADDR_READ_B = "9" *) 
  (* P_WIDTH_ADDR_WRITE_A = "9" *) 
  (* P_WIDTH_ADDR_WRITE_B = "9" *) 
  (* P_WIDTH_COL_WRITE_A = "72" *) 
  (* P_WIDTH_COL_WRITE_B = "72" *) 
  (* RAM_DECOMP = "auto" *) 
  (* READ_DATA_WIDTH_A = "72" *) 
  (* READ_DATA_WIDTH_B = "72" *) 
  (* READ_LATENCY_A = "2" *) 
  (* READ_LATENCY_B = "1" *) 
  (* READ_RESET_VALUE_A = "0" *) 
  (* READ_RESET_VALUE_B = "0" *) 
  (* RST_MODE_A = "SYNC" *) 
  (* RST_MODE_B = "SYNC" *) 
  (* SIM_ASSERT_CHK = "0" *) 
  (* USE_EMBEDDED_CONSTRAINT = "0" *) 
  (* USE_MEM_INIT = "1" *) 
  (* USE_MEM_INIT_MMI = "0" *) 
  (* VERSION = "0" *) 
  (* WAKEUP_TIME = "0" *) 
  (* WRITE_DATA_WIDTH_A = "72" *) 
  (* WRITE_DATA_WIDTH_B = "72" *) 
  (* WRITE_MODE_A = "1" *) 
  (* WRITE_MODE_B = "1" *) 
  (* WRITE_PROTECT = "1" *) 
  (* XPM_MODULE = "TRUE" *) 
  (* rsta_loop_iter = "72" *) 
  (* rstb_loop_iter = "72" *) 
  xdma_0_xpm_memory_base__parameterized0__2 xpm_memory_base_inst
       (.addra(addra),
        .addrb(addrb),
        .clka(clka),
        .clkb(1'b0),
        .dbiterra(NLW_xpm_memory_base_inst_dbiterra_UNCONNECTED),
        .dbiterrb(NLW_xpm_memory_base_inst_dbiterrb_UNCONNECTED),
        .dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[63:0]}),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(NLW_xpm_memory_base_inst_douta_UNCONNECTED[71:0]),
        .doutb({NLW_xpm_memory_base_inst_doutb_UNCONNECTED[71:64],\^doutb }),
        .ena(1'b0),
        .enb(1'b1),
        .injectdbiterra(1'b0),
        .injectdbiterrb(1'b0),
        .injectsbiterra(1'b0),
        .injectsbiterrb(1'b0),
        .regcea(1'b0),
        .regceb(1'b0),
        .rsta(1'b0),
        .rstb(1'b0),
        .sbiterra(NLW_xpm_memory_base_inst_sbiterra_UNCONNECTED),
        .sbiterrb(NLW_xpm_memory_base_inst_sbiterrb_UNCONNECTED),
        .sleep(1'b0),
        .wea(wea),
        .web(1'b0));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2024.1"
`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
jzcdAXR+sYplKV/W5WsnLlqj3qrtqmT9iTYd2y+nN1KrN35vciPFh2VE1F9/OY7uvUSjKLyYMT30
P0a4AWnmxbUBe9oCKd5V9PJXZ8glStN5l5DbU+tXjaBSFHgGGOfVLYHojCiUUOMn6iUc9RxPVEKt
Jjbv9iaS3iy8vfcMxZE=

`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
Wf0HrmD4J7ud3pBBHUa/M8ZMh1UZ3s51/Kbu9yXvp5MZXrutLTE4SrdR0dOqXxUJAernmzqlETUy
hGEykoweimod8gFXLIYLnlrMVc0jAilha0uMTsf1pNEhiSm3qlAI2MwGpaHT8sNs1a4QLt3tSNGr
c8mM2ND7OmUBQQoqwegNJK6Yv1dQhLFocmBrPDyusTM1A/Q073r286xDiO8TQTF/KMjfC09LPR4t
HaZu+1S4A+mPBeUgFeCE/qK2D5ejPoAhzov8iuyWH2H7gyb527xfmEuXL4yPgyPgYEyWIDckvc9r
umkeH6DZBoupqM99jyt7IPd500wnI8P4hGfpJw==

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
aKDnjVh4YN9G7X+bUvZFCPWZFjipHxc+slxjIRAU1NFm77Mh0Ins6wJis1e+7KyJrN5DBLFQg3r2
WDlIXMR0nH/ayaTSpccXZ0V8YxPZEYr+kPntEYUJ2UenevRhoIExqX/Ryl+U3I+WFuXFeaWllGRk
7mIY1DmmspYuc5XwJNY=

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
pg5i17EGOrWaM3gqGzEDYgDeBJg2OHXrJJpTmyUZrDsxNtDQ/iv6rRhNWtzmgihiFJHmjZQAnyvu
OuMxVe8RqkWGDTn3d8Yd5M6vDXqhZRQzIeB7gQkwtcnRC+aMt1DNi2mNlNLVxqQI76ZXusE/ARTv
2vU/5+9R7icl1BfdLFgCxRY7BgpIGNkO4CiRFDT7dbxdV0bTQfWTrcjDDQvmrYSz62xrvZVVKJ61
Tb8Uz6l9QC2ffZQsLsS6cY/MvWKimmmvEBTcSI2zLVFQJksaaQmXqBipEo5w1xU/X8GN7MNpXFCc
psS+4CmlCYmv9+IW/vIBJ9sq5tXybhP6FatXiQ==

`pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
c6FJDJp0866FY2m7AUNztGVC2aYLjQbXoZUjd7qdIpvb8sJ9uKW1oOlyDvV0hNzUGSbKTfr49kAc
bRUn0hauToz92eFcWzWuk4SELuPPdSPLbwwYCfAYYAbgiv4CdaI6Qmtl1cDYZA83MScg7GNWZRmf
vA6boBpJZhwXxN/St6CqxORIcKQCZvZhxOp0ImwHD5hcUPBl39y8RKuHkr+EWMiF+uJqzSe1TGhZ
m3ooqk/7YAH2j3S2f7uEv/1AbGjxSkLOIHuADwFaa5C7HCbOSuRpkQErFNl5u+OY45K/334ttpjc
MdigQ36vkmB9zJd1Xt8roSrAfXRGmv9u07tWIg==

`pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
Ei4Q6mAkYh8L+52ba1+OMBE/jC1MmnoU3gIrySsE7ReAEA6zWZ1574MnZGyv24g0DWMAhyrvDxSL
1Xtz4RTd95OQXhjhfLkbfNgGdrH7qduriajHYvltgNumI4vLt/X1tl6TZ1BYJzdUX4YaAjXsxxFq
yG+/8qIDfTnQVqR1+A0In1O1b/qwr9od0byXGccOp9FEqCCd7v7RqaYIaeUqO2Jy74++oV63j53M
YHCDuIMjx3xXZZfK1o+0XUvv5oBNV2y7ppTvyys4KQgUvvWDwufUxfdEM3dBPvFJ+Pxn8skRbV7D
Zon+Jrz4Gp6u+76Xj16RyL6REbMmQqZd6Sg9uA==

`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2023_11", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
Hqqy3JBuPbnK0pBagbnIYF0w+32iWlKW6TY6Kk1rbWVP0+5xKvlnOwempEpPUPNmw6ceQ6kQSp21
gFc5btmToFc5vYjN6JNmZdRmfhKimPZ1EOyn2pZ7DrhWXgHxPL9UpNpq7brMjUnmL81njQWFOikB
xWnvtFcaEFIv9WcxARSXsf9uv+Ta0fTLaaQEjyhu57YwyBtrfeN1hhiA1Dbnk4pM6zp+H1Wsmebe
NksQe0o/Ms9Un7PuS/vopXCtNhjqQ33oekwHJflNtM80X7uNGWAcZZSqf172qXhJpTE13PUC3e1f
6iE4BimsFkJ9SdQ7KhjtiuJKJbfV4UBlP9uKOw==

`pragma protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`pragma protect key_block
fxduhZPnaRDGtnjlS1plpxz+UAkBtCzaxOXnhInJYrTT7aaX3x41tHfm+81u3s5auPEBbK8ZrQPr
lujXnuKWkC9kkty65XMkVdlgxSfub1jSocz0EzhPpZP4TVmyZ18bcBIOColcCaGFEDM57sqx/ezn
LwKAUi2q5IQgDp1n/+YT9nLUPMjp2AH1PPyE5Jz++j16IRzwqpqHgb5qTbfSYaod1VsyVNBsub5V
SP5/lrlG66CMdIB8PBx3UL8pUbWvYOo6xIC0DxIEcw6V/BZ2W0bQQVCGE3XXX6olYIzTLQ6pe6Ch
HQBAGK6UxTPVwtgXkd2rZeJO9iuATaU/SwTDdmnDtgXbuJVuM9mslP6CTc2qjOd/ZG72e6eGwVkJ
3L8YT9ZrBSiUlybFBhVA1CbxGWiZYyWDvEJHynRcOTY3lSDlQm0DpGZJeOFiOrpJ6lDDuKtIr0RV
ntmbkS69MdVkjgT/7pOGRSuWP1feksN7AAe8J1E03xXQiFBVVReq/+NE

`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
Jz3q9lzcrxfD7F84oZ7wN4GS8oaYeieahSAOQxOLiZnxWJfY8aB0SY6SChFx63fOoLc3+Oy39BJR
tK+shmJHGnXWtb2qDepTiAbH7A4NLHpljLNjstgdwHbBX2JVVgGemCmeyMcTCJFu4mDZtkbkgmHv
oUO4nhT5/KXuQH+VBBGHwrWwhAKQmfoPht6WoqFwIH0HPvZcNgPyPsRwu9H3uRF5rvbC1P0aLusQ
ovVMABd+8UmySIPgwpf4CFaBJCnjwn/wCt0C2/e/7B/RdFoL625AihEbJyDDZ8yrjmOq8UqwZmih
/rp9PJqjjRkHTGit0B/YNzh1QzEEUSMvIw52XQ==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6656016)
`pragma protect data_block
[encoded data, 8991444 characters]
cZkeHU9OSOeA9RUT
`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2024.1"
`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
BICNEU/vVpC+fmcUBXKpMQvz87gKh0TQL5xvKe4HyGPKEPaBo3qOOX9HRefqvLup/DU7zW/gDpau
T5/OYF7qCkG/hldkuOBcdcg2L6qlk3D1M3Tb0x5Z6ndW8NVluHbF1m3wqFe2rrYJxZ5pHjBkX5eJ
KuDdQYEoENgFAmFMsCU=

`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
lXiVO86jaC5ynLO6Z/CNRNAAVYpsRR/+BCJC+jg1cVjvCS3tTzTwVDZp/pw0KemYB1KZ3KLh6iWI
kO9MIq/x13z2pk4mduld4svMRiyf2lDTUsz3evwEUTAx3whWSfmVSZspXG3U8db9jnKHN1f48erO
15VCvm1rTuq+BKAXFZ9vo4EipeenqAj8DGgrOyI5+cw0GImvBCNFkyRYJyEKXXtR365Cm8kgQerd
wT8IKHKWx7BZQ/7BYfwsrnadbLjwl76d7gjqGFNYKk/0faP5U63xsMO2j8+WV46u8XA+v9zSPjmD
7iaDKPavaL3QWM6yp6p9tsavW0Ldko7wXYvEuw==

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
nSWxf3uCQo+nRf+5wx35OitQEqutTrObCxvcqMwmjgrTmMSH1mUiFV/7iIokhWONfT3hyDoBsb0B
TEp/eqAkqM9Rk2ejMw2RopM7wBIEBIeBR8QN5M/ruBncOpgiOCY/rPn9b1mPrAmodfkgOJX7QOzB
Z5iKeHDfi9OBhsm0Lm0=

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
kR7cRNj9SHTvRVJEhY1Xhp2WzwW/RoW1wI4aWQKt67ImOYXc7sCL2m93rAwFffdRv2YoFZcMQU4A
zFNDJiAIZ0K06FeP1Aw3lQ251C0n+xs3+ONoDdL4s/k7rgsVV+D5HrhH5IhSFqufBXsZjQw4LeCv
R9tKEHNnGoN8e26e4K1w8tce0yTTEeg0jPQohC9eINXJfZ3s610tddKAs6eECJI4vKDQmZS25k40
OXSjB/MmdDvAuJEpFPN1XDwrFsPsiRy0oBqKhMpnrBD0rrNUwKKX2oNwtpjgymBFDec1rnJJ1S8F
IVFgBy/uNQbubeeq5b7gvvhvHgCGhyHKycaWlQ==

`pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
ZiWMDNIC8751mpvmS7BQB6GEm5tfD5eOjBjBKnU3R/ZqARYOWFPqWjepExqdHpXFaMP1ZYKxlaj1
Kbs5GSaMMtR10dPrJ2YMWhwcp8s4iMJfzQpIyW0xsVKOMvDMvkLrEXheG0cIOVGLkcOfUq/5tA8i
gIZVad3d/OC3+dz7X7UeNW3UgkvEfQHBQoSSBmHPpwnzlw4mVQLkdYOchqO74w8XcTIPInfaQsea
xMlxY3V4LTs+MIzYZulqDlwYDzX+0ISlxQocfTUvRuO1Y/HZo55svipd7GC/1KveKt71x+ItjQKL
TWLa+oyarsgKaXapygUgd/TlJ6NcpJI+pbhtZQ==

`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2023_11", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
KA5/UBl4eiJ+IacjQrORMTaPIS/ndkBM1RK5KlLqiBAcTV1Bki2A6s0ezE0LWpag9TgmAMV9GtNh
d061OE8yG+ZKH/AFxXcL+q85Ch+PO1nPh9F4OrZZSXE+Kck9VMrcXhphvA+Hza+CQpfnhcRIDBQy
IM+tZaJbg5oeo2XbPJ40l/TliItz2uhhH1Dx2EGm3IH6Seu8vZXEI5X+JCzzAc7RC70Y6jr8uN3A
/SChyu+VD8HwqPs4Xf0vN0MgR8TLGkZXtNOWisQPKgzPfiz6LuL0DroEA4GGPJERtPlrDILZJ5tb
Jjj9FzvAGPCq7H6SRLuq8ilkgPt6Vx7BWGwdAw==

`pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
W92HoBqA3HToqvoakldrkGZ2hRF8n+TtCOfVJ2TaSk/woSo+5Z1mv+cAy8QZavUHTssxEjK4IXDZ
fve58I1Ohz6geZIVm2LjaiDdUKHVEGBAzM+R9VJnwi8I7O42Fx89f1og2itqxUVp458lR7YIpGwY
ec9Hlb1hWOgI8+jnITfxNOGrMIGtEn0YFY7NKxx12dDnxF79zuhLR7twxk6CUPqgYq0IrgWTOgzM
+A4NdnAZhZwqmK5AlEb7VSkKZvxEXA8ctL4FqxmJKrSmkJMJ6spgP3VOuEyjlqZrsaVMtzAAtc1p
DvQ+qmVtIZwcnLNj3t1HbcDeRA3gc6+7wmrNYw==

`pragma protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`pragma protect key_block
LjytwzQ9wydutKPAkHWjdzESXRPron7mV+pgBrL2g8RkxQXks9dEhbhTVQxZl/g3V664KH7AcKUC
1B2+hh6JAkQJvWYVohe7EzBo/3IQQNCpJqLgdnxHlz3tC7fqDclAuzprt6HMpXLTLak0DoQCcEYL
PDr7JJoUqZk2lxlcHMsap35+Nv8ux8UytFCDEyuYOTYAheCN6cSf8KTFk4Dw/zMbAqvBC4Lm3mhT
lPw/G0mzKgVxa1GxUA68y31NzLh6iTQjQ71G6QqMuytwdQkvZ4lHigrM536urdQIrM+6TsS21FG7
BOQ2ok2ye0chDXyJMCOh0nsPGhPmCY6pzwVgDwuWn+PQm4vNkJ5QkvbUkRRCJmrnMf9uWqLpK8Br
e3UK+LLpoUXZxPOjpQ8CYfECmUXdvUpu/8NhH4sQ76hBnbDvK3rye1tQ41qhymCLkDJyrhfEv9LK
BBayP19oB7RJ0NeEgbwv0hBJhVYi7KfMt7u/+oMApp9u1OErjfm9meD9

`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
jIAEOaMqklk3JTcbY/EhwUEYkc+BEfsblUT5D0I+peB271RN6H131GTskSt+mtjYNNpRADQqrHMj
zATbqqsJ9hQ+YS8Ctbsc+3NHDd8tLNdh09WjkIdDzSpt5KmIGdXnL2sIlJSY1uRdnYFEJQop7P2V
kDzSEnkT5uEPF2tJMYXBQsX52VcXEL6o6/QWhzD2qUhma3+Wvo4IJ7/UAC4n7j8hjjH2K8h1mvIv
0n3p5DHyuTf8/SmkV14oY6OzqTK1CSMykTiTU+1FkJLpJ28sepCA7eVfuWYyuiHsgUFk2WJJK1NZ
JyQH/apeswKlQRqJWgEYidTxqoAnG2SRLwxEqw==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 259472)
`pragma protect data_block
[encoded data, 350504 characters]
673c41CYjFk=
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
