// Company:         TAIR
// Engineer:        Chigrinskiy A.  
// 
// Create Date:     18/04/2024 
// Design Name: 
// Module Name:     SbTmsgWrapper
// Project Name:    SB_TMSG44V1_FPGA
// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
// Tool versions:
// Description:    This module is a wrapper for the LMX Fifo, LMX Fifo Controller and SPI Master modules.
//
// Dependencies:  
// Revision: 
// Revision 1.0 - File Created
// Additional Comments: 
//
////////////////////////////////////////////////////////////////////////////////////////////
module SbTmsgWrapper #(
    parameter IN_WIDTH = 32,
    parameter WR_NUM = 1,
    parameter OUT_WIDTH = 32,
    parameter DATA_MAX_WIDTH = 32
)(
    input WrClk_i,
    input RdClk_i,
    input Rst_i,
    input [IN_WIDTH-1:0] Data_i,
    input Val_i,
    input [6:0] WidthCurrent_i,
	input SpiMode_i,

    output Ss_o,
    output Sck_o,
    output Mosi_o,
	output Mosi1_io,
	output Mosi2_o,
	output Mosi3_o
);
//================================================================================
//	                                REG/WIRE
//================================================================================    
wire [OUT_WIDTH-1:0] dataFromLmkFifoCtrl;
wire [OUT_WIDTH-1:0] dataFromLmkFifo;
wire readEn;
wire writeEn;
wire valRdDataLmk;
wire busySpiMLmx;
wire lmkFifoFull;
wire lmkFifoEmpty;

wire busySpiMLmxR;
wire busySpiMLmxQ;

wire mosi0R;
wire mosi0Q;

wire mosi1;

wire sckR;
wire sckQ;

wire ssR;
wire ssQ;

//================================================================================
//	                                ASSIGNMENTS
//================================================================================ 
assign Mosi_o = (SpiMode_i == 0) ? mosi0R : mosi0Q;

assign Sck_o = (SpiMode_i == 0) ? sckR : sckQ;
assign Ss_o = (SpiMode_i == 0) ? ssR : ssQ;
assign busySpiMLmx = (SpiMode_i == 0) ? busySpiMLmxR : busySpiMLmxQ;
//==========================================================================//
//									CODING									//
//==========================================================================//
FifoCtrl #(
	.IN_WIDTH		(IN_WIDTH),
	.WR_NUM			(WR_NUM),
	.OUT_WIDTH		(OUT_WIDTH)
) FifoCtrlLmx
(
	.WrClk_i		(WrClk_i),
	.RdClk_i		(RdClk_i),
	.Rst_i			(Rst_i),
	.Data_i			(Data_i),
	.Val_i			(Val_i),
	.BusySpiM_i		(busySpiMLmx),
	.FifoFull_i		(lmkFifoFull),
	.FifoEmpty_i	(lmkFifoEmpty),
	.Data_o			(dataFromLmkFifoCtrl),
	.ReadEn_o		(readEn),
	.WriteEn_o		(writeEn),
	.ValRdData_o	(valRdDataLmk)
);

FifoTmsg FifoTmsg (
	.rst	(Rst_i),				// input wire rst
	.wr_clk	(WrClk_i),				// input wire wr_clk
	.rd_clk	(RdClk_i),				// input wire rd_clk
	.din	(dataFromLmkFifoCtrl),	// input wire [31 : 0] din
	.wr_en	(writeEn),				// input wire wr_en
	.rd_en	(readEn),				// input wire rd_en
	.dout	(dataFromLmkFifo),		// output wire [31 : 0] dout
	.full	(lmkFifoFull),			// output wire full
	.empty	(lmkFifoEmpty)			// output wire empty
);

SpiMVariableWidth #(
	.DATA_MAX_WIDTH	(DATA_MAX_WIDTH)
)SpiMTmsg(
	.Clk_i			(RdClk_i),
	.Rst_i			(Rst_i | SpiMode_i),
	.Val_i			(valRdDataLmk),
	.SpiData_i		(dataFromLmkFifo),
	.WidthCurrent_i	(WidthCurrent_i),
	.Busy_o			(busySpiMLmxR),
	.Ss_o			(ssR),
	.Mosi_o			(mosi0R),
	.Sck_o			(sckR)
);

QuadSpiMVariableWidth #(
	.DATA_MAX_WIDTH	(DATA_MAX_WIDTH)
)QuadSpiMTmsg(
	.Clk_i			(RdClk_i),
	.Rst_i			(Rst_i | (!SpiMode_i)),
	.Val_i			(valRdDataLmk),
	.SpiData_i		(dataFromLmkFifo),
	.WidthCurrent_i	(WidthCurrent_i),
	.Ss_o			(ssQ),
	.Mosi0_o		(mosi0Q),
	.Mosi1_o		(Mosi1_io),
	.Mosi2_o		(Mosi2_o),
	.Mosi3_o		(Mosi3_o),
	.Sck_o			(sckQ),
	.Busy_o			(busySpiMLmxQ)
);

endmodule