-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1 (win64) Build 5076996 Wed May 22 18:37:14 MDT 2024
-- Date        : Wed Oct 16 12:59:49 2024
-- Host        : DESKTOP-1TRD5RL running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode synth_stub c:/VNA_XDMA_REPO/src/ip/xdma_0/xdma_0_stub.vhdl
-- Design      : xdma_0
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xc7a100tfgg484-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity xdma_0 is
  Port ( 
    sys_clk : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    user_lnk_up : out STD_LOGIC;
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    axi_aclk : out STD_LOGIC;
    axi_aresetn : out STD_LOGIC;
    usr_irq_req : in STD_LOGIC_VECTOR ( 0 to 0 );
    usr_irq_ack : out STD_LOGIC_VECTOR ( 0 to 0 );
    msi_enable : out STD_LOGIC;
    msi_vector_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awready : in STD_LOGIC;
    m_axi_wready : in STD_LOGIC;
    m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_bvalid : in STD_LOGIC;
    m_axi_arready : in STD_LOGIC;
    m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_rlast : in STD_LOGIC;
    m_axi_rvalid : in STD_LOGIC;
    m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_awvalid : out STD_LOGIC;
    m_axi_awlock : out STD_LOGIC;
    m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_wlast : out STD_LOGIC;
    m_axi_wvalid : out STD_LOGIC;
    m_axi_bready : out STD_LOGIC;
    m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axi_arvalid : out STD_LOGIC;
    m_axi_arlock : out STD_LOGIC;
    m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axi_rready : out STD_LOGIC;
    cfg_mgmt_addr : in STD_LOGIC_VECTOR ( 18 downto 0 );
    cfg_mgmt_write : in STD_LOGIC;
    cfg_mgmt_write_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_enable : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_mgmt_read : in STD_LOGIC;
    cfg_mgmt_read_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_read_write_done : out STD_LOGIC;
    cfg_mgmt_type1_cfg_reg_access : in STD_LOGIC;
    m_axib_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_awvalid : out STD_LOGIC;
    m_axib_awready : in STD_LOGIC;
    m_axib_awlock : out STD_LOGIC;
    m_axib_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_wlast : out STD_LOGIC;
    m_axib_wvalid : out STD_LOGIC;
    m_axib_wready : in STD_LOGIC;
    m_axib_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_bvalid : in STD_LOGIC;
    cfg_aer_interrupt_msgnum_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dsn_i : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_err_aer_headerlog_i : in STD_LOGIC_VECTOR ( 127 downto 0 );
    cfg_err_tlp_cpl_header_i : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_interrupt_di_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_mgmt_di_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_dwaddr_i : in STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_pciecap_interrupt_msgnum_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_pm_force_state_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_turnoff_ok_i : in STD_LOGIC;
    fc_sel_i : in STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axis_rx_tready_i : in STD_LOGIC;
    pl_directed_link_auton_i : in STD_LOGIC;
    pl_directed_link_change_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_speed_i : in STD_LOGIC;
    pl_directed_link_width_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_upstream_prefer_deemph_i : in STD_LOGIC;
    rx_np_ok_i : in STD_LOGIC;
    rx_np_req_i : in STD_LOGIC;
    s_axis_tx_tdata_i : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tkeep_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tx_tlast_i : in STD_LOGIC;
    s_axis_tx_tuser_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axis_tx_tvalid_i : in STD_LOGIC;
    tx_cfg_gnt_i : in STD_LOGIC;
    cfg_bus_number_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number_o : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_to_turnoff_o : out STD_LOGIC;
    m_axis_rx_tdata_o : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tlast_o : out STD_LOGIC;
    m_axis_rx_tuser_o : out STD_LOGIC_VECTOR ( 21 downto 0 );
    m_axis_rx_tvalid_o : out STD_LOGIC;
    Integrated_bloc_reset_o : out STD_LOGIC;
    s_axis_tx_tready_o : out STD_LOGIC;
    m_axib_bready : out STD_LOGIC;
    m_axib_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axib_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    m_axib_arvalid : out STD_LOGIC;
    m_axib_arready : in STD_LOGIC;
    m_axib_arlock : out STD_LOGIC;
    m_axib_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
    m_axib_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axib_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axib_rlast : in STD_LOGIC;
    m_axib_rvalid : in STD_LOGIC;
    m_axib_rready : out STD_LOGIC
  );

end xdma_0;

architecture stub of xdma_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "sys_clk,sys_rst_n,user_lnk_up,pci_exp_txp[1:0],pci_exp_txn[1:0],pci_exp_rxp[1:0],pci_exp_rxn[1:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],m_axi_awready,m_axi_wready,m_axi_bid[3:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_arready,m_axi_rid[3:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_awid[3:0],m_axi_awaddr[63:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awlock,m_axi_awcache[3:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_bready,m_axi_arid[3:0],m_axi_araddr[63:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arlock,m_axi_arcache[3:0],m_axi_rready,cfg_mgmt_addr[18:0],cfg_mgmt_write,cfg_mgmt_write_data[31:0],cfg_mgmt_byte_enable[3:0],cfg_mgmt_read,cfg_mgmt_read_data[31:0],cfg_mgmt_read_write_done,cfg_mgmt_type1_cfg_reg_access,m_axib_awid[3:0],m_axib_awaddr[63:0],m_axib_awlen[7:0],m_axib_awsize[2:0],m_axib_awburst[1:0],m_axib_awprot[2:0],m_axib_awvalid,m_axib_awready,m_axib_awlock,m_axib_awcache[3:0],m_axib_wdata[63:0],m_axib_wstrb[7:0],m_axib_wlast,m_axib_wvalid,m_axib_wready,m_axib_bid[3:0],m_axib_bresp[1:0],m_axib_bvalid,cfg_aer_interrupt_msgnum_i[4:0],cfg_dsn_i[63:0],cfg_err_aer_headerlog_i[127:0],cfg_err_tlp_cpl_header_i[47:0],cfg_interrupt_di_i[7:0],cfg_mgmt_di_i[31:0],cfg_mgmt_dwaddr_i[9:0],cfg_pciecap_interrupt_msgnum_i[4:0],cfg_pm_force_state_i[1:0],cfg_turnoff_ok_i,fc_sel_i[2:0],m_axis_rx_tready_i,pl_directed_link_auton_i,pl_directed_link_change_i[1:0],pl_directed_link_speed_i,pl_directed_link_width_i[1:0],pl_upstream_prefer_deemph_i,rx_np_ok_i,rx_np_req_i,s_axis_tx_tdata_i[63:0],s_axis_tx_tkeep_i[7:0],s_axis_tx_tlast_i,s_axis_tx_tuser_i[3:0],s_axis_tx_tvalid_i,tx_cfg_gnt_i,cfg_bus_number_o[7:0],cfg_device_number_o[4:0],cfg_function_number_o[2:0],cfg_to_turnoff_o,m_axis_rx_tdata_o[63:0],m_axis_rx_tkeep_o[7:0],m_axis_rx_tlast_o,m_axis_rx_tuser_o[21:0],m_axis_rx_tvalid_o,Integrated_bloc_reset_o,s_axis_tx_tready_o,m_axib_bready,m_axib_arid[3:0],m_axib_araddr[63:0],m_axib_arlen[7:0],m_axib_arsize[2:0],m_axib_arburst[1:0],m_axib_arprot[2:0],m_axib_arvalid,m_axib_arready,m_axib_arlock,m_axib_arcache[3:0],m_axib_rid[3:0],m_axib_rdata[63:0],m_axib_rresp[1:0],m_axib_rlast,m_axib_rvalid,m_axib_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "xdma_0_core_top,Vivado 2024.1";
begin
end;
