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##-----------------------------------------------------------------------------
##
## Project    : The Xilinx PCI Express DMA 
## File       : xdma_0_pcie3_7vx_ip.xdc
## Version    : 4.1
##-----------------------------------------------------------------------------
#
# SXX
# false
# false
###############################################################################
# User Time Names / User Time Groups / Time Specs
###############################################################################

###############################################################################
# User Physical Constraints
###############################################################################


###############################################################################
# Pinout and Related I/O Constraints
###############################################################################
#
# Transceiver instance placement.  This constraint selects the
# transceivers to be used, which also dictates the pinout for the
# transmit and receive differential pairs.  Please refer to the
# Virtex-7 GT Transceiver User Guide (UG) for more information.
#
###############################################################################

###############################################################################
#
# PCI Express Block placement. This constraint selects the PCI Express
# Block to be used.
#
###############################################################################

###############################################################################
#
# Buffer (BRAM) Placement Constraints
#
###############################################################################

###############################################################################
# Timing Constraints
###############################################################################
#
#
###############################################################################
# Physical Constraints
###############################################################################
#
#create_clock -period 10 [get_ports sys_clk]
#

###############################################################################
# End
##############################################################################
#create_waiver -internal -scope -id "TIMING-1" -user "xdma" -tag "1019576" -desc " TIMING-1 wavied" 
#create_waiver -internal -scope -id "TIMING-3" -user "xdma" -tag "1019576" -desc " TIMING-3 wavied" 
#create_waiver -internal -scope -id "TIMING-6" -user "xdma" -tag "1019576" -desc " TIMING-6 wavied" 
#create_waiver -internal -scope -id "TIMING-7" -user "xdma" -tag "1019576" -desc " TIMING-7 wavied"
#create_waiver -internal -scope -id "TIMING-18" -user "xdma" -tag "1019576" -desc " TIMING-18 wavied"
#create_waiver -internal -scope -id "LUTAR-1" -user "xdma" -tag "1019576" -desc " LUTAR-1 wavied"

#---------------------- Adding REQP waivers for IP level constraints --------------------------------#


create_waiver -type DRC -id {REQP-1839} -tags "1166691" -user "xdma" -internal -scope -desc "DRC expects synchronous pins to be provided to BRAM inputs. Since synchronization is present one stage before, it is safe to ignore" -objects [list [get_cells -hierarchical -filter {NAME =~ {*pcie2_to_pcie3_wrapper_i/*dma_cpl_fifo_inst/U0/*.WIDE_PRIM36_NO_ECC.ram}}] [get_cells -hierarchical -filter {NAME =~ {*udma_wrapper/dma_top/*_nn1_reg*} && PRIMITIVE_TYPE =~ {*BRAM*}}]]

create_waiver -type DRC -id {REQP-1840} -tags "1166691" -user "xdma" -internal -scope -desc "DRC expects synchronous pins to be provided to BRAM inputs. Since synchronization is present one stage before, it is safe to ignore" -objects [list [get_cells -hierarchical -filter {NAME =~ {*pcie2_to_pcie3_wrapper_i/*dma_cpl_fifo_inst/U0/*.WIDE_PRIM18.ram}}] [get_cells -hierarchical -filter {NAME =~ {*udma_wrapper/dma_top/*_nn1_reg*} && PRIMITIVE_TYPE =~ {*BRAM*}}]]


create_waiver -type DRC -id {REQP-1839} -tags "1166691" -user "xdma" -internal -scope -desc "DRC expects synchronous pins to be provided to BRAM inputs. Since synchronization is present one stage before, it is safe to ignore" -objects [list [get_cells -hierarchical -filter {NAME =~ {*ram_top/*_PCIE_DSC_CPLD_RAM/the_bram_reg_*} && PRIMITIVE_TYPE =~ {*BRAM*}}] [get_cells -hierarchical -filter {NAME =~ {*ram_top/MASTER_READ_BRAM/*.mem_reg*} && PRIMITIVE_TYPE =~ {*BRAM*}}] [get_cells -hierarchical -filter {NAME =~ {*ram_top/mas_bridge_ram_write_512.MASTER*.mem_reg*} && PRIMITIVE_TYPE =~ {*BRAM*}}] [get_cells -hierarchical -filter {NAME =~ {*ram_top/*_DAT*_FIFO/*.mem_reg*} && PRIMITIVE_TYPE =~ {*BRAM*}}]]

create_waiver -type DRC -id {REQP-1840} -tags "1166691" -user "xdma" -internal -scope -desc "DRC expects synchronous pins to be provided to BRAM inputs. Since synchronization is present one stage before, it is safe to ignore" -objects [get_cells -hierarchical -filter {NAME =~ {*ram_top/*_DAT*_FIFO/*.mem_reg*} && PRIMITIVE_TYPE =~ {*BRAM*}}]
