{
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  "ip_inst": {
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    "component_reference": "xilinx.com:ip:pcie_7x:3.3",
    "ip_revision": "21",
    "gen_directory": ".",
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        "Interface_Width": [ { "value": "64_bit", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
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        "Bar2_64bit": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
        "Bar2_Prefetchable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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        "Bar2_Size": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
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        "Bar3_Prefetchable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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        "Bar3_Size": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
        "Bar4_Enabled": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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        "Bar4_Prefetchable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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        "Bar4_Size": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
        "Bar5_Enabled": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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        "Bar5_Scale": [ { "value": "Kilobytes", "resolve_type": "user", "usage": "all" } ],
        "Bar5_Size": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
        "Expansion_Rom_Enabled": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
        "Expansion_Rom_Scale": [ { "value": "Kilobytes", "resolve_type": "user", "usage": "all" } ],
        "Expansion_Rom_Size": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
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        "Prefetchable_Memory_Base_Limit_Registers": [ { "value": "Disabled", "resolve_type": "user", "usage": "all" } ],
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        "Device_ID": [ { "value": "7022", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
        "Revision_ID": [ { "value": "00", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
        "Subsystem_Vendor_ID": [ { "value": "10EE", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
        "Subsystem_ID": [ { "value": "0007", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
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        "Class_Code_Sub": [ { "value": "00", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
        "Class_Code_Interface": [ { "value": "01", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
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        "Sub_Class_Interface_Menu": [ { "value": "16450_compatible_serial_controller", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
        "Cardbus_CIS_Pointer": [ { "value": "00000000", "resolve_type": "user", "usage": "all" } ],
        "PCIe_Cap_Slot_Implemented": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
        "Max_Payload_Size": [ { "value": "512_bytes", "resolve_type": "user", "usage": "all" } ],
        "Extended_Tag_Field": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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        "Phantom_Functions": [ { "value": "No_function_number_bits_used", "resolve_type": "user", "usage": "all" } ],
        "Acceptable_L0s_Latency": [ { "value": "Maximum_of_64_ns", "resolve_type": "user", "usage": "all" } ],
        "Acceptable_L1_Latency": [ { "value": "No_limit", "resolve_type": "user", "usage": "all" } ],
        "Cpl_Finite": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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        "Cpl_Timeout_Range": [ { "value": "Range_B", "resolve_type": "user", "usage": "all" } ],
        "Buf_Opt_BMA": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
        "Perf_Level": [ { "value": "High", "resolve_type": "user", "usage": "all" } ],
        "Dll_Link_Active_Cap": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
        "RCB": [ { "value": "64_byte", "resolve_type": "user", "usage": "all" } ],
        "Trgt_Link_Speed": [ { "value": "4'h2", "resolve_type": "user", "usage": "all" } ],
        "Hw_Auton_Spd_Disable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
        "De_emph": [ { "value": "-3.5", "resolve_type": "user", "usage": "all" } ],
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        "Root_Cap_CRS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
        "Slot_Cap_Attn_Butn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
        "Slot_Cap_Pwr_Ctrl": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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        "Slot_Cap_Attn_Ind": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
        "Slot_Cap_Pwr_Ind": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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        "IntX_Generation": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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        "Multiple_Message_Capable": [ { "value": "1_vector", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
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        "MSIx_Enabled": [ { "value": "false", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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        "MSIx_PBA_Offset": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
        "MSIx_PBA_BIR": [ { "value": "BAR_0", "resolve_type": "user", "usage": "all" } ],
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        "D2_Power_Consumed": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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        "D3_Power_Consumed": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
        "D3_Power_Consumed_Factor": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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        "D0_Power_Dissipated_Factor": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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        "Pcie_fast_config": [ { "value": "None", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
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        "ATOMICOP32_Completer_Supported": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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            "TUSER": [ { "physical_name": "m_axis_rx_tuser" } ],
            "TVALID": [ { "physical_name": "m_axis_rx_tvalid" } ]
          }
        },
        "s_axis_tx": {
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          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
          "mode": "slave",
          "parameters": {
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            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "TUSER_WIDTH": [ { "value": "4", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "HAS_TKEEP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
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            "TKEEP": [ { "physical_name": "s_axis_tx_tkeep" } ],
            "TLAST": [ { "physical_name": "s_axis_tx_tlast" } ],
            "TREADY": [ { "physical_name": "s_axis_tx_tready" } ],
            "TUSER": [ { "physical_name": "s_axis_tx_tuser" } ],
            "TVALID": [ { "physical_name": "s_axis_tx_tvalid" } ]
          }
        },
        "pcie_7x_mgt": {
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          "abstraction_type": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0",
          "mode": "master",
          "port_maps": {
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            "rxp": [ { "physical_name": "pci_exp_rxp" } ],
            "txn": [ { "physical_name": "pci_exp_txn" } ],
            "txp": [ { "physical_name": "pci_exp_txp" } ]
          }
        },
        "CLK.sys_clk": {
          "vlnv": "xilinx.com:signal:clock:1.0",
          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
          "mode": "slave",
          "parameters": {
            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "CLK": [ { "physical_name": "sys_clk" } ]
          }
        },
        "CLK.user_clk_out": {
          "vlnv": "xilinx.com:signal:clock:1.0",
          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
          "mode": "master",
          "parameters": {
            "ASSOCIATED_BUSIF": [ { "value": "m_axis_rx:s_axis_tx", "value_src": "constant", "usage": "all" } ],
            "FREQ_HZ": [ { "value": "125000000", "value_src": "constant", "usage": "all" } ],
            "ASSOCIATED_RESET": [ { "value": "user_reset_out", "value_src": "constant", "usage": "all" } ],
            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "CLK": [ { "physical_name": "user_clk_out" } ]
          }
        },
        "RST.sys_rst_n": {
          "vlnv": "xilinx.com:signal:reset:1.0",
          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
          "mode": "slave",
          "parameters": {
            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "sys_rst_n" } ]
          }
        },
        "RST.user_reset_out": {
          "vlnv": "xilinx.com:signal:reset:1.0",
          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
          "mode": "master",
          "parameters": {
            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "user_reset_out" } ]
          }
        },
        "pcie2_cfg_err": {
          "vlnv": "xilinx.com:interface:pcie2_cfg_err:1.0",
          "abstraction_type": "xilinx.com:interface:pcie2_cfg_err_rtl:1.0",
          "mode": "slave",
          "port_maps": {
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            "aer_ecrc_check_en": [ { "physical_name": "cfg_aer_ecrc_check_en" } ],
            "aer_ecrc_gen_en": [ { "physical_name": "cfg_aer_ecrc_gen_en" } ],
            "aer_interrupt_msgnum": [ { "physical_name": "cfg_aer_interrupt_msgnum" } ],
            "atomic_egress_blocked": [ { "physical_name": "cfg_err_atomic_egress_blocked" } ],
            "cor": [ { "physical_name": "cfg_err_cor" } ],
            "cpl_abort": [ { "physical_name": "cfg_err_cpl_abort" } ],
            "cpl_rdy": [ { "physical_name": "cfg_err_cpl_rdy" } ],
            "cpl_timeout": [ { "physical_name": "cfg_err_cpl_timeout" } ],
            "cpl_unexpect": [ { "physical_name": "cfg_err_cpl_unexpect" } ],
            "ecrc": [ { "physical_name": "cfg_err_ecrc" } ],
            "err_aer_headerlog": [ { "physical_name": "cfg_err_aer_headerlog" } ],
            "err_aer_headerlog_set": [ { "physical_name": "cfg_err_aer_headerlog_set" } ],
            "internal_cor": [ { "physical_name": "cfg_err_internal_cor" } ],
            "internal_uncor": [ { "physical_name": "cfg_err_internal_uncor" } ],
            "locked": [ { "physical_name": "cfg_err_locked" } ],
            "malformed": [ { "physical_name": "cfg_err_malformed" } ],
            "mc_blocked": [ { "physical_name": "cfg_err_mc_blocked" } ],
            "norecovery": [ { "physical_name": "cfg_err_norecovery" } ],
            "poisoned": [ { "physical_name": "cfg_err_poisoned" } ],
            "posted": [ { "physical_name": "cfg_err_posted" } ],
            "tlp_cpl_header": [ { "physical_name": "cfg_err_tlp_cpl_header" } ],
            "ur": [ { "physical_name": "cfg_err_ur" } ]
          }
        },
        "pcie2_cfg_interrupt": {
          "vlnv": "xilinx.com:interface:pcie2_cfg_interrupt:1.0",
          "abstraction_type": "xilinx.com:interface:pcie2_cfg_interrupt_rtl:1.0",
          "mode": "slave",
          "port_maps": {
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            "interrupt": [ { "physical_name": "cfg_interrupt" } ],
            "mmenable": [ { "physical_name": "cfg_interrupt_mmenable" } ],
            "msienable": [ { "physical_name": "cfg_interrupt_msienable" } ],
            "msixenable": [ { "physical_name": "cfg_interrupt_msixenable" } ],
            "msixfm": [ { "physical_name": "cfg_interrupt_msixfm" } ],
            "pciecap_interrupt_msgnum": [ { "physical_name": "cfg_pciecap_interrupt_msgnum" } ],
            "rdy": [ { "physical_name": "cfg_interrupt_rdy" } ],
            "read_data": [ { "physical_name": "cfg_interrupt_do" } ],
            "stat": [ { "physical_name": "cfg_interrupt_stat" } ],
            "write_data": [ { "physical_name": "cfg_interrupt_di" } ]
          }
        },
        "pcie2_cfg_status": {
          "vlnv": "xilinx.com:interface:pcie2_cfg_status:1.0",
          "abstraction_type": "xilinx.com:interface:pcie2_cfg_status_rtl:1.0",
          "mode": "master",
          "port_maps": {
            "aer_rooterr_corr_err_received": [ { "physical_name": "cfg_aer_rooterr_corr_err_received" } ],
            "aer_rooterr_corr_err_reporting_en": [ { "physical_name": "cfg_aer_rooterr_corr_err_reporting_en" } ],
            "aer_rooterr_fatal_err_received": [ { "physical_name": "cfg_aer_rooterr_fatal_err_received" } ],
            "aer_rooterr_fatal_err_reporting_en": [ { "physical_name": "cfg_aer_rooterr_fatal_err_reporting_en" } ],
            "aer_rooterr_non_fatal_err_received": [ { "physical_name": "cfg_aer_rooterr_non_fatal_err_received" } ],
            "aer_rooterr_non_fatal_err_reporting_en": [ { "physical_name": "cfg_aer_rooterr_non_fatal_err_reporting_en" } ],
            "bridge_serr_en": [ { "physical_name": "cfg_bridge_serr_en" } ],
            "bus_number": [ { "physical_name": "cfg_bus_number" } ],
            "command": [ { "physical_name": "cfg_command" } ],
            "dcommand": [ { "physical_name": "cfg_dcommand" } ],
            "dcommand2": [ { "physical_name": "cfg_dcommand2" } ],
            "device_number": [ { "physical_name": "cfg_device_number" } ],
            "dstatus": [ { "physical_name": "cfg_dstatus" } ],
            "function_number": [ { "physical_name": "cfg_function_number" } ],
            "lcommand": [ { "physical_name": "cfg_lcommand" } ],
            "lstatus": [ { "physical_name": "cfg_lstatus" } ],
            "pcie_link_state": [ { "physical_name": "cfg_pcie_link_state" } ],
            "pmcsr_pme_en": [ { "physical_name": "cfg_pmcsr_pme_en" } ],
            "pmcsr_pme_status": [ { "physical_name": "cfg_pmcsr_pme_status" } ],
            "pmcsr_powerstate": [ { "physical_name": "cfg_pmcsr_powerstate" } ],
            "received_func_lvl_rst": [ { "physical_name": "cfg_received_func_lvl_rst" } ],
            "root_control_pme_int_en": [ { "physical_name": "cfg_root_control_pme_int_en" } ],
            "root_control_syserr_corr_err_en": [ { "physical_name": "cfg_root_control_syserr_corr_err_en" } ],
            "root_control_syserr_fatal_err_en": [ { "physical_name": "cfg_root_control_syserr_fatal_err_en" } ],
            "root_control_syserr_non_fatal_err_en": [ { "physical_name": "cfg_root_control_syserr_non_fatal_err_en" } ],
            "slot_control_electromech_il_ctl_pulse": [ { "physical_name": "cfg_slot_control_electromech_il_ctl_pulse" } ],
            "status": [ { "physical_name": "cfg_status" } ],
            "turnoff": [ { "physical_name": "cfg_to_turnoff" } ],
            "tx_buf_av": [ { "physical_name": "tx_buf_av" } ],
            "tx_cfg_req": [ { "physical_name": "tx_cfg_req" } ],
            "tx_err_drop": [ { "physical_name": "tx_err_drop" } ],
            "vc_tcvc_map": [ { "physical_name": "cfg_vc_tcvc_map" } ]
          }
        },
        "pcie_cfg_fc": {
          "vlnv": "xilinx.com:interface:pcie_cfg_fc:1.0",
          "abstraction_type": "xilinx.com:interface:pcie_cfg_fc_rtl:1.0",
          "mode": "master",
          "port_maps": {
            "CPLD": [ { "physical_name": "fc_cpld" } ],
            "CPLH": [ { "physical_name": "fc_cplh" } ],
            "NPD": [ { "physical_name": "fc_npd" } ],
            "NPH": [ { "physical_name": "fc_nph" } ],
            "PD": [ { "physical_name": "fc_pd" } ],
            "PH": [ { "physical_name": "fc_ph" } ],
            "SEL": [ { "physical_name": "fc_sel" } ]
          }
        },
        "pcie2_cfg_control": {
          "vlnv": "xilinx.com:interface:pcie2_cfg_control:1.0",
          "abstraction_type": "xilinx.com:interface:pcie2_cfg_control_rtl:1.0",
          "mode": "slave",
          "port_maps": {
            "ds_bus_number": [ { "physical_name": "cfg_ds_bus_number" } ],
            "ds_device_number": [ { "physical_name": "cfg_ds_device_number" } ],
            "ds_function_number": [ { "physical_name": "cfg_ds_function_number" } ],
            "dsn": [ { "physical_name": "cfg_dsn" } ],
            "pm_force_state": [ { "physical_name": "cfg_pm_force_state" } ],
            "pm_force_state_en": [ { "physical_name": "cfg_pm_force_state_en" } ],
            "pm_halt_aspm_l0s": [ { "physical_name": "cfg_pm_halt_aspm_l0s" } ],
            "pm_halt_aspm_l1": [ { "physical_name": "cfg_pm_halt_aspm_l1" } ],
            "pm_send_pme_to": [ { "physical_name": "cfg_pm_send_pme_to" } ],
            "pm_wake": [ { "physical_name": "cfg_pm_wake" } ],
            "rx_np_ok": [ { "physical_name": "rx_np_ok" } ],
            "rx_np_req": [ { "physical_name": "rx_np_req" } ],
            "trn_pending": [ { "physical_name": "cfg_trn_pending" } ],
            "turnoff_ok": [ { "physical_name": "cfg_turnoff_ok" } ],
            "tx_cfg_gnt": [ { "physical_name": "tx_cfg_gnt" } ]
          }
        },
        "pcie2_cfg_msg_rcvd": {
          "vlnv": "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0",
          "abstraction_type": "xilinx.com:interface:pcie2_cfg_msg_rcvd_rtl:1.0",
          "mode": "master",
          "port_maps": {
            "assert_int_a": [ { "physical_name": "cfg_msg_received_assert_int_a" } ],
            "assert_int_b": [ { "physical_name": "cfg_msg_received_assert_int_b" } ],
            "assert_int_c": [ { "physical_name": "cfg_msg_received_assert_int_c" } ],
            "assert_int_d": [ { "physical_name": "cfg_msg_received_assert_int_d" } ],
            "data": [ { "physical_name": "cfg_msg_data" } ],
            "deassert_int_a": [ { "physical_name": "cfg_msg_received_deassert_int_a" } ],
            "deassert_int_b": [ { "physical_name": "cfg_msg_received_deassert_int_b" } ],
            "deassert_int_c": [ { "physical_name": "cfg_msg_received_deassert_int_c" } ],
            "deassert_int_d": [ { "physical_name": "cfg_msg_received_deassert_int_d" } ],
            "err_cor": [ { "physical_name": "cfg_msg_received_err_cor" } ],
            "err_fatal": [ { "physical_name": "cfg_msg_received_err_fatal" } ],
            "err_non_fatal": [ { "physical_name": "cfg_msg_received_err_non_fatal" } ],
            "pm_pme": [ { "physical_name": "cfg_msg_received_pm_pme" } ],
            "pme_to_ack": [ { "physical_name": "cfg_msg_received_pme_to_ack" } ],
            "received": [ { "physical_name": "cfg_msg_received" } ],
            "received_pm_as_nak": [ { "physical_name": "cfg_msg_received_pm_as_nak" } ],
            "received_setslotpowerlimit": [ { "physical_name": "cfg_msg_received_setslotpowerlimit" } ]
          }
        },
        "pcie_cfg_mgmt": {
          "vlnv": "xilinx.com:interface:pcie_cfg_mgmt:1.0",
          "abstraction_type": "xilinx.com:interface:pcie_cfg_mgmt_rtl:1.0",
          "mode": "slave",
          "port_maps": {
            "ADDR": [ { "physical_name": "cfg_mgmt_dwaddr" } ],
            "BYTE_EN": [ { "physical_name": "cfg_mgmt_byte_en" } ],
            "READ_DATA": [ { "physical_name": "cfg_mgmt_do" } ],
            "READ_EN": [ { "physical_name": "cfg_mgmt_rd_en" } ],
            "READ_WRITE_DONE": [ { "physical_name": "cfg_mgmt_rd_wr_done" } ],
            "READONLY": [ { "physical_name": "cfg_mgmt_wr_readonly" } ],
            "TYPE1_CFG_REG_ACCESS": [ { "physical_name": "cfg_mgmt_wr_rw1c_as_rw" } ],
            "WRITE_DATA": [ { "physical_name": "cfg_mgmt_di" } ],
            "WRITE_EN": [ { "physical_name": "cfg_mgmt_wr_en" } ]
          }
        },
        "pcie2_pl": {
          "vlnv": "xilinx.com:interface:pcie2_pl:1.0",
          "abstraction_type": "xilinx.com:interface:pcie2_pl_rtl:1.0",
          "mode": "slave",
          "port_maps": {
            "directed_change_done": [ { "physical_name": "pl_directed_change_done" } ],
            "directed_link_auton": [ { "physical_name": "pl_directed_link_auton" } ],
            "directed_link_change": [ { "physical_name": "pl_directed_link_change" } ],
            "directed_link_speed": [ { "physical_name": "pl_directed_link_speed" } ],
            "directed_link_width": [ { "physical_name": "pl_directed_link_width" } ],
            "downstream_deemph_source": [ { "physical_name": "pl_downstream_deemph_source" } ],
            "initial_link_width": [ { "physical_name": "pl_initial_link_width" } ],
            "lane_reversal_mode": [ { "physical_name": "pl_lane_reversal_mode" } ],
            "link_gen2_cap": [ { "physical_name": "pl_link_gen2_cap" } ],
            "link_partner_gen2_supported": [ { "physical_name": "pl_link_partner_gen2_supported" } ],
            "link_upcfg_cap": [ { "physical_name": "pl_link_upcfg_cap" } ],
            "ltssm_state": [ { "physical_name": "pl_ltssm_state" } ],
            "phy_lnk_up": [ { "physical_name": "pl_phy_lnk_up" } ],
            "received_hot_rst": [ { "physical_name": "pl_received_hot_rst" } ],
            "rx_pm_state": [ { "physical_name": "pl_rx_pm_state" } ],
            "sel_lnk_rate": [ { "physical_name": "pl_sel_lnk_rate" } ],
            "sel_lnk_width": [ { "physical_name": "pl_sel_lnk_width" } ],
            "transmit_hot_rst": [ { "physical_name": "pl_transmit_hot_rst" } ],
            "tx_pm_state": [ { "physical_name": "pl_tx_pm_state" } ],
            "upstream_prefer_deemph": [ { "physical_name": "pl_upstream_prefer_deemph" } ]
          }
        }
      }
    }
  }
}