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## Project    : The Xilinx PCI Express DMA 
## File       : xdma_0_ooc.xdc
## Version    : 4.1
##-----------------------------------------------------------------------------
#
# This constraints file contains default clock frequencies to be used during out-of-context flows such as
# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
# to match the target frequencies. 
# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
#
create_clock  -period 10 [get_ports sys_clk]
create_clock -name axi_aclk -period 8 [get_ports axi_aclk]
	
#
#
#

