Инициализация репозитория

script/recreate.tcl

@@ -0,0 +1,945 @@
+#*****************************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# recreate.tcl: Tcl script for re-creating project 'VNA_XDMA'
+#
+# Generated by Vivado on Fri Oct 11 11:13:01 +0700 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (recreate.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    "C:/VNA_XDMA_PROJ/VNA_XDMA.srcs/utils_1/imports/synth_1/xilinx_dma_pcie_ep.dcp"
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "C:/VNA_XDMA_REPO/src/ip/xdma_0/xdma_0.xci"
+#    "C:/VNA_XDMA_REPO/src/src/DevicesWrappers/AttPeWrapper.v"
+#    "C:/VNA_XDMA_REPO/src/src/IntBlockApp/EP_MEM.v"
+#    "C:/VNA_XDMA_REPO/src/src/FifoCtrl/FifoCtrl.v"
+#    "C:/VNA_XDMA_REPO/src/src/DevicesWrappers/LmkWrapperA.v"
+#    "C:/VNA_XDMA_REPO/src/src/DevicesWrappers/LmkWrapperB.v"
+#    "C:/VNA_XDMA_REPO/src/src/IntBlockApp/PIO.v"
+#    "C:/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_EP.v"
+#    "C:/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_EP_MEM_ACCESS.v"
+#    "C:/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_RX_ENGINE.v"
+#    "C:/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_TO_CTRL.v"
+#    "C:/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_TX_ENGINE.v"
+#    "C:/VNA_XDMA_REPO/src/src/QSpiM/QuadSpiMVariableWidth.v"
+#    "C:/VNA_XDMA_REPO/src/src/DevicesWrappers/SbTmsgWrapper.v"
+#    "C:/VNA_XDMA_REPO/src/src/SpiM/SpiM.v"
+#    "C:/VNA_XDMA_REPO/src/src/SpiM/SpiMVariableWidth.v"
+#    "C:/VNA_XDMA_REPO/src/src/IntBlockApp/pcie_app_7x.v"
+#    "C:/VNA_XDMA_REPO/src/src/Xdma/xdma_app.v"
+#    "C:/VNA_XDMA_REPO/src/src/Xdma/xilinx_dma_pcie_ep.sv"
+#    "C:/VNA_XDMA_REPO/src/constrs/xilinx_xdma_pcie_x0y0.xdc"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/board_common.vh"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_cfg.v"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_com.v"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_rx.v"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/tests.vh"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/sample_tests.vh"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_tx.v"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/pcie3_uscale_rp_core_top.v"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/pcie3_uscale_rp_top.v"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/sys_clk_gen.v"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/sys_clk_gen_ds.v"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/xilinx_pcie_uscale_rp.v"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/board.v"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/xilinx_dma_pcie_ep.sv"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_pl.v"
+#    "C:/VNA_XDMA_REPO/src/src/PCIeImports/xdma_app.v"
+#
+#*****************************************************************************************
+
+# Check file required for this script exists
+proc checkRequiredFiles { origin_dir} {
+  set status true
+  set files [list \
+ "[file normalize "$origin_dir/VNA_XDMA_PROJ/VNA_XDMA.srcs/utils_1/imports/synth_1/xilinx_dma_pcie_ep.dcp"]"\
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find local file $ifile "
+      set status false
+    }
+  }
+
+  set files [list \
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/ip/xdma_0/xdma_0.xci"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/DevicesWrappers/AttPeWrapper.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/IntBlockApp/EP_MEM.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/FifoCtrl/FifoCtrl.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/DevicesWrappers/LmkWrapperA.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/DevicesWrappers/LmkWrapperB.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/IntBlockApp/PIO.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_EP.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_EP_MEM_ACCESS.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_RX_ENGINE.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_TO_CTRL.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_TX_ENGINE.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/QSpiM/QuadSpiMVariableWidth.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/DevicesWrappers/SbTmsgWrapper.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/SpiM/SpiM.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/SpiM/SpiMVariableWidth.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/IntBlockApp/pcie_app_7x.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/Xdma/xdma_app.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/Xdma/xilinx_dma_pcie_ep.sv"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/constrs/xilinx_xdma_pcie_x0y0.xdc"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/board_common.vh"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_cfg.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_com.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_rx.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/tests.vh"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/sample_tests.vh"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_tx.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/pcie3_uscale_rp_core_top.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/pcie3_uscale_rp_top.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/sys_clk_gen.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/sys_clk_gen_ds.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/xilinx_pcie_uscale_rp.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/board.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/xilinx_dma_pcie_ep.sv"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_pl.v"]"\
+ "[file normalize "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/xdma_app.v"]"\
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find remote file $ifile "
+      set status false
+    }
+  }
+
+  return $status
+}
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "C:/"
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "VNA_XDMA"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "recreate.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/VNA_XDMA_PROJ"]"
+
+# Check for paths and files needed for project creation
+set validate_required 0
+if { $validate_required } {
+  if { [checkRequiredFiles $origin_dir] } {
+    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
+  } else {
+    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
+    return
+  }
+}
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a100tfgg484-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Reconstruct message rules
+# None
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_resource_estimation" -value "0" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "revised_directory_structure" -value "1" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "sim_compile_state" -value "1" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "1" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "1" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "1" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "1" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "1" -objects $obj
+set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "1" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/ip/xdma_0/xdma_0.xci"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/DevicesWrappers/AttPeWrapper.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/IntBlockApp/EP_MEM.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/FifoCtrl/FifoCtrl.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/DevicesWrappers/LmkWrapperA.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/DevicesWrappers/LmkWrapperB.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/IntBlockApp/PIO.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_EP.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_EP_MEM_ACCESS.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_RX_ENGINE.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_TO_CTRL.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/IntBlockApp/PIO_TX_ENGINE.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/QSpiM/QuadSpiMVariableWidth.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/DevicesWrappers/SbTmsgWrapper.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/SpiM/SpiM.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/SpiM/SpiMVariableWidth.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/IntBlockApp/pcie_app_7x.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/Xdma/xdma_app.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/Xdma/xilinx_dma_pcie_ep.sv"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sources_1' fileset file properties for remote files
+set file "$origin_dir/VNA_XDMA_REPO/src/ip/xdma_0/xdma_0.xci"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "is_locked" -value "1" -objects $file_obj
+}
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+
+set file "$origin_dir/VNA_XDMA_REPO/src/src/Xdma/xilinx_dma_pcie_ep.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
+set_property -name "top" -value "xilinx_dma_pcie_ep" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/VNA_XDMA_REPO/src/constrs/xilinx_xdma_pcie_x0y0.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/VNA_XDMA_REPO/src/constrs/xilinx_xdma_pcie_x0y0.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7a100tfgg484-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+set files [list \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/board_common.vh"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_cfg.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_com.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_rx.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/tests.vh"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/sample_tests.vh"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_tx.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/pcie3_uscale_rp_core_top.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/pcie3_uscale_rp_top.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/sys_clk_gen.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/sys_clk_gen_ds.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/xilinx_pcie_uscale_rp.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/board.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/xilinx_dma_pcie_ep.sv"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_pl.v"] \
+ [file normalize "${origin_dir}/VNA_XDMA_REPO/src/src/PCIeImports/xdma_app.v"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sim_1' fileset file properties for remote files
+set file "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/board_common.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_usrapp_cfg.v"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "used_in" -value "simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "0" -objects $file_obj
+set_property -name "used_in_synthesis" -value "0" -objects $file_obj
+
+set file "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/tests.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/sample_tests.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/VNA_XDMA_REPO/src/src/PCIeImports/xilinx_dma_pcie_ep.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+
+# Set 'sim_1' fileset file properties for local files
+# None
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "top" -value "board" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/VNA_XDMA_PROJ/VNA_XDMA.srcs/utils_1/imports/synth_1/xilinx_dma_pcie_ep.dcp" ]\
+]
+set imported_files ""
+foreach f $files {
+  lappend imported_files [import_files -fileset utils_1 $f]
+}
+
+# Set 'utils_1' fileset file properties for remote files
+# None
+
+# Set 'utils_1' fileset file properties for local files
+set file "synth_1/xilinx_dma_pcie_ep.dcp"
+set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
+set_property -name "netlist_only" -value "0" -objects $file_obj
+
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+set idrFlowPropertiesConstraints ""
+catch {
+ set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints]
+ set_param runs.disableIDRFlowPropertyConstraints 1
+}
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a100tfgg484-2 -flow {Vivado Synthesis 2024} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2024" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "needs_refresh" -value "1" -objects $obj
+set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "incremental_checkpoint" -value "$proj_dir/${_xil_proj_name_}.srcs/utils_1/imports/synth_1/xilinx_dma_pcie_ep.dcp" -objects $obj
+set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a100tfgg484-2 -flow {Vivado Implementation 2024} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2024" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "needs_refresh" -value "1" -objects $obj
+set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+catch {
+ if { $idrFlowPropertiesConstraints != {} } {
+   set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints
+ }
+}
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1
+
+##################################################################
+# CHECK VIVADO VERSION
+##################################################################
+
+set scripts_vivado_version 2024.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+  catch {common::send_msg_id "IPS_TCL-100" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_ip_tcl to create an updated script."}
+  return 1
+}
+
+##################################################################
+# START
+##################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source recreateIp.tcl
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+  create_project VNA_XDMA VNA_XDMA_PROJ -part xc7a100tfgg484-2
+  set_property target_language Verilog [current_project]
+  set_property simulator_language Verilog [current_project]
+}
+
+##################################################################
+# CHECK IPs
+##################################################################
+
+set bCheckIPs 1
+set bCheckIPsPassed 1
+if { $bCheckIPs == 1 } {
+  set list_check_ips { xilinx.com:ip:fifo_generator:13.2 xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:ip:xdma:4.1 }
+  set list_ips_missing ""
+  common::send_msg_id "IPS_TCL-1001" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+  foreach ip_vlnv $list_check_ips {
+  set ip_obj [get_ipdefs -all $ip_vlnv]
+  if { $ip_obj eq "" } {
+    lappend list_ips_missing $ip_vlnv
+    }
+  }
+
+  if { $list_ips_missing ne "" } {
+    catch {common::send_msg_id "IPS_TCL-105" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+    set bCheckIPsPassed 0
+  }
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "IPS_TCL-102" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 1
+}
+
+##################################################################
+# CREATE IP FifoAttPe
+##################################################################
+
+set FifoAttPe [create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name FifoAttPe]
+
+# User Parameters
+set_property -dict [list \
+  CONFIG.Fifo_Implementation {Independent_Clocks_Distributed_RAM} \
+  CONFIG.Input_Data_Width {8} \
+  CONFIG.Input_Depth {16} \
+  CONFIG.Performance_Options {First_Word_Fall_Through} \
+] [get_ips FifoAttPe]
+
+# Runtime Parameters
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $FifoAttPe
+
+##################################################################
+
+##################################################################
+# CREATE IP FifoLMK
+##################################################################
+
+set FifoLMK [create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name FifoLMK]
+
+# User Parameters
+set_property -dict [list \
+  CONFIG.Fifo_Implementation {Independent_Clocks_Builtin_FIFO} \
+  CONFIG.Input_Data_Width {24} \
+  CONFIG.Input_Depth {512} \
+  CONFIG.Performance_Options {First_Word_Fall_Through} \
+] [get_ips FifoLMK]
+
+# Runtime Parameters
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $FifoLMK
+
+##################################################################
+
+##################################################################
+# CREATE IP FifoTmsg
+##################################################################
+
+set FifoTmsg [create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name FifoTmsg]
+
+# User Parameters
+set_property -dict [list \
+  CONFIG.Fifo_Implementation {Independent_Clocks_Builtin_FIFO} \
+  CONFIG.Input_Data_Width {32} \
+  CONFIG.Input_Depth {512} \
+  CONFIG.Performance_Options {First_Word_Fall_Through} \
+] [get_ips FifoTmsg]
+
+# Runtime Parameters
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $FifoTmsg
+
+##################################################################
+
+##################################################################
+# CREATE IP PllSpi
+##################################################################
+
+set PllSpi [create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name PllSpi]
+
+# User Parameters
+set_property -dict [list \
+  CONFIG.CLKIN1_JITTER_PS {80.0} \
+  CONFIG.CLKOUT1_JITTER {197.700} \
+  CONFIG.CLKOUT1_PHASE_ERROR {96.948} \
+  CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {10} \
+  CONFIG.CLKOUT2_JITTER {143.688} \
+  CONFIG.CLKOUT2_PHASE_ERROR {96.948} \
+  CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50} \
+  CONFIG.CLKOUT2_USED {true} \
+  CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} \
+  CONFIG.MMCM_CLKIN1_PERIOD {8.000} \
+  CONFIG.MMCM_CLKOUT0_DIVIDE_F {100.000} \
+  CONFIG.MMCM_CLKOUT1_DIVIDE {20} \
+  CONFIG.NUM_OUT_CLKS {2} \
+  CONFIG.PRIM_IN_FREQ {125} \
+  CONFIG.USE_LOCKED {false} \
+  CONFIG.USE_RESET {false} \
+] [get_ips PllSpi]
+
+# Runtime Parameters
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $PllSpi
+
+##################################################################
+
+##################################################################
+# CREATE IP blk_mem_gen_1
+##################################################################
+
+set blk_mem_gen_1 [create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name blk_mem_gen_1]
+
+# User Parameters
+set_property -dict [list \
+  CONFIG.Interface_Type {AXI4} \
+  CONFIG.Write_Width_A {64} \
+] [get_ips blk_mem_gen_1]
+
+# Runtime Parameters
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $blk_mem_gen_1
+
+##################################################################
+
+##################################################################
+# CREATE IP xdma_0
+##################################################################
+
+# set_property simulator_language MIXED [current_project]
+# set xdma_0 [create_ip -name xdma -vendor xilinx.com -library ip -version 4.1 -module_name xdma_0]
+
+# # User Parameters
+# set_property -dict [list \
+  # CONFIG.PF0_DEVICE_ID_mqdma {9022} \
+  # CONFIG.PF0_SRIOV_VF_DEVICE_ID {0000} \
+  # CONFIG.PF1_SRIOV_VF_DEVICE_ID {A132} \
+  # CONFIG.PF2_DEVICE_ID_mqdma {9022} \
+  # CONFIG.PF2_SRIOV_VF_DEVICE_ID {A232} \
+  # CONFIG.PF3_DEVICE_ID_mqdma {9022} \
+  # CONFIG.PF3_SRIOV_VF_DEVICE_ID {A332} \
+  # CONFIG.axist_bypass_en {true} \
+  # CONFIG.axisten_freq {125} \
+  # CONFIG.copy_pf0 {true} \
+  # CONFIG.pf0_device_id {7022} \
+  # CONFIG.pf1_msix_cap_pba_offset {00000000} \
+  # CONFIG.pf1_msix_cap_table_offset {00000000} \
+  # CONFIG.pf1_msix_cap_table_size {000} \
+  # CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \
+  # CONFIG.pl_link_cap_max_link_width {X2} \
+  # CONFIG.plltype {QPLL1} \
+  # CONFIG.runbit_fix {false} \
+# ] [get_ips xdma_0]
+
+# # Runtime Parameters
+# set_property -dict { 
+  # GENERATE_SYNTH_CHECKPOINT {1}
+# } $xdma_0
+
+##################################################################
+
+

src/ip/xdma_0/doc/xdma_v4_1_changelog.txt

@@ -0,0 +1,271 @@
+2020.2:
+ * Version 4.1 (Rev. 8)
+ * General: Added XCZU43DR and XCVU57P device support.
+ * Revision change in one or more subcores
+
+2020.1.1:
+ * Version 4.1 (Rev. 7)
+ * General: Added XQVU9P and XQVU13P device support.
+ * Revision change in one or more subcores
+
+2020.1:
+ * Version 4.1 (Rev. 6)
+ * General: Added a GUI option, in "Debug" tab, to enable store_ltssm logic
+ * General: Shared logic not supported in the example design when Tandem is enabled.
+ * Revision change in one or more subcores
+
+2019.2.2:
+ * Version 4.1 (Rev. 5)
+ * General: Added device support for xcvu15p and xczu5xdr devices.
+ * Revision change in one or more subcores
+
+2019.2.1:
+ * Version 4.1 (Rev. 4)
+ * No changes
+
+2019.2:
+ * Version 4.1 (Rev. 4)
+ * General: Added Tandem support for xcvu45p and xcvu47p devices.
+ * Revision change in one or more subcores
+
+2019.1.3:
+ * Version 4.1 (Rev. 3)
+ * No changes
+
+2019.1.2:
+ * Version 4.1 (Rev. 3)
+ * No changes
+
+2019.1.1:
+ * Version 4.1 (Rev. 3)
+ * No changes
+
+2019.1:
+ * Version 4.1 (Rev. 3)
+ * Bug Fix: Fixed core generation issue for -1M device with Gen2 and 125 MHz AXI clock frequencey.
+ * Bug Fix: Fixed back to back reads failure for 7series Gen2 DMA.
+ * Feature Enhancement: Added GUI option to disable the GT channel LOC constraints in GTWizard IP XDC
+ * Revision change in one or more subcores
+
+2018.3.1:
+ * Version 4.1 (Rev. 2)
+ * No changes
+
+2018.3:
+ * Version 4.1 (Rev. 2)
+ * Bug Fix: Disabled vendor ID change for non PF0 case
+ * Bug Fix: Fixed MSI-X packet corruption in case Gen2 devices.
+ * Bug Fix: Added an option in the GUI to enable lane reversal parameter for Gen2 devices
+ * Bug Fix: Fixed Slot Capabilities register offset for Root Port example design in Bridge mode
+ * Bug Fix: Fixed Bridge address translation issue for 32bit AXI BAR to 64bit PCIe BAR(when AXI Address width is lessthan 64)
+ * Bug Fix: Fixed IPI block automation for vu440 device
+ * Feature Enhancement: Added Resizable BAR for SDAccel
+ * Feature Enhancement: Added EROM functionality
+ * Feature Enhancement: Added Parity option for AXI Bridge mode. Added s_axib_wuser and s_axib_ruser signal when it's enabled
+ * Feature Enhancement: Added an option in the GUI to select PCIe IDs through ports
+ * Feature Enhancement: Added an option in the GUI to select FIFO mode or decode mode for MSI interrupt in Root Port Bridge mode
+ * Feature Enhancement: Added an option in the GUI to select MPSOC Root Port solution in basic page for Bridge Root Port mode
+ * Feature Enhancement: Added an option in the GUI to enable optional debug ports cfg_current_speed and cfg_negotiated_width
+ * Revision change in one or more subcores
+
+2018.2:
+ * Version 4.1 (Rev. 1)
+ * Bug Fix: Allowed AXI-MM Bypass BAR size till 256GB for 64bit BAR (Xilinx Answer Record - 71012)
+ * Bug Fix: Removed dependency of 'GT Channel DRP' parameter on 'Enable In System IBERT' parameter. Now, both the options can be selected at the same time
+ * Bug Fix: Slave AXI Lite memory range is updated to 64KB for DMA functional mode and 512MB for AXI Bridge functional mode
+ * Bug Fix: Fixed Posted TLP ordering issue on Slave AXI Lite and Slave AXI interfaces
+ * Bug Fix: Fixed Master MemWr and received interrupt ordering issue for AxiBridge RC configuration
+ * Bug Fix: Fix for CQ NP credits after Partial Reconfiguration
+ * Bug Fix: Fixed 7series Gen2 DMA hang issue due to TLP drop and incorrect TLP for straddled packets
+ * Feature Enhancement: Enabled x16g3 configuration support for -1 speedgrade of  UltraScale Plus family devices
+ * Other: Performance improved for axi bridge slave interface (Xilinx Answer Record - 71052)
+ * Other: Added support for the defense grade devices xqvu7p,xqvu11p,xqzu5ev,xqzu7ev,xqzu19eg,xqzu21dr and xqzu28dr
+ * Other: Added support for xcvu29p device
+ * Revision change in one or more subcores
+
+2018.1:
+ * Version 4.1
+ * Bug Fix: Fixed the issue with the H2C transfer where completions are not returned when odd number of bytes are being transferred (Xilinx Answer Record - 70324)
+ * Bug Fix: Fixed the issue with the C2H transfer where s_axis_cc_tready signal is not asserted when odd number of bytes are being transferred (Xilinx Answer Record - 70324)
+ * Bug Fix: Fixed issue with H2C transfer when 128bit axi datawidth and 64 bit address is enabled (Xilinx Answer Record - 70324)
+ * Bug Fix: Force overwrite PCIEBAR2AXIBAR translation vector to 0x0 is now allowed when PCIe BAR is disabled to turn off Address Translation feature in Root Port AXI Bridge mode if chosen
+ * Bug Fix: Fixed the issue where axi_ctl_aresetn is de-asserted before axi_clk is stable for UltraScale Plus devices
+ * Bug Fix: Changed the interface mode of dsc_bypass_c2h_* and dsc_bypass_h2c_* interfaces to slave
+ * Feature Enhancement: Added GEN4 control skip filter module with parameter(ctrl_skip_mask).This can be used for EndPoint to work with GEN4 RootPort generating control skips
+ * Feature Enhancement: Added ASPM L1 support for GEN3 and ASPM L0s for Gen1 & Gen2 with GUI option(in PCIe:MISC page) for Bridge Endpoint mode
+ * Feature Enhancement: Added a new optional dma_bridge_resetn pin that allows DMA/Bridge engine/registers to be reset without bringing PCIe link down. This can be enabled through soft_reset_en parameter
+ * Feature Enhancement: Added a new Interrupt Decode mode for RootPort Bridge can be enabled via TCL parameter CONFIG.msi_rx_pin_en(true). Enabling this option will allow the IP to internally decode Legacy and MSI interrupt and remove the use of Interrupt FIFO. Bridge Info Register [5] is updated to reflect this change
+ * Feature Enhancement: Added msix_enable output port when msix is enabled
+ * Feature Enhancement: Added pcie_id input ports for UltraScalePlus devices with parameter(pcie_id_if)
+ * Feature Enhancement: Rename Parity as Data Protection in GUI
+ * Feature Enhancement: Added Tandem XDMA support for the xczu7ev, xczu7eg, xczu7cg, xcku11p, and xcvu11p devices.
+ * Feature Enhancement: Added support for fsve1156,fsvg1517 packages for xczu25dr,xczu27dr,xczu28dr devices and fsvf1760 for xczu29dr device
+ * Other: Bridge mode Root Port only: By default, axi_ctl_aresetn now deasserts after PHY is ready (GT Initialization done)
+ * Other: Bridge mode Endpoint only: By default, axi_ctl_aresetn now deasserts after PCIe link is in D0_active power state (PCIe link up, configured, and enabled)
+ * Revision change in one or more subcores
+
+2017.4:
+ * Version 4.0 (Rev. 1)
+ * Bug Fix: Allow MSI-X Table and PBA registers to be programed while MSI-X Enable bit in MSIX Control register is 0. (Affects Bridge functional mode only)
+ * Bug Fix: Corrected MSI-X Table Size to 'h1F (32 vectors)
+ * Bug Fix: Corrected CC to TX conversion which was causing register read failures when there is high C2H traffic. (this issue affects both DMA and Bridge functional mode - 7 Series only)
+ * Bug Fix: Fixed the receive data for PCIe Hard Block when 64 bit addressing is enabled. (this issue affects both DMA and Bridge functional mode - 7 Series only)
+ * Bug Fix: Fixed ext_sys_clk_bufg option in US+
+ * Feature Enhancement: Added Auto Rx Equalization support in the GT Settings GUI page.
+ * Revision change in one or more subcores
+
+2017.3:
+ * Version 4.0
+ * Bug Fix: Fixed issue with the generation of example design in IPI canvas
+ * Bug Fix: Updated arrow colors for JTAG debugger LTSSM graph
+ * Bug Fix: Added missing ports for 'Include GT Wizard in Example Design' mode
+ * Bug Fix: Corrected GT DRP address width for Ultrascale Plus device family
+ * Bug Fix: Fixed connection between cfg_err_cor_in or cfg_err_uncor_in signals and XDMA Bridge internal register. Remove unused cfg_err_uncor_in port in multi PF designs
+ * Bug Fix: Removed invalid dependency on M_AXIB_Wvalid and M_AXIB_AWready signal
+ * Bug Fix: Fixed Address Translation mechanism in RP AXI Bridge mode when no BAR is enabled
+ * Bug Fix: Fixed Address Translation for 64-bit AXI/PCIe BAR
+ * Feature Enhancement: Added option to enable external BUFG_GT/SYNC for sys_clk
+ * Feature Enhancement: Moved phy_clk module in support wrapper when Include GT Wizard in Example Design mode is selected
+ * Feature Enhancement: Added GT COMMON sharing support
+ * Feature Enhancement: Added Tandem support for VU7P, KU15P, ZU19 devices
+ * Feature Enhancement: Added support for xcvu33p, xazu4ev and xazu5ev devices
+ * Feature Enhancement: Enabled x8g3 configuration support for -1 and -2LV speedgrades for all the devices and packages
+ * Other: Removed s_axib_wuser and s_axib_ruser signal in AXI Bridge mode
+ * Revision change in one or more subcores
+
+2017.2:
+ * Version 3.1 (Rev. 1)
+ * Bug Fix: PCI Express Extended Configuration Space Enable parameter enables config extended interface
+ * Bug Fix: Limit PCIe BAR and address translation value for AXI Lite Master interface to 32-bit only
+ * Bug Fix: Limit PCIe BAR and address translation value for DMA Bridge mode up to the chosen AXI Address Width only
+ * Bug Fix: Disable Slave AXI Bridge Timeout Counter and use PCIe Hard Block Timeout Counter for Vrtex7-XT, UltraScale and UltraScale Plus devices
+ * Bug Fix: Handle Message TLP for 7-series Gen2 DMA
+ * Feature Enhancement: Added support for xczu27dr device
+ * Revision change in one or more subcores
+
+2017.1:
+ * Version 3.1
+ * Bug Fix: Fixed axi_aresetn output signal driving based on user_reset
+ * Bug Fix: Added simulation support for 128byte DMA
+ * Bug Fix: Enabled support for g1x16, g2x16 configurations for -1L, -1LV and -2LV speedgrades for UltraScale Plus device family
+ * Bug Fix: Removed option to select 250Mhz of UserClk_freq (AXI Interface Frequency) for the devices xc7z015,xc7z15i and xc7z12s since the timing does not meet
+ * Bug Fix: Removed m_axib_ruser and m_axib_wuser from M_AXI_B interface when AXI Bridge mode is selected, since these signals are not used in this mode. No change in M_AXI_BYPASS interface when DMA mode is selected
+ * Feature Enhancement: Added support for xczu7ev device
+ * Feature Enhancement: Added support for xczu21dr, xczu25dr, xczu28dr and xczu29dr devices
+ * Feature Enhancement: Added JTAG debugger support in the Add. Debug Options GUI page to debug LTSSM, Reset sequence and Rx detect sequence.
+ * Feature Enhancement: Added In-System IBERT support in the Add. Debug Options page to scan eye diagram of the serial lane
+ * Feature Enhancement: Added support for zynquplus devices - xczu4cg,xczu4eg, xczu5cg, xczu5eg, xczu7cg and xczu7eg
+ * Feature Enhancement: Enabled g3x16 support for all the UltraScale Plus devices and packages for -2L speedgrades
+ * Feature Enhancement: Removed g3x16 and g3x8 option for -1 speedgrade for all the UltraScale Plus devices and packages
+ * Feature Enhancement: For all the UltraScale Plus devices and pacakges, Removed the option to select the coreclock frequency. It is always set to 500MHz now.
+ * Feature Enhancement: Added support for external GT DRP interface
+ * Feature Enhancement: Added option to enable PM_L23_Entry
+ * Feature Enhancement: Added GT Wizard support for Xilinx example design in the Shared Logic page.
+ * Feature Enhancement: Added Tandem support for vu3p, vu9p, and vu13p.
+ * Feature Enhancement: Change the default value of User Interrupt Enable Mask in IRQ Block register to always allow interrupt after reset when Bridge functional mode is selected.
+ * Revision change in one or more subcores
+
+2016.4:
+ * Version 3.0 (Rev. 1)
+ * Bug Fix: Fixed simulation issue with Vivado simulator
+ * Feature Enhancement: Added AXI Bridge functionality for UltraScale Plus family devices
+ * Feature Enhancement: Enabled x16g3 support for -2L speedgrades for xcvu9p - flga2104,flgb2104,flgc2104 and fsgd2104
+ * Revision change in one or more subcores
+
+2016.3:
+ * Version 3.0
+ * Port Change: Added debug ports. When option 'Enable Debug Ports' is selected on 'PCIe DMA' tab all m_axis_rq/cc_* and s_axis_rc/cq_* signals will appear at boundary
+ * Bug Fix: Fixed issues with the example design generation for xcvu9p-flgc2104 and flga2577 packages
+ * Feature Enhancement: Added support for PCIe Gen2 devcies
+ * Feature Enhancement: Added shared logic support for 7 series and UltraScale variants. Currently Shared logic is not supported when Tandem feature is selected.
+ * Feature Enhancement: Added Check parity to check parity on pcie reads and add parity for pcie writes. Added Parity propagate to send and receive parity bits to/from user
+ * Revision change in one or more subcores
+
+2016.2:
+ * Version 2.0 (Rev. 1)
+ * Fixed issue with the generation of acknowledgement for interrupt assertion and de-assertion when multiple interrupts are generated.
+ * Removed the GUI selections for AXI Data Widths that are not supported for -1 speedgrade parts.
+ * Updated the Tandem with Field Updates example design scripts to handle IP core containers where the output products were not generated.
+ * Added support for defense grade Kintex UltraScale device xqku115
+ * Modified the insertion loss profile parameter to provide three options Chip-to-Chip(5db), Add-in_Card(15db) and Backplane(20db). Core operates in LPM mode for the values < 15db and DFE mode for the values >= 15db.
+ * Revision change in one or more subcores
+
+2016.1:
+ * Version 2.0
+ * Modified the width of pipe_tx_*_sigs, common_commands_in and common_commands_out
+ * Modified the mapping of logical and physical external pipe interface ports for End Point configurations so that it can be connected to Root Port device directly
+ * Changes to HDL library management to support Vivado IP simulation library
+ * Added Tandem and MCAP support for Ultrascale configuration of the core.
+ * Removed m_axis_h2c_tkeep_0/1/2/3 signals
+ * Added option to disable pcie_cfg_mgmt interface depending on the parameter Configuration Management Interface
+ * Added support for defense grade kintexu devices - xqku040-rfa1156,xqku040-rba676,xqku060-rfa1156 and xqku095-rfa1156
+ * Added bus interfaces for dsc_bypass_c2h_* and dsc_bypass_h2c_* signals for all the 4 channels
+ * Added interface dma_status_ports for c2h_sts_* and h2c_sts_* signals
+ * Fixed issue with the default values of 'Base_Class_Menu' and 'Sub Class_Interface_Menu' 
+ * Added the required Tandem and MCAP ports: cap_*, startup_*, mcap_* interfaces
+ * Added HAS_BURST parameter on M_AXI interfaces for SmartConnect optimization
+ * Added two new ports to transceiver debug interface section: gt_dmonfiforeset gt_dmonitorclk.
+ * Revision change in one or more subcores
+
+2015.4.2:
+ * Version 1.0 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 1.0 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 1.0 (Rev. 1)
+ * Added support for ffva1156 package for xcku095 device
+ * Revision change in one or more subcores
+
+2015.3:
+ * Version 1.0
+ * Initial release
+
+(c) Copyright 2015 - 2020 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.

src/ip/xdma_0/hdl/verilog/axi_infrastructure_header.vh

@@ -0,0 +1,138 @@
+//  (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+//
+//  This file contains confidential and proprietary information
+//  of Xilinx, Inc. and is protected under U.S. and
+//  international copyright and other intellectual property
+//  laws.
+//
+//  DISCLAIMER
+//  This disclaimer is not a license and does not grant any
+//  rights to the materials distributed herewith. Except as
+//  otherwise provided in a valid license issued to you by
+//  Xilinx, and to the maximum extent permitted by applicable
+//  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+//  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+//  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+//  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+//  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+//  (2) Xilinx shall not be liable (whether in contract or tort,
+//  including negligence, or under any other theory of
+//  liability) for any loss or damage of any kind or nature
+//  related to, arising under or in connection with these
+//  materials, including for any direct, or any indirect,
+//  special, incidental, or consequential loss or damage
+//  (including loss of data, profits, goodwill, or any type of
+//  loss or damage suffered as a result of any action brought
+//  by a third party) even if such damage or loss was
+//  reasonably foreseeable or Xilinx had been advised of the
+//  possibility of the same.
+//
+//  CRITICAL APPLICATIONS
+//  Xilinx products are not designed or intended to be fail-
+//  safe, or for use in any application requiring fail-safe
+//  performance, such as life-support or safety devices or
+//  systems, Class III medical devices, nuclear facilities,
+//  applications related to the deployment of airbags, or any
+//  other applications that could lead to death, personal
+//  injury, or severe property or environmental damage
+//  (individually and collectively, "Critical
+//  Applications"). Customer assumes the sole risk and
+//  liability of any use of Xilinx products in Critical
+//  Applications, subject only to applicable laws and
+//  regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//  PART OF THIS FILE AT ALL TIMES. 
+//-----------------------------------------------------------------------------
+//
+// Generic Functions used by AXI Infrastructure Modules
+//
+// Verilog-standard:  Verilog 2001
+//--------------------------------------------------------------------------
+// Global Parameters:
+//
+// Functions:
+//
+// Tasks:
+//--------------------------------------------------------------------------
+///////////////////////////////////////////////////////////////////////////////
+// BEGIN Global Parameters
+///////////////////////////////////////////////////////////////////////////////
+localparam G_AXI_AWADDR_INDEX   = 0;
+localparam G_AXI_AWADDR_WIDTH   = C_AXI_ADDR_WIDTH;
+localparam G_AXI_AWPROT_INDEX   = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH;
+localparam G_AXI_AWPROT_WIDTH   = 3;
+localparam G_AXI_AWSIZE_INDEX   = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH;
+localparam G_AXI_AWSIZE_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : 3;
+localparam G_AXI_AWBURST_INDEX  = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH;
+localparam G_AXI_AWBURST_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 2;
+localparam G_AXI_AWCACHE_INDEX  = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH;
+localparam G_AXI_AWCACHE_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_AWLEN_INDEX    = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH;
+localparam G_AXI_AWLEN_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
+localparam G_AXI_AWLOCK_INDEX   = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH;
+localparam G_AXI_AWLOCK_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
+localparam G_AXI_AWID_INDEX     = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH;
+localparam G_AXI_AWID_WIDTH     = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_AWQOS_INDEX    = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH;
+localparam G_AXI_AWQOS_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH;
+localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
+localparam G_AXI_AWUSER_INDEX   = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH;
+localparam G_AXI_AWUSER_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH;
+localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH;
+localparam G_AXI_ARADDR_INDEX   = 0;
+localparam G_AXI_ARADDR_WIDTH   = C_AXI_ADDR_WIDTH;
+localparam G_AXI_ARPROT_INDEX   = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH;
+localparam G_AXI_ARPROT_WIDTH   = 3;
+localparam G_AXI_ARSIZE_INDEX   = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH;
+localparam G_AXI_ARSIZE_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : 3;
+localparam G_AXI_ARBURST_INDEX  = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH;
+localparam G_AXI_ARBURST_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 2;
+localparam G_AXI_ARCACHE_INDEX  = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH;
+localparam G_AXI_ARCACHE_WIDTH  = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_ARLEN_INDEX    = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH;
+localparam G_AXI_ARLEN_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
+localparam G_AXI_ARLOCK_INDEX   = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH;
+localparam G_AXI_ARLOCK_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
+localparam G_AXI_ARID_INDEX     = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH;
+localparam G_AXI_ARID_WIDTH     = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_ARQOS_INDEX    = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH;
+localparam G_AXI_ARQOS_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 4;
+localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH;
+localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
+localparam G_AXI_ARUSER_INDEX   = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH;
+localparam G_AXI_ARUSER_WIDTH   = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH;
+localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH;
+// Write channel widths
+localparam G_AXI_WDATA_INDEX    = 0;
+localparam G_AXI_WDATA_WIDTH    = C_AXI_DATA_WIDTH;
+localparam G_AXI_WSTRB_INDEX    = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH;
+localparam G_AXI_WSTRB_WIDTH    = C_AXI_DATA_WIDTH / 8;
+localparam G_AXI_WLAST_INDEX    = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH;
+localparam G_AXI_WLAST_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 1;
+localparam G_AXI_WID_INDEX      = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH;
+localparam G_AXI_WID_WIDTH      = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_WUSER_INDEX    = G_AXI_WID_INDEX + G_AXI_WID_WIDTH;
+localparam G_AXI_WUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH;
+localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH;
+// Write Response channel Widths
+localparam G_AXI_BRESP_INDEX    = 0;
+localparam G_AXI_BRESP_WIDTH    = 2;
+localparam G_AXI_BID_INDEX      = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH;
+localparam G_AXI_BID_WIDTH      = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_BUSER_INDEX    = G_AXI_BID_INDEX + G_AXI_BID_WIDTH;
+localparam G_AXI_BUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH;
+localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH;
+// Read channel widths
+localparam G_AXI_RDATA_INDEX    = 0;
+localparam G_AXI_RDATA_WIDTH    = C_AXI_DATA_WIDTH;
+localparam G_AXI_RRESP_INDEX    = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH;
+localparam G_AXI_RRESP_WIDTH    = 2;
+localparam G_AXI_RLAST_INDEX    = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH;
+localparam G_AXI_RLAST_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : 1;
+localparam G_AXI_RID_INDEX      = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH;
+localparam G_AXI_RID_WIDTH      = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
+localparam G_AXI_RUSER_INDEX    = G_AXI_RID_INDEX + G_AXI_RID_WIDTH;
+localparam G_AXI_RUSER_WIDTH    = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH;
+localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH;

src/ip/xdma_0/hdl/verilog/dma_defines.svh

@@ -0,0 +1,387 @@
+`ifndef DMA_DEFINES_SVH
+`define DMA_DEFINES_SVH
+
+`include "dma_defines.vh"
+`include "pcie_dma_attr_defines.svh"
+
+// Interface Includes at bottom of file (use some structures defined in this file)
+
+`define IF_MI_CONVERSION_M \
+    always_comb begin \
+        ifc.wadr = wadr;\
+        ifc.wen  = wen;\
+        ifc.wpar = wpar;\
+        ifc.wdat = wdat;\
+        ifc.ren  = ren;\
+        ifc.radr = radr;\
+       rpar = ifc.rpar;\
+       rdat = ifc.rdat;\
+       rsbe = ifc.rsbe;\
+       rdbe = ifc.rdbe;\
+    end
+
+`define IF_MI_CONVERSION_S \
+    always_comb begin \
+        wadr = ifc.wadr;\
+        wen  = ifc.wen;\
+        wpar = ifc.wpar;\
+        wdat = ifc.wdat;\
+        ren  = ifc.ren;\
+        radr = ifc.radr;\
+        ifc.rpar = rpar;\
+        ifc.rdat = rdat;\
+        ifc.rsbe = rsbe;\
+        ifc.rdbe = rdbe;\
+    end
+
+typedef struct packed {
+   logic                  spl;
+    logic [`ADR_WIDTH-1:0] adr;
+    logic [`RID_WIDTH-1:0] rid;
+    logic [`LEN_WIDTH-1:0] byte_len;   // byte length
+    logic [`DID_WIDTH-1:0] did;
+        logic [7:0]            fnc;        // function
+} rrq_t;
+
+// Descriptor Sideband Info (Context RAM to DSC_CPLI_RAM)
+typedef struct packed {
+    logic                       wbi;     // Do writeback/interrupt on descriptor completion
+    logic                       wbi_chk; // Check status before writeback/interrupt
+    logic   [`QID_WIDTH-1:0]    qid;     // Q ID 
+    logic   [3:0]               qst;
+    logic   [7:0]               fnc;
+    logic   [15:0]              cidx;
+} dsc_sbi_t;  // 10 + 4 + 8 + 16 = 54
+
+typedef struct packed {
+    logic            sop;
+    logic            eop;
+    logic            wbk;
+    logic [4:0]      err;
+    logic [3:0]      errc;
+    //logic [`DAT_WIDTH/32-1:0] wen; // dword write enable
+    logic [`RID_WIDTH-1:0]    rid;
+    logic [`DID_WIDTH-1:0]    did;
+    logic [5:0]               lba;    // Last beat length adjustment (AXI ST C2H)
+    logic [`DAT_WIDTH/8-1:0]  par;
+    logic [`DAT_WIDTH-1:0]    dat;
+} rcp_t;
+
+typedef struct packed {
+   logic                   err;
+    logic [`ADR_WIDTH-1:0] adr;
+    logic [`RID_WIDTH-1:0] rid;
+    logic [`LEN_WIDTH-1:0] byte_len;   // byte length
+    logic [5:0]            aln;        // Source alignment
+    logic                  eop;
+    logic                  eod;
+    logic                  eor;
+} wrq_t;
+
+typedef struct packed {
+    logic    [`DAT_WIDTH/8-1:0]   par;
+    logic    [`DAT_WIDTH-1:0]     dat;
+} wpl_t;
+
+typedef struct packed {
+    logic    [`RID_WIDTH-1:0]  rid;
+    logic    [4:0]             err;
+} wcp_t;
+
+typedef struct packed {
+    logic [31:0]    dat;
+} wbrq_t;
+
+typedef struct packed {
+    logic [3:0]      be;    
+    logic            rd;
+    logic            wr;
+    logic [31:0]     dat;
+    logic [31:0]     adr;
+    logic [7:0]      func;
+} trq_t;
+
+typedef struct packed {
+    logic            vld;
+    logic [31:0]         dat;
+} tcp_t;
+
+typedef struct packed {
+    logic                     run;
+    logic                     c2h_wbk_ena;
+    logic                     noninc;
+    logic [`ADR_WIDTH-1:0]    cdc_wbk_adr;
+} creg_t;
+
+typedef struct packed {
+    logic    [63:0]        par;         // 136:73 Parity filled later
+    logic    [5:0]         seq1;        // 72:67  Sequence Num 1
+    logic    [5:0]         seq0;        // 66:61  Sequence Num 0
+    logic    [23:0]        tph;         // 60:45  TPH St Tag
+                                        // 44:43  TPH Ind Tag
+                                        // 42:39  TPH Type
+                                        // 38:37  TPH Present
+    logic                  disc;        // 36     Discontinue
+    logic    [3:0]         eop1_ptr;    // 35:32  EOP 1 Ptr
+    logic    [3:0]         eop0_ptr;    // 31:28  EOP 0 Ptr
+    logic                  eop1;        // 27     EOP 1
+    logic                  eop0;        // 26     EOP 0
+    logic    [1:0]         sop1_ptr;    // 25:24  SOP 1 Ptr
+    logic    [1:0]         sop0_ptr;    // 23:22  SOP 0 Ptr
+    logic                  sop1;        // 21     SOP 1
+    logic                  sop0;        // 20     SOP 0
+    logic    [3:0]         adr;         // 19:16  Address offset - Address aligned mode only
+    logic    [3:0]         lbe1;
+    logic    [3:0]         lbe0;
+    logic    [3:0]         fbe1;
+    logic    [3:0]         fbe0;
+} rq_usr_straddle_t;
+
+typedef struct packed {
+    logic    [76:0]        rsv;
+    logic    [31:0]        par;         // 59:28
+    logic    [3:0]        seq;        // 27:24
+    logic    [11:0]        tph;        // 23:12
+    logic            dis;        // 11
+    logic    [2:0]        adr;         // 10:8
+    logic    [3:0]         lbe;        // 7:4
+    logic    [3:0]         fbe;        // 3:0
+} rq_usr_nostraddle_t;
+
+typedef union packed {
+    rq_usr_straddle_t       rqu_str;
+    rq_usr_nostraddle_t      rqu_nstr;
+} rq_usr_t;
+
+typedef struct packed {
+    logic   [12:0]  pcie_mrrs;
+    logic   [12:0]  pcie_mps;
+    logic   [12:0]  axi_mrrs;
+    logic   [12:0]  axi_mps;
+} cfg_dma_t;
+
+typedef struct packed { 
+    logic            ecrc;
+    logic     [2:0]        attr;        
+    logic    [2:0]        tc;    
+    logic            rid_en;
+    logic    [15:0]        cpl_id;
+    logic    [7:0]        tag;
+    logic    [15:0]        req_id;
+    logic            poison;
+    logic    [3:0]        req;
+    logic    [10:0]        len;        
+    logic    [63:0]        adr;
+} rq_hdr_fields_t;
+
+typedef struct packed { 
+    logic    [23:0]        dw3_misc;
+    logic    [7:0]        tag;
+    logic    [16:0]        dw2_misc;
+    logic    [3:0]        req;
+    logic    [10:0]        len;        
+    logic    [63:0]        adr;
+} rq_hdr_compact_t;
+
+typedef struct packed { 
+    logic    [31:0]        dw3;
+    logic    [31:0]        dw2;
+    logic    [31:0]        dw1;
+    logic    [31:0]        dw0;
+} rq_hdr_dwords_t;
+
+typedef union packed {
+    rq_hdr_fields_t        rqh_f;
+    rq_hdr_compact_t      rqh_c;
+    rq_hdr_dwords_t      rqh_d;
+} rq_hdr_t;
+
+typedef struct packed { 
+    logic                    tlast;
+    logic    [`MULTQ_C2H_TUSER_WIDTH-1:0]    tuser;
+    logic    [`DAT_WIDTH/8-1:0]        tkeep;
+    logic    [`DAT_WIDTH/8-1:0]        tparity;
+    logic    [`DAT_WIDTH-1:0]        tdata;
+} dma_s_axis_t;
+
+typedef struct packed {
+    logic [`DID_WIDTH-1:0]            waddr;
+    logic [`DID_WIDTH-1:0]            raddr;
+    logic [`DAT_WIDTH/8-1:0]        wen;
+} dat_bram_cmd_t;
+
+typedef struct packed {
+    logic [`DAT_WIDTH-1:0]            dat;
+    logic [`DAT_WIDTH/8-1:0]        parity; // Even parity
+}dat_bram_dat_t;
+
+
+typedef struct packed {
+    
+    logic                    tlast;
+    logic    [`MULTQ_H2C_TUSER_WIDTH-1:0]    tuser;
+    logic    [`DAT_WIDTH/8-1:0]        tkeep;
+    logic    [`DAT_WIDTH/8-1:0]        tparity;
+    logic    [`DAT_WIDTH-1:0]        tdata;
+} dma_m_axis_t;
+
+
+// Descriptor Completion Memory Interface
+typedef struct packed {
+    logic    [`DAT_WIDTH-1:0]        rdat;
+    logic                    rbe;
+}dsc_cpl_bram_out_t;
+
+typedef struct packed {
+    logic                wen;
+    logic    [`DSC_DID_WIDTH-1:0]    waddr;
+    logic    [`DAT_WIDTH-1:0]        wdat;
+    logic    [`DSC_RID_WIDTH-1:0]    raddr;
+}dsc_cpl_bram_in_t;
+
+// XDMA Descriptor Memory Interface
+//typedef struct packed {    
+    //logic    [255:0]     rdat;
+    //logic                rbe;
+//}dsc_bram_out_t;      
+
+typedef struct packed {
+    logic                wen;
+    logic    [`DSC_DID_WIDTH-1:0]    waddr;
+    logic    [255:0]            wdat;
+    logic    [`DSC_RID_WIDTH-1:0]    raddr;
+}dsc_bram_in_t;
+
+
+//
+typedef struct packed {
+    logic    [7:0]            func;
+    //logic    [3:0]            be;
+} dma_axil_user_t;
+
+// Descriptor Completion
+typedef struct packed {
+    logic   [63:0]    wadr;
+    logic   [63:0]    radr;
+    logic   [27:0]    len;
+    logic             eop;
+    logic             cpl;
+    logic             stp;
+} dcp_t;
+
+// Descriptor In (user descriptors -> dma)
+typedef struct packed {
+    logic    [`QID_WIDTH-1:0] qid;    // Q ID 
+    logic    [1:0]            chn;    // Channel
+    logic    [3:0]            qst;    // Q status
+    logic    [2:0]            fmt;    // Format
+    logic    [255:0]          dsc;
+    logic    [3:0]            vld;
+} dma_dsc_in_t;
+
+// Descriptor In Credits (dma credits -> user)
+typedef struct packed {
+    logic                        vld;
+    logic    [8:0]               num;
+    logic    [`QID_WIDTH-1:0]    qid;
+} dma_dsc_in_crd_t;
+
+// Descriptor Out (dma descriptors -> user)
+typedef struct packed {
+    logic                       wbi;
+    logic                       wbi_chk;
+    logic    [15:0]             cidx;
+    logic    [`QID_WIDTH-1:0]   qid;    // Q ID
+    logic    [1:0]              chn;    // Channel
+    logic    [3:0]              qst;    // Q status
+    logic    [2:0]              siz;    // Format
+    logic                       dir;    // Direction
+    logic    [3:0]              vld;
+    logic    [255:0]            dsc;
+} dma_dsc_block_t;
+
+typedef struct packed {
+    logic                       wbi;
+    logic                       wbi_chk;
+    logic    [15:0]             cidx;
+    logic    [`QID_WIDTH-1:0]   qid;    // Q ID
+    logic    [1:0]              chn;    // Channel
+    logic    [3:0]              qst;    // Q status
+    logic    [2:0]              siz;    // Format
+    logic                       dir;    // Direction
+    logic    [255:0]            dsc;
+} dma_dsc_t;
+
+// Descriptor Out Credits (user credits -> dma)
+typedef struct packed {
+    logic                        vld;
+    logic    [8:0]               num;
+    logic    [`QID_WIDTH-1:0]    qid;
+    logic    [1:0]               chn;
+    logic                        clr;
+} dma_dsc_out_crd_t;
+
+
+// Interface Conversion
+
+`define PCIE_CC_TO_DMA_CC_IF(pcie_cc, dma_cc) \
+assign pcie_cc.axis_cc_tvalid =       dma_cc.tvalid; \
+assign pcie_cc.axis_cc_tdata  = 'h0 | dma_cc.tdata; \
+assign pcie_cc.axis_cc_tuser  = 'h0 | dma_cc.tuser; \
+assign pcie_cc.axis_cc_tkeep  = 'h0 | dma_cc.tkeep; \
+assign pcie_cc.axis_cc_tlast  =       dma_cc.tlast; \
+assign dma_cc.tready          = 'h0 | pcie_cc.axis_cc_tready; 
+
+`define PCIE_CQ_TO_DMA_CQ_IF(pcie_cq, dma_cq) \
+assign dma_cq.tvalid           =     | pcie_cq.axis_cq_tvalid; \
+assign dma_cq.tdata            = 'h0 | pcie_cq.axis_cq_tdata; \
+assign dma_cq.tuser            = 'h0 | pcie_cq.axis_cq_tuser; \
+assign dma_cq.tkeep            = 'h0 | pcie_cq.axis_cq_tkeep; \
+assign dma_cq.tlast            =     | pcie_cq.axis_cq_tlast; \
+assign pcie_cq.axis_cq_tready  = 'h0 | dma_cq.tready; 
+
+`define PCIE_RC_TO_DMA_RC_IF(pcie_rc, dma_rc) \
+assign dma_rc.tvalid           =     | pcie_rc.axis_rc_tvalid; \
+assign dma_rc.tdata            = 'h0 | pcie_rc.axis_rc_tdata; \
+assign dma_rc.tuser            = 'h0 | pcie_rc.axis_rc_tuser; \
+assign dma_rc.tkeep            = 'h0 | pcie_rc.axis_rc_tkeep; \
+assign dma_rc.tlast            =     | pcie_rc.axis_rc_tlast; \
+assign pcie_rc.axis_rc_tready  = 'h0 | dma_rc.tready; 
+
+`define PCIE_RQ_TO_DMA_RQ_IF(pcie_rq, dma_rq) \
+assign pcie_rq.axis_rq_tvalid =       dma_rq.tvalid; \
+assign pcie_rq.axis_rq_tdata  = 'h0 | dma_rq.tdata; \
+assign pcie_rq.axis_rq_tuser  = 'h0 | dma_rq.tuser; \
+assign pcie_rq.axis_rq_tkeep  = 'h0 | dma_rq.tkeep; \
+assign pcie_rq.axis_rq_tlast  =       dma_rq.tlast; \
+assign dma_rq.tready          = 'h0 | pcie_rq.axis_rq_tready; 
+
+`include "dma_pcie_axis_cc_if.svh"
+`include "dma_pcie_axis_cq_if.svh"
+`include "dma_pcie_axis_rc_if.svh"
+`include "dma_pcie_axis_rq_if.svh"
+//`include "dma_pcie_c2h_axis_if.svh"
+`include "dma_pcie_c2h_crdt_if.svh"
+`include "dma_pcie_dsc_in_if.svh"
+`include "dma_pcie_dsc_out_if.svh"
+`include "dma_pcie_fabric_input_if.svh"
+`include "dma_pcie_fabric_output_if.svh"
+`include "dma_pcie_gic_if.svh"
+//`include "dma_pcie_h2c_axis_if.svh"
+`include "dma_pcie_h2c_crdt_if.svh"
+`include "dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh"
+`include "dma_pcie_mi_2Bx2048_ram_if.svh"
+`include "dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh"
+`include "dma_pcie_mi_64Bx128_32Bwe_ram_if.svh"
+`include "dma_pcie_mi_64Bx256_32Bwe_ram_if.svh"
+`include "dma_pcie_mi_64Bx512_32Bwe_ram_if.svh"
+`include "dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh"
+`include "dma_pcie_mi_64Bx2048_32Bwe_ram_if.svh"
+`include "dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh"
+`include "dma_pcie_mi_dsc_cpld_if.svh"
+`include "dma_pcie_mi_dsc_cpli_if.svh"
+`include "dma_pcie_misc_input_if.svh"
+`include "dma_pcie_misc_output_if.svh"
+`endif
+
+

src/ip/xdma_0/hdl/verilog/dma_defines.vh

@@ -0,0 +1,33 @@
+`ifndef DMA_DEFINES_VH
+`define DMA_DEFINES_VH
+
+`include "dma_soft_defines.vh"
+
+`define CPLI_WIDTH 80
+
+`define DAT_WIDTH 512
+`define ADR_WIDTH 64
+`define ALN_WIDTH 4	// Bits used for subbeat dword alignment 
+`define LEN_WIDTH 28
+`define RID_WIDTH 10 
+`define DID_WIDTH 10 
+`define QID_WIDTH 8	// Support for 128 H2C and 128 C2H queues
+`define DSC_RID_WIDTH 16
+`define DSC_DID_WIDTH 16
+
+`define H2C_TAR_ID 0
+`define C2H_TAR_ID 1
+`define IRQ_TAR_ID 2
+`define CFG_TAR_ID 3
+`define DSC_H2C_TAR_ID 4
+`define DSC_C2H_TAR_ID 5
+`define DSC_TAR_ID 6
+//`define MSIX_TAR_ID 8
+//`define PF1_MSIX_TAR_ID 9
+
+`define MSIX_PBA_OFFSET 12'hfe0
+
+`define MULTQ_C2H_TUSER_WIDTH   64
+`define MULTQ_H2C_TUSER_WIDTH   64 
+
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_axis_cc_if.svh

@@ -0,0 +1,35 @@
+`ifndef iF_AXIS_CC_PCIE_DMA_PORT_VS
+`define iF_AXIS_CC_PCIE_DMA_PORT_VS
+interface dma_pcie_axis_cc_if#(DATA_WIDTH = 512, USER_WIDTH = 81)();
+
+  wire [DATA_WIDTH-1:0]     tdata;
+  wire [USER_WIDTH-1:0]     tuser;
+  wire                      tlast;
+  wire [DATA_WIDTH/32-1:0]  tkeep;
+  wire                 tvalid;
+  wire                 tready;
+
+  modport s (
+    
+    input              tdata
+   ,input              tuser
+   ,input              tlast
+   ,input              tkeep
+   ,input              tvalid
+   ,output             tready
+
+  );
+
+  modport m (
+
+    output             tdata
+   ,output             tuser
+   ,output             tlast
+   ,output             tkeep
+   ,output             tvalid
+   ,input              tready
+
+  );
+  
+endinterface : dma_pcie_axis_cc_if
+`endif // iF_AXIS_CC_PCIE_PORT_VS

src/ip/xdma_0/hdl/verilog/dma_pcie_axis_cq_if.svh

@@ -0,0 +1,35 @@
+`ifndef IF_AXIS_CQ_PCIE_DMA_PORT_SV
+`define IF_AXIS_CQ_PCIE_DMA_PORT_SV
+interface dma_pcie_axis_cq_if#(DATA_WIDTH = 512, USER_WIDTH = 183)();
+
+  wire [DATA_WIDTH-1:0]         tdata;
+  wire [USER_WIDTH-1:0]         tuser;
+  wire                          tlast;
+  wire [DATA_WIDTH/32-1:0]      tkeep;
+  wire                 tvalid;
+  wire [21:0]          tready;
+  
+  modport m (
+
+    output             tdata 
+   ,output             tuser 
+   ,output             tlast 
+   ,output             tkeep 
+   ,output             tvalid 
+   ,input              tready 
+  
+  );
+
+  modport s (
+
+    input              tdata 
+   ,input              tuser 
+   ,input              tlast 
+   ,input              tkeep 
+   ,input              tvalid 
+   ,output             tready 
+  
+  );
+
+endinterface : dma_pcie_axis_cq_if
+`endif // IF_AXIS_CQ_PCIE_DMA_PORT_SV

src/ip/xdma_0/hdl/verilog/dma_pcie_axis_rc_if.svh

@@ -0,0 +1,35 @@
+`ifndef IF_AXIS_RC_PCIE_DMA_PORT_VS
+`define IF_AXIS_RC_PCIE_DMA_PORT_VS
+interface dma_pcie_axis_rc_if#(DATA_WIDTH = 512, USER_WIDTH = 161)();
+
+  wire [DATA_WIDTH-1:0]         tdata;
+  wire                          tlast;
+  wire [USER_WIDTH-1:0]         tuser;
+  wire [DATA_WIDTH/32-1:0]      tkeep;
+  wire                          tvalid;
+  wire  [21:0]                  tready;
+
+  modport m (
+ 
+     output            tdata
+    ,output            tlast
+    ,output            tuser
+    ,output            tkeep
+    ,output            tvalid
+    ,input             tready
+
+  ); 
+
+  modport s (
+ 
+     input             tdata
+    ,input             tlast
+    ,input             tuser
+    ,input             tkeep
+    ,input             tvalid
+    ,output            tready
+
+  ); 
+
+endinterface : dma_pcie_axis_rc_if
+`endif // PCIE4_IF_AXIS_RC_PCIE_PORT

src/ip/xdma_0/hdl/verilog/dma_pcie_axis_rq_if.svh

@@ -0,0 +1,35 @@
+`ifndef IF_AXIS_RQ_PCIE_DMA_PORT_SV
+`define IF_AXIS_RQ_PCIE_DMA_PORT_SV
+interface dma_pcie_axis_rq_if#(DATA_WIDTH = 512, USER_WIDTH = 137)();
+
+  wire [DATA_WIDTH-1:0]    tdata;
+  wire                     tlast;
+  wire [USER_WIDTH-1:0]    tuser;
+  wire [DATA_WIDTH/32-1:0]   tkeep;
+  wire                 tvalid;
+  wire                 tready;
+
+  modport s (
+
+    input              tdata
+   ,input              tlast
+   ,input              tuser
+   ,input              tkeep
+   ,input              tvalid
+   ,output             tready
+
+  );
+
+  modport m (
+
+    output             tdata
+   ,output             tlast
+   ,output             tuser
+   ,output             tkeep
+   ,output             tvalid
+   ,input              tready
+
+  );
+
+endinterface : dma_pcie_axis_rq_if
+`endif // IF_AXIS_RQ_PCIE_DMA_PORT_SV

src/ip/xdma_0/hdl/verilog/dma_pcie_c2h_crdt_if.svh

@@ -0,0 +1,42 @@
+`ifndef IF_PCIE_DMA_C2H_CRDT_SV
+`define IF_PCIE_DMA_C2H_CRDT_SV
+interface dma_pcie_c2h_crdt_if #();
+    logic   [511:0]             tdata;
+    logic   [512/8-1:0]         tparity;
+    logic                       tlast;
+    logic   [512/8-1:0]         tkeep;
+    logic   [127:0]             tusr;
+    logic                       tvalid;
+    logic   [1:0]               tch;
+
+    logic                       crdt;
+    logic   [1:0]               crdt_ch;
+
+    modport m (
+        output                      tdata,
+        output                      tparity,
+        output                      tlast,
+        output                      tkeep,
+        output                      tusr,
+        output                      tvalid,
+        output                      tch,
+
+        input                       crdt,
+        input                       crdt_ch
+    );
+
+    modport s (
+        input                       tdata,
+        input                       tparity,
+        input                       tlast,
+        input                       tkeep,
+        input                       tusr,
+        input                       tvalid,
+        input                       tch,
+
+        output                      crdt,
+        output                      crdt_ch
+    );
+
+endinterface : dma_pcie_c2h_crdt_if
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_dsc_in_if.svh

@@ -0,0 +1,20 @@
+`ifndef IF_PCIE_DMA_DSC_IN_SV
+`define IF_PCIE_DMA_DSC_IN_SV
+`include "dma_defines.svh"
+
+interface dma_pcie_dsc_in_if();
+    dma_dsc_in_crd_t      crd;
+    dma_dsc_block_t       dsc;
+
+modport snk (
+input  dsc,
+output  crd
+);
+
+modport src (
+input dsc,
+output crd
+);
+
+endinterface : dma_pcie_dsc_in_if
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_dsc_out_if.svh

@@ -0,0 +1,28 @@
+`ifndef DMA_PCIE_DSC_OUT_IF_SV
+`define DMA_PCIE_DSC_OUT_IF_SV
+`include "dma_defines.svh"
+
+interface dma_pcie_dsc_out_if();
+    dma_dsc_out_crd_t      crd;
+    dma_dsc_block_t        dsc;
+
+modport snk (
+    output       crd,
+    input        dsc
+);
+
+modport src (
+    input       crd,
+    output      dsc
+);
+
+modport outputs (
+    output       dsc
+);
+
+modport inputs (
+    input        crd
+);
+
+endinterface : dma_pcie_dsc_out_if
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_fabric_input_if.svh

@@ -0,0 +1,29 @@
+`ifndef IF_PCIE_DMA_FABRIC_INPUT_SV
+`define IF_PCIE_DMA_FABRIC_INPUT_SV
+interface dma_pcie_fabric_input_if();
+logic               usr_irq_clr;
+logic               usr_irq_set;
+logic   [4:0]       usr_irq_vec;
+logic   [7:0]       usr_irq_fnc;
+logic               flr_done_vld;
+logic   [7:0]       flr_done_fnc;
+
+modport s (
+input       usr_irq_clr,
+input       usr_irq_set,
+input       usr_irq_vec,
+input       usr_irq_fnc,
+input       flr_done_vld,
+input       flr_done_fnc
+);
+
+modport m (
+output       usr_irq_clr,
+output       usr_irq_set,
+output       usr_irq_vec,
+output       usr_irq_fnc,
+output       flr_done_vld,
+output       flr_done_fnc
+);
+endinterface : dma_pcie_fabric_input_if
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_fabric_output_if.svh

@@ -0,0 +1,64 @@
+`ifndef IF_PCIE_DMA_FABRIC_OUTPUT_SV
+`define IF_PCIE_DMA_FABRIC_OUTPUT_SV
+interface dma_pcie_fabric_output_if();
+logic            c2h_dsc_avail_inc_vld;
+logic  [1:0]     c2h_dsc_avail_inc_chn;
+logic  [7:0]     c2h_dsc_avail_inc_qid;
+logic  [1:0]     c2h_dsc_avail_inc_state;
+logic  [15:0]    c2h_dsc_avail_inc_num;
+logic            s_axis_c2h_tstat_vld;
+logic  [1:0]     s_axis_c2h_tstat_chn;
+logic  [4:0]     s_axis_c2h_tstat_qid;
+logic  [7:0]     s_axis_c2h_tstat;
+logic  [3:0][7:0]    c2h_sts;
+logic  [3:0][7:0]    h2c_sts;
+logic            flr_set;
+logic            flr_clr;
+logic  [7:0]     flr_fnc;
+logic  [4:0]     usr_irq_rvec;
+logic  [7:0]     usr_irq_rfnc;
+logic            usr_irq_fail;
+logic            usr_irq_sent;
+
+modport m (
+output  c2h_dsc_avail_inc_vld,
+output  c2h_dsc_avail_inc_chn,
+output  c2h_dsc_avail_inc_qid,
+output  c2h_dsc_avail_inc_state,
+output  c2h_dsc_avail_inc_num,
+output  s_axis_c2h_tstat_vld,
+output  s_axis_c2h_tstat_chn,
+output  s_axis_c2h_tstat_qid,
+output  s_axis_c2h_tstat,
+output  c2h_sts,
+output  h2c_sts,
+output  flr_set,
+output  flr_clr,
+output  flr_fnc,
+output  usr_irq_rvec,
+output  usr_irq_rfnc,
+output  usr_irq_fail,
+output  usr_irq_sent
+);
+modport s (
+input  c2h_dsc_avail_inc_vld,
+input  c2h_dsc_avail_inc_chn,
+input  c2h_dsc_avail_inc_qid,
+input  c2h_dsc_avail_inc_state,
+input  c2h_dsc_avail_inc_num,
+input  s_axis_c2h_tstat_vld,
+input  s_axis_c2h_tstat_chn,
+input  s_axis_c2h_tstat_qid,
+input  s_axis_c2h_tstat,
+input  c2h_sts,
+input  h2c_sts,
+input  flr_set,
+input  flr_clr,
+input  flr_fnc,
+input  usr_irq_rvec,
+input  usr_irq_rfnc,
+input  usr_irq_fail,
+input  usr_irq_sent
+);
+endinterface : dma_pcie_fabric_output_if
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_gic_if.svh

@@ -0,0 +1,13 @@
+`ifndef IF_PCIE_DMA_GIC_SV
+`define IF_PCIE_DMA_GIC_SV
+interface dma_pcie_gic_if();
+    logic [6:0] interrupt;
+modport m (
+    output interrupt
+);
+modport s (
+    input interrupt
+);
+
+endinterface : dma_pcie_gic_if
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_h2c_crdt_if.svh

@@ -0,0 +1,42 @@
+`ifndef IF_PCIE_DMA_H2C_CRDT_SV
+`define IF_PCIE_DMA_H2C_CRDT_SV
+interface dma_pcie_h2c_crdt_if #();
+    logic   [511:0]             tdata;
+    logic   [512/8-1:0]         tparity;
+    logic                       tlast;
+    logic   [512/8-1:0]         tkeep;
+    logic   [63:0]              tusr;
+    logic                       tvalid;
+    logic   [1:0]               tch;
+
+    logic                       crdt;
+    logic   [1:0]               crdt_ch;
+
+    modport m (
+        output                      tdata,
+        output                      tparity,
+        output                      tlast,
+        output                      tkeep,
+        output                      tusr,
+        output                      tvalid,
+        output                      tch,
+
+        input                       crdt,
+        input                       crdt_ch
+    );
+
+    modport s (
+        input                       tdata,
+        input                       tparity,
+        input                       tlast,
+        input                       tkeep,
+        input                       tusr,
+        input                       tvalid,
+        input                       tch,
+
+        output                      crdt,
+        output                      crdt_ch
+    );
+
+endinterface : dma_pcie_h2c_crdt_if
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh

@@ -0,0 +1,43 @@
+`ifndef DMA_PCIE_MI_16BX2048_4BWE_RAM_IF_SV
+`define DMA_PCIE_MI_16BX2048_4BWE_RAM_IF_SV
+
+
+interface dma_pcie_mi_16Bx2048_4Bwe_ram_if();
+        logic   [11:0]  wadr; // 1024 H2C Qs, 1024 C2H Qs
+        logic    [3:0]  wen;
+        logic   [7:0]   wpar;
+        logic   [127:0]  wdat;  // 15:8 func, 3:0 = sts, 63:32 = produce index, 127:64 = base address
+        logic           ren;
+        logic   [11:0]   radr;
+        logic   [7:0]   rpar;
+        logic   [127:0]  rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+endinterface
+
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_mi_2Bx2048_ram_if.svh

@@ -0,0 +1,40 @@
+`ifndef DMA_PCIE_MI_2BX2048_RAM_IF_SV
+`define DMA_PCIE_MI_2BX2048_RAM_IF_SV
+interface dma_pcie_mi_2Bx2048_ram_if();
+        logic   [11:0]  wadr;
+        logic           wen;
+        logic   [1:0]   wpar;
+        logic   [15:0]  wdat;
+        logic           ren;
+        logic   [11:0]  radr;
+        logic   [1:0]   rpar;
+        logic   [15:0]  rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+endinterface
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh

@@ -0,0 +1,41 @@
+`ifndef DMA_PCIE_MI_4BX2048_4BWE_RAM_IF_SV
+`define DMA_PCIE_MI_4BX2048_4BWE_RAM_IF_SV
+
+interface dma_pcie_mi_4Bx2048_4Bwe_ram_if();
+        logic   [11:0]  wadr;
+        logic           wen;
+        logic   [7:0]   wpar;
+        logic   [31:0]  wdat;   // 31:16 = used credits.  15:0= consumer index
+        logic           ren;
+        logic   [11:0]  radr;
+        logic   [7:0]   rpar;
+        logic   [31:0]  rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+endinterface
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh

@@ -0,0 +1,44 @@
+`ifndef DMA_PCIE_MI_64BX1024_32BWE_RAM_IF_SV
+`define DMA_PCIE_MI_64BX1024_32BWE_RAM_IF_SV
+interface dma_pcie_mi_64Bx1024_32Bwe_ram_if();
+                logic   [9:0]       wadr;
+                logic   [1:0]       wen;
+                logic   [63:0]      wpar;
+                logic   [511:0]     wdat;
+                logic               ren;
+                logic   [9:0]       radr;
+
+                logic   [63:0]      rpar;
+                logic   [511:0]     rdat;
+                logic               rsbe;
+                logic               rdbe;
+
+modport m (
+                output        wadr,
+                output        wen,
+                output        wpar,
+                output        wdat,
+                output        ren,
+                output        radr,
+
+                input         rpar,
+                input         rdat,
+                input         rsbe,
+                input         rdbe
+);
+
+modport s (
+                input         wadr,
+                input         wen,
+                input         wpar,
+                input         wdat,
+                input         ren,
+                input         radr,
+
+                output        rpar,
+                output        rdat,
+                output        rsbe,
+                output        rdbe
+);
+endinterface
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_mi_64Bx128_32Bwe_ram_if.svh

@@ -0,0 +1,44 @@
+`ifndef DMA_PCIE_MI_64BX128_32BWE_RAM_IF_SV
+`define DMA_PCIE_MI_64BX128_32BWE_RAM_IF_SV
+interface dma_pcie_mi_64Bx128_32Bwe_ram_if();
+                logic   [6:0]       wadr;
+                logic   [1:0]       wen;
+                logic   [63:0]      wpar;
+                logic   [511:0]     wdat;
+                logic               ren;
+                logic   [6:0]       radr;
+
+                logic   [63:0]      rpar;
+                logic   [511:0]     rdat;
+                logic               rsbe;
+                logic               rdbe;
+
+modport m (
+                output        wadr,
+                output        wen,
+                output        wpar,
+                output        wdat,
+                output        ren,
+                output        radr,
+
+                input         rpar,
+                input         rdat,
+                input         rsbe,
+                input         rdbe
+);
+
+modport s (
+                input         wadr,
+                input         wen,
+                input         wpar,
+                input         wdat,
+                input         ren,
+                input         radr,
+
+                output        rpar,
+                output        rdat,
+                output        rsbe,
+                output        rdbe
+);
+endinterface
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_mi_64Bx2048_32Bwe_ram_if.svh

@@ -0,0 +1,44 @@
+`ifndef DMA_PCIE_MI_64BX2048_32BWE_RAM_IF_SV
+`define DMA_PCIE_MI_64BX2048_32BWE_RAM_IF_SV
+interface dma_pcie_mi_64Bx2048_32Bwe_ram_if();
+                logic   [10:0]      wadr;
+                logic   [1:0]       wen;
+                logic   [63:0]      wpar;
+                logic   [511:0]     wdat;
+                logic               ren;
+                logic   [10:0]      radr;
+
+                logic   [63:0]      rpar;
+                logic   [511:0]     rdat;
+                logic               rsbe;
+                logic               rdbe;
+
+modport m (
+                output        wadr,
+                output        wen,
+                output        wpar,
+                output        wdat,
+                output        ren,
+                output        radr,
+
+                input         rpar,
+                input         rdat,
+                input         rsbe,
+                input         rdbe
+);
+
+modport s (
+                input         wadr,
+                input         wen,
+                input         wpar,
+                input         wdat,
+                input         ren,
+                input         radr,
+
+                output        rpar,
+                output        rdat,
+                output        rsbe,
+                output        rdbe
+);
+endinterface
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh

@@ -0,0 +1,44 @@
+`ifndef DMA_PCIE_MI_64BX256_32BWE_RAM_IF_SV
+`define DMA_PCIE_MI_64BX256_32BWE_RAM_IF_SV
+interface dma_pcie_mi_64Bx256_32Bwe_ram_if();
+                logic   [8:0]       wadr;  // FIXME hack should be 8 bits
+                logic   [1:0]       wen;
+                logic   [63:0]      wpar;
+                logic   [511:0]     wdat;
+                logic               ren;
+                logic   [8:0]       radr;  // FIXME hack should be 8 bits
+
+                logic   [63:0]      rpar;
+                logic   [511:0]     rdat;
+                logic               rsbe;
+                logic               rdbe;
+
+modport m (
+                output        wadr,
+                output        wen,
+                output        wpar,
+                output        wdat,
+                output        ren,
+                output        radr,
+
+                input         rpar,
+                input         rdat,
+                input         rsbe,
+                input         rdbe
+);
+
+modport s (
+                input         wadr,
+                input         wen,
+                input         wpar,
+                input         wdat,
+                input         ren,
+                input         radr,
+
+                output        rpar,
+                output        rdat,
+                output        rsbe,
+                output        rdbe
+);
+endinterface
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_mi_64Bx512_32Bwe_ram_if.svh

@@ -0,0 +1,44 @@
+`ifndef DMA_PCIE_MI_64BX512_32BWE_RAM_IF_SV
+`define DMA_PCIE_MI_64BX512_32BWE_RAM_IF_SV
+interface dma_pcie_mi_64Bx512_32Bwe_ram_if();
+                logic   [8:0]       wadr;
+                logic   [1:0]       wen;
+                logic   [63:0]      wpar;
+                logic   [511:0]     wdat;
+                logic               ren;
+                logic   [8:0]       radr;
+
+                logic   [63:0]      rpar;
+                logic   [511:0]     rdat;
+                logic               rsbe;
+                logic               rdbe;
+
+modport m (
+                output        wadr,
+                output        wen,
+                output        wpar,
+                output        wdat,
+                output        ren,
+                output        radr,
+
+                input         rpar,
+                input         rdat,
+                input         rsbe,
+                input         rdbe
+);
+
+modport s (
+                input         wadr,
+                input         wen,
+                input         wpar,
+                input         wdat,
+                input         ren,
+                input         radr,
+
+                output        rpar,
+                output        rdat,
+                output        rsbe,
+                output        rdbe
+);
+endinterface
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh

@@ -0,0 +1,41 @@
+`ifndef DMA_PCIE_MI_8BX2048_4BWE_RAM_IF_SV
+`define DMA_PCIE_MI_8BX2048_4BWE_RAM_IF_SV
+
+interface dma_pcie_mi_8Bx2048_4Bwe_ram_if();
+        logic   [11:0]  wadr; // 1024 H2C Qs, 1024 C2H Qs
+        logic    [1:0]  wen;
+        logic   [7:0]   wpar;
+        logic   [63:0]  wdat;  // 63:0 writeback base address
+        logic           ren;
+        logic   [11:0]   radr;
+        logic   [7:0]   rpar;
+        logic   [127:0]  rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+endinterface
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_mi_dsc_cpld_if.svh

@@ -0,0 +1,71 @@
+`ifndef DMA_PCIE_MI_DSC_CPLD_IF_SV
+`define DMA_PCIE_MI_DSC_CPLD_IF_SV
+interface dma_pcie_mi_dsc_cpld_if();
+        logic   [9:0]   wadr; // 10 bits for MULTQ C2H
+        logic   [7:0]   wen;
+        logic   [63:0]  wpar;
+        logic   [511:0] wdat;
+        logic           ren;
+        logic   [9:0]   radr; // 10 bits for MULTQ C2H
+        logic   [63:0]  rpar;
+        logic   [511:0] rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+        modport s_outputs (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr
+        );
+
+        modport m_outputs (
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+
+        modport s_inputs (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr
+        );
+
+        modport m_inputs (
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+        );
+endinterface
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_mi_dsc_cpli_if.svh

@@ -0,0 +1,41 @@
+`ifndef DMA_PCIE_MI_DSC_CPLI_IF_SV
+`define DMA_PCIE_MI_DSC_CPLI_IF_SV
+`include "dma_defines.vh"
+interface dma_pcie_mi_dsc_cpli_if();
+        logic   [9:0]   wadr;  // 10 bits for MULTQ C2H
+        logic   [7:0]   wen;
+        logic   [3:0]  wpar;
+        logic   [`CPLI_WIDTH-1:0] wdat;
+        logic           ren;
+        logic   [9:0]   radr;  // 10 bits for MULTQ C2H
+        logic   [3:0]  rpar;
+        logic   [`CPLI_WIDTH-1:0] rdat;
+        logic           rsbe;
+        logic           rdbe;
+
+        modport  m (
+                output  wadr,
+                output  wen,
+                output  wpar,
+                output  wdat,
+                output  ren,
+                output  radr,
+                input   rpar,
+                input   rdat,
+                input   rsbe,
+                input   rdbe
+         );
+        modport  s (
+                input   wadr,
+                input   wen,
+                input   wpar,
+                input   wdat,
+                input   ren,
+                input   radr,
+                output  rpar,
+                output  rdat,
+                output  rsbe,
+                output  rdbe
+         );
+endinterface
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_misc_input_if.svh

@@ -0,0 +1,157 @@
+`ifndef IF_PCIE_DMA_MISC_INPUT_SV
+`define IF_PCIE_DMA_MISC_INPUT_SV
+
+interface dma_pcie_misc_input_if();
+logic          cfg_interrupt_msi_mask_update;
+logic          cfg_err_cor_out;
+logic          cfg_err_fatal_out;
+logic          cfg_err_nonfatal_out;
+logic          cfg_ext_read_received;
+logic          cfg_ext_write_received;
+logic          cfg_hot_reset_out;
+logic          cfg_interrupt_msi_enable;
+logic          cfg_interrupt_msi_fail;
+logic          cfg_interrupt_msi_sent;
+logic          cfg_interrupt_msix_fail;
+logic          cfg_interrupt_msix_sent;
+logic          cfg_interrupt_sent;
+logic          cfg_local_error;
+logic          cfg_mgmt_read_write_done;
+logic          cfg_msg_received;
+logic          cfg_msg_transmit_done;
+logic          cfg_per_function_update_done;
+logic          cfg_phy_link_down;
+logic          pcie_rq_seq_num_vld0;
+logic          pcie_rq_seq_num_vld1;
+logic   [15:0] cfg_function_status;
+logic   [15:0] cfg_per_func_status_data;
+logic   [3:0]  cfg_interrupt_msix_enable;
+logic   [3:0]  cfg_interrupt_msix_mask;
+logic   [1:0]  cfg_phy_link_status;
+logic   [251:0]cfg_vf_flr_in_process;
+logic   [2:0]  cfg_current_speed;
+logic   [2:0]  cfg_max_payload;
+logic   [2:0]  cfg_max_read_req;
+logic   [31:0] cfg_ext_write_data;
+logic   [31:0] cfg_mgmt_read_data;
+logic   [3:0]  cfg_ext_write_byte_enable;
+logic   [3:0]  cfg_flr_in_process;
+logic   [3:0]  cfg_negotiated_width;
+logic   [5:0]  pcie_cq_np_req_count;
+logic   [3:0]  pcie_rq_seq_num0;
+logic   [3:0]  pcie_rq_seq_num1;
+logic   [3:0]  pcie_tfc_nph_av;
+logic   [4:0]  cfg_msg_received_type;
+logic   [5:0]  cfg_interrupt_msix_vf_enable;
+logic   [5:0]  cfg_interrupt_msix_vf_mask;
+logic   [5:0]  cfg_ltssm_state;
+logic          cfg_pl_status_change;
+logic   [7:0]  cfg_ext_function_number;
+logic   [7:0]  cfg_msg_received_data;
+logic   [7:0]  cfg_fc_nph;
+logic   [9:0]  cfg_ext_register_number;
+
+modport s (
+input   cfg_interrupt_msi_mask_update,
+input   cfg_err_cor_out,
+input   cfg_err_fatal_out,
+input   cfg_err_nonfatal_out,
+input   cfg_ext_read_received,
+input   cfg_ext_write_received,
+input   cfg_hot_reset_out,
+input   cfg_interrupt_msi_enable,
+input   cfg_interrupt_msi_fail,
+input   cfg_interrupt_msi_sent,
+input   cfg_interrupt_msix_fail,
+input   cfg_interrupt_msix_sent,
+input   cfg_interrupt_sent,
+input   cfg_local_error,
+input   cfg_mgmt_read_write_done,
+input   cfg_msg_received,
+input   cfg_msg_transmit_done,
+input   cfg_per_function_update_done,
+input   cfg_phy_link_down,
+input   pcie_cq_np_req_count,
+input   pcie_rq_seq_num_vld0,
+input   pcie_rq_seq_num_vld1,
+input   cfg_function_status,
+input   cfg_per_func_status_data,
+input   cfg_interrupt_msix_enable,
+input   cfg_interrupt_msix_mask,
+input   cfg_phy_link_status,
+input   cfg_vf_flr_in_process,
+input   cfg_current_speed,
+input   cfg_max_payload,
+input   cfg_max_read_req,
+input   cfg_ext_write_data,
+input   cfg_mgmt_read_data,
+input   cfg_ext_write_byte_enable,
+input   cfg_flr_in_process,
+input   cfg_negotiated_width,
+input   pcie_rq_seq_num0,
+input   pcie_rq_seq_num1,
+input   pcie_tfc_nph_av,
+input   cfg_msg_received_type,
+input   cfg_interrupt_msix_vf_enable,
+input   cfg_interrupt_msix_vf_mask,
+input   cfg_ltssm_state,
+input   cfg_pl_status_change,
+input   cfg_ext_function_number,
+input   cfg_msg_received_data,
+input   cfg_fc_nph,
+input   cfg_ext_register_number
+);
+
+modport m (
+output   cfg_interrupt_msi_mask_update,
+output   cfg_err_cor_out,
+output   cfg_err_fatal_out,
+output   cfg_err_nonfatal_out,
+output   cfg_ext_read_received,
+output   cfg_ext_write_received,
+output   cfg_hot_reset_out,
+output   cfg_interrupt_msi_enable,
+output   cfg_interrupt_msi_fail,
+output   cfg_interrupt_msi_sent,
+output   cfg_interrupt_msix_fail,
+output   cfg_interrupt_msix_sent,
+output   cfg_interrupt_sent,
+output   cfg_local_error,
+output   cfg_mgmt_read_write_done,
+output   cfg_msg_received,
+output   cfg_msg_transmit_done,
+output   cfg_per_function_update_done,
+output   cfg_phy_link_down,
+output   pcie_cq_np_req_count,
+output   pcie_rq_seq_num_vld0,
+output   pcie_rq_seq_num_vld1,
+output   cfg_function_status,
+output   cfg_per_func_status_data,
+output   cfg_interrupt_msix_enable,
+output   cfg_interrupt_msix_mask,
+output   cfg_phy_link_status,
+output   cfg_vf_flr_in_process,
+output   cfg_current_speed,
+output   cfg_max_payload,
+output   cfg_max_read_req,
+output   cfg_ext_write_data,
+output   cfg_mgmt_read_data,
+output   cfg_ext_write_byte_enable,
+output   cfg_flr_in_process,
+output   cfg_negotiated_width,
+output   pcie_rq_seq_num0,
+output   pcie_rq_seq_num1,
+output   pcie_tfc_nph_av,
+output   cfg_msg_received_type,
+output   cfg_interrupt_msix_vf_enable,
+output   cfg_interrupt_msix_vf_mask,
+output   cfg_ltssm_state,
+output   cfg_pl_status_change,
+output   cfg_ext_function_number,
+output   cfg_msg_received_data,
+output   cfg_fc_nph,
+output   cfg_ext_register_number
+);
+endinterface : dma_pcie_misc_input_if
+
+`endif

src/ip/xdma_0/hdl/verilog/dma_pcie_misc_output_if.svh

@@ -0,0 +1,158 @@
+`ifndef IF_PCIE_DMA_MISC_OUTPUT_SV
+`define IF_PCIE_DMA_MISC_OUTPUT_SV
+
+interface dma_pcie_misc_output_if();
+logic  [2:0]       cfg_fc_sel;
+logic  [1:0]       pcie_cq_np_req;
+logic  [18:0]      cfg_mgmt_addr;
+logic              cfg_mgmt_write;
+logic  [31:0]      cfg_mgmt_write_data;
+logic  [3:0]       cfg_mgmt_byte_enable;
+logic              cfg_mgmt_read;
+logic  [7:0]       cfg_mgmt_function_number;
+logic              cfg_mgmt_type1_cfg_reg_access;
+logic  [7:0]       cfg_ds_port_number;
+logic  [7:0]       cfg_ds_bus_number;
+logic  [4:0]       cfg_ds_device_number;
+logic  [2:0]       cfg_ds_function_number;
+logic  [2:0]       cfg_per_func_status_control;
+logic  [6:0]       cfg_per_function_number;
+logic              cfg_per_function_output_request;
+logic              cfg_per_function_logic_request;
+logic              cfg_msg_transmit;
+logic  [2:0]       cfg_msg_transmit_type;
+logic  [31:0]      cfg_msg_transmit_data;
+//logic  [15:0]      cfg_subsys_id;
+//logic  [15:0]      cfg_subsys_vend_id;
+//logic  [15:0]      cfg_vend_id;
+logic  [63:0]      cfg_dsn;
+logic              cfg_err_cor_in;
+logic              cfg_err_uncor_in;
+logic              cfg_link_training_enable;
+logic  [31:0]      cfg_ext_read_data;
+logic              cfg_ext_read_data_valid;
+logic  [3:0]       cfg_flr_done;
+logic              cfg_vf_flr_done;
+logic  [7:0]       cfg_vf_flr_func_num;
+logic              cfg_config_space_enable;
+logic              cfg_hot_reset_in;
+logic  [31:0]      cfg_interrupt_msi_int;
+logic  [31:0]      cfg_interrupt_msi_pending_status;
+logic              cfg_interrupt_msi_pending_status_data_enable;
+logic  [3:0]       cfg_interrupt_msi_pending_status_function_num;
+logic  [2:0]       cfg_interrupt_msi_attr;
+logic              cfg_interrupt_msi_tph_present;
+logic  [1:0]       cfg_interrupt_msi_tph_type;
+logic  [8:0]       cfg_interrupt_msi_tph_st_tag;
+logic  [3:0]       cfg_interrupt_msi_function_number;
+logic              cfg_interrupt_msix_int;
+logic  [31:0]      cfg_interrupt_msix_data;
+logic  [255:0]     cfg_interrupt_msix_address;
+logic  [3:0]       cfg_interrupt_int;
+logic  [3:0]       cfg_interrupt_pending;
+
+modport m (
+output      cfg_fc_sel,
+output      pcie_cq_np_req,
+output      cfg_mgmt_addr,
+output      cfg_mgmt_write,
+output      cfg_mgmt_write_data,
+output      cfg_mgmt_byte_enable,
+output      cfg_mgmt_read,
+output      cfg_mgmt_function_number,
+output      cfg_mgmt_type1_cfg_reg_access,
+output      cfg_ds_port_number,
+output      cfg_ds_bus_number,
+output      cfg_ds_device_number,
+output      cfg_ds_function_number,
+output      cfg_per_function_output_request,
+output      cfg_per_function_logic_request,
+output      cfg_per_func_status_control,
+output      cfg_per_function_number,
+output      cfg_msg_transmit,
+output      cfg_msg_transmit_type,
+output      cfg_msg_transmit_data,
+//output      cfg_rev_id,
+//output      cfg_subsys_id,
+//output      cfg_subsys_vend_id,
+//output      cfg_vend_id,
+output      cfg_dsn,
+output      cfg_err_cor_in,
+output      cfg_err_uncor_in,
+output      cfg_link_training_enable,
+output      cfg_ext_read_data,
+output      cfg_ext_read_data_valid,
+output      cfg_flr_done,
+output      cfg_vf_flr_done,
+output      cfg_vf_flr_func_num,
+output      cfg_config_space_enable,
+output      cfg_hot_reset_in,
+output      cfg_interrupt_msi_int,
+output      cfg_interrupt_msi_pending_status,
+output      cfg_interrupt_msi_pending_status_data_enable,
+output      cfg_interrupt_msi_pending_status_function_num,
+output      cfg_interrupt_msi_attr,
+output      cfg_interrupt_msi_tph_present,
+output      cfg_interrupt_msi_tph_type,
+output      cfg_interrupt_msi_tph_st_tag,
+output      cfg_interrupt_msi_function_number,
+output      cfg_interrupt_msix_int,
+output      cfg_interrupt_msix_data,
+output      cfg_interrupt_msix_address,
+output      cfg_interrupt_int,
+output      cfg_interrupt_pending
+);
+
+modport s (
+input      cfg_fc_sel,
+input      pcie_cq_np_req,
+input      cfg_mgmt_addr,
+input      cfg_mgmt_write,
+input      cfg_mgmt_write_data,
+input      cfg_mgmt_byte_enable,
+input      cfg_mgmt_read,
+input      cfg_mgmt_function_number,
+input      cfg_mgmt_type1_cfg_reg_access,
+input      cfg_ds_port_number,
+input      cfg_ds_bus_number,
+input      cfg_ds_device_number,
+input      cfg_ds_function_number,
+input      cfg_per_func_status_control,
+input      cfg_per_function_number,
+input      cfg_per_function_output_request,
+input      cfg_per_function_logic_request,
+input      cfg_msg_transmit,
+input      cfg_msg_transmit_type,
+input      cfg_msg_transmit_data,
+//input      cfg_rev_id,
+//input      cfg_subsys_id,
+//input      cfg_subsys_vend_id,
+//input      cfg_vend_id,
+input      cfg_dsn,
+input      cfg_err_cor_in,
+input      cfg_err_uncor_in,
+input      cfg_link_training_enable,
+input      cfg_ext_read_data,
+input      cfg_ext_read_data_valid,
+input      cfg_flr_done,
+input      cfg_vf_flr_done,
+input      cfg_vf_flr_func_num,
+input      cfg_config_space_enable,
+input      cfg_hot_reset_in,
+input      cfg_interrupt_msi_int,
+input      cfg_interrupt_msi_pending_status,
+input      cfg_interrupt_msi_pending_status_data_enable,
+input      cfg_interrupt_msi_pending_status_function_num,
+input      cfg_interrupt_msi_attr,
+input      cfg_interrupt_msi_tph_present,
+input      cfg_interrupt_msi_tph_type,
+input      cfg_interrupt_msi_tph_st_tag,
+input      cfg_interrupt_msi_function_number,
+input      cfg_interrupt_msix_int,
+input      cfg_interrupt_msix_data,
+input      cfg_interrupt_msix_address,
+input      cfg_interrupt_int,
+input      cfg_interrupt_pending
+);
+endinterface : dma_pcie_misc_output_if
+`endif

src/ip/xdma_0/hdl/verilog/dma_soft_defines.vh

@@ -0,0 +1,6 @@
+`ifndef DMA_SOFT_DEFINES_VH
+`define DMA_SOFT_DEFINES_VH
+
+`define SOFT_IP
+
+`endif

src/ip/xdma_0/hdl/verilog/pcie_dma_attr_defines.svh

@@ -0,0 +1,162 @@
+`ifndef PCIE_DMA_ATTR_DEFINES_VH
+`define PCIE_DMA_ATTR_DEFINES_VH
+
+typedef struct packed {
+    logic  [255:213] unused;                       //255:213
+    logic           dis_pfch_evict_cache_fix;      //212      // If set, disable the prefetch eviction fix in cache
+    logic           dis_pfch_evict_lru_fix;        //211      // If set, disable the prefetch eviction fix in lru
+    logic           dis_crdt_coal_depth_fix;       //210      // If set, disable the credit coal fifo depth fix
+    logic           dis_timer_stall_fix;           //209      // If set, disable the mdma timer stall fix
+    logic  [3:0]    qinv_cnt_limit;                //208:205  // If qinv_limit_en is set, this is the limit of qinv from dsc engine through c2h st pfch_evt_fifo that is allowed.
+    logic           qinv_limit_en;                 //204      // If set, limit the number of qinvalidation in the pipe from dsc engine through C2H ST pfch_evt_fifo
+    logic           qinv_arb_stall;                //203      // If set, allow descriptor fetching to continue even if tm_dsc_sts is full.
+    logic           brdg_rro_en;                   //202      // If set, enable relaxed ordering for all bridge slave reads to pcie.
+    logic           mm_wbrq_ovf_fix_dis;           //201      // If set, disable fix to prevent qdma writeback fifo overflow in the MM engine.
+    logic           pcie_mrs_reg_en;               //200      // If set, pcie max read size used will be defined by register
+    logic           pcie_mpl_reg_en;               //199      // If set, pcie max payload used will be define by register
+    logic           bdg_mst_rw_rlx_dis;            //198      // If set, disable the fix to bypass r/w ordering based on attr[1]
+    logic           dis_wrb_prty_chk_fix;          //197      // If set, disable the fix to check WRB parity C2H WRB
+    logic           dis_h2c_sbe_dbe_err_fix;       //196      // If set, disable the fix to handle sbe/dbe on h2c-st
+    logic           dis_wrb_bad_cidx_chk_fix;      //195      // If set, disable the fix to check bad cidx update in C2H WRB
+    logic           dis_xdma_wcp_err_bsy_clr;      //194      // If set, disable fix to clear busy bit in event of wcp error.  Needed for surprise xdma  FLR.
+    logic           dis_acc_irq;                   //193      // If set, disable MM/H2C ST periodic interrupts in wb_acc mode
+    logic           dis_h2c_wrb_on_src_err_fix;    //192      // If set, disable the fix to send wrb on h2c src err
+    logic           sw_crdt_fix_dis;               //191      // If set, disable the sw_crdt fix in c2h_pfch_crdt
+    logic           fix_dbe_parity_dis;            //190      // If set, disable fix for EDT-985612, generate invalid parity on dbe at write interfaces
+    logic           pcie_rq_vf_flr_check_dis;      //189      // If set, flr for vfs will be assumed to be false in dma_pcie_req
+    logic           pcie_rq_pf_flr_check_dis;      //188      // If set, flr for pfs will be assumed to be false in dma_pcie_req
+    logic           mm_err_wbk_fix_dis;            //187      // If set, disable the fix for the write completion from the DMA Write Engine
+    logic           dis_c2h_ctxt_mgr_fix;          //186      // If set, disable the C2H fix for ctxt mgr, affects both wrb and pfch
+    logic           full_upd_fix_dis;              //185      // If set, disable the full_upd feature in the C2H-ST WRB
+    logic           slv_bresp_fix_dis;             //184      // If set, disable the fix for Slave Bresp (1: slv_wrq_commit; 0: slave_wcp_vld)
+    logic           wr_cmp_fix_dis;                //183      // If set, disable the fix for the write completion from the DMA Write Engine
+    logic           rcv_crd_chk_dis;               //182      // If set, disable dsc engine received credit check
+    logic           cfg_space_delay_en;            //181      // If set, enable Bridge register to control config space enable in the EP mode
+    logic  [31:0]   misc_cap;                      //180:149  // Misc capability registers, register accessible
+    logic           st_rx_msg_if_en;               //148      // If set, send vdm to the streaming i/f
+    logic           exp_rom_bar_to_axil;           //147      // If set, send hits to bar 6 (exp rom) to axi-lite
+    logic           pcie_rq_vf_bme_check_dis;      //146      // If set, bme for vfs will be assumed to be true.
+    logic           dsc_upd_ovf_dis;               //145      // If set, disable descriptor overflow detection.
+    logic           tm_dsc_sts_pidx_en;            //144      // If set, send out pidx instead of new descriptors available.
+    logic           dsc_ctxt_is_mm_en;             //143      // If set, the interface (st or mm) is determined by sw_ctxt.sts.is_mm instead of dsc_sz.
+    logic           trq_timeout_dat;               //142      // If set, return all 1 for tcp timeout data, else all 0
+    logic           trq_timeout_rsp;               //141      // If set, return all slv_err for tcp timeout response, else okay
+    logic           dsc_ctxt_err_on_rcp_ur_ca_dis; //140      // If set, the context error bit will not be set if a dsc fetch receives an ur_ca error including bme check failure
+    logic           cfg_mgmt_ep_wr_dis;            //139      // 1'b1: Disable CFG MGMT Write in EP and back to legacy; 1'b0: Enable
+    logic           axi_slv_brdge_range;           //138      // 1'b1: 16M, 1'b0: 256M 
+    logic           dsc_ctxt_err_on_rcp_flr_dis;   //137      // If set, the context error bit will be set if a dsc fetch receives an flr abort
+    logic           dma_rq_0len_dis;               //136      // If set, disble 0 length read support.
+    logic           ign_byp_irq_arm;               //135      // If set, in bypass mode ignore the irq arm bit
+    logic           dma_mm_linkdown_reset_dis;     //134      // If set, do not reset mm engine rrq, wrq fifos
+    logic           rsv_use_h2c_data_aln;          //133      // Reserved. Was: If set, H2C data to AXIS will be aligned and packed
+    logic           dma_rst_rc_rdy;                //132      // If set, assert rc_tready when dma in under reset.
+    logic           ign_pidx_upd_on_irq_arm;       //131      // If irq_arm bit is set by trq write, do not update the pidx
+    logic           use_stm_dsc_format;            //130      // Makes QDMA work on STM descriptor format
+    logic           dma_aximm_rsp_clr;             //129      // Clear aximm rsp count for channel when run bit is asserted.
+    logic           dsc_qinv_on_err_dis;           //128      // Invalidate queue on error disable
+    logic           xdma_drain_dat_en;             //127      // Enable draining of dat when run bit is not set for xdma.  Set to 1 for Evereset
+    logic           xdma_drain_dsc_en;             //126      // Enable draining of dsc when run bit is not set for xdma.  Set to 1 for Evereset
+    logic           disable_port_id_check;         //125      // Disable the port_id check
+    logic           wb_sts_all;                    //124      // All writeback check results from dsc engine are output to wb sts port
+    logic  [11:0]   brdg_slv_wr_pasid_offset;      //123:112  // Pasid index offset for bridge slave write requests if shared_rdwr_pasid_dis is set
+    logic           brdg_slv_shared_rdwr_pasid_dis;//111      // Enable different pasid for rd and writes from bridge slave.
+    logic           dsc_stall_irq_fl_dis ;//110               // Disable stall descriptor context if dsc engine has too many irqs to send.
+    logic           axi_parity_chk_dis   ;//109               // Disable AXI slave parity checks
+    logic  [7:0]    slv_fnc_msk          ;//108:101           // Mask for function bits received by aximm slave. Useful if number of functions supported needs less than 8 bits.  Upper bits can then be used for SMID
+    logic           dsc_rcp_evt_pri      ;//100               // Rcp events have priority for dsc context lookup
+    logic           fabric_reset_en      ;//99                // Enable reset from fabric // Not hooked up to reset yet
+    logic           rrq_disable_en       ;//98                // Block new read requests on RQ timeout or register write
+    logic           shared_rdwr_pasid_dis;//97                // Reads and writes for a qid/function will share the same pasid index.
+    logic  [11:0]   brdg_slv_pasid_offset;//96:85             // Pasid index offset for bridge slave requests
+    logic           fab_wb_dis           ;//84                // Send out mdma writeback check completions qid/cidx through the descriptor bypass output interface.
+    logic           axis_h2c_ext_cmp_en  ;//83                // Use external signal to indicating h2c stream packet is complete, for the purpose of issueing writeback and interrupts.
+    logic           axim_auser_mode      ;//82                // Everest only attribute, 1 will pass {vfg, vfg_off} instead of address[63:50]
+    logic           dma_bar_ext_en       ;//81                // Enable DMA bar aperture to extranal MM or external Lite interface.
+    logic  [4:0]    tcp_timeout_exp      ;//80:76             // Exponential timer for TRQ completion timeout;  2^exp,  0 = disabled
+    logic           brdg_slv_pasid_en    ;// 75               // Pasid_en below must also be set to enable pasid for the bridge slave
+    logic           system_id_ovr        ;// 74
+    logic  [15:0]   system_id            ;//73:58             // System ID csr[15:0]
+    logic           rq_flr_check_dis     ;// 57               // Disable RQ FLR check
+    logic           pasid_en             ;// 56               // Enable PASID
+    logic  [2:0]    vf_bar_num           ;//55:53             // Bar number of VFs
+    logic           pcie_rc_unmask_uc    ; //52               // Unmask unexpected completions coming out or dma_pcie_rc
+    logic           dsc_ecc_chk_dis      ; //51               // Disable ECC check
+    logic           mdma_one_err_wb_dis  ; //50               // If set, allow more writebacks for queue even if writeback with error was sent already
+    logic           mdma_dsc_wb_chk_all  ; //49               // Set wb_chk (if ctxt enabled) on all descriptors of fetch even if not last
+    logic           mdma_dsc_wb_imm_all  ; //48               //  Set wb_imm (if ctxt enabled) on all descriptors of fetch even if not last
+    logic           xdma_byp_eng_flr_done; //47               // Ignore xdma engines for flr_done
+    logic           mdma_eng_err_halt    ; //46               // Halt mdma mm engine on logging error in status reg
+    logic           mdma_sw_ctxt_clr_all ; //45               // Clear hw and crd ctxt if sw ctxt cleared
+    logic  [3:0][3:0]  xdma_c2h_axi_wr_cache;//44:41          // awcache for C2H writeback to AXI
+    logic  [3:0]       xdma_c2h_axi_wr_sec  ;//28             // awprot for C2H writeback to AXI
+    logic  [3:0][3:0]  xdma_h2c_axi_rd_cache;//23             // arcache for H2C writeback to AXI
+    logic  [3:0]       xdma_h2c_axi_rd_sec ;//8               // arprot for H2C writeback to AXI
+    logic          mgmt_flr_done_en     ;   //4               // flr_done needs mgmt ifc flr done bit
+    logic  [3:0]   mgmt_flr_done_src_dis;   //3:0             // Disable mgmt flr_done access per PF
+} attr_spare_t;
+
+// DMA PF Attributes
+typedef struct packed {
+    logic    [3:0]       ch_alloc;
+    logic    [1:0]       multq_chbits;
+    logic    [5:0]       multq_maxq;
+    logic    [2:0]       multq_bits;
+    logic    [5:0]       vfmaxq;
+    logic    [2:0]       multq_vfqbits;
+    logic    [7:0]       num_vfs;
+    logic    [7:0]       firstvf_offset;
+} attr_dma_pf_t;
+
+// DMA PCIeBAR to AXIBAR Attributes
+typedef struct packed {
+    logic    [63:12]     bar;
+    logic                sec;
+    logic    [3:0]       cache;
+    logic    [7:0]       len;
+    logic    [31:0]      bar_vf;
+    logic                sec_vf;
+    logic    [3:0]       cache_vf;
+    logic    [7:0]       len_vf;
+} attr_dma_pciebar2axibar_pf_t;
+
+// DMA AXIBAR to PCIeBAR Attributes
+typedef struct packed {
+    logic    [63:0]       base;
+    logic                 as;
+    logic    [7:0]        highaddr;
+    logic    [63:0]       bar;
+} attr_dma_axibar2pciebar_t;
+
+// DMA General Attributes 
+typedef struct packed {
+    logic    [63:0]       axi_slv_brdg_base_addr;
+    logic    [63:0]       axi_slv_multq_base_addr;
+    logic    [63:0]       axi_slv_xdma_base_addr;
+    logic                 enable;
+    logic                 bypass_msix;
+    logic    [2:0]        data_width;
+    logic                 metering_enable;
+    logic    [5:0]        mask50; 
+    logic                 root_port;
+    logic                 msi_rx_decode_en;
+    logic                 pcie_if_parity_check;
+    logic    [31:0]       slvlite_base0;
+    logic    [31:0]       slvlite_base1;
+    logic    [2:0]        barlite0;
+    logic    [2:0]        barlite1;
+    logic    [2:0]        axibar_num;
+    logic    [2:0]        pciebar_num;
+    logic    [3:0]        ch_en;
+    logic    [3:0][1:0]   ch_pfid;
+    logic    [3:0]        ch_multq;
+    logic    [3:0]        ch_stream;
+    logic    [3:0]        ch_c2h_axi_dsc;
+    logic    [3:0]        ch_h2c_axi_dsc;
+    logic    [3:0]        ch_multq_ll;
+    logic    [3:0][5:0]   ch_multq_max;
+    logic                 cq_rcfg_en;
+    logic                 rq_rcfg_en;
+    attr_spare_t          spare;
+} attr_dma_t;
+
+`endif

src/ip/xdma_0/hdl/verilog/pciedmacoredefines.vh

@@ -0,0 +1,453 @@
+/*****************************************************************************
+** (c) Copyright 2007-2013 Xilinx, Inc. All rights reserved.
+**
+** This file contains confidential and proprietary information
+** of Xilinx, Inc. and is protected under U.S. and
+** international copyright and other intellectual property
+** laws.
+**
+** DISCLAIMER
+** This disclaimer is not a license and does not grant any
+** rights to the materials distributed herewith. Except as
+** otherwise provided in a valid license issued to you by
+** Xilinx, and to the maximum extent permitted by applicable
+** law: (1) THESE MATERIALS ARE MADE AVAILABLE AS IS  AND
+** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+** (2) Xilinx shall not be liable (whether in contract or tort,
+** including negligence, or under any other theory of
+** liability) for any loss or damage of any kind or nature
+** related to, arising under or in connection with these
+** materials, including for any direct, or any indirect,
+** special, incidental, or consequential loss or damage
+** (including loss of data, profits, goodwill, or any type of
+** loss or damage suffered as a result of any action brought
+** by a third party) even if such damage or loss was
+** reasonably foreseeable or Xilinx had been advised of the
+** possibility of the same.
+**
+** CRITICAL APPLICATIONS
+** Xilinx products are not designed or intended to be fail-
+** safe, or for use in any application requiring fail-safe
+** performance, such as life-support or safety devices or
+** systems, Class III medical devices, nuclear facilities,
+** applications related to the deployment of airbags, or any
+** other applications that could lead to death, personal
+** injury, or severe property or environmental damage
+** (individually and collectively, ; Critical; 
+** Applications). Customer assumes the sole risk and
+** liability of any use of Xilinx products in Critical
+** Applications, subject only to applicable laws and
+** regulations governing limitations on product liability.
+**
+** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+** PART OF THIS FILE AT ALL TIMES.
+******************************************************************************
+**
+**  Project:PCI Express Gen4
+**  Author: Siva Prasad
+**  Date:$DateTime: 2014/08/05 13:55:49 $
+**  Description: PCIE core common defines and Macros
+**  Revision: $Revision: #22 $
+**  Changed By: $Author: dpan $
+**
+*****************************************************************************/
+`timescale 1ps/1ps
+
+`ifdef PCIEDMACOREDEFINES_VH
+`else
+    `define PCIEDMACOREDEFINES_VH
+// Default is asynchronous reset flops
+// X REG with async clear and sync load (reset), and enable
+`define XPLREG_EN(clk,reset_n,load,q,d,rstval,ldval,en) \
+`ifndef SYNC_FF \
+`XPLREG_ASYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \
+`else \
+`XPLREG_SYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \
+`endif
+
+
+`define XPLREG_SYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \
+always @(posedge clk)                                   \
+begin                                                   \
+  if (reset_n == 1'b0)                                  \
+    q <= #(TCQ) rstval;                                     \
+  else if (load == 1'b1)                                \
+    q <= #(TCQ) ldval;                                      \
+  else                                                  \
+`ifdef FOURVALCLKPROP                                   \
+    q <= #(TCQ) (en & clk) ? d : q;                         \
+`else                                                   \
+    q <= #(TCQ) en ? d : q;                                 \
+`endif                                                  \
+end
+
+`define XPLREG_ASYNC_EN(clk,reset_n,load,q,d,rstval,ldval,en) \
+always @(posedge clk or negedge reset_n)                \
+begin                                                   \
+  if (reset_n == 1'b0)                                  \
+    q <= #(TCQ) rstval;                                     \
+  else if (load == 1'b1)                                \
+    q <= #(TCQ) ldval;                                      \
+  else                                                  \
+`ifdef FOURVALCLKPROP                                   \
+    q <= #(TCQ) (en & clk) ? d : q;                         \
+`else                                                   \
+    q <= #(TCQ) en ? d : q;                                 \
+`endif                                                  \
+end
+
+// X REG with async clear and sync load (reset)
+`define XPLREG(clk,reset_n,load,q,d,rstval,ldval)       \
+`ifndef SYNC_FF \
+`XPLREG_ASYNC(clk,reset_n,load,q,d,rstval,ldval)       \
+`else \
+`XPLREG_SYNC(clk,reset_n,load,q,d,rstval,ldval)       \
+`endif
+`define XPLREG_SYNC(clk,reset_n,load,q,d,rstval,ldval)       \
+always @(posedge clk)                                   \
+begin                                                   \
+  if (reset_n == 1'b0)                                  \
+    q <= #(TCQ) rstval;                                     \
+  else if (load == 1'b1)                                \
+    q <= #(TCQ) ldval;                                      \
+  else                                                  \
+`ifdef FOURVALCLKPROP                                   \
+    q <= #(TCQ) clk ? d : q;                                \
+`else                                                   \
+    q <= #(TCQ)  d;                                         \
+`endif                                                  \
+end
+`define XPLREG_ASYNC(clk,reset_n,load,q,d,rstval,ldval)       \
+always @(posedge clk or negedge reset_n)                \
+begin                                                   \
+  if (reset_n == 1'b0)                                  \
+    q <= #(TCQ) rstval;                                     \
+  else if (load == 1'b1)                                \
+    q <= #(TCQ) ldval;                                      \
+  else                                                  \
+`ifdef FOURVALCLKPROP                                   \
+    q <= #(TCQ) clk ? d : q;                                \
+`else                                                   \
+    q <= #(TCQ)  d;                                         \
+`endif                                                  \
+end
+
+`define XPREG(clk, reset_n, q,d,rstval)		\
+  `ifndef SYNC_FF                               \
+`XPREG_ASYNC(clk, reset_n, q,d,rstval)		\
+  `else                              \
+`XPREG_SYNC(clk, reset_n, q,d,rstval)		\
+  `endif                            
+`define XPREG_SYNC(clk, reset_n, q,d,rstval)		\
+    always @(posedge clk)	                \
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+`define XPREG_ASYNC(clk, reset_n, q,d,rstval)		\
+    always @(posedge clk or negedge reset_n )	\
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+
+`define XPREG_EN(clk, reset_n, q, d, rstval, en)    \
+   `ifndef SYNC_FF                                  \
+`XPREG_ASYNC_EN(clk, reset_n, q, d, rstval, en)    \
+   `else                                 \
+`XPREG_SYNC_EN(clk, reset_n, q, d, rstval, en)    \
+   `endif
+`define XPREG_SYNC_EN(clk, reset_n, q, d, rstval, en)    \
+    always @(posedge clk)	                    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) (en & clk) ? d : q;		    \
+	  `else					    \
+	    q <= #(TCQ) en ? d : q;			    \
+	  `endif				    \
+     end
+`define XPREG_ASYNC_EN(clk, reset_n, q, d, rstval, en)    \
+    always @(posedge clk or negedge reset_n)	    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) (en & clk) ? d : q;		    \
+	  `else					    \
+	    q <= #(TCQ) en ? d : q;			    \
+	  `endif				    \
+     end
+
+`define XPREG_NORESET(clk,q,d)			    \
+    always @(posedge clk)			    \
+    begin					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) clk? d : q;			    \
+	  `else					    \
+	    q <= #(TCQ) d;				    \
+	  `endif				    \
+     end
+
+`define XARREG(clk, reset_n, q,d,rstval)	\
+`ifndef SYNC_FF                              \
+`XARREG_ASYNC(clk, reset_n, q,d,rstval)	\
+`else                             \
+`XARREG_SYNC(clk, reset_n, q,d,rstval)	\
+`endif
+`define XARREG_SYNC(clk, reset_n, q,d,rstval)	\
+    always @(posedge clk)	                \
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+`define XARREG_ASYNC(clk, reset_n, q,d,rstval)	\
+    always @(posedge clk or negedge reset_n )	\
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+
+`define XARREG_EN(clk, reset_n, q, d, rstval, en)   \
+`ifndef SYNC_FF                                  \
+`XARREG_ASYNC_EN(clk, reset_n, q, d, rstval, en)   \
+`else                                 \
+`XARREG_SYNC_EN(clk, reset_n, q, d, rstval, en)   \
+`endif
+`define XARREG_SYNC_EN(clk, reset_n, q, d, rstval, en)   \
+    always @(posedge clk)	                    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) ((en & clk)  ? d : q);		    \
+	  `else					    \
+	    q <= #(TCQ) (en ? d : q);			    \
+	  `endif				    \
+     end
+`define XARREG_ASYNC_EN(clk, reset_n, q, d, rstval, en)   \
+    always @(posedge clk or negedge reset_n)	    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) ((en & clk)  ? d : q);		    \
+	  `else					    \
+	    q <= #(TCQ) (en ? d : q);			    \
+	  `endif				    \
+     end
+
+`define XSRREG(clk, reset_n, q,d,rstval)	\
+`ifndef SYNC_FF                              \
+`XSRREG_ASYNC(clk, reset_n, q,d,rstval)	\
+`else \
+`XSRREG_SYNC(clk, reset_n, q,d,rstval)	\
+`endif
+`define XSRREG_ASYNC(clk, reset_n, q,d,rstval)	\
+    always @(posedge clk or negedge reset_n)    \
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+`define XSRREG_SYNC(clk, reset_n, q,d,rstval)	\
+    always @(posedge clk)	                \
+    begin					\
+     if (reset_n == 1'b0)			\
+         q <= #(TCQ) rstval;				\
+     else					\
+	 `ifdef FOURVALCLKPROP			\
+	    q <= #(TCQ) clk ? d : q;			\
+	  `else					\
+	    q <= #(TCQ)  d;				\
+	  `endif				\
+     end
+
+`define XSRREG_EN(clk, reset_n, q,d,rstval, en)     \
+`ifndef SYNC_FF \
+`XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en)     \
+`else   \
+`XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en)     \
+`endif
+`define XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en)     \
+    always @(posedge clk)	                    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) ((en & clk)  ? d : q);		    \
+	  `else					    \
+	    q <= #(TCQ) (en ? d : q);			    \
+	  `endif				    \
+     end
+`define XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en)     \
+    always @(posedge clk or negedge reset_n)	    \
+    begin					    \
+     if (reset_n == 1'b0)			    \
+         q <= #(TCQ) rstval;				    \
+     else					    \
+         `ifdef FOURVALCLKPROP			    \
+	    q <= #(TCQ) ((en & clk)  ? d : q);		    \
+	  `else					    \
+	    q <= #(TCQ) (en ? d : q);			    \
+	  `endif				    \
+     end
+
+`define XLREG(clk, reset_n) \
+   `ifndef SYNC_FF \
+`XLREGS_ASYNC(clk, reset_n) \
+   `else \
+`XLREGS_SYNC(clk, reset_n) \
+   `endif
+`define XLREGS_SYNC(clk, reset_n) \
+      always @(posedge clk)
+`define XLREGS_ASYNC(clk, reset_n) \
+      always @(posedge clk or negedge reset_n)
+
+// Define for legacy FFs with arguments for edges
+`define XLREG_EDGE(clkedge,clk,rstedge,rst) \
+  `ifndef SYNC_FF \
+`XLREG_ASYNC_EDGE(clkedge,clk,rstedge,rst) \
+  `else \
+`XLREG_SYNC_EDGE(clkedge,clk,rstedge,rst) \
+  `endif
+`define XLREG_SYNC_EDGE(clkedge,clk,rstedge,rst) \
+    always @(clkedge clk)
+`define XLREG_ASYNC_EDGE(clkedge,clk,rstedge,rst) \
+    always @(clkedge clk or rstedge rst)
+
+// Define for legacy FFs with no reset and arguments for edges
+`define XLREG_EDGE_NORESET(clkedge,clk) \
+    always @(clkedge clk) \
+
+//General defines
+`define byte0    7:0
+`define byte1	15:8
+`define byte2	23:16
+`define byte3	31:24
+`define byte4	39:32
+`define byte5	47:40
+`define byte6	55:48
+`define byte7	63:56
+`define byte8	71:64
+`define byte9	79:72
+`define byte10	87:80
+`define byte11	95:88
+`define byte12 103:96
+`define byte13 111:104
+`define byte14 119:112
+`define byte15 127:120
+`define byte16 135:128
+`define byte17 143:136
+`define byte18 151:144
+`define byte19 159:152
+`define byte20 167:160
+`define byte21 175:168
+`define byte22 183:176
+`define byte23 191:184
+`define byte24 199:192
+`define byte25 207:200
+`define byte26 215:208
+`define byte27 223:216
+`define byte28 231:224
+`define byte29 239:232
+`define byte30 247:240
+`define byte31 255:248
+
+`define dw0b0    7:0
+`define dw0b1	15:8
+`define dw0b2	23:16
+`define dw0b3	31:24
+`define dw0b012	23:0
+`define dw0b123	31:8
+`define dw1b0	39:32
+`define dw1b1	47:40
+`define dw1b2	55:48
+`define dw1b3	63:56
+`define dw1b012	55:32
+`define dw1b123	63:40
+`define dw2b0	71:64
+`define dw2b1	79:72
+`define dw2b2	87:80
+`define dw2b3	95:88
+`define dw2b012	87:64
+`define dw2b123	95:72
+`define dw3b0 103:96
+`define dw3b1 111:104
+`define dw3b2 119:112
+`define dw3b3 127:120
+`define dw3b012 119:96
+`define dw3b123 127:104
+`define dw4b0 135:128
+`define dw4b1 143:136
+`define dw4b2 151:144
+`define dw4b3 159:152
+`define dw4b012 151:128
+`define dw4b123 159:136
+`define dw5b0 167:160
+`define dw5b1 175:168
+`define dw5b2 183:176
+`define dw5b3 191:184
+`define dw5b012 183:160
+`define dw5b123 191:168
+`define dw6b0 199:192
+`define dw6b1 207:200
+`define dw6b2 215:208
+`define dw6b3 223:216
+`define dw6b123 223:200
+`define dw6b012 215:192
+`define dw7b0 231:224
+`define dw7b1 239:232
+`define dw7b2 247:240
+`define dw7b3 255:248
+`define dw7b012 247:224
+`define dw7b123 255:232
+
+`define dw0  31:0
+`define dw1  63:32
+`define dw2  95:64
+`define dw3 127:96 
+`define dw4 159:128
+`define dw5 191:160
+`define dw6 223:192
+`define dw7 255:224
+
+`endif

src/ip/xdma_0/hdl/verilog/xdma_axi4mm_axi_bridge.vh

@@ -0,0 +1,202 @@
+`ifndef AXI_BRIDGE_VH
+`define AXI_BRIDGE_VH
+`include "pciedmacoredefines.vh"
+//-----------------------------------------------------------------------------
+// $Id: 
+//-----------------------------------------------------------------------------
+// axi_bridge.vh
+//-----------------------------------------------------------------------------
+// (c) Copyright 2010 - 2016 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and 
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//-----------------------------------------------------------------------------
+// Filename:        axi_bridge.vh
+//
+// Description:     
+//                  
+// This file needs to be included in all modules so that all the modules can commonly 
+// reference state_transitions
+//                   
+//                  
+// VHDL-Standard:   VHDL'93
+//-----------------------------------------------------------------------------
+// Structure:   
+//              Include file
+//
+//-----------------------------------------------------------------------------
+// Revision:        v1.05.a
+// Date:            06/28/12
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1 ps / 1 ps
+`define XSRREG_AXIMM(clk, reset_n, q,d,rstval)        \
+`ifdef SOFT_IP  \
+`XSRREG_SYNC (clk, reset_n, q,d,rstval) \
+`else   \
+`XSRREG_ASYNC (clk, reset_n, q,d,rstval)  \
+`endif 
+
+`define XSRREG_EN_AXIMM(clk, reset_n, q,d,rstval, en)     \
+`ifdef SOFT_IP \
+`XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en) \
+`else \
+`XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en) \
+`endif
+
+`define XSRREG_XDMA(clk, reset_n, q,d,rstval)        \
+`ifdef SOFT_IP  \
+`XSRREG_SYNC (clk, reset_n, q,d,rstval) \
+`else   \
+`XSRREG_ASYNC (clk, reset_n, q,d,rstval)  \
+`endif
+
+`define XSRREG_EN_XDMA(clk, reset_n, q,d,rstval, en)     \
+`ifdef SOFT_IP \
+`XSRREG_SYNC_EN(clk, reset_n, q,d,rstval, en) \
+`else \
+`XSRREG_ASYNC_EN(clk, reset_n, q,d,rstval, en) \
+`endif
+
+`define XLREG_AXIMM(clk, reset_n) \
+`ifdef SOFT_IP \
+`XLREGS_SYNC(clk, reset_n) \
+`else \
+`XLREGS_ASYNC(clk, reset_n)  \
+`endif
+
+`define XLREG_XDMA(clk, reset_n) \
+`ifdef SOFT_IP \
+`XLREGS_SYNC(clk, reset_n) \
+`else \
+`XLREGS_ASYNC(clk, reset_n)  \
+`endif
+
+`define XNRREG_AXIMM(clk,q,d)                            \
+    always @(posedge clk)                            \
+    begin                                            \
+         `ifdef FOURVALCLKPROP                            \
+            q <= #(TCQ) clk? d : q;                            \
+          `else                                            \
+            q <= #(TCQ) d;                                    \
+          `endif                                    \
+     end
+
+`define XNRREG_EN_AXIMM(clk,q,d,en)     \
+    always @(posedge clk)                            \
+    begin                                            \
+         `ifdef FOURVALCLKPROP                            \
+            q <= #(TCQ) ((en & clk)  ? d : q);                    \
+          `else                                            \
+            q <= #(TCQ) (en ? d : q);                            \
+          `endif                                    \
+     end
+
+// AXI Defines
+`define SIZE64 0
+`define SIZE128 1
+`define SIZE256 2
+`define SIZE512 3
+`define CQ_USER_FBELO 0
+`define CQ_USER_FBEHI 3
+`define CQ_USER_LBELO 4
+`define CQ_USER_LBEHI 7
+`define CQ_USER_LBELO_512 8
+`define CQ_USER_LBEHI_512 11
+`define CQ_USER_BELO 8
+`define CQ_USER_BEHI (CQ_USER_BELO +31)
+`define CQ_USER_PARLO 53
+`define CQ_USER_PARLO_512 119
+`define CQ_USER_PARHI (CQ_USER_PARLO +31)
+`define AXIS_MEM_READ 4'h0
+`define AXIS_MEM_WRITE 4'h1
+`define AXIS_IO_READ 4'h2
+`define AXIS_IO_WRITE 4'h3
+`define AXIS_IO_WRITE 4'h3
+`define AXIS_FETCH_ADD 4'h4
+`define AXIS_UCOND_SWAP 4'h5
+`define AXIS_COMP_SWAP 4'h6
+`define AXIS_READ_LCK 4'h7
+`define AXIS_CFGRD_TYPE0 4'h8
+`define AXIS_CFGRD_TYPE1 4'h9
+`define AXIS_CFGWR_TYPE0 4'ha
+`define AXIS_CFGWR_TYPE1 4'hb
+`define AXIS_MSG_GEN 4'hc
+`define AXIS_MSG_VNDDEF 4'hd
+`define AXIS_MSG_ATS 4'he
+`define AXIS_RSVD 4'hf
+
+
+`define AXIMM_RRESP_OK 2'b00
+`define AXIMM_RRESP_EXOK 2'b01
+`define AXIMM_RRESP_SLVERR 2'b10
+`define AXIMM_RRESP_DECERR 2'b11
+//   typedef enum {IDLE_read_reqSM, CHECK_read_reqSM, SEND_REQ, WAIT_FOR_OPEN_SLOT} read_reqSM_STATES ;
+   // Add these to the State machines
+   //signal read_reqSM_cs : read_reqSM_STATES;
+   //signal read_reqSM_ns : read_reqSM_STATES;
+
+//   typedef enum {IDLE_read_dataSM,WAIT_FOR_CPLE, LOAD_READ_COUNTERE, FIRST_BRAM_READE, STR_DATAE, STR_DONEE, WAIT_SLOT_CLRE} read_dataSM_STATES ;
+   // Add This to the appropriate file
+   //signal read_dataSM_cs : read_dataSM_STATES;
+   //signal read_dataSM_ns : read_dataSM_STATES;
+   //signal read_dataSM_cs_d : read_dataSM_STATES;
+   
+//   typedef enum {IDLE_arid_dependencySM, FIND_HISTORY_MATCH, SET_DEPENDENCY, CLEAR_DEPENDENCY} arid_dependencySM_STATES ;
+//   typedef enum {IDLE_write_reqSM, CHECK_write_reqSM, CHECK2, ONE_REQ_ACTIVE, TWO_REQ_ACTIVE} write_reqSM_STATES ;
+
+
+//   typedef enum {IDLE_write_dataSM, FIRST_DATA_WORD, DATA_STREAM, DONE_write_dataSM, WAIT_TLP_START, WAIT_STR_DONE, FIRST_DATA_WORD_2, DATA_STREAM_2, DONE_2} write_dataSM_STATES ;
+
+//function integer clog2;
+//   input [0:7] value; // Input value
+//    begin : dummy
+//        reg [0:7] value_int;
+//        value_int = value;
+//        for (clog2 = 0; value_int > 0; clog2 = clog2 + 1)
+//            value_int = value_int >> 1;
+//   end
+//endfunction
+`endif // AXI_BRIDGE_VH

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip-PCIE_X0Y0.xdc

@@ -0,0 +1,173 @@
+##-----------------------------------------------------------------------------
+##
+## (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+##-----------------------------------------------------------------------------
+## Project    : Series-7 Integrated Block for PCI Express
+## File       : xdma_0_pcie2_ip-PCIE_X0Y0.xdc
+## Version    : 3.3
+#
+###############################################################################
+# Vivado - PCIe GUI / User Configuration 
+###############################################################################
+#
+# Family       - artix7
+# Part         - xc7a100t
+# Package      - fgg484
+# Speed grade  - -2
+# PCIe Block   - PCIE_X0Y0
+#
+# Link Speed   - 2
+# Link Width   - X2
+# AXIST Width  - 64-bit
+# AXIST Frequ  - 2
+#
+###############################################################################
+# User Time Names / User Time Groups / Time Specs
+###############################################################################
+
+###############################################################################
+# User Physical Constraints
+###############################################################################
+
+
+###############################################################################
+# Pinout and Related I/O Constraints
+###############################################################################
+
+
+###############################################################################
+# Physical Constraints
+###############################################################################
+#
+# Transceiver instance placement.  This constraint selects the
+# transceivers to be used, which also dictates the pinout for the
+# transmit and receive differential pairs.  Please refer to the
+# Virtex-7 GT Transceiver User Guide (UG) for more information.
+#
+
+# PCIe Lane 0
+set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+# PCIe Lane 1
+set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+
+# GTP Common Placement
+set_property LOC GTPE2_COMMON_X0Y1 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gtp_common.gtpe2_common_i}]
+
+#
+# PCI Express Block placement. This constraint selects the PCI Express
+# Block to be used.
+#
+
+set_property LOC PCIE_X0Y0 [get_cells inst/pcie_top_i/pcie_7x_i/pcie_block_i]
+
+#
+# BlockRAM placement
+#
+set_property LOC RAMB36_X2Y36 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[3].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
+set_property LOC RAMB36_X1Y37 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[2].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
+set_property LOC RAMB36_X1Y36 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[1].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
+set_property LOC RAMB36_X1Y35 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[0].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
+set_property LOC RAMB36_X1Y34 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
+set_property LOC RAMB36_X1Y33 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[1].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
+set_property LOC RAMB36_X1Y32 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[2].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
+set_property LOC RAMB36_X1Y31 [get_cells {inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[3].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]
+
+###############################################################################
+# Timing Constraints
+###############################################################################
+#
+create_clock -name txoutclk_x0y0 -period 10 [get_pins {inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i/TXOUTCLK}]
+#
+#
+set_false_path -to [get_pins {inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0}]
+set_false_path -to [get_pins {inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S1}]
+
+
+
+
+#
+create_generated_clock -name clk_125mhz_x0y0 [get_pins inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT0]
+create_generated_clock -name clk_250mhz_x0y0 [get_pins inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT1]
+create_generated_clock -name clk_125mhz_mux_x0y0 \
+                        -source [get_pins inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/I0] \
+                        -divide_by 1 \
+                        [get_pins inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/O]
+#
+create_generated_clock -name clk_250mhz_mux_x0y0 \
+                        -source [get_pins inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/I1] \
+                        -divide_by 1 -add -master_clock [get_clocks -of [get_pins inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/I1]] \
+                        [get_pins inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/O]
+#
+set_clock_groups -name pcieclkmux -physically_exclusive -group clk_125mhz_mux_x0y0 -group clk_250mhz_mux_x0y0
+#
+#
+# Timing ignoring the below pins to avoid CDC analysis, but care has been taken in RTL to sync properly to other clock domain.
+#
+#
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~PLPHYLNKUPN} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ * }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~PLRECEIVEDHOTRST} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ * }]]
+
+#------------------------------------------------------------------------------
+# Asynchronous Paths
+#------------------------------------------------------------------------------
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXELECIDLE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~TXPHINITDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~TXPHALIGNDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~TXDLYSRESETDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXDLYSRESETDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXPHALIGNDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXCDRLOCK} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~CFGMSGRECEIVEDPMETO} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ * }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~PLL0LOCK} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXPMARESETDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXSYNCDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]]
+set_false_path -through [get_pins -filter {REF_PIN_NAME=~TXSYNCDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.gt.* }]]
+
+###############################################################################
+# End
+###############################################################################

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_axi_basic_rx.v

@@ -0,0 +1,212 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_axi_basic_rx.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  TRN to AXI RX module. Instantiates pipeline and null generator RX         //
+//  submodules.                                                               //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_rx                                                          //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_axi_basic_rx #(
+  parameter C_DATA_WIDTH  = 128,          // RX/TX interface data width
+  parameter C_FAMILY      = "X7",         // Targeted FPGA family
+  parameter C_ROOT_PORT   = "FALSE",      // PCIe block is in root port mode
+  parameter C_PM_PRIORITY = "FALSE",      // Disable TX packet boundary thrtl
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter REM_WIDTH  = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8               // KEEP width
+  ) (
+  //---------------------------------------------//
+  // User Design I/O                             //
+  //---------------------------------------------//
+
+  // AXI RX
+  //-----------
+  output  [C_DATA_WIDTH-1:0] m_axis_rx_tdata,        // RX data to user
+  output                     m_axis_rx_tvalid,       // RX data is valid
+  input                      m_axis_rx_tready,       // RX ready for data
+  output    [KEEP_WIDTH-1:0] m_axis_rx_tkeep,        // RX strobe byte enables
+  output                     m_axis_rx_tlast,        // RX data is last
+  output              [21:0] m_axis_rx_tuser,        // RX user signals
+
+  //---------------------------------------------//
+  // PCIe Block I/O                              //
+  //---------------------------------------------//
+
+  // TRN RX
+  //-----------
+  input  [C_DATA_WIDTH-1:0] trn_rd,                  // RX data from block
+  input                     trn_rsof,                // RX start of packet
+  input                     trn_reof,                // RX end of packet
+  input                     trn_rsrc_rdy,            // RX source ready
+  output                    trn_rdst_rdy,            // RX destination ready
+  input                     trn_rsrc_dsc,            // RX source discontinue
+  input     [REM_WIDTH-1:0] trn_rrem,                // RX remainder
+  input                     trn_rerrfwd,             // RX error forward
+  input               [6:0] trn_rbar_hit,            // RX BAR hit
+  input                     trn_recrc_err,           // RX ECRC error
+
+  // System
+  //-----------
+  output              [2:0] np_counter,              // Non-posted counter
+  input                     user_clk,                // user clock from block
+  input                     user_rst                 // user reset from block
+);
+
+
+// Wires
+wire                  null_rx_tvalid;
+wire                  null_rx_tlast;
+wire [KEEP_WIDTH-1:0] null_rx_tkeep;
+wire                  null_rdst_rdy;
+wire            [4:0] null_is_eof;
+
+//---------------------------------------------//
+// RX Data Pipeline                            //
+//---------------------------------------------//
+
+xdma_0_pcie2_ip_axi_basic_rx_pipeline #(
+  .C_DATA_WIDTH( C_DATA_WIDTH ),
+  .C_FAMILY( C_FAMILY ),
+  .TCQ( TCQ ),
+
+  .REM_WIDTH( REM_WIDTH ),
+  .KEEP_WIDTH( KEEP_WIDTH )
+
+) rx_pipeline_inst (
+
+  // Outgoing AXI TX
+  //-----------
+  .m_axis_rx_tdata( m_axis_rx_tdata ),
+  .m_axis_rx_tvalid( m_axis_rx_tvalid ),
+  .m_axis_rx_tready( m_axis_rx_tready ),
+  .m_axis_rx_tkeep( m_axis_rx_tkeep ),
+  .m_axis_rx_tlast( m_axis_rx_tlast ),
+  .m_axis_rx_tuser( m_axis_rx_tuser ),
+
+  // Incoming TRN RX
+  //-----------
+  .trn_rd( trn_rd ),
+  .trn_rsof( trn_rsof ),
+  .trn_reof( trn_reof ),
+  .trn_rsrc_rdy( trn_rsrc_rdy ),
+  .trn_rdst_rdy( trn_rdst_rdy ),
+  .trn_rsrc_dsc( trn_rsrc_dsc ),
+  .trn_rrem( trn_rrem ),
+  .trn_rerrfwd( trn_rerrfwd ),
+  .trn_rbar_hit( trn_rbar_hit ),
+  .trn_recrc_err( trn_recrc_err ),
+
+  // Null Inputs
+  //-----------
+  .null_rx_tvalid( null_rx_tvalid ),
+  .null_rx_tlast( null_rx_tlast ),
+  .null_rx_tkeep( null_rx_tkeep ),
+  .null_rdst_rdy( null_rdst_rdy ),
+  .null_is_eof( null_is_eof ),
+
+  // System
+  //-----------
+  .np_counter( np_counter ),
+  .user_clk( user_clk ),
+  .user_rst( user_rst )
+);
+
+
+ //---------------------------------------------//
+ // RX Null Packet Generator                    //
+ //---------------------------------------------//
+
+xdma_0_pcie2_ip_axi_basic_rx_null_gen #(
+  .C_DATA_WIDTH( C_DATA_WIDTH ),
+  .TCQ( TCQ ),
+
+  .KEEP_WIDTH( KEEP_WIDTH )
+
+ ) rx_null_gen_inst (
+
+  // Inputs
+  //-----------
+  .m_axis_rx_tdata( m_axis_rx_tdata ),
+  .m_axis_rx_tvalid( m_axis_rx_tvalid ),
+  .m_axis_rx_tready( m_axis_rx_tready ),
+  .m_axis_rx_tlast( m_axis_rx_tlast ),
+  .m_axis_rx_tuser( m_axis_rx_tuser ),
+
+  // Null Outputs
+  //-----------
+  .null_rx_tvalid( null_rx_tvalid ),
+  .null_rx_tlast( null_rx_tlast ),
+  .null_rx_tkeep( null_rx_tkeep ),
+  .null_rdst_rdy( null_rdst_rdy ),
+  .null_is_eof( null_is_eof ),
+
+  // System
+  //-----------
+  .user_clk( user_clk ),
+  .user_rst( user_rst )
+ );
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_axi_basic_rx_null_gen.v

@@ -0,0 +1,383 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_axi_basic_rx_null_gen.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  TRN to AXI RX null generator. Generates null packets for use in           //
+//  discontinue situations.                                                   //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_rx                                                          //
+//        axi_basic_rx_null_gen                                               //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_axi_basic_rx_null_gen # (
+  parameter C_DATA_WIDTH = 128,           // RX/TX interface data width
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8            // KEEP width
+  ) (
+
+  // AXI RX
+  //-----------
+  input      [C_DATA_WIDTH-1:0] m_axis_rx_tdata,     // RX data to user
+  input                         m_axis_rx_tvalid,    // RX data is valid
+  input                         m_axis_rx_tready,    // RX ready for data
+  input                         m_axis_rx_tlast,     // RX data is last
+  input                  [21:0] m_axis_rx_tuser,     // RX user signals
+
+  // Null Inputs
+  //-----------
+  output                        null_rx_tvalid,      // NULL generated tvalid
+  output                        null_rx_tlast,       // NULL generated tlast
+  output       [KEEP_WIDTH-1:0] null_rx_tkeep,       // NULL generated tkeep
+  output                        null_rdst_rdy,       // NULL generated rdst_rdy
+  output reg              [4:0] null_is_eof,         // NULL generated is_eof
+
+  // System
+  //-----------
+  input                         user_clk,            // user clock from block
+  input                         user_rst             // user reset from block
+);
+
+
+localparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 :
+                                           (C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;
+
+//----------------------------------------------------------------------------//
+// NULL packet generator state machine                                        //
+// This state machine shadows the AXI RX interface, tracking each packet as   //
+// it's passed to the AXI user. When a multi-cycle packet is detected, the    //
+// state machine automatically generates a "null" packet. In the event of a   //
+// discontinue, the RX pipeline can switch over to this null packet as        //
+// necessary.                                                                 //
+//----------------------------------------------------------------------------//
+
+// State machine variables and states
+localparam            IDLE      = 0;
+localparam            IN_PACKET = 1;
+reg                   cur_state;
+reg                   next_state;
+
+// Signals for tracking a packet on the AXI interface
+reg            [11:0] reg_pkt_len_counter;
+reg            [11:0] pkt_len_counter;
+wire           [11:0] pkt_len_counter_dec;
+wire                  pkt_done;
+
+// Calculate packet fields, which are needed to determine total packet length.
+wire           [11:0] new_pkt_len;
+wire            [9:0] payload_len;
+wire            [1:0] packet_fmt;
+wire                  packet_td;
+reg             [3:0] packet_overhead;
+
+// Misc.
+wire [KEEP_WIDTH-1:0] eof_tkeep;
+wire                  straddle_sof;
+wire                  eof;
+
+
+// Create signals to detect sof and eof situations. These signals vary depending
+// on data width.
+assign eof = m_axis_rx_tuser[21];
+generate
+  if(C_DATA_WIDTH == 128) begin : sof_eof_128
+    assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11);
+  end
+  else begin : sof_eof_64_32
+    assign straddle_sof = 1'b0;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Calculate the length of the packet being presented on the RX interface. To //
+// do so, we need the relevent packet fields that impact total packet length. //
+// These are:                                                                 //
+//   - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //
+//   - Payload length: obtained from LENGTH field in 1st DWORD of header      //
+//   - TLP digest: obtained from TD field in 1st DWORD of header              //
+//   - Current data: the number of bytes that have already been presented     //
+//                   on the data interface                                    //
+//                                                                            //
+// packet length = header + payload + tlp digest - # of DWORDS already        //
+//                 transmitted                                                //
+//                                                                            //
+// packet_overhead is where we calculate everything except payload.           //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : len_calc_128
+    assign packet_fmt  = straddle_sof ?
+                                m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29];
+    assign packet_td   = straddle_sof ?
+                                      m_axis_rx_tdata[79] : m_axis_rx_tdata[15];
+    assign payload_len = packet_fmt[1] ?
+         (straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0;
+
+    always @(*) begin
+      // In 128-bit mode, the amount of data currently on the interface
+      // depends on whether we're straddling or not. If so, 2 DWORDs have been
+      // seen. If not, 4 DWORDs.
+      case({packet_fmt[0], packet_td, straddle_sof})
+        //                        Header +  TD  - Data currently on interface
+        3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4;
+        3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2;
+        3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4;
+        3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
+        3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4;
+        3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2;
+        3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4;
+        3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
+      endcase
+    end
+assign new_pkt_len =
+         {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
+  end
+  else if(C_DATA_WIDTH == 64) begin : len_calc_64
+    assign packet_fmt  = m_axis_rx_tdata[30:29];
+    assign packet_td   = m_axis_rx_tdata[15];
+    assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
+
+    always @(*) begin
+      // 64-bit mode: no straddling, so always 2 DWORDs
+      case({packet_fmt[0], packet_td})
+        //                      Header +  TD  - Data currently on interface
+        2'b0_0: packet_overhead[1:0] = 2'b01 ;//4'd3 + 4'd0 - 4'd2; // 1
+        2'b0_1: packet_overhead[1:0] = 2'b10 ;//4'd3 + 4'd1 - 4'd2; // 2
+        2'b1_0: packet_overhead[1:0] = 2'b10 ;//4'd4 + 4'd0 - 4'd2; // 2 
+        2'b1_1: packet_overhead[1:0] = 2'b11 ;//4'd4 + 4'd1 - 4'd2; // 3
+      endcase
+    end
+assign new_pkt_len =
+         {{10{1'b0}}, packet_overhead[1:0]} + {2'b0, payload_len};
+  end
+  else begin : len_calc_32
+    assign packet_fmt  = m_axis_rx_tdata[30:29];
+    assign packet_td   = m_axis_rx_tdata[15];
+    assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
+
+    always @(*) begin
+      // 32-bit mode: no straddling, so always 1 DWORD
+      case({packet_fmt[0], packet_td})
+        //                      Header +  TD  - Data currently on interface
+        2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1;
+        2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1;
+        2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1;
+        2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1;
+      endcase
+    end
+assign new_pkt_len =
+         {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
+  end
+endgenerate
+
+// Now calculate actual packet length, adding the packet overhead and the
+// payload length. This is signed math, so sign-extend packet_overhead.
+// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this
+//       behavior isn't supported in our block.
+//assign new_pkt_len =
+//         {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
+
+
+// Math signals needed in the state machine below. These are seperate wires to
+// help ensure synthesis tools sre smart about optimizing them.
+assign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;
+assign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
+
+//----------------------------------------------------------------------------//
+// Null generator Mealy state machine. Determine outputs based on:            //
+//   1) current st                                                            //
+//   2) current inp                                                           //
+//----------------------------------------------------------------------------//
+always @(*) begin
+  case (cur_state)
+
+    // IDLE state: the interface is IDLE and we're waiting for a packet to
+    // start. If a packet starts, move to state IN_PACKET and begin tracking
+    // it as long as it's NOT a single cycle packet (indicated by assertion of
+    // eof at packet start)
+    IDLE: begin
+      if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin
+        next_state = IN_PACKET;
+      end
+      else begin
+        next_state = IDLE;
+      end
+
+      pkt_len_counter = new_pkt_len;
+    end
+
+    // IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We
+    // are in lock-step with the AXI interface decrementing our packet length
+    // tracking reg, and waiting for the packet to finish.
+    //
+    // * If packet finished and a new one starts, this is a straddle situation.
+    //   Next state is IN_PACKET (128-bit only).
+    // * If the current packet is done, next state is IDLE.
+    // * Otherwise, next state is IN_PACKET.
+    IN_PACKET: begin
+      // Straddle packet
+      if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin
+        pkt_len_counter = new_pkt_len;
+        next_state = IN_PACKET;
+      end
+
+      // Current packet finished
+      else if(m_axis_rx_tready && pkt_done)
+      begin
+        pkt_len_counter = new_pkt_len;
+        next_state      = IDLE;
+      end
+
+      // Packet in progress
+      else begin
+        if(m_axis_rx_tready) begin
+          // Not throttled
+          pkt_len_counter = pkt_len_counter_dec;
+        end
+        else begin
+          // Throttled
+          pkt_len_counter = reg_pkt_len_counter;
+        end
+
+        next_state = IN_PACKET;
+      end
+    end
+
+    default: begin
+      pkt_len_counter = reg_pkt_len_counter;
+      next_state      = IDLE;
+    end
+  endcase
+end
+
+
+// Synchronous NULL packet generator state machine logic
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    cur_state           <= #TCQ IDLE;
+    reg_pkt_len_counter <= #TCQ 12'h0;
+  end
+  else begin
+    cur_state           <= #TCQ next_state;
+    reg_pkt_len_counter <= #TCQ pkt_len_counter;
+  end
+end
+
+
+// Generate tkeep/is_eof for an end-of-packet situation.
+generate
+  if(C_DATA_WIDTH == 128) begin : strb_calc_128
+    always @(*) begin
+      // Assign null_is_eof depending on how many DWORDs are left in the
+      // packet.
+      case(pkt_len_counter)
+        10'd1:   null_is_eof = 5'b10011;
+        10'd2:   null_is_eof = 5'b10111;
+        10'd3:   null_is_eof = 5'b11011;
+        10'd4:   null_is_eof = 5'b11111;
+        default: null_is_eof = 5'b00011;
+      endcase
+    end
+
+    // tkeep not used in 128-bit interface
+    assign eof_tkeep = {KEEP_WIDTH{1'b0}};
+  end
+  else if(C_DATA_WIDTH == 64) begin : strb_calc_64
+    always @(*) begin
+      // Assign null_is_eof depending on how many DWORDs are left in the
+      // packet.
+      case(pkt_len_counter)
+        10'd1:   null_is_eof = 5'b10011;
+        10'd2:   null_is_eof = 5'b10111;
+        default: null_is_eof = 5'b00011;
+      endcase
+    end
+
+    // Assign tkeep to 0xFF or 0x0F depending on how many DWORDs are left in
+    // the current packet.
+    assign eof_tkeep = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF };
+  end
+  else begin : strb_calc_32
+    always @(*) begin
+      // is_eof is either on or off for 32-bit
+      if(pkt_len_counter == 12'd1) begin
+        null_is_eof = 5'b10011;
+      end
+      else begin
+        null_is_eof = 5'b00011;
+      end
+    end
+
+    // The entire DWORD is always valid in 32-bit mode, so tkeep is always 0xF
+    assign eof_tkeep = 4'hF;
+  end
+endgenerate
+
+
+// Finally, use everything we've generated to calculate our NULL outputs
+assign null_rx_tvalid = 1'b1;
+assign null_rx_tlast  = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
+assign null_rx_tkeep  = null_rx_tlast ? eof_tkeep : {KEEP_WIDTH{1'b1}};
+assign null_rdst_rdy  = null_rx_tlast;
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_axi_basic_rx_pipeline.v

@@ -0,0 +1,623 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_axi_basic_rx_pipeline.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI.  //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_rx                                                          //
+//        axi_basic_rx_pipeline                                               //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_axi_basic_rx_pipeline #(
+  parameter C_DATA_WIDTH = 128,           // RX/TX interface data width
+  parameter C_FAMILY     = "X7",          // Targeted FPGA family
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter REM_WIDTH  = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8               // KEEP width
+  ) (
+
+  // AXI RX
+  //-----------
+  output reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata,     // RX data to user
+  output reg                    m_axis_rx_tvalid,    // RX data is valid
+  input                         m_axis_rx_tready,    // RX ready for data
+  output       [KEEP_WIDTH-1:0] m_axis_rx_tkeep,     // RX strobe byte enables
+  output                        m_axis_rx_tlast,     // RX data is last
+  output reg             [21:0] m_axis_rx_tuser,     // RX user signals
+
+  // TRN RX
+  //-----------
+  input      [C_DATA_WIDTH-1:0] trn_rd,              // RX data from block
+  input                         trn_rsof,            // RX start of packet
+  input                         trn_reof,            // RX end of packet
+  input                         trn_rsrc_rdy,        // RX source ready
+  output reg                    trn_rdst_rdy,        // RX destination ready
+  input                         trn_rsrc_dsc,        // RX source discontinue
+  input         [REM_WIDTH-1:0] trn_rrem,            // RX remainder
+  input                         trn_rerrfwd,         // RX error forward
+  input                   [6:0] trn_rbar_hit,        // RX BAR hit
+  input                         trn_recrc_err,       // RX ECRC error
+
+  // Null Inputs
+  //-----------
+  input                         null_rx_tvalid,      // NULL generated tvalid
+  input                         null_rx_tlast,       // NULL generated tlast
+  input        [KEEP_WIDTH-1:0] null_rx_tkeep,       // NULL generated tkeep
+  input                         null_rdst_rdy,       // NULL generated rdst_rdy
+  input                   [4:0] null_is_eof,         // NULL generated is_eof
+
+  // System
+  //-----------
+  output                  [2:0] np_counter,          // Non-posted counter
+  input                         user_clk,            // user clock from block
+  input                         user_rst             // user reset from block
+);
+
+
+// Wires and regs for creating AXI signals
+wire              [4:0] is_sof;
+wire              [4:0] is_sof_prev;
+
+wire              [4:0] is_eof;
+wire              [4:0] is_eof_prev;
+
+reg    [KEEP_WIDTH-1:0] reg_tkeep;
+wire   [KEEP_WIDTH-1:0] tkeep;
+wire   [KEEP_WIDTH-1:0] tkeep_prev;
+
+reg                     reg_tlast;
+wire                    rsrc_rdy_filtered;
+
+// Wires and regs for previous value buffer
+wire [C_DATA_WIDTH-1:0] trn_rd_DW_swapped;
+reg  [C_DATA_WIDTH-1:0] trn_rd_prev;
+
+wire                    data_hold;
+reg                     data_prev;
+
+reg                     trn_reof_prev;
+reg     [REM_WIDTH-1:0] trn_rrem_prev;
+reg                     trn_rsrc_rdy_prev;
+reg                     trn_rsrc_dsc_prev;
+reg                     trn_rsof_prev;
+reg               [6:0] trn_rbar_hit_prev;
+reg                     trn_rerrfwd_prev;
+reg                     trn_recrc_err_prev;
+
+// Null packet handling signals
+reg                     null_mux_sel;
+reg                     trn_in_packet;
+wire                    dsc_flag;
+wire                    dsc_detect;
+reg                     reg_dsc_detect;
+reg                     trn_rsrc_dsc_d;
+
+
+// Create "filtered" version of rsrc_rdy, where discontinued SOFs are removed.
+assign rsrc_rdy_filtered = trn_rsrc_rdy &&
+                                 (trn_in_packet || (trn_rsof && !trn_rsrc_dsc));
+
+//----------------------------------------------------------------------------//
+// Previous value buffer                                                      //
+// ---------------------                                                      //
+// We are inserting a pipeline stage in between TRN and AXI, which causes     //
+// some issues with handshaking signals m_axis_rx_tready/trn_rdst_rdy. The    //
+// added cycle of latency in the path causes the user design to fall behind   //
+// the TRN interface whenever it throttles.                                   //
+//                                                                            //
+// To avoid loss of data, we must keep the previous value of all trn_r*       //
+// signals in case the user throttles.                                        //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    trn_rd_prev        <= #TCQ {C_DATA_WIDTH{1'b0}};
+    trn_rsof_prev      <= #TCQ 1'b0;
+    trn_rrem_prev      <= #TCQ {REM_WIDTH{1'b0}};
+    trn_rsrc_rdy_prev  <= #TCQ 1'b0;
+    trn_rbar_hit_prev  <= #TCQ 7'h00;
+    trn_rerrfwd_prev   <= #TCQ 1'b0;
+    trn_recrc_err_prev <= #TCQ 1'b0;
+    trn_reof_prev      <= #TCQ 1'b0;
+    trn_rsrc_dsc_prev  <= #TCQ 1'b0;
+  end
+  else begin
+    // prev buffer works by checking trn_rdst_rdy. When trn_rdst_rdy is
+    // asserted, a new value is present on the interface.
+    if(trn_rdst_rdy) begin
+      trn_rd_prev        <= #TCQ trn_rd_DW_swapped;
+      trn_rsof_prev      <= #TCQ trn_rsof;
+      trn_rrem_prev      <= #TCQ trn_rrem;
+      trn_rbar_hit_prev  <= #TCQ trn_rbar_hit;
+      trn_rerrfwd_prev   <= #TCQ trn_rerrfwd;
+      trn_recrc_err_prev <= #TCQ trn_recrc_err;
+      trn_rsrc_rdy_prev  <= #TCQ rsrc_rdy_filtered;
+      trn_reof_prev      <= #TCQ trn_reof;
+      trn_rsrc_dsc_prev  <= #TCQ trn_rsrc_dsc || dsc_flag;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create TDATA                                                               //
+//----------------------------------------------------------------------------//
+
+// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN
+// 128-bit:                 64-bit:                  32-bit:
+// TRN DW0 maps to AXI DW3  TRN DW0 maps to AXI DW1  TNR DW0 maps to AXI DW0
+// TRN DW1 maps to AXI DW2  TRN DW1 maps to AXI DW0
+// TRN DW2 maps to AXI DW1
+// TRN DW3 maps to AXI DW0
+generate
+  if(C_DATA_WIDTH == 128) begin : rd_DW_swap_128
+    assign trn_rd_DW_swapped = {trn_rd[31:0],
+                                trn_rd[63:32],
+                                trn_rd[95:64],
+                                trn_rd[127:96]};
+  end
+  else if(C_DATA_WIDTH == 64) begin : rd_DW_swap_64
+    assign trn_rd_DW_swapped = {trn_rd[31:0], trn_rd[63:32]};
+  end
+  else begin : rd_DW_swap_32
+    assign trn_rd_DW_swapped = trn_rd;
+  end
+endgenerate
+
+
+// Create special buffer which locks in the proper value of TDATA depending
+// on whether the user is throttling or not. This buffer has three states:
+//
+//       HOLD state: TDATA maintains its current value
+//                   - the user has throttled the PCIe block
+//   PREVIOUS state: the buffer provides the previous value on trn_rd
+//                   - the user has finished throttling, and is a little behind
+//                     the PCIe block
+//    CURRENT state: the buffer passes the current value on trn_rd
+//                   - the user is caught up and ready to receive the latest
+//                     data from the PCIe block
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    m_axis_rx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
+  end
+  else begin
+    if(!data_hold) begin
+      // PREVIOUS state
+      if(data_prev) begin
+        m_axis_rx_tdata <= #TCQ trn_rd_prev;
+      end
+
+      // CURRENT state
+      else begin
+        m_axis_rx_tdata <= #TCQ trn_rd_DW_swapped;
+      end
+    end
+    // else HOLD state
+  end
+end
+
+// Logic to instruct pipeline to hold its value
+assign data_hold = (!m_axis_rx_tready && m_axis_rx_tvalid);
+
+// Logic to instruct pipeline to use previous bus values. Always use previous
+// value after holding a value.
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    data_prev <= #TCQ 1'b0;
+  end
+  else begin
+    data_prev <= #TCQ data_hold;
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create TVALID, TLAST, tkeep, TUSER                                         //
+// -----------------------------------                                        //
+// Use the same strategy for these signals as for TDATA, except here we need  //
+// an extra provision for null packets.                                       //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    m_axis_rx_tvalid <= #TCQ 1'b0;
+    reg_tlast        <= #TCQ 1'b0;
+    reg_tkeep        <= #TCQ {KEEP_WIDTH{1'b1}};
+    m_axis_rx_tuser  <= #TCQ 22'h0;
+  end
+  else begin
+    if(!data_hold) begin
+      // If in a null packet, use null generated value
+      if(null_mux_sel) begin
+        m_axis_rx_tvalid <= #TCQ null_rx_tvalid;
+        reg_tlast        <= #TCQ null_rx_tlast;
+        reg_tkeep        <= #TCQ null_rx_tkeep;
+        m_axis_rx_tuser  <= #TCQ {null_is_eof, 17'h0000};
+      end
+
+      // PREVIOUS state
+      else if(data_prev) begin
+        m_axis_rx_tvalid <= #TCQ (trn_rsrc_rdy_prev || dsc_flag);
+        reg_tlast        <= #TCQ trn_reof_prev;
+        reg_tkeep        <= #TCQ tkeep_prev;
+        m_axis_rx_tuser  <= #TCQ {is_eof_prev,          // TUSER bits [21:17]
+                                  2'b00,                // TUSER bits [16:15]
+                                  is_sof_prev,          // TUSER bits [14:10]
+                                  1'b0,                 // TUSER bit  [9]
+                                  trn_rbar_hit_prev,    // TUSER bits [8:2]
+                                  trn_rerrfwd_prev,     // TUSER bit  [1]
+                                  trn_recrc_err_prev};  // TUSER bit  [0]
+      end
+
+      // CURRENT state
+      else begin
+        m_axis_rx_tvalid <= #TCQ (rsrc_rdy_filtered || dsc_flag);
+        reg_tlast        <= #TCQ trn_reof;
+        reg_tkeep        <= #TCQ tkeep;
+        m_axis_rx_tuser  <= #TCQ {is_eof,               // TUSER bits [21:17]
+                                  2'b00,                // TUSER bits [16:15]
+                                  is_sof,               // TUSER bits [14:10]
+                                  1'b0,                 // TUSER bit  [9]
+                                  trn_rbar_hit,         // TUSER bits [8:2]
+                                  trn_rerrfwd,          // TUSER bit  [1]
+                                  trn_recrc_err};       // TUSER bit  [0]
+      end
+    end
+    // else HOLD state
+  end
+end
+
+// Hook up TLAST and tkeep depending on interface width
+generate
+  // For 128-bit interface, don't pass TLAST and tkeep to user (is_eof and
+  // is_data passed to user instead). reg_tlast is still used internally.
+  if(C_DATA_WIDTH == 128) begin : tlast_tkeep_hookup_128
+    assign m_axis_rx_tlast = 1'b0;
+    assign m_axis_rx_tkeep = {KEEP_WIDTH{1'b1}};
+  end
+
+  // For 64/32-bit interface, pass TLAST to user.
+  else begin : tlast_tkeep_hookup_64_32
+    assign m_axis_rx_tlast = reg_tlast;
+    assign m_axis_rx_tkeep = reg_tkeep;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Create tkeep                                                               //
+// ------------                                                               //
+// Convert RREM to STRB. Here, we are converting the encoding method for the  //
+// location of the EOF from TRN flavor (rrem) to AXI (tkeep).                 //
+//                                                                            //
+// NOTE: for each configuration, we need two values of tkeep, the current and //
+//       previous values. The need for these two values is described below.   //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : rrem_to_tkeep_128
+    // TLAST and tkeep not used in 128-bit interface. is_sof and is_eof used
+    // instead.
+    assign tkeep      = 16'h0000;
+    assign tkeep_prev = 16'h0000;
+  end
+  else if(C_DATA_WIDTH == 64) begin : rrem_to_tkeep_64
+    // 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes
+    //  - tkeep has only two possible values here, 0xFF or 0x0F
+    assign tkeep      = trn_rrem      ? 8'hFF : 8'h0F;
+    assign tkeep_prev = trn_rrem_prev ? 8'hFF : 8'h0F;
+  end
+  else begin : rrem_to_tkeep_32
+    // 32-bit interface: contains 1 DWORD per cycle, for a total of 4 bytes
+    //  - tkeep is always 0xF in this case, due to the nature of the PCIe block
+    assign tkeep      = 4'hF;
+    assign tkeep_prev = 4'hF;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Create is_sof                                                              //
+// -------------                                                              //
+// is_sof is a signal to the user indicating the location of SOF in TDATA   . //
+// Due to inherent 64-bit alignment of packets from the block, the only       //
+// possible values are:                                                       //
+//                      Value                      Valid data widths          //
+//                      5'b11000 (sof @ byte 8)    128                        //
+//                      5'b10000 (sof @ byte 0)    128, 64, 32                //
+//                      5'b00000 (sof not present) 128, 64, 32                //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : is_sof_128
+    assign is_sof      = {(trn_rsof && !trn_rsrc_dsc), // bit 4:   enable
+                          (trn_rsof && !trn_rrem[1]),  // bit 3:   sof @ byte 8?
+                          3'b000};                     // bit 2-0: hardwired 0
+
+    assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
+                          (trn_rsof_prev && !trn_rrem_prev[1]),  // bit 3
+                          3'b000};                               // bit 2-0
+  end
+  else begin : is_sof_64_32
+    assign is_sof      = {(trn_rsof && !trn_rsrc_dsc), // bit 4:   enable
+                          4'b0000};                    // bit 3-0: hardwired 0
+
+    assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
+                          4'b0000};                              // bit 3-0
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Create is_eof                                                              //
+// -------------                                                              //
+// is_eof is a signal to the user indicating the location of EOF in TDATA   . //
+// Due to DWORD granularity of packets from the block, the only               //
+// possible values are:                                                       //
+//                      Value                      Valid data widths          //
+//                      5'b11111 (eof @ byte 15)   128                        //
+//                      5'b11011 (eof @ byte 11)   128                        //
+//                      5'b10111 (eof @ byte 7)    128, 64                    //
+//                      5'b10011 (eof @ byte 3)`   128, 64, 32                //
+//                      5'b00011 (eof not present) 128, 64, 32                //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : is_eof_128
+    assign is_eof      = {trn_reof,      // bit 4:   enable
+                          trn_rrem,      // bit 3-2: encoded eof loc rom block
+                          2'b11};        // bit 1-0: hardwired 1
+
+    assign is_eof_prev = {trn_reof_prev, // bit 4:   enable
+                          trn_rrem_prev, // bit 3-2: encoded eof loc from block
+                          2'b11};        // bit 1-0: hardwired 1
+  end
+  else if(C_DATA_WIDTH == 64) begin : is_eof_64
+    assign is_eof      = {trn_reof,      // bit 4:   enable
+                          1'b0,          // bit 3:   hardwired 0
+                          trn_rrem,      // bit 2:   encoded eof loc from block
+                          2'b11};        // bit 1-0: hardwired 1
+
+    assign is_eof_prev = {trn_reof_prev, // bit 4:   enable
+                          1'b0,          // bit 3:   hardwired 0
+                          trn_rrem_prev, // bit 2:   encoded eof loc from block
+                          2'b11};        // bit 1-0: hardwired 1
+  end
+  else begin : is_eof_32
+    assign is_eof      = {trn_reof,      // bit 4:   enable
+                          4'b0011};      // bit 3-0: hardwired to byte 3
+
+    assign is_eof_prev = {trn_reof_prev, // bit 4:   enable
+                          4'b0011};      // bit 3-0: hardwired to byte 3
+  end
+endgenerate
+
+
+
+//----------------------------------------------------------------------------//
+// Create trn_rdst_rdy                                                        //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    trn_rdst_rdy <= #TCQ 1'b0;
+  end
+  else begin
+    // If in a null packet, use null generated value
+    if(null_mux_sel && m_axis_rx_tready) begin
+      trn_rdst_rdy <= #TCQ null_rdst_rdy;
+    end
+
+    // If a discontinue needs to be serviced, throttle the block until we are
+    // ready to pad out the packet.
+    else if(dsc_flag) begin
+      trn_rdst_rdy <= #TCQ 1'b0;
+    end
+
+    // If in a packet, pass user back-pressure directly to block
+    else if(m_axis_rx_tvalid) begin
+      trn_rdst_rdy <= #TCQ m_axis_rx_tready;
+    end
+
+    // If idle, default to no back-pressure. We need to default to the
+    // "ready to accept data" state to make sure we catch the first
+    // clock of data of a new packet.
+    else begin
+      trn_rdst_rdy <= #TCQ 1'b1;
+    end
+  end
+end
+
+//----------------------------------------------------------------------------//
+// Create null_mux_sel                                                        //
+// null_mux_sel is the signal used to detect a discontinue situation and      //
+// mux in the null packet generated in rx_null_gen. Only mux in null data     //
+// when not at the beginningof a packet. SOF discontinues do not require      //
+// padding, as the whole packet is simply squashed instead.                   //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    null_mux_sel <= #TCQ 1'b0;
+  end
+  else begin
+    // NULL packet done
+    if(null_mux_sel && null_rx_tlast && m_axis_rx_tready)
+    begin
+      null_mux_sel <= #TCQ 1'b0;
+    end
+
+    // Discontinue detected and we're in packet, so switch to NULL packet
+    else if(dsc_flag && !data_hold) begin
+      null_mux_sel <= #TCQ 1'b1;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create discontinue tracking signals                                        //
+//----------------------------------------------------------------------------//
+// Create signal trn_in_packet, which is needed to validate trn_rsrc_dsc. We
+// should ignore trn_rsrc_dsc when it's asserted out-of-packet.
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    trn_in_packet <= #TCQ 1'b0;
+  end
+  else begin
+    if(trn_rsof && !trn_reof && rsrc_rdy_filtered && trn_rdst_rdy)
+    begin
+      trn_in_packet <= #TCQ 1'b1;
+    end
+    else if(trn_rsrc_dsc) begin
+      trn_in_packet <= #TCQ 1'b0;
+    end
+    else if(trn_reof && !trn_rsof && trn_rsrc_rdy && trn_rdst_rdy) begin
+      trn_in_packet <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+// Create dsc_flag, which identifies and stores mid-packet discontinues that
+// require null packet padding. This signal is edge sensitive to trn_rsrc_dsc,
+// to make sure we don't service the same dsc twice in the event that
+// trn_rsrc_dsc stays asserted for longer than it takes to pad out the packet.
+assign dsc_detect = trn_rsrc_dsc && !trn_rsrc_dsc_d && trn_in_packet &&
+                         (!trn_rsof || trn_reof) && !(trn_rdst_rdy && trn_reof);
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    reg_dsc_detect <= #TCQ 1'b0;
+    trn_rsrc_dsc_d <= #TCQ 1'b0;
+  end
+  else begin
+    if(dsc_detect) begin
+      reg_dsc_detect <= #TCQ 1'b1;
+    end
+    else if(null_mux_sel) begin
+      reg_dsc_detect <= #TCQ 1'b0;
+    end
+
+    trn_rsrc_dsc_d <= #TCQ trn_rsrc_dsc;
+  end
+end
+
+assign dsc_flag = dsc_detect || reg_dsc_detect;
+
+
+
+//----------------------------------------------------------------------------//
+// Create np_counter (V6 128-bit only). This counter tells the V6 128-bit     //
+// interface core how many NP packets have left the RX pipeline. The V6       //
+// 128-bit interface uses this count to perform rnp_ok modulation.            //
+//----------------------------------------------------------------------------//
+generate
+  if(C_FAMILY == "V6" && C_DATA_WIDTH == 128) begin : np_cntr_to_128_enabled
+    reg [2:0] reg_np_counter;
+
+    // Look for NP packets beginning on lower (i.e. unaligned) start
+    wire mrd_lower      = (!(|m_axis_rx_tdata[92:88]) && !m_axis_rx_tdata[94]);
+    wire mrd_lk_lower   = (m_axis_rx_tdata[92:88] == 5'b00001);
+    wire io_rdwr_lower  = (m_axis_rx_tdata[92:88] == 5'b00010);
+    wire cfg_rdwr_lower = (m_axis_rx_tdata[92:89] == 4'b0010);
+    wire atomic_lower   = ((&m_axis_rx_tdata[91:90]) && m_axis_rx_tdata[94]);
+
+    wire np_pkt_lower = (mrd_lower      ||
+                         mrd_lk_lower   ||
+                         io_rdwr_lower  ||
+                         cfg_rdwr_lower ||
+                         atomic_lower) && m_axis_rx_tuser[13];
+
+    // Look for NP packets beginning on upper (i.e. aligned) start
+    wire mrd_upper      = (!(|m_axis_rx_tdata[28:24]) && !m_axis_rx_tdata[30]);
+    wire mrd_lk_upper   = (m_axis_rx_tdata[28:24] == 5'b00001);
+    wire io_rdwr_upper  = (m_axis_rx_tdata[28:24] == 5'b00010);
+    wire cfg_rdwr_upper = (m_axis_rx_tdata[28:25] == 4'b0010);
+    wire atomic_upper   = ((&m_axis_rx_tdata[27:26]) && m_axis_rx_tdata[30]);
+
+    wire np_pkt_upper = (mrd_upper      ||
+                         mrd_lk_upper   ||
+                         io_rdwr_upper  ||
+                         cfg_rdwr_upper ||
+                         atomic_upper) && !m_axis_rx_tuser[13];
+
+    wire pkt_accepted =
+                    m_axis_rx_tuser[14] && m_axis_rx_tready && m_axis_rx_tvalid;
+
+    // Increment counter whenever an NP packet leaves the RX pipeline
+    always @(posedge user_clk)  begin
+      if (user_rst) begin
+        reg_np_counter <= #TCQ 0;
+      end
+      else begin
+        if((np_pkt_lower || np_pkt_upper) && pkt_accepted)
+        begin
+          reg_np_counter <= #TCQ reg_np_counter + 3'h1;
+        end
+      end
+    end
+
+    assign np_counter = reg_np_counter;
+  end
+  else begin : np_cntr_to_128_disabled
+    assign np_counter = 3'h0;
+  end
+endgenerate
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_axi_basic_top.v

@@ -0,0 +1,282 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_axi_basic_top.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules.       //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_axi_basic_top #(
+  parameter C_DATA_WIDTH  = 128,          // RX/TX interface data width
+  parameter C_FAMILY      = "X7",         // Targeted FPGA family
+  parameter C_ROOT_PORT   = "FALSE",      // PCIe block is in root port mode
+  parameter C_PM_PRIORITY = "FALSE",      // Disable TX packet boundary thrtl
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter REM_WIDTH  = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8               // KEEP width
+  ) (
+  //---------------------------------------------//
+  // User Design I/O                             //
+  //---------------------------------------------//
+
+  // AXI TX
+  //-----------
+  input   [C_DATA_WIDTH-1:0] s_axis_tx_tdata,        // TX data from user
+  input                      s_axis_tx_tvalid,       // TX data is valid
+  output                     s_axis_tx_tready,       // TX ready for data
+  input     [KEEP_WIDTH-1:0] s_axis_tx_tkeep,        // TX strobe byte enables
+  input                      s_axis_tx_tlast,        // TX data is last
+  input                [3:0] s_axis_tx_tuser,        // TX user signals
+
+  // AXI RX
+  //-----------
+  output  [C_DATA_WIDTH-1:0] m_axis_rx_tdata,        // RX data to user
+  output                     m_axis_rx_tvalid,       // RX data is valid
+  input                      m_axis_rx_tready,       // RX ready for data
+  output    [KEEP_WIDTH-1:0] m_axis_rx_tkeep,        // RX strobe byte enables
+  output                     m_axis_rx_tlast,        // RX data is last
+  output              [21:0] m_axis_rx_tuser,        // RX user signals
+
+  // User Misc.
+  //-----------
+  input                      user_turnoff_ok,        // Turnoff OK from user
+  input                      user_tcfg_gnt,          // Send cfg OK from user
+
+  //---------------------------------------------//
+  // PCIe Block I/O                              //
+  //---------------------------------------------//
+
+  // TRN TX
+  //-----------
+  output [C_DATA_WIDTH-1:0] trn_td,                  // TX data from block
+  output                    trn_tsof,                // TX start of packet
+  output                    trn_teof,                // TX end of packet
+  output                    trn_tsrc_rdy,            // TX source ready
+  input                     trn_tdst_rdy,            // TX destination ready
+  output                    trn_tsrc_dsc,            // TX source discontinue
+  output    [REM_WIDTH-1:0] trn_trem,                // TX remainder
+  output                    trn_terrfwd,             // TX error forward
+  output                    trn_tstr,                // TX streaming enable
+  input               [5:0] trn_tbuf_av,             // TX buffers available
+  output                    trn_tecrc_gen,           // TX ECRC generate
+
+  // TRN RX
+  //-----------
+  input  [127:0] trn_rd,                  // RX data from block
+  input                     trn_rsof,                // RX start of packet
+  input                     trn_reof,                // RX end of packet
+  input                     trn_rsrc_rdy,            // RX source ready
+  output                    trn_rdst_rdy,            // RX destination ready
+  input                     trn_rsrc_dsc,            // RX source discontinue
+  input     [1:0] trn_rrem,                // RX remainder
+  input                     trn_rerrfwd,             // RX error forward
+  input               [6:0] trn_rbar_hit,            // RX BAR hit
+  input                     trn_recrc_err,           // RX ECRC error
+
+  // TRN Misc.
+  //-----------
+  input                     trn_tcfg_req,            // TX config request
+  output                    trn_tcfg_gnt,            // RX config grant
+  input                     trn_lnk_up,              // PCIe link up
+
+  // 7 Series/Virtex6 PM
+  //-----------
+  input               [2:0] cfg_pcie_link_state,     // Encoded PCIe link state
+
+  // Virtex6 PM
+  //-----------
+  input                     cfg_pm_send_pme_to,      // PM send PME turnoff msg
+  input               [1:0] cfg_pmcsr_powerstate,    // PMCSR power state
+  input              [31:0] trn_rdllp_data,          // RX DLLP data
+  input                     trn_rdllp_src_rdy,       // RX DLLP source ready
+
+  // Virtex6/Spartan6 PM
+  //-----------
+  input                     cfg_to_turnoff,          // Turnoff request
+  output                    cfg_turnoff_ok,          // Turnoff grant
+
+  // System
+  //-----------
+  output              [2:0] np_counter,              // Non-posted counter
+  input                     user_clk,                // user clock from block
+  input                     user_rst                 // user reset from block
+);
+
+
+//---------------------------------------------//
+// RX Data Pipeline                            //
+//---------------------------------------------//
+
+xdma_0_pcie2_ip_axi_basic_rx #(
+  .C_DATA_WIDTH( C_DATA_WIDTH ),
+  .C_FAMILY( C_FAMILY ),
+
+  .TCQ( TCQ ),
+  .REM_WIDTH( REM_WIDTH ),
+  .KEEP_WIDTH( KEEP_WIDTH )
+) rx_inst (
+
+  // Outgoing AXI TX
+  //-----------
+  .m_axis_rx_tdata( m_axis_rx_tdata ),
+  .m_axis_rx_tvalid( m_axis_rx_tvalid ),
+  .m_axis_rx_tready( m_axis_rx_tready ),
+  .m_axis_rx_tkeep( m_axis_rx_tkeep ),
+  .m_axis_rx_tlast( m_axis_rx_tlast ),
+  .m_axis_rx_tuser( m_axis_rx_tuser ),
+
+  // Incoming TRN RX
+  //-----------
+  .trn_rd( trn_rd[C_DATA_WIDTH-1:0] ),
+  .trn_rsof( trn_rsof ),
+  .trn_reof( trn_reof ),
+  .trn_rsrc_rdy( trn_rsrc_rdy ),
+  .trn_rdst_rdy( trn_rdst_rdy ),
+  .trn_rsrc_dsc( trn_rsrc_dsc ),
+  .trn_rrem( trn_rrem[REM_WIDTH-1:0] ),
+  .trn_rerrfwd( trn_rerrfwd ),
+  .trn_rbar_hit( trn_rbar_hit ),
+  .trn_recrc_err( trn_recrc_err ),
+
+  // System
+  //-----------
+  .np_counter( np_counter ),
+  .user_clk( user_clk ),
+  .user_rst( user_rst )
+);
+
+
+
+//---------------------------------------------//
+// TX Data Pipeline                            //
+//---------------------------------------------//
+
+xdma_0_pcie2_ip_axi_basic_tx #(
+  .C_DATA_WIDTH( C_DATA_WIDTH ),
+  .C_FAMILY( C_FAMILY ),
+  .C_ROOT_PORT( C_ROOT_PORT ),
+  .C_PM_PRIORITY( C_PM_PRIORITY ),
+
+  .TCQ( TCQ ),
+  .REM_WIDTH( REM_WIDTH ),
+  .KEEP_WIDTH( KEEP_WIDTH )
+) tx_inst (
+
+  // Incoming AXI RX
+  //-----------
+  .s_axis_tx_tdata( s_axis_tx_tdata ),
+  .s_axis_tx_tvalid( s_axis_tx_tvalid ),
+  .s_axis_tx_tready( s_axis_tx_tready ),
+  .s_axis_tx_tkeep( s_axis_tx_tkeep ),
+  .s_axis_tx_tlast( s_axis_tx_tlast ),
+  .s_axis_tx_tuser( s_axis_tx_tuser ),
+
+  // User Misc.
+  //-----------
+  .user_turnoff_ok( user_turnoff_ok ),
+  .user_tcfg_gnt( user_tcfg_gnt ),
+
+  // Outgoing TRN TX
+  //-----------
+  .trn_td( trn_td ),
+  .trn_tsof( trn_tsof ),
+  .trn_teof( trn_teof ),
+  .trn_tsrc_rdy( trn_tsrc_rdy ),
+  .trn_tdst_rdy( trn_tdst_rdy ),
+  .trn_tsrc_dsc( trn_tsrc_dsc ),
+  .trn_trem( trn_trem ),
+  .trn_terrfwd( trn_terrfwd ),
+  .trn_tstr( trn_tstr ),
+  .trn_tbuf_av( trn_tbuf_av ),
+  .trn_tecrc_gen( trn_tecrc_gen ),
+
+  // TRN Misc.
+  //-----------
+  .trn_tcfg_req( trn_tcfg_req ),
+  .trn_tcfg_gnt( trn_tcfg_gnt ),
+  .trn_lnk_up( trn_lnk_up ),
+
+  // 7 Series/Virtex6 PM
+  //-----------
+  .cfg_pcie_link_state( cfg_pcie_link_state ),
+
+  // Virtex6 PM
+  //-----------
+  .cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
+  .cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
+  .trn_rdllp_data( trn_rdllp_data ),
+  .trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
+
+  // Spartan6 PM
+  //-----------
+  .cfg_to_turnoff( cfg_to_turnoff ),
+  .cfg_turnoff_ok( cfg_turnoff_ok ),
+
+  // System
+  //-----------
+  .user_clk( user_clk ),
+  .user_rst( user_rst )
+);
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_axi_basic_tx.v

@@ -0,0 +1,260 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_axi_basic_tx.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  AXI to TRN TX module. Instantiates pipeline and throttle control TX       //
+//  submodules.                                                               //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_tx                                                          //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_axi_basic_tx #(
+  parameter C_DATA_WIDTH  = 128,          // RX/TX interface data width
+  parameter C_FAMILY      = "X7",         // Targeted FPGA family
+  parameter C_ROOT_PORT   = "FALSE",      // PCIe block is in root port mode
+  parameter C_PM_PRIORITY = "FALSE",      // Disable TX packet boundary thrtl
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter REM_WIDTH  = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8               // KEEP width
+  ) (
+  //---------------------------------------------//
+  // User Design I/O                             //
+  //---------------------------------------------//
+
+  // AXI TX
+  //-----------
+  input   [C_DATA_WIDTH-1:0] s_axis_tx_tdata,        // TX data from user
+  input                      s_axis_tx_tvalid,       // TX data is valid
+  output                     s_axis_tx_tready,       // TX ready for data
+  input     [KEEP_WIDTH-1:0] s_axis_tx_tkeep,        // TX strobe byte enables
+  input                      s_axis_tx_tlast,        // TX data is last
+  input                [3:0] s_axis_tx_tuser,        // TX user signals
+
+  // User Misc.
+  //-----------
+  input                      user_turnoff_ok,        // Turnoff OK from user
+  input                      user_tcfg_gnt,          // Send cfg OK from user
+
+  //---------------------------------------------//
+  // PCIe Block I/O                              //
+  //---------------------------------------------//
+
+  // TRN TX
+  //-----------
+  output [C_DATA_WIDTH-1:0] trn_td,                  // TX data from block
+  output                    trn_tsof,                // TX start of packet
+  output                    trn_teof,                // TX end of packet
+  output                    trn_tsrc_rdy,            // TX source ready
+  input                     trn_tdst_rdy,            // TX destination ready
+  output                    trn_tsrc_dsc,            // TX source discontinue
+  output    [REM_WIDTH-1:0] trn_trem,                // TX remainder
+  output                    trn_terrfwd,             // TX error forward
+  output                    trn_tstr,                // TX streaming enable
+  input               [5:0] trn_tbuf_av,             // TX buffers available
+  output                    trn_tecrc_gen,           // TX ECRC generate
+
+  // TRN Misc.
+  //-----------
+  input                     trn_tcfg_req,            // TX config request
+  output                    trn_tcfg_gnt,            // RX config grant
+  input                     trn_lnk_up,              // PCIe link up
+
+  // 7 Series/Virtex6 PM
+  //-----------
+  input               [2:0] cfg_pcie_link_state,     // Encoded PCIe link state
+
+  // Virtex6 PM
+  //-----------
+  input                     cfg_pm_send_pme_to,      // PM send PME turnoff msg
+  input               [1:0] cfg_pmcsr_powerstate,    // PMCSR power state
+  input              [31:0] trn_rdllp_data,          // RX DLLP data
+  input                     trn_rdllp_src_rdy,       // RX DLLP source ready
+
+  // Virtex6/Spartan6 PM
+  //-----------
+  input                     cfg_to_turnoff,          // Turnoff request
+  output                    cfg_turnoff_ok,          // Turnoff grant
+
+  // System
+  //-----------
+  input                     user_clk,                // user clock from block
+  input                     user_rst                 // user reset from block
+);
+
+
+wire tready_thrtl;
+
+//---------------------------------------------//
+// TX Data Pipeline                            //
+//---------------------------------------------//
+
+xdma_0_pcie2_ip_axi_basic_tx_pipeline #(
+  .C_DATA_WIDTH( C_DATA_WIDTH ),
+  .C_PM_PRIORITY( C_PM_PRIORITY ),
+  .TCQ( TCQ ),
+
+  .REM_WIDTH( REM_WIDTH ),
+  .KEEP_WIDTH( KEEP_WIDTH )
+) tx_pipeline_inst (
+
+  // Incoming AXI RX
+  //-----------
+  .s_axis_tx_tdata( s_axis_tx_tdata ),
+  .s_axis_tx_tready( s_axis_tx_tready ),
+  .s_axis_tx_tvalid( s_axis_tx_tvalid ),
+  .s_axis_tx_tkeep( s_axis_tx_tkeep ),
+  .s_axis_tx_tlast( s_axis_tx_tlast ),
+  .s_axis_tx_tuser( s_axis_tx_tuser ),
+
+  // Outgoing TRN TX
+  //-----------
+  .trn_td( trn_td ),
+  .trn_tsof( trn_tsof ),
+  .trn_teof( trn_teof ),
+  .trn_tsrc_rdy( trn_tsrc_rdy ),
+  .trn_tdst_rdy( trn_tdst_rdy ),
+  .trn_tsrc_dsc( trn_tsrc_dsc ),
+  .trn_trem( trn_trem ),
+  .trn_terrfwd( trn_terrfwd ),
+  .trn_tstr( trn_tstr ),
+  .trn_tecrc_gen( trn_tecrc_gen ),
+  .trn_lnk_up( trn_lnk_up ),
+
+  // System
+  //-----------
+  .tready_thrtl( tready_thrtl ),
+  .user_clk( user_clk ),
+  .user_rst( user_rst )
+);
+
+
+//---------------------------------------------//
+// TX Throttle Controller                      //
+//---------------------------------------------//
+
+generate
+  if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
+xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl #(
+      .C_DATA_WIDTH( C_DATA_WIDTH ),
+      .C_FAMILY( C_FAMILY ),
+      .C_ROOT_PORT( C_ROOT_PORT ),
+      .TCQ( TCQ )
+
+    ) tx_thrl_ctl_inst (
+
+      // Outgoing AXI TX
+      //-----------
+      .s_axis_tx_tdata( s_axis_tx_tdata ),
+      .s_axis_tx_tvalid( s_axis_tx_tvalid ),
+      .s_axis_tx_tuser( s_axis_tx_tuser ),
+      .s_axis_tx_tlast( s_axis_tx_tlast ),
+
+      // User Misc.
+      //-----------
+      .user_turnoff_ok( user_turnoff_ok ),
+      .user_tcfg_gnt( user_tcfg_gnt ),
+
+      // Incoming TRN RX
+      //-----------
+      .trn_tbuf_av( trn_tbuf_av ),
+      .trn_tdst_rdy( trn_tdst_rdy ),
+
+      // TRN Misc.
+      //-----------
+      .trn_tcfg_req( trn_tcfg_req ),
+      .trn_tcfg_gnt( trn_tcfg_gnt ),
+      .trn_lnk_up( trn_lnk_up ),
+
+      // 7 Seriesq/Virtex6 PM
+      //-----------
+      .cfg_pcie_link_state( cfg_pcie_link_state ),
+
+      // Virtex6 PM
+      //-----------
+      .cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
+      .cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
+      .trn_rdllp_data( trn_rdllp_data ),
+      .trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
+
+      // Spartan6 PM
+      //-----------
+      .cfg_to_turnoff( cfg_to_turnoff ),
+      .cfg_turnoff_ok( cfg_turnoff_ok ),
+
+      // System
+      //-----------
+      .tready_thrtl( tready_thrtl ),
+      .user_clk( user_clk ),
+      .user_rst( user_rst )
+    );
+  end
+  else begin : thrtl_ctl_disabled
+    assign tready_thrtl   = 1'b0;
+
+    assign cfg_turnoff_ok = user_turnoff_ok;
+    assign trn_tcfg_gnt   = user_tcfg_gnt;
+  end
+endgenerate
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_axi_basic_tx_pipeline.v

@@ -0,0 +1,543 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_axi_basic_tx_pipeline.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  AXI to TRN TX pipeline. Converts transmitted data from AXI protocol to    //
+//  TRN.                                                                      //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_tx                                                          //
+//        axi_basic_tx_pipeline                                               //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_axi_basic_tx_pipeline #(
+  parameter C_DATA_WIDTH = 128,           // RX/TX interface data width
+  parameter C_PM_PRIORITY = "FALSE",      // Disable TX packet boundary thrtl
+  parameter TCQ = 1,                      // Clock to Q time
+
+  // Do not override parameters below this line
+  parameter REM_WIDTH  = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8               // KEEP width
+  ) (
+  //---------------------------------------------//
+  // User Design I/O                             //
+  //---------------------------------------------//
+
+  // AXI TX
+  //-----------
+  input      [C_DATA_WIDTH-1:0] s_axis_tx_tdata,     // TX data from user
+  input                         s_axis_tx_tvalid,    // TX data is valid
+  output                        s_axis_tx_tready,    // TX ready for data
+  input        [KEEP_WIDTH-1:0] s_axis_tx_tkeep,     // TX strobe byte enables
+  input                         s_axis_tx_tlast,     // TX data is last
+  input                   [3:0] s_axis_tx_tuser,     // TX user signals
+
+  //---------------------------------------------//
+  // PCIe Block I/O                              //
+  //---------------------------------------------//
+
+  // TRN TX
+  //-----------
+  output     [C_DATA_WIDTH-1:0] trn_td,              // TX data from block
+  output                        trn_tsof,            // TX start of packet
+  output                        trn_teof,            // TX end of packet
+  output                        trn_tsrc_rdy,        // TX source ready
+  input                         trn_tdst_rdy,        // TX destination ready
+  output                        trn_tsrc_dsc,        // TX source discontinue
+  output        [REM_WIDTH-1:0] trn_trem,            // TX remainder
+  output                        trn_terrfwd,         // TX error forward
+  output                        trn_tstr,            // TX streaming enable
+  output                        trn_tecrc_gen,       // TX ECRC generate
+  input                         trn_lnk_up,          // PCIe link up
+
+  // System
+  //-----------
+  input                         tready_thrtl,        // TREADY from thrtl ctl
+  input                         user_clk,            // user clock from block
+  input                         user_rst             // user reset from block
+);
+
+
+// Input register stage
+reg  [C_DATA_WIDTH-1:0] reg_tdata;
+reg                     reg_tvalid;
+reg    [KEEP_WIDTH-1:0] reg_tkeep;
+reg               [3:0] reg_tuser;
+reg                     reg_tlast;
+reg                     reg_tready;
+
+// Pipeline utility signals
+reg                     trn_in_packet;
+reg                     axi_in_packet;
+reg                     flush_axi;
+wire                    disable_trn;
+reg                     reg_disable_trn;
+
+wire                    axi_beat_live  = s_axis_tx_tvalid && s_axis_tx_tready;
+wire                    axi_end_packet = axi_beat_live && s_axis_tx_tlast;
+
+
+//----------------------------------------------------------------------------//
+// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN. //
+// 128-bit:                 64-bit:                  32-bit:                  //
+// TRN DW0 maps to AXI DW3  TRN DW0 maps to AXI DW1  TNR DW0 maps to AXI DW0  //
+// TRN DW1 maps to AXI DW2  TRN DW1 maps to AXI DW0                           //
+// TRN DW2 maps to AXI DW1                                                    //
+// TRN DW3 maps to AXI DW0                                                    //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : td_DW_swap_128
+    assign trn_td = {reg_tdata[31:0],
+                     reg_tdata[63:32],
+                     reg_tdata[95:64],
+                     reg_tdata[127:96]};
+  end
+  else if(C_DATA_WIDTH == 64) begin : td_DW_swap_64
+    assign trn_td = {reg_tdata[31:0], reg_tdata[63:32]};
+  end
+  else begin : td_DW_swap_32
+    assign trn_td = reg_tdata;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Create trn_tsof. If we're not currently in a packet and TVALID goes high,  //
+// assert TSOF.                                                               //
+//----------------------------------------------------------------------------//
+assign trn_tsof = reg_tvalid && !trn_in_packet;
+
+
+//----------------------------------------------------------------------------//
+// Create trn_in_packet. This signal tracks if the TRN interface is currently //
+// in the middle of a packet, which is needed to generate trn_tsof            //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    trn_in_packet <= #TCQ 1'b0;
+  end
+  else begin
+    if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof) begin
+      trn_in_packet <= #TCQ 1'b1;
+    end
+    else if((trn_in_packet && trn_teof && trn_tsrc_rdy) || !trn_lnk_up) begin
+      trn_in_packet <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create axi_in_packet. This signal tracks if the AXI interface is currently //
+// in the middle of a packet, which is needed in case the link goes down.     //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    axi_in_packet <= #TCQ 1'b0;
+  end
+  else begin
+    if(axi_beat_live && !s_axis_tx_tlast) begin
+      axi_in_packet <= #TCQ 1'b1;
+    end
+    else if(axi_beat_live) begin
+      axi_in_packet <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create disable_trn. This signal asserts when the link goes down and        //
+// triggers the deassertiong of trn_tsrc_rdy. The deassertion of disable_trn  //
+// depends on C_PM_PRIORITY, as described below.                              //
+//----------------------------------------------------------------------------//
+generate
+  // In the C_PM_PRIORITY pipeline, we disable the TRN interfacefrom the time
+  // the link goes down until the the AXI interface is ready to accept packets
+  // again (via assertion of TREADY). By waiting for TREADY, we allow the
+  // previous value buffer to fill, so we're ready for any throttling by the
+  // user or the block.
+  if(C_PM_PRIORITY == "TRUE") begin : pm_priority_trn_flush
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_disable_trn    <= #TCQ 1'b1;
+      end
+      else begin
+        // When the link goes down, disable the TRN interface.
+        if(!trn_lnk_up)
+        begin
+          reg_disable_trn  <= #TCQ 1'b1;
+        end
+
+        // When the link comes back up and the AXI interface is ready, we can
+        // release the pipeline and return to normal operation.
+        else if(!flush_axi && s_axis_tx_tready) begin
+          reg_disable_trn <= #TCQ 1'b0;
+        end
+      end
+    end
+
+    assign disable_trn = reg_disable_trn;
+  end
+
+  // In the throttle-controlled pipeline, we don't have a previous value buffer.
+  // The throttle control mechanism handles TREADY, so all we need to do is
+  // detect when the link goes down and disable the TRN interface until the link
+  // comes back up and the AXI interface is finished flushing any packets.
+  else begin : thrtl_ctl_trn_flush
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_disable_trn    <= #TCQ 1'b0;
+      end
+      else begin
+        // If the link is down and AXI is in packet, disable TRN and look for
+        // the end of the packet
+        if(axi_in_packet && !trn_lnk_up && !axi_end_packet)
+        begin
+          reg_disable_trn  <= #TCQ 1'b1;
+        end
+
+        // AXI packet is ending, so we're done flushing
+        else if(axi_end_packet) begin
+          reg_disable_trn <= #TCQ 1'b0;
+        end
+      end
+    end
+
+    // Disable the TRN interface if link is down or we're still flushing the AXI
+    // interface.
+    assign disable_trn = reg_disable_trn || !trn_lnk_up;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Convert STRB to RREM. Here, we are converting the encoding method for the  //
+// location of the EOF from AXI (tkeep) to TRN flavor (rrem).                 //
+//----------------------------------------------------------------------------//
+generate
+  if(C_DATA_WIDTH == 128) begin : tkeep_to_trem_128
+    //---------------------------------------//
+    // Conversion table:                     //
+    // trem    | tkeep                       //
+    // [1] [0] | [15:12] [11:8] [7:4] [3:0]  //
+    // ------------------------------------- //
+    //  1   1  |   D3      D2    D1    D0    //
+    //  1   0  |   --      D2    D1    D0    //
+    //  0   1  |   --      --    D1    D0    //
+    //  0   0  |   --      --    --    D0    //
+    //---------------------------------------//
+
+    wire   axi_DW_1    = reg_tkeep[7];
+    wire   axi_DW_2    = reg_tkeep[11];
+    wire   axi_DW_3    = reg_tkeep[15];
+    assign trn_trem[1] = axi_DW_2;
+    assign trn_trem[0] = axi_DW_3 || (axi_DW_1 && !axi_DW_2);
+  end
+  else if(C_DATA_WIDTH == 64) begin : tkeep_to_trem_64
+    assign trn_trem    = reg_tkeep[7];
+  end
+  else begin : tkeep_to_trem_32
+    assign trn_trem    = 1'b0;
+  end
+endgenerate
+
+
+//----------------------------------------------------------------------------//
+// Create remaining TRN signals                                               //
+//----------------------------------------------------------------------------//
+assign trn_teof      = reg_tlast;
+assign trn_tecrc_gen = reg_tuser[0];
+assign trn_terrfwd   = reg_tuser[1];
+assign trn_tstr      = reg_tuser[2];
+assign trn_tsrc_dsc  = reg_tuser[3];
+
+
+//----------------------------------------------------------------------------//
+// Pipeline stage                                                             //
+//----------------------------------------------------------------------------//
+// We need one of two approaches for the pipeline stage depending on the
+// C_PM_PRIORITY parameter.
+generate
+  reg reg_tsrc_rdy;
+
+  // If set to FALSE, that means the user wants to use the TX packet boundary
+  // throttling feature. Since all Block throttling will now be predicted, we
+  // can use a simple straight-through pipeline.
+  if(C_PM_PRIORITY == "FALSE") begin : throttle_ctl_pipeline
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_tdata        <= #TCQ {C_DATA_WIDTH{1'b0}};
+        reg_tvalid       <= #TCQ 1'b0;
+        reg_tkeep        <= #TCQ {KEEP_WIDTH{1'b0}};
+        reg_tlast        <= #TCQ 1'b0;
+        reg_tuser        <= #TCQ 4'h0;
+        reg_tsrc_rdy     <= #TCQ 1'b0;
+      end
+      else begin
+        reg_tdata        <= #TCQ s_axis_tx_tdata;
+        reg_tvalid       <= #TCQ s_axis_tx_tvalid;
+        reg_tkeep        <= #TCQ s_axis_tx_tkeep;
+        reg_tlast        <= #TCQ s_axis_tx_tlast;
+        reg_tuser        <= #TCQ s_axis_tx_tuser;
+
+        // Hold trn_tsrc_rdy low when flushing a packet.
+        reg_tsrc_rdy     <= #TCQ axi_beat_live && !disable_trn;
+      end
+    end
+
+    assign trn_tsrc_rdy = reg_tsrc_rdy;
+
+    // With TX packet boundary throttling, TREADY is pipelined in
+    // axi_basic_tx_thrtl_ctl and wired through here.
+    assign s_axis_tx_tready = tready_thrtl;
+  end
+
+  //**************************************************************************//
+
+  // If C_PM_PRIORITY is set to TRUE, that means the user prefers to have all PM
+  // functionality intact isntead of TX packet boundary throttling. Now the
+  // Block could back-pressure at any time, which creates the standard problem
+  // of potential data loss due to the handshaking latency. Here we need a
+  // previous value buffer, just like the RX data path.
+  else begin : pm_prioity_pipeline
+    reg  [C_DATA_WIDTH-1:0] tdata_prev;
+    reg                     tvalid_prev;
+    reg    [KEEP_WIDTH-1:0] tkeep_prev;
+    reg                     tlast_prev;
+    reg               [3:0] tuser_prev;
+    reg                     reg_tdst_rdy;
+
+    wire                    data_hold;
+    reg                     data_prev;
+
+
+    //------------------------------------------------------------------------//
+    // Previous value buffer                                                  //
+    // ---------------------                                                  //
+    // We are inserting a pipeline stage in between AXI and TRN, which causes //
+    // some issues with handshaking signals trn_tsrc_rdy/s_axis_tx_tready.    //
+    // The added cycle of latency in the path causes the Block to fall behind //
+    // the AXI interface whenever it throttles.                               //
+    //                                                                        //
+    // To avoid loss of data, we must keep the previous value of all          //
+    // s_axis_tx_* signals in case the Block throttles.                       //
+    //------------------------------------------------------------------------//
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        tdata_prev   <= #TCQ {C_DATA_WIDTH{1'b0}};
+        tvalid_prev  <= #TCQ 1'b0;
+        tkeep_prev   <= #TCQ {KEEP_WIDTH{1'b0}};
+        tlast_prev   <= #TCQ 1'b0;
+        tuser_prev   <= #TCQ 4'h 0;
+      end
+      else begin
+        // prev buffer works by checking s_axis_tx_tready. When
+        // s_axis_tx_tready is asserted, a new value is present on the
+        // interface.
+        if(!s_axis_tx_tready) begin
+          tdata_prev   <= #TCQ tdata_prev;
+          tvalid_prev  <= #TCQ tvalid_prev;
+          tkeep_prev   <= #TCQ tkeep_prev;
+          tlast_prev   <= #TCQ tlast_prev;
+          tuser_prev   <= #TCQ tuser_prev;
+        end
+        else begin
+          tdata_prev   <= #TCQ s_axis_tx_tdata;
+          tvalid_prev  <= #TCQ s_axis_tx_tvalid;
+          tkeep_prev   <= #TCQ s_axis_tx_tkeep;
+          tlast_prev   <= #TCQ s_axis_tx_tlast;
+          tuser_prev   <= #TCQ s_axis_tx_tuser;
+        end
+      end
+    end
+
+    // Create special buffer which locks in the proper value of TDATA depending
+    // on whether the user is throttling or not. This buffer has three states:
+    //
+    //       HOLD state: TDATA maintains its current value
+    //                   - the Block has throttled the PCIe block
+    //   PREVIOUS state: the buffer provides the previous value on TDATA
+    //                   - the Block has finished throttling, and is a little
+    //                     behind the user
+    //    CURRENT state: the buffer passes the current value on TDATA
+    //                   - the Block is caught up and ready to receive the
+    //                     latest data from the user
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_tdata  <= #TCQ {C_DATA_WIDTH{1'b0}};
+        reg_tvalid <= #TCQ 1'b0;
+        reg_tkeep  <= #TCQ {KEEP_WIDTH{1'b0}};
+        reg_tlast  <= #TCQ 1'b0;
+        reg_tuser  <= #TCQ 4'h0;
+
+        reg_tdst_rdy <= #TCQ 1'b0;
+      end
+      else begin
+        reg_tdst_rdy <= #TCQ trn_tdst_rdy;
+
+        if(!data_hold) begin
+          // PREVIOUS state
+          if(data_prev) begin
+            reg_tdata  <= #TCQ tdata_prev;
+            reg_tvalid <= #TCQ tvalid_prev;
+            reg_tkeep  <= #TCQ tkeep_prev;
+            reg_tlast  <= #TCQ tlast_prev;
+            reg_tuser  <= #TCQ tuser_prev;
+          end
+
+          // CURRENT state
+          else begin
+            reg_tdata  <= #TCQ s_axis_tx_tdata;
+            reg_tvalid <= #TCQ s_axis_tx_tvalid;
+            reg_tkeep  <= #TCQ s_axis_tx_tkeep;
+            reg_tlast  <= #TCQ s_axis_tx_tlast;
+            reg_tuser  <= #TCQ s_axis_tx_tuser;
+          end
+        end
+        // else HOLD state
+      end
+    end
+
+
+    // Logic to instruct pipeline to hold its value
+    assign data_hold = trn_tsrc_rdy && !trn_tdst_rdy;
+
+
+    // Logic to instruct pipeline to use previous bus values. Always use
+    // previous value after holding a value.
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        data_prev <= #TCQ 1'b0;
+      end
+      else begin
+        data_prev <= #TCQ data_hold;
+      end
+    end
+
+
+    //------------------------------------------------------------------------//
+    // Create trn_tsrc_rdy. If we're flushing the TRN hold trn_tsrc_rdy low.  //
+    //------------------------------------------------------------------------//
+    assign trn_tsrc_rdy = reg_tvalid && !disable_trn;
+
+
+    //------------------------------------------------------------------------//
+    // Create TREADY                                                          //
+    //------------------------------------------------------------------------//
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_tready <= #TCQ 1'b0;
+      end
+      else begin
+        // If the link went down and we need to flush a packet in flight, hold
+        // TREADY high
+        if(flush_axi && !axi_end_packet) begin
+          reg_tready <= #TCQ 1'b1;
+        end
+
+        // If the link is up, TREADY is as follows:
+        //   TREADY = 1 when trn_tsrc_rdy == 0
+        //      - While idle, keep the pipeline primed and ready for the next
+        //        packet
+        //
+        //   TREADY = trn_tdst_rdy when trn_tsrc_rdy == 1
+        //      - While in packet, throttle pipeline based on state of TRN
+        else if(trn_lnk_up) begin
+          reg_tready <= #TCQ trn_tdst_rdy || !trn_tsrc_rdy;
+        end
+
+        // If the link is down and we're not flushing a packet, hold TREADY low
+        // wait for link to come back up
+        else begin
+          reg_tready <= #TCQ 1'b0;
+        end
+      end
+    end
+
+    assign s_axis_tx_tready = reg_tready;
+  end
+
+
+  //--------------------------------------------------------------------------//
+  // Create flush_axi. This signal detects if the link goes down while the    //
+  // AXI interface is in packet. In this situation, we need to flush the      //
+  // packet through the AXI interface and discard it.                         //
+  //--------------------------------------------------------------------------//
+  always @(posedge user_clk) begin
+    if(user_rst) begin
+      flush_axi    <= #TCQ 1'b0;
+    end
+    else begin
+      // If the AXI interface is in packet and the link goes down, purge it.
+      if(axi_in_packet && !trn_lnk_up && !axi_end_packet) begin
+        flush_axi <= #TCQ 1'b1;
+      end
+
+      // The packet is finished, so we're done flushing.
+      else if(axi_end_packet) begin
+        flush_axi <= #TCQ 1'b0;
+      end
+    end
+  end
+endgenerate
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl.v

@@ -0,0 +1,784 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl.v
+// Version    : 3.3
+//                                                                            //
+//  Description:                                                              //
+//  TX throttle controller. Anticipates back-pressure from PCIe block and     //
+//  preemptively back-pressures user design (packet boundary throttling).     //
+//                                                                            //
+//  Notes:                                                                    //
+//  Optional notes section.                                                   //
+//                                                                            //
+//  Hierarchical:                                                             //
+//    axi_basic_top                                                           //
+//      axi_basic_tx                                                          //
+//        axi_basic_tx_thrtl_ctl                                              //
+//                                                                            //
+//----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_axi_basic_tx_thrtl_ctl #(
+  parameter C_DATA_WIDTH = 128,           // RX/TX interface data width
+  parameter C_FAMILY     = "X7",          // Targeted FPGA family
+  parameter C_ROOT_PORT  = "FALSE",       // PCIe block is in root port mode
+  parameter TCQ = 1                       // Clock to Q time
+  ) (
+
+  // AXI TX
+  //-----------
+  input  [C_DATA_WIDTH-1:0] s_axis_tx_tdata,         // TX data from user
+  input                     s_axis_tx_tvalid,        // TX data is valid
+  input               [3:0] s_axis_tx_tuser,         // TX user signals
+  input                     s_axis_tx_tlast,         // TX data is last
+
+  // User Misc.
+  //-----------
+  input                     user_turnoff_ok,         // Turnoff OK from user
+  input                     user_tcfg_gnt,           // Send cfg OK from user
+
+  // TRN TX
+  //-----------
+  input               [5:0] trn_tbuf_av,             // TX buffers available
+  input                     trn_tdst_rdy,            // TX destination ready
+
+  // TRN Misc.
+  //-----------
+  input                     trn_tcfg_req,            // TX config request
+  output                    trn_tcfg_gnt,            // TX config grant
+  input                     trn_lnk_up,              // PCIe link up
+
+  // 7 Series/Virtex6 PM
+  //-----------
+  input               [2:0] cfg_pcie_link_state,     // Encoded PCIe link state
+
+  // Virtex6 PM
+  //-----------
+  input                     cfg_pm_send_pme_to,      // PM send PME turnoff msg
+  input               [1:0] cfg_pmcsr_powerstate,    // PMCSR power state
+  input              [31:0] trn_rdllp_data,          // RX DLLP data
+  input                     trn_rdllp_src_rdy,       // RX DLLP source ready
+
+  // Virtex6/Spartan6 PM
+  //-----------
+  input                     cfg_to_turnoff,          // Turnoff request
+  output reg                cfg_turnoff_ok,          // Turnoff grant
+
+  // System
+  //-----------
+  output reg                tready_thrtl,            // TREADY to pipeline
+  input                     user_clk,                // user clock from block
+  input                     user_rst                 // user reset from block
+);
+
+// Thrtl user when TBUF hits this val
+localparam TBUF_AV_MIN = (C_DATA_WIDTH == 128) ? 5 :
+                                                   (C_DATA_WIDTH == 64) ? 1 : 0;
+
+// Pause user when TBUF hits this val
+localparam TBUF_AV_GAP = TBUF_AV_MIN + 1;
+
+// GAP pause time - the latency from the time a packet is accepted on the TRN
+// interface to the time trn_tbuf_av from the Block will decrement.
+localparam TBUF_GAP_TIME = (C_DATA_WIDTH == 128) ? 4 : 1;
+
+// Latency time from when tcfg_gnt is asserted to when PCIe block will throttle
+localparam TCFG_LATENCY_TIME = 2'd2;
+
+// Number of pipeline stages to delay trn_tcfg_gnt. For V6 128-bit only
+localparam TCFG_GNT_PIPE_STAGES = 3;
+
+// Throttle condition registers and constants
+reg        lnk_up_thrtl;
+wire       lnk_up_trig;
+wire       lnk_up_exit;
+
+reg        tbuf_av_min_thrtl;
+wire       tbuf_av_min_trig;
+
+reg        tbuf_av_gap_thrtl;
+reg  [2:0] tbuf_gap_cnt;
+wire       tbuf_av_gap_trig;
+wire       tbuf_av_gap_exit;
+wire       gap_trig_tlast;
+wire       gap_trig_decr;
+wire       gap_trig_tcfg;
+reg  [5:0] tbuf_av_d;
+
+reg        tcfg_req_thrtl;
+reg  [1:0] tcfg_req_cnt;
+reg        trn_tdst_rdy_d;
+wire       tcfg_req_trig;
+wire       tcfg_req_exit;
+reg        tcfg_gnt_log;
+
+wire       pre_throttle;
+wire       reg_throttle;
+wire       exit_crit;
+reg        reg_tcfg_gnt;
+reg        trn_tcfg_req_d;
+reg        tcfg_gnt_pending;
+wire       wire_to_turnoff;
+reg        reg_turnoff_ok;
+
+reg        tready_thrtl_mux;
+
+localparam LINKSTATE_L0             = 3'b000;
+localparam LINKSTATE_PPM_L1         = 3'b001;
+localparam LINKSTATE_PPM_L1_TRANS   = 3'b101;
+localparam LINKSTATE_PPM_L23R_TRANS = 3'b110;
+localparam PM_ENTER_L1              = 8'h20;
+localparam POWERSTATE_D0            = 2'b00;
+
+reg        ppm_L1_thrtl;
+wire       ppm_L1_trig;
+wire       ppm_L1_exit;
+reg  [2:0] cfg_pcie_link_state_d;
+reg        trn_rdllp_src_rdy_d;
+
+reg        ppm_L23_thrtl;
+wire       ppm_L23_trig;
+reg        cfg_turnoff_ok_pending;
+
+reg        reg_tlast;
+
+// Throttle control state machine states and registers
+localparam IDLE       = 0;
+localparam THROTTLE   = 1;
+reg        cur_state;
+reg        next_state;
+
+reg        reg_axi_in_pkt;
+wire       axi_in_pkt;
+wire       axi_pkt_ending;
+wire       axi_throttled;
+wire       axi_thrtl_ok;
+wire       tx_ecrc_pause;
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: PCIe link is down                                         //
+//   - When to throttle: trn_lnk_up deasserted                                //
+//   - When to stop: trn_tdst_rdy assesrted                                   //
+//----------------------------------------------------------------------------//
+assign lnk_up_trig = !trn_lnk_up;
+assign lnk_up_exit = trn_tdst_rdy;
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    lnk_up_thrtl <= #TCQ 1'b1;
+  end
+  else begin
+    if(lnk_up_trig) begin
+      lnk_up_thrtl <= #TCQ 1'b1;
+    end
+    else if(lnk_up_exit) begin
+      lnk_up_thrtl <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: Transmit buffers depleted                                 //
+//   - When to throttle: trn_tbuf_av falls to 0                               //
+//   - When to stop: trn_tbuf_av rises above 0 again                          //
+//----------------------------------------------------------------------------//
+assign tbuf_av_min_trig = (trn_tbuf_av <= TBUF_AV_MIN);
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    tbuf_av_min_thrtl <= #TCQ 1'b0;
+  end
+  else begin
+    if(tbuf_av_min_trig) begin
+      tbuf_av_min_thrtl <= #TCQ 1'b1;
+    end
+
+    // The exit condition for tbuf_av_min_thrtl is !tbuf_av_min_trig
+    else begin
+      tbuf_av_min_thrtl <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: Transmit buffers getting low                              //
+//   - When to throttle: trn_tbuf_av falls below "gap" threshold TBUF_AV_GAP  //
+//   - When to stop: after TBUF_GAP_TIME cycles elapse                        //
+//                                                                            //
+// If we're about to run out of transmit buffers, throttle the user for a     //
+// few clock cycles to give the PCIe block time to catch up. This is          //
+// needed to compensate for latency in decrementing trn_tbuf_av in the PCIe   //
+// Block transmit path.                                                       //
+//----------------------------------------------------------------------------//
+
+// Detect two different scenarios for buffers getting low:
+// 1) If we see a TLAST. a new packet has been inserted into the buffer, and
+//    we need to pause and let that packet "soak in"
+assign gap_trig_tlast = (trn_tbuf_av <= TBUF_AV_GAP) &&
+                            s_axis_tx_tvalid && tready_thrtl && s_axis_tx_tlast;
+
+// 2) Any time tbug_avail decrements to the TBUF_AV_GAP threshold, we need to
+//    pause and make sure no other packets are about to soak in and cause the
+//    buffer availability to drop further.
+assign gap_trig_decr  = (trn_tbuf_av == (TBUF_AV_GAP)) &&
+                                                 (tbuf_av_d == (TBUF_AV_GAP+1));
+
+assign gap_trig_tcfg  = (tcfg_req_thrtl && tcfg_req_exit);
+assign tbuf_av_gap_trig = gap_trig_tlast || gap_trig_decr || gap_trig_tcfg;
+assign tbuf_av_gap_exit = (tbuf_gap_cnt == 0);
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    tbuf_av_gap_thrtl <= #TCQ 1'b0;
+    tbuf_gap_cnt      <= #TCQ 3'h0;
+    tbuf_av_d         <= #TCQ 6'h00;
+  end
+  else begin
+    if(tbuf_av_gap_trig) begin
+      tbuf_av_gap_thrtl <= #TCQ 1'b1;
+    end
+    else if(tbuf_av_gap_exit) begin
+      tbuf_av_gap_thrtl <= #TCQ 1'b0;
+    end
+
+    // tbuf gap counter:
+    // This logic controls the length of the throttle condition when tbufs are
+    // getting low.
+    if(tbuf_av_gap_thrtl && (cur_state == THROTTLE)) begin
+      if(tbuf_gap_cnt > 0) begin
+        tbuf_gap_cnt <= #TCQ tbuf_gap_cnt - 3'd1;
+      end
+    end
+    else begin
+      tbuf_gap_cnt <= #TCQ TBUF_GAP_TIME;
+    end
+
+    tbuf_av_d <= #TCQ trn_tbuf_av;
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: Block needs to send a CFG response                        //
+//   - When to throttle: trn_tcfg_req and user_tcfg_gnt asserted              //
+//   - When to stop: after trn_tdst_rdy transitions to unasserted             //
+//                                                                            //
+// If the block needs to send a response to a CFG packet, this will cause     //
+// the subsequent deassertion of trn_tdst_rdy. When the user design permits,  //
+// grant permission to the block to service request and throttle the user.    //
+//----------------------------------------------------------------------------//
+assign tcfg_req_trig = trn_tcfg_req && reg_tcfg_gnt;
+assign tcfg_req_exit = (tcfg_req_cnt == 2'd0) && !trn_tdst_rdy_d &&
+                                                                   trn_tdst_rdy;
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    tcfg_req_thrtl   <= #TCQ 1'b0;
+    trn_tcfg_req_d   <= #TCQ 1'b0;
+    trn_tdst_rdy_d   <= #TCQ 1'b1;
+    reg_tcfg_gnt     <= #TCQ 1'b0;
+    tcfg_req_cnt     <= #TCQ 2'd0;
+    tcfg_gnt_pending <= #TCQ 1'b0;
+  end
+  else begin
+    if(tcfg_req_trig) begin
+      tcfg_req_thrtl <= #TCQ 1'b1;
+    end
+    else if(tcfg_req_exit) begin
+      tcfg_req_thrtl <= #TCQ 1'b0;
+    end
+
+    // We need to wait the appropriate amount of time for the tcfg_gnt to
+    // "sink in" to the PCIe block. After that, we know that the PCIe block will
+    // not reassert trn_tdst_rdy until the CFG request has been serviced. If a
+    // new request is being service (tcfg_gnt_log == 1), then reset the timer.
+    if((trn_tcfg_req && !trn_tcfg_req_d) || tcfg_gnt_pending) begin
+      tcfg_req_cnt <= #TCQ TCFG_LATENCY_TIME;
+    end
+    else begin
+      if(tcfg_req_cnt > 0) begin
+        tcfg_req_cnt <= #TCQ tcfg_req_cnt - 2'd1;
+      end
+    end
+
+    // Make sure tcfg_gnt_log pulses once for one clock cycle for every
+    // cfg packet request.
+    if(trn_tcfg_req && !trn_tcfg_req_d) begin
+      tcfg_gnt_pending <= #TCQ 1'b1;
+    end
+    else if(tcfg_gnt_log) begin
+      tcfg_gnt_pending <= #TCQ 1'b0;
+    end
+
+    trn_tcfg_req_d <= #TCQ trn_tcfg_req;
+    trn_tdst_rdy_d <= #TCQ trn_tdst_rdy;
+    reg_tcfg_gnt   <= #TCQ user_tcfg_gnt;
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: Block needs to transition to low power state PPM L1       //
+//   - When to throttle: appropriate low power state signal asserted          //
+//     (architecture dependent)                                               //
+//   - When to stop: cfg_pcie_link_state goes to proper value (C_ROOT_PORT    //
+//     dependent)                                                             //
+//                                                                            //
+// If the block needs to transition to PM state PPM L1, we need to finish     //
+// up what we're doing and throttle immediately.                              //
+//----------------------------------------------------------------------------//
+generate
+  // PPM L1 signals for 7 Series in RC mode
+  if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L1_thrtl_rp
+    assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
+                           (cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
+    assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
+  end
+
+  // PPM L1 signals for 7 Series in EP mode
+  else if((C_FAMILY == "X7") && (C_ROOT_PORT == "FALSE")) begin : x7_L1_thrtl_ep
+    assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
+                           (cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
+    assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
+  end
+
+  // PPM L1 signals for V6 in RC mode
+  else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L1_thrtl_rp
+    assign ppm_L1_trig = (trn_rdllp_data[31:24] == PM_ENTER_L1) &&
+                                      trn_rdllp_src_rdy && !trn_rdllp_src_rdy_d;
+    assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
+  end
+
+  // PPM L1 signals for V6 in EP mode
+  else if((C_FAMILY == "V6") && (C_ROOT_PORT == "FALSE")) begin : v6_L1_thrtl_ep
+    assign ppm_L1_trig = (cfg_pmcsr_powerstate != POWERSTATE_D0);
+    assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
+  end
+
+  // PPM L1 detection not supported for S6
+  else begin : s6_L1_thrtl
+    assign ppm_L1_trig = 1'b0;
+    assign ppm_L1_exit = 1'b1;
+  end
+endgenerate
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    ppm_L1_thrtl          <= #TCQ 1'b0;
+    cfg_pcie_link_state_d <= #TCQ 3'b0;
+    trn_rdllp_src_rdy_d   <= #TCQ 1'b0;
+  end
+  else begin
+    if(ppm_L1_trig) begin
+      ppm_L1_thrtl <= #TCQ 1'b1;
+    end
+    else if(ppm_L1_exit) begin
+      ppm_L1_thrtl <= #TCQ 1'b0;
+    end
+    cfg_pcie_link_state_d <= #TCQ cfg_pcie_link_state;
+    trn_rdllp_src_rdy_d   <= #TCQ trn_rdllp_src_rdy;
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// THROTTLE REASON: Block needs to transition to low power state PPM L2/3     //
+//   - When to throttle: appropriate PM signal indicates a transition to      //
+//     L2/3 is pending or in progress (family and role dependent)             //
+//   - When to stop: never (the only path out of L2/3 is a full reset)        //
+//                                                                            //
+// If the block needs to transition to PM state PPM L2/3, we need to finish   //
+// up what we're doing and throttle when the user gives permission.           //
+//----------------------------------------------------------------------------//
+generate
+  // PPM L2/3 signals for 7 Series in RC mode
+  if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L23_thrtl_rp
+    assign ppm_L23_trig = (cfg_pcie_link_state_d == LINKSTATE_PPM_L23R_TRANS);
+    assign wire_to_turnoff = 1'b0;
+  end
+
+  // PPM L2/3 signals for V6 in RC mode
+  else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L23_thrtl_rp
+    assign ppm_L23_trig = cfg_pm_send_pme_to;
+    assign wire_to_turnoff = 1'b0;
+  end
+
+  // PPM L2/3 signals in EP mode
+  else begin : L23_thrtl_ep
+    assign ppm_L23_trig = wire_to_turnoff && reg_turnoff_ok;
+
+    // PPM L2/3 signals for 7 Series in EP mode
+    // For 7 Series, cfg_to_turnoff pulses once when a turnoff request is
+    // outstanding, so we need a "sticky" register that grabs the request.
+    if(C_FAMILY == "X7") begin : x7_L23_thrtl_ep
+      reg reg_to_turnoff;
+
+      always @(posedge user_clk) begin
+        if(user_rst) begin
+          reg_to_turnoff <= #TCQ 1'b0;
+        end
+        else begin
+          if(cfg_to_turnoff) begin
+            reg_to_turnoff <= #TCQ 1'b1;
+          end
+        end
+      end
+
+      assign wire_to_turnoff = reg_to_turnoff;
+    end
+
+    // PPM L2/3 signals for V6/S6 in EP mode
+    // In V6 and S6, the to_turnoff signal asserts and remains asserted until
+    // turnoff_ok is asserted, so a sticky reg is not necessary.
+    else begin : v6_s6_L23_thrtl_ep
+      assign wire_to_turnoff = cfg_to_turnoff;
+    end
+
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_turnoff_ok <= #TCQ 1'b0;
+      end
+      else begin
+        reg_turnoff_ok <= #TCQ user_turnoff_ok;
+      end
+    end
+  end
+endgenerate
+
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    ppm_L23_thrtl   <= #TCQ 1'b0;
+    cfg_turnoff_ok_pending <= #TCQ 1'b0;
+  end
+  else begin
+    if(ppm_L23_trig) begin
+      ppm_L23_thrtl <= #TCQ 1'b1;
+    end
+
+    // Make sure cfg_turnoff_ok pulses once for one clock cycle for every
+    // turnoff request.
+    if(ppm_L23_trig && !ppm_L23_thrtl) begin
+      cfg_turnoff_ok_pending <= #TCQ 1'b1;
+    end
+    else if(cfg_turnoff_ok) begin
+      cfg_turnoff_ok_pending <= #TCQ 1'b0;
+    end
+  end
+end
+
+
+//----------------------------------------------------------------------------//
+// Create axi_thrtl_ok. This signal determines if it's OK to throttle the     //
+// user design on the AXI interface. Since TREADY is registered, this signal  //
+// needs to assert on the cycle ~before~ we actually intend to throttle.      //
+// The only time it's OK to throttle when TVALID is asserted is on the first  //
+// beat of a new packet. Therefore, assert axi_thrtl_ok if one of the         //
+// is true:                                                                   //
+//    1) The user is not in a packet and is not starting one                  //
+//    2) The user is just finishing a packet                                  //
+//    3) We're already throttled, so it's OK to continue throttling           //
+//----------------------------------------------------------------------------//
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    reg_axi_in_pkt <= #TCQ 1'b0;
+  end
+  else begin
+    if(s_axis_tx_tvalid && s_axis_tx_tlast) begin
+      reg_axi_in_pkt <= #TCQ 1'b0;
+    end
+    else if(tready_thrtl && s_axis_tx_tvalid) begin
+      reg_axi_in_pkt <= #TCQ 1'b1;
+    end
+  end
+end
+
+assign axi_in_pkt     = s_axis_tx_tvalid || reg_axi_in_pkt;
+assign axi_pkt_ending = s_axis_tx_tvalid && s_axis_tx_tlast;
+assign axi_throttled  = !tready_thrtl;
+assign axi_thrtl_ok   = !axi_in_pkt || axi_pkt_ending || axi_throttled;
+
+
+//----------------------------------------------------------------------------//
+// Throttle CTL State Machine:                                                //
+// Throttle user design when a throttle trigger (or triggers) occur.          //
+// Keep user throttled until all exit criteria have been met.                 //
+//----------------------------------------------------------------------------//
+
+// Immediate throttle signal. Used to "pounce" on a throttle opportunity when
+// we're seeking one
+assign pre_throttle = tbuf_av_min_trig || tbuf_av_gap_trig || lnk_up_trig
+                                || tcfg_req_trig || ppm_L1_trig || ppm_L23_trig;
+
+
+// Registered throttle signals. Used to control throttle state machine
+assign reg_throttle = tbuf_av_min_thrtl || tbuf_av_gap_thrtl || lnk_up_thrtl
+                             || tcfg_req_thrtl || ppm_L1_thrtl || ppm_L23_thrtl;
+
+assign exit_crit = !tbuf_av_min_thrtl && !tbuf_av_gap_thrtl && !lnk_up_thrtl
+                          && !tcfg_req_thrtl && !ppm_L1_thrtl && !ppm_L23_thrtl;
+
+always @(*) begin
+  case(cur_state)
+    // IDLE: in this state we're waiting for a trigger event to occur. As
+    // soon as an event occurs and the user isn't transmitting a packet, we
+    // throttle the PCIe block and the user and next state is THROTTLE.
+    IDLE: begin
+      if(reg_throttle && axi_thrtl_ok) begin
+        // Throttle user
+        tready_thrtl_mux = 1'b0;
+        next_state       = THROTTLE;
+
+        // Assert appropriate grant signal depending on the throttle type.
+        if(tcfg_req_thrtl) begin
+          tcfg_gnt_log   = 1'b1;   // For cfg request, grant the request
+          cfg_turnoff_ok = 1'b0;   //
+        end
+        else if(ppm_L23_thrtl) begin
+          tcfg_gnt_log   = 1'b0;   //
+          cfg_turnoff_ok = 1'b1;   // For PM request, permit transition
+        end
+        else begin
+          tcfg_gnt_log   = 1'b0;   // Otherwise do nothing
+          cfg_turnoff_ok = 1'b0;   //
+        end
+      end
+
+      // If there's not throttle event, do nothing
+      else begin
+        // Throttle user as soon as possible
+        tready_thrtl_mux = !(axi_thrtl_ok && pre_throttle);
+        next_state       = IDLE;
+
+        tcfg_gnt_log     = 1'b0;
+        cfg_turnoff_ok   = 1'b0;
+      end
+    end
+
+    // THROTTLE: in this state the user is throttle and we're waiting for
+    // exit criteria, which tells us that the throttle event is over. When
+    // the exit criteria is satisfied, de-throttle the user and next state
+    // is IDLE.
+    THROTTLE: begin
+      if(exit_crit) begin
+        // Dethrottle user
+        tready_thrtl_mux = !pre_throttle;
+        next_state       = IDLE;
+      end
+      else begin
+        // Throttle user
+        tready_thrtl_mux = 1'b0;
+        next_state       = THROTTLE;
+      end
+
+      // Assert appropriate grant signal depending on the throttle type.
+      if(tcfg_req_thrtl && tcfg_gnt_pending) begin
+        tcfg_gnt_log   = 1'b1;   // For cfg request, grant the request
+        cfg_turnoff_ok = 1'b0;   //
+      end
+      else if(cfg_turnoff_ok_pending) begin
+        tcfg_gnt_log   = 1'b0;   //
+        cfg_turnoff_ok = 1'b1;   // For PM request, permit transition
+      end
+      else begin
+        tcfg_gnt_log   = 1'b0;   // Otherwise do nothing
+        cfg_turnoff_ok = 1'b0;   //
+      end
+    end
+
+    default: begin
+      tready_thrtl_mux = 1'b0;
+      next_state       = IDLE;
+      tcfg_gnt_log     = 1'b0;
+      cfg_turnoff_ok   = 1'b0;
+    end
+  endcase
+end
+
+// Synchronous logic
+always @(posedge user_clk) begin
+  if(user_rst) begin
+    // Throttle user by default until link comes up
+    cur_state        <= #TCQ THROTTLE;
+
+    reg_tlast        <= #TCQ 1'b0;
+
+    tready_thrtl     <= #TCQ 1'b0;
+  end
+  else begin
+    cur_state        <= #TCQ next_state;
+
+    tready_thrtl     <= #TCQ tready_thrtl_mux && !tx_ecrc_pause;
+    reg_tlast        <= #TCQ s_axis_tx_tlast;
+  end
+end
+
+// For X7, the PCIe block will generate the ECRC for a packet if trn_tecrc_gen
+// is asserted at SOF. In this case, the Block needs an extra data beat to
+// calculate the ECRC, but only if the following conditions are met:
+//  1) there is no empty DWORDS at the end of the packet
+//     (i.e. packet length % C_DATA_WIDTH == 0)
+//
+//  2) There isn't a ECRC in the TLP already, as indicated by the TD bit in the
+//     TLP header
+//
+// If both conditions are met, the Block will stall the TRN interface for one
+// data beat after EOF. We need to predict this stall and preemptively stall the
+// User for one beat.
+generate
+  if(C_FAMILY == "X7") begin : ecrc_pause_enabled
+    wire        tx_ecrc_pkt;
+    reg         reg_tx_ecrc_pkt;
+
+    wire  [1:0] packet_fmt;
+    wire        packet_td;
+    wire  [2:0] header_len;
+    wire  [9:0] payload_len;
+    wire [13:0] packet_len;
+    wire        pause_needed;
+
+    // Grab necessary packet fields
+    assign packet_fmt  = s_axis_tx_tdata[30:29];
+    assign packet_td   = s_axis_tx_tdata[15];
+
+    // Calculate total packet length
+    assign header_len  = packet_fmt[0] ? 3'd4 : 3'd3;
+    assign payload_len = packet_fmt[1] ? s_axis_tx_tdata[9:0] : 10'h0;
+    assign packet_len  = {10'h000, header_len} + {4'h0, payload_len};
+
+
+    // Determine if packet a ECRC pause is needed
+    if(C_DATA_WIDTH == 128) begin : packet_len_check_128
+      assign pause_needed = (packet_len[1:0] == 2'b00) && !packet_td;
+    end
+    else begin : packet_len_check_64
+      assign pause_needed = (packet_len[0] == 1'b0) && !packet_td;
+    end
+
+
+    // Create flag to alert TX pipeline to insert a stall
+    assign tx_ecrc_pkt = s_axis_tx_tuser[0] && pause_needed &&
+                            tready_thrtl && s_axis_tx_tvalid && !reg_axi_in_pkt;
+
+    always @(posedge user_clk) begin
+      if(user_rst) begin
+        reg_tx_ecrc_pkt <= #TCQ 1'b0;
+      end
+      else begin
+        if(tx_ecrc_pkt && !s_axis_tx_tlast) begin
+          reg_tx_ecrc_pkt <= #TCQ 1'b1;
+        end
+        else if(tready_thrtl && s_axis_tx_tvalid && s_axis_tx_tlast) begin
+          reg_tx_ecrc_pkt <= #TCQ 1'b0;
+        end
+      end
+    end
+
+
+    // Insert the stall now
+    assign tx_ecrc_pause = ((tx_ecrc_pkt || reg_tx_ecrc_pkt) &&
+                           s_axis_tx_tlast && s_axis_tx_tvalid && tready_thrtl);
+
+  end
+  else begin : ecrc_pause_disabled
+    assign tx_ecrc_pause = 1'b0;
+  end
+endgenerate
+
+
+// Logic for 128-bit single cycle bug fix.
+// This tcfg_gnt pipeline addresses an issue with 128-bit V6 designs where a
+// single cycle packet transmitted simultaneously with an assertion of tcfg_gnt
+// from AXI Basic causes the packet to be dropped. The packet drop occurs
+// because the 128-bit shim doesn't know about the tcfg_req/gnt, and therefor
+// isn't expecting trn_tdst_rdy to go low. Since the 128-bit shim does throttle
+// prediction just as we do, it ignores the value of trn_tdst_rdy, and
+// ultimately drops the packet when transmitting the packet to the block.
+generate
+  if(C_DATA_WIDTH == 128 && C_FAMILY == "V6") begin : tcfg_gnt_pipeline
+    genvar stage;
+    reg tcfg_gnt_pipe [TCFG_GNT_PIPE_STAGES:0];
+
+    // Create a configurable depth FF delay pipeline
+    for(stage = 0; stage < TCFG_GNT_PIPE_STAGES; stage = stage + 1)
+    begin : tcfg_gnt_pipeline_stage
+
+      always @(posedge user_clk) begin
+        if(user_rst) begin
+          tcfg_gnt_pipe[stage] <= #TCQ 1'b0;
+        end
+        else begin
+          // For stage 0, insert the actual tcfg_gnt signal from logic
+          if(stage == 0) begin
+            tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_log;
+          end
+
+          // For stages 1+, chain together
+          else begin
+            tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_pipe[stage - 1];
+          end
+        end
+      end
+
+      // tcfg_gnt output to block assigned the last pipeline stage
+      assign trn_tcfg_gnt = tcfg_gnt_pipe[TCFG_GNT_PIPE_STAGES-1];
+    end
+  end
+  else begin : tcfg_gnt_no_pipeline
+
+    // For all other architectures, no pipeline delay needed for tcfg_gnt
+    assign trn_tcfg_gnt = tcfg_gnt_log;
+  end
+endgenerate
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_gt_common.v

@@ -0,0 +1,166 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_gt_common.v
+// Version    : 3.3
+`timescale 1ns / 1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_gt_common #(
+
+parameter PCIE_SIM_MODE    = "FALSE",   // PCIe sim mode
+parameter PCIE_GT_DEVICE   = "GTX",     // PCIe GT device
+parameter PCIE_USE_MODE    = "2.1",     // PCIe use mode
+parameter PCIE_PLL_SEL     = "CPLL",    // PCIe PLL select for Gen1/Gen2 only
+parameter PCIE_REFCLK_FREQ = 0          // PCIe reference clock frequency
+)
+
+(
+input                   CPLLPDREFCLK,
+input               	PIPE_CLK,
+input               	QPLL_QPLLPD,
+input               	QPLL_QPLLRESET,
+input               	QPLL_DRP_CLK,
+input               	QPLL_DRP_RST_N,
+input               	QPLL_DRP_OVRD,
+input               	QPLL_DRP_GEN3,
+input               	QPLL_DRP_START,
+output      [5:0]  	QPLL_DRP_CRSCODE,
+output      [8:0]  	QPLL_DRP_FSM,
+output                  QPLL_DRP_DONE,
+output                  QPLL_DRP_RESET,
+output                  QPLL_QPLLLOCK,
+output                  QPLL_QPLLOUTCLK,
+output                  QPLL_QPLLOUTREFCLK
+);
+
+    //---------- QPLL DRP Module Output --------------------
+
+wire        [7:0]  qpll_drp_addr;
+wire               qpll_drp_en;
+wire        [15:0] qpll_drp_di;
+wire               qpll_drp_we;
+
+   //---------- QPLL Wrapper Output -----------------------
+
+wire        [15:0] qpll_drp_do;
+wire               qpll_drp_rdy;
+
+   //---------- QPLL Resets -----------------------
+
+
+        //---------- QPLL DRP Module ---------------------------------------
+
+xdma_0_pcie2_ip_qpll_drp #
+        (
+
+	        .PCIE_GT_DEVICE                 (PCIE_GT_DEVICE),               // PCIe GT device
+	        .PCIE_USE_MODE                  (PCIE_USE_MODE),                // PCIe use mode
+	        .PCIE_PLL_SEL                   (PCIE_PLL_SEL),                 // PCIe PLL select for Gen1/Gen2 only
+	        .PCIE_REFCLK_FREQ               (PCIE_REFCLK_FREQ)              // PCIe reference clock frequency
+
+        )
+        qpll_drp_i
+        (
+
+        //---------- Input -------------------------
+	    .DRP_CLK                        (QPLL_DRP_CLK),
+            .DRP_RST_N                      (!QPLL_DRP_RST_N),
+            .DRP_OVRD                       (QPLL_DRP_OVRD),
+            .DRP_GEN3                       (&QPLL_DRP_GEN3),
+            .DRP_QPLLLOCK                   (QPLL_QPLLLOCK),
+            .DRP_START                      (QPLL_DRP_START),
+            .DRP_DO                         (qpll_drp_do),
+            .DRP_RDY                        (qpll_drp_rdy),
+																													     
+        //----------           Output ------------------------
+            .DRP_ADDR                       (qpll_drp_addr),
+            .DRP_EN                         (qpll_drp_en),
+            .DRP_DI                         (qpll_drp_di),
+            .DRP_WE                         (qpll_drp_we),
+            .DRP_DONE                       (QPLL_DRP_DONE),
+            .DRP_QPLLRESET                  (QPLL_DRP_RESET),
+            .DRP_CRSCODE                    (QPLL_DRP_CRSCODE),
+            .DRP_FSM                        (QPLL_DRP_FSM)
+        );
+
+
+        //---------- QPLL Wrapper ------------------------------------------
+xdma_0_pcie2_ip_qpll_wrapper #
+        (
+	        .PCIE_SIM_MODE                  (PCIE_SIM_MODE),                // PCIe sim mode
+	        .PCIE_GT_DEVICE                 (PCIE_GT_DEVICE),               // PCIe GT device
+	        .PCIE_USE_MODE                  (PCIE_USE_MODE),                // PCIe use mode
+	        .PCIE_PLL_SEL                   (PCIE_PLL_SEL),                 // PCIe PLL select for Gen1/Gen2 only
+	        .PCIE_REFCLK_FREQ               (PCIE_REFCLK_FREQ)              // PCIe reference clock frequency
+        )
+        qpll_wrapper_i
+        (
+        //---------- QPLL Clock Ports --------------
+            .QPLL_CPLLPDREFCLK              (CPLLPDREFCLK),
+            .QPLL_GTGREFCLK                 (PIPE_CLK),
+            .QPLL_QPLLLOCKDETCLK            (1'd0),
+            .QPLL_QPLLOUTCLK                (QPLL_QPLLOUTCLK),
+            .QPLL_QPLLOUTREFCLK             (QPLL_QPLLOUTREFCLK),
+            .QPLL_QPLLLOCK                  (QPLL_QPLLLOCK),
+        //---------- QPLL Reset Ports --------------
+            .QPLL_QPLLPD                    (QPLL_QPLLPD),
+            .QPLL_QPLLRESET                 (QPLL_QPLLRESET),
+        //---------- QPLL DRP Ports ----------------
+            .QPLL_DRPCLK                    (QPLL_DRP_CLK),
+            .QPLL_DRPADDR                   (qpll_drp_addr),
+            .QPLL_DRPEN                     (qpll_drp_en),
+            .QPLL_DRPDI                     (qpll_drp_di),
+            .QPLL_DRPWE                     (qpll_drp_we),
+            .QPLL_DRPDO                     (qpll_drp_do),
+            .QPLL_DRPRDY                    (qpll_drp_rdy)			
+        );
+  
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_gt_rx_valid_filter_7x.v

@@ -0,0 +1,285 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_gt_rx_valid_filter_7x.v
+// Version    : 3.3
+//-- Description: GTX module for 7-series Integrated PCIe Block
+//--
+//--
+//--
+//--------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_gt_rx_valid_filter_7x #(
+
+  parameter           CLK_COR_MIN_LAT    = 28,
+  parameter           TCQ                = 1
+
+)
+(
+  output  [1:0]       USER_RXCHARISK,
+  output  [15:0]      USER_RXDATA,
+  output              USER_RXVALID,
+  output              USER_RXELECIDLE,
+  output  [ 2:0]      USER_RX_STATUS,
+  output              USER_RX_PHY_STATUS,
+  input  [1:0]        GT_RXCHARISK,
+  input  [15:0]       GT_RXDATA,
+  input               GT_RXVALID,
+  input               GT_RXELECIDLE,
+  input  [ 2:0]       GT_RX_STATUS,
+  input               GT_RX_PHY_STATUS,
+
+  input               PLM_IN_L0,
+  input               PLM_IN_RS,
+
+  input               USER_CLK,
+  input               RESET
+
+);
+
+
+
+  localparam EIOS_DET_IDL      = 5'b00001;
+  localparam EIOS_DET_NO_STR0  = 5'b00010;
+  localparam EIOS_DET_STR0     = 5'b00100;
+  localparam EIOS_DET_STR1     = 5'b01000;
+  localparam EIOS_DET_DONE     = 5'b10000;
+
+  localparam EIOS_COM          = 8'hBC;
+  localparam EIOS_IDL          = 8'h7C;
+  localparam FTSOS_COM         = 8'hBC;
+  localparam FTSOS_FTS         = 8'h3C;
+
+  reg    [4:0]        reg_state_eios_det;
+  wire   [4:0]        state_eios_det;
+
+  reg                 reg_eios_detected;
+  wire                eios_detected;
+
+  reg                 reg_symbol_after_eios;
+  wire                symbol_after_eios;
+
+  localparam USER_RXVLD_IDL     = 4'b0001;
+  localparam USER_RXVLD_EI      = 4'b0010;
+  localparam USER_RXVLD_EI_DB0  = 4'b0100;
+  localparam USER_RXVLD_EI_DB1  = 4'b1000;
+
+
+  reg    [1:0]        gt_rxcharisk_q;
+  reg    [15:0]       gt_rxdata_q;
+  reg                 gt_rxvalid_q;
+  reg                 gt_rxelecidle_q;
+
+  reg    [ 2:0]       gt_rx_status_q;
+  reg                 gt_rx_phy_status_q;
+  reg                 gt_rx_is_skp0_q;
+  reg                 gt_rx_is_skp1_q;
+
+  // EIOS detector
+
+  always @(posedge USER_CLK) begin
+
+    if (RESET) begin
+
+      reg_eios_detected <= #TCQ 1'b0;
+      reg_state_eios_det <= #TCQ EIOS_DET_IDL;
+      reg_symbol_after_eios <= #TCQ 1'b0;
+      gt_rxcharisk_q <= #TCQ 2'b00;
+      gt_rxdata_q <= #TCQ 16'h0;
+      gt_rxvalid_q <= #TCQ 1'b0;
+      gt_rxelecidle_q <= #TCQ 1'b0;
+      gt_rx_status_q <= #TCQ 3'b000;
+      gt_rx_phy_status_q <= #TCQ 1'b0;
+      gt_rx_is_skp0_q <= #TCQ 1'b0;
+      gt_rx_is_skp1_q <= #TCQ 1'b0;
+
+    end else begin
+      reg_eios_detected <= #TCQ 1'b0;
+      reg_symbol_after_eios <= #TCQ 1'b0;
+        gt_rxcharisk_q <= #TCQ GT_RXCHARISK;
+        gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;
+      gt_rxdata_q <= #TCQ GT_RXDATA;
+      gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;
+      
+     //De-assert rx_valid signal when EIOS is detected on RXDATA
+      if(((reg_state_eios_det == 5'b10000)) && (PLM_IN_L0)
+       ) begin
+       
+        gt_rxvalid_q <= #TCQ 1'b0; 
+      end
+      else if (GT_RXELECIDLE && !gt_rxvalid_q) begin
+         gt_rxvalid_q <= #TCQ 1'b0; 
+      end   
+      else begin
+       gt_rxvalid_q <= GT_RXVALID;
+     end  
+
+     if (gt_rxvalid_q) begin
+      gt_rx_status_q <= #TCQ GT_RX_STATUS;
+       
+     end
+     else if (!gt_rxvalid_q && PLM_IN_L0) begin
+      gt_rx_status_q <= #TCQ 3'b0;
+     end
+     else begin
+      gt_rx_status_q <= #TCQ GT_RX_STATUS;
+     end  
+
+      
+      
+      if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS)
+        gt_rx_is_skp0_q <= #TCQ 1'b1;
+      else
+        gt_rx_is_skp0_q <= #TCQ 1'b0;
+
+      if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS)
+        gt_rx_is_skp1_q <= #TCQ 1'b1;
+      else
+        gt_rx_is_skp1_q <= #TCQ 1'b0;
+
+      case ( state_eios_det )
+
+        EIOS_DET_IDL : begin
+
+          if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&
+              (gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin
+
+            reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;
+            reg_eios_detected <= #TCQ 1'b1;
+          //  gt_rxvalid_q <= #TCQ 1'b0;
+
+          end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))
+            reg_state_eios_det <= #TCQ EIOS_DET_STR0;
+          else
+            reg_state_eios_det <= #TCQ EIOS_DET_IDL;
+
+        end
+
+        EIOS_DET_NO_STR0 : begin
+
+          if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
+              (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))
+              begin
+            reg_state_eios_det <= #TCQ EIOS_DET_DONE;
+            gt_rxvalid_q <= #TCQ 1'b0;
+            end
+         else if (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) begin
+            
+            reg_state_eios_det <= #TCQ EIOS_DET_DONE;
+            gt_rxvalid_q <= #TCQ 1'b0;
+            end
+          else
+            reg_state_eios_det <= #TCQ EIOS_DET_IDL;
+
+        end
+
+        EIOS_DET_STR0 : begin
+
+          if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
+              (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin
+
+            reg_state_eios_det <= #TCQ EIOS_DET_STR1;
+            reg_eios_detected <= #TCQ 1'b1;
+            gt_rxvalid_q <= #TCQ 1'b0;
+            reg_symbol_after_eios <= #TCQ 1'b1;
+
+          end else
+            reg_state_eios_det <= #TCQ EIOS_DET_IDL;
+
+        end
+
+        EIOS_DET_STR1 : begin
+
+          if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))
+          begin
+            reg_state_eios_det <= #TCQ EIOS_DET_DONE;
+            gt_rxvalid_q <= #TCQ 1'b0;
+          end  
+          else
+            reg_state_eios_det <= #TCQ EIOS_DET_IDL;
+
+        end
+
+        EIOS_DET_DONE : begin
+
+          reg_state_eios_det <= #TCQ EIOS_DET_IDL;
+
+        end
+
+      endcase
+
+    end
+
+  end
+  assign state_eios_det = reg_state_eios_det;
+  assign eios_detected = reg_eios_detected;
+  assign symbol_after_eios = reg_symbol_after_eios;
+  /*SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),
+                                         .D(gt_rxelecidle_q),
+                                         .CLK(USER_CLK),
+                                         .CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
+*/
+wire    rst_l = ~RESET;
+
+
+assign USER_RXVALID = gt_rxvalid_q;
+assign USER_RXCHARISK[0] = gt_rxvalid_q ? gt_rxcharisk_q[0] : 1'b0;
+assign USER_RXCHARISK[1] = (gt_rxvalid_q && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;
+assign USER_RXDATA[7:0] = gt_rxdata_q[7:0];
+assign USER_RXDATA[15:8] = gt_rxdata_q[15:8];
+assign USER_RX_STATUS = gt_rx_status_q;
+assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;
+assign USER_RXELECIDLE = gt_rxelecidle_q;
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_gtp_cpllpd_ovrd.v

@@ -0,0 +1,68 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_gtp_cpllpd_ovrd.v
+// Version    : 3.3
+`timescale 1ns / 1ps
+module xdma_0_pcie2_ip_gtp_cpllpd_ovrd (                                                                                        
+    input   i_ibufds_gte2,                                                                                     
+    output  o_cpllpd_ovrd,                                                                                     
+    output  o_cpllreset_ovrd                                                                                   
+    );                                                                                                         
+    (* equivalent_register_removal="no" *)  reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;             
+    (* equivalent_register_removal="no" *)  reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF;
+    always @(posedge i_ibufds_gte2)                                                                            
+    begin                                                                                                      
+        cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};                                                              
+        cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};                                                       
+    end                                                                                                        
+    assign o_cpllpd_ovrd = cpllpd_wait[95];                                                                    
+    assign o_cpllreset_ovrd = cpllreset_wait[127];                                                             
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_gtp_pipe_drp.v

@@ -0,0 +1,370 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_gtp_pipe_drp.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  gtp_pipe_drp.v
+//  Description  :  GTP PIPE DRP Module for 7 Series Transceiver
+//  Version      :  19.0
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- GTP PIPE DRP Module -----------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_gtp_pipe_drp #
+(
+
+    parameter LOAD_CNT_MAX     = 2'd1,                      // Load max count
+    parameter INDEX_MAX        = 1'd0                       // Index max count
+    
+)
+
+(
+    
+    //---------- Input -------------------------------------
+    input               DRP_CLK,
+    input               DRP_RST_N,
+    input               DRP_X16,
+    input               DRP_START,
+    input       [15:0]  DRP_DO,
+    input               DRP_RDY,
+    
+    //---------- Output ------------------------------------
+    output      [ 8:0]  DRP_ADDR,
+    output              DRP_EN,  
+    output      [15:0]  DRP_DI,   
+    output              DRP_WE,
+    output              DRP_DONE,
+    output      [ 2:0]  DRP_FSM
+    
+);
+
+    //---------- Input Registers ---------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 x16_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 start_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [15:0]  do_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rdy_reg1;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 x16_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 start_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [15:0]  do_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rdy_reg2;
+    
+    //---------- Internal Signals --------------------------
+    reg         [ 1:0]  load_cnt =  2'd0;
+    reg         [ 4:0]  index    =  5'd0;
+    reg         [ 8:0]  addr_reg =  9'd0;
+    reg         [15:0]  di_reg   = 16'd0;
+    
+    //---------- Output Registers --------------------------
+    reg                 done     =  1'd0;
+    reg         [ 2:0]  fsm      =  0;      
+                        
+    //---------- DRP Address -------------------------------          
+    localparam          ADDR_RX_DATAWIDTH  = 9'h011;              
+    
+    //---------- DRP Mask ----------------------------------
+    localparam          MASK_RX_DATAWIDTH  = 16'b1111011111111111;  // Unmask bit [   11]  
+         
+    //---------- DRP Data for x16 --------------------------
+    localparam          X16_RX_DATAWIDTH   = 16'b0000000000000000;  // 2-byte (16-bit) internal data width
+    
+    //---------- DRP Data for x20 --------------------------                                  
+    localparam          X20_RX_DATAWIDTH   = 16'b0000100000000000;  // 2-byte (20-bit) internal data width               
+      
+    //---------- DRP Data ----------------------------------                  
+    wire        [15:0]  data_rx_datawidth;                 
+           
+    //---------- FSM ---------------------------------------  
+    localparam          FSM_IDLE  = 0;  
+    localparam          FSM_LOAD  = 1;                           
+    localparam          FSM_READ  = 2;
+    localparam          FSM_RRDY  = 3;
+    localparam          FSM_WRITE = 4;
+    localparam          FSM_WRDY  = 5;    
+    localparam          FSM_DONE  = 6;   
+
+    
+    
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        begin
+        //---------- 1st Stage FF --------------------------
+        x16_reg1   <=  1'd0;
+        do_reg1    <= 16'd0;
+        rdy_reg1   <=  1'd0;
+        start_reg1 <=  1'd0;
+        //---------- 2nd Stage FF --------------------------
+        x16_reg2   <=  1'd0;
+        do_reg2    <= 16'd0;
+        rdy_reg2   <=  1'd0;
+        start_reg2 <=  1'd0;
+        end
+        
+    else
+        begin
+        //---------- 1st Stage FF --------------------------
+        x16_reg1   <= DRP_X16;
+        do_reg1    <= DRP_DO;
+        rdy_reg1   <= DRP_RDY;
+        start_reg1 <= DRP_START;
+        //---------- 2nd Stage FF --------------------------
+        x16_reg2   <= x16_reg1;
+        do_reg2    <= do_reg1;
+        rdy_reg2   <= rdy_reg1;
+        start_reg2 <= start_reg1;
+        end
+    
+end  
+
+
+
+//---------- Select DRP Data ---------------------------------------------------
+assign data_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
+
+
+
+//---------- Load Counter ------------------------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        load_cnt <= 2'd0;
+    else
+    
+        //---------- Increment Load Counter ----------------
+        if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
+            load_cnt <= load_cnt + 2'd1;
+            
+        //---------- Hold Load Counter ---------------------
+        else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
+            load_cnt <= load_cnt;
+            
+        //---------- Reset Load Counter --------------------
+        else
+            load_cnt <= 2'd0;
+        
+end 
+
+
+
+//---------- Update DRP Address and Data ---------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        begin
+        addr_reg <=  9'd0;
+        di_reg   <= 16'd0;
+        end
+    else
+        begin
+        
+        case (index)
+        
+        //--------------------------------------------------     
+        1'd0 :
+            begin        
+            addr_reg <= ADDR_RX_DATAWIDTH;
+            di_reg   <= (do_reg2 & MASK_RX_DATAWIDTH) | data_rx_datawidth;
+            end              
+            
+        //--------------------------------------------------
+        default : 
+            begin
+            addr_reg <=  9'd0;
+            di_reg   <= 16'd0;
+            end
+            
+        endcase
+        
+        end
+        
+end  
+
+
+
+//---------- PIPE DRP FSM ------------------------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        begin
+        fsm   <= FSM_IDLE;
+        index <= 5'd0;
+        done  <= 1'd1; //Fix applied for GTP DRP issue
+        end
+    else
+        begin
+        
+        case (fsm)
+
+        //---------- Idle State ----------------------------
+        FSM_IDLE :  
+          
+            begin
+            //---------- Reset or Rate Change --------------
+            if (start_reg2)
+                begin
+                fsm   <= FSM_LOAD;
+                index <= 5'd0;
+                done  <= 1'd0; 
+                end
+            //---------- Idle ------------------------------
+            else       
+                begin
+                fsm   <= FSM_IDLE;
+                index <= 5'd0;
+                done  <= 1'd1;
+                end 
+            end    
+            
+        //---------- Load DRP Address  ---------------------
+        FSM_LOAD :
+        
+            begin
+            fsm   <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
+            index <= index;
+
+            done  <= 1'd0;
+            end  
+            
+        //---------- Read DRP ------------------------------
+        FSM_READ :
+        
+            begin
+            fsm   <= FSM_RRDY;
+            index <= index;
+            done  <= 1'd0;
+            end
+            
+        //---------- Read DRP Ready ------------------------
+        FSM_RRDY :    
+        
+            begin
+            fsm   <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
+            index <= index;
+            done  <= 1'd0;
+            end
+  
+            
+        //---------- Write DRP -----------------------------
+        FSM_WRITE :    
+        
+            begin
+            fsm   <= FSM_WRDY;
+            index <= index;
+            done  <= 1'd0;
+            end       
+            
+        //---------- Write DRP Ready -----------------------
+        FSM_WRDY :    
+        
+            begin
+            fsm   <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
+            index <= index;
+            done  <= 1'd0;
+            end        
+             
+        //---------- DRP Done ------------------------------
+        FSM_DONE :
+        
+            begin
+            if (index == INDEX_MAX)
+                begin
+                fsm   <= FSM_IDLE;
+                index <= 5'd0;
+                done  <= 1'd1;	//Fix applied for GTP DRP issue
+                end
+            else       
+                begin
+                fsm   <= FSM_LOAD;
+                index <= index + 5'd1;
+                done  <= 1'd0;
+                end
+            end     
+              
+        //---------- Default State -------------------------
+        default :
+        
+            begin      
+            fsm   <= FSM_IDLE;
+            index <= 5'd0;
+            done  <= 1'd1; //Fix applied for GTP DRP issue
+            end
+            
+        endcase
+        
+        end
+        
+end 
+
+
+
+//---------- PIPE DRP Output ---------------------------------------------------
+assign DRP_ADDR = addr_reg;
+assign DRP_EN   = (fsm == FSM_READ) || (fsm == FSM_WRITE);
+assign DRP_DI   = di_reg;
+assign DRP_WE   = (fsm == FSM_WRITE);
+assign DRP_DONE = done;
+assign DRP_FSM  = fsm;
+
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_gtp_pipe_rate.v

@@ -0,0 +1,461 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_gtp_pipe_rate.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  gtp_pipe_rate.v
+//  Description  :  PIPE Rate Module for 7 Series Transceiver
+//  Version      :  19.0
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- PIPE Rate Module --------------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_gtp_pipe_rate #
+(
+
+    parameter PCIE_SIM_SPEEDUP = "FALSE",                   // PCIe sim mode 
+    parameter TXDATA_WAIT_MAX  = 4'd15                      // TXDATA wait max
+
+)
+
+(
+
+    //---------- Input -------------------------------------
+    input               RATE_CLK,
+    input               RATE_RST_N,
+    input       [ 1:0]  RATE_RATE_IN,
+    input               RATE_DRP_DONE,
+    input               RATE_RXPMARESETDONE,
+    input               RATE_TXRATEDONE,
+    input               RATE_RXRATEDONE,
+    input               RATE_TXSYNC_DONE,
+    input               RATE_PHYSTATUS,
+    
+    //---------- Output ------------------------------------
+    output              RATE_PCLK_SEL,
+    output              RATE_DRP_START,
+    output              RATE_DRP_X16,
+    output      [ 2:0]  RATE_RATE_OUT,
+    output              RATE_TXSYNC_START,
+    output              RATE_DONE,
+    output              RATE_IDLE,
+    output      [ 4:0]  RATE_FSM
+
+);
+
+    //---------- Input FF or Buffer ------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 1:0]  rate_in_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 drp_done_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxpmaresetdone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txratedone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxratedone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 phystatus_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsync_done_reg1;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 1:0]  rate_in_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 drp_done_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxpmaresetdone_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txratedone_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxratedone_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 phystatus_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsync_done_reg2;
+    
+    //---------- Internal Signals --------------------------
+    wire        [ 2:0]  rate;
+    reg         [ 3:0]  txdata_wait_cnt = 4'd0;
+    reg                 txratedone      = 1'd0;
+    reg                 rxratedone      = 1'd0;
+    reg                 phystatus       = 1'd0;
+    reg                 ratedone        = 1'd0;
+    
+    //---------- Output FF or Buffer -----------------------
+    reg                 pclk_sel =  1'd0; 
+    reg         [ 2:0]  rate_out =  3'd0; 
+    reg         [ 3:0]  fsm      =  0;                 
+   
+    //---------- FSM ---------------------------------------                                         
+    localparam          FSM_IDLE           = 0; 
+    localparam          FSM_TXDATA_WAIT    = 1;           
+    localparam          FSM_PCLK_SEL       = 2; 
+    localparam          FSM_DRP_X16_START  = 3;
+    localparam          FSM_DRP_X16_DONE   = 4;   
+    localparam          FSM_RATE_SEL       = 5;
+    localparam          FSM_RXPMARESETDONE = 6; 
+    localparam          FSM_DRP_X20_START  = 7;
+    localparam          FSM_DRP_X20_DONE   = 8;   
+    localparam          FSM_RATE_DONE      = 9;
+    localparam          FSM_TXSYNC_START   = 10;
+    localparam          FSM_TXSYNC_DONE    = 11;             
+    localparam          FSM_DONE           = 12; // Must sync value to pipe_user.v
+    
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge RATE_CLK)
+begin
+
+    if (!RATE_RST_N)
+        begin    
+        //---------- 1st Stage FF -------------------------- 
+        rate_in_reg1        <= 2'd0;
+        drp_done_reg1       <= 1'd0;
+        rxpmaresetdone_reg1 <= 1'd0;
+        txratedone_reg1     <= 1'd0;
+        rxratedone_reg1     <= 1'd0;
+        phystatus_reg1      <= 1'd0;
+        txsync_done_reg1    <= 1'd0;
+        //---------- 2nd Stage FF --------------------------
+        rate_in_reg2        <= 2'd0;
+        drp_done_reg2       <= 1'd0;
+        rxpmaresetdone_reg2 <= 1'd0;
+        txratedone_reg2     <= 1'd0;
+        rxratedone_reg2     <= 1'd0;
+        phystatus_reg2      <= 1'd0;
+        txsync_done_reg2    <= 1'd0;
+        end
+    else
+        begin  
+        //---------- 1st Stage FF --------------------------
+        rate_in_reg1        <= RATE_RATE_IN;
+        drp_done_reg1       <= RATE_DRP_DONE;
+        rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
+        txratedone_reg1     <= RATE_TXRATEDONE;
+        rxratedone_reg1     <= RATE_RXRATEDONE;
+        phystatus_reg1      <= RATE_PHYSTATUS;
+        txsync_done_reg1    <= RATE_TXSYNC_DONE;
+        //---------- 2nd Stage FF --------------------------
+        rate_in_reg2        <= rate_in_reg1;
+        drp_done_reg2       <= drp_done_reg1;
+        rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
+        txratedone_reg2     <= txratedone_reg1;
+        rxratedone_reg2     <= rxratedone_reg1;
+        phystatus_reg2      <= phystatus_reg1;
+        txsync_done_reg2    <= txsync_done_reg1;   
+        end
+        
+end    
+
+
+
+//---------- Select Rate -------------------------------------------------------
+//  Gen1 :  div 2 using [TX/RX]OUT_DIV = 2
+//  Gen2 :  div 1 using [TX/RX]RATE = 3'd1
+//------------------------------------------------------------------------------
+assign rate = (rate_in_reg2 == 2'd1) ? 3'd1 : 3'd0;
+
+
+
+//---------- TXDATA Wait Counter -----------------------------------------------
+always @ (posedge RATE_CLK)
+begin
+
+    if (!RATE_RST_N)
+        txdata_wait_cnt <= 4'd0;
+    else
+    
+        //---------- Increment Wait Counter ----------------
+        if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
+            txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
+            
+        //---------- Hold Wait Counter ---------------------
+        else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
+            txdata_wait_cnt <= txdata_wait_cnt;
+            
+        //---------- Reset Wait Counter --------------------
+        else
+            txdata_wait_cnt <= 4'd0;
+        
+end 
+
+
+
+//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
+always @ (posedge RATE_CLK)
+begin
+
+    if (!RATE_RST_N)
+        begin   
+        txratedone <= 1'd0;
+        rxratedone <= 1'd0; 
+        phystatus  <= 1'd0;
+        ratedone   <= 1'd0;
+        end
+    else
+        begin  
+
+        if ((fsm == FSM_RATE_DONE) || (fsm == FSM_RXPMARESETDONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE))
+        
+            begin
+            
+            //---------- Latch TXRATEDONE ------------------
+            if (txratedone_reg2)
+                txratedone <= 1'd1; 
+            else
+                txratedone <= txratedone;
+ 
+            //---------- Latch RXRATEDONE ------------------
+            if (rxratedone_reg2)
+                rxratedone <= 1'd1; 
+            else
+                rxratedone <= rxratedone;
+  
+            //---------- Latch PHYSTATUS -------------------
+            if (phystatus_reg2)
+                phystatus <= 1'd1; 
+            else
+                phystatus <= phystatus;
+  
+            //---------- Latch Rate Done -------------------
+            if (rxratedone && txratedone && phystatus)
+                ratedone <= 1'd1; 
+            else
+                ratedone <= ratedone;
+  
+            end
+  
+        else 
+        
+            begin
+            txratedone <= 1'd0;
+            rxratedone <= 1'd0;
+            phystatus  <= 1'd0;
+            ratedone   <= 1'd0;
+            end
+        
+        end
+        
+end    
+
+
+
+//---------- PIPE Rate FSM -----------------------------------------------------
+always @ (posedge RATE_CLK)
+begin
+
+    if (!RATE_RST_N)
+        begin
+        fsm      <= FSM_IDLE;
+        pclk_sel <= 1'd0; 
+        rate_out <= 3'd0;                              
+        end
+    else
+        begin
+        
+        case (fsm)
+            
+        //---------- Idle State ----------------------------
+        FSM_IDLE :
+        
+            begin
+            //---------- Detect Rate Change ----------------
+            if (rate_in_reg2 != rate_in_reg1)
+                begin
+                fsm      <= FSM_TXDATA_WAIT;
+                pclk_sel <= pclk_sel;
+                rate_out <= rate_out;
+                end
+            else
+                begin
+                fsm      <= FSM_IDLE;
+                pclk_sel <= pclk_sel;
+                rate_out <= rate_out;
+                end
+            end 
+            
+        //---------- Wait for TXDATA to TX[P/N] Latency ----    
+        FSM_TXDATA_WAIT :
+        
+            begin
+            fsm      <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
+            pclk_sel <= pclk_sel;
+            rate_out <= rate_out;
+            end 
+
+        //---------- Select PCLK Frequency -----------------
+        //  Gen1 : PCLK = 125 MHz
+        //  Gen2 : PCLK = 250 MHz
+        //--------------------------------------------------
+        FSM_PCLK_SEL :
+        
+            begin
+            fsm      <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_SEL : FSM_DRP_X16_START;    
+            pclk_sel <= (rate_in_reg2 == 2'd1);
+            rate_out <= rate_out;
+            end
+            
+        //---------- Start DRP x16 -------------------------
+        FSM_DRP_X16_START :
+            
+            begin
+            fsm      <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
+            pclk_sel <= pclk_sel;
+            rate_out <= rate_out;
+            end
+            
+        //---------- Wait for DRP x16 Done -----------------    
+        FSM_DRP_X16_DONE :
+        
+            begin  
+            fsm      <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
+            pclk_sel <= pclk_sel;
+            rate_out <= rate_out;
+            end      
+
+        //---------- Select Rate ---------------------------
+        FSM_RATE_SEL :
+        
+            begin
+            fsm      <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_DONE : FSM_RXPMARESETDONE;
+            pclk_sel <= pclk_sel;
+            rate_out <= rate;                               // Update [TX/RX]RATE
+            end    
+            
+        //---------- Wait for RXPMARESETDONE De-assertion --
+        FSM_RXPMARESETDONE :
+        
+            begin
+            fsm      <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;  
+            pclk_sel <= pclk_sel;
+            rate_out <= rate_out;
+            end  
+            
+        //---------- Start DRP x20 -------------------------
+        FSM_DRP_X20_START :
+            
+            begin
+            fsm      <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
+            pclk_sel <= pclk_sel;
+            rate_out <= rate_out;
+            end
+            
+        //---------- Wait for DRP x20 Done -----------------    
+        FSM_DRP_X20_DONE :
+        
+            begin  
+            fsm      <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
+            pclk_sel <= pclk_sel;
+            rate_out <= rate_out;
+            end      
+            
+        //---------- Wait for Rate Change Done ------------- 
+        FSM_RATE_DONE :
+        
+            begin
+            if (ratedone) 
+                fsm <= FSM_TXSYNC_START;
+            else      
+                fsm <= FSM_RATE_DONE;
+            
+            pclk_sel <= pclk_sel;
+            rate_out <= rate_out;
+            end      
+            
+        //---------- Start TX Sync -------------------------
+        FSM_TXSYNC_START:
+        
+            begin
+            fsm      <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
+            pclk_sel <= pclk_sel;
+            rate_out <= rate_out;
+            end
+            
+        //---------- Wait for TX Sync Done -----------------
+        FSM_TXSYNC_DONE:
+        
+            begin
+            fsm      <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
+            pclk_sel <= pclk_sel;
+            rate_out <= rate_out;
+            end        
+
+        //---------- Rate Change Done ----------------------
+        FSM_DONE :  
+          
+            begin  
+            fsm      <= FSM_IDLE;
+            pclk_sel <= pclk_sel;
+            rate_out <= rate_out;
+            end
+               
+        //---------- Default State -------------------------
+        default :
+        
+            begin
+            fsm      <= FSM_IDLE;
+            pclk_sel <= 1'd0; 
+            rate_out <= 3'd0;  
+            end
+
+        endcase
+        
+        end
+        
+end 
+
+
+
+//---------- PIPE Rate Output --------------------------------------------------
+assign RATE_PCLK_SEL     = pclk_sel;
+assign RATE_DRP_START    = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); 
+assign RATE_DRP_X16      = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
+assign RATE_RATE_OUT     = rate_out;
+assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
+assign RATE_DONE         = (fsm == FSM_DONE);
+assign RATE_IDLE         = (fsm == FSM_IDLE);
+assign RATE_FSM          = {1'd0, fsm};   
+
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_gtp_pipe_reset.v

@@ -0,0 +1,537 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_gtp_pipe_reset.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  gtp_pipe_reset.v
+//  Description  :  GTP PIPE Reset Module for 7 Series Transceiver
+//  Version      :  19.0
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- PIPE Reset Module -------------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_gtp_pipe_reset #
+(
+
+    //---------- Global ------------------------------------
+    parameter PCIE_SIM_SPEEDUP = "FALSE",                   // PCIe sim speedup 
+    parameter PCIE_LANE        = 1,                         // PCIe number of lanes
+    //---------- Local -------------------------------------
+    parameter CFG_WAIT_MAX     = 6'd63,                     // Configuration wait max
+    parameter BYPASS_RXCDRLOCK = 1                          // Bypass RXCDRLOCK
+
+)
+
+(
+
+    //---------- Input -------------------------------------
+    input                           RST_CLK,
+    input                           RST_RXUSRCLK,
+    input                           RST_DCLK,
+    input                           RST_RST_N,
+    input       [PCIE_LANE-1:0]     RST_DRP_DONE,
+    input       [PCIE_LANE-1:0]     RST_RXPMARESETDONE,
+    input                           RST_PLLLOCK,
+    input       [PCIE_LANE-1:0]     RST_RATE_IDLE,
+    input       [PCIE_LANE-1:0]     RST_RXCDRLOCK,
+    input                           RST_MMCM_LOCK,
+    input       [PCIE_LANE-1:0]     RST_RESETDONE,
+    input       [PCIE_LANE-1:0]     RST_PHYSTATUS,
+    input       [PCIE_LANE-1:0]     RST_TXSYNC_DONE,
+    
+    //---------- Output ------------------------------------
+    output                          RST_CPLLRESET,
+    output                          RST_CPLLPD,
+    output reg                      RST_DRP_START,
+    output reg                      RST_DRP_X16,
+    output                          RST_RXUSRCLK_RESET,
+    output                          RST_DCLK_RESET,
+    output                          RST_GTRESET,
+    output                          RST_USERRDY,
+    output                          RST_TXSYNC_START,
+    output                          RST_IDLE,
+    output      [ 4:0]              RST_FSM
+
+);
+
+    //---------- Input Register ----------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     drp_done_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rxpmaresetdone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             plllock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rate_idle_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rxcdrlock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             mmcm_lock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     resetdone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     phystatus_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     txsync_done_reg1;  
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     drp_done_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rxpmaresetdone_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             plllock_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rate_idle_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rxcdrlock_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             mmcm_lock_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     resetdone_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     phystatus_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     txsync_done_reg2;
+    
+    //---------- Internal Signal ---------------------------
+    reg         [ 5:0]              cfg_wait_cnt      =  6'd0;
+    
+    //---------- Output Register ---------------------------
+    reg                             pllreset          =  1'd0;
+    reg                             pllpd             =  1'd0;
+    reg                             rxusrclk_rst_reg1 =  1'd0;
+    reg                             rxusrclk_rst_reg2 =  1'd0;
+    reg                             dclk_rst_reg1     =  1'd0;
+    reg                             dclk_rst_reg2     =  1'd0;
+    reg                             gtreset           =  1'd0;
+    reg                             userrdy           =  1'd0;
+    reg         [ 4:0]              fsm               =  5'h1;                 
+   
+    //---------- FSM ---------------------------------------                                         
+    localparam                      FSM_IDLE             = 5'h0; 
+    localparam                      FSM_CFG_WAIT         = 5'h1;
+    localparam                      FSM_PLLRESET         = 5'h2; 
+    localparam                      FSM_DRP_X16_START    = 5'h3;
+    localparam                      FSM_DRP_X16_DONE     = 5'h4;   
+    localparam                      FSM_PLLLOCK          = 5'h5;
+    localparam                      FSM_GTRESET          = 5'h6;
+    localparam                      FSM_RXPMARESETDONE_1 = 5'h7; 
+    localparam                      FSM_RXPMARESETDONE_2 = 5'h8; 
+    localparam                      FSM_DRP_X20_START    = 5'h9;
+    localparam                      FSM_DRP_X20_DONE     = 5'hA;                    
+    localparam                      FSM_MMCM_LOCK        = 5'hB;  
+    localparam                      FSM_RESETDONE        = 5'hC;  
+    localparam                      FSM_TXSYNC_START     = 5'hD;
+    localparam                      FSM_TXSYNC_DONE      = 5'hE;                                 
+
+    
+
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge RST_CLK)
+begin
+
+    if (!RST_RST_N)
+        begin    
+        //---------- 1st Stage FF --------------------------  
+        drp_done_reg1       <= {PCIE_LANE{1'd0}};   
+        rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}}; 
+        plllock_reg1        <= 1'd0; 
+        rate_idle_reg1      <= {PCIE_LANE{1'd0}}; 
+        rxcdrlock_reg1      <= {PCIE_LANE{1'd0}}; 
+        mmcm_lock_reg1      <= 1'd0; 
+        resetdone_reg1      <= {PCIE_LANE{1'd0}}; 
+        phystatus_reg1      <= {PCIE_LANE{1'd0}}; 
+        txsync_done_reg1    <= {PCIE_LANE{1'd0}}; 
+        //---------- 2nd Stage FF --------------------------
+        drp_done_reg2       <= {PCIE_LANE{1'd0}};
+        rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}}; 
+        plllock_reg2        <= 1'd0; 
+        rate_idle_reg2      <= {PCIE_LANE{1'd0}}; 
+        rxcdrlock_reg2      <= {PCIE_LANE{1'd0}}; 
+        mmcm_lock_reg2      <= 1'd0;
+        resetdone_reg2      <= {PCIE_LANE{1'd0}}; 
+        phystatus_reg2      <= {PCIE_LANE{1'd0}}; 
+        txsync_done_reg2    <= {PCIE_LANE{1'd0}}; 
+        end
+    else
+        begin  
+        //---------- 1st Stage FF --------------------------   
+        drp_done_reg1       <= RST_DRP_DONE; 
+        rxpmaresetdone_reg1 <= RST_RXPMARESETDONE; 
+        plllock_reg1        <= RST_PLLLOCK;
+        rate_idle_reg1      <= RST_RATE_IDLE;
+        rxcdrlock_reg1      <= RST_RXCDRLOCK;
+        mmcm_lock_reg1      <= RST_MMCM_LOCK;
+        resetdone_reg1      <= RST_RESETDONE;
+        phystatus_reg1      <= RST_PHYSTATUS;
+        txsync_done_reg1    <= RST_TXSYNC_DONE;
+        //---------- 2nd Stage FF --------------------------
+        drp_done_reg2       <= drp_done_reg1;
+        rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
+        plllock_reg2        <= plllock_reg1;
+        rate_idle_reg2      <= rate_idle_reg1;
+        rxcdrlock_reg2      <= rxcdrlock_reg1;
+        mmcm_lock_reg2      <= mmcm_lock_reg1;
+        resetdone_reg2      <= resetdone_reg1;
+        phystatus_reg2      <= phystatus_reg1;
+        txsync_done_reg2    <= txsync_done_reg1;   
+        end
+        
+end    
+
+
+
+//---------- Configuration Reset Wait Counter ----------------------------------
+always @ (posedge RST_CLK)
+begin
+
+    if (!RST_RST_N)
+        cfg_wait_cnt <= 6'd0;
+    else
+    
+        //---------- Increment Configuration Reset Wait Counter
+        if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
+            cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
+            
+        //---------- Hold Configuration Reset Wait Counter -
+        else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
+            cfg_wait_cnt <= cfg_wait_cnt;
+            
+        //---------- Reset Configuration Reset Wait Counter 
+        else
+            cfg_wait_cnt <= 6'd0;
+        
+end 
+
+
+
+//---------- PIPE Reset FSM ----------------------------------------------------
+always @ (posedge RST_CLK)
+begin
+
+    if (!RST_RST_N)
+        begin
+        fsm      <= FSM_CFG_WAIT;
+        pllreset <= 1'd0;
+        pllpd    <= 1'd0;
+        gtreset  <= 1'd0;
+        userrdy  <= 1'd0;
+        end
+    else
+        begin
+        
+        case (fsm)
+            
+        //---------- Idle State ----------------------------
+        FSM_IDLE :
+        
+            begin
+            if (!RST_RST_N)
+                begin
+                fsm      <= FSM_CFG_WAIT;
+                pllreset <= 1'd0;
+                pllpd    <= 1'd0;
+                gtreset  <= 1'd0;
+                userrdy  <= 1'd0;
+                end
+            else
+                begin
+                fsm      <= FSM_IDLE;
+                pllreset <= pllreset;
+                pllpd    <= pllpd;
+                gtreset  <= gtreset;
+                userrdy  <= userrdy;
+                end
+            end  
+            
+        //----------  Wait for Configuration Reset Delay ---
+        FSM_CFG_WAIT :
+          
+            begin
+            fsm       <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_PLLRESET : FSM_CFG_WAIT);
+            pllreset  <= pllreset;
+            pllpd     <= pllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end 
+            
+        //---------- Hold PLL and GTP Channel in Reset ----
+        FSM_PLLRESET :
+        
+            begin
+            fsm       <= (((~plllock_reg2) && (&(~resetdone_reg2))) ? FSM_DRP_X16_START : FSM_PLLRESET);
+            pllreset  <= 1'd1;
+            pllpd     <= pllpd;
+            gtreset   <= 1'd1;
+            userrdy   <= userrdy;
+            end  
+
+        //---------- Start DRP x16 -------------------------
+        FSM_DRP_X16_START :
+            
+            begin
+            fsm       <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
+            pllreset  <= pllreset;
+            pllpd     <= pllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+            
+        //---------- Wait for DRP x16 Done -----------------    
+        FSM_DRP_X16_DONE :
+        
+            begin  
+            fsm       <= (&drp_done_reg2) ? FSM_PLLLOCK : FSM_DRP_X16_DONE;
+            pllreset  <= pllreset;
+            pllpd     <= pllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end  
+
+        //---------- Wait for PLL Lock --------------------
+        FSM_PLLLOCK :
+        
+            begin
+            fsm       <= (plllock_reg2 ? FSM_GTRESET : FSM_PLLLOCK);
+            pllreset  <= 1'd0;
+            pllpd     <= pllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+
+        //---------- Release GTRESET -----------------------
+        FSM_GTRESET :
+        
+            begin
+            fsm       <= FSM_RXPMARESETDONE_1;
+            pllreset  <= pllreset;
+            pllpd     <= pllpd;
+            gtreset   <= 1'b0;
+            userrdy   <= userrdy;
+            end
+            
+        //---------- Wait for RXPMARESETDONE Assertion -----  
+        FSM_RXPMARESETDONE_1 :
+        
+            begin
+            fsm       <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1;
+            pllreset  <= pllreset;
+            pllpd     <= pllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end  
+
+        //---------- Wait for RXPMARESETDONE De-assertion --
+        FSM_RXPMARESETDONE_2 :
+        
+            begin
+            fsm       <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2;
+            pllreset  <= pllreset;
+            pllpd     <= pllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end  
+            
+        //---------- Start DRP x20 -------------------------
+        FSM_DRP_X20_START :
+            
+            begin
+            fsm       <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
+            pllreset  <= pllreset;
+            pllpd     <= pllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+            
+        //---------- Wait for DRP x20 Done -----------------    
+        FSM_DRP_X20_DONE :
+        
+            begin  
+            fsm       <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE;
+            pllreset  <= pllreset;
+            pllpd     <= pllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end      
+
+        //---------- Wait for MMCM and RX CDR Lock ---------
+        FSM_MMCM_LOCK :
+        
+            begin  
+            if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)))
+                begin
+                fsm       <= FSM_RESETDONE;
+                pllreset  <= pllreset;
+                pllpd     <= pllpd;
+                gtreset   <= gtreset;
+                userrdy   <= 1'd1;
+                end
+            else
+                begin
+                fsm       <= FSM_MMCM_LOCK;
+                pllreset  <= pllreset;
+                pllpd     <= pllpd;
+                gtreset   <= gtreset;
+                userrdy   <= 1'd0;
+                end
+            end
+
+        //---------- Wait for [TX/RX]RESETDONE and PHYSTATUS 
+        FSM_RESETDONE :
+        
+            begin
+            fsm       <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_TXSYNC_START : FSM_RESETDONE);  
+            pllreset  <= pllreset;
+            pllpd     <= pllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+            
+        //---------- Start TX Sync -------------------------
+        FSM_TXSYNC_START :
+        
+            begin
+            fsm       <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
+            pllreset  <= pllreset;
+            pllpd     <= pllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+            
+        //---------- Wait for TX Sync Done -----------------
+        FSM_TXSYNC_DONE :
+        
+            begin
+            fsm       <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
+            pllreset  <= pllreset;
+            pllpd     <= pllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end     
+            
+        //---------- Default State -------------------------
+        default :
+        
+            begin
+            fsm       <= FSM_CFG_WAIT;
+            pllreset  <= 1'd0;
+            pllpd     <= 1'd0;
+            gtreset   <= 1'd0;
+            userrdy   <= 1'd0;
+            end
+
+        endcase
+        
+        end
+        
+end
+
+
+
+//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
+always @ (posedge RST_RXUSRCLK)
+begin
+
+    if (pllreset) 
+        begin
+        rxusrclk_rst_reg1 <= 1'd1;
+        rxusrclk_rst_reg2 <= 1'd1;
+        end
+    else
+        begin
+        rxusrclk_rst_reg1 <= 1'd0;
+        rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
+        end   
+          
+end  
+
+//---------- DCLK Reset Synchronizer -------------------------------------------
+always @ (posedge RST_DCLK)
+begin
+
+    if (fsm == FSM_CFG_WAIT)
+        begin
+        dclk_rst_reg1 <= 1'd1;
+        dclk_rst_reg2 <= dclk_rst_reg1;
+        end
+    else
+        begin
+        dclk_rst_reg1 <= 1'd0;
+        dclk_rst_reg2 <= dclk_rst_reg1;
+        end   
+          
+end  
+
+
+
+//---------- PIPE Reset Output -------------------------------------------------
+assign RST_CPLLRESET      = pllreset;
+assign RST_CPLLPD         = pllpd;
+assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
+assign RST_DCLK_RESET     = dclk_rst_reg2;
+assign RST_GTRESET        = gtreset;  
+assign RST_USERRDY        = userrdy;
+assign RST_TXSYNC_START   = (fsm == FSM_TXSYNC_START);
+assign RST_IDLE           = (fsm == FSM_IDLE);
+assign RST_FSM            = fsm;                   
+
+
+
+//--------------------------------------------------------------------------------------------------
+//  Register Output
+//--------------------------------------------------------------------------------------------------
+always @ (posedge RST_CLK)
+begin
+
+    if (!RST_RST_N) 
+        begin
+        RST_DRP_START <= 1'd0;
+        RST_DRP_X16   <= 1'd0;
+        end
+    else
+        begin
+        RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); 
+        RST_DRP_X16   <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
+        end
+        
+end  
+
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_gtx_cpllpd_ovrd.v

@@ -0,0 +1,68 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_gtx_cpllpd_ovrd.v
+// Version    : 3.3
+`timescale 1ns / 1ps
+module xdma_0_pcie2_ip_gtx_cpllpd_ovrd (                                                                                        
+    input   i_ibufds_gte2,                                                                                     
+    output  o_cpllpd_ovrd,                                                                                     
+    output  o_cpllreset_ovrd                                                                                   
+    );                                                                                                         
+    (* equivalent_register_removal="no" *)  reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;             
+    (* equivalent_register_removal="no" *)  reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF;
+    always @(posedge i_ibufds_gte2)                                                                            
+    begin                                                                                                      
+        cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};                                                              
+        cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};                                                       
+    end                                                                                                        
+    assign o_cpllpd_ovrd = cpllpd_wait[95];                                                                    
+    assign o_cpllreset_ovrd = cpllreset_wait[127];                                                             
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pcie_bram_7x.v

@@ -0,0 +1,212 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pcie_bram_7x.v
+// Version    : 3.3
+//  Description : single bram wrapper for the mb pcie block
+//                The bram A port is the write port
+//                the      B port is the read port
+//
+//
+//-----------------------------------------------------------------------------//
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_pcie_bram_7x
+  #(
+    parameter [3:0]  LINK_CAP_MAX_LINK_SPEED = 4'h1,        // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
+    parameter [5:0]  LINK_CAP_MAX_LINK_WIDTH = 6'h08,       // PCIe Link Width : 1 / 2 / 4 / 8
+    parameter IMPL_TARGET = "HARD",                         // the implementation target : HARD, SOFT
+    parameter DOB_REG = 0,                                  // 1 - use the output register;
+                                                            // 0 - don't use the output register
+    parameter WIDTH = 0                                     // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
+                                                            //                     72 - uses RAMB36SDP
+    )
+    (
+     input               user_clk_i,// user clock
+     input               reset_i,   // bram reset
+
+     input               wen_i,     // write enable
+     input [12:0]        waddr_i,   // write address
+     input [WIDTH - 1:0] wdata_i,   // write data
+
+     input               ren_i,     // read enable
+     input               rce_i,     // output register clock enable
+     input [12:0]        raddr_i,   // read address
+
+     output [WIDTH - 1:0] rdata_o   // read data
+     );
+
+   // map the address bits
+   localparam ADDR_MSB = ((WIDTH == 4)  ? 12 :
+                          (WIDTH == 9)  ? 11 :
+                          (WIDTH == 18) ? 10 :
+                          (WIDTH == 36) ?  9 :
+                                           8
+                          );
+
+   // set the width of the tied off low address bits
+   localparam ADDR_LO_BITS = ((WIDTH == 4)  ? 2 :
+                              (WIDTH == 9)  ? 3 :
+                              (WIDTH == 18) ? 4 :
+                              (WIDTH == 36) ? 5 :
+                                              0 // for WIDTH 72 use RAMB36SDP
+                              );
+
+   // map the data bits
+   localparam D_MSB =  ((WIDTH == 4)  ?  3 :
+                        (WIDTH == 9)  ?  7 :
+                        (WIDTH == 18) ? 15 :
+                        (WIDTH == 36) ? 31 :
+                                        63
+                        );
+
+   // map the data parity bits
+   localparam DP_LSB =  D_MSB + 1;
+
+   localparam DP_MSB =  ((WIDTH == 4)  ? 4 :
+                         (WIDTH == 9)  ? 8 :
+                         (WIDTH == 18) ? 17 :
+                         (WIDTH == 36) ? 35 :
+                                         71
+                        );
+
+   localparam DPW = DP_MSB - DP_LSB + 1;
+   localparam WRITE_MODE = ((WIDTH == 72) && (!((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)))) ? "WRITE_FIRST" :
+                           ((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ? "WRITE_FIRST" : "NO_CHANGE";
+
+   localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6";
+   localparam BRAM_SIZE = "36Kb";
+
+   localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ?
+                            ((WIDTH <= 9) ? 1 :
+                             (WIDTH > 9 && WIDTH <= 18) ? 2 :
+                             (WIDTH > 18 && WIDTH <= 36) ? 4 :
+                             (WIDTH > 36 && WIDTH <= 72) ? 8 :
+                             (BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8;
+
+   //synthesis translate_off
+   initial begin
+      //$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
+      //          $time, DOB_REG,   WIDTH,    ADDR_MSB,    ADDR_LO_BITS,    DP_MSB,    DP_LSB,    D_MSB);
+
+      case (WIDTH)
+        4,9,18,36,72:;
+        default:
+          begin
+             $display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
+             $finish;
+          end
+      endcase // case (WIDTH)
+   end
+   //synthesis translate_on
+
+   generate
+   if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp
+        BRAM_SDP_MACRO #(
+               .DEVICE        (DEVICE),
+               .BRAM_SIZE     (BRAM_SIZE),
+               .DO_REG        (DOB_REG),
+               .READ_WIDTH    (WIDTH),
+               .WRITE_WIDTH   (WIDTH),
+               .WRITE_MODE    (WRITE_MODE)
+               )
+        ramb36sdp(
+               .DO             (rdata_o[WIDTH-1:0]),
+               .DI             (wdata_i[WIDTH-1:0]),
+               .RDADDR         (raddr_i[ADDR_MSB:0]),
+               .RDCLK          (user_clk_i),
+               .RDEN           (ren_i),
+               .REGCE          (rce_i),
+               .RST            (reset_i),
+               .WE             ({WE_WIDTH{1'b1}}),
+               .WRADDR         (waddr_i[ADDR_MSB:0]),
+               .WRCLK          (user_clk_i),
+               .WREN           (wen_i)
+               );
+
+    end  // block: use_sdp
+    else if (WIDTH <= 36) begin : use_tdp
+    // use RAMB36's if the width is 4, 9, 18, or 36
+        BRAM_TDP_MACRO #(
+               .DEVICE        (DEVICE),
+               .BRAM_SIZE     (BRAM_SIZE),
+               .DOA_REG       (0),
+               .DOB_REG       (DOB_REG),
+               .READ_WIDTH_A  (WIDTH),
+               .READ_WIDTH_B  (WIDTH),
+               .WRITE_WIDTH_A (WIDTH),
+               .WRITE_WIDTH_B (WIDTH),
+               .WRITE_MODE_A  (WRITE_MODE)
+               )
+        ramb36(
+               .DOA            (),
+               .DOB            (rdata_o[WIDTH-1:0]),
+               .ADDRA          (waddr_i[ADDR_MSB:0]),
+               .ADDRB          (raddr_i[ADDR_MSB:0]),
+               .CLKA           (user_clk_i),
+               .CLKB           (user_clk_i),
+               .DIA            (wdata_i[WIDTH-1:0]),
+               .DIB            ({WIDTH{1'b0}}),
+               .ENA            (wen_i),
+               .ENB            (ren_i),
+               .REGCEA         (1'b0),
+               .REGCEB         (rce_i),
+               .RSTA           (reset_i),
+               .RSTB           (reset_i),
+               .WEA            ({WE_WIDTH{1'b1}}),
+               .WEB            ({WE_WIDTH{1'b0}})
+               );
+   end // block: use_tdp
+   endgenerate
+
+endmodule // pcie_bram_7x
+

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pcie_bram_top_7x.v

@@ -0,0 +1,184 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pcie_bram_top_7x.v
+// Version    : 3.3
+//  Description : bram wrapper for Tx and Rx
+//                given the pcie block attributes calculate the number of brams
+//                and pipeline stages and instantiate the brams
+//
+//  Hierarchy:
+//            pcie_bram_top    top level
+//              pcie_brams     pcie_bram instantiations,
+//                             pipeline stages (if any),
+//                             address decode logic (if any),
+//                             datapath muxing (if any)
+//                pcie_bram    bram library cell wrapper
+//                             the pcie_bram module can have a paramter that
+//                             specifies the family (V6, V5, V4)
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_pcie_bram_top_7x
+#(
+  parameter IMPL_TARGET               = "HARD",        // the implementation target : HARD, SOFT
+  parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,         // MPS Supported : 0 - 128 B, 1 - 256 B, 2 - 512 B, 3 - 1024 B
+  parameter [3:0]  LINK_CAP_MAX_LINK_SPEED = 4'h1,     // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
+  parameter [5:0]  LINK_CAP_MAX_LINK_WIDTH = 6'h08,    // PCIe Link Width : 1 / 2 / 4 / 8
+
+  parameter VC0_TX_LASTPACKET         = 31,            // Number of Packets in Transmit
+  parameter TLM_TX_OVERHEAD           = 24,            // Overhead Bytes for Packets (Transmit)
+  parameter TL_TX_RAM_RADDR_LATENCY   = 1,             // BRAM Read Address Latency (Transmit)
+  parameter TL_TX_RAM_RDATA_LATENCY   = 2,             // BRAM Read Data Latency (Transmit)
+  parameter TL_TX_RAM_WRITE_LATENCY   = 1,             // BRAM Write Latency (Transmit)
+
+  parameter VC0_RX_RAM_LIMIT          = 'h1FFF,        // RAM Size (Receive)
+  parameter TL_RX_RAM_RADDR_LATENCY   = 1,             // BRAM Read Address Latency (Receive)
+  parameter TL_RX_RAM_RDATA_LATENCY   = 2,             // BRAM Read Data Latency (Receive)
+  parameter TL_RX_RAM_WRITE_LATENCY   = 1              // BRAM Write Latency (Receive)
+)
+(
+  input          user_clk_i,                  // Clock input
+  input          reset_i,                     // Reset input
+
+  input          mim_tx_wen,                  // Write Enable for Transmit path BRAM
+  input  [12:0]  mim_tx_waddr,                // Write Address for Transmit path BRAM
+  input  [71:0]  mim_tx_wdata,                // Write Data for Transmit path BRAM
+  input          mim_tx_ren,                  // Read Enable for Transmit path BRAM
+  input          mim_tx_rce,                  // Read Output Register Clock Enable for Transmit path BRAM
+  input  [12:0]  mim_tx_raddr,                // Read Address for Transmit path BRAM
+  output [71:0]  mim_tx_rdata,                // Read Data for Transmit path BRAM
+
+  input          mim_rx_wen,                  // Write Enable for Receive path BRAM
+  input  [12:0]  mim_rx_waddr,                // Write Enable for Receive path BRAM
+  input  [71:0]  mim_rx_wdata,                // Write Enable for Receive path BRAM
+  input          mim_rx_ren,                  // Read Enable for Receive path BRAM
+  input          mim_rx_rce,                  // Read Output Register Clock Enable for Receive path BRAM
+  input  [12:0]  mim_rx_raddr,                // Read Address for Receive path BRAM
+  output [71:0]  mim_rx_rdata                 // Read Data for Receive path BRAM
+);
+
+  // TX calculations
+  localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
+                          (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
+                          (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
+                                                                1024 );
+
+  localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
+
+  localparam ROWS_TX = 1;
+  localparam COLS_TX = ((BYTES_TX <= 4096) ?  1 :
+                        (BYTES_TX <= 8192) ?  2 :
+                        (BYTES_TX <= 16384) ? 4 :
+                        (BYTES_TX <= 32768) ? 8 :
+                                             18
+                       );
+
+  // RX calculations
+  localparam ROWS_RX = 1;
+
+  localparam COLS_RX = ((VC0_RX_RAM_LIMIT < 'h0200) ? 1 :
+                        (VC0_RX_RAM_LIMIT < 'h0400) ? 2 :
+                        (VC0_RX_RAM_LIMIT < 'h0800) ? 4 :
+                        (VC0_RX_RAM_LIMIT < 'h1000) ? 8 :
+                                                 18
+                       );
+
+  initial begin
+     $display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
+     $display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
+  end
+
+xdma_0_pcie2_ip_pcie_brams_7x #(
+    .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
+    .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
+    .IMPL_TARGET             ( IMPL_TARGET ),
+    .NUM_BRAMS               ( COLS_TX ),
+    .RAM_RADDR_LATENCY       ( TL_TX_RAM_RADDR_LATENCY ),
+    .RAM_RDATA_LATENCY       ( TL_TX_RAM_RDATA_LATENCY ),
+    .RAM_WRITE_LATENCY       ( TL_TX_RAM_WRITE_LATENCY )
+  ) 
+  pcie_brams_tx (
+    .user_clk_i ( user_clk_i ),
+    .reset_i    ( reset_i ),
+    .waddr      ( mim_tx_waddr ),
+    .wen        ( mim_tx_wen ),
+    .ren        ( mim_tx_ren ),
+    .rce        ( mim_tx_rce ),
+    .wdata      ( mim_tx_wdata ),
+    .raddr      ( mim_tx_raddr ),
+    .rdata      ( mim_tx_rdata )
+  );
+
+xdma_0_pcie2_ip_pcie_brams_7x #(
+    .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
+    .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
+    .IMPL_TARGET             ( IMPL_TARGET ),
+    .NUM_BRAMS               ( COLS_RX ),
+    .RAM_RADDR_LATENCY       ( TL_RX_RAM_RADDR_LATENCY ),
+    .RAM_RDATA_LATENCY       ( TL_RX_RAM_RDATA_LATENCY ),
+    .RAM_WRITE_LATENCY       ( TL_RX_RAM_WRITE_LATENCY )
+  ) pcie_brams_rx (
+    .user_clk_i ( user_clk_i ),
+    .reset_i    ( reset_i ),
+    .waddr      ( mim_rx_waddr ),
+    .wen        ( mim_rx_wen ),
+    .ren        ( mim_rx_ren ),
+    .rce        ( mim_rx_rce ),
+    .wdata      ( mim_rx_wdata ),
+    .raddr      ( mim_rx_raddr ),
+    .rdata      ( mim_rx_rdata )
+   );
+
+endmodule // pcie_bram_top
+

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pcie_brams_7x.v

@@ -0,0 +1,296 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pcie_brams_7x.v
+// Version    : 3.3
+//  Description : pcie bram wrapper
+//                arrange and connect brams
+//                implement address decoding, datapath muxing and pipeline stages
+//
+//                banks of brams are used for 1,2,4,8,18 brams
+//                brams are stacked for other values of NUM_BRAMS
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_pcie_brams_7x
+#(
+  parameter [3:0]  LINK_CAP_MAX_LINK_SPEED = 4'h1,        // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
+  parameter [5:0]  LINK_CAP_MAX_LINK_WIDTH = 6'h08,       // PCIe Link Width : 1 / 2 / 4 / 8
+  parameter IMPL_TARGET             = "HARD",             // the implementation target : HARD, SOFT
+
+  // the number of BRAMs to use
+  // supported values are:
+  // 1,2,4,8,18
+  parameter NUM_BRAMS               = 0,
+
+  // BRAM read address latency
+  //
+  // value     meaning
+  // ====================================================
+  //   0       BRAM read address port sample
+  //   1       BRAM read address port sample and a pipeline stage on the address port
+  parameter RAM_RADDR_LATENCY   = 1,
+
+  // BRAM read data latency
+  //
+  // value     meaning
+  // ====================================================
+  //   1       no BRAM OREG
+  //   2       use BRAM OREG
+  //   3       use BRAM OREG and a pipeline stage on the data port
+  parameter RAM_RDATA_LATENCY   = 1,
+
+  // BRAM write latency
+  // The BRAM write port is synchronous
+  //
+  // value     meaning
+  // ====================================================
+  //   0       BRAM write port sample
+  //   1       BRAM write port sample plus pipeline stage
+  parameter RAM_WRITE_LATENCY       = 1,
+  parameter TCQ           = 1 // synthesis warning removed: parameter declaration becomes local
+)
+(
+  input          user_clk_i,
+  input          reset_i,
+
+  input          wen,
+  input  [12:0]  waddr,
+  input  [71:0]  wdata,
+  input          ren,
+  input          rce,
+  input  [12:0]  raddr,
+  output [71:0]  rdata
+  );
+
+  // turn on the bram output register
+  localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
+
+  // calculate the data width of the individual brams
+  localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :
+                            (NUM_BRAMS == 2) ? 36 :
+                            (NUM_BRAMS == 4) ? 18 :
+                            (NUM_BRAMS == 8) ?  9 :
+                                                4
+                           );
+
+//  parameter TCQ           = 1;
+
+  wire        wen_int;
+  wire [12:0] waddr_int;
+  wire [71:0] wdata_int;
+
+  wire        ren_int;
+  wire [12:0] raddr_int;
+  wire [71:0] rdata_int;
+
+  //synthesis translate_off
+  initial
+  begin
+    $display("[%t] %m NUM_BRAMS %0d  DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
+    $time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);
+
+    case (NUM_BRAMS)
+      1,2,4,8,18:;
+      default:
+        begin
+           $display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
+           $finish;
+        end
+    endcase // case(NUM_BRAMS)
+
+    case (RAM_RADDR_LATENCY)
+      0,1:;
+      default:
+        begin
+           $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
+           $finish;
+        end
+    endcase // case (RAM_RADDR_LATENCY)
+
+    case (RAM_RDATA_LATENCY)
+      1,2,3:;
+      default:
+        begin
+           $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
+           $finish;
+        end
+    endcase // case (RAM_RDATA_LATENCY)
+
+    case (RAM_WRITE_LATENCY)
+      0,1:;
+      default:
+        begin
+           $display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
+           $finish;
+        end
+    endcase // case(RAM_WRITE_LATENCY)
+
+  end
+  //synthesis translate_on
+
+  // model the delays for ram write latency
+
+  generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
+   reg        wen_q;
+   reg [12:0] waddr_q;
+   reg [71:0] wdata_q;
+
+    always @(posedge user_clk_i) begin
+      if (reset_i)
+      begin
+        wen_q   <= #TCQ 1'b0;
+        waddr_q <= #TCQ 13'b0;
+      // Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
+      //  wdata_q <= #TCQ 72'b0;
+      end 
+      else 
+      begin
+        wen_q   <= #TCQ wen;
+        waddr_q <= #TCQ waddr;
+        wdata_q <= #TCQ wdata;
+      end
+    end
+
+    assign wen_int   = wen_q;
+    assign waddr_int = waddr_q;
+    assign wdata_int = wdata_q;
+  end // if (RAM_WRITE_LATENCY == 1)
+
+  else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
+    assign wen_int   = wen;
+    assign waddr_int = waddr;
+    assign wdata_int = wdata;
+  end
+  endgenerate
+
+  // model the delays for ram read latency
+
+  generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
+    reg        ren_q;
+    reg [12:0] raddr_q;
+
+    always @(posedge user_clk_i) begin
+      if (reset_i)
+      begin
+        ren_q   <= #TCQ 1'b0;
+        raddr_q <= #TCQ 13'b0;
+      end
+      else
+      begin
+        ren_q   <= #TCQ ren;
+        raddr_q <= #TCQ raddr;
+      end // else: !if(reset_i)
+    end
+
+    assign ren_int   = ren_q;
+    assign raddr_int = raddr_q;
+  end // block: rd_lat_addr_2
+
+  else begin : raddr_lat_1
+    assign ren_int   = ren;
+    assign raddr_int = raddr;
+  end
+  endgenerate
+
+  generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
+    reg [71:0] rdata_q;
+
+    always @(posedge user_clk_i) begin
+      // Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
+      //if (reset_i)
+      //begin
+      //  rdata_q <= #TCQ 72'b0;
+      //end
+      //else
+      //begin
+        rdata_q <= #TCQ rdata_int;
+      //end // else: !if(reset_i)
+    end
+
+    assign rdata     = rdata_q;
+
+  end // block: rd_lat_data_3
+
+  else begin : rdata_lat_1_2
+    assign rdata     = rdata_int;
+  end
+  endgenerate
+
+  // instantiate the brams
+  generate
+    genvar ii;
+    for (ii = 0; ii < NUM_BRAMS; ii = ii + 1) begin : brams
+xdma_0_pcie2_ip_pcie_bram_7x #(
+        .LINK_CAP_MAX_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
+        .LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
+        .IMPL_TARGET      (IMPL_TARGET),
+        .DOB_REG          (DOB_REG),
+        .WIDTH            (WIDTH)
+      )
+      ram (
+        .user_clk_i(user_clk_i),
+        .reset_i(reset_i),
+        .wen_i(wen_int),
+        .waddr_i(waddr_int),
+        .wdata_i(wdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
+        .ren_i(ren_int),
+        .raddr_i(raddr_int),
+        .rdata_o(rdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
+        .rce_i(rce)
+      );
+    end
+  endgenerate
+
+endmodule // pcie_brams_7x
+

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pcie_pipe_lane.v

@@ -0,0 +1,328 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pcie_pipe_lane.v
+// Version    : 3.3
+//
+// Description: PIPE per lane module for 7-Series PCIe Block
+//
+//
+//
+//--------------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_pcie_pipe_lane #
+(
+    parameter        PIPE_PIPELINE_STAGES = 0,    // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
+    parameter TCQ  = 1 // synthesis warning solved : parameter declaration becomes local
+)
+(
+    output  wire [ 1:0] pipe_rx_char_is_k_o     ,    // Pipelined PIPE Rx Char Is K
+    output  wire [15:0] pipe_rx_data_o          ,    // Pipelined PIPE Rx Data
+    output  wire        pipe_rx_valid_o         ,    // Pipelined PIPE Rx Data Valid
+    output  wire        pipe_rx_chanisaligned_o ,    // Pipelined PIPE Rx Chan Is Aligned
+    output  wire [ 2:0] pipe_rx_status_o        ,    // Pipelined PIPE Rx Status
+    output  wire        pipe_rx_phy_status_o    ,    // Pipelined PIPE Rx Phy Status
+    output  wire        pipe_rx_elec_idle_o     ,    // Pipelined PIPE Rx Electrical Idle
+    input   wire        pipe_rx_polarity_i      ,    // PIPE Rx Polarity
+    input   wire        pipe_tx_compliance_i    ,    // PIPE Tx Compliance
+    input   wire [ 1:0] pipe_tx_char_is_k_i     ,    // PIPE Tx Char Is K
+    input   wire [15:0] pipe_tx_data_i          ,    // PIPE Tx Data
+    input   wire        pipe_tx_elec_idle_i     ,    // PIPE Tx Electrical Idle
+    input   wire [ 1:0] pipe_tx_powerdown_i     ,    // PIPE Tx Powerdown
+
+    input  wire [ 1:0]  pipe_rx_char_is_k_i     ,    // PIPE Rx Char Is K
+    input  wire [15:0]  pipe_rx_data_i          ,    // PIPE Rx Data
+    input  wire         pipe_rx_valid_i         ,    // PIPE Rx Data Valid
+    input  wire         pipe_rx_chanisaligned_i ,    // PIPE Rx Chan Is Aligned
+    input  wire [ 2:0]  pipe_rx_status_i        ,    // PIPE Rx Status
+    input  wire         pipe_rx_phy_status_i    ,    // PIPE Rx Phy Status
+    input  wire         pipe_rx_elec_idle_i     ,    // PIPE Rx Electrical Idle
+    output wire         pipe_rx_polarity_o      ,    // Pipelined PIPE Rx Polarity
+    output wire         pipe_tx_compliance_o    ,    // Pipelined PIPE Tx Compliance
+    output wire [ 1:0]  pipe_tx_char_is_k_o     ,    // Pipelined PIPE Tx Char Is K
+    output wire [15:0]  pipe_tx_data_o          ,    // Pipelined PIPE Tx Data
+    output wire         pipe_tx_elec_idle_o     ,    // Pipelined PIPE Tx Electrical Idle
+    output wire [ 1:0]  pipe_tx_powerdown_o     ,    // Pipelined PIPE Tx Powerdown
+
+    input   wire        pipe_clk                ,    // PIPE Clock
+    input   wire        rst_n                        // Reset
+);
+
+  //******************************************************************//
+  // Reality check.                                                   //
+  //******************************************************************//
+
+//    parameter TCQ  = 1;      // clock to out delay model
+
+    generate
+
+    if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
+
+        assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i;
+        assign pipe_rx_data_o = pipe_rx_data_i;
+        assign pipe_rx_valid_o = pipe_rx_valid_i;
+        assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_i;
+        assign pipe_rx_status_o = pipe_rx_status_i;
+        assign pipe_rx_phy_status_o = pipe_rx_phy_status_i;
+        assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i;
+
+        assign pipe_rx_polarity_o = pipe_rx_polarity_i;
+        assign pipe_tx_compliance_o = pipe_tx_compliance_i;
+        assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i;
+        assign pipe_tx_data_o = pipe_tx_data_i;
+        assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i;
+        assign pipe_tx_powerdown_o = pipe_tx_powerdown_i;
+
+    end // if (PIPE_PIPELINE_STAGES == 0)
+    else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
+
+    reg [ 1:0]          pipe_rx_char_is_k_q     ;
+    reg [15:0]          pipe_rx_data_q          ;
+    reg                 pipe_rx_valid_q         ;
+    reg                 pipe_rx_chanisaligned_q ;
+    reg [ 2:0]          pipe_rx_status_q        ;
+    reg                 pipe_rx_phy_status_q    ;
+    reg                 pipe_rx_elec_idle_q     ;
+
+    reg                 pipe_rx_polarity_q      ;
+    reg                 pipe_tx_compliance_q    ;
+    reg [ 1:0]          pipe_tx_char_is_k_q     ;
+    reg [15:0]          pipe_tx_data_q          ;
+    reg                 pipe_tx_elec_idle_q     ;
+    reg [ 1:0]          pipe_tx_powerdown_q     ;
+
+        always @(posedge pipe_clk) begin
+
+        if (rst_n) 
+        begin
+
+            pipe_rx_char_is_k_q <= #TCQ 0;
+            pipe_rx_data_q <= #TCQ 0;
+            pipe_rx_valid_q <= #TCQ 0;
+            pipe_rx_chanisaligned_q <= #TCQ 0;
+            pipe_rx_status_q <= #TCQ 0;
+            pipe_rx_phy_status_q <= #TCQ 0;
+            pipe_rx_elec_idle_q <= #TCQ 0;
+
+            pipe_rx_polarity_q <= #TCQ 0;
+            pipe_tx_compliance_q <= #TCQ 0;
+            pipe_tx_char_is_k_q <= #TCQ 0;
+            pipe_tx_data_q <= #TCQ 0;
+            pipe_tx_elec_idle_q <= #TCQ 1'b1;
+            pipe_tx_powerdown_q <= #TCQ 2'b10;
+
+        end
+        else 
+        begin
+
+            pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;
+            pipe_rx_data_q <= #TCQ pipe_rx_data_i;
+            pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;
+            pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;
+            pipe_rx_status_q <= #TCQ pipe_rx_status_i;
+            pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;
+            pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;
+
+            pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;
+            pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;
+            pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;
+            pipe_tx_data_q <= #TCQ pipe_tx_data_i;
+            pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;
+            pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;
+
+          end
+
+        end
+
+        assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q;
+        assign pipe_rx_data_o = pipe_rx_data_q;
+        assign pipe_rx_valid_o = pipe_rx_valid_q;
+        assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_q;
+        assign pipe_rx_status_o = pipe_rx_status_q;
+        assign pipe_rx_phy_status_o = pipe_rx_phy_status_q;
+        assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q;
+
+        assign pipe_rx_polarity_o = pipe_rx_polarity_q;
+        assign pipe_tx_compliance_o = pipe_tx_compliance_q;
+        assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q;
+        assign pipe_tx_data_o = pipe_tx_data_q;
+        assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q;
+        assign pipe_tx_powerdown_o = pipe_tx_powerdown_q;
+
+    end // if (PIPE_PIPELINE_STAGES == 1)
+    else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
+
+    reg [ 1:0]          pipe_rx_char_is_k_q     ;
+    reg [15:0]          pipe_rx_data_q          ;
+    reg                 pipe_rx_valid_q         ;
+    reg                 pipe_rx_chanisaligned_q ;
+    reg [ 2:0]          pipe_rx_status_q        ;
+    reg                 pipe_rx_phy_status_q    ;
+    reg                 pipe_rx_elec_idle_q     ;
+
+    reg                 pipe_rx_polarity_q      ;
+    reg                 pipe_tx_compliance_q    ;
+    reg [ 1:0]          pipe_tx_char_is_k_q     ;
+    reg [15:0]          pipe_tx_data_q          ;
+    reg                 pipe_tx_elec_idle_q     ;
+    reg [ 1:0]          pipe_tx_powerdown_q     ;
+
+    reg [ 1:0]          pipe_rx_char_is_k_qq    ;
+    reg [15:0]          pipe_rx_data_qq         ;
+    reg                 pipe_rx_valid_qq        ;
+    reg                 pipe_rx_chanisaligned_qq;
+    reg [ 2:0]          pipe_rx_status_qq       ;
+    reg                 pipe_rx_phy_status_qq   ;
+    reg                 pipe_rx_elec_idle_qq    ;
+
+    reg                 pipe_rx_polarity_qq     ;
+    reg                 pipe_tx_compliance_qq   ;
+    reg [ 1:0]          pipe_tx_char_is_k_qq    ;
+    reg [15:0]          pipe_tx_data_qq         ;
+    reg                 pipe_tx_elec_idle_qq    ;
+    reg [ 1:0]          pipe_tx_powerdown_qq    ;
+
+        always @(posedge pipe_clk) begin
+
+        if (rst_n) 
+        begin
+
+            pipe_rx_char_is_k_q <= #TCQ 0;
+            pipe_rx_data_q <= #TCQ 0;
+            pipe_rx_valid_q <= #TCQ 0;
+            pipe_rx_chanisaligned_q <= #TCQ 0;
+            pipe_rx_status_q <= #TCQ 0;
+            pipe_rx_phy_status_q <= #TCQ 0;
+            pipe_rx_elec_idle_q <= #TCQ 0;
+
+            pipe_rx_polarity_q <= #TCQ 0;
+            pipe_tx_compliance_q <= #TCQ 0;
+            pipe_tx_char_is_k_q <= #TCQ 0;
+            pipe_tx_data_q <= #TCQ 0;
+            pipe_tx_elec_idle_q <= #TCQ 1'b1;
+            pipe_tx_powerdown_q <= #TCQ 2'b10;
+
+            pipe_rx_char_is_k_qq <= #TCQ 0;
+            pipe_rx_data_qq <= #TCQ 0;
+            pipe_rx_valid_qq <= #TCQ 0;
+            pipe_rx_chanisaligned_qq <= #TCQ 0;
+            pipe_rx_status_qq <= #TCQ 0;
+            pipe_rx_phy_status_qq <= #TCQ 0;
+            pipe_rx_elec_idle_qq <= #TCQ 0;
+
+            pipe_rx_polarity_qq <= #TCQ 0;
+            pipe_tx_compliance_qq <= #TCQ 0;
+            pipe_tx_char_is_k_qq <= #TCQ 0;
+            pipe_tx_data_qq <= #TCQ 0;
+            pipe_tx_elec_idle_qq <= #TCQ 1'b1;
+            pipe_tx_powerdown_qq <= #TCQ 2'b10;
+
+        end 
+        else 
+        begin
+
+            pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;
+            pipe_rx_data_q <= #TCQ pipe_rx_data_i;
+            pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;
+            pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;
+            pipe_rx_status_q <= #TCQ pipe_rx_status_i;
+            pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;
+            pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;
+
+            pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;
+            pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;
+            pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;
+            pipe_tx_data_q <= #TCQ pipe_tx_data_i;
+            pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;
+            pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;
+
+            pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q;
+            pipe_rx_data_qq <= #TCQ pipe_rx_data_q;
+            pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q;
+            pipe_rx_chanisaligned_qq <= #TCQ pipe_rx_chanisaligned_q;
+            pipe_rx_status_qq <= #TCQ pipe_rx_status_q;
+            pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q;
+            pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q;
+
+            pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q;
+            pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q;
+            pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q;
+            pipe_tx_data_qq <= #TCQ pipe_tx_data_q;
+            pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q;
+            pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q;
+
+          end
+
+        end
+
+        assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq;
+        assign pipe_rx_data_o = pipe_rx_data_qq;
+        assign pipe_rx_valid_o = pipe_rx_valid_qq;
+        assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_qq;
+        assign pipe_rx_status_o = pipe_rx_status_qq;
+        assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq;
+        assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq;
+
+        assign pipe_rx_polarity_o = pipe_rx_polarity_qq;
+        assign pipe_tx_compliance_o = pipe_tx_compliance_qq;
+        assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq;
+        assign pipe_tx_data_o = pipe_tx_data_qq;
+        assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq;
+        assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq;
+
+    end // if (PIPE_PIPELINE_STAGES == 2)
+
+    endgenerate
+
+endmodule
+

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pcie_pipe_misc.v

@@ -0,0 +1,219 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pcie_pipe_misc.v
+// Version    : 3.3
+//
+// Description: Misc PIPE module for 7-Series PCIe Block
+//
+//
+//
+//--------------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_pcie_pipe_misc #
+(
+    parameter        PIPE_PIPELINE_STAGES = 0,    // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
+    parameter TCQ  = 1 // synthesis warning solved: parameter declaration becomes local
+)
+(
+
+    input   wire        pipe_tx_rcvr_det_i       ,     // PIPE Tx Receiver Detect
+    input   wire        pipe_tx_reset_i          ,     // PIPE Tx Reset
+    input   wire        pipe_tx_rate_i           ,     // PIPE Tx Rate
+    input   wire        pipe_tx_deemph_i         ,     // PIPE Tx Deemphasis
+    input   wire [2:0]  pipe_tx_margin_i         ,     // PIPE Tx Margin
+    input   wire        pipe_tx_swing_i          ,     // PIPE Tx Swing
+
+    output  wire        pipe_tx_rcvr_det_o       ,     // Pipelined PIPE Tx Receiver Detect
+    output  wire        pipe_tx_reset_o          ,     // Pipelined PIPE Tx Reset
+    output  wire        pipe_tx_rate_o           ,     // Pipelined PIPE Tx Rate
+    output  wire        pipe_tx_deemph_o         ,     // Pipelined PIPE Tx Deemphasis
+    output  wire [2:0]  pipe_tx_margin_o         ,     // Pipelined PIPE Tx Margin
+    output  wire        pipe_tx_swing_o          ,     // Pipelined PIPE Tx Swing
+
+    input   wire        pipe_clk                ,      // PIPE Clock
+    input   wire        rst_n                          // Reset
+);
+
+//******************************************************************//
+// Reality check.                                                   //
+//******************************************************************//
+
+//    parameter TCQ  = 1;      // clock to out delay model
+
+    generate
+
+    if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
+
+        assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
+        assign pipe_tx_reset_o  = pipe_tx_reset_i;
+        assign pipe_tx_rate_o = pipe_tx_rate_i;
+        assign pipe_tx_deemph_o = pipe_tx_deemph_i;
+        assign pipe_tx_margin_o = pipe_tx_margin_i;
+        assign pipe_tx_swing_o = pipe_tx_swing_i;
+
+    end // if (PIPE_PIPELINE_STAGES == 0)
+    else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
+
+    reg                pipe_tx_rcvr_det_q       ;
+    reg                pipe_tx_reset_q          ;
+    reg                pipe_tx_rate_q           ;
+    reg                pipe_tx_deemph_q         ;
+    reg [2:0]          pipe_tx_margin_q         ;
+    reg                pipe_tx_swing_q          ;
+
+        always @(posedge pipe_clk) begin
+
+        if (rst_n)
+        begin
+
+            pipe_tx_rcvr_det_q <= #TCQ 0;
+            pipe_tx_reset_q  <= #TCQ 1'b1;
+            pipe_tx_rate_q <= #TCQ 0;
+            pipe_tx_deemph_q <= #TCQ 1'b1;
+            pipe_tx_margin_q <= #TCQ 0;
+            pipe_tx_swing_q <= #TCQ 0;
+
+        end
+        else
+        begin
+
+            pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
+            pipe_tx_reset_q  <= #TCQ pipe_tx_reset_i;
+            pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
+            pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
+            pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
+            pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
+
+          end
+
+        end
+
+        assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
+        assign pipe_tx_reset_o  = pipe_tx_reset_q;
+        assign pipe_tx_rate_o = pipe_tx_rate_q;
+        assign pipe_tx_deemph_o = pipe_tx_deemph_q;
+        assign pipe_tx_margin_o = pipe_tx_margin_q;
+        assign pipe_tx_swing_o = pipe_tx_swing_q;
+
+    end // if (PIPE_PIPELINE_STAGES == 1)
+    else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
+
+    reg                pipe_tx_rcvr_det_q       ;
+    reg                pipe_tx_reset_q          ;
+    reg                pipe_tx_rate_q           ;
+    reg                pipe_tx_deemph_q         ;
+    reg [2:0]          pipe_tx_margin_q         ;
+    reg                pipe_tx_swing_q          ;
+
+    reg                pipe_tx_rcvr_det_qq      ;
+    reg                pipe_tx_reset_qq         ;
+    reg                pipe_tx_rate_qq          ;
+    reg                pipe_tx_deemph_qq        ;
+    reg [2:0]          pipe_tx_margin_qq        ;
+    reg                pipe_tx_swing_qq         ;
+
+        always @(posedge pipe_clk) begin
+
+        if (rst_n)
+        begin
+
+            pipe_tx_rcvr_det_q <= #TCQ 0;
+            pipe_tx_reset_q  <= #TCQ 1'b1;
+            pipe_tx_rate_q <= #TCQ 0;
+            pipe_tx_deemph_q <= #TCQ 1'b1;
+            pipe_tx_margin_q <= #TCQ 0;
+            pipe_tx_swing_q <= #TCQ 0;
+
+            pipe_tx_rcvr_det_qq <= #TCQ 0;
+            pipe_tx_reset_qq  <= #TCQ 1'b1;
+            pipe_tx_rate_qq <= #TCQ 0;
+            pipe_tx_deemph_qq <= #TCQ 1'b1;
+            pipe_tx_margin_qq <= #TCQ 0;
+            pipe_tx_swing_qq <= #TCQ 0;
+
+        end
+        else
+        begin
+
+            pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
+            pipe_tx_reset_q  <= #TCQ pipe_tx_reset_i;
+            pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
+            pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
+            pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
+            pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
+
+            pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
+            pipe_tx_reset_qq  <= #TCQ pipe_tx_reset_q;
+            pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
+            pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
+            pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
+            pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
+
+          end
+
+        end
+
+        assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
+        assign pipe_tx_reset_o  = pipe_tx_reset_qq;
+        assign pipe_tx_rate_o = pipe_tx_rate_qq;
+        assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
+        assign pipe_tx_margin_o = pipe_tx_margin_qq;
+        assign pipe_tx_swing_o = pipe_tx_swing_qq;
+
+    end // if (PIPE_PIPELINE_STAGES == 2)
+
+    endgenerate
+
+endmodule
+

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pcie_pipe_pipeline.v

@@ -0,0 +1,798 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pcie_pipe_pipeline.v
+// Version    : 3.3
+//
+// Description: PIPE module for Virtex7 PCIe Block
+//
+//
+//
+//--------------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_pcie_pipe_pipeline #
+(
+  parameter        LINK_CAP_MAX_LINK_WIDTH = 8,
+  parameter        PIPE_PIPELINE_STAGES = 0    // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
+)
+(
+  // Pipe Per-Link Signals
+  input   wire        pipe_tx_rcvr_det_i       ,
+  input   wire        pipe_tx_reset_i          ,
+  input   wire        pipe_tx_rate_i           ,
+  input   wire        pipe_tx_deemph_i         ,
+  input   wire [2:0]  pipe_tx_margin_i         ,
+  input   wire        pipe_tx_swing_i          ,
+
+  output  wire        pipe_tx_rcvr_det_o       ,
+  output  wire        pipe_tx_reset_o          ,
+  output  wire        pipe_tx_rate_o           ,
+  output  wire        pipe_tx_deemph_o         ,
+  output  wire [2:0]  pipe_tx_margin_o         ,
+  output  wire        pipe_tx_swing_o          ,
+
+  // Pipe Per-Lane Signals - Lane 0
+  output  wire [ 1:0] pipe_rx0_char_is_k_o     ,
+  output  wire [15:0] pipe_rx0_data_o          ,
+  output  wire        pipe_rx0_valid_o         ,
+  output  wire        pipe_rx0_chanisaligned_o ,
+  output  wire [ 2:0] pipe_rx0_status_o        ,
+  output  wire        pipe_rx0_phy_status_o    ,
+  output  wire        pipe_rx0_elec_idle_o     ,
+  input   wire        pipe_rx0_polarity_i      ,
+  input   wire        pipe_tx0_compliance_i    ,
+  input   wire [ 1:0] pipe_tx0_char_is_k_i     ,
+  input   wire [15:0] pipe_tx0_data_i          ,
+  input   wire        pipe_tx0_elec_idle_i     ,
+  input   wire [ 1:0] pipe_tx0_powerdown_i     ,
+
+  input  wire [ 1:0]  pipe_rx0_char_is_k_i     ,
+  input  wire [15:0]  pipe_rx0_data_i         ,
+  input  wire         pipe_rx0_valid_i         ,
+  input  wire         pipe_rx0_chanisaligned_i ,
+  input  wire [ 2:0]  pipe_rx0_status_i        ,
+  input  wire         pipe_rx0_phy_status_i    ,
+  input  wire         pipe_rx0_elec_idle_i     ,
+  output wire         pipe_rx0_polarity_o      ,
+  output wire         pipe_tx0_compliance_o    ,
+  output wire [ 1:0]  pipe_tx0_char_is_k_o     ,
+  output wire [15:0]  pipe_tx0_data_o          ,
+  output wire         pipe_tx0_elec_idle_o     ,
+  output wire [ 1:0]  pipe_tx0_powerdown_o     ,
+
+  // Pipe Per-Lane Signals - Lane 1
+  output  wire [ 1:0] pipe_rx1_char_is_k_o     ,
+  output  wire [15:0] pipe_rx1_data_o         ,
+  output  wire        pipe_rx1_valid_o         ,
+  output  wire        pipe_rx1_chanisaligned_o ,
+  output  wire [ 2:0] pipe_rx1_status_o        ,
+  output  wire        pipe_rx1_phy_status_o    ,
+  output  wire        pipe_rx1_elec_idle_o     ,
+  input   wire        pipe_rx1_polarity_i      ,
+  input   wire        pipe_tx1_compliance_i    ,
+  input   wire [ 1:0] pipe_tx1_char_is_k_i     ,
+  input   wire [15:0] pipe_tx1_data_i          ,
+  input   wire        pipe_tx1_elec_idle_i     ,
+  input   wire [ 1:0] pipe_tx1_powerdown_i     ,
+
+  input  wire [ 1:0]  pipe_rx1_char_is_k_i     ,
+  input  wire [15:0]  pipe_rx1_data_i         ,
+  input  wire         pipe_rx1_valid_i         ,
+  input  wire         pipe_rx1_chanisaligned_i ,
+  input  wire [ 2:0]  pipe_rx1_status_i        ,
+  input  wire         pipe_rx1_phy_status_i    ,
+  input  wire         pipe_rx1_elec_idle_i     ,
+  output wire         pipe_rx1_polarity_o      ,
+  output wire         pipe_tx1_compliance_o    ,
+  output wire [ 1:0]  pipe_tx1_char_is_k_o     ,
+  output wire [15:0]  pipe_tx1_data_o          ,
+  output wire         pipe_tx1_elec_idle_o     ,
+  output wire [ 1:0]  pipe_tx1_powerdown_o     ,
+
+  // Pipe Per-Lane Signals - Lane 2
+  output  wire [ 1:0] pipe_rx2_char_is_k_o     ,
+  output  wire [15:0] pipe_rx2_data_o         ,
+  output  wire        pipe_rx2_valid_o         ,
+  output  wire        pipe_rx2_chanisaligned_o ,
+  output  wire [ 2:0] pipe_rx2_status_o        ,
+  output  wire        pipe_rx2_phy_status_o    ,
+  output  wire        pipe_rx2_elec_idle_o     ,
+  input   wire        pipe_rx2_polarity_i      ,
+  input   wire        pipe_tx2_compliance_i    ,
+  input   wire [ 1:0] pipe_tx2_char_is_k_i     ,
+  input   wire [15:0] pipe_tx2_data_i          ,
+  input   wire        pipe_tx2_elec_idle_i     ,
+  input   wire [ 1:0] pipe_tx2_powerdown_i     ,
+
+  input  wire [ 1:0]  pipe_rx2_char_is_k_i     ,
+  input  wire [15:0]  pipe_rx2_data_i         ,
+  input  wire         pipe_rx2_valid_i         ,
+  input  wire         pipe_rx2_chanisaligned_i ,
+  input  wire [ 2:0]  pipe_rx2_status_i        ,
+  input  wire         pipe_rx2_phy_status_i    ,
+  input  wire         pipe_rx2_elec_idle_i     ,
+  output wire         pipe_rx2_polarity_o      ,
+  output wire         pipe_tx2_compliance_o    ,
+  output wire [ 1:0]  pipe_tx2_char_is_k_o     ,
+  output wire [15:0]  pipe_tx2_data_o          ,
+  output wire         pipe_tx2_elec_idle_o     ,
+  output wire [ 1:0]  pipe_tx2_powerdown_o     ,
+
+  // Pipe Per-Lane Signals - Lane 3
+  output  wire [ 1:0] pipe_rx3_char_is_k_o     ,
+  output  wire [15:0] pipe_rx3_data_o         ,
+  output  wire        pipe_rx3_valid_o         ,
+  output  wire        pipe_rx3_chanisaligned_o ,
+  output  wire [ 2:0] pipe_rx3_status_o        ,
+  output  wire        pipe_rx3_phy_status_o    ,
+  output  wire        pipe_rx3_elec_idle_o     ,
+  input   wire        pipe_rx3_polarity_i      ,
+  input   wire        pipe_tx3_compliance_i    ,
+  input   wire [ 1:0] pipe_tx3_char_is_k_i     ,
+  input   wire [15:0] pipe_tx3_data_i          ,
+  input   wire        pipe_tx3_elec_idle_i     ,
+  input   wire [ 1:0] pipe_tx3_powerdown_i     ,
+
+  input  wire [ 1:0]  pipe_rx3_char_is_k_i     ,
+  input  wire [15:0]  pipe_rx3_data_i         ,
+  input  wire         pipe_rx3_valid_i         ,
+  input  wire         pipe_rx3_chanisaligned_i ,
+  input  wire [ 2:0]  pipe_rx3_status_i        ,
+  input  wire         pipe_rx3_phy_status_i    ,
+  input  wire         pipe_rx3_elec_idle_i     ,
+  output wire         pipe_rx3_polarity_o      ,
+  output wire         pipe_tx3_compliance_o    ,
+  output wire [ 1:0]  pipe_tx3_char_is_k_o     ,
+  output wire [15:0]  pipe_tx3_data_o          ,
+  output wire         pipe_tx3_elec_idle_o     ,
+  output wire [ 1:0]  pipe_tx3_powerdown_o     ,
+
+  // Pipe Per-Lane Signals - Lane 4
+  output  wire [ 1:0] pipe_rx4_char_is_k_o     ,
+  output  wire [15:0] pipe_rx4_data_o         ,
+  output  wire        pipe_rx4_valid_o         ,
+  output  wire        pipe_rx4_chanisaligned_o ,
+  output  wire [ 2:0] pipe_rx4_status_o        ,
+  output  wire        pipe_rx4_phy_status_o    ,
+  output  wire        pipe_rx4_elec_idle_o     ,
+  input   wire        pipe_rx4_polarity_i      ,
+  input   wire        pipe_tx4_compliance_i    ,
+  input   wire [ 1:0] pipe_tx4_char_is_k_i     ,
+  input   wire [15:0] pipe_tx4_data_i          ,
+  input   wire        pipe_tx4_elec_idle_i     ,
+  input   wire [ 1:0] pipe_tx4_powerdown_i     ,
+
+  input  wire [ 1:0]  pipe_rx4_char_is_k_i     ,
+  input  wire [15:0]  pipe_rx4_data_i         ,
+  input  wire         pipe_rx4_valid_i         ,
+  input  wire         pipe_rx4_chanisaligned_i ,
+  input  wire [ 2:0]  pipe_rx4_status_i        ,
+  input  wire         pipe_rx4_phy_status_i    ,
+  input  wire         pipe_rx4_elec_idle_i     ,
+  output wire         pipe_rx4_polarity_o      ,
+  output wire         pipe_tx4_compliance_o    ,
+  output wire [ 1:0]  pipe_tx4_char_is_k_o     ,
+  output wire [15:0]  pipe_tx4_data_o          ,
+  output wire         pipe_tx4_elec_idle_o     ,
+  output wire [ 1:0]  pipe_tx4_powerdown_o     ,
+
+  // Pipe Per-Lane Signals - Lane 5
+  output  wire [ 1:0] pipe_rx5_char_is_k_o     ,
+  output  wire [15:0] pipe_rx5_data_o         ,
+  output  wire        pipe_rx5_valid_o         ,
+  output  wire        pipe_rx5_chanisaligned_o ,
+  output  wire [ 2:0] pipe_rx5_status_o        ,
+  output  wire        pipe_rx5_phy_status_o    ,
+  output  wire        pipe_rx5_elec_idle_o     ,
+  input   wire        pipe_rx5_polarity_i      ,
+  input   wire        pipe_tx5_compliance_i    ,
+  input   wire [ 1:0] pipe_tx5_char_is_k_i     ,
+  input   wire [15:0] pipe_tx5_data_i          ,
+  input   wire        pipe_tx5_elec_idle_i     ,
+  input   wire [ 1:0] pipe_tx5_powerdown_i     ,
+
+  input  wire [ 1:0]  pipe_rx5_char_is_k_i     ,
+  input  wire [15:0]  pipe_rx5_data_i         ,
+  input  wire         pipe_rx5_valid_i         ,
+  input  wire         pipe_rx5_chanisaligned_i ,
+  input  wire [ 2:0]  pipe_rx5_status_i        ,
+  input  wire         pipe_rx5_phy_status_i    ,
+  input  wire         pipe_rx5_elec_idle_i     ,
+  output wire         pipe_rx5_polarity_o      ,
+  output wire         pipe_tx5_compliance_o    ,
+  output wire [ 1:0]  pipe_tx5_char_is_k_o     ,
+  output wire [15:0]  pipe_tx5_data_o          ,
+  output wire         pipe_tx5_elec_idle_o     ,
+  output wire [ 1:0]  pipe_tx5_powerdown_o     ,
+
+  // Pipe Per-Lane Signals - Lane 6
+  output  wire [ 1:0] pipe_rx6_char_is_k_o     ,
+  output  wire [15:0] pipe_rx6_data_o         ,
+  output  wire        pipe_rx6_valid_o         ,
+  output  wire        pipe_rx6_chanisaligned_o ,
+  output  wire [ 2:0] pipe_rx6_status_o        ,
+  output  wire        pipe_rx6_phy_status_o    ,
+  output  wire        pipe_rx6_elec_idle_o     ,
+  input   wire        pipe_rx6_polarity_i      ,
+  input   wire        pipe_tx6_compliance_i    ,
+  input   wire [ 1:0] pipe_tx6_char_is_k_i     ,
+  input   wire [15:0] pipe_tx6_data_i          ,
+  input   wire        pipe_tx6_elec_idle_i     ,
+  input   wire [ 1:0] pipe_tx6_powerdown_i     ,
+
+  input  wire [ 1:0]  pipe_rx6_char_is_k_i     ,
+  input  wire [15:0]  pipe_rx6_data_i         ,
+  input  wire         pipe_rx6_valid_i         ,
+  input  wire         pipe_rx6_chanisaligned_i ,
+  input  wire [ 2:0]  pipe_rx6_status_i        ,
+  input  wire         pipe_rx6_phy_status_i    ,
+  input  wire         pipe_rx6_elec_idle_i     ,
+  output wire         pipe_rx6_polarity_o      ,
+  output wire         pipe_tx6_compliance_o    ,
+  output wire [ 1:0]  pipe_tx6_char_is_k_o     ,
+  output wire [15:0]  pipe_tx6_data_o          ,
+  output wire         pipe_tx6_elec_idle_o     ,
+  output wire [ 1:0]  pipe_tx6_powerdown_o     ,
+
+  // Pipe Per-Lane Signals - Lane 7
+  output  wire [ 1:0] pipe_rx7_char_is_k_o     ,
+  output  wire [15:0] pipe_rx7_data_o         ,
+  output  wire        pipe_rx7_valid_o         ,
+  output  wire        pipe_rx7_chanisaligned_o ,
+  output  wire [ 2:0] pipe_rx7_status_o        ,
+  output  wire        pipe_rx7_phy_status_o    ,
+  output  wire        pipe_rx7_elec_idle_o     ,
+  input   wire        pipe_rx7_polarity_i      ,
+  input   wire        pipe_tx7_compliance_i    ,
+  input   wire [ 1:0] pipe_tx7_char_is_k_i     ,
+  input   wire [15:0] pipe_tx7_data_i          ,
+  input   wire        pipe_tx7_elec_idle_i     ,
+  input   wire [ 1:0] pipe_tx7_powerdown_i     ,
+
+  input  wire [ 1:0]  pipe_rx7_char_is_k_i     ,
+  input  wire [15:0]  pipe_rx7_data_i         ,
+  input  wire         pipe_rx7_valid_i         ,
+  input  wire         pipe_rx7_chanisaligned_i ,
+  input  wire [ 2:0]  pipe_rx7_status_i        ,
+  input  wire         pipe_rx7_phy_status_i    ,
+  input  wire         pipe_rx7_elec_idle_i     ,
+  output wire         pipe_rx7_polarity_o      ,
+  output wire         pipe_tx7_compliance_o    ,
+  output wire [ 1:0]  pipe_tx7_char_is_k_o     ,
+  output wire [15:0]  pipe_tx7_data_o          ,
+  output wire         pipe_tx7_elec_idle_o     ,
+  output wire [ 1:0]  pipe_tx7_powerdown_o     ,
+
+  // Non PIPE signals
+  input   wire        pipe_clk               ,
+  input   wire        rst_n
+);
+
+  //******************************************************************//
+  // Reality check.                                                   //
+  //******************************************************************//
+  
+  //synthesis translate_off
+  //   initial begin
+  //      $display("[%t] %m LINK_CAP_MAX_LINK_WIDTH %0d  PIPE_PIPELINE_STAGES %0d", 
+  //                 $time, LINK_CAP_MAX_LINK_WIDTH, PIPE_PIPELINE_STAGES);
+  //   end
+  //synthesis translate_on
+
+  generate
+
+xdma_0_pcie2_ip_pcie_pipe_misc # (
+
+      .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
+
+    )
+    pipe_misc_i (
+
+      .pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),
+      .pipe_tx_reset_i(pipe_tx_reset_i),
+      .pipe_tx_rate_i(pipe_tx_rate_i),
+      .pipe_tx_deemph_i(pipe_tx_deemph_i),
+      .pipe_tx_margin_i(pipe_tx_margin_i),
+      .pipe_tx_swing_i(pipe_tx_swing_i),
+
+      .pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o),
+      .pipe_tx_reset_o(pipe_tx_reset_o),
+      .pipe_tx_rate_o(pipe_tx_rate_o),
+      .pipe_tx_deemph_o(pipe_tx_deemph_o),
+      .pipe_tx_margin_o(pipe_tx_margin_o),
+      .pipe_tx_swing_o(pipe_tx_swing_o)          ,
+
+      .pipe_clk(pipe_clk),
+      .rst_n(rst_n)
+  );
+
+
+xdma_0_pcie2_ip_pcie_pipe_lane # (
+
+      .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
+
+    )
+    pipe_lane_0_i (
+
+      .pipe_rx_char_is_k_o(pipe_rx0_char_is_k_o),
+      .pipe_rx_data_o(pipe_rx0_data_o),
+      .pipe_rx_valid_o(pipe_rx0_valid_o),
+      .pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o),
+      .pipe_rx_status_o(pipe_rx0_status_o),
+      .pipe_rx_phy_status_o(pipe_rx0_phy_status_o),
+      .pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o),
+      .pipe_rx_polarity_i(pipe_rx0_polarity_i),
+      .pipe_tx_compliance_i(pipe_tx0_compliance_i),
+      .pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i),
+      .pipe_tx_data_i(pipe_tx0_data_i),
+      .pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i),
+      .pipe_tx_powerdown_i(pipe_tx0_powerdown_i),
+
+      .pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i),
+      .pipe_rx_data_i(pipe_rx0_data_i),
+      .pipe_rx_valid_i(pipe_rx0_valid_i),
+      .pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i),
+      .pipe_rx_status_i(pipe_rx0_status_i),
+      .pipe_rx_phy_status_i(pipe_rx0_phy_status_i),
+      .pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i),
+      .pipe_rx_polarity_o(pipe_rx0_polarity_o),
+      .pipe_tx_compliance_o(pipe_tx0_compliance_o),
+      .pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o),
+      .pipe_tx_data_o(pipe_tx0_data_o),
+      .pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o),
+      .pipe_tx_powerdown_o(pipe_tx0_powerdown_o),
+
+      .pipe_clk(pipe_clk),
+      .rst_n(rst_n)
+
+    );
+
+    if (LINK_CAP_MAX_LINK_WIDTH >= 2) begin : pipe_2_lane
+
+xdma_0_pcie2_ip_pcie_pipe_lane # (
+
+        .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
+
+      )
+      pipe_lane_1_i (
+
+        .pipe_rx_char_is_k_o(pipe_rx1_char_is_k_o),
+        .pipe_rx_data_o(pipe_rx1_data_o),
+        .pipe_rx_valid_o(pipe_rx1_valid_o),
+        .pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o),
+        .pipe_rx_status_o(pipe_rx1_status_o),
+        .pipe_rx_phy_status_o(pipe_rx1_phy_status_o),
+        .pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o),
+        .pipe_rx_polarity_i(pipe_rx1_polarity_i),
+        .pipe_tx_compliance_i(pipe_tx1_compliance_i),
+        .pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i),
+        .pipe_tx_data_i(pipe_tx1_data_i),
+        .pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i),
+        .pipe_tx_powerdown_i(pipe_tx1_powerdown_i),
+
+        .pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i),
+        .pipe_rx_data_i(pipe_rx1_data_i),
+        .pipe_rx_valid_i(pipe_rx1_valid_i),
+        .pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i),
+        .pipe_rx_status_i(pipe_rx1_status_i),
+        .pipe_rx_phy_status_i(pipe_rx1_phy_status_i),
+        .pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i),
+        .pipe_rx_polarity_o(pipe_rx1_polarity_o),
+        .pipe_tx_compliance_o(pipe_tx1_compliance_o),
+        .pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o),
+        .pipe_tx_data_o(pipe_tx1_data_o),
+        .pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o),
+        .pipe_tx_powerdown_o(pipe_tx1_powerdown_o),
+
+        .pipe_clk(pipe_clk),
+        .rst_n(rst_n)
+
+      );
+
+    end // if (LINK_CAP_MAX_LINK_WIDTH >= 2)
+    else
+    begin
+      assign pipe_rx1_char_is_k_o = 2'b00;
+      assign pipe_rx1_data_o = 16'h0000;
+      assign pipe_rx1_valid_o = 1'b0;
+      assign pipe_rx1_chanisaligned_o = 1'b0;
+      assign pipe_rx1_status_o = 3'b000;
+      assign pipe_rx1_phy_status_o = 1'b0;
+      assign pipe_rx1_elec_idle_o = 1'b1;
+      assign pipe_rx1_polarity_o = 1'b0;
+      assign pipe_tx1_compliance_o = 1'b0;
+      assign pipe_tx1_char_is_k_o = 2'b00;
+      assign pipe_tx1_data_o = 16'h0000;
+      assign pipe_tx1_elec_idle_o = 1'b1;
+      assign pipe_tx1_powerdown_o = 2'b00;
+    end // if !(LINK_CAP_MAX_LINK_WIDTH >= 2)
+
+    if (LINK_CAP_MAX_LINK_WIDTH >= 4) begin : pipe_4_lane
+
+xdma_0_pcie2_ip_pcie_pipe_lane # (
+
+        .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
+      )
+      pipe_lane_2_i (
+
+        .pipe_rx_char_is_k_o(pipe_rx2_char_is_k_o),
+        .pipe_rx_data_o(pipe_rx2_data_o),
+        .pipe_rx_valid_o(pipe_rx2_valid_o),
+        .pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o),
+        .pipe_rx_status_o(pipe_rx2_status_o),
+        .pipe_rx_phy_status_o(pipe_rx2_phy_status_o),
+        .pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o),
+        .pipe_rx_polarity_i(pipe_rx2_polarity_i),
+        .pipe_tx_compliance_i(pipe_tx2_compliance_i),
+        .pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i),
+        .pipe_tx_data_i(pipe_tx2_data_i),
+        .pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i),
+        .pipe_tx_powerdown_i(pipe_tx2_powerdown_i),
+
+        .pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i),
+        .pipe_rx_data_i(pipe_rx2_data_i),
+        .pipe_rx_valid_i(pipe_rx2_valid_i),
+        .pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i),
+        .pipe_rx_status_i(pipe_rx2_status_i),
+        .pipe_rx_phy_status_i(pipe_rx2_phy_status_i),
+        .pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i),
+        .pipe_rx_polarity_o(pipe_rx2_polarity_o),
+        .pipe_tx_compliance_o(pipe_tx2_compliance_o),
+        .pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o),
+        .pipe_tx_data_o(pipe_tx2_data_o),
+        .pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o),
+        .pipe_tx_powerdown_o(pipe_tx2_powerdown_o),
+
+        .pipe_clk(pipe_clk),
+        .rst_n(rst_n)
+
+      );
+
+xdma_0_pcie2_ip_pcie_pipe_lane # (
+
+        .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
+
+      )
+      pipe_lane_3_i (
+
+        .pipe_rx_char_is_k_o(pipe_rx3_char_is_k_o),
+        .pipe_rx_data_o(pipe_rx3_data_o),
+        .pipe_rx_valid_o(pipe_rx3_valid_o),
+        .pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o),
+        .pipe_rx_status_o(pipe_rx3_status_o),
+        .pipe_rx_phy_status_o(pipe_rx3_phy_status_o),
+        .pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o),
+        .pipe_rx_polarity_i(pipe_rx3_polarity_i),
+        .pipe_tx_compliance_i(pipe_tx3_compliance_i),
+        .pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i),
+        .pipe_tx_data_i(pipe_tx3_data_i),
+        .pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i),
+        .pipe_tx_powerdown_i(pipe_tx3_powerdown_i),
+
+        .pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i),
+        .pipe_rx_data_i(pipe_rx3_data_i),
+        .pipe_rx_valid_i(pipe_rx3_valid_i),
+        .pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i),
+        .pipe_rx_status_i(pipe_rx3_status_i),
+        .pipe_rx_phy_status_i(pipe_rx3_phy_status_i),
+        .pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i),
+        .pipe_rx_polarity_o(pipe_rx3_polarity_o),
+        .pipe_tx_compliance_o(pipe_tx3_compliance_o),
+        .pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o),
+        .pipe_tx_data_o(pipe_tx3_data_o),
+        .pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o),
+        .pipe_tx_powerdown_o(pipe_tx3_powerdown_o),
+
+        .pipe_clk(pipe_clk),
+        .rst_n(rst_n)
+
+      );
+
+    end // if (LINK_CAP_MAX_LINK_WIDTH >= 4)
+    else
+    begin
+      assign pipe_rx2_char_is_k_o = 2'b00;
+      assign pipe_rx2_data_o = 16'h0000;
+      assign pipe_rx2_valid_o = 1'b0;
+      assign pipe_rx2_chanisaligned_o = 1'b0;
+      assign pipe_rx2_status_o = 3'b000;
+      assign pipe_rx2_phy_status_o = 1'b0;
+      assign pipe_rx2_elec_idle_o = 1'b1;
+      assign pipe_rx2_polarity_o = 1'b0;
+      assign pipe_tx2_compliance_o = 1'b0;
+      assign pipe_tx2_char_is_k_o = 2'b00;
+      assign pipe_tx2_data_o = 16'h0000;
+      assign pipe_tx2_elec_idle_o = 1'b1;
+      assign pipe_tx2_powerdown_o = 2'b00;
+
+      assign pipe_rx3_char_is_k_o = 2'b00;
+      assign pipe_rx3_data_o = 16'h0000;
+      assign pipe_rx3_valid_o = 1'b0;
+      assign pipe_rx3_chanisaligned_o = 1'b0;
+      assign pipe_rx3_status_o = 3'b000;
+      assign pipe_rx3_phy_status_o = 1'b0;
+      assign pipe_rx3_elec_idle_o = 1'b1;
+      assign pipe_rx3_polarity_o = 1'b0;
+      assign pipe_tx3_compliance_o = 1'b0;
+      assign pipe_tx3_char_is_k_o = 2'b00;
+      assign pipe_tx3_data_o = 16'h0000;
+      assign pipe_tx3_elec_idle_o = 1'b1;
+      assign pipe_tx3_powerdown_o = 2'b00;
+    end // if !(LINK_CAP_MAX_LINK_WIDTH >= 4)
+
+    if (LINK_CAP_MAX_LINK_WIDTH >= 8) begin : pipe_8_lane
+
+xdma_0_pcie2_ip_pcie_pipe_lane # (
+
+        .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
+
+      )
+      pipe_lane_4_i (
+
+        .pipe_rx_char_is_k_o(pipe_rx4_char_is_k_o),
+        .pipe_rx_data_o(pipe_rx4_data_o),
+        .pipe_rx_valid_o(pipe_rx4_valid_o),
+        .pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o),
+        .pipe_rx_status_o(pipe_rx4_status_o),
+        .pipe_rx_phy_status_o(pipe_rx4_phy_status_o),
+        .pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o),
+        .pipe_rx_polarity_i(pipe_rx4_polarity_i),
+        .pipe_tx_compliance_i(pipe_tx4_compliance_i),
+        .pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i),
+        .pipe_tx_data_i(pipe_tx4_data_i),
+        .pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i),
+        .pipe_tx_powerdown_i(pipe_tx4_powerdown_i),
+
+        .pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i),
+        .pipe_rx_data_i(pipe_rx4_data_i),
+        .pipe_rx_valid_i(pipe_rx4_valid_i),
+        .pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i),
+        .pipe_rx_status_i(pipe_rx4_status_i),
+        .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
+        .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
+        .pipe_rx_polarity_o(pipe_rx4_polarity_o),
+        .pipe_tx_compliance_o(pipe_tx4_compliance_o),
+        .pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o),
+        .pipe_tx_data_o(pipe_tx4_data_o),
+        .pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o),
+        .pipe_tx_powerdown_o(pipe_tx4_powerdown_o),
+
+        .pipe_clk(pipe_clk),
+        .rst_n(rst_n)
+
+      );
+
+xdma_0_pcie2_ip_pcie_pipe_lane # (
+
+        .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
+
+      )
+      pipe_lane_5_i (
+
+        .pipe_rx_char_is_k_o(pipe_rx5_char_is_k_o),
+        .pipe_rx_data_o(pipe_rx5_data_o),
+        .pipe_rx_valid_o(pipe_rx5_valid_o),
+        .pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o),
+        .pipe_rx_status_o(pipe_rx5_status_o),
+        .pipe_rx_phy_status_o(pipe_rx5_phy_status_o),
+        .pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o),
+        .pipe_rx_polarity_i(pipe_rx5_polarity_i),
+        .pipe_tx_compliance_i(pipe_tx5_compliance_i),
+        .pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i),
+        .pipe_tx_data_i(pipe_tx5_data_i),
+        .pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i),
+        .pipe_tx_powerdown_i(pipe_tx5_powerdown_i),
+
+        .pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i),
+        .pipe_rx_data_i(pipe_rx5_data_i),
+        .pipe_rx_valid_i(pipe_rx5_valid_i),
+        .pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i),
+        .pipe_rx_status_i(pipe_rx5_status_i),
+        .pipe_rx_phy_status_i(pipe_rx5_phy_status_i),
+        .pipe_rx_elec_idle_i(pipe_rx5_elec_idle_i),
+        .pipe_rx_polarity_o(pipe_rx5_polarity_o),
+        .pipe_tx_compliance_o(pipe_tx5_compliance_o),
+        .pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o),
+        .pipe_tx_data_o(pipe_tx5_data_o),
+        .pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o),
+        .pipe_tx_powerdown_o(pipe_tx5_powerdown_o),
+
+        .pipe_clk(pipe_clk),
+        .rst_n(rst_n)
+
+      );
+
+xdma_0_pcie2_ip_pcie_pipe_lane # (
+
+        .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
+
+      )
+      pipe_lane_6_i (
+
+        .pipe_rx_char_is_k_o(pipe_rx6_char_is_k_o),
+        .pipe_rx_data_o(pipe_rx6_data_o),
+        .pipe_rx_valid_o(pipe_rx6_valid_o),
+        .pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o),
+        .pipe_rx_status_o(pipe_rx6_status_o),
+        .pipe_rx_phy_status_o(pipe_rx6_phy_status_o),
+        .pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o),
+        .pipe_rx_polarity_i(pipe_rx6_polarity_i),
+        .pipe_tx_compliance_i(pipe_tx6_compliance_i),
+        .pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i),
+        .pipe_tx_data_i(pipe_tx6_data_i),
+        .pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i),
+        .pipe_tx_powerdown_i(pipe_tx6_powerdown_i),
+
+        .pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i),
+        .pipe_rx_data_i(pipe_rx6_data_i),
+        .pipe_rx_valid_i(pipe_rx6_valid_i),
+        .pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i),
+        .pipe_rx_status_i(pipe_rx6_status_i),
+        .pipe_rx_phy_status_i(pipe_rx6_phy_status_i),
+        .pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i),
+        .pipe_rx_polarity_o(pipe_rx6_polarity_o),
+        .pipe_tx_compliance_o(pipe_tx6_compliance_o),
+        .pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o),
+        .pipe_tx_data_o(pipe_tx6_data_o),
+        .pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o),
+        .pipe_tx_powerdown_o(pipe_tx6_powerdown_o),
+
+        .pipe_clk(pipe_clk),
+        .rst_n(rst_n)
+
+      );
+
+xdma_0_pcie2_ip_pcie_pipe_lane # (
+
+        .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
+
+      )
+      pipe_lane_7_i (
+
+        .pipe_rx_char_is_k_o(pipe_rx7_char_is_k_o),
+        .pipe_rx_data_o(pipe_rx7_data_o),
+        .pipe_rx_valid_o(pipe_rx7_valid_o),
+        .pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o),
+        .pipe_rx_status_o(pipe_rx7_status_o),
+        .pipe_rx_phy_status_o(pipe_rx7_phy_status_o),
+        .pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o),
+        .pipe_rx_polarity_i(pipe_rx7_polarity_i),
+        .pipe_tx_compliance_i(pipe_tx7_compliance_i),
+        .pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i),
+        .pipe_tx_data_i(pipe_tx7_data_i),
+        .pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i),
+        .pipe_tx_powerdown_i(pipe_tx7_powerdown_i),
+
+        .pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i),
+        .pipe_rx_data_i(pipe_rx7_data_i),
+        .pipe_rx_valid_i(pipe_rx7_valid_i),
+        .pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i),
+        .pipe_rx_status_i(pipe_rx7_status_i),
+        .pipe_rx_phy_status_i(pipe_rx7_phy_status_i),
+        .pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i),
+        .pipe_rx_polarity_o(pipe_rx7_polarity_o),
+        .pipe_tx_compliance_o(pipe_tx7_compliance_o),
+        .pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o),
+        .pipe_tx_data_o(pipe_tx7_data_o),
+        .pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o),
+        .pipe_tx_powerdown_o(pipe_tx7_powerdown_o),
+
+        .pipe_clk(pipe_clk),
+        .rst_n(rst_n)
+
+      );
+
+    end // if (LINK_CAP_MAX_LINK_WIDTH >= 8)
+    else
+    begin
+      assign pipe_rx4_char_is_k_o = 2'b00;
+      assign pipe_rx4_data_o = 16'h0000;
+      assign pipe_rx4_valid_o = 1'b0;
+      assign pipe_rx4_chanisaligned_o = 1'b0;
+      assign pipe_rx4_status_o = 3'b000;
+      assign pipe_rx4_phy_status_o = 1'b0;
+      assign pipe_rx4_elec_idle_o = 1'b1;
+      assign pipe_rx4_polarity_o = 1'b0;
+      assign pipe_tx4_compliance_o = 1'b0;
+      assign pipe_tx4_char_is_k_o = 2'b00;
+      assign pipe_tx4_data_o = 16'h0000;
+      assign pipe_tx4_elec_idle_o = 1'b1;
+      assign pipe_tx4_powerdown_o = 2'b00;
+
+      assign pipe_rx5_char_is_k_o = 2'b00;
+      assign pipe_rx5_data_o = 16'h0000;
+      assign pipe_rx5_valid_o = 1'b0;
+      assign pipe_rx5_chanisaligned_o = 1'b0;
+      assign pipe_rx5_status_o = 3'b000;
+      assign pipe_rx5_phy_status_o = 1'b0;
+      assign pipe_rx5_elec_idle_o = 1'b1;
+      assign pipe_rx5_polarity_o = 1'b0;
+      assign pipe_tx5_compliance_o = 1'b0;
+      assign pipe_tx5_char_is_k_o = 2'b00;
+      assign pipe_tx5_data_o = 16'h0000;
+      assign pipe_tx5_elec_idle_o = 1'b1;
+      assign pipe_tx5_powerdown_o = 2'b00;
+
+      assign pipe_rx6_char_is_k_o = 2'b00;
+      assign pipe_rx6_data_o = 16'h0000;
+      assign pipe_rx6_valid_o = 1'b0;
+      assign pipe_rx6_chanisaligned_o = 1'b0;
+      assign pipe_rx6_status_o = 3'b000;
+      assign pipe_rx6_phy_status_o = 1'b0;
+      assign pipe_rx6_elec_idle_o = 1'b1;
+      assign pipe_rx6_polarity_o = 1'b0;
+      assign pipe_tx6_compliance_o = 1'b0;
+      assign pipe_tx6_char_is_k_o = 2'b00;
+      assign pipe_tx6_data_o = 16'h0000;
+      assign pipe_tx6_elec_idle_o = 1'b1;
+      assign pipe_tx6_powerdown_o = 2'b00;
+
+      assign pipe_rx7_char_is_k_o = 2'b00;
+      assign pipe_rx7_data_o = 16'h0000;
+      assign pipe_rx7_valid_o = 1'b0;
+      assign pipe_rx7_chanisaligned_o = 1'b0;
+      assign pipe_rx7_status_o = 3'b000;
+      assign pipe_rx7_phy_status_o = 1'b0;
+      assign pipe_rx7_elec_idle_o = 1'b1;
+      assign pipe_rx7_polarity_o = 1'b0;
+      assign pipe_tx7_compliance_o = 1'b0;
+      assign pipe_tx7_char_is_k_o = 2'b00;
+      assign pipe_tx7_data_o = 16'h0000;
+      assign pipe_tx7_elec_idle_o = 1'b1;
+      assign pipe_tx7_powerdown_o = 2'b00;
+    end // if !(LINK_CAP_MAX_LINK_WIDTH >= 8)
+
+  endgenerate
+
+endmodule
+

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pipe_clock.v

@@ -0,0 +1,613 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pipe_clock.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  pipe_clock.v
+//  Description  :  PIPE Clock Module for 7 Series Transceiver
+//  Version      :  15.3
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- PIPE Clock Module -------------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_pipe_clock #
+(
+
+    parameter PCIE_ASYNC_EN      = "FALSE",                 // PCIe async enable
+    parameter PCIE_TXBUF_EN      = "FALSE",                 // PCIe TX buffer enable for Gen1/Gen2 only
+    parameter PCIE_CLK_SHARING_EN= "FALSE",                 // Enable Clock Sharing
+    parameter PCIE_LANE          = 1,                       // PCIe number of lanes
+    parameter PCIE_LINK_SPEED    = 3,                       // PCIe link speed 
+    parameter PCIE_REFCLK_FREQ   = 0,                       // PCIe reference clock frequency
+    parameter PCIE_USERCLK1_FREQ = 2,                       // PCIe user clock 1 frequency
+    parameter PCIE_USERCLK2_FREQ = 2,                       // PCIe user clock 2 frequency
+    parameter PCIE_OOBCLK_MODE   = 1,                       // PCIe oob clock mode
+    parameter PCIE_DEBUG_MODE    = 0                        // PCIe Debug mode
+    
+)
+
+(
+
+    //---------- Input -------------------------------------
+    input                       CLK_CLK,
+    input                       CLK_TXOUTCLK,
+    input       [PCIE_LANE-1:0] CLK_RXOUTCLK_IN,
+    input                       CLK_RST_N,
+    input       [PCIE_LANE-1:0] CLK_PCLK_SEL,
+    input       [PCIE_LANE-1:0] CLK_PCLK_SEL_SLAVE,
+    input                       CLK_GEN3,
+    
+    //---------- Output ------------------------------------
+    output                      CLK_PCLK,
+    output                      CLK_PCLK_SLAVE,
+    output                      CLK_RXUSRCLK,
+    output      [PCIE_LANE-1:0] CLK_RXOUTCLK_OUT,
+    output                      CLK_DCLK,
+    output                      CLK_OOBCLK,
+    output                      CLK_USERCLK1,
+    output                      CLK_USERCLK2,
+    output                      CLK_MMCM_LOCK
+    
+);
+    
+    //---------- Select Clock Divider ----------------------
+    localparam          DIVCLK_DIVIDE    = (PCIE_REFCLK_FREQ == 2) ? 1 :
+                                           (PCIE_REFCLK_FREQ == 1) ? 1 : 1;
+                                               
+    localparam          CLKFBOUT_MULT_F  = (PCIE_REFCLK_FREQ == 2) ? 4 :
+                                           (PCIE_REFCLK_FREQ == 1) ? 8 : 10;
+               
+    localparam          CLKIN1_PERIOD    = (PCIE_REFCLK_FREQ == 2) ? 4 :
+                                           (PCIE_REFCLK_FREQ == 1) ? 8 : 10;
+                                               
+    localparam          CLKOUT0_DIVIDE_F = 8;
+    
+    localparam          CLKOUT1_DIVIDE   = 4;
+    
+    localparam          CLKOUT2_DIVIDE   = (PCIE_USERCLK1_FREQ == 5) ?  2 : 
+                                           (PCIE_USERCLK1_FREQ == 4) ?  4 :
+                                           (PCIE_USERCLK1_FREQ == 3) ?  8 :
+                                           (PCIE_USERCLK1_FREQ == 1) ? 32 : 16;
+                                               
+    localparam          CLKOUT3_DIVIDE   = (PCIE_USERCLK2_FREQ == 5) ?  2 : 
+                                           (PCIE_USERCLK2_FREQ == 4) ?  4 :
+                                           (PCIE_USERCLK2_FREQ == 3) ?  8 :
+                                           (PCIE_USERCLK2_FREQ == 1) ? 32 : 16;
+                                           
+    localparam          CLKOUT4_DIVIDE   = 20;
+
+    localparam          PCIE_GEN1_MODE    = 1'b0;             // PCIe link speed is GEN1 only
+                                    
+       
+    //---------- Input Registers ---------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0] pclk_sel_slave_reg1 = {PCIE_LANE{1'd0}};
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                         gen3_reg1     = 1'd0;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0] pclk_sel_slave_reg2 = {PCIE_LANE{1'd0}};
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                         gen3_reg2     = 1'd0;   
+       
+    //---------- Internal Signals -------------------------- 
+    wire                            refclk;
+    wire                            mmcm_fb;
+    wire                            clk_125mhz;
+    wire                            clk_125mhz_buf;
+    wire                            clk_250mhz;
+    wire                            userclk1;
+    wire                            userclk2;
+    wire                            oobclk;
+    reg    pclk_sel = 1'd0;
+    reg                             pclk_sel_slave = 1'd0;
+
+    //---------- Output Registers --------------------------
+    wire                        pclk_1;
+    wire                        pclk;
+    wire                        userclk1_1;
+    wire                        userclk2_1;
+    wire                        mmcm_lock;
+    
+    //---------- Generate Per-Lane Signals -----------------
+    genvar              i;                                  // Index for per-lane signals
+
+
+
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge pclk)
+begin
+
+    if (!CLK_RST_N)
+        begin
+        //---------- 1st Stage FF --------------------------
+        pclk_sel_reg1 <= {PCIE_LANE{1'd0}};
+        pclk_sel_slave_reg1 <= {PCIE_LANE{1'd0}};
+        gen3_reg1     <= 1'd0;
+        //---------- 2nd Stage FF --------------------------
+        pclk_sel_reg2 <= {PCIE_LANE{1'd0}};
+        pclk_sel_slave_reg2 <= {PCIE_LANE{1'd0}};
+        gen3_reg2     <= 1'd0;
+        end
+    else
+        begin  
+        //---------- 1st Stage FF --------------------------
+        pclk_sel_reg1 <= CLK_PCLK_SEL;
+        pclk_sel_slave_reg1 <= CLK_PCLK_SEL_SLAVE;
+        gen3_reg1     <= CLK_GEN3;
+        //---------- 2nd Stage FF --------------------------
+        pclk_sel_reg2 <= pclk_sel_reg1;
+        pclk_sel_slave_reg2 <= pclk_sel_slave_reg1;
+        gen3_reg2     <= gen3_reg1;
+        end
+        
+end
+
+
+   
+//---------- Select Reference clock or TXOUTCLK --------------------------------   
+generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3))
+
+    begin : refclk_i
+
+    //---------- Select Reference Clock ----------------------------------------
+    BUFG refclk_i
+    (
+    
+        //---------- Input -------------------------------------
+        .I                          (CLK_CLK),
+        //---------- Output ------------------------------------
+        .O                          (refclk)
+       
+    );
+      
+    end
+
+else
+
+    begin : txoutclk_i
+    
+    //---------- Select TXOUTCLK -----------------------------------------------
+    BUFG txoutclk_i
+    (
+    
+        //---------- Input -------------------------------------
+        .I                          (CLK_TXOUTCLK),
+        //---------- Output ------------------------------------
+        .O                          (refclk)
+       
+    );
+   
+    end
+
+endgenerate
+
+
+
+//---------- MMCM --------------------------------------------------------------
+MMCME2_ADV #
+(
+
+    .BANDWIDTH                  ("OPTIMIZED"),
+    .CLKOUT4_CASCADE            ("FALSE"),
+    .COMPENSATION               ("ZHOLD"),
+    .STARTUP_WAIT               ("FALSE"),
+    .DIVCLK_DIVIDE              (DIVCLK_DIVIDE),
+    .CLKFBOUT_MULT_F            (CLKFBOUT_MULT_F),  
+    .CLKFBOUT_PHASE             (0.000),
+    .CLKFBOUT_USE_FINE_PS       ("FALSE"),
+    .CLKOUT0_DIVIDE_F           (CLKOUT0_DIVIDE_F),                    
+    .CLKOUT0_PHASE              (0.000),
+    .CLKOUT0_DUTY_CYCLE         (0.500),
+    .CLKOUT0_USE_FINE_PS        ("FALSE"),
+    .CLKOUT1_DIVIDE             (CLKOUT1_DIVIDE),                    
+    .CLKOUT1_PHASE              (0.000),
+    .CLKOUT1_DUTY_CYCLE         (0.500),
+    .CLKOUT1_USE_FINE_PS        ("FALSE"),
+    .CLKOUT2_DIVIDE             (CLKOUT2_DIVIDE),                  
+    .CLKOUT2_PHASE              (0.000),
+    .CLKOUT2_DUTY_CYCLE         (0.500),
+    .CLKOUT2_USE_FINE_PS        ("FALSE"),
+    .CLKOUT3_DIVIDE             (CLKOUT3_DIVIDE),                  
+    .CLKOUT3_PHASE              (0.000),
+    .CLKOUT3_DUTY_CYCLE         (0.500),
+    .CLKOUT3_USE_FINE_PS        ("FALSE"),
+    .CLKOUT4_DIVIDE             (CLKOUT4_DIVIDE),                  
+    .CLKOUT4_PHASE              (0.000),
+    .CLKOUT4_DUTY_CYCLE         (0.500),
+    .CLKOUT4_USE_FINE_PS        ("FALSE"),
+    .CLKIN1_PERIOD              (CLKIN1_PERIOD),                   
+    .REF_JITTER1                (0.010)
+    
+)
+mmcm_i
+(
+
+     //---------- Input ------------------------------------
+    .CLKIN1                     (refclk),
+    .CLKIN2                     (1'd0),                     // not used, comment out CLKIN2 if it cause implementation issues
+  //.CLKIN2                     (refclk),                   // not used, comment out CLKIN2 if it cause implementation issues
+    .CLKINSEL                   (1'd1),
+    .CLKFBIN                    (mmcm_fb),
+    .RST                        (!CLK_RST_N),
+    .PWRDWN                     (1'd0), 
+    
+    //---------- Output ------------------------------------
+    .CLKFBOUT                   (mmcm_fb),
+    .CLKFBOUTB                  (),
+    .CLKOUT0                    (clk_125mhz),
+    .CLKOUT0B                   (),
+    .CLKOUT1                    (clk_250mhz),
+    .CLKOUT1B                   (),
+    .CLKOUT2                    (userclk1),
+    .CLKOUT2B                   (),
+    .CLKOUT3                    (userclk2),
+    .CLKOUT3B                   (),
+    .CLKOUT4                    (oobclk),
+    .CLKOUT5                    (),
+    .CLKOUT6                    (),
+    .LOCKED                     (mmcm_lock),
+    
+    //---------- Dynamic Reconfiguration -------------------
+    .DCLK                       ( 1'd0),
+    .DADDR                      ( 7'd0),
+    .DEN                        ( 1'd0),
+    .DWE                        ( 1'd0),
+    .DI                         (16'd0),
+    .DO                         (),
+    .DRDY                       (),
+    
+    //---------- Dynamic Phase Shift -----------------------
+    .PSCLK                      (1'd0),
+    .PSEN                       (1'd0),
+    .PSINCDEC                   (1'd0),
+    .PSDONE                     (),
+    
+    //---------- Status ------------------------------------
+    .CLKINSTOPPED               (),
+    .CLKFBSTOPPED               ()  
+
+); 
+  
+
+
+//---------- Select PCLK MUX ---------------------------------------------------
+generate if (PCIE_LINK_SPEED != 1) 
+
+    begin : pclk_i1_bufgctrl
+    //---------- PCLK Mux ----------------------------------
+    BUFGCTRL pclk_i1
+    (
+        //---------- Input ---------------------------------
+        .CE0                        (1'd1),         
+        .CE1                        (1'd1),        
+        .I0                         (clk_125mhz),   
+        .I1                         (clk_250mhz),   
+        .IGNORE0                    (1'd0),        
+        .IGNORE1                    (1'd0),        
+        .S0                         (~pclk_sel),    
+        .S1                         ( pclk_sel),    
+        //---------- Output --------------------------------
+        .O                          (pclk_1)
+    );
+    end
+
+else 
+
+    //---------- Select PCLK Buffer ------------------------
+    begin : pclk_i1_bufg
+    //---------- PCLK Buffer -------------------------------
+    BUFG pclk_i1
+    (
+        //---------- Input ---------------------------------
+        .I                          (clk_125mhz), 
+        //---------- Output --------------------------------
+        .O                          (clk_125mhz_buf)
+    );
+    assign pclk_1 = clk_125mhz_buf;
+    end 
+
+endgenerate
+
+//---------- Select PCLK MUX for Slave---------------------------------------------------
+generate  if(PCIE_CLK_SHARING_EN == "FALSE")
+   //---------- PCLK MUX for Slave------------------// 
+    begin : pclk_slave_disable
+    assign CLK_PCLK_SLAVE = 1'b0;
+    end  
+
+else if (PCIE_LINK_SPEED != 1) 
+
+    begin : pclk_slave_bufgctrl
+    //---------- PCLK Mux ----------------------------------
+    BUFGCTRL pclk_slave
+    (
+        //---------- Input ---------------------------------
+        .CE0                        (1'd1),         
+        .CE1                        (1'd1),        
+        .I0                         (clk_125mhz),   
+        .I1                         (clk_250mhz),   
+        .IGNORE0                    (1'd0),        
+        .IGNORE1                    (1'd0),        
+        .S0                         (~pclk_sel_slave),    
+        .S1                         ( pclk_sel_slave),    
+        //---------- Output --------------------------------
+        .O                          (CLK_PCLK_SLAVE)
+    );
+    end
+
+else 
+
+    //---------- Select PCLK Buffer ------------------------
+    begin : pclk_slave_bufg
+    //---------- PCLK Buffer -------------------------------
+    BUFG pclk_slave
+    (
+        //---------- Input ---------------------------------
+        .I                          (clk_125mhz), 
+        //---------- Output --------------------------------
+        .O                          (CLK_PCLK_SLAVE)
+    );
+    end 
+
+endgenerate
+
+
+
+//---------- Generate RXOUTCLK Buffer for Debug --------------------------------
+generate if ((PCIE_DEBUG_MODE == 1) || (PCIE_ASYNC_EN == "TRUE"))
+        
+    begin : rxoutclk_per_lane
+    //---------- Generate per Lane -------------------------
+    for (i=0; i<PCIE_LANE; i=i+1) 
+    
+        begin : rxoutclk_i
+        //---------- RXOUTCLK Buffer -----------------------
+        BUFG rxoutclk_i
+        (
+            //---------- Input -----------------------------
+            .I                          (CLK_RXOUTCLK_IN[i]), 
+            //---------- Output ----------------------------
+            .O                          (CLK_RXOUTCLK_OUT[i])
+        );
+        end
+
+    end 
+        
+else
+
+    //---------- Disable RXOUTCLK Buffer for Normal Operation 
+    begin : rxoutclk_i_disable
+    assign CLK_RXOUTCLK_OUT = {PCIE_LANE{1'd0}};
+    end       
+            
+endgenerate 
+
+
+//---------- Generate DCLK Buffer ----------------------------------------------
+//generate if (PCIE_USERCLK2_FREQ <= 3)
+//---------- Disable DCLK Buffer -----------------------
+//    begin : dclk_i
+//    assign CLK_DCLK = userclk2_1;                       // always less than 125Mhz
+//   end
+//else
+//    begin : dclk_i_bufg
+//---------- DCLK Buffer -------------------------------
+//    BUFG dclk_i
+//    (
+//---------- Input ---------------------------------
+//        .I                          (clk_125mhz), 
+//---------- Output --------------------------------
+//        .O                          (CLK_DCLK)
+//    );
+//    end 
+//endgenerate
+
+generate if (PCIE_LINK_SPEED != 1)
+
+    begin : dclk_i_bufg
+    //---------- DCLK Buffer -------------------------------
+    BUFG dclk_i
+    (
+        //---------- Input ---------------------------------
+        .I                          (clk_125mhz),
+        //---------- Output --------------------------------
+        .O                          (CLK_DCLK)
+    );
+    end
+
+else
+
+    //---------- Disable DCLK Buffer -----------------------
+    begin : dclk_i
+    assign CLK_DCLK = clk_125mhz_buf;                       // always 125 MHz in Gen1
+    end
+
+endgenerate
+
+
+
+
+//---------- Generate USERCLK1 Buffer ------------------------------------------
+generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK1_FREQ == 3) 
+    //---------- USERCLK1 same as PCLK -------------------
+    begin :userclk1_i1_no_bufg
+    assign userclk1_1 = pclk_1;
+    end 
+else
+    begin : userclk1_i1
+    //---------- USERCLK1 Buffer ---------------------------
+    BUFG usrclk1_i1
+    (
+        //---------- Input ---------------------------------
+        .I                          (userclk1),
+        //---------- Output --------------------------------
+        .O                          (userclk1_1)
+    );
+    end 
+endgenerate 
+
+
+
+//---------- Generate USERCLK2 Buffer ------------------------------------------
+
+generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK2_FREQ == 3 ) 
+//---------- USERCLK2 same as PCLK -------------------
+    begin : userclk2_i1_no_bufg0
+    assign userclk2_1 = pclk_1;
+    end 
+else if (PCIE_USERCLK2_FREQ == PCIE_USERCLK1_FREQ ) 
+//---------- USERCLK2 same as USERCLK1 -------------------
+    begin : userclk2_i1_no_bufg1
+    assign userclk2_1 = userclk1_1;
+    end  
+else    
+    begin : userclk2_i1
+    //---------- USERCLK2 Buffer ---------------------------
+    BUFG usrclk2_i1
+    (
+        //---------- Input ---------------------------------
+        .I                          (userclk2),
+        //---------- Output --------------------------------
+        .O                          (userclk2_1)
+    );
+    end
+endgenerate 
+
+
+
+//---------- Generate OOBCLK Buffer --------------------------------------------
+generate if (PCIE_OOBCLK_MODE == 2) 
+
+    begin : oobclk_i1
+    //---------- OOBCLK Buffer -----------------------------
+    BUFG oobclk_i1
+    (
+        //---------- Input ---------------------------------
+        .I                          (oobclk),
+        //---------- Output --------------------------------
+        .O                          (CLK_OOBCLK)
+    );
+    end
+
+else 
+        
+    //---------- Disable OOBCLK Buffer ---------------------
+    begin : oobclk_i1_disable
+    assign CLK_OOBCLK = pclk;
+    end  
+
+endgenerate 
+
+
+// Disabled Second Stage Buffers
+    assign pclk         = pclk_1;
+    assign CLK_RXUSRCLK = pclk_1;
+    assign CLK_USERCLK1 = userclk1_1;
+    assign CLK_USERCLK2 = userclk2_1;
+ 
+
+
+
+//---------- Select PCLK -------------------------------------------------------
+always @ (posedge pclk)
+begin
+
+    if (!CLK_RST_N)
+        pclk_sel <= 1'd0;
+    else
+        begin 
+        //---------- Select 250 MHz ------------------------
+        if (&pclk_sel_reg2)
+            pclk_sel <= 1'd1;
+        //---------- Select 125 MHz ------------------------  
+        else if (&(~pclk_sel_reg2))
+            pclk_sel <= 1'd0;  
+        //---------- Hold PCLK -----------------------------
+        else
+            pclk_sel <= pclk_sel;
+        end
+
+end        
+
+always @ (posedge pclk)
+begin
+
+    if (!CLK_RST_N)
+        pclk_sel_slave<= 1'd0;
+    else
+        begin 
+        //---------- Select 250 MHz ------------------------
+        if (&pclk_sel_slave_reg2)
+            pclk_sel_slave <= 1'd1;
+        //---------- Select 125 MHz ------------------------  
+        else if (&(~pclk_sel_slave_reg2))
+            pclk_sel_slave <= 1'd0;  
+        //---------- Hold PCLK -----------------------------
+        else
+            pclk_sel_slave <= pclk_sel_slave;
+        end
+
+end     
+
+
+
+//---------- PIPE Clock Output -------------------------------------------------
+assign CLK_PCLK      = pclk;
+assign CLK_MMCM_LOCK = mmcm_lock;
+
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pipe_drp.v

@@ -0,0 +1,782 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pipe_drp.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  pipe_drp.v
+//  Description  :  PIPE DRP Module for 7 Series Transceiver
+//  Version      :  20.0
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- PIPE DRP Module ---------------------------------------------------
+module xdma_0_pcie2_ip_pipe_drp #
+(
+
+    parameter PCIE_GT_DEVICE       = "GTX",                                     // PCIe GT device
+    parameter PCIE_USE_MODE        = "3.0",                                     // PCIe use mode
+    parameter PCIE_ASYNC_EN        = "FALSE",                                   // PCIe async mode
+    parameter PCIE_PLL_SEL         = "CPLL",                                    // PCIe PLL select for Gen1/Gen2 only
+    parameter PCIE_AUX_CDR_GEN3_EN = "TRUE",                                    // PCIe AUX CDR Gen3 enable
+    parameter PCIE_TXBUF_EN        = "FALSE",                                   // PCIe TX buffer enable for Gen1/Gen2 only
+    parameter PCIE_RXBUF_EN        = "TRUE",                                    // PCIe RX buffer enable for Gen3      only
+    parameter PCIE_TXSYNC_MODE     = 0,                                         // PCIe TX sync mode
+    parameter PCIE_RXSYNC_MODE     = 0,                                         // PCIe RX sync mode
+    parameter LOAD_CNT_MAX         = 2'd1,                                      // Load max count
+    parameter INDEX_MAX            = 5'd21                                      // Index max count
+    
+)
+
+(
+    
+    //---------- Input -------------------------------------
+    input               DRP_CLK,
+    input               DRP_RST_N,
+    input               DRP_GTXRESET,
+    input       [ 1:0]  DRP_RATE,
+    input               DRP_X16X20_MODE,
+    input               DRP_X16,
+    input               DRP_START,
+    input       [15:0]  DRP_DO,
+    input               DRP_RDY,
+    
+    //---------- Output ------------------------------------
+    output      [ 8:0]  DRP_ADDR,
+    output              DRP_EN,  
+    output      [15:0]  DRP_DI,   
+    output              DRP_WE,
+    output              DRP_DONE,
+    output      [ 2:0]  DRP_FSM
+    
+);
+
+    //---------- Input Registers ---------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 gtxreset_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 1:0]  rate_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 x16x20_mode_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 x16_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 start_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [15:0]  do_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rdy_reg1;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 gtxreset_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 1:0]  rate_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 x16x20_mode_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 x16_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 start_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [15:0]  do_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rdy_reg2;
+    
+    //---------- Internal Signals --------------------------
+    reg         [ 1:0]  load_cnt =  2'd0;
+    reg         [ 4:0]  index    =  5'd0;
+    reg                 mode     =  1'd0;
+    reg         [ 8:0]  addr_reg =  9'd0;
+    reg         [15:0]  di_reg   = 16'd0;
+    
+    //---------- Output Registers --------------------------
+    reg                 done     =  1'd0;
+    reg         [ 2:0]  fsm      =  0;      
+                        
+    //---------- DRP Address -------------------------------
+    //  DRP access for *RXCDR_EIDLE includes 
+    //    - [11] RXCDR_HOLD_DURING_EIDLE
+    //    - [12] RXCDR_FR_RESET_ON_EIDLE
+    //    - [13] RXCDR_PH_RESET_ON_EIDLE
+    //------------------------------------------------------
+    localparam          ADDR_PCS_RSVD_ATTR        = 9'h06F;
+    localparam          ADDR_TXOUT_DIV            = 9'h088;
+    localparam          ADDR_RXOUT_DIV            = 9'h088;
+    localparam          ADDR_TX_DATA_WIDTH        = 9'h06B;            
+    localparam          ADDR_TX_INT_DATAWIDTH     = 9'h06B;         
+    localparam          ADDR_RX_DATA_WIDTH        = 9'h011;            
+    localparam          ADDR_RX_INT_DATAWIDTH     = 9'h011;              
+    localparam          ADDR_TXBUF_EN             = 9'h01C;           
+    localparam          ADDR_RXBUF_EN             = 9'h09D;
+    localparam          ADDR_TX_XCLK_SEL          = 9'h059;
+    localparam          ADDR_RX_XCLK_SEL          = 9'h059;                 
+    localparam          ADDR_CLK_CORRECT_USE      = 9'h044; 
+    localparam          ADDR_TX_DRIVE_MODE        = 9'h019;
+    localparam          ADDR_RXCDR_EIDLE          = 9'h0A7;  
+    localparam          ADDR_RX_DFE_LPM_EIDLE     = 9'h01E;
+    localparam          ADDR_PMA_RSV_A            = 9'h099;
+    localparam          ADDR_PMA_RSV_B            = 9'h09A;
+    localparam          ADDR_RXCDR_CFG_A          = 9'h0A8;
+    localparam          ADDR_RXCDR_CFG_B          = 9'h0A9;
+    localparam          ADDR_RXCDR_CFG_C          = 9'h0AA;
+    localparam          ADDR_RXCDR_CFG_D          = 9'h0AB;
+    localparam          ADDR_RXCDR_CFG_E          = 9'h0AC;
+    localparam          ADDR_RXCDR_CFG_F          = 9'h0AD;  // GTH only
+    
+    //---------- DRP Mask ----------------------------------
+    localparam          MASK_PCS_RSVD_ATTR        = 16'b1111111111111001;  // Unmask bit [ 2: 1]
+    localparam          MASK_TXOUT_DIV            = 16'b1111111110001111;  // Unmask bit [ 6: 4]
+    localparam          MASK_RXOUT_DIV            = 16'b1111111111111000;  // Unmask bit [ 2: 0]
+    localparam          MASK_TX_DATA_WIDTH        = 16'b1111111111111000;  // Unmask bit [ 2: 0]   
+    localparam          MASK_TX_INT_DATAWIDTH     = 16'b1111111111101111;  // Unmask bit [    4]
+    localparam          MASK_RX_DATA_WIDTH        = 16'b1100011111111111;  // Unmask bit [13:11]  
+    localparam          MASK_X16X20_RX_DATA_WIDTH = 16'b1111011111111111;  // Unmask bit [   11] // for x16 or x20 mode only 
+    localparam          MASK_RX_INT_DATAWIDTH     = 16'b1011111111111111;  // Unmask bit [   14]  
+    localparam          MASK_TXBUF_EN             = 16'b1011111111111111;  // Unmask bit [   14]  
+    localparam          MASK_RXBUF_EN             = 16'b1111111111111101;  // Unmask bit [    1] 
+    localparam          MASK_TX_XCLK_SEL          = 16'b1111111101111111;  // Unmask bit [    7]    
+    localparam          MASK_RX_XCLK_SEL          = 16'b1111111110111111;  // Unmask bit [    6]       
+    localparam          MASK_CLK_CORRECT_USE      = 16'b1011111111111111;  // Unmask bit [   14]
+    localparam          MASK_TX_DRIVE_MODE        = 16'b1111111111100000;  // Unmask bit [  4:0]      
+    localparam          MASK_RXCDR_EIDLE          = 16'b1111011111111111;  // Unmask bit [   11]  
+    localparam          MASK_RX_DFE_LPM_EIDLE     = 16'b1011111111111111;  // Unmask bit [   14] 
+    localparam          MASK_PMA_RSV_A            = 16'b0000000000000000;  // Unmask bit [15: 0]
+    localparam          MASK_PMA_RSV_B            = 16'b0000000000000000;  // Unmask bit [15: 0]
+    localparam          MASK_RXCDR_CFG_A          = 16'b0000000000000000;  // Unmask bit [15: 0]
+    localparam          MASK_RXCDR_CFG_B          = 16'b0000000000000000;  // Unmask bit [15: 0]
+    localparam          MASK_RXCDR_CFG_C          = 16'b0000000000000000;  // Unmask bit [15: 0]    
+    localparam          MASK_RXCDR_CFG_D          = 16'b0000000000000000;  // Unmask bit [15: 0]  
+    localparam          MASK_RXCDR_CFG_E_GTX      = 16'b1111111100000000;  // Unmask bit [ 7: 0]   
+    localparam          MASK_RXCDR_CFG_E_GTH      = 16'b0000000000000000;  // Unmask bit [15: 0] 
+    localparam          MASK_RXCDR_CFG_F_GTX      = 16'b1111111111111111;  // Unmask bit [     ] 
+    localparam          MASK_RXCDR_CFG_F_GTH      = 16'b1111111111111000;  // Unmask bit [ 2: 0]
+         
+    //---------- DRP Data for PCIe Gen1 and Gen2 -----------
+    localparam          GEN12_TXOUT_DIV           = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000100000 : 16'b0000000000010000;  // Divide by 4 or 2
+    localparam          GEN12_RXOUT_DIV           = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000010 : 16'b0000000000000001;  // Divide by 4 or 2
+    localparam          GEN12_TX_DATA_WIDTH       = 16'b0000000000000011;  // 2-byte (16-bit) external data width   
+    localparam          GEN12_TX_INT_DATAWIDTH    = 16'b0000000000000000;  // 2-byte (20-bit) internal data width
+    localparam          GEN12_RX_DATA_WIDTH       = 16'b0001100000000000;  // 2-byte (16-bit) external data width
+    localparam          GEN12_RX_INT_DATAWIDTH    = 16'b0000000000000000;  // 2-byte (20-bit) internal data width
+    localparam          GEN12_TXBUF_EN            = 16'b0100000000000000;  // Use TX buffer if PCIE_TXBUF_EN == "TRUE"
+    localparam          GEN12_RXBUF_EN            = 16'b0000000000000010;  // Use RX buffer 
+    localparam          GEN12_TX_XCLK_SEL         = 16'b0000000000000000;  // Use TXOUT if PCIE_TXBUF_EN == "TRUE"
+    localparam          GEN12_RX_XCLK_SEL         = 16'b0000000000000000;  // Use RXREC  
+    localparam          GEN12_CLK_CORRECT_USE     = 16'b0100000000000000;  // Use clock correction
+    localparam          GEN12_TX_DRIVE_MODE       = 16'b0000000000000001;  // Use PIPE   Gen1 and Gen2 mode    
+    localparam          GEN12_RXCDR_EIDLE         = 16'b0000100000000000;  // Hold RXCDR during electrical idle 
+    localparam          GEN12_RX_DFE_LPM_EIDLE    = 16'b0100000000000000;  // Hold RX DFE or LPM during electrical idle
+    localparam          GEN12_PMA_RSV_A_GTX       = 16'b1000010010000000;  // 16'h8480
+    localparam          GEN12_PMA_RSV_B_GTX       = 16'b0000000000000001;  // 16'h0001
+    localparam          GEN12_PMA_RSV_A_GTH       = 16'b0000000000001000;  // 16'h0008
+    localparam          GEN12_PMA_RSV_B_GTH       = 16'b0000000000000000;  // 16'h0000
+    //----------
+    localparam          GEN12_RXCDR_CFG_A_GTX     = 16'h0020;              // 16'h0020
+    localparam          GEN12_RXCDR_CFG_B_GTX     = 16'h1020;              // 16'h1020
+    localparam          GEN12_RXCDR_CFG_C_GTX     = 16'h23FF;              // 16'h23FF
+    localparam          GEN12_RXCDR_CFG_D_GTX_S   = 16'h0000;              // 16'h0000 Sync
+    localparam          GEN12_RXCDR_CFG_D_GTX_A   = 16'h8000;              // 16'h8000 Async    
+    localparam          GEN12_RXCDR_CFG_E_GTX     = 16'h0003;              // 16'h0003
+    localparam          GEN12_RXCDR_CFG_F_GTX     = 16'h0000;              // 16'h0000
+    //----------
+    localparam          GEN12_RXCDR_CFG_A_GTH_S   = 16'h0018;              // 16'h0018 Sync
+    localparam          GEN12_RXCDR_CFG_A_GTH_A   = 16'h8018;              // 16'h8018 Async
+    localparam          GEN12_RXCDR_CFG_B_GTH     = 16'hC208;              // 16'hC208
+    localparam          GEN12_RXCDR_CFG_C_GTH     = 16'h2000;              // 16'h2000
+    localparam          GEN12_RXCDR_CFG_D_GTH     = 16'h07FE;              // 16'h07FE
+    localparam          GEN12_RXCDR_CFG_E_GTH     = 16'h0020;              // 16'h0020
+    localparam          GEN12_RXCDR_CFG_F_GTH     = 16'h0000;              // 16'h0000  
+    
+    //---------- DRP Data for PCIe Gen3 --------------------                 
+    localparam          GEN3_TXOUT_DIV            = 16'b0000000000000000;  // Divide by 1
+    localparam          GEN3_RXOUT_DIV            = 16'b0000000000000000;  // Divide by 1
+    localparam          GEN3_TX_DATA_WIDTH        = 16'b0000000000000100;  // 4-byte (32-bit) external data width                     
+    localparam          GEN3_TX_INT_DATAWIDTH     = 16'b0000000000010000;  // 4-byte (32-bit) internal data width               
+    localparam          GEN3_RX_DATA_WIDTH        = 16'b0010000000000000;  // 4-byte (32-bit) external data width                  
+    localparam          GEN3_RX_INT_DATAWIDTH     = 16'b0100000000000000;  // 4-byte (32-bit) internal data width               
+    localparam          GEN3_TXBUF_EN             = 16'b0000000000000000;  // Bypass TX buffer 
+    localparam          GEN3_RXBUF_EN             = 16'b0000000000000000;  // Bypass RX buffer  
+    localparam          GEN3_TX_XCLK_SEL          = 16'b0000000010000000;  // Use TXUSR  
+    localparam          GEN3_RX_XCLK_SEL          = 16'b0000000001000000;  // Use RXUSR                         
+    localparam          GEN3_CLK_CORRECT_USE      = 16'b0000000000000000;  // Bypass clock correction  
+    localparam          GEN3_TX_DRIVE_MODE        = 16'b0000000000000010;  // Use PIPE Gen3 mode   
+    localparam          GEN3_RXCDR_EIDLE          = 16'b0000000000000000;  // Disable Hold RXCDR during electrical idle 
+    localparam          GEN3_RX_DFE_LPM_EIDLE     = 16'b0000000000000000;  // Disable RX DFE or LPM during electrical idle   
+    localparam          GEN3_PMA_RSV_A_GTX        = 16'b0111000010000000;  // 16'h7080
+    localparam          GEN3_PMA_RSV_B_GTX        = 16'b0000000000011110;  // 16'h001E
+    localparam          GEN3_PMA_RSV_A_GTH        = 16'b0000000000001000;  // 16'h0008
+    localparam          GEN3_PMA_RSV_B_GTH        = 16'b0000000000000000;  // 16'h0000   
+    //---------- 
+    localparam          GEN3_RXCDR_CFG_A_GTX      = 16'h0080;              // 16'h0080
+    localparam          GEN3_RXCDR_CFG_B_GTX      = 16'h1010;              // 16'h1010
+    localparam          GEN3_RXCDR_CFG_C_GTX      = 16'h0BFF;              // 16'h0BFF
+    localparam          GEN3_RXCDR_CFG_D_GTX_S    = 16'h0000;              // 16'h0000 Sync
+    localparam          GEN3_RXCDR_CFG_D_GTX_A    = 16'h8000;              // 16'h8000 Async    
+    localparam          GEN3_RXCDR_CFG_E_GTX      = 16'h000B;              // 16'h000B
+    localparam          GEN3_RXCDR_CFG_F_GTX      = 16'h0000;              // 16'h0000
+    //----------                                 
+  //localparam          GEN3_RXCDR_CFG_A_GTH_S    = 16'h0018;              // 16'h0018 Sync
+  //localparam          GEN3_RXCDR_CFG_A_GTH_A    = 16'h8018;              // 16'h8018 Async
+  //localparam          GEN3_RXCDR_CFG_B_GTH      = 16'hC208;              // 16'hC848
+  //localparam          GEN3_RXCDR_CFG_C_GTH      = 16'h2000;              // 16'h1000
+  //localparam          GEN3_RXCDR_CFG_D_GTH      = 16'h07FE;              // 16'h07FE v1.0 silicon
+  //localparam          GEN3_RXCDR_CFG_D_GTH_AUX  = 16'h0FFE;              // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
+  //localparam          GEN3_RXCDR_CFG_E_GTH      = 16'h0020;              // 16'h0010
+  //localparam          GEN3_RXCDR_CFG_F_GTH      = 16'h0000;              // 16'h0000 v1.0 silicon
+  //localparam          GEN3_RXCDR_CFG_F_GTH_AUX  = 16'h0002;              // 16'h0000 v2.0 silicon, [81] AUX CDR enable
+    //----------                                 
+    localparam          GEN3_RXCDR_CFG_A_GTH_S    = 16'h0018;              // 16'h0018 Sync
+    localparam          GEN3_RXCDR_CFG_A_GTH_A    = 16'h8018;              // 16'h8018 Async
+    localparam          GEN3_RXCDR_CFG_B_GTH      = 16'hC848;              // 16'hC848
+    localparam          GEN3_RXCDR_CFG_C_GTH      = 16'h1000;              // 16'h1000
+    localparam          GEN3_RXCDR_CFG_D_GTH      = 16'h07FE;              // 16'h07FE v1.0 silicon
+    localparam          GEN3_RXCDR_CFG_D_GTH_AUX  = 16'h0FFE;              // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
+    localparam          GEN3_RXCDR_CFG_E_GTH      = 16'h0010;              // 16'h0010
+    localparam          GEN3_RXCDR_CFG_F_GTH      = 16'h0000;              // 16'h0000 v1.0 silicon
+    localparam          GEN3_RXCDR_CFG_F_GTH_AUX  = 16'h0002;              // 16'h0000 v2.0 silicon, [81] AUX CDR enable
+      
+    //---------- DRP Data for PCIe Gen1, Gen2 and Gen3 -----    
+    localparam          GEN123_PCS_RSVD_ATTR_A    = 16'b0000000000000000;  // Auto TX and RX sync mode
+    localparam          GEN123_PCS_RSVD_ATTR_M_TX = 16'b0000000000000010;  // Manual TX sync mode
+    localparam          GEN123_PCS_RSVD_ATTR_M_RX = 16'b0000000000000100;  // Manual RX sync mode
+      
+    //---------- DRP Data for x16 --------------------------
+    localparam          X16_RX_DATAWIDTH   = 16'b0000000000000000;  // 2-byte (16-bit) internal data width
+    
+    //---------- DRP Data for x20 --------------------------                                  
+    localparam          X20_RX_DATAWIDTH   = 16'b0000100000000000;  // 2-byte (20-bit) internal data width       
+      
+    //---------- DRP Data ----------------------------------     
+    wire        [15:0]  data_txout_div;
+    wire        [15:0]  data_rxout_div;
+    wire        [15:0]  data_tx_data_width;               
+    wire        [15:0]  data_tx_int_datawidth;            
+    wire        [15:0]  data_rx_data_width;               
+    wire        [15:0]  data_rx_int_datawidth;                
+    wire        [15:0]  data_txbuf_en;        
+    wire        [15:0]  data_rxbuf_en;        
+    wire        [15:0]  data_tx_xclk_sel;
+    wire        [15:0]  data_rx_xclk_sel;            
+    wire        [15:0]  data_clk_correction_use; 
+    wire        [15:0]  data_tx_drive_mode;
+    wire        [15:0]  data_rxcdr_eidle;
+    wire        [15:0]  data_rx_dfe_lpm_eidle;
+    wire        [15:0]  data_pma_rsv_a;
+    wire        [15:0]  data_pma_rsv_b;
+    
+    wire        [15:0]  data_rxcdr_cfg_a;
+    wire        [15:0]  data_rxcdr_cfg_b; 
+    wire        [15:0]  data_rxcdr_cfg_c;
+    wire        [15:0]  data_rxcdr_cfg_d; 
+    wire        [15:0]  data_rxcdr_cfg_e;
+    wire        [15:0]  data_rxcdr_cfg_f;
+        
+    wire        [15:0]  data_pcs_rsvd_attr_a;  
+    wire        [15:0]  data_pcs_rsvd_attr_m_tx; 
+    wire        [15:0]  data_pcs_rsvd_attr_m_rx; 
+    wire        [15:0]  data_pcs_rsvd_attr_m;   
+                
+    wire        [15:0]  data_x16x20_rx_datawidth;    
+           
+    //---------- FSM ---------------------------------------  
+    localparam          FSM_IDLE  = 0;  
+    localparam          FSM_LOAD  = 1;                           
+    localparam          FSM_READ  = 2;
+    localparam          FSM_RRDY  = 3;
+    localparam          FSM_WRITE = 4;
+    localparam          FSM_WRDY  = 5;    
+    localparam          FSM_DONE  = 6;   
+
+    
+    
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        begin
+        //---------- 1st Stage FF --------------------------
+        gtxreset_reg1    <=  1'd0;
+        rate_reg1        <=  2'd0;
+        x16x20_mode_reg1 <=  1'd0;
+        x16_reg1         <=  1'd0;
+        do_reg1          <= 16'd0;
+        rdy_reg1         <=  1'd0;
+        start_reg1       <=  1'd0;
+        //---------- 2nd Stage FF --------------------------
+        gtxreset_reg2    <=  1'd0;
+        rate_reg2        <=  2'd0;
+        x16x20_mode_reg2 <=  1'd0;
+        x16_reg2         <=  1'd0;
+        do_reg2          <= 16'd0;
+        rdy_reg2         <=  1'd0;
+        start_reg2       <=  1'd0;
+        end
+        
+    else
+        begin
+        //---------- 1st Stage FF --------------------------
+        gtxreset_reg1    <= DRP_GTXRESET;
+        rate_reg1        <= DRP_RATE;
+        x16x20_mode_reg1 <= DRP_X16X20_MODE;
+        x16_reg1         <= DRP_X16;
+        do_reg1          <= DRP_DO;
+        rdy_reg1         <= DRP_RDY;
+        start_reg1       <= DRP_START;
+        //---------- 2nd Stage FF --------------------------
+        gtxreset_reg2    <= gtxreset_reg1;
+        rate_reg2        <= rate_reg1;
+        x16x20_mode_reg2 <= x16x20_mode_reg1;
+        x16_reg2         <= x16_reg1;
+        do_reg2          <= do_reg1;
+        rdy_reg2         <= rdy_reg1;
+        start_reg2       <= start_reg1;
+        end
+    
+end  
+
+
+
+//---------- Select DRP Data ---------------------------------------------------
+assign data_txout_div          =  (rate_reg2 == 2'd2)                                ? GEN3_TXOUT_DIV        : GEN12_TXOUT_DIV;
+assign data_rxout_div          =  (rate_reg2 == 2'd2)                                ? GEN3_RXOUT_DIV        : GEN12_RXOUT_DIV;
+assign data_tx_data_width      =  (rate_reg2 == 2'd2)                                ? GEN3_TX_DATA_WIDTH    : GEN12_TX_DATA_WIDTH;
+assign data_tx_int_datawidth   =  (rate_reg2 == 2'd2)                                ? GEN3_TX_INT_DATAWIDTH : GEN12_TX_INT_DATAWIDTH;
+assign data_rx_data_width      =  (rate_reg2 == 2'd2)                                ? GEN3_RX_DATA_WIDTH    : GEN12_RX_DATA_WIDTH;
+
+assign data_rx_int_datawidth   =  (rate_reg2 == 2'd2)                                ? GEN3_RX_INT_DATAWIDTH : GEN12_RX_INT_DATAWIDTH;
+
+assign data_txbuf_en           = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TXBUF_EN         : GEN12_TXBUF_EN;
+assign data_rxbuf_en           = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RXBUF_EN         : GEN12_RXBUF_EN;
+assign data_tx_xclk_sel        = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TX_XCLK_SEL      : GEN12_TX_XCLK_SEL;
+assign data_rx_xclk_sel        = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RX_XCLK_SEL      : GEN12_RX_XCLK_SEL;
+assign data_clk_correction_use =  (rate_reg2 == 2'd2)                                ? GEN3_CLK_CORRECT_USE  : GEN12_CLK_CORRECT_USE;
+assign data_tx_drive_mode      =  (rate_reg2 == 2'd2)                                ? GEN3_TX_DRIVE_MODE    : GEN12_TX_DRIVE_MODE;   
+assign data_rxcdr_eidle        =  (rate_reg2 == 2'd2)                                ? GEN3_RXCDR_EIDLE      : GEN12_RXCDR_EIDLE;
+assign data_rx_dfe_lpm_eidle   =  (rate_reg2 == 2'd2)                                ? GEN3_RX_DFE_LPM_EIDLE : GEN12_RX_DFE_LPM_EIDLE;
+assign data_pma_rsv_a          =  (rate_reg2 == 2'd2)                                ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_A_GTH  : GEN3_PMA_RSV_A_GTX) :
+                                                                                       ((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_A_GTH : GEN12_PMA_RSV_A_GTX);
+assign data_pma_rsv_b          =  (rate_reg2 == 2'd2)                                ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_B_GTH  : GEN3_PMA_RSV_B_GTX) :
+                                                                                       ((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_B_GTH : GEN12_PMA_RSV_B_GTX);
+
+assign data_rxcdr_cfg_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_A_GTH_A  : GEN3_RXCDR_CFG_A_GTH_S)  : GEN3_RXCDR_CFG_A_GTX) :
+                                                ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN12_RXCDR_CFG_A_GTH_A : GEN12_RXCDR_CFG_A_GTH_S) : GEN12_RXCDR_CFG_A_GTX);
+
+assign data_rxcdr_cfg_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ?  GEN3_RXCDR_CFG_B_GTH  : GEN3_RXCDR_CFG_B_GTX) :
+                                                ((PCIE_GT_DEVICE == "GTH") ?  GEN12_RXCDR_CFG_B_GTH : GEN12_RXCDR_CFG_B_GTX);
+
+assign data_rxcdr_cfg_c = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ?  GEN3_RXCDR_CFG_C_GTH  : GEN3_RXCDR_CFG_C_GTX) :
+                                                ((PCIE_GT_DEVICE == "GTH") ?  GEN12_RXCDR_CFG_C_GTH : GEN12_RXCDR_CFG_C_GTX);
+                                                
+assign data_rxcdr_cfg_d = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ?  ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTH_AUX : GEN3_RXCDR_CFG_D_GTH) : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S)) :
+                                                ((PCIE_GT_DEVICE == "GTH") ?  GEN12_RXCDR_CFG_D_GTH : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S));
+
+assign data_rxcdr_cfg_e = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ?  GEN3_RXCDR_CFG_E_GTH  : GEN3_RXCDR_CFG_E_GTX) :
+                                                ((PCIE_GT_DEVICE == "GTH") ?  GEN12_RXCDR_CFG_E_GTH : GEN12_RXCDR_CFG_E_GTX);
+                                                
+assign data_rxcdr_cfg_f = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ?  ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_F_GTH_AUX : GEN3_RXCDR_CFG_F_GTH) : GEN3_RXCDR_CFG_F_GTX) :
+                                                ((PCIE_GT_DEVICE == "GTH") ?  GEN12_RXCDR_CFG_F_GTH : GEN12_RXCDR_CFG_F_GTX);
+
+assign data_pcs_rsvd_attr_a    = GEN123_PCS_RSVD_ATTR_A;
+assign data_pcs_rsvd_attr_m_tx = PCIE_TXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_TX;
+assign data_pcs_rsvd_attr_m_rx = PCIE_RXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_RX;
+assign data_pcs_rsvd_attr_m    = data_pcs_rsvd_attr_m_tx | data_pcs_rsvd_attr_m_rx;
+
+assign data_x16x20_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
+
+
+//---------- Load Counter ------------------------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        load_cnt <= 2'd0;
+    else
+    
+        //---------- Increment Load Counter ----------------
+        if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
+            load_cnt <= load_cnt + 2'd1;
+            
+        //---------- Hold Load Counter ---------------------
+        else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
+            load_cnt <= load_cnt;
+            
+        //---------- Reset Load Counter --------------------
+        else
+            load_cnt <= 2'd0;
+        
+end 
+
+
+
+//---------- Update DRP Address and Data ---------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        begin
+        addr_reg <=  9'd0;
+        di_reg   <= 16'd0;
+        end
+    else
+        begin
+        
+        case (index)
+        
+        //--------------------------------------------------      
+        5'd0:     
+            begin
+            addr_reg <= mode             ? ADDR_PCS_RSVD_ATTR : 
+                        x16x20_mode_reg2 ? ADDR_RX_DATA_WIDTH : ADDR_TXOUT_DIV; 
+            di_reg   <= mode             ? ((do_reg2 & MASK_PCS_RSVD_ATTR)        | data_pcs_rsvd_attr_a) : 
+                        x16x20_mode_reg2 ? ((do_reg2 & MASK_X16X20_RX_DATA_WIDTH) | data_x16x20_rx_datawidth) : 
+                                           ((do_reg2 & MASK_TXOUT_DIV)            | data_txout_div);
+            end 
+            
+        //--------------------------------------------------      
+        5'd1:    
+            begin
+            addr_reg <= mode ? ADDR_PCS_RSVD_ATTR : ADDR_RXOUT_DIV;
+            di_reg   <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR)  | data_pcs_rsvd_attr_m) : 
+                               ((do_reg2 & MASK_RXOUT_DIV)      | data_rxout_div);
+            end 
+            
+        //--------------------------------------------------
+        5'd2 :
+            begin        
+            addr_reg <= ADDR_TX_DATA_WIDTH;
+            di_reg   <= (do_reg2 & MASK_TX_DATA_WIDTH) | data_tx_data_width;
+            end
+           
+        //--------------------------------------------------    
+        5'd3 :
+            begin        
+            addr_reg <= ADDR_TX_INT_DATAWIDTH;
+            di_reg   <= (do_reg2 & MASK_TX_INT_DATAWIDTH) | data_tx_int_datawidth;
+            end    
+        
+        //--------------------------------------------------     
+        5'd4 :
+            begin
+            addr_reg <= ADDR_RX_DATA_WIDTH;
+            di_reg   <= (do_reg2 & MASK_RX_DATA_WIDTH) | data_rx_data_width;
+            end   
+        
+        //--------------------------------------------------     
+        5'd5 :
+            begin        
+            addr_reg <= ADDR_RX_INT_DATAWIDTH;
+            di_reg   <= (do_reg2 & MASK_RX_INT_DATAWIDTH) | data_rx_int_datawidth;
+            end  
+  
+        //--------------------------------------------------         
+        5'd6 :
+            begin        
+            addr_reg <= ADDR_TXBUF_EN;
+            di_reg   <= (do_reg2 & MASK_TXBUF_EN) | data_txbuf_en;
+            end   
+        
+        //--------------------------------------------------         
+        5'd7 :
+            begin        
+            addr_reg <= ADDR_RXBUF_EN;
+            di_reg   <= (do_reg2 & MASK_RXBUF_EN) | data_rxbuf_en;
+            end   
+        
+        //--------------------------------------------------         
+        5'd8 :
+            begin        
+            addr_reg <= ADDR_TX_XCLK_SEL;
+            di_reg   <= (do_reg2 & MASK_TX_XCLK_SEL) | data_tx_xclk_sel;
+            end   
+        
+        //--------------------------------------------------         
+        5'd9 :
+            begin        
+            addr_reg <= ADDR_RX_XCLK_SEL;
+            di_reg   <= (do_reg2 & MASK_RX_XCLK_SEL) | data_rx_xclk_sel;
+            end   
+        
+        //--------------------------------------------------      
+        5'd10 :
+            begin
+            addr_reg <= ADDR_CLK_CORRECT_USE;
+            di_reg   <= (do_reg2 & MASK_CLK_CORRECT_USE) | data_clk_correction_use;
+            end 
+
+        //--------------------------------------------------      
+        5'd11 :
+            begin
+            addr_reg <= ADDR_TX_DRIVE_MODE;
+            di_reg   <= (do_reg2 & MASK_TX_DRIVE_MODE) | data_tx_drive_mode;
+            end 
+            
+        //--------------------------------------------------      
+        5'd12 :
+            begin
+            addr_reg <= ADDR_RXCDR_EIDLE;
+            di_reg   <= (do_reg2 & MASK_RXCDR_EIDLE) | data_rxcdr_eidle;
+            end 
+            
+        //--------------------------------------------------      
+        5'd13 :
+            begin
+            addr_reg <= ADDR_RX_DFE_LPM_EIDLE;
+            di_reg   <= (do_reg2 & MASK_RX_DFE_LPM_EIDLE) | data_rx_dfe_lpm_eidle;
+            end     
+            
+        //--------------------------------------------------      
+        5'd14 :
+            begin
+            addr_reg <= ADDR_PMA_RSV_A;
+            di_reg   <= (do_reg2 & MASK_PMA_RSV_A) | data_pma_rsv_a;
+            end  
+            
+        //--------------------------------------------------      
+        5'd15 :
+            begin
+            addr_reg <= ADDR_PMA_RSV_B;
+            di_reg   <= (do_reg2 & MASK_PMA_RSV_B) | data_pma_rsv_b;
+            end 
+
+        //--------------------------------------------------      
+        5'd16 :
+            begin
+            addr_reg <= ADDR_RXCDR_CFG_A;
+            di_reg   <= (do_reg2 & MASK_RXCDR_CFG_A) | data_rxcdr_cfg_a;
+            end 
+            
+        //--------------------------------------------------      
+        5'd17 :
+            begin
+            addr_reg <= ADDR_RXCDR_CFG_B;
+            di_reg   <= (do_reg2 & MASK_RXCDR_CFG_B) | data_rxcdr_cfg_b;
+            end 
+            
+        //--------------------------------------------------      
+        5'd18 :
+            begin
+            addr_reg <= ADDR_RXCDR_CFG_C;
+            di_reg   <= (do_reg2 & MASK_RXCDR_CFG_C) | data_rxcdr_cfg_c;
+            end                         
+
+        //--------------------------------------------------      
+        5'd19 :
+            begin
+            addr_reg <= ADDR_RXCDR_CFG_D;
+            di_reg   <= (do_reg2 & MASK_RXCDR_CFG_D) | data_rxcdr_cfg_d;
+            end    
+            
+        //--------------------------------------------------      
+        5'd20 :
+            begin
+            addr_reg <= ADDR_RXCDR_CFG_E;
+            di_reg   <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_E_GTH : MASK_RXCDR_CFG_E_GTX)) | data_rxcdr_cfg_e;
+            end             
+            
+        //--------------------------------------------------      
+        5'd21 :
+            begin
+            addr_reg <= ADDR_RXCDR_CFG_F;
+            di_reg   <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_F_GTH : MASK_RXCDR_CFG_F_GTX)) | data_rxcdr_cfg_f;
+            end             
+            
+        //--------------------------------------------------
+        default : 
+            begin
+            addr_reg <=  9'd0;
+            di_reg   <= 16'd0;
+            end
+            
+        endcase
+        
+        end
+        
+end  
+
+
+
+//---------- PIPE DRP FSM ------------------------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        begin
+        fsm   <= FSM_IDLE;
+        index <= 5'd0;
+        mode  <= 1'd0;
+        done  <= 1'd0;
+        end
+    else
+        begin
+        
+        case (fsm)
+
+        //---------- Idle State ----------------------------
+        FSM_IDLE :  
+          
+            begin
+            //---------- Reset or Rate Change --------------
+            if (start_reg2)
+                begin
+                fsm   <= FSM_LOAD;
+                index <= 5'd0;
+                mode  <= 1'd0;
+                done  <= 1'd0; 
+                end
+            //---------- GTXRESET --------------------------    
+            else if ((gtxreset_reg2 && !gtxreset_reg1) && ((PCIE_TXSYNC_MODE == 0) || (PCIE_RXSYNC_MODE == 0)) && (PCIE_USE_MODE == "1.0"))
+                begin
+                fsm   <= FSM_LOAD;
+                index <= 5'd0;
+                mode  <= 1'd1;
+                done  <= 1'd0;
+                end
+            //---------- Idle ------------------------------
+            else       
+                begin
+                fsm   <= FSM_IDLE;
+                index <= 5'd0;
+                mode  <= 1'd0;
+                done  <= 1'd1;
+                end 
+            end    
+            
+        //---------- Load DRP Address  ---------------------
+        FSM_LOAD :
+        
+            begin
+            fsm   <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
+            index <= index;
+            mode  <= mode;
+            done  <= 1'd0;
+            end  
+            
+        //---------- Read DRP ------------------------------
+        FSM_READ :
+        
+            begin
+            fsm   <= FSM_RRDY;
+            index <= index;
+            mode  <= mode;
+            done  <= 1'd0;
+            end
+            
+        //---------- Read DRP Ready ------------------------
+        FSM_RRDY :    
+        
+            begin
+            fsm   <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
+            index <= index;
+            mode  <= mode;
+            done  <= 1'd0;
+            end
+  
+            
+        //---------- Write DRP -----------------------------
+        FSM_WRITE :    
+        
+            begin
+            fsm   <= FSM_WRDY;
+            index <= index;
+            mode  <= mode;
+            done  <= 1'd0;
+            end       
+            
+        //---------- Write DRP Ready -----------------------
+        FSM_WRDY :    
+        
+            begin
+            fsm   <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
+            index <= index;
+            mode  <= mode;
+            done  <= 1'd0;
+            end        
+             
+        //---------- DRP Done ------------------------------
+        FSM_DONE :
+        
+            begin
+            if ((index == INDEX_MAX) || (mode && (index == 5'd1)) || (x16x20_mode_reg2 && (index == 5'd0)))
+                begin
+                fsm   <= FSM_IDLE;
+                index <= 5'd0;
+                mode  <= 1'd0;
+                done  <= 1'd0;
+                end
+            else       
+                begin
+                fsm   <= FSM_LOAD;
+                index <= index + 5'd1;
+                mode  <= mode;
+                done  <= 1'd0;
+                end
+            end     
+              
+        //---------- Default State -------------------------
+        default :
+        
+            begin      
+            fsm   <= FSM_IDLE;
+            index <= 5'd0;
+            mode  <= 1'd0;
+            done  <= 1'd0;
+            end
+            
+        endcase
+        
+        end
+        
+end 
+
+
+
+//---------- PIPE DRP Output ---------------------------------------------------
+assign DRP_ADDR = addr_reg;
+assign DRP_EN   = (fsm == FSM_READ) || (fsm == FSM_WRITE);
+assign DRP_DI   = di_reg;
+assign DRP_WE   = (fsm == FSM_WRITE);
+assign DRP_DONE = done;
+assign DRP_FSM  = fsm;
+
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pipe_eq.v

@@ -0,0 +1,830 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pipe_eq.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  pipe_eq.v
+//  Description  :  PIPE Equalization Module for 7 Series Transceiver
+//  Version      :  20.1
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- PIPE Equalization Module ------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_pipe_eq #
+(
+    parameter PCIE_SIM_MODE       = "FALSE",
+    parameter PCIE_GT_DEVICE      = "GTX",
+    parameter PCIE_RXEQ_MODE_GEN3 = 1
+)
+
+(
+
+    //---------- Input -------------------------------------
+    input               EQ_CLK,                            
+    input               EQ_RST_N,
+    input               EQ_GEN3,
+
+    input       [ 1:0]  EQ_TXEQ_CONTROL,    
+    input       [ 3:0]  EQ_TXEQ_PRESET,
+    input       [ 3:0]  EQ_TXEQ_PRESET_DEFAULT,
+    input       [ 5:0]  EQ_TXEQ_DEEMPH_IN,
+                                
+    input       [ 1:0]  EQ_RXEQ_CONTROL,  
+    input       [ 2:0]  EQ_RXEQ_PRESET,
+    input       [ 5:0]  EQ_RXEQ_LFFS,  
+    input       [ 3:0]  EQ_RXEQ_TXPRESET,
+    input               EQ_RXEQ_USER_EN,
+    input       [17:0]  EQ_RXEQ_USER_TXCOEFF,
+    input               EQ_RXEQ_USER_MODE, 
+    
+    
+    //---------- Output ------------------------------------
+    output              EQ_TXEQ_DEEMPH,
+    output      [ 4:0]  EQ_TXEQ_PRECURSOR,
+    output      [ 6:0]  EQ_TXEQ_MAINCURSOR,
+    output      [ 4:0]  EQ_TXEQ_POSTCURSOR,
+    output      [17:0]  EQ_TXEQ_DEEMPH_OUT,
+    output              EQ_TXEQ_DONE,
+    output      [ 5:0]  EQ_TXEQ_FSM,
+    
+    output      [17:0]  EQ_RXEQ_NEW_TXCOEFF,
+    output              EQ_RXEQ_LFFS_SEL,
+    output              EQ_RXEQ_ADAPT_DONE,
+    output              EQ_RXEQ_DONE, 
+    output      [ 5:0]  EQ_RXEQ_FSM
+
+);          
+
+    //---------- Input Registers ---------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 gen3_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 gen3_reg2;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 1:0]  txeq_control_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 3:0]  txeq_preset_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 5:0]  txeq_deemph_reg1;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 1:0]  txeq_control_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg	      [ 3:0]  txeq_preset_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 5:0]  txeq_deemph_reg2;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 1:0]  rxeq_control_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg	      [ 2:0]  rxeq_preset_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 5:0]  rxeq_lffs_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 3:0]  rxeq_txpreset_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxeq_user_en_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [17:0]  rxeq_user_txcoeff_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxeq_user_mode_reg1;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 1:0]  rxeq_control_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg	      [ 2:0]  rxeq_preset_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 5:0]  rxeq_lffs_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 3:0]  rxeq_txpreset_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxeq_user_en_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [17:0]  rxeq_user_txcoeff_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxeq_user_mode_reg2;
+    
+    //---------- Internal Signals --------------------------
+    reg         [18:0]  txeq_preset          = 19'd0;          
+    reg                 txeq_preset_done     =  1'd0;
+    reg         [ 1:0]  txeq_txcoeff_cnt     =  2'd0;
+    
+    reg         [ 2:0]  rxeq_preset          =  3'd0;
+    reg                 rxeq_preset_valid    =  1'd0;
+    reg         [ 3:0]  rxeq_txpreset        =  4'd0;
+    reg         [17:0]  rxeq_txcoeff         = 18'd0; 
+    reg         [ 2:0]  rxeq_cnt             =  3'd0;
+    reg         [ 5:0]  rxeq_fs              =  6'd0;
+    reg         [ 5:0]  rxeq_lf              =  6'd0;
+    reg                 rxeq_new_txcoeff_req =  1'd0;
+   
+    //---------- Output Registers --------------------------     
+    reg         [18:0]  txeq_txcoeff        = 19'd0;
+    reg                 txeq_done           =  1'd0;
+    reg         [ 5:0]  fsm_tx              =  6'd0;
+   
+    reg         [17:0]  rxeq_new_txcoeff    = 18'd0;
+    reg                 rxeq_lffs_sel       =  1'd0;
+    reg                 rxeq_adapt_done_reg =  1'd0;
+    reg                 rxeq_adapt_done     =  1'd0;
+    reg                 rxeq_done           =  1'd0; 
+    reg         [ 5:0]  fsm_rx              =  6'd0;    
+    
+    //---------- RXEQ Eye Scan Module Output ---------------
+    wire                rxeqscan_lffs_sel;
+    wire                rxeqscan_preset_done;
+    wire        [17:0]  rxeqscan_new_txcoeff;
+    wire                rxeqscan_new_txcoeff_done;
+    wire                rxeqscan_adapt_done;
+                  
+    //---------- FSM ---------------------------------------   
+    localparam          FSM_TXEQ_IDLE            = 6'b000001; 
+    localparam          FSM_TXEQ_PRESET          = 6'b000010;                                     
+    localparam          FSM_TXEQ_TXCOEFF         = 6'b000100;
+    localparam          FSM_TXEQ_REMAP           = 6'b001000;
+    localparam          FSM_TXEQ_QUERY           = 6'b010000;                                     
+    localparam          FSM_TXEQ_DONE            = 6'b100000;
+                                          
+    localparam          FSM_RXEQ_IDLE            = 6'b000001; 
+    localparam          FSM_RXEQ_PRESET          = 6'b000010;                                     
+    localparam          FSM_RXEQ_TXCOEFF         = 6'b000100;
+    localparam          FSM_RXEQ_LF              = 6'b001000;
+    localparam          FSM_RXEQ_NEW_TXCOEFF_REQ = 6'b010000;                                  
+    localparam          FSM_RXEQ_DONE            = 6'b100000;
+                
+    //---------- TXEQ Presets Look-up Table ----------------
+    // TXPRECURSOR  = Coefficient range between  0 and 20 units 
+    // TXMAINCURSOR = Coefficient range between 29 and 80 units
+    // TXPOSTCURSOR = Coefficient range between  0 and 31 units
+    //------------------------------------------------------
+    // Actual    Full Swing    (FS) = 80
+    // Actual    Low Frequency (LF) = 29
+    // Advertise Full Swing    (FS) = 40
+    // Advertise Low Frequency (LF) = 15
+    //------------------------------------------------------
+    // Pre-emphasis  = 20 log [80 - (2 * TXPRECURSOR)] / 80], assuming no de-emphasis
+    // Main-emphasis = 80 - (TXPRECURSOR + TXPOSTCURSOR)
+    // De-emphasis   = 20 log [80 - (2 *  TXPOSTCURSOR)] / 80], assuming no pre-emphasis
+    //------------------------------------------------------    
+    // Note:  TXMAINCURSOR calculated internally in GT
+    //------------------------------------------------------                           
+    localparam          TXPRECURSOR_00  = 6'd0;             //  0.0 dB
+    localparam          TXMAINCURSOR_00 = 7'd60;                                
+    localparam          TXPOSTCURSOR_00 = 6'd20;            // -6.0 +/- 1 dB
+    
+    localparam          TXPRECURSOR_01  = 6'd0;             //  0.0 dB
+    localparam          TXMAINCURSOR_01 = 7'd68;            // added 1 to compensate decimal                                
+    localparam          TXPOSTCURSOR_01 = 6'd13;            // -3.5 +/- 1 dB
+    
+    localparam          TXPRECURSOR_02  = 6'd0;             //  0.0 dB
+    localparam          TXMAINCURSOR_02 = 7'd64;                                
+    localparam          TXPOSTCURSOR_02 = 6'd16;            // -4.4 +/- 1.5 dB
+    
+    localparam          TXPRECURSOR_03  = 6'd0;             //  0.0 dB
+    localparam          TXMAINCURSOR_03 = 7'd70;                                
+    localparam          TXPOSTCURSOR_03 = 6'd10;            // -2.5 +/- 1 dB
+
+    localparam          TXPRECURSOR_04  = 6'd0;             //  0.0 dB
+    localparam          TXMAINCURSOR_04 = 7'd80;                                
+    localparam          TXPOSTCURSOR_04 = 6'd0;             //  0.0 dB
+    
+    localparam          TXPRECURSOR_05  = 6'd8;             // -1.9 +/- 1 dB
+    localparam          TXMAINCURSOR_05 = 7'd72;                                
+    localparam          TXPOSTCURSOR_05 = 6'd0;             //  0.0 dB
+    
+    localparam          TXPRECURSOR_06  = 6'd10;            // -2.5 +/- 1 dB
+    localparam          TXMAINCURSOR_06 = 7'd70;                                
+    localparam          TXPOSTCURSOR_06 = 6'd0;             //  0.0 dB
+    
+    localparam          TXPRECURSOR_07  = 6'd8;             // -3.5 +/- 1 dB
+    localparam          TXMAINCURSOR_07 = 7'd56;                                
+    localparam          TXPOSTCURSOR_07 = 6'd16;            // -6.0 +/- 1 dB
+        
+    localparam          TXPRECURSOR_08  = 6'd10;            // -3.5 +/- 1 dB
+    localparam          TXMAINCURSOR_08 = 7'd60;                                
+    localparam          TXPOSTCURSOR_08 = 6'd10;            // -3.5 +/- 1 dB
+    
+    localparam          TXPRECURSOR_09  = 6'd13;            // -3.5 +/- 1 dB
+    localparam          TXMAINCURSOR_09 = 7'd68;            //  added 1 to compensate decimal                  
+    localparam          TXPOSTCURSOR_09 = 6'd0;             //  0.0 dB
+    
+    localparam          TXPRECURSOR_10  = 6'd0;             //  0.0 dB
+    localparam          TXMAINCURSOR_10 = 7'd56;            //  added 1 to compensate decimal                     
+    localparam          TXPOSTCURSOR_10 = 6'd25;            //  9.5 +/- 1 dB, updated for coefficient rules
+    
+    
+    
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge EQ_CLK)
+begin
+
+    if (!EQ_RST_N)
+        begin   
+        //---------- 1st Stage FF --------------------------  
+        gen3_reg1              <=  1'd0;
+                                  
+        txeq_control_reg1      <=  2'd0;
+        txeq_preset_reg1       <=  4'd0;
+        txeq_deemph_reg1       <=  6'd1;
+                                  
+        rxeq_control_reg1      <=  2'd0;
+        rxeq_preset_reg1       <=  3'd0;
+        rxeq_lffs_reg1         <=  6'd0;
+        rxeq_txpreset_reg1     <=  4'd0;
+        rxeq_user_en_reg1      <=  1'd0;
+        rxeq_user_txcoeff_reg1 <= 18'd0;
+        rxeq_user_mode_reg1    <=  1'd0;
+        //---------- 2nd Stage FF --------------------------
+        gen3_reg2              <=  1'd0;
+                                   
+        txeq_control_reg2      <=  2'd0;
+        txeq_preset_reg2       <=  4'd0;
+        txeq_deemph_reg2       <=  6'd1;
+                                   
+        rxeq_control_reg2      <=  2'd0;
+        rxeq_preset_reg2       <=  3'd0;
+        rxeq_lffs_reg2         <=  6'd0;
+        rxeq_txpreset_reg2     <=  4'd0;
+        rxeq_user_en_reg2      <=  1'd0;
+        rxeq_user_txcoeff_reg2 <= 18'd0;
+        rxeq_user_mode_reg2    <=  1'd0;
+        end
+    else
+        begin  
+        //---------- 1st Stage FF -------------------------- 
+        gen3_reg1              <= EQ_GEN3;
+                               
+        txeq_control_reg1      <= EQ_TXEQ_CONTROL;
+        txeq_preset_reg1       <= EQ_TXEQ_PRESET;
+        txeq_deemph_reg1       <= EQ_TXEQ_DEEMPH_IN;
+                               
+        rxeq_control_reg1      <= EQ_RXEQ_CONTROL;
+        rxeq_preset_reg1       <= EQ_RXEQ_PRESET;
+        rxeq_lffs_reg1         <= EQ_RXEQ_LFFS;
+        rxeq_txpreset_reg1     <= EQ_RXEQ_TXPRESET;
+        rxeq_user_en_reg1      <= EQ_RXEQ_USER_EN;
+        rxeq_user_txcoeff_reg1 <= EQ_RXEQ_USER_TXCOEFF;
+        rxeq_user_mode_reg1    <= EQ_RXEQ_USER_MODE;
+        //---------- 2nd Stage FF -------------------------- 
+        gen3_reg2              <= gen3_reg1;
+                               
+        txeq_control_reg2      <= txeq_control_reg1;
+        txeq_preset_reg2       <= txeq_preset_reg1;
+        txeq_deemph_reg2       <= txeq_deemph_reg1;
+                               
+        rxeq_control_reg2      <= rxeq_control_reg1;
+        rxeq_preset_reg2       <= rxeq_preset_reg1;
+        rxeq_lffs_reg2         <= rxeq_lffs_reg1;
+        rxeq_txpreset_reg2     <= rxeq_txpreset_reg1;
+        rxeq_user_en_reg2      <= rxeq_user_en_reg1;
+        rxeq_user_txcoeff_reg2 <= rxeq_user_txcoeff_reg1;
+        rxeq_user_mode_reg2    <= rxeq_user_mode_reg1;
+        end
+        
+end       
+
+
+
+//---------- TXEQ Preset -------------------------------------------------------
+always @ (posedge EQ_CLK)
+begin
+
+    if (!EQ_RST_N)
+        begin
+        
+        //---------- Select TXEQ Preset ----------------
+        case (EQ_TXEQ_PRESET_DEFAULT)
+        4'd0    : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
+        4'd1    : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
+        4'd2    : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
+        4'd3    : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
+        4'd4    : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
+        4'd5    : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
+        4'd6    : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
+        4'd7    : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
+        4'd8    : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};      
+        4'd9    : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};   
+        4'd10   : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};                 
+        default : txeq_preset <= 19'd4;     
+        endcase
+        	   
+        txeq_preset_done <=  1'd0;
+        end                    
+    else
+        begin   
+        if (fsm_tx == FSM_TXEQ_PRESET)
+            begin
+            
+            //---------- Select TXEQ Preset ----------------
+            case (txeq_preset_reg2)
+            4'd0    : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
+            4'd1    : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
+            4'd2    : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
+            4'd3    : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
+            4'd4    : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
+            4'd5    : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
+            4'd6    : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
+            4'd7    : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
+            4'd8    : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};      
+            4'd9    : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09}; 
+            4'd10   : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};                   
+            default : txeq_preset <= 19'd4;     
+        	   endcase
+        
+            txeq_preset_done <= 1'd1;
+            end
+        else
+            begin
+            txeq_preset      <= txeq_preset;
+            txeq_preset_done <= 1'd0;
+            end
+        end
+        
+end     
+
+
+
+//---------- TXEQ FSM ----------------------------------------------------------
+always @ (posedge EQ_CLK)
+begin
+
+    if (!EQ_RST_N)
+        begin
+        fsm_tx           <=  FSM_TXEQ_IDLE; 
+        txeq_txcoeff     <= 19'd0;
+        txeq_txcoeff_cnt <=  2'd0;
+        txeq_done        <=  1'd0;
+        end                    
+    else
+        begin
+        
+        case (fsm_tx)
+        
+        //---------- Idle State ----------------------------
+        FSM_TXEQ_IDLE :
+        
+            begin
+            
+            case (txeq_control_reg2)
+            
+            //---------- Idle ------------------------------
+            2'd0    :
+                begin
+                fsm_tx           <= FSM_TXEQ_IDLE; 
+                txeq_txcoeff     <= txeq_txcoeff;
+                txeq_txcoeff_cnt <= 2'd0;
+                txeq_done        <= 1'd0;
+                end 
+                
+            //---------- Process TXEQ Preset ---------------
+            2'd1    :
+                begin
+                fsm_tx           <= FSM_TXEQ_PRESET; 
+                txeq_txcoeff     <= txeq_txcoeff;
+                txeq_txcoeff_cnt <= 2'd0;
+                txeq_done        <= 1'd0;
+                end  
+                
+            //---------- Coefficient -----------------------
+            2'd2    :
+                begin
+                fsm_tx           <= FSM_TXEQ_TXCOEFF; 
+                txeq_txcoeff     <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
+                txeq_txcoeff_cnt <= 2'd1;
+                txeq_done        <= 1'd0;
+                end
+                
+            //---------- Query -----------------------------
+            2'd3    :
+                begin
+                fsm_tx           <= FSM_TXEQ_QUERY; 
+                txeq_txcoeff     <= txeq_txcoeff;
+                txeq_txcoeff_cnt <= 2'd0;
+                txeq_done        <= 1'd0;
+                end
+                
+            //---------- Default ---------------------------
+            default :
+                begin
+                fsm_tx           <= FSM_TXEQ_IDLE; 
+                txeq_txcoeff     <= txeq_txcoeff;
+                txeq_txcoeff_cnt <= 2'd0;
+                txeq_done        <= 1'd0;
+                end
+                
+            endcase
+            
+            end
+            
+        //---------- Process TXEQ Preset -------------------
+        FSM_TXEQ_PRESET :
+        
+            begin
+            fsm_tx           <= (txeq_preset_done ? FSM_TXEQ_DONE : FSM_TXEQ_PRESET);
+            txeq_txcoeff     <= txeq_preset;
+            txeq_txcoeff_cnt <= 2'd0;
+            txeq_done        <= 1'd0;
+            end    
+            
+        //---------- Latch Link Partner TX Coefficient -----
+        FSM_TXEQ_TXCOEFF :
+        
+            begin
+            fsm_tx <= ((txeq_txcoeff_cnt == 2'd2) ? FSM_TXEQ_REMAP : FSM_TXEQ_TXCOEFF);
+            
+            //---------- Shift in extra bit for TXMAINCURSOR 
+            if (txeq_txcoeff_cnt == 2'd1)
+                txeq_txcoeff <= {1'd0, txeq_deemph_reg2, txeq_txcoeff[18:7]};
+            else
+                txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
+                
+            txeq_txcoeff_cnt <= txeq_txcoeff_cnt + 2'd1;
+            txeq_done        <= 1'd0; 
+            end
+            
+        //---------- Remap to GT TX Coefficient ------------
+        FSM_TXEQ_REMAP :
+        
+            begin
+            fsm_tx           <= FSM_TXEQ_DONE;
+            txeq_txcoeff     <= txeq_txcoeff << 1;          // Multiply by 2x
+            txeq_txcoeff_cnt <= 2'd0;
+            txeq_done        <= 1'd0; 
+            end
+            
+        //---------- Query TXEQ Coefficient ----------------
+        FSM_TXEQ_QUERY:
+        
+            begin
+            fsm_tx           <= FSM_TXEQ_DONE;
+            txeq_txcoeff     <= txeq_txcoeff; 
+            txeq_txcoeff_cnt <= 2'd0;
+            txeq_done        <= 1'd0;
+            end     
+                  
+        //---------- Done ----------------------------------
+        FSM_TXEQ_DONE :
+        
+            begin
+            fsm_tx           <= ((txeq_control_reg2 == 2'd0) ? FSM_TXEQ_IDLE : FSM_TXEQ_DONE);
+            txeq_txcoeff     <= txeq_txcoeff;          
+            txeq_txcoeff_cnt <= 2'd0;
+            txeq_done        <= 1'd1;
+            end        
+                          
+        //---------- Default State -------------------------
+        default : 
+            begin
+            fsm_tx           <=  FSM_TXEQ_IDLE;
+            txeq_txcoeff     <= 19'd0;
+            txeq_txcoeff_cnt <=  2'd0;
+            txeq_done        <=  1'd0;
+            end    
+                    
+        endcase
+        
+        end
+        
+end  
+
+
+
+//---------- RXEQ FSM ----------------------------------------------------------
+always @ (posedge EQ_CLK)
+begin
+
+    if (!EQ_RST_N)
+        begin
+        fsm_rx               <= FSM_RXEQ_IDLE; 
+        rxeq_preset          <=  3'd0;
+        rxeq_preset_valid    <=  1'd0;
+        rxeq_txpreset        <=  4'd0;
+        rxeq_txcoeff         <= 18'd0; 
+        rxeq_cnt             <=  3'd0;
+        rxeq_fs              <=  6'd0;
+        rxeq_lf              <=  6'd0;
+        rxeq_new_txcoeff_req <=  1'd0; 
+        rxeq_new_txcoeff     <= 18'd0;
+        rxeq_lffs_sel        <=  1'd0;
+        rxeq_adapt_done_reg  <=  1'd0;
+        rxeq_adapt_done      <=  1'd0;   
+        rxeq_done            <=  1'd0; 
+        end                    
+    else
+        begin
+        
+        case (fsm_rx)
+        
+        //---------- Idle State ----------------------------
+        FSM_RXEQ_IDLE :
+        
+            begin
+            
+            case (rxeq_control_reg2)
+                
+            //---------- Process RXEQ Preset ---------------
+            2'd1 :
+                begin
+                fsm_rx               <= FSM_RXEQ_PRESET; 
+                rxeq_preset          <= rxeq_preset_reg2;
+                rxeq_preset_valid    <= 1'd0;
+                rxeq_txpreset        <= rxeq_txpreset;
+                rxeq_txcoeff         <= rxeq_txcoeff;
+                rxeq_cnt             <= 3'd0;
+                rxeq_fs              <= rxeq_fs;
+                rxeq_lf              <= rxeq_lf;
+                rxeq_new_txcoeff_req <= 1'd0;
+                rxeq_new_txcoeff     <= rxeq_new_txcoeff;
+                rxeq_lffs_sel        <= 1'd0;
+                rxeq_adapt_done_reg  <= 1'd0;
+                rxeq_adapt_done      <= 1'd0;
+                rxeq_done            <= 1'd0; 
+                end  
+                
+            //---------- Request New TX Coefficient --------
+            2'd2 :
+                begin
+                fsm_rx               <= FSM_RXEQ_TXCOEFF; 
+                rxeq_preset          <= rxeq_preset;
+                rxeq_preset_valid    <= 1'd0;
+                rxeq_txpreset        <= rxeq_txpreset_reg2;
+                rxeq_txcoeff         <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
+                rxeq_cnt             <= 3'd1;
+                rxeq_fs              <= rxeq_lffs_reg2;
+                rxeq_lf              <= rxeq_lf;
+                rxeq_new_txcoeff_req <= 1'd0;
+                rxeq_new_txcoeff     <= rxeq_new_txcoeff;
+                rxeq_lffs_sel        <= 1'd0;
+                rxeq_adapt_done_reg  <= rxeq_adapt_done_reg;
+                rxeq_adapt_done      <= 1'd0;
+                rxeq_done            <= 1'd0; 
+                end
+                
+            //---------- Phase2/3 Bypass (reuse logic from rxeq_control = 2 ----
+            2'd3 :
+                begin
+                fsm_rx               <= FSM_RXEQ_TXCOEFF; 
+                rxeq_preset          <= rxeq_preset;
+                rxeq_preset_valid    <= 1'd0;
+                rxeq_txpreset        <= rxeq_txpreset_reg2;
+                rxeq_txcoeff         <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
+                rxeq_cnt             <= 3'd1;
+                rxeq_fs              <= rxeq_lffs_reg2;
+                rxeq_lf              <= rxeq_lf;
+                rxeq_new_txcoeff_req <= 1'd0;
+                rxeq_new_txcoeff     <= rxeq_new_txcoeff;
+                rxeq_lffs_sel        <= 1'd0;
+                rxeq_adapt_done_reg  <= rxeq_adapt_done_reg;
+                rxeq_adapt_done      <= 1'd0;
+                rxeq_done            <= 1'd0; 
+                end
+                
+            //---------- Default ---------------------------
+            default :
+                begin
+                fsm_rx               <= FSM_RXEQ_IDLE; 
+                rxeq_preset          <= rxeq_preset;
+                rxeq_preset_valid    <= 1'd0;
+                rxeq_txpreset        <= rxeq_txpreset;
+                rxeq_txcoeff         <= rxeq_txcoeff;
+                rxeq_cnt             <= 3'd0;
+                rxeq_fs              <= rxeq_fs;
+                rxeq_lf              <= rxeq_lf;
+                rxeq_new_txcoeff_req <= 1'd0;
+                rxeq_new_txcoeff     <= rxeq_new_txcoeff;
+                rxeq_lffs_sel        <= 1'd0;
+                rxeq_adapt_done_reg  <= rxeq_adapt_done_reg;
+                rxeq_adapt_done      <= 1'd0;
+                rxeq_done            <= 1'd0; 
+                end
+                
+            endcase
+            
+            end
+            
+        //---------- Process RXEQ Preset -------------------
+        FSM_RXEQ_PRESET :
+        
+            begin
+            fsm_rx               <= (rxeqscan_preset_done ? FSM_RXEQ_DONE : FSM_RXEQ_PRESET);
+            rxeq_preset          <= rxeq_preset_reg2;
+            rxeq_preset_valid    <= 1'd1; 
+            rxeq_txpreset        <= rxeq_txpreset;
+            rxeq_txcoeff         <= rxeq_txcoeff; 
+            rxeq_cnt             <= 3'd0;
+            rxeq_fs              <= rxeq_fs;
+            rxeq_lf              <= rxeq_lf;
+            rxeq_new_txcoeff_req <= 1'd0;
+            rxeq_new_txcoeff     <= rxeq_new_txcoeff;
+            rxeq_lffs_sel        <= 1'd0;
+            rxeq_adapt_done_reg  <= rxeq_adapt_done_reg;
+            rxeq_adapt_done      <= 1'd0;
+            rxeq_done            <= 1'd0; 
+            end    
+            
+        //---------- Shift-in Link Partner TX Coefficient and Preset 
+        FSM_RXEQ_TXCOEFF :
+        
+            begin
+            fsm_rx               <= ((rxeq_cnt == 3'd2) ? FSM_RXEQ_LF : FSM_RXEQ_TXCOEFF);
+            rxeq_preset          <= rxeq_preset;
+            rxeq_preset_valid    <= 1'd0; 
+            rxeq_txpreset        <= rxeq_txpreset_reg2;
+            rxeq_txcoeff         <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]}; 
+            rxeq_cnt             <= rxeq_cnt + 2'd1;
+            rxeq_fs              <= rxeq_fs;
+            rxeq_lf              <= rxeq_lf;
+            rxeq_new_txcoeff_req <= 1'd0;
+            rxeq_new_txcoeff     <= rxeq_new_txcoeff;
+            rxeq_lffs_sel        <= 1'd1;
+            rxeq_adapt_done_reg  <= rxeq_adapt_done_reg;
+            rxeq_adapt_done      <= 1'd0;
+            rxeq_done            <= 1'd0; 
+            end
+            
+        //---------- Read Low Frequency (LF) Value ---------
+        FSM_RXEQ_LF :
+            begin
+            fsm_rx               <= ((rxeq_cnt == 3'd7) ? FSM_RXEQ_NEW_TXCOEFF_REQ : FSM_RXEQ_LF);
+            rxeq_preset          <= rxeq_preset;
+            rxeq_preset_valid    <= 1'd0; 
+            rxeq_txpreset        <= rxeq_txpreset;
+            rxeq_txcoeff         <= rxeq_txcoeff; 
+            rxeq_cnt             <= rxeq_cnt + 2'd1;
+            rxeq_fs              <= rxeq_fs;
+            rxeq_lf              <= ((rxeq_cnt == 3'd7) ? rxeq_lffs_reg2 : rxeq_lf);
+            rxeq_new_txcoeff_req <= 1'd0;
+            rxeq_new_txcoeff     <= rxeq_new_txcoeff;
+            rxeq_lffs_sel        <= 1'd1;
+            rxeq_adapt_done_reg  <= rxeq_adapt_done_reg;
+            rxeq_adapt_done      <= 1'd0;
+            rxeq_done            <= 1'd0; 
+            end
+            
+        //---------- Request New TX Coefficient ------------
+        FSM_RXEQ_NEW_TXCOEFF_REQ :
+        
+            begin            
+            rxeq_preset          <= rxeq_preset;
+            rxeq_preset_valid    <= 1'd0; 
+            rxeq_txpreset        <= rxeq_txpreset;
+            rxeq_txcoeff         <= rxeq_txcoeff; 
+            rxeq_cnt             <= 3'd0;
+            rxeq_fs              <= rxeq_fs;
+            rxeq_lf              <= rxeq_lf;
+            
+            if (rxeqscan_new_txcoeff_done)
+                begin
+                fsm_rx               <= FSM_RXEQ_DONE;
+                rxeq_new_txcoeff_req <= 1'd0;
+                rxeq_new_txcoeff     <= rxeqscan_lffs_sel ? {14'd0, rxeqscan_new_txcoeff[3:0]} : rxeqscan_new_txcoeff;
+                rxeq_lffs_sel        <= rxeqscan_lffs_sel;
+                rxeq_adapt_done_reg  <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
+                rxeq_adapt_done      <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
+                rxeq_done            <= 1'd1; 
+                end
+            else
+                begin
+                fsm_rx               <= FSM_RXEQ_NEW_TXCOEFF_REQ;
+                rxeq_new_txcoeff_req <= 1'd1;
+                rxeq_new_txcoeff     <= rxeq_new_txcoeff;
+                rxeq_lffs_sel        <= 1'd0;
+                rxeq_adapt_done_reg  <= rxeq_adapt_done_reg;
+                rxeq_adapt_done      <= 1'd0;
+                rxeq_done            <= 1'd0; 
+                end
+            
+            end     
+             
+        //---------- RXEQ Done -----------------------------
+        FSM_RXEQ_DONE :
+        
+            begin
+            fsm_rx               <= ((rxeq_control_reg2 == 2'd0) ? FSM_RXEQ_IDLE : FSM_RXEQ_DONE);
+            rxeq_preset          <= rxeq_preset;
+            rxeq_preset_valid    <= 1'd0;
+            rxeq_txpreset        <= rxeq_txpreset; 
+            rxeq_txcoeff         <= rxeq_txcoeff;
+            rxeq_cnt             <= 3'd0;
+            rxeq_fs              <= rxeq_fs;
+            rxeq_lf              <= rxeq_lf;
+            rxeq_new_txcoeff_req <= 1'd0;
+            rxeq_new_txcoeff     <= rxeq_new_txcoeff;
+            rxeq_lffs_sel        <= rxeq_lffs_sel;
+            rxeq_adapt_done_reg  <= rxeq_adapt_done_reg;
+            rxeq_adapt_done      <= rxeq_adapt_done;  
+            rxeq_done            <= 1'd1; 
+            end        
+                          
+        //---------- Default State -------------------------
+        default : 
+            begin
+            fsm_rx               <= FSM_RXEQ_IDLE;
+            rxeq_preset          <=  3'd0;
+            rxeq_preset_valid    <=  1'd0;
+            rxeq_txpreset        <=  4'd0;
+            rxeq_txcoeff         <= 18'd0;
+            rxeq_cnt             <=  3'd0;
+            rxeq_fs              <=  6'd0;
+            rxeq_lf              <=  6'd0;
+            rxeq_new_txcoeff_req <=  1'd0;
+            rxeq_new_txcoeff     <= 18'd0;
+            rxeq_lffs_sel        <=  1'd0;
+            rxeq_adapt_done_reg  <=  1'd0;
+            rxeq_adapt_done      <=  1'd0;
+            rxeq_done            <=  1'd0;   
+            end    
+                    
+    	   endcase
+        
+        end
+        
+end      
+
+
+
+//---------- RXEQ Eye Scan Module ----------------------------------------------
+xdma_0_pcie2_ip_rxeq_scan #
+(
+    .PCIE_SIM_MODE                      (PCIE_SIM_MODE),
+    .PCIE_GT_DEVICE                     (PCIE_GT_DEVICE),
+    .PCIE_RXEQ_MODE_GEN3                (PCIE_RXEQ_MODE_GEN3)
+)
+
+rxeq_scan_i
+(
+
+    //---------- Input -------------------------------------
+    .RXEQSCAN_CLK                       (EQ_CLK),
+    .RXEQSCAN_RST_N                     (EQ_RST_N),
+    .RXEQSCAN_CONTROL                   (rxeq_control_reg2),
+    .RXEQSCAN_FS                        (rxeq_fs),      
+    .RXEQSCAN_LF                        (rxeq_lf), 
+    .RXEQSCAN_PRESET                    (rxeq_preset),
+    .RXEQSCAN_PRESET_VALID              (rxeq_preset_valid),   
+    .RXEQSCAN_TXPRESET                  (rxeq_txpreset),
+    .RXEQSCAN_TXCOEFF                   (rxeq_txcoeff),    
+    .RXEQSCAN_NEW_TXCOEFF_REQ           (rxeq_new_txcoeff_req),                
+    
+    //---------- Output ------------------------------------
+    .RXEQSCAN_PRESET_DONE               (rxeqscan_preset_done),
+    .RXEQSCAN_NEW_TXCOEFF               (rxeqscan_new_txcoeff),
+    .RXEQSCAN_NEW_TXCOEFF_DONE          (rxeqscan_new_txcoeff_done),
+    .RXEQSCAN_LFFS_SEL                  (rxeqscan_lffs_sel),
+    .RXEQSCAN_ADAPT_DONE                (rxeqscan_adapt_done)
+    
+); 
+
+
+
+//---------- PIPE EQ Output ----------------------------------------------------
+assign EQ_TXEQ_DEEMPH      = txeq_txcoeff[0];       
+assign EQ_TXEQ_PRECURSOR   = gen3_reg2 ? txeq_txcoeff[ 4: 0] : 5'h00;
+assign EQ_TXEQ_MAINCURSOR  = gen3_reg2 ? txeq_txcoeff[12: 6] : 7'h00; 
+assign EQ_TXEQ_POSTCURSOR  = gen3_reg2 ? txeq_txcoeff[17:13] : 5'h00;
+assign EQ_TXEQ_DEEMPH_OUT  = {1'd0, txeq_txcoeff[18:14], txeq_txcoeff[12:7], 1'd0, txeq_txcoeff[5:1]}; // Divide by 2x
+assign EQ_TXEQ_DONE        = txeq_done;
+assign EQ_TXEQ_FSM         = fsm_tx;
+
+assign EQ_RXEQ_NEW_TXCOEFF = rxeq_user_en_reg2 ? rxeq_user_txcoeff_reg2 : rxeq_new_txcoeff;
+assign EQ_RXEQ_LFFS_SEL    = rxeq_user_en_reg2 ? rxeq_user_mode_reg2    : rxeq_lffs_sel;
+assign EQ_RXEQ_ADAPT_DONE  = rxeq_adapt_done;
+assign EQ_RXEQ_DONE        = rxeq_done;
+assign EQ_RXEQ_FSM         = fsm_rx;
+
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pipe_reset.v

@@ -0,0 +1,576 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pipe_reset.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  pipe_reset.v
+//  Description  :  PIPE Reset Module for 7 Series Transceiver
+//  Version      :  20.2
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- PIPE Reset Module -------------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_pipe_reset #
+(
+
+    //---------- Global ------------------------------------
+    parameter PCIE_SIM_SPEEDUP  = "FALSE",                  // PCIe sim speedup
+    parameter PCIE_GT_DEVICE    = "GTX",
+    parameter PCIE_PLL_SEL      = "CPLL",                   // PCIe PLL select for Gen1/Gen2 only
+    parameter PCIE_POWER_SAVING = "TRUE",                   // PCIe power saving
+    parameter PCIE_TXBUF_EN     = "FALSE",                  // PCIe TX buffer enable
+    parameter PCIE_LANE         = 1,                        // PCIe number of lanes
+    //---------- Local -------------------------------------
+    parameter CFG_WAIT_MAX      = 6'd63,                    // Configuration wait max
+    parameter BYPASS_RXCDRLOCK  = 1                         // Bypass RXCDRLOCK
+
+)
+
+(
+
+    //---------- Input -------------------------------------
+    input                           RST_CLK,
+    input                           RST_RXUSRCLK,
+    input                           RST_DCLK,
+    input                           RST_RST_N,
+    input       [PCIE_LANE-1:0]     RST_DRP_DONE,
+    input       [PCIE_LANE-1:0]     RST_RXPMARESETDONE,
+    input       [PCIE_LANE-1:0]     RST_CPLLLOCK,
+    input                           RST_QPLL_IDLE,
+    input       [PCIE_LANE-1:0]     RST_RATE_IDLE,
+    input       [PCIE_LANE-1:0]     RST_RXCDRLOCK,
+    input                           RST_MMCM_LOCK,
+    input       [PCIE_LANE-1:0]     RST_RESETDONE,
+    input       [PCIE_LANE-1:0]     RST_PHYSTATUS,
+    input       [PCIE_LANE-1:0]     RST_TXSYNC_DONE,
+    
+    //---------- Output ------------------------------------
+    output                          RST_CPLLRESET,
+    output                          RST_CPLLPD,
+    output reg                      RST_DRP_START,
+    output reg                      RST_DRP_X16X20_MODE,
+    output reg                      RST_DRP_X16,
+    output                          RST_RXUSRCLK_RESET,
+    output                          RST_DCLK_RESET,
+    output                          RST_GTRESET,
+    output                          RST_USERRDY,
+    output                          RST_TXSYNC_START,
+    output                          RST_IDLE,
+    output      [4:0]               RST_FSM
+
+);
+
+    //---------- Input Register ----------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     drp_done_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rxpmaresetdone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     cplllock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             qpll_idle_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rate_idle_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rxcdrlock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             mmcm_lock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     resetdone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     phystatus_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     txsync_done_reg1;  
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     drp_done_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rxpmaresetdone_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     cplllock_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             qpll_idle_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rate_idle_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     rxcdrlock_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             mmcm_lock_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     resetdone_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     phystatus_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     txsync_done_reg2;
+    
+    //---------- Internal Signal ---------------------------
+    reg         [ 5:0]              cfg_wait_cnt      =  6'd0;
+    
+    //---------- Output Register ---------------------------
+    reg                             cpllreset         =  1'd0;
+    reg                             cpllpd            =  1'd0;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             rxusrclk_rst_reg1 =  1'd0;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             rxusrclk_rst_reg2 =  1'd0;
+                                                  reg                             dclk_rst          =  1'd0;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             dclk_rst_reg1     =  1'd0;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             dclk_rst_reg2     =  1'd0;
+    reg                             gtreset           =  1'd0;
+    reg                             userrdy           =  1'd0;
+    reg         [4:0]               fsm               =  5'h2;
+   
+    //---------- FSM ---------------------------------------                                         
+    localparam                      FSM_IDLE             = 5'h0;
+    localparam                      FSM_CFG_WAIT         = 5'h1;
+    localparam                      FSM_CPLLRESET        = 5'h2;
+    localparam                      FSM_DRP_X16_START    = 5'h3;
+    localparam                      FSM_DRP_X16_DONE     = 5'h4;
+    localparam                      FSM_CPLLLOCK         = 5'h5;
+    localparam                      FSM_DRP              = 5'h6;
+    localparam                      FSM_GTRESET          = 5'h7;
+    localparam                      FSM_RXPMARESETDONE_1 = 5'h8;
+    localparam                      FSM_RXPMARESETDONE_2 = 5'h9;
+    localparam                      FSM_DRP_X20_START    = 5'hA;
+    localparam                      FSM_DRP_X20_DONE     = 5'hB;
+    localparam                      FSM_MMCM_LOCK        = 5'hC;
+    localparam                      FSM_RESETDONE        = 5'hD;
+    localparam                      FSM_CPLL_PD          = 5'hE;
+    localparam                      FSM_TXSYNC_START     = 5'hF;
+    localparam                      FSM_TXSYNC_DONE      = 5'h10;
+
+    
+
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge RST_CLK)
+begin
+
+    if (!RST_RST_N)
+        begin    
+        //---------- 1st Stage FF --------------------------    
+        drp_done_reg1       <= {PCIE_LANE{1'd0}};   
+        rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}}; 
+        cplllock_reg1       <= {PCIE_LANE{1'd0}}; 
+        qpll_idle_reg1      <= 1'd0;
+        rate_idle_reg1      <= {PCIE_LANE{1'd0}}; 
+        rxcdrlock_reg1      <= {PCIE_LANE{1'd0}}; 
+        mmcm_lock_reg1      <= 1'd0; 
+        resetdone_reg1      <= {PCIE_LANE{1'd0}}; 
+        phystatus_reg1      <= {PCIE_LANE{1'd0}}; 
+        txsync_done_reg1    <= {PCIE_LANE{1'd0}}; 
+        //---------- 2nd Stage FF --------------------------
+        drp_done_reg2       <= {PCIE_LANE{1'd0}};
+        rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}}; 
+        cplllock_reg2       <= {PCIE_LANE{1'd0}}; 
+        qpll_idle_reg2      <= 1'd0;
+        rate_idle_reg2      <= {PCIE_LANE{1'd0}}; 
+        rxcdrlock_reg2      <= {PCIE_LANE{1'd0}}; 
+        mmcm_lock_reg2      <= 1'd0;
+        resetdone_reg2      <= {PCIE_LANE{1'd0}}; 
+        phystatus_reg2      <= {PCIE_LANE{1'd0}}; 
+        txsync_done_reg2    <= {PCIE_LANE{1'd0}}; 
+        end
+    else
+        begin  
+        //---------- 1st Stage FF --------------------------  
+        drp_done_reg1       <= RST_DRP_DONE; 
+        rxpmaresetdone_reg1 <= RST_RXPMARESETDONE;   
+        cplllock_reg1       <= RST_CPLLLOCK;
+        qpll_idle_reg1      <= RST_QPLL_IDLE;
+        rate_idle_reg1      <= RST_RATE_IDLE;
+        rxcdrlock_reg1      <= RST_RXCDRLOCK;
+        mmcm_lock_reg1      <= RST_MMCM_LOCK;
+        resetdone_reg1      <= RST_RESETDONE;
+        phystatus_reg1      <= RST_PHYSTATUS;
+        txsync_done_reg1    <= RST_TXSYNC_DONE;
+        //---------- 2nd Stage FF --------------------------
+        drp_done_reg2       <= drp_done_reg1;
+        rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
+        cplllock_reg2       <= cplllock_reg1;
+        qpll_idle_reg2      <= qpll_idle_reg1;
+        rate_idle_reg2      <= rate_idle_reg1;
+        rxcdrlock_reg2      <= rxcdrlock_reg1;
+        mmcm_lock_reg2      <= mmcm_lock_reg1;
+        resetdone_reg2      <= resetdone_reg1;
+        phystatus_reg2      <= phystatus_reg1;
+        txsync_done_reg2    <= txsync_done_reg1;   
+        end
+        
+end    
+
+
+
+//---------- Configuration Reset Wait Counter ----------------------------------
+always @ (posedge RST_CLK)
+begin
+
+    if (!RST_RST_N)
+        cfg_wait_cnt <= 6'd0;
+    else
+    
+        //---------- Increment Configuration Reset Wait Counter
+        if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
+            cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
+            
+        //---------- Hold Configuration Reset Wait Counter -
+        else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
+            cfg_wait_cnt <= cfg_wait_cnt;
+            
+        //---------- Reset Configuration Reset Wait Counter 
+        else
+            cfg_wait_cnt <= 6'd0;
+        
+end 
+
+
+
+//---------- PIPE Reset FSM ----------------------------------------------------
+always @ (posedge RST_CLK)
+begin
+
+    if (!RST_RST_N)
+        begin
+        fsm       <= FSM_CFG_WAIT;
+        cpllreset <= 1'd0;
+        cpllpd    <= 1'd0;
+        gtreset   <= 1'd0;
+        userrdy   <= 1'd0;
+        end
+    else
+        begin
+        
+        case (fsm)
+            
+        //---------- Idle State ----------------------------
+        FSM_IDLE :
+        
+            begin
+            if (!RST_RST_N)
+                begin
+                fsm       <= FSM_CFG_WAIT;
+                cpllreset <= 1'd0;
+                cpllpd    <= 1'd0;
+                gtreset   <= 1'd0;
+                userrdy   <= 1'd0;
+                end
+            else
+                begin
+                fsm       <= FSM_IDLE;
+                cpllreset <= cpllreset;
+                cpllpd    <= cpllpd;
+                gtreset   <= gtreset;
+                userrdy   <= userrdy;
+                end
+            end  
+            
+        //----------  Wait for Configuration Reset Delay ---
+        FSM_CFG_WAIT :
+          
+            begin
+            fsm       <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_CPLLRESET : FSM_CFG_WAIT);
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end 
+            
+        //---------- Hold CPLL and GTX Channel in Reset ----
+        FSM_CPLLRESET :
+        
+            begin
+            fsm       <= ((&(~cplllock_reg2) && (&(~resetdone_reg2))) ?  FSM_CPLLLOCK : FSM_CPLLRESET);
+            cpllreset <= 1'd1;
+            cpllpd    <= cpllpd;
+            gtreset   <= 1'd1;
+            userrdy   <= userrdy;
+            end  
+
+        //---------- Wait for CPLL Lock --------------------
+        FSM_CPLLLOCK :
+        
+            begin
+            fsm       <= (&cplllock_reg2 ? FSM_DRP : FSM_CPLLLOCK);
+            cpllreset <= 1'd0;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+
+        //---------- Wait for DRP Done to Setup Gen1 -------
+        FSM_DRP :
+        
+            begin
+            fsm       <= (&rate_idle_reg2 ? ((PCIE_GT_DEVICE == "GTX") ? FSM_GTRESET : FSM_DRP_X16_START) : FSM_DRP);
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+
+        //---------- Start DRP x16 -------------------------
+        FSM_DRP_X16_START :
+            
+            begin
+            fsm       <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+            
+        //---------- Wait for DRP x16 Done -----------------    
+        FSM_DRP_X16_DONE :
+        
+            begin  
+            fsm       <= (&drp_done_reg2) ? FSM_GTRESET : FSM_DRP_X16_DONE;
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end  
+
+        //---------- Release GTX Channel Reset -------------
+        FSM_GTRESET :
+        
+            begin
+            fsm       <= (PCIE_GT_DEVICE == "GTX") ? FSM_MMCM_LOCK : FSM_RXPMARESETDONE_1;
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= 1'b0;
+            userrdy   <= userrdy;
+            end
+            
+        //---------- Wait for RXPMARESETDONE Assertion -----
+        FSM_RXPMARESETDONE_1 :
+        
+            begin
+            fsm       <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1;
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end  
+
+        //---------- Wait for RXPMARESETDONE De-assertion --
+        FSM_RXPMARESETDONE_2 :
+        
+            begin
+            fsm       <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2;
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end  
+            
+        //---------- Start DRP x20 -------------------------
+        FSM_DRP_X20_START :
+            
+            begin
+            fsm       <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+            
+        //---------- Wait for DRP x20 Done -----------------    
+        FSM_DRP_X20_DONE :
+        
+            begin  
+            fsm       <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE;
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end   
+
+        //---------- Wait for MMCM and RX CDR Lock ---------
+        FSM_MMCM_LOCK :
+        
+            begin  
+            if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)) && (qpll_idle_reg2 || (PCIE_PLL_SEL == "CPLL")))
+                begin
+                fsm       <= FSM_RESETDONE;
+                cpllreset <= cpllreset;
+                cpllpd    <= cpllpd;
+                gtreset   <= gtreset;
+                userrdy   <= 1'd1;
+                end
+            else
+                begin
+                fsm       <= FSM_MMCM_LOCK;
+                cpllreset <= cpllreset;
+                cpllpd    <= cpllpd;
+                gtreset   <= gtreset;
+                userrdy   <= 1'd0;
+                end
+            end
+
+        //---------- Wait for [TX/RX]RESETDONE and PHYSTATUS 
+        FSM_RESETDONE :
+        
+            begin
+            fsm       <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_CPLL_PD : FSM_RESETDONE);  
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+            
+        //---------- Power-Down CPLL if QPLL is Used for Gen1/Gen2
+        FSM_CPLL_PD :
+        
+            begin
+            fsm       <= ((PCIE_TXBUF_EN == "TRUE") ? FSM_IDLE : FSM_TXSYNC_START);
+            cpllreset <= cpllreset;
+            cpllpd    <= (PCIE_PLL_SEL == "QPLL");
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+        
+        //---------- Start TX Sync -------------------------
+        FSM_TXSYNC_START :
+        
+            begin
+            fsm       <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end
+            
+        //---------- Wait for TX Sync Done -----------------
+        FSM_TXSYNC_DONE :
+        
+            begin
+            fsm       <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
+            cpllreset <= cpllreset;
+            cpllpd    <= cpllpd;
+            gtreset   <= gtreset;
+            userrdy   <= userrdy;
+            end     
+            
+        //---------- Default State -------------------------
+        default :
+        
+            begin
+            fsm       <= FSM_CFG_WAIT;
+            cpllreset <= 1'd0;
+            cpllpd    <= 1'd0;
+            gtreset   <= 1'd0;
+            userrdy   <= 1'd0;
+            end
+
+        endcase
+        
+        end
+        
+end
+
+
+
+//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
+always @ (posedge RST_RXUSRCLK)
+begin
+
+    rxusrclk_rst_reg1 <= cpllreset;
+    rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
+          
+end  
+
+
+
+//---------- DCLK Reset Synchronizer -------------------------------------------
+always @ (posedge RST_CLK)
+begin
+
+    if (fsm == FSM_CFG_WAIT)
+        begin
+        dclk_rst      <= 1'd1;
+        end
+    else
+        begin
+        dclk_rst      <= 1'd0;
+        end
+end
+
+always @ (posedge RST_DCLK)
+begin
+
+    dclk_rst_reg1 <= dclk_rst;
+    dclk_rst_reg2 <= dclk_rst_reg1;
+
+end  
+
+
+
+//---------- PIPE Reset Output -------------------------------------------------
+assign RST_CPLLRESET       = cpllreset; 
+assign RST_CPLLPD          = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
+assign RST_RXUSRCLK_RESET  = rxusrclk_rst_reg2;
+assign RST_DCLK_RESET      = dclk_rst_reg2;
+assign RST_GTRESET         = gtreset;  
+assign RST_USERRDY         = userrdy;
+assign RST_TXSYNC_START    = (fsm == FSM_TXSYNC_START);
+assign RST_IDLE            = (fsm == FSM_IDLE);
+assign RST_FSM             = fsm;                   
+
+
+
+
+//--------------------------------------------------------------------------------------------------
+//  Register Output
+//--------------------------------------------------------------------------------------------------
+always @ (posedge RST_CLK)
+begin
+
+    if (!RST_RST_N) 
+        begin
+        RST_DRP_START       <= 1'd0;
+        RST_DRP_X16X20_MODE <= 1'd0; 
+        RST_DRP_X16         <= 1'd0;
+        end
+    else
+        begin
+        RST_DRP_START       <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START); 
+        RST_DRP_X16X20_MODE <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
+        RST_DRP_X16         <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
+        end
+        
+end  
+
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pipe_sync.v

@@ -0,0 +1,645 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pipe_sync.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  pipe_sync.v
+//  Description  :  PIPE Sync Module for 7 Series Transceiver
+//  Version      :  20.1
+//------------------------------------------------------------------------------
+//  PCIE_TXSYNC_MODE  : 0 = Manual TX sync (default).
+//                    : 1 = Auto TX sync.
+//  PCIE_RXSYNC_MODE  : 0 = Manual RX sync (default).
+//                    : 1 = Auto RX sync.
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- PIPE Sync Module --------------------------------------------------
+module xdma_0_pcie2_ip_pipe_sync #
+(
+
+    parameter PCIE_GT_DEVICE       = "GTX",                 // PCIe GT device
+    parameter PCIE_TXBUF_EN        = "FALSE",               // PCIe TX buffer enable for Gen1/Gen2 only
+    parameter PCIE_RXBUF_EN        = "TRUE",                // PCIe TX buffer enable for Gen3      only
+    parameter PCIE_TXSYNC_MODE     = 0,                     // PCIe TX sync mode
+    parameter PCIE_RXSYNC_MODE     = 0,                     // PCIe RX sync mode
+    parameter PCIE_LANE            = 1,                     // PCIe lane
+    parameter PCIE_LINK_SPEED      = 3,                     // PCIe link speed
+    parameter BYPASS_TXDELAY_ALIGN = 0,                     // Bypass TX delay align
+    parameter BYPASS_RXDELAY_ALIGN = 0                      // Bypass RX delay align
+
+)
+
+(
+
+    //---------- Input -------------------------------------
+    input               SYNC_CLK,
+    input               SYNC_RST_N,
+    input               SYNC_SLAVE,
+    input               SYNC_GEN3,
+    input               SYNC_RATE_IDLE,
+    input               SYNC_MMCM_LOCK,
+    input               SYNC_RXELECIDLE,
+    input               SYNC_RXCDRLOCK,
+    input               SYNC_ACTIVE_LANE,
+    
+    input               SYNC_TXSYNC_START,
+    input               SYNC_TXPHINITDONE,   
+    input               SYNC_TXDLYSRESETDONE,
+    input               SYNC_TXPHALIGNDONE,
+    input               SYNC_TXSYNCDONE,
+        
+    input               SYNC_RXSYNC_START,
+    input               SYNC_RXDLYSRESETDONE,
+    input               SYNC_RXPHALIGNDONE_M,
+    input               SYNC_RXPHALIGNDONE_S,
+    input               SYNC_RXSYNC_DONEM_IN,
+    input               SYNC_RXSYNCDONE,
+    
+    //---------- Output ------------------------------------
+    output              SYNC_TXPHDLYRESET,
+    output              SYNC_TXPHALIGN,     
+    output              SYNC_TXPHALIGNEN,  
+    output              SYNC_TXPHINIT,       
+    output              SYNC_TXDLYBYPASS,  
+    output              SYNC_TXDLYSRESET,
+    output              SYNC_TXDLYEN,   
+    output              SYNC_TXSYNC_DONE,
+    output    [ 5:0]    SYNC_FSM_TX,
+    
+    output              SYNC_RXPHALIGN,
+    output              SYNC_RXPHALIGNEN,
+    output              SYNC_RXDLYBYPASS,
+    output              SYNC_RXDLYSRESET,
+    output              SYNC_RXDLYEN,
+    output              SYNC_RXDDIEN,
+    output              SYNC_RXSYNC_DONEM_OUT,
+    output              SYNC_RXSYNC_DONE,
+    output    [ 6:0]    SYNC_FSM_RX
+
+);          
+
+    //---------- Input Register ----------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 gen3_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_idle_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg		      mmcm_lock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxelecidle_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxcdrlock_reg1;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 gen3_reg2;     
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_idle_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg		      mmcm_lock_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxelecidle_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxcdrlock_reg2;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg		      txsync_start_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphinitdone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txdlysresetdone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphaligndone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsyncdone_reg1;
+                                                   
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsync_start_reg2;     
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphinitdone_reg2;     
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txdlysresetdone_reg2;    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphaligndone_reg2;   
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsyncdone_reg2; 
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsync_start_reg3;     
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphinitdone_reg3;     
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txdlysresetdone_reg3;    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txphaligndone_reg3;   
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txsyncdone_reg3;     
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg		      rxsync_start_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxdlysresetdone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxphaligndone_m_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxphaligndone_s_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxsync_donem_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxsyncdone_reg1;
+
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg		      rxsync_start_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxdlysresetdone_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxphaligndone_m_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxphaligndone_s_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxsync_donem_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxsyncdone_reg2;
+    
+    //---------- Output Register ---------------------------          
+    reg                 txdlyen     = 1'd0;
+    reg                 txsync_done = 1'd0;
+    reg         [ 5:0]  fsm_tx      = 6'd0;     
+    
+    reg                 rxdlyen     = 1'd0;
+    reg                 rxsync_done = 1'd0;         
+    reg	        [ 6:0]  fsm_rx      = 7'd0;   
+   
+    //---------- FSM ---------------------------------------                                         
+    localparam          FSM_TXSYNC_IDLE  = 6'b000001; 
+    localparam          FSM_MMCM_LOCK    = 6'b000010;                                     
+    localparam          FSM_TXSYNC_START = 6'b000100;
+    localparam          FSM_TXPHINITDONE = 6'b001000;       // Manual TX sync only
+    localparam          FSM_TXSYNC_DONE1 = 6'b010000;   
+    localparam          FSM_TXSYNC_DONE2 = 6'b100000;             
+        
+    localparam          FSM_RXSYNC_IDLE  = 7'b0000001; 
+    localparam          FSM_RXCDRLOCK    = 7'b0000010;                                     
+    localparam          FSM_RXSYNC_START = 7'b0000100;
+    localparam          FSM_RXSYNC_DONE1 = 7'b0001000;                                     
+    localparam          FSM_RXSYNC_DONE2 = 7'b0010000;
+    localparam          FSM_RXSYNC_DONES = 7'b0100000;
+    localparam          FSM_RXSYNC_DONEM = 7'b1000000;
+        
+    
+    
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge SYNC_CLK)
+begin
+
+    if (!SYNC_RST_N)
+        begin    
+        //---------- 1st Stage FF --------------------------  
+        gen3_reg1            <= 1'd0;
+        rate_idle_reg1       <= 1'd0;
+        mmcm_lock_reg1       <= 1'd0;
+        rxelecidle_reg1      <= 1'd0;
+        rxcdrlock_reg1 	     <= 1'd0;
+ 
+        txsync_start_reg1	   <= 1'd0;
+        txphinitdone_reg1    <= 1'd0;
+        txdlysresetdone_reg1 <= 1'd0;
+        txphaligndone_reg1   <= 1'd0;
+        txsyncdone_reg1      <= 1'd0;
+        
+        rxsync_start_reg1	   <= 1'd0; 
+        rxdlysresetdone_reg1 <= 1'd0;
+        rxphaligndone_m_reg1 <= 1'd0;
+        rxphaligndone_s_reg1 <= 1'd0;
+        rxsync_donem_reg1    <= 1'd0;    
+        rxsyncdone_reg1      <= 1'd0;
+        //---------- 2nd Stage FF --------------------------
+        gen3_reg2            <= 1'd0;
+        rate_idle_reg2       <= 1'd0;
+        mmcm_lock_reg2       <= 1'd0;
+        rxelecidle_reg2      <= 1'd0;
+        rxcdrlock_reg2 	     <= 1'd0;
+        
+        txsync_start_reg2	   <= 1'd0;
+        txphinitdone_reg2    <= 1'd0;
+        txdlysresetdone_reg2 <= 1'd0;
+        txphaligndone_reg2   <= 1'd0;
+        txsyncdone_reg2      <= 1'd0;
+        
+        rxsync_start_reg2	   <= 1'd0; 
+        rxdlysresetdone_reg2 <= 1'd0;
+        rxphaligndone_m_reg2 <= 1'd0;
+        rxphaligndone_s_reg2 <= 1'd0;
+        rxsync_donem_reg2    <= 1'd0;
+        rxsyncdone_reg2      <= 1'd0;
+        //---------- 3rd Stage FF --------------------------
+        txsync_start_reg3	   <= 1'd0;
+        txphinitdone_reg3    <= 1'd0;
+        txdlysresetdone_reg3 <= 1'd0;
+        txphaligndone_reg3   <= 1'd0;
+        txsyncdone_reg3      <= 1'd0;
+        
+        end
+    else
+        begin  
+        //---------- 1st Stage FF --------------------------
+        gen3_reg1            <= SYNC_GEN3;
+        rate_idle_reg1       <= SYNC_RATE_IDLE;
+        mmcm_lock_reg1       <= SYNC_MMCM_LOCK;
+        rxelecidle_reg1      <= SYNC_RXELECIDLE; 
+        rxcdrlock_reg1       <= SYNC_RXCDRLOCK;
+
+        txsync_start_reg1    <= SYNC_TXSYNC_START;
+        txphinitdone_reg1    <= SYNC_TXPHINITDONE;
+        txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE;
+        txphaligndone_reg1   <= SYNC_TXPHALIGNDONE;
+        txsyncdone_reg1      <= SYNC_TXSYNCDONE;
+        
+        rxsync_start_reg1	   <= SYNC_RXSYNC_START; 
+        rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE;
+        rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M;
+        rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S;
+        rxsync_donem_reg1    <= SYNC_RXSYNC_DONEM_IN;
+        rxsyncdone_reg1      <= SYNC_RXSYNCDONE; 
+        //---------- 2nd Stage FF --------------------------
+        gen3_reg2            <= gen3_reg1;
+        rate_idle_reg2       <= rate_idle_reg1;
+        mmcm_lock_reg2       <= mmcm_lock_reg1;
+        rxelecidle_reg2      <= rxelecidle_reg1;
+        rxcdrlock_reg2       <= rxcdrlock_reg1;
+        
+        txsync_start_reg2    <= txsync_start_reg1;       
+        txphinitdone_reg2    <= txphinitdone_reg1; 
+        txdlysresetdone_reg2 <= txdlysresetdone_reg1;   
+        txphaligndone_reg2   <= txphaligndone_reg1;
+        txsyncdone_reg2      <= txsyncdone_reg1;
+        
+        rxsync_start_reg2    <= rxsync_start_reg1;
+        rxdlysresetdone_reg2 <= rxdlysresetdone_reg1; 
+        rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
+        rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
+        rxsync_donem_reg2    <= rxsync_donem_reg1; 
+        rxsyncdone_reg2      <= rxsyncdone_reg1;
+        //---------- 3rd Stage FF --------------------------
+        txsync_start_reg3    <= txsync_start_reg2;	   
+        txphinitdone_reg3    <= txphinitdone_reg2;    
+        txdlysresetdone_reg3 <= txdlysresetdone_reg2; 
+        txphaligndone_reg3   <= txphaligndone_reg2;   
+        txsyncdone_reg3      <= txsyncdone_reg2;      
+        end
+        
+end       
+
+
+
+//---------- Generate TX Sync FSM ----------------------------------------------
+generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE")) 
+
+    begin : txsync_fsm
+
+    //---------- PIPE TX Sync FSM ----------------------------------------------
+    always @ (posedge SYNC_CLK)
+    begin
+    
+        if (!SYNC_RST_N)
+            begin
+            fsm_tx      <= FSM_TXSYNC_IDLE;   
+            txdlyen     <= 1'd0; 
+            txsync_done <= 1'd0;
+            end                    
+        else
+            begin
+            
+            case (fsm_tx)
+            
+            //---------- Idle State ------------------------
+            FSM_TXSYNC_IDLE :
+            
+                begin     
+                //---------- Exiting Reset or Rate Change --
+                if (txsync_start_reg2)
+                    begin
+                    fsm_tx      <= FSM_MMCM_LOCK;
+                    txdlyen     <= 1'd0; 
+                    txsync_done <= 1'd0;
+                    end
+                else
+                    begin
+                    fsm_tx      <= FSM_TXSYNC_IDLE;
+                    txdlyen     <= txdlyen; 
+                    txsync_done <= txsync_done;
+                    end
+                end
+                
+            //---------- Check MMCM Lock -------------------
+            FSM_MMCM_LOCK :
+            
+                begin
+                fsm_tx      <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK);
+                txdlyen     <= 1'd0; 
+                txsync_done <= 1'd0;  
+                end
+                
+            //---------- TX Delay Soft Reset --------------- 
+            FSM_TXSYNC_START :
+            
+                begin
+                fsm_tx      <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
+                txdlyen     <= 1'd0; 
+                txsync_done <= 1'd0;
+                end
+                
+            //---------- Wait for TX Phase Init Done (Manual Mode Only)
+            FSM_TXPHINITDONE :
+            
+                begin
+                fsm_tx      <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
+                txdlyen     <= 1'd0; 
+                txsync_done <= 1'd0;
+                end
+                
+            //---------- Wait for TX Phase Alignment Done --
+            FSM_TXSYNC_DONE1 :
+            
+                begin
+                if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
+                   fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2)       || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1); 
+                else
+                   fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1); 
+                
+                txdlyen     <= 1'd0; 
+                txsync_done <= 1'd0;
+                end  
+                
+            //---------- Wait for Master TX Delay Alignment Done 
+            FSM_TXSYNC_DONE2 :
+            
+                begin
+                if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1)) 
+                    begin
+                    fsm_tx      <= FSM_TXSYNC_IDLE;
+                    txdlyen     <= !SYNC_SLAVE; 
+                    txsync_done <= 1'd1;
+                    end
+                else
+                    begin
+                    fsm_tx      <= FSM_TXSYNC_DONE2;
+                    txdlyen     <= !SYNC_SLAVE; 
+                    txsync_done <= 1'd0;
+                    end
+                end         
+                              
+            //---------- Default State ---------------------
+            default :
+                begin 
+                fsm_tx      <= FSM_TXSYNC_IDLE;
+                txdlyen     <= 1'd0; 
+                txsync_done <= 1'd0;
+                end
+                
+            endcase
+            
+            end
+            
+    end     
+
+    end  
+          
+//---------- TX Sync FSM Default------------------------------------------------
+else 
+
+    begin : txsync_fsm_disable
+       
+    //---------- Default -------------------------------------------------------
+    always @ (posedge SYNC_CLK)
+    begin    
+        fsm_tx      <= FSM_TXSYNC_IDLE;
+        txdlyen     <= 1'd0;
+        txsync_done <= 1'd0; 
+    end
+
+    end 
+
+endgenerate  
+
+          
+       
+//---------- Generate RX Sync FSM ----------------------------------------------
+generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE")) 
+
+    begin : rxsync_fsm
+   
+    //---------- PIPE RX Sync FSM ----------------------------------------------
+    always @ (posedge SYNC_CLK)
+    begin
+    
+        if (!SYNC_RST_N)
+            begin
+            fsm_rx      <= FSM_RXSYNC_IDLE; 
+            rxdlyen     <= 1'd0;
+            rxsync_done <= 1'd0;   
+            end                    
+        else
+            begin
+            
+            case (fsm_rx)
+            
+            //---------- Idle State ------------------------
+            FSM_RXSYNC_IDLE :
+            
+                begin
+                //---------- Exiting Rate Change -----------
+                if (rxsync_start_reg2)
+                    begin
+                    fsm_rx      <= FSM_RXCDRLOCK;
+                    rxdlyen     <= 1'd0;
+                    rxsync_done <= 1'd0;
+                    end
+                //---------- Exiting Electrical Idle without Rate Change 
+                else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0)))
+                    begin
+                    fsm_rx      <= FSM_RXCDRLOCK;
+                    rxdlyen     <= 1'd0;
+                    rxsync_done <= 1'd0;   
+                    end 
+                //---------- Idle --------------------------
+                else                    
+                    begin
+                    fsm_rx      <= FSM_RXSYNC_IDLE;
+                    rxdlyen     <= rxelecidle_reg2 ? 1'd0 : rxdlyen;
+                    rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done;
+                    end
+                end
+                
+            //---------- Wait for RX Electrical Idle Exit and RX CDR Lock 
+            FSM_RXCDRLOCK :
+            
+                begin
+                fsm_rx      <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK);
+                rxdlyen     <= 1'd0;
+                rxsync_done <= 1'd0;
+                end
+                
+            //---------- Start RX Sync with RX Delay Soft Reset
+            FSM_RXSYNC_START :
+            
+                begin
+                fsm_rx      <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START);
+                rxdlyen     <= 1'd0;
+                rxsync_done <= 1'd0;
+                end     
+                      
+            //---------- Wait for RX Phase Alignment Done --
+            FSM_RXSYNC_DONE1 :
+            
+                begin
+                if (SYNC_SLAVE)
+                    begin
+                    fsm_rx      <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
+                    rxdlyen     <= 1'd0;
+                    rxsync_done <= 1'd0;
+                    end
+                else
+                    begin
+                    fsm_rx      <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
+                    rxdlyen     <= 1'd0;
+                    rxsync_done <= 1'd0;
+                    end
+                end  
+                
+            //---------- Wait for Master RX Delay Alignment Done 
+            FSM_RXSYNC_DONE2 :
+            
+                begin   
+                if (SYNC_SLAVE)
+                    begin
+                    fsm_rx      <= FSM_RXSYNC_IDLE;
+                    rxdlyen     <= 1'd0;
+                    rxsync_done <= 1'd1;
+                    end
+                else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1)) 
+                    begin
+                    fsm_rx      <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES);
+                    rxdlyen     <=  (PCIE_LANE == 1);
+                    rxsync_done <=  (PCIE_LANE == 1);
+                    end
+                else
+                    begin
+                    fsm_rx      <= FSM_RXSYNC_DONE2;
+                    rxdlyen     <= 1'd1;
+                    rxsync_done <= 1'd0;
+                    end
+                end     
+                
+            //---------- Wait for Slave RX Phase Alignment Done 
+            FSM_RXSYNC_DONES :
+            
+                begin
+                if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) 
+                    begin
+                    fsm_rx      <= FSM_RXSYNC_DONEM;
+                    rxdlyen     <= 1'd1;
+                    rxsync_done <= 1'd0;
+                    end
+                else
+                    begin
+                    fsm_rx      <= FSM_RXSYNC_DONES;
+                    rxdlyen     <= 1'd0;
+                    rxsync_done <= 1'd0;
+                    end
+                end           
+                   
+            //---------- Wait for Master RX Delay Alignment Done 
+            FSM_RXSYNC_DONEM :
+            
+                begin
+                if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1)) 
+                    begin
+                    fsm_rx      <= FSM_RXSYNC_IDLE;
+                    rxdlyen     <= 1'd1;
+                    rxsync_done <= 1'd1;
+                    end
+                else
+                    begin
+                    fsm_rx      <= FSM_RXSYNC_DONEM;
+                    rxdlyen     <= 1'd1;
+                    rxsync_done <= 1'd0;
+                    end
+                end         
+                              
+            //---------- Default State ---------------------
+            default : 
+                begin
+                fsm_rx      <= FSM_RXSYNC_IDLE;
+                rxdlyen     <= 1'd0;
+                rxsync_done <= 1'd0;
+                end    
+                        
+        	   endcase
+            
+            end
+            
+    end            
+        
+    end  
+          
+//---------- RX Sync FSM Default -----------------------------------------------
+else 
+
+    begin : rxsync_fsm_disable
+       
+    //---------- Default -------------------------------------------------------
+    always @ (posedge SYNC_CLK)
+    begin    
+        fsm_rx      <= FSM_RXSYNC_IDLE;
+        rxdlyen     <= 1'd0;
+        rxsync_done <= 1'd0; 
+    end
+
+    end 
+
+endgenerate      
+   
+
+
+//---------- PIPE Sync Output --------------------------------------------------            
+assign SYNC_TXPHALIGNEN      = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1;   
+assign SYNC_TXDLYBYPASS      = 1'd0;                     
+//assign SYNC_TXDLYSRESET    = !(((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0; 
+assign SYNC_TXDLYSRESET      = (fsm_tx == FSM_TXSYNC_START);
+assign SYNC_TXPHDLYRESET     =  (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;   
+assign SYNC_TXPHINIT         = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE); 
+assign SYNC_TXPHALIGN        = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1);
+assign SYNC_TXDLYEN          = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen;
+assign SYNC_TXSYNC_DONE      = txsync_done;
+assign SYNC_FSM_TX           = fsm_tx;
+
+assign SYNC_RXPHALIGNEN      = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1;  
+assign SYNC_RXDLYBYPASS      = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE");
+assign SYNC_RXDLYSRESET      = (fsm_rx == FSM_RXSYNC_START);
+assign SYNC_RXPHALIGN        = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1)));
+assign SYNC_RXDLYEN          = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen;
+assign SYNC_RXDDIEN          = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE"); 
+assign SYNC_RXSYNC_DONE      = rxsync_done;
+assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES);
+assign SYNC_FSM_RX	         = fsm_rx;  
+
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_pipe_user.v

@@ -0,0 +1,605 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_pipe_user.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  pipe_user.v
+//  Description  :  PIPE User Module for 7 Series Transceiver
+//  Version      :  15.3.3
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- PIPE User Module --------------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_pipe_user #
+(
+
+    parameter PCIE_SIM_MODE    = "FALSE",                   // PCIe sim mode 
+    parameter PCIE_USE_MODE    = "3.0",                     // PCIe sim version
+    parameter PCIE_OOBCLK_MODE = 1,                         // PCIe OOB clock mode
+    parameter RXCDRLOCK_MAX    = 4'd15,                     // RXCDRLOCK max count
+    parameter RXVALID_MAX      = 4'd15,                     // RXVALID max count
+    parameter CONVERGE_MAX     = 22'd3125000                // Convergence max count
+    
+)
+
+(
+
+    //---------- Input -------------------------------------
+    input               USER_TXUSRCLK,
+    input               USER_RXUSRCLK,
+    input               USER_OOBCLK_IN,
+    input               USER_RST_N,
+    input               USER_RXUSRCLK_RST_N,
+    input               USER_PCLK_SEL,
+    input               USER_RESETOVRD_START,
+    input               USER_TXRESETDONE,
+    input               USER_RXRESETDONE,
+    input               USER_TXELECIDLE,
+    input               USER_TXCOMPLIANCE,
+    input               USER_RXCDRLOCK_IN,
+    input               USER_RXVALID_IN,
+    input               USER_RXSTATUS_IN,
+    input               USER_PHYSTATUS_IN,
+    input               USER_RATE_DONE, 
+    input               USER_RST_IDLE,
+    input               USER_RATE_RXSYNC,
+    input               USER_RATE_IDLE,
+    input               USER_RATE_GEN3,
+    input               USER_RXEQ_ADAPT_DONE,
+    
+    //---------- Output ------------------------------------
+    output              USER_OOBCLK,
+    output              USER_RESETOVRD,
+    output              USER_TXPMARESET,                            
+    output              USER_RXPMARESET,                           
+    output              USER_RXCDRRESET,               
+    output              USER_RXCDRFREQRESET,           
+    output              USER_RXDFELPMRESET,            
+    output              USER_EYESCANRESET,             
+    output              USER_TXPCSRESET,                              
+    output              USER_RXPCSRESET,                            
+    output              USER_RXBUFRESET,   
+    output              USER_RESETOVRD_DONE,            
+    output              USER_RESETDONE,
+    output              USER_ACTIVE_LANE,
+    output              USER_RXCDRLOCK_OUT,
+    output              USER_RXVALID_OUT,
+    output              USER_PHYSTATUS_OUT,
+    output              USER_PHYSTATUS_RST,
+    output              USER_GEN3_RDY,
+    output              USER_RX_CONVERGE 
+
+);
+    
+    //---------- Input Registers ---------------------------   
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 pclk_sel_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 resetovrd_start_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txresetdone_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxresetdone_reg1; 
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txelecidle_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txcompliance_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxcdrlock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxvalid_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxstatus_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_done_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rst_idle_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_rxsync_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_idle_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_gen3_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxeq_adapt_done_reg1;
+
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 pclk_sel_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 resetovrd_start_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txresetdone_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxresetdone_reg2; 
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txelecidle_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 txcompliance_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)	  reg	              rxcdrlock_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxvalid_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxstatus_reg2; 
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_done_reg2;   
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rst_idle_reg2; 
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_rxsync_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_idle_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rate_gen3_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rxeq_adapt_done_reg2;
+    
+    //---------- Internal Signal ---------------------------
+    reg         [ 7:0]  reset_cnt     =  8'd127;
+    reg         [ 3:0]  rxcdrlock_cnt =  4'd0;
+    reg         [ 3:0]  rxvalid_cnt   =  4'd0;
+    reg         [21:0]  converge_cnt  = 22'd0;
+    reg                 converge_gen3 =  1'd0;
+    
+    //---------- Output Registers --------------------------
+    reg                 oobclk   = 1'd0;
+    reg         [ 7:0]  reset    = 8'h00;
+    reg                 gen3_rdy = 1'd0;
+    reg         [ 1:0]  fsm      = 2'd0;
+    
+    //---------- FSM ---------------------------------------                                         
+    localparam          FSM_IDLE       = 2'd0; 
+    localparam          FSM_RESETOVRD  = 2'd1;
+    localparam          FSM_RESET_INIT = 2'd2;
+    localparam          FSM_RESET      = 2'd3;    
+    
+    //---------- Simulation Speedup ------------------------
+    localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd100 : CONVERGE_MAX;                                                              
+
+
+
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge USER_TXUSRCLK)
+begin
+
+    if (!USER_RST_N)
+        begin    
+        //---------- 1st Stage FF --------------------------  
+        pclk_sel_reg1        <= 1'd0; 
+        resetovrd_start_reg1 <= 1'd0;
+        txresetdone_reg1     <= 1'd0;
+        rxresetdone_reg1     <= 1'd0; 
+        txelecidle_reg1      <= 1'd0;
+        txcompliance_reg1    <= 1'd0;
+        rxcdrlock_reg1 	     <= 1'd0;
+        rxeq_adapt_done_reg1 <= 1'd0;
+        //---------- 2nd Stage FF --------------------------
+        pclk_sel_reg2        <= 1'd0;
+        resetovrd_start_reg2 <= 1'd0;
+        txresetdone_reg2     <= 1'd0;
+        rxresetdone_reg2     <= 1'd0; 
+        txelecidle_reg2      <= 1'd0;
+        txcompliance_reg2    <= 1'd0;
+        rxcdrlock_reg2 	     <= 1'd0;
+        rxeq_adapt_done_reg2 <= 1'd0;
+        end
+    else
+        begin  
+        //---------- 1st Stage FF --------------------------
+        pclk_sel_reg1        <= USER_PCLK_SEL;
+        resetovrd_start_reg1 <= USER_RESETOVRD_START;
+        txresetdone_reg1     <= USER_TXRESETDONE;
+        rxresetdone_reg1     <= USER_RXRESETDONE;
+        txelecidle_reg1      <= USER_TXELECIDLE;
+        txcompliance_reg1    <= USER_TXCOMPLIANCE;
+        rxcdrlock_reg1 	     <= USER_RXCDRLOCK_IN;
+        rxeq_adapt_done_reg1 <= USER_RXEQ_ADAPT_DONE;
+        //---------- 2nd Stage FF --------------------------
+        pclk_sel_reg2        <= pclk_sel_reg1;
+        resetovrd_start_reg2 <= resetovrd_start_reg1;
+        txresetdone_reg2     <= txresetdone_reg1;      
+        rxresetdone_reg2     <= rxresetdone_reg1;      
+        txelecidle_reg2      <= txelecidle_reg1;       
+        txcompliance_reg2    <= txcompliance_reg1;  
+        rxcdrlock_reg2 	     <= rxcdrlock_reg1;  
+        rxeq_adapt_done_reg2 <= rxeq_adapt_done_reg1;
+        end
+        
+end 
+
+
+
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge USER_RXUSRCLK)
+begin
+
+    if (!USER_RXUSRCLK_RST_N)
+        begin    
+        //---------- 1st Stage FF --------------------------   
+        rxvalid_reg1     <= 1'd0;
+        rxstatus_reg1    <= 1'd0;
+        rst_idle_reg1    <= 1'd0; 
+        rate_done_reg1   <= 1'd0;
+        rate_rxsync_reg1 <= 1'd0;
+        rate_idle_reg1   <= 1'd0;
+        rate_gen3_reg1   <= 1'd0;
+        //---------- 2nd Stage FF --------------------------
+        rxvalid_reg2     <= 1'd0;
+        rxstatus_reg2    <= 1'd0;
+        rst_idle_reg2    <= 1'd0; 
+        rate_done_reg2   <= 1'd0;
+        rate_rxsync_reg2 <= 1'd0;
+        rate_idle_reg2   <= 1'd0;
+        rate_gen3_reg2   <= 1'd0;
+        end
+    else
+        begin  
+        //---------- 1st Stage FF --------------------------
+        rxvalid_reg1     <= USER_RXVALID_IN;
+        rxstatus_reg1    <= USER_RXSTATUS_IN;
+        rst_idle_reg1    <= USER_RST_IDLE; 
+        rate_done_reg1   <= USER_RATE_DONE;
+        rate_rxsync_reg1 <= USER_RATE_RXSYNC;
+        rate_idle_reg1   <= USER_RATE_IDLE;
+        rate_gen3_reg1   <= USER_RATE_GEN3;
+        //---------- 2nd Stage FF --------------------------  	   
+        rxvalid_reg2     <= rxvalid_reg1;            
+        rxstatus_reg2    <= rxstatus_reg1; 
+        rst_idle_reg2    <= rst_idle_reg1;
+        rate_done_reg2   <= rate_done_reg1;  
+        rate_rxsync_reg2 <= rate_rxsync_reg1;
+        rate_idle_reg2   <= rate_idle_reg1;
+        rate_gen3_reg2   <= rate_gen3_reg1;      
+        end
+        
+end 
+
+
+
+//---------- Generate Reset Override -------------------------------------------
+generate if (PCIE_USE_MODE == "1.0") 
+
+    begin : resetovrd
+
+    //---------- Reset Counter -------------------------------------------------
+    always @ (posedge USER_TXUSRCLK)
+    begin
+    
+        if (!USER_RST_N)
+            reset_cnt <= 8'd127;
+        else
+        
+            //---------- Decrement Counter ---------------------
+            if (((fsm == FSM_RESETOVRD) || (fsm == FSM_RESET)) && (reset_cnt != 8'd0))
+                reset_cnt <= reset_cnt - 8'd1;
+                
+            //---------- Reset Counter -------------------------
+            else 
+            
+                case (reset) 
+                8'b00000000 : reset_cnt <= 8'd127;              // Programmable PMARESET       time
+                8'b11111111 : reset_cnt <= 8'd127;              // Programmable RXCDRRESET     time
+                8'b11111110 : reset_cnt <= 8'd127;              // Programmable RXCDRFREQRESET time
+                8'b11111100 : reset_cnt <= 8'd127;              // Programmable RXDFELPMRESET  time
+                8'b11111000 : reset_cnt <= 8'd127;              // Programmable EYESCANRESET   time
+                8'b11110000 : reset_cnt <= 8'd127;              // Programmable PCSRESET       time
+                8'b11100000 : reset_cnt <= 8'd127;              // Programmable RXBUFRESET     time
+                8'b11000000 : reset_cnt <= 8'd127;              // Programmable RESETOVRD deassertion time
+                8'b10000000 : reset_cnt <= 8'd127;
+                default     : reset_cnt <= 8'd127; 
+                endcase
+                
+    end 
+    
+    
+    
+    //---------- Reset Shift Register ------------------------------------------
+    always @ (posedge USER_TXUSRCLK)
+    begin
+    
+        if (!USER_RST_N)
+            reset <= 8'h00;
+        else
+        
+            //---------- Initialize Reset Register ---------
+            if (fsm == FSM_RESET_INIT)
+                reset <= 8'hFF;   
+            //---------- Shift Reset Register --------------
+            else if ((fsm == FSM_RESET) && (reset_cnt == 8'd0))
+                reset <= {reset[6:0], 1'd0};        
+            //---------- Hold Reset Register ---------------
+            else
+                reset <= reset;
+            
+    end
+         
+            
+    
+    //---------- Reset Override FSM --------------------------------------------
+    always @ (posedge USER_TXUSRCLK)
+    begin
+    
+        if (!USER_RST_N)
+            fsm <= FSM_IDLE;     
+                           
+        else
+        
+            begin
+            
+            case (fsm)
+            //---------- Idle State ------------------------
+            FSM_IDLE       : fsm <= resetovrd_start_reg2 ? FSM_RESETOVRD : FSM_IDLE;
+            //---------- Assert RESETOVRD ------------------
+            FSM_RESETOVRD  : fsm <= (reset_cnt == 8'd0) ? FSM_RESET_INIT : FSM_RESETOVRD;
+            //---------- Initialize Reset ------------------
+            FSM_RESET_INIT : fsm <= FSM_RESET;
+            //---------- Shift Reset -----------------------
+            FSM_RESET      : fsm <= ((reset == 8'd0) && rxresetdone_reg2) ? FSM_IDLE : FSM_RESET;  
+            //---------- Default State ---------------------
+            default        : fsm <= FSM_IDLE;
+        	  endcase
+            
+            end
+    
+    end
+    
+    end 
+
+//---------- Disable Reset Override --------------------------------------------
+else 
+
+    begin : resetovrd_disble
+
+    //---------- Generate Default Signals --------------------------------------
+    always @ (posedge USER_TXUSRCLK)
+    begin    
+    
+       if (!USER_RST_N)
+           begin   
+           reset_cnt <= 8'hFF;
+           reset     <= 8'd0;
+           fsm       <= 2'd0; 
+           end
+       else
+           begin   
+           reset_cnt <= 8'hFF;
+           reset     <= 8'd0;
+           fsm       <= 2'd0; 
+           end
+        
+    end
+
+    end
+
+endgenerate
+
+
+
+reg         [ 1:0]  oobclk_cnt    =  2'd0;
+//---------- Generate OOB Clock Divider ------------------------
+generate if (PCIE_OOBCLK_MODE == 1) 
+
+    begin : oobclk_div
+
+    //---------- OOB Clock Divider -----------------------------
+    always @ (posedge USER_OOBCLK_IN)
+    begin
+    
+        if (!USER_RST_N)
+            begin
+            oobclk_cnt <= 2'd0;
+            oobclk     <= 1'd0;
+            end
+        else
+            begin
+            oobclk_cnt <= oobclk_cnt + 2'd1;
+            oobclk     <= pclk_sel_reg2 ? oobclk_cnt[1] : oobclk_cnt[0];
+            end
+            
+    end 
+    
+    end
+   
+else
+
+    begin : oobclk_div_disable
+
+    //---------- OOB Clock Default -------------------------
+    always @ (posedge USER_OOBCLK_IN)
+    begin
+    
+        if (!USER_RST_N)
+            begin
+            oobclk_cnt <= 2'd0;
+            oobclk     <= 1'd0;
+            end
+        else
+            begin
+            oobclk_cnt <= 2'd0;
+            oobclk     <= 1'd0;
+            end
+            
+    end 
+    
+    end   
+   
+endgenerate
+
+//---------- RXCDRLOCK Filter --------------------------------------------------
+always @ (posedge USER_TXUSRCLK)
+begin
+
+    if (!USER_RST_N)
+        rxcdrlock_cnt <= 4'd0;
+    else
+    
+        //---------- Increment RXCDRLOCK Counter -----------
+        if (rxcdrlock_reg2 && (rxcdrlock_cnt != RXCDRLOCK_MAX))
+            rxcdrlock_cnt <= rxcdrlock_cnt + 4'd1;
+            
+        //---------- Hold RXCDRLOCK Counter ----------------
+        else if (rxcdrlock_reg2 && (rxcdrlock_cnt == RXCDRLOCK_MAX))
+            rxcdrlock_cnt <= rxcdrlock_cnt;
+            
+        //---------- Reset RXCDRLOCK Counter ---------------
+        else
+            rxcdrlock_cnt <= 4'd0;
+        
+end 
+
+
+
+//---------- RXVALID Filter ----------------------------------------------------
+always @ (posedge USER_RXUSRCLK)
+begin
+
+    if (!USER_RXUSRCLK_RST_N)
+        rxvalid_cnt <= 4'd0;
+    else
+    
+        //---------- Increment RXVALID Counter -------------
+        if (rxvalid_reg2 && (rxvalid_cnt != RXVALID_MAX) && (!rxstatus_reg2))
+            rxvalid_cnt <= rxvalid_cnt + 4'd1;
+            
+        //---------- Hold RXVALID Counter ------------------
+        else if (rxvalid_reg2 && (rxvalid_cnt == RXVALID_MAX))
+            rxvalid_cnt <= rxvalid_cnt;
+            
+        //---------- Reset RXVALID Counter -----------------
+        else
+            rxvalid_cnt <= 4'd0;
+        
+end 
+
+
+
+//---------- Converge Counter --------------------------------------------------
+always @ (posedge USER_TXUSRCLK)
+begin
+
+    if (!USER_RST_N)
+        converge_cnt <= 22'd0;
+    else
+    
+        //---------- Enter Gen1/Gen2 -----------------------
+        if (rst_idle_reg2 && rate_idle_reg2 && !rate_gen3_reg2)
+            begin
+            
+            //---------- Increment Converge Counter --------
+            if (converge_cnt < converge_max_cnt) 
+                converge_cnt <= converge_cnt + 22'd1;
+            //---------- Hold Converge Counter -------------
+            else 
+                converge_cnt <= converge_cnt;
+                
+            end
+            
+        //---------- Reset Converge Counter ----------------
+        else
+            converge_cnt <= 22'd0;
+        
+end 
+
+
+
+//---------- Converge ----------------------------------------------------------
+always @ (posedge USER_TXUSRCLK)
+begin
+
+    if (!USER_RST_N)
+        converge_gen3 <= 1'd0;
+    else
+    
+        //---------- Enter Gen3 ----------------------------
+        if (rate_gen3_reg2)
+        
+            //---------- Wait for RX equalization adapt done 
+            if (rxeq_adapt_done_reg2)
+                converge_gen3 <= 1'd1;
+            else
+                converge_gen3 <= converge_gen3;
+        
+        //-------- Exit Gen3 -------------------------------
+        else
+        
+            converge_gen3 <= 1'd0;
+        
+        
+end 
+
+
+
+//---------- GEN3_RDY Generator ------------------------------------------------
+always @ (posedge USER_RXUSRCLK)
+begin
+
+    if (!USER_RXUSRCLK_RST_N)
+        gen3_rdy <= 1'd0;
+    else   
+        gen3_rdy <= rate_idle_reg2 && rate_gen3_reg2;    
+        
+end 
+
+
+
+//---------- PIPE User Override Reset Output -----------------------------------  
+assign USER_RESETOVRD      = (fsm != FSM_IDLE);
+assign USER_TXPMARESET     = 1'd0; 
+assign USER_RXPMARESET     = reset[0];  
+assign USER_RXCDRRESET     = reset[1];
+assign USER_RXCDRFREQRESET = reset[2];
+assign USER_RXDFELPMRESET  = reset[3];
+assign USER_EYESCANRESET   = reset[4];
+assign USER_TXPCSRESET     = 1'd0;  
+assign USER_RXPCSRESET     = reset[5];  
+assign USER_RXBUFRESET     = reset[6];  
+assign USER_RESETOVRD_DONE = (fsm == FSM_IDLE);
+
+//---------- PIPE User Output --------------------------------------------------
+assign USER_OOBCLK         = oobclk; 
+assign USER_RESETDONE      = (txresetdone_reg2 && rxresetdone_reg2);
+assign USER_ACTIVE_LANE    = !(txelecidle_reg2 && txcompliance_reg2);
+//----------------------------------------------------------
+assign USER_RXCDRLOCK_OUT  = (USER_RXCDRLOCK_IN && (rxcdrlock_cnt == RXCDRLOCK_MAX));        // Filtered RXCDRLOCK
+//----------------------------------------------------------
+assign USER_RXVALID_OUT    = ((USER_RXVALID_IN  && (rxvalid_cnt == RXVALID_MAX)) &&          // Filtered RXVALID
+                              rst_idle_reg2                                      &&          // Force RXVALID = 0 during reset
+                              rate_idle_reg2);                                               // Force RXVALID = 0 during rate change
+//----------------------------------------------------------
+assign USER_PHYSTATUS_OUT  = (!rst_idle_reg2                                              || // Force PHYSTATUS = 1 during reset
+                              ((rate_idle_reg2 || rate_rxsync_reg2) && USER_PHYSTATUS_IN) || // Raw PHYSTATUS
+                              rate_done_reg2);                                               // Gated PHYSTATUS for rate change
+//----------------------------------------------------------
+assign USER_PHYSTATUS_RST  = !rst_idle_reg2;                                                 // Filtered PHYSTATUS for reset
+//----------------------------------------------------------
+assign USER_GEN3_RDY       = 0;//gen3_rdy;                                                      
+//----------------------------------------------------------
+assign USER_RX_CONVERGE    = (converge_cnt == converge_max_cnt) || converge_gen3;   
+
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_qpll_drp.v

@@ -0,0 +1,550 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_qpll_drp.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  qpll_drp.v
+//  Description  :  QPLL DRP Module for 7 Series Transceiver
+//  Version      :  18.2
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- QPLL DRP Module ---------------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_qpll_drp #
+(
+
+    parameter PCIE_GT_DEVICE   = "GTX",                     // PCIe GT device
+    parameter PCIE_USE_MODE    = "3.0",                     // PCIe use mode
+    parameter PCIE_PLL_SEL     = "CPLL",                    // PCIe PLL select for Gen1/Gen2 only
+    parameter PCIE_REFCLK_FREQ = 0,                         // PCIe reference clock frequency
+    parameter LOAD_CNT_MAX     = 2'd3,                      // Load max count
+    parameter INDEX_MAX        = 3'd6                       // Index max count
+        
+)
+
+(
+    
+    //---------- Input -------------------------------------
+    input               DRP_CLK,
+    input               DRP_RST_N,
+    input               DRP_OVRD,
+    input               DRP_GEN3,
+    input               DRP_QPLLLOCK,
+    input               DRP_START,
+    input       [15:0]  DRP_DO,
+    input               DRP_RDY,
+    
+    //---------- Output ------------------------------------
+    output      [ 7:0]  DRP_ADDR,
+    output              DRP_EN,  
+    output      [15:0]  DRP_DI,   
+    output              DRP_WE,
+    output              DRP_DONE,
+    output              DRP_QPLLRESET,
+    output      [ 5:0]  DRP_CRSCODE,
+    output      [ 8:0]  DRP_FSM
+    
+);
+
+    //---------- Input Registers ---------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 ovrd_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 gen3_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 qplllock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 start_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [15:0]  do_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rdy_reg1;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 ovrd_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 gen3_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 qplllock_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 start_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [15:0]  do_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 rdy_reg2;
+    
+    //---------- Internal Signals --------------------------
+    reg         [ 1:0]  load_cnt =  2'd0;
+    reg         [ 2:0]  index    =  3'd0;
+    reg                 mode     =  1'd0;
+    reg         [ 5:0]  crscode  =  6'd0;
+    
+    //---------- Output Registers --------------------------
+    reg         [ 7:0]  addr    =  8'd0;
+    reg         [15:0]  di      = 16'd0;
+    reg                 done    =  1'd0;
+    reg         [ 8:0]  fsm     =  7'd1;      
+                        
+    //---------- DRP Address -------------------------------  
+    localparam          ADDR_QPLL_FBDIV               = 8'h36;
+    localparam          ADDR_QPLL_CFG                 = 8'h32;
+    localparam          ADDR_QPLL_LPF                 = 8'h31;  
+    localparam          ADDR_CRSCODE                  = 8'h88;  
+    localparam          ADDR_QPLL_COARSE_FREQ_OVRD    = 8'h35;
+    localparam          ADDR_QPLL_COARSE_FREQ_OVRD_EN = 8'h36;  
+    localparam          ADDR_QPLL_LOCK_CFG            = 8'h34;
+    
+    //---------- DRP Mask ----------------------------------
+    localparam          MASK_QPLL_FBDIV               = 16'b1111110000000000;  // Unmask bit [ 9: 0] 
+    localparam          MASK_QPLL_CFG                 = 16'b1111111110111111;  // Unmask bit [    6]
+    localparam          MASK_QPLL_LPF                 = 16'b1000011111111111;  // Unmask bit [14:11]
+    localparam          MASK_QPLL_COARSE_FREQ_OVRD    = 16'b0000001111111111;  // Unmask bit [15:10] 
+    localparam          MASK_QPLL_COARSE_FREQ_OVRD_EN = 16'b1111011111111111;  // Unmask bit [   11]      
+    localparam          MASK_QPLL_LOCK_CFG            = 16'b1110011111111111;  // Unmask bit [12:11]     
+
+    //---------- DRP Data for Normal QPLLLOCK Mode ---------
+    localparam          NORM_QPLL_COARSE_FREQ_OVRD    = 16'b0000000000000000;  // Coarse freq value
+    localparam          NORM_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000000000000000;  // Normal QPLL lock  
+    localparam          NORM_QPLL_LOCK_CFG            = 16'b0000000000000000;  // Normal QPLL lock config 
+     
+    //---------- DRP Data for Optimize QPLLLOCK Mode -------
+    localparam          OVRD_QPLL_COARSE_FREQ_OVRD    = 16'b0000000000000000;  // Coarse freq value
+    localparam          OVRD_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000100000000000;  // Override QPLL lock 
+    localparam          OVRD_QPLL_LOCK_CFG            = 16'b0000000000000000;  // Override QPLL lock config 
+    
+    //---------- Select QPLL Feedback Divider --------------
+    //  N = 100 for 100 MHz ref clk and 10Gb/s line rate
+    //  N =  80 for 125 MHz ref clk and 10Gb/s line rate
+    //  N =  40 for 250 MHz ref clk and 10Gb/s line rate
+    //------------------------------------------------------
+    //  N =  80 for 100 MHz ref clk and  8Gb/s line rate
+    //  N =  64 for 125 MHz ref clk and  8Gb/s line rate
+    //  N =  32 for 250 MHz ref clk and  8Gb/s line rate
+    //------------------------------------------------------
+    localparam          QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000010000000 : 
+                                     (PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000100100000 : 
+                                     (PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000101110000 : 
+                                     (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000001100000 : 
+                                     (PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000011100000 : 16'b0000000100100000;
+    
+    localparam          GEN12_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000010000000 : 
+                                           (PCIE_REFCLK_FREQ == 1) ? 16'b0000000100100000 : 16'b0000000101110000;
+
+    localparam          GEN3_QPLL_FBDIV  = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000001100000 : 
+                                           (PCIE_REFCLK_FREQ == 1) ? 16'b0000000011100000 : 16'b0000000100100000;
+     
+    //---------- Select QPLL Configuration ---------------------------
+    //  QPLL_CFG[6] = 0 for upper band
+    //              = 1 for lower band
+    //----------------------------------------------------------------
+    localparam          GEN12_QPLL_CFG = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000000 : 16'b0000000001000000;
+    localparam          GEN3_QPLL_CFG  = 16'b0000000001000000;  
+     
+    //---------- Select QPLL LPF -------------------------------------
+    localparam          GEN12_QPLL_LPF = (PCIE_PLL_SEL == "QPLL") ? 16'b0_0100_00000000000 : 16'b0_1101_00000000000;
+    localparam          GEN3_QPLL_LPF  = 16'b0_1101_00000000000;  
+     
+     
+     
+    //---------- DRP Data ----------------------------------       
+    wire        [15:0]  data_qpll_fbdiv;  
+    wire        [15:0]  data_qpll_cfg;  
+    wire        [15:0]  data_qpll_lpf;  
+    wire        [15:0]  data_qpll_coarse_freq_ovrd;               
+    wire        [15:0]  data_qpll_coarse_freq_ovrd_en; 
+    wire        [15:0]  data_qpll_lock_cfg;      
+           
+    //---------- FSM ---------------------------------------  
+    localparam          FSM_IDLE      = 9'b000000001;  
+    localparam          FSM_LOAD      = 9'b000000010;                           
+    localparam          FSM_READ      = 9'b000000100;
+    localparam          FSM_RRDY      = 9'b000001000;
+    localparam          FSM_WRITE     = 9'b000010000;
+    localparam          FSM_WRDY      = 9'b000100000;    
+    localparam          FSM_DONE      = 9'b001000000; 
+    localparam          FSM_QPLLRESET = 9'b010000000; 
+    localparam          FSM_QPLLLOCK  = 9'b100000000;
+
+
+    
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        begin
+        //---------- 1st Stage FF --------------------------
+        ovrd_reg1     <=  1'd0;
+        gen3_reg1     <=  1'd0;
+        qplllock_reg1 <=  1'd0;
+        start_reg1    <=  1'd0;
+        do_reg1       <= 16'd0;
+        rdy_reg1      <=  1'd0;
+        //---------- 2nd Stage FF --------------------------
+        ovrd_reg2     <=  1'd0;
+        gen3_reg2     <=  1'd0;
+        qplllock_reg2 <=  1'd0;
+        start_reg2    <=  1'd0;
+        do_reg2       <= 16'd0;
+        rdy_reg2      <=  1'd0;
+        end
+        
+    else
+        begin
+        //---------- 1st Stage FF --------------------------
+        ovrd_reg1     <= DRP_OVRD;
+        gen3_reg1     <= DRP_GEN3;
+        qplllock_reg1 <= DRP_QPLLLOCK;
+        start_reg1    <= DRP_START;
+        do_reg1       <= DRP_DO;
+        rdy_reg1      <= DRP_RDY;
+        //---------- 2nd Stage FF --------------------------
+        ovrd_reg2     <= ovrd_reg1;
+        gen3_reg2     <= gen3_reg1;
+        qplllock_reg2 <= qplllock_reg1;
+        start_reg2    <= start_reg1;
+        do_reg2       <= do_reg1;
+        rdy_reg2      <= rdy_reg1;
+        end
+    
+end  
+
+
+
+//---------- Select DRP Data ---------------------------------------------------
+assign data_qpll_fbdiv               = (gen3_reg2) ? GEN3_QPLL_FBDIV : GEN12_QPLL_FBDIV;
+assign data_qpll_cfg                 = (gen3_reg2) ? GEN3_QPLL_CFG   : GEN12_QPLL_CFG;
+assign data_qpll_lpf                 = (gen3_reg2) ? GEN3_QPLL_LPF   : GEN12_QPLL_LPF;
+assign data_qpll_coarse_freq_ovrd    =  NORM_QPLL_COARSE_FREQ_OVRD;
+assign data_qpll_coarse_freq_ovrd_en = (ovrd_reg2) ? OVRD_QPLL_COARSE_FREQ_OVRD_EN : NORM_QPLL_COARSE_FREQ_OVRD_EN;
+assign data_qpll_lock_cfg            = (ovrd_reg2) ? OVRD_QPLL_LOCK_CFG            : NORM_QPLL_LOCK_CFG;
+
+
+//---------- Load Counter ------------------------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        load_cnt <= 2'd0;
+    else
+    
+        //---------- Increment Load Counter ----------------
+        if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
+            load_cnt <= load_cnt + 2'd1;
+            
+        //---------- Hold Load Counter ---------------------
+        else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
+            load_cnt <= load_cnt;
+            
+        //---------- Reset Load Counter --------------------
+        else
+            load_cnt <= 2'd0;
+        
+end 
+
+
+
+//---------- Update DRP Address and Data ---------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        begin
+        addr    <=  8'd0;
+        di      <= 16'd0;
+        crscode <=  6'd0;
+        end
+    else
+        begin
+        
+        case (index)
+
+        //--------------------------------------------------    
+        3'd0 :
+            begin        
+            addr    <= ADDR_QPLL_FBDIV;
+            di      <= (do_reg2 & MASK_QPLL_FBDIV) | (mode ? data_qpll_fbdiv : QPLL_FBDIV);
+            crscode <= crscode;
+            end   
+                
+        //--------------------------------------------------    
+        3'd1 :
+            begin       
+            addr    <= ADDR_QPLL_CFG;
+            if (PCIE_GT_DEVICE == "GTX") 
+                di <= (do_reg2 & MASK_QPLL_CFG) | data_qpll_cfg;
+            else
+                di <= (do_reg2 & 16'hFFFF) | data_qpll_cfg;
+            crscode <= crscode;
+            end       
+            
+        //--------------------------------------------------    
+        3'd2 :
+            begin        
+            addr    <= ADDR_QPLL_LPF;
+            if (PCIE_GT_DEVICE == "GTX") 
+                di <= (do_reg2 & MASK_QPLL_LPF) | data_qpll_lpf;
+            else
+                di <= (do_reg2 & 16'hFFFF) | data_qpll_lpf;
+            crscode <= crscode;
+            end     
+                
+        //--------------------------------------------------
+        3'd3 :
+            begin        
+            addr <= ADDR_CRSCODE;
+            di   <= do_reg2;
+            
+            //---------- Latch CRS Code --------------------
+            if (ovrd_reg2)
+                crscode <= do_reg2[6:1];                 
+            else
+                crscode <= crscode;   
+            end
+           
+        //--------------------------------------------------    
+        3'd4 :
+            begin        
+            addr    <= ADDR_QPLL_COARSE_FREQ_OVRD;
+            di      <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD) | {(crscode - 6'd1), data_qpll_coarse_freq_ovrd[9:0]};
+            crscode <= crscode;
+            end    
+            
+        //--------------------------------------------------    
+        3'd5 :
+            begin        
+            addr    <= ADDR_QPLL_COARSE_FREQ_OVRD_EN;
+            di      <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD_EN) | data_qpll_coarse_freq_ovrd_en;
+            crscode <= crscode;
+            end    
+            
+        //--------------------------------------------------    
+        3'd6 :
+            begin        
+            addr    <= ADDR_QPLL_LOCK_CFG;
+            di      <= (do_reg2 & MASK_QPLL_LOCK_CFG) | data_qpll_lock_cfg;
+            crscode <= crscode;
+            end       
+            
+        //--------------------------------------------------
+        default : 
+            begin
+            addr    <=  8'd0;
+            di      <= 16'd0;
+            crscode <=  6'd0;
+            end
+            
+        endcase
+        
+        end
+        
+end  
+
+
+
+//---------- QPLL DRP FSM ------------------------------------------------------
+always @ (posedge DRP_CLK)
+begin
+
+    if (!DRP_RST_N)
+        begin
+        fsm   <= FSM_IDLE;
+        index <= 3'd0;
+        mode  <= 1'd0;
+        done  <= 1'd0;
+        end
+    else
+        begin
+        
+        case (fsm)
+
+        //---------- Idle State ----------------------------
+        FSM_IDLE :  
+          
+            begin
+            if (start_reg2)
+                begin
+                fsm   <= FSM_LOAD;
+                index <= 3'd0;
+                mode  <= 1'd0;
+                done  <= 1'd0;
+                end
+            else if ((gen3_reg2 != gen3_reg1) && (PCIE_PLL_SEL == "QPLL"))
+                begin
+                fsm   <= FSM_LOAD;
+                index <= 3'd0;
+                mode  <= 1'd1;
+                done  <= 1'd0;
+                end
+            else
+                begin
+                fsm   <= FSM_IDLE;
+                index <= 3'd0;
+                mode  <= 1'd0;
+                done  <= 1'd1;
+                end
+            end    
+            
+        //---------- Load DRP Address  ---------------------
+        FSM_LOAD :
+        
+            begin
+            fsm   <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
+            index <= index;
+            mode  <= mode;
+            done  <= 1'd0;
+            end  
+            
+        //---------- Read DRP ------------------------------
+        FSM_READ :
+        
+            begin
+            fsm   <= FSM_RRDY;
+            index <= index;
+            mode  <= mode;
+            done  <= 1'd0;
+            end
+            
+        //---------- Read DRP Ready ------------------------
+        FSM_RRDY :    
+        
+            begin
+            fsm   <= (rdy_reg2 ? FSM_WRITE : FSM_RRDY);
+            index <= index;
+            mode  <= mode;
+            done  <= 1'd0;
+            end  
+            
+        //---------- Write DRP -----------------------------
+        FSM_WRITE :    
+        
+            begin
+            fsm   <= FSM_WRDY;
+            index <= index;
+            mode  <= mode;
+            done  <= 1'd0;
+            end       
+            
+        //---------- Write DRP Ready -----------------------
+        FSM_WRDY :    
+        
+            begin
+            fsm   <= (rdy_reg2 ? FSM_DONE : FSM_WRDY);
+            index <= index;
+            mode  <= mode;
+            done  <= 1'd0;
+            end        
+             
+        //---------- DRP Done ------------------------------
+        FSM_DONE :
+        
+            begin
+            if ((index == INDEX_MAX) || (mode && (index == 3'd2)))
+                begin
+                fsm   <= mode ? FSM_QPLLRESET : FSM_IDLE;
+                index <= 3'd0;
+                mode  <= mode;
+                done  <= 1'd0;
+                end
+            else       
+                begin
+                fsm   <= FSM_LOAD;
+                index <= index + 3'd1;
+                mode  <= mode;
+                done  <= 1'd0;
+                end
+            end     
+        
+        //---------- QPLL Reset ----------------------------      
+        FSM_QPLLRESET :
+        
+            begin
+            fsm   <= !qplllock_reg2 ? FSM_QPLLLOCK : FSM_QPLLRESET;
+            index <= 3'd0;
+            mode  <= mode;
+            done  <= 1'd0;
+            end
+            
+        //---------- QPLL Reset ----------------------------      
+        FSM_QPLLLOCK :
+        
+            begin
+            fsm   <= qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK;
+            index <= 3'd0;
+            mode  <= mode;
+            done  <= 1'd0;
+            end
+              
+        //---------- Default State -------------------------
+        default :
+        
+            begin      
+            fsm   <= FSM_IDLE;
+            index <= 3'd0;
+            mode  <= 1'd0;
+            done  <= 1'd0;
+            end
+            
+        endcase
+        
+        end
+        
+end 
+
+
+
+//---------- QPLL DRP Output ---------------------------------------------------
+assign DRP_ADDR      = addr;
+assign DRP_EN        = (fsm == FSM_READ) || (fsm == FSM_WRITE);
+assign DRP_DI        = di;
+assign DRP_WE        = (fsm == FSM_WRITE); // || (fsm == FSM_WRDY);
+assign DRP_DONE      = done;
+assign DRP_QPLLRESET = (fsm == FSM_QPLLRESET);
+assign DRP_CRSCODE   = crscode;
+assign DRP_FSM       = fsm;
+
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_qpll_reset.v

@@ -0,0 +1,370 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_qpll_reset.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  qpll_reset.v
+//  Description  :  QPLL Reset Module for 7 Series Transceiver
+//  Version      :  11.4
+//------------------------------------------------------------------------------
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- QPLL Reset Module --------------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_qpll_reset #
+(
+
+    //---------- Global ------------------------------------
+    parameter PCIE_PLL_SEL       = "CPLL",                  // PCIe PLL select for Gen1/Gen2 only
+    parameter PCIE_POWER_SAVING  = "TRUE",                  // PCIe power saving
+    parameter PCIE_LANE          = 1,                       // PCIe number of lanes
+    parameter BYPASS_COARSE_OVRD = 1                        // Bypass coarse frequency override
+
+)
+
+(
+
+    //---------- Input -------------------------------------
+    input                           QRST_CLK,
+    input                           QRST_RST_N,
+    input                           QRST_MMCM_LOCK,
+    input       [PCIE_LANE-1:0]     QRST_CPLLLOCK,
+    input       [(PCIE_LANE-1)>>2:0]QRST_DRP_DONE,
+    input       [(PCIE_LANE-1)>>2:0]QRST_QPLLLOCK,
+    input       [ 1:0]              QRST_RATE,
+    input       [PCIE_LANE-1:0]     QRST_QPLLRESET_IN,
+    input       [PCIE_LANE-1:0]     QRST_QPLLPD_IN,
+    
+    //---------- Output ------------------------------------                     
+    output                          QRST_OVRD,
+    output                          QRST_DRP_START,
+    output                          QRST_QPLLRESET_OUT,
+    output                          QRST_QPLLPD_OUT,
+    output                          QRST_IDLE,
+    output      [3:0]               QRST_FSM
+
+);
+
+    //---------- Input Register ----------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             mmcm_lock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     cplllock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [(PCIE_LANE-1)>>2:0]drp_done_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [(PCIE_LANE-1)>>2:0]qplllock_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 1:0]              rate_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     qpllreset_in_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     qpllpd_in_reg1;
+
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                             mmcm_lock_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     cplllock_reg2;  
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [(PCIE_LANE-1)>>2:0]drp_done_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [(PCIE_LANE-1)>>2:0]qplllock_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 1:0]              rate_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     qpllreset_in_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0]     qpllpd_in_reg2;
+    
+    //---------- Output Register  --------------------------
+    reg                             ovrd              =  1'd0;
+    reg                             qpllreset         =  1'd1;
+    reg                             qpllpd            =  1'd0;
+    reg         [3:0]               fsm               =  2;                 
+   
+    //---------- FSM ---------------------------------------                                         
+    localparam                      FSM_IDLE          = 1;//12'b000000000001; 
+    localparam                      FSM_WAIT_LOCK     = 2;//12'b000000000010;
+    localparam                      FSM_MMCM_LOCK     = 3;//12'b000000000100;   
+    localparam                      FSM_DRP_START_NOM = 4;//12'b000000001000;
+    localparam                      FSM_DRP_DONE_NOM  = 5;//12'b000000010000;
+    localparam                      FSM_QPLLLOCK      = 6;//12'b000000100000;
+    localparam                      FSM_DRP_START_OPT = 7;//12'b000001000000;                            
+    localparam                      FSM_DRP_DONE_OPT  = 8;//12'b000010000000;
+    localparam                      FSM_QPLL_RESET    = 9;//12'b000100000000;                                                         
+    localparam                      FSM_QPLLLOCK2     = 10;//12'b001000000000;
+    localparam                      FSM_QPLL_PDRESET  = 11;//12'b010000000000;
+    localparam                      FSM_QPLL_PD       = 12;//12'b100000000000;                                         
+ 
+ 
+    
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge QRST_CLK)
+begin
+
+    if (!QRST_RST_N)
+        begin    
+        //---------- 1st Stage FF --------------------------
+        mmcm_lock_reg1    <=  1'd0;
+        cplllock_reg1     <= {PCIE_LANE{1'd1}}; 
+        drp_done_reg1     <= {(((PCIE_LANE-1)>>2)+1){1'd0}};     
+        qplllock_reg1     <= {(((PCIE_LANE-1)>>2)+1){1'd0}}; 
+        rate_reg1         <=  2'd0; 
+        qpllreset_in_reg1 <= {PCIE_LANE{1'd1}}; 
+        qpllpd_in_reg1    <= {PCIE_LANE{1'd0}}; 
+        //---------- 2nd Stage FF --------------------------
+        mmcm_lock_reg2    <=  1'd0;
+        cplllock_reg2     <= {PCIE_LANE{1'd1}};
+        drp_done_reg2     <= {(((PCIE_LANE-1)>>2)+1){1'd0}}; 
+        qplllock_reg2     <= {(((PCIE_LANE-1)>>2)+1){1'd0}}; 
+        rate_reg2         <=  2'd0;
+        qpllreset_in_reg2 <= {PCIE_LANE{1'd1}}; 
+        qpllpd_in_reg2    <= {PCIE_LANE{1'd0}};  
+        end
+    else
+        begin  
+        //---------- 1st Stage FF --------------------------
+        mmcm_lock_reg1    <= QRST_MMCM_LOCK;   
+        cplllock_reg1     <= QRST_CPLLLOCK; 
+        drp_done_reg1     <= QRST_DRP_DONE; 
+        qplllock_reg1     <= QRST_QPLLLOCK;
+        rate_reg1         <= QRST_RATE; 
+        qpllreset_in_reg1 <= QRST_QPLLRESET_IN;
+        qpllpd_in_reg1    <= QRST_QPLLPD_IN;
+        //---------- 2nd Stage FF --------------------------
+        mmcm_lock_reg2    <= mmcm_lock_reg1;
+        cplllock_reg2     <= cplllock_reg1;
+        drp_done_reg2     <= drp_done_reg1; 
+        qplllock_reg2     <= qplllock_reg1;
+        rate_reg2         <= rate_reg1;
+        qpllreset_in_reg2 <= qpllreset_in_reg1;
+        qpllpd_in_reg2    <= qpllpd_in_reg1;
+        end
+        
+end    
+
+
+
+//---------- QPLL Reset FSM ----------------------------------------------------
+always @ (posedge QRST_CLK)
+begin
+
+    if (!QRST_RST_N)
+        begin
+        fsm       <= FSM_WAIT_LOCK;
+        ovrd      <= 1'd0;
+        qpllreset <= 1'd1;
+        qpllpd    <= 1'd0;
+        end
+    else
+        begin
+        
+        case (fsm)
+            
+        //---------- Idle State ----------------------------
+        FSM_IDLE :
+        
+            begin
+            if (!QRST_RST_N)
+                begin
+                fsm       <= FSM_WAIT_LOCK;
+                ovrd      <= 1'd0;
+                qpllreset <= 1'd1;
+                qpllpd    <= 1'd0;
+                end
+            else
+                begin
+                fsm       <= FSM_IDLE;
+                ovrd      <= ovrd;
+                qpllreset <= &qpllreset_in_reg2;
+                qpllpd    <= &qpllpd_in_reg2;
+                end
+            end  
+            
+        //---------- Wait for CPLL and QPLL to Lose Lock ---
+        FSM_WAIT_LOCK :
+        
+            begin
+            fsm       <= ((&(~cplllock_reg2)) && (&(~qplllock_reg2)) ? FSM_MMCM_LOCK : FSM_WAIT_LOCK);
+            ovrd      <= ovrd;
+            qpllreset <= qpllreset;
+            qpllpd    <= qpllpd;
+            end      
+            
+        //---------- Wait for MMCM and CPLL Lock -----------
+        FSM_MMCM_LOCK :
+        
+            begin
+            fsm       <= ((mmcm_lock_reg2 && (&cplllock_reg2)) ? FSM_DRP_START_NOM : FSM_MMCM_LOCK);
+            ovrd      <= ovrd;
+            qpllreset <= qpllreset;
+            qpllpd    <= qpllpd;
+            end      
+            
+        //---------- Start QPLL DRP for Normal QPLL Lock Mode 
+        FSM_DRP_START_NOM:
+        
+            begin
+            fsm       <= (&(~drp_done_reg2) ? FSM_DRP_DONE_NOM : FSM_DRP_START_NOM);
+            ovrd      <= ovrd;
+            qpllreset <= qpllreset;
+            qpllpd    <= qpllpd;
+            end
+
+        //---------- Wait for QPLL DRP Done ----------------
+        FSM_DRP_DONE_NOM :
+        
+            begin
+            fsm       <= (&drp_done_reg2 ? FSM_QPLLLOCK : FSM_DRP_DONE_NOM);
+            ovrd      <= ovrd;
+            qpllreset <= qpllreset;
+            qpllpd    <= qpllpd;
+            end 
+            
+        //---------- Wait for QPLL Lock --------------------
+        FSM_QPLLLOCK :
+        
+            begin
+            fsm       <= (&qplllock_reg2 ? ((BYPASS_COARSE_OVRD == 1) ? FSM_QPLL_PDRESET : FSM_DRP_START_OPT) : FSM_QPLLLOCK);
+            ovrd      <= ovrd;
+            qpllreset <= 1'd0;
+            qpllpd    <= qpllpd;
+            end
+            
+        //---------- Start QPLL DRP for Optimized QPLL Lock Mode 
+        FSM_DRP_START_OPT:
+        
+            begin
+            fsm       <= (&(~drp_done_reg2) ? FSM_DRP_DONE_OPT : FSM_DRP_START_OPT);
+            ovrd      <= 1'd1;
+            qpllreset <= qpllreset;
+            qpllpd    <= qpllpd;
+            end
+
+        //---------- Wait for QPLL DRP Done ----------------
+        FSM_DRP_DONE_OPT :
+        
+            begin
+            if (&drp_done_reg2)
+                begin
+                fsm       <= ((PCIE_PLL_SEL == "QPLL") ? FSM_QPLL_RESET : FSM_QPLL_PDRESET);
+                ovrd      <= ovrd;
+                qpllreset <= (PCIE_PLL_SEL == "QPLL");
+                qpllpd    <= qpllpd;
+                end
+            else
+                begin
+                fsm       <= FSM_DRP_DONE_OPT;
+                ovrd      <= ovrd;
+                qpllreset <= qpllreset;
+                qpllpd    <= qpllpd;
+                end
+            end 
+            
+        //---------- Reset QPLL ----------------------------
+        FSM_QPLL_RESET :
+            
+            begin
+            fsm       <= (&(~qplllock_reg2) ? FSM_QPLLLOCK2 : FSM_QPLL_RESET);  
+            ovrd      <= ovrd;
+            qpllreset <= 1'd1;
+            qpllpd    <= 1'd0;
+            end     
+            
+        //---------- Wait for QPLL Lock --------------------
+        FSM_QPLLLOCK2 :
+        
+            begin
+            fsm       <= (&qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK2);
+            ovrd      <= ovrd;
+            qpllreset <= 1'd0;
+            qpllpd    <= 1'd0;
+            end
+            
+        //---------- Hold QPLL in Reset --------------------
+        FSM_QPLL_PDRESET :
+        
+            begin
+            fsm       <= FSM_QPLL_PD;
+            ovrd      <= ovrd;
+            qpllreset <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0; 
+            qpllpd    <= qpllpd;
+            end
+            
+        //---------- Power-down QPLL ----------------------- 
+        FSM_QPLL_PD :
+        
+            begin
+            fsm       <= FSM_IDLE;
+            ovrd      <= ovrd;
+            qpllreset <= qpllreset;
+            qpllpd    <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0; 
+            end 
+                
+        //---------- Default State -------------------------
+        default :
+        
+            begin
+            fsm       <= FSM_WAIT_LOCK;
+            ovrd      <= 1'd0;
+            qpllreset <= 1'd0;
+            qpllpd    <= 1'd0;
+            end
+
+        endcase
+        
+        end
+        
+end
+
+
+
+//---------- QPLL Lock Output --------------------------------------------------
+assign QRST_OVRD          = ovrd;
+assign QRST_DRP_START     = (fsm == FSM_DRP_START_NOM) || (fsm == FSM_DRP_START_OPT); 
+assign QRST_QPLLRESET_OUT = qpllreset;
+assign QRST_QPLLPD_OUT    = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);  
+assign QRST_IDLE          = (fsm == FSM_IDLE);
+assign QRST_FSM           = fsm;                   
+
+
+
+endmodule

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_qpll_wrapper.v

@@ -0,0 +1,439 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_qpll_wrapper.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  qpll_wrapper.v
+//  Description  :  QPLL Wrapper Module for 7 Series Transceiver
+//  Version      :  18.1
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- QPLL Wrapper ----------------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_qpll_wrapper #
+(
+    
+    parameter PCIE_SIM_MODE    = "FALSE",                   // PCIe sim mode
+    parameter PCIE_GT_DEVICE   = "GTX",                     // PCIe GT device
+    parameter PCIE_USE_MODE    = "3.0",                     // PCIe use mode
+    parameter PCIE_PLL_SEL     = "CPLL",                    // PCIe PLL select for Gen1/Gen2 only
+    parameter PCIE_REFCLK_FREQ = 0                          // PCIe reference clock frequency
+ 
+)
+
+(    
+    
+    //---------- QPLL Clock Ports --------------------------
+    input               QPLL_CPLLPDREFCLK,
+    input               QPLL_GTGREFCLK,
+    input               QPLL_QPLLLOCKDETCLK,
+    
+    output              QPLL_QPLLOUTCLK,
+    output              QPLL_QPLLOUTREFCLK,
+    output              QPLL_QPLLLOCK,
+    
+    //---------- QPLL Reset Ports --------------------------
+    input               QPLL_QPLLPD,
+    input               QPLL_QPLLRESET,
+
+    //---------- QPLL DRP Ports ----------------------------
+    input               QPLL_DRPCLK,
+    input       [ 7:0]  QPLL_DRPADDR,
+    input               QPLL_DRPEN,
+    input       [15:0]  QPLL_DRPDI,
+    input               QPLL_DRPWE,
+    
+    output      [15:0]  QPLL_DRPDO,
+    output              QPLL_DRPRDY
+    
+);
+
+
+
+    //---------- Select QPLL Feedback Divider --------------
+    //  N = 100 for 100 MHz ref clk and 10Gb/s line rate
+    //  N =  80 for 125 MHz ref clk and 10Gb/s line rate
+    //  N =  40 for 250 MHz ref clk and 10Gb/s line rate
+    //------------------------------------------------------
+    //  N =  80 for 100 MHz ref clk and  8Gb/s line rate
+    //  N =  64 for 125 MHz ref clk and  8Gb/s line rate
+    //  N =  32 for 250 MHz ref clk and  8Gb/s line rate
+    //------------------------------------------------------
+    localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 10'b0010000000 : 
+                            (PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 10'b0100100000 : 
+                            (PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 10'b0101110000 : 
+                            (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 10'b0001100000 : 
+                            (PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 10'b0011100000 : 10'b0100100000;
+    
+    //---------- Select GTP QPLL Feedback Divider ----------                     
+    localparam GTP_QPLL_FBDIV  = (PCIE_REFCLK_FREQ == 2) ? 3'd2 :
+                                 (PCIE_REFCLK_FREQ == 1) ? 3'd4 : 3'd5;
+
+    //---------- Select BIAS_CFG ---------------------------
+    localparam BIAS_CFG = ((PCIE_USE_MODE == "1.0") && (PCIE_PLL_SEL == "CPLL")) ? 64'h0000042000001000 : 64'h0000040000001000;
+
+
+    wire cpllpd;        
+    wire cpllrst;       
+
+//---------- Select GTX or GTH or GTP ------------------------------------------
+//  Notes  :  Attributes that are commented out uses the GT default settings
+//------------------------------------------------------------------------------
+generate if (PCIE_GT_DEVICE == "GTP") 
+
+    //---------- GTP Common ----------------------------------------------------
+    begin : gtp_common
+
+    //---------- GTP Common Module ---------------------------------------------
+    GTPE2_COMMON #
+    (
+       
+        //---------- Simulation Attributes -------------------------------------                                                     
+        .SIM_PLL0REFCLK_SEL             (3'b001),                               //                                                   
+        .SIM_PLL1REFCLK_SEL             (3'b001),                               //                                                   
+        .SIM_RESET_SPEEDUP              (PCIE_SIM_MODE),                        //                                                   
+        .SIM_VERSION                    (PCIE_USE_MODE),                        //                                                   
+                                                                                                                                     
+        //---------- Clock Attributes ------------------------------------------                                                     
+        .PLL0_CFG                       (27'h01F024C),                          // Optimized for IES                                                  
+        .PLL1_CFG                       (27'h01F024C),                          // Optimized for IES                                                  
+        .PLL_CLKOUT_CFG                 (8'd0),                                 // Optimized for IES                                                   
+        .PLL0_DMON_CFG                  (1'b0),                                 // Optimized for IES                                                  
+        .PLL1_DMON_CFG                  (1'b0),                                 // Optimized for IES                                      
+        .PLL0_FBDIV                     (GTP_QPLL_FBDIV),                       // Optimized for IES                                                  
+        .PLL1_FBDIV                     (GTP_QPLL_FBDIV),                       // Optimized for IES                                                   
+        .PLL0_FBDIV_45                  (5),                                    // Optimized for IES                                                  
+        .PLL1_FBDIV_45                  (5),                                    // Optimized for IES                                                  
+        .PLL0_INIT_CFG                  (24'h00001E),                           // Optimized for IES                                                  
+        .PLL1_INIT_CFG                  (24'h00001E),                           // Optimized for IES                                                   
+        .PLL0_LOCK_CFG                  ( 9'h1E8),                              // Optimized for IES    
+        .PLL1_LOCK_CFG                  ( 9'h1E8),                              // Optimized for IES                                                                                                                   
+        .PLL0_REFCLK_DIV                (1),                                    // Optimized for IES                                                  
+        .PLL1_REFCLK_DIV                (1),                                    // Optimized for IES                                                  
+                                                                                                                                     
+        //---------- MISC ------------------------------------------------------                                                     
+        .BIAS_CFG                       (64'h0000000000050001),                 // Optimized for GES                                                 
+      //.COMMON_CFG                     (32'd0),                                //                                                                                                   
+        .RSVD_ATTR0                     (16'd0),                                //                                                   
+        .RSVD_ATTR1                     (16'd0)                                 //                                                   
+    
+    )
+    gtpe2_common_i 
+    (
+           
+        //---------- Clock -----------------------------------------------------                         
+        .GTGREFCLK0                     ( 1'd0),                                //                       
+        .GTGREFCLK1                     ( 1'd0),                                //                       
+        .GTREFCLK0                      (QPLL_GTGREFCLK),                       //                       
+        .GTREFCLK1                      ( 1'd0),                                //                       
+        .GTEASTREFCLK0                  ( 1'd0),                                //                       
+        .GTEASTREFCLK1                  ( 1'd0),                                //                       
+        .GTWESTREFCLK0                  ( 1'd0),                                //                       
+        .GTWESTREFCLK1                  ( 1'd0),                                //                       
+        .PLL0LOCKDETCLK                 (QPLL_QPLLLOCKDETCLK),                  //                       
+        .PLL1LOCKDETCLK                 (QPLL_QPLLLOCKDETCLK),                  //                       
+        .PLL0LOCKEN                     ( 1'd1),                                //                       
+        .PLL1LOCKEN                     ( 1'd1),                                //                       
+        .PLL0REFCLKSEL                  ( 3'd1),                                // Optimized for IES                      
+        .PLL1REFCLKSEL                  ( 3'd1),                                // Optimized for IES                      
+        .PLLRSVD1                       (16'd0),                                // Optimized for IES                    
+        .PLLRSVD2                       ( 5'd0),                                // Optimized for IES                  
+        
+        .PLL0OUTCLK                     (QPLL_QPLLOUTCLK),                      //                       
+        .PLL1OUTCLK                     (),                                     //                       
+        .PLL0OUTREFCLK                  (QPLL_QPLLOUTREFCLK),                   //                       
+        .PLL1OUTREFCLK                  (),                                     //                       
+        .PLL0LOCK                       (QPLL_QPLLLOCK),                        //                       
+        .PLL1LOCK                       (),                                     //                       
+        .PLL0FBCLKLOST                  (),                                     //                       
+        .PLL1FBCLKLOST                  (),                                     //                       
+        .PLL0REFCLKLOST                 (),                                     //                       
+        .PLL1REFCLKLOST                 (),                                     //                       
+        .DMONITOROUT                    (),                                     // 
+                                                                                                         
+        //---------- Reset -----------------------------------------------------                         
+        .PLL0PD                         (cpllpd | QPLL_QPLLPD),                 //                       
+        .PLL1PD                         ( 1'd1),                                //                       
+        .PLL0RESET                      (cpllrst | QPLL_QPLLRESET),             //                       
+        .PLL1RESET                      ( 1'd1),                                //                       
+                                                                                                   
+        //---------- DRP -------------------------------------------------------                         
+        .DRPCLK                         (QPLL_DRPCLK),                          //                       
+        .DRPADDR                        (QPLL_DRPADDR),                         //                       
+        .DRPEN                          (QPLL_DRPEN),                           //                       
+        .DRPDI                          (QPLL_DRPDI),                           //                       
+        .DRPWE                          (QPLL_DRPWE),                           //                       
+                                                                                                         
+        .DRPDO                          (QPLL_DRPDO),                           //                       
+        .DRPRDY                         (QPLL_DRPRDY),                          //                       
+                                                                                                         
+        //---------- Band Gap --------------------------------------------------                         
+        .BGBYPASSB                      ( 1'd1),                                // Optimized for IES                      
+        .BGMONITORENB                   ( 1'd1),                                // Optimized for IES                      
+        .BGPDB                          ( 1'd1),                                // Optimized for IES
+        .BGRCALOVRD                     ( 5'd31),                               // Optimized for IES
+        .BGRCALOVRDENB                  ( 1'd1),                                // Optimized for IES
+        
+        //---------- MISC ------------------------------------------------------
+        .PMARSVD                        ( 8'd0),                                //
+        .RCALENB                        ( 1'd1),                                // Optimized for IES
+                                                                               
+        .REFCLKOUTMONITOR0              (),                                     //
+        .REFCLKOUTMONITOR1              (),                                     //
+        .PMARSVDOUT                     ()                                      //  
+    
+    );
+   
+    end
+
+else if (PCIE_GT_DEVICE == "GTH") 
+    
+    //---------- GTH Common ----------------------------------------------------
+    begin : gth_common
+    
+    //---------- GTX Common Module ---------------------------------------------
+    GTHE2_COMMON #
+    (
+       
+        //---------- Simulation Attributes -------------------------------------
+        .SIM_QPLLREFCLK_SEL             (3'b001),                               //
+        .SIM_RESET_SPEEDUP              (PCIE_SIM_MODE),                        //
+        .SIM_VERSION                    ("2.0"),                                // 
+        
+        //---------- Clock Attributes ------------------------------------------
+        .QPLL_CFG                       (27'h04801C7),                          // QPLL for Gen3, optimized for GES
+        .QPLL_CLKOUT_CFG                ( 4'b1111),                             // Optimized for GES
+        .QPLL_COARSE_FREQ_OVRD          ( 6'b010000),                           // 
+        .QPLL_COARSE_FREQ_OVRD_EN       ( 1'd0),                                // 
+        .QPLL_CP                        (10'h0FF),                              // * Optimized for IES and PCIe PLL BW 
+        .QPLL_CP_MONITOR_EN             ( 1'd0),                                //
+        .QPLL_DMONITOR_SEL              ( 1'd0),                                //
+        .QPLL_FBDIV                     (QPLL_FBDIV),                           // 
+        .QPLL_FBDIV_MONITOR_EN          ( 1'd0),                                //
+        .QPLL_FBDIV_RATIO               ( 1'd1),                                // Optimized
+        .QPLL_INIT_CFG	                (24'h000006),                           // 
+        .QPLL_LOCK_CFG                  (16'h05E8),                             // Optimized for IES
+        .QPLL_LPF                       ( 4'hD),                                // Optimized for IES, [1:0] = 2'b00 (13.3 KOhm), [1:0] = 2'b01 (57.0 KOhm)
+        .QPLL_REFCLK_DIV	              ( 1),                                   // 
+        .QPLL_RP_COMP                   ( 1'd0),                                // GTH new
+        .QPLL_VTRL_RESET                ( 2'd0),                                // GTH new
+    
+        //---------- MISC ------------------------------------------------------
+        .BIAS_CFG	                      (64'h0000040000001050),                 // Optimized for GES
+        .COMMON_CFG	                    (32'd0),                                // 
+        .RCAL_CFG                       ( 2'b00),                               // GTH new
+        .RSVD_ATTR0                     (16'd0),                                // GTH
+        .RSVD_ATTR1                     (16'd0)                                 // GTH    
+    )
+    gthe2_common_i 
+    (
+           
+        //---------- Clock -----------------------------------------------------
+        .GTGREFCLK                      ( 1'd0),                                //    
+        .GTREFCLK0                      (QPLL_GTGREFCLK),                       //
+        .GTREFCLK1                      ( 1'd0),                                //
+        .GTNORTHREFCLK0                 ( 1'd0),                                //
+        .GTNORTHREFCLK1                 ( 1'd0),                                //
+        .GTSOUTHREFCLK0                 ( 1'd0),                                //
+        .GTSOUTHREFCLK1                 ( 1'd0),                                //
+        .QPLLLOCKDETCLK                 (QPLL_QPLLLOCKDETCLK),                  //
+        .QPLLLOCKEN                     ( 1'd1),                                //
+        .QPLLREFCLKSEL                  ( 3'd1),                                //
+        .QPLLRSVD1                      (16'd0),                                //
+        .QPLLRSVD2                      ( 5'b11111),                            //
+                                                                               
+        .QPLLOUTCLK                     (QPLL_QPLLOUTCLK),                      //
+        .QPLLOUTREFCLK                  (QPLL_QPLLOUTREFCLK),                   //
+        .QPLLLOCK                       (QPLL_QPLLLOCK),                        //
+        .QPLLFBCLKLOST                  (),                                     //
+        .QPLLREFCLKLOST                 (),                                     //
+        .QPLLDMONITOR                   (),                                     //
+        
+        //---------- Reset -----------------------------------------------------
+        .QPLLPD                         (QPLL_QPLLPD),                          // 
+        .QPLLRESET                      (QPLL_QPLLRESET),                       //
+        .QPLLOUTRESET                   ( 1'd0),                                //
+        
+        //---------- DRP -------------------------------------------------------
+        .DRPCLK                         (QPLL_DRPCLK),                          //
+        .DRPADDR                        (QPLL_DRPADDR),                         //
+        .DRPEN                          (QPLL_DRPEN),                           //
+        .DRPDI                          (QPLL_DRPDI),                           //
+        .DRPWE                          (QPLL_DRPWE),                           //
+                                                                              
+        .DRPDO                          (QPLL_DRPDO),                           //
+        .DRPRDY                         (QPLL_DRPRDY),                          //
+                
+        //---------- Band Gap --------------------------------------------------    
+        .BGBYPASSB                      ( 1'd1),                                // Optimized for IES
+        .BGMONITORENB                   ( 1'd1),                                // Optimized for IES
+        .BGPDB                          ( 1'd1),                                // Optimized for IES
+        .BGRCALOVRD                     ( 5'd31),                               // Optimized for IES
+        .BGRCALOVRDENB                  ( 1'd1),                                // GTH, Optimized for IES
+        
+        //---------- MISC ------------------------------------------------------
+        .PMARSVD                        ( 8'd0),                                //
+        .RCALENB                        ( 1'd1),                                // Optimized for IES
+                                                                              
+        .REFCLKOUTMONITOR               (),                                     //
+        .PMARSVDOUT                     ()                                      // GTH
+    
+    );
+
+    end    
+    
+else
+
+    //---------- GTX Common ----------------------------------------------------
+    begin : gtx_common
+
+    //---------- GTX Common Module ---------------------------------------------
+    GTXE2_COMMON #
+    (
+       
+        //---------- Simulation Attributes ------------------------------------- 
+        .SIM_QPLLREFCLK_SEL             ( 3'b001),                              //
+        .SIM_RESET_SPEEDUP              (PCIE_SIM_MODE),                        //
+        .SIM_VERSION                    (PCIE_USE_MODE),                        // 
+        
+        //---------- Clock Attributes ------------------------------------------
+        .QPLL_CFG                       (27'h06801C1),                          // QPLL for Gen3, Optimized for silicon, 
+      //.QPLL_CLKOUT_CFG                ( 4'd0),                                //
+        .QPLL_COARSE_FREQ_OVRD          ( 6'b010000),                           // 
+        .QPLL_COARSE_FREQ_OVRD_EN       ( 1'd0),                                // 
+        .QPLL_CP                        (10'h01F),                              // Optimized for Gen3 compliance (Gen1/Gen2 = 10'h1FF) 
+        .QPLL_CP_MONITOR_EN             ( 1'd0),                                //
+        .QPLL_DMONITOR_SEL              ( 1'd0),                                //
+        .QPLL_FBDIV                     (QPLL_FBDIV),                           // 
+        .QPLL_FBDIV_MONITOR_EN          ( 1'd0),                                //
+        .QPLL_FBDIV_RATIO               ( 1'd1),                                // Optimized for silicon
+      //.QPLL_INIT_CFG	                (24'h000006),                           // 
+        .QPLL_LOCK_CFG                  (16'h21E8),                             // Optimized for silicon, IES = 16'h01D0, GES 16'h21D0
+        .QPLL_LPF                       ( 4'hD),                                // Optimized for silicon, [1:0] = 2'b00 (13.3 KOhm), [1:0] = 2'b01 (57.0 KOhm)
+        .QPLL_REFCLK_DIV	              (1),                                    // 
+    
+        //---------- MISC ------------------------------------------------------
+        .BIAS_CFG                       (BIAS_CFG)                              // Optimized for silicon
+      //.COMMON_CFG                     (32'd0)                                 //
+    
+    )
+    gtxe2_common_i 
+    (
+           
+        //---------- Clock -----------------------------------------------------
+        .GTGREFCLK                      ( 1'd0),                                //
+        .GTREFCLK0                      (QPLL_GTGREFCLK),                       //
+        .GTREFCLK1                      ( 1'd0),                                //
+        .GTNORTHREFCLK0                 ( 1'd0),                                //
+        .GTNORTHREFCLK1                 ( 1'd0),                                //
+        .GTSOUTHREFCLK0                 ( 1'd0),                                //
+        .GTSOUTHREFCLK1                 ( 1'd0),                                //
+        .QPLLLOCKDETCLK                 (QPLL_QPLLLOCKDETCLK),                  //
+        .QPLLLOCKEN                     ( 1'd1),                                //
+        .QPLLREFCLKSEL                  ( 3'd1),                                //
+        .QPLLRSVD1                      (16'd0),                                //
+        .QPLLRSVD2                      ( 5'b11111),                            //
+                                                                               
+        .QPLLOUTCLK                     (QPLL_QPLLOUTCLK),                      //
+        .QPLLOUTREFCLK                  (QPLL_QPLLOUTREFCLK),                   //
+        .QPLLLOCK                       (QPLL_QPLLLOCK),                        //
+        .QPLLFBCLKLOST                  (),                                     //
+        .QPLLREFCLKLOST                 (),                                     //
+        .QPLLDMONITOR                   (),                                     //
+        
+        //---------- Reset -----------------------------------------------------
+        .QPLLPD                         (QPLL_QPLLPD),                          // 
+        .QPLLRESET                      (QPLL_QPLLRESET),                       //
+        .QPLLOUTRESET                   ( 1'd0),                                //
+        
+        //---------- DRP -------------------------------------------------------
+        .DRPCLK                         (QPLL_DRPCLK),                          //
+        .DRPADDR                        (QPLL_DRPADDR),                         //
+        .DRPEN                          (QPLL_DRPEN),                           //
+        .DRPDI                          (QPLL_DRPDI),                           //
+        .DRPWE                          (QPLL_DRPWE),                           //
+                                                                               
+        .DRPDO                          (QPLL_DRPDO),                           //
+        .DRPRDY                         (QPLL_DRPRDY),                          //
+                
+        //---------- Band Gap --------------------------------------------------    
+        .BGBYPASSB                      ( 1'd1),                                //
+        .BGMONITORENB                   ( 1'd1),                                //
+        .BGPDB                          ( 1'd1),                                //
+        .BGRCALOVRD                     ( 5'd31),                               //
+        
+        //---------- MISC ------------------------------------------------------
+        .PMARSVD                        ( 8'd0),                                //
+        .RCALENB                        ( 1'd1),                                // Optimized for GES
+                                                                               
+        .REFCLKOUTMONITOR               ()                                      //
+    
+    );
+    
+    end
+            
+endgenerate
+
+xdma_0_pcie2_ip_gtp_cpllpd_ovrd cpllPDInst (                                                                                   
+        .i_ibufds_gte2(QPLL_CPLLPDREFCLK),                                                                                 
+        .o_cpllpd_ovrd(cpllpd),                                                                                       
+        .o_cpllreset_ovrd(cpllrst));                       
+
+
+endmodule
+
+                                              

src/ip/xdma_0/ip_0/source/xdma_0_pcie2_ip_rxeq_scan.v

@@ -0,0 +1,366 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xdma_0_pcie2_ip_rxeq_scan.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  rxeq_scan.v
+//  Description  :  PIPE RX Equalization Eye Scan Module for 7 Series Transceiver
+//  Version      :  18.0
+//------------------------------------------------------------------------------
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- RXEQ Eye Scan Module ----------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_0_pcie2_ip_rxeq_scan #
+(
+
+    parameter PCIE_SIM_MODE       = "FALSE",                // PCIe sim mode 
+    parameter PCIE_GT_DEVICE      = "GTX",                  // PCIe GT device
+    parameter PCIE_RXEQ_MODE_GEN3 = 1,                      // PCIe RX equalization mode
+    parameter CONVERGE_MAX        = 22'd3125000,            // Convergence max count (12ms) 
+    parameter CONVERGE_MAX_BYPASS = 22'd2083333             // Convergence max count for phase2/3 bypass mode (8ms)
+)
+
+(
+
+    //---------- Input -------------------------------------
+    input               RXEQSCAN_CLK,                      
+    input               RXEQSCAN_RST_N,
+       
+    input       [ 1:0]  RXEQSCAN_CONTROL,   
+    input       [ 2:0]  RXEQSCAN_PRESET,
+    input               RXEQSCAN_PRESET_VALID,
+    input       [ 3:0]  RXEQSCAN_TXPRESET,
+    input       [17:0]  RXEQSCAN_TXCOEFF,
+    input               RXEQSCAN_NEW_TXCOEFF_REQ,
+    input       [ 5:0]  RXEQSCAN_FS,
+    input       [ 5:0]  RXEQSCAN_LF,
+     
+    
+    //---------- Output ------------------------------------
+    output              RXEQSCAN_PRESET_DONE,
+    output      [17:0]  RXEQSCAN_NEW_TXCOEFF,
+    output              RXEQSCAN_NEW_TXCOEFF_DONE,
+    output              RXEQSCAN_LFFS_SEL,
+    output              RXEQSCAN_ADAPT_DONE
+
+);
+
+    //---------- Input Register ----------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 2:0]  preset_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 preset_valid_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 3:0]  txpreset_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [17:0]  txcoeff_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 new_txcoeff_req_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 5:0]  fs_reg1;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 5:0]  lf_reg1;
+    
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 2:0]  preset_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 preset_valid_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 3:0]  txpreset_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [17:0]  txcoeff_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                 new_txcoeff_req_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 5:0]  fs_reg2;
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [ 5:0]  lf_reg2;
+
+    //---------- Internal Signals --------------------------
+    reg                 adapt_done_cnt = 1'd0;
+
+    //---------- Output Register ---------------------------          
+    reg                 preset_done      =  1'd0;
+    reg         [21:0]  converge_cnt     = 22'd0;
+    reg         [17:0]  new_txcoeff      = 18'd0;
+    reg                 new_txcoeff_done =  1'd0;
+    reg                 lffs_sel         =  1'd0;
+    reg                 adapt_done       =  1'd0;
+    reg         [ 3:0]  fsm              =  4'd0;
+
+    //---------- FSM ---------------------------------------                                         
+    localparam          FSM_IDLE            = 4'b0001;
+    localparam          FSM_PRESET          = 4'b0010;
+    localparam          FSM_CONVERGE        = 4'b0100;
+    localparam          FSM_NEW_TXCOEFF_REQ = 4'b1000; 
+    
+    //---------- Simulation Speedup ------------------------
+    //  Gen3:  32 bits / PCLK : 1 million bits / X PCLK
+    //         X = 
+    //------------------------------------------------------
+    localparam converge_max_cnt        = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX;   
+    localparam converge_max_bypass_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX_BYPASS;   
+    
+    
+
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge RXEQSCAN_CLK)
+begin
+
+    if (!RXEQSCAN_RST_N)
+        begin   
+        //---------- 1st Stage FF --------------------------  
+        preset_reg1          <=  3'd0;
+        preset_valid_reg1    <=  1'd0;
+        txpreset_reg1        <=  4'd0;
+        txcoeff_reg1         <= 18'd0;
+        new_txcoeff_req_reg1 <=  1'd0;
+        fs_reg1              <=  6'd0;
+        lf_reg1              <=  6'd0;
+        //---------- 2nd Stage FF --------------------------
+        preset_reg2          <=  3'd0;
+        preset_valid_reg2    <=  1'd0;
+        txpreset_reg2        <=  4'd0;
+        txcoeff_reg2         <= 18'd0;
+        new_txcoeff_req_reg2 <=  1'd0;
+        fs_reg2              <=  6'd0;
+        lf_reg2              <=  6'd0;
+        end
+    else
+        begin  
+        //---------- 1st Stage FF --------------------------  
+        preset_reg1          <= RXEQSCAN_PRESET;
+        preset_valid_reg1    <= RXEQSCAN_PRESET_VALID;
+        txpreset_reg1        <= RXEQSCAN_TXPRESET;
+        txcoeff_reg1         <= RXEQSCAN_TXCOEFF;
+        new_txcoeff_req_reg1 <= RXEQSCAN_NEW_TXCOEFF_REQ;
+        fs_reg1              <= RXEQSCAN_FS;
+        lf_reg1              <= RXEQSCAN_LF;
+        //---------- 2nd Stage FF -------------------------- 
+        preset_reg2          <= preset_reg1;
+        preset_valid_reg2    <= preset_valid_reg1;
+        txpreset_reg2        <= txpreset_reg1;
+        txcoeff_reg2         <= txcoeff_reg1;
+        new_txcoeff_req_reg2 <= new_txcoeff_req_reg1;
+        fs_reg2              <= fs_reg1;
+        lf_reg2              <= lf_reg1;
+        end
+        
+end     
+
+
+
+//---------- Eye Scan ----------------------------------------------------------
+always @ (posedge RXEQSCAN_CLK)
+begin
+
+    if (!RXEQSCAN_RST_N)
+        begin
+        fsm              <=  FSM_IDLE;
+        preset_done      <=  1'd0;
+        converge_cnt     <= 22'd0;
+        new_txcoeff      <= 18'd0;
+        new_txcoeff_done <=  1'd0;
+        lffs_sel         <=  1'd0;
+        adapt_done       <=  1'd0;
+        adapt_done_cnt   <=  1'd0;
+        end                   
+    else
+    
+        begin
+    
+        case (fsm)
+        
+        //---------- Idle State ----------------------------
+        FSM_IDLE : 
+            
+            begin   
+             
+            //---------- Process RXEQ Preset ---------------
+            if (preset_valid_reg2)
+                begin
+                fsm              <=  FSM_PRESET;
+                preset_done      <=  1'd1;
+                converge_cnt     <= 22'd0;
+                new_txcoeff      <=  new_txcoeff;
+                new_txcoeff_done <=  1'd0;
+                lffs_sel         <=  1'd0;
+                adapt_done       <=  1'd0;
+                adapt_done_cnt   <=  adapt_done_cnt;
+                end            
+            //---------- Request New TX Coefficient --------
+            else if (new_txcoeff_req_reg2)
+                begin
+                fsm              <=  FSM_CONVERGE;
+                preset_done      <=  1'd0;
+                converge_cnt     <= 22'd0;
+              //new_txcoeff      <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : 18'd4;  // Default
+                new_txcoeff      <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : (PCIE_GT_DEVICE == "GTX") ? 18'd5 : 18'd4;  // Optimized for Gen3 RX JTOL
+                new_txcoeff_done <=  1'd0;
+                lffs_sel         <= (PCIE_RXEQ_MODE_GEN3 == 0) ? 1'd0 : 1'd1;
+                adapt_done       <=  1'd0; 
+                adapt_done_cnt   <=  adapt_done_cnt;
+                end  
+            //---------- Default ---------------------------
+            else
+                begin
+                fsm              <=  FSM_IDLE;
+                preset_done      <=  1'd0;
+                converge_cnt     <= 22'd0;
+                new_txcoeff      <=  new_txcoeff;
+                new_txcoeff_done <=  1'd0;
+                lffs_sel         <=  1'd0;
+                adapt_done       <=  1'd0;
+                adapt_done_cnt   <=  adapt_done_cnt;
+                end
+                
+            end
+            
+        //---------- Process RXEQ Preset -------------------
+        FSM_PRESET :
+
+            begin
+            fsm              <= (!preset_valid_reg2) ? FSM_IDLE : FSM_PRESET;
+            preset_done      <=  1'd1;
+            converge_cnt     <= 22'd0;
+            new_txcoeff      <=  new_txcoeff;
+            new_txcoeff_done <=  1'd0;
+            lffs_sel         <=  1'd0;
+            adapt_done       <=  1'd0;
+            adapt_done_cnt   <=  adapt_done_cnt;
+            end
+            
+        //---------- Wait for Convergence ------------------    
+        FSM_CONVERGE :
+           
+            begin
+            if ((adapt_done_cnt == 1'd0) && (RXEQSCAN_CONTROL == 2'd2))
+                begin
+                fsm              <= FSM_NEW_TXCOEFF_REQ;
+                preset_done      <=  1'd0;
+                converge_cnt     <= 22'd0;
+                new_txcoeff      <= new_txcoeff;
+                new_txcoeff_done <= 1'd0;
+                lffs_sel         <= lffs_sel;
+                adapt_done       <= 1'd0;
+                adapt_done_cnt   <= adapt_done_cnt;
+                end
+            else
+                begin
+                
+                //---------- Phase2/3 ----------------------
+                if (RXEQSCAN_CONTROL == 2'd2)
+                    fsm <= (converge_cnt == converge_max_cnt)        ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
+                //---------- Phase2/3 Bypass ---------------
+                else
+                    fsm <= (converge_cnt == converge_max_bypass_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
+                
+                preset_done      <= 1'd0;
+                converge_cnt     <= converge_cnt + 1'd1;
+                new_txcoeff      <= new_txcoeff;
+                new_txcoeff_done <= 1'd0;
+                lffs_sel         <= lffs_sel;
+                adapt_done       <= 1'd0;
+                adapt_done_cnt   <= adapt_done_cnt;
+                end
+            end
+            
+        //---------- Request New TX Coefficient ------------
+        FSM_NEW_TXCOEFF_REQ :
+
+            begin 
+            if (!new_txcoeff_req_reg2)
+                begin
+                fsm              <= FSM_IDLE;
+                preset_done      <=  1'd0;
+                converge_cnt     <= 22'd0;
+                new_txcoeff      <= new_txcoeff;
+                new_txcoeff_done <= 1'd0;
+                lffs_sel         <= lffs_sel;
+                adapt_done       <= 1'd0;
+                adapt_done_cnt   <= (RXEQSCAN_CONTROL == 2'd3) ? 1'd0 : adapt_done_cnt + 1'd1;
+                end
+            else
+                begin
+                fsm              <= FSM_NEW_TXCOEFF_REQ;
+                preset_done      <=  1'd0;
+                converge_cnt     <= 22'd0;
+                new_txcoeff      <= new_txcoeff;
+                new_txcoeff_done <= 1'd1;
+                lffs_sel         <= lffs_sel;
+                adapt_done       <= (adapt_done_cnt == 1'd1) || (RXEQSCAN_CONTROL == 2'd3);
+                adapt_done_cnt   <= adapt_done_cnt;
+                end
+            end
+            
+        //---------- Default State -------------------------
+        default :
+        
+            begin
+            fsm              <=  FSM_IDLE;
+            preset_done      <=  1'd0;
+            converge_cnt     <= 22'd0;
+            new_txcoeff      <= 18'd0;
+            new_txcoeff_done <=  1'd0;
+            lffs_sel         <=  1'd0;
+            adapt_done       <=  1'd0;
+            adapt_done_cnt   <=  1'd0;
+            end    
+
+        endcase
+        
+        end
+        
+end
+
+
+
+//---------- RXEQ Eye Scan Output ----------------------------------------------
+assign RXEQSCAN_PRESET_DONE      = preset_done;     
+assign RXEQSCAN_NEW_TXCOEFF      = new_txcoeff;
+assign RXEQSCAN_NEW_TXCOEFF_DONE = new_txcoeff_done; 
+assign RXEQSCAN_LFFS_SEL         = lffs_sel;  
+assign RXEQSCAN_ADAPT_DONE       = adapt_done;
+
+
+
+endmodule

src/ip/xdma_0/ip_0/synth/xdma_0_pcie2_ip_ooc.xdc

@@ -0,0 +1,62 @@
+##-----------------------------------------------------------------------------
+##
+## (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+##-----------------------------------------------------------------------------
+## Project    : Series-7 Integrated Block for PCI Express
+## File       : xdma_0_pcie2_ip_ooc.xdc
+## Version    : 3.3
+#
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+
+#
+create_clock -name xdma_0_pcie2_ip_sys_clk -period 10 [get_ports sys_clk]
+# 100/125/250 MHz
+

src/ip/xdma_0/ip_0/sys_clk_gen_ps_v.txt

@@ -0,0 +1 @@
+//--------------------------------------------------------------------------------

src/ip/xdma_0/ip_0/xdma_0_pcie2_ip.xci

@@ -0,0 +1,968 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "xdma_0_pcie2_ip",
+    "component_reference": "xilinx.com:ip:pcie_7x:3.3",
+    "ip_revision": "14",
+    "gen_directory": ".",
+    "parameters": {
+      "component_parameters": {
+        "mode_selection": [ { "value": "Advanced", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Use_Class_Code_Lookup_Assistant": [ { "value": "false", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "xdma_0_pcie2_ip", "resolve_type": "user", "usage": "all" } ],
+        "Device_Port_Type": [ { "value": "PCI_Express_Endpoint_device", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Maximum_Link_Width": [ { "value": "X2", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Link_Speed": [ { "value": "5.0_GT/s", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Width": [ { "value": "64_bit", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "User_Clk_Freq": [ { "value": "125", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Bar0_Enabled": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar0_Type": [ { "value": "Memory", "resolve_type": "user", "usage": "all" } ],
+        "Bar0_64bit": [ { "value": "false", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar0_Prefetchable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar0_Scale": [ { "value": "Kilobytes", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Bar0_Size": [ { "value": "64", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Bar1_Enabled": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar1_Type": [ { "value": "Memory", "resolve_type": "user", "usage": "all" } ],
+        "Bar1_64bit": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar1_Prefetchable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar1_Scale": [ { "value": "Megabytes", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Bar1_Size": [ { "value": "1", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Bar2_Enabled": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar2_Type": [ { "value": "N/A", "resolve_type": "user", "usage": "all" } ],
+        "Bar2_64bit": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar2_Prefetchable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar2_Scale": [ { "value": "Kilobytes", "resolve_type": "user", "usage": "all" } ],
+        "Bar2_Size": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
+        "Bar3_Enabled": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar3_Type": [ { "value": "N/A", "resolve_type": "user", "usage": "all" } ],
+        "Bar3_64bit": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar3_Prefetchable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar3_Scale": [ { "value": "Kilobytes", "resolve_type": "user", "usage": "all" } ],
+        "Bar3_Size": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
+        "Bar4_Enabled": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar4_Type": [ { "value": "N/A", "resolve_type": "user", "usage": "all" } ],
+        "Bar4_64bit": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar4_Prefetchable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar4_Scale": [ { "value": "Kilobytes", "resolve_type": "user", "usage": "all" } ],
+        "Bar4_Size": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
+        "Bar5_Enabled": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar5_Type": [ { "value": "N/A", "resolve_type": "user", "usage": "all" } ],
+        "Bar5_Prefetchable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Bar5_Scale": [ { "value": "Kilobytes", "resolve_type": "user", "usage": "all" } ],
+        "Bar5_Size": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
+        "Expansion_Rom_Enabled": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Expansion_Rom_Scale": [ { "value": "Kilobytes", "resolve_type": "user", "usage": "all" } ],
+        "Expansion_Rom_Size": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
+        "IO_Base_Limit_Registers": [ { "value": "Disabled", "resolve_type": "user", "usage": "all" } ],
+        "Prefetchable_Memory_Base_Limit_Registers": [ { "value": "Disabled", "resolve_type": "user", "usage": "all" } ],
+        "Vendor_ID": [ { "value": "10EE", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Device_ID": [ { "value": "7022", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Revision_ID": [ { "value": "00", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Subsystem_Vendor_ID": [ { "value": "10EE", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Subsystem_ID": [ { "value": "0007", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Class_Code_Base": [ { "value": "07", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Class_Code_Sub": [ { "value": "00", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Class_Code_Interface": [ { "value": "01", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Base_Class_Menu": [ { "value": "Simple_communication_controllers", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Sub_Class_Interface_Menu": [ { "value": "16450_compatible_serial_controller", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Cardbus_CIS_Pointer": [ { "value": "00000000", "resolve_type": "user", "usage": "all" } ],
+        "PCIe_Cap_Slot_Implemented": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Max_Payload_Size": [ { "value": "512_bytes", "resolve_type": "user", "usage": "all" } ],
+        "Extended_Tag_Field": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Extended_Tag_Default": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Phantom_Functions": [ { "value": "No_function_number_bits_used", "resolve_type": "user", "usage": "all" } ],
+        "Acceptable_L0s_Latency": [ { "value": "Maximum_of_64_ns", "resolve_type": "user", "usage": "all" } ],
+        "Acceptable_L1_Latency": [ { "value": "No_limit", "resolve_type": "user", "usage": "all" } ],
+        "Cpl_Finite": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Cpl_Timeout_Disable_Sup": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Cpl_Timeout_Range": [ { "value": "Range_B", "resolve_type": "user", "usage": "all" } ],
+        "Buf_Opt_BMA": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Perf_Level": [ { "value": "High", "resolve_type": "user", "usage": "all" } ],
+        "Dll_Link_Active_Cap": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RCB": [ { "value": "64_byte", "resolve_type": "user", "usage": "all" } ],
+        "Trgt_Link_Speed": [ { "value": "4'h2", "resolve_type": "user", "usage": "all" } ],
+        "Hw_Auton_Spd_Disable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "De_emph": [ { "value": "-3.5", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Slot_Clock_Cfg": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Root_Cap_CRS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Slot_Cap_Attn_Butn": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Slot_Cap_Pwr_Ctrl": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Slot_Cap_MRL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Slot_Cap_Attn_Ind": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Slot_Cap_Pwr_Ind": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Slot_Cap_HotPlug_Surprise": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Slot_Cap_HotPlug_Cap": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Slot_Cap_Elec_Interlock": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Slot_Cap_No_Cmd_Comp_Sup": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Slot_Cap_Pwr_Limit_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "Slot_Cap_Pwr_Limit_Scale": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Slot_Cap_Physical_Slot_Num": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "IntX_Generation": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Legacy_Interrupt": [ { "value": "INTA", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "MSI_Enabled": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MSI_64b": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Multiple_Message_Capable": [ { "value": "1_vector", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "MSI_Vec_Mask": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MSIx_Enabled": [ { "value": "false", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MSIx_Table_Size": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "MSIx_Table_Offset": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "MSIx_Table_BIR": [ { "value": "BAR_0", "resolve_type": "user", "usage": "all" } ],
+        "MSIx_PBA_Offset": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "MSIx_PBA_BIR": [ { "value": "BAR_0", "resolve_type": "user", "usage": "all" } ],
+        "Device_Specific_Initialization": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "D1_Support": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "D2_Support": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "D0_PME_Support": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "D1_PME_Support": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "D2_PME_Support": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "D3hot_PME_Support": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "D3cold_PME_Support": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "No_Soft_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "D0_Power_Consumed": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D0_Power_Consumed_Factor": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D1_Power_Consumed": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D1_Power_Consumed_Factor": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D2_Power_Consumed": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D2_Power_Consumed_Factor": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D3_Power_Consumed": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D3_Power_Consumed_Factor": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D0_Power_Dissipated": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D0_Power_Dissipated_Factor": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D1_Power_Dissipated": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D1_Power_Dissipated_Factor": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D2_Power_Dissipated": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D2_Power_Dissipated_Factor": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D3_Power_Dissipated": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "D3_Power_Dissipated_Factor": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DSN_Enabled": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "VC_Cap_Enabled": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "VC_Cap_Reject_Snoop": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "VSEC_Enabled": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PCI_CFG_Space": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PCI_CFG_Space_Addr": [ { "value": "3F", "resolve_type": "user", "usage": "all" } ],
+        "EXT_PCI_CFG_Space": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "EXT_PCI_CFG_Space_Addr": [ { "value": "3FF", "resolve_type": "user", "usage": "all" } ],
+        "Xlnx_Ref_Board": [ { "value": "None", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "PCIe_Blk_Locn": [ { "value": "X0Y0", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Trans_Buf_Pipeline": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "En_route_unlock": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "En_route_pme_to": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "En_route_err_cor": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "En_route_err_nfl": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "En_route_err_ftl": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "En_route_inta": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "En_route_intb": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "En_route_intc": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "En_route_intd": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "En_route_pm_pme": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "En_route_pme_to_ack": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Receive_NP_Request": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_ACK_NAK_Timer": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ACK_NAK_Timeout_Func": [ { "value": "Absolute", "resolve_type": "user", "usage": "all" } ],
+        "ACK_NAK_Timeout_Value": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Replay_Timer": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Replay_Timeout_Func": [ { "value": "Add", "resolve_type": "user", "usage": "all" } ],
+        "Replay_Timeout_Value": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Lane_Reversal": [ { "value": "false", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Upconfigure_Capable": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Force_No_Scrambling": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Disable_Tx_ASPM_L0s": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Downstream_Link_Num": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
+        "UR_INV_REQ": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "UR_PRS_RESPONSE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Silicon_Rev": [ { "value": "GES_and_Production", "resolve_type": "user", "usage": "all" } ],
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+        "pl_sel_lnk_rate": [ { "direction": "out" } ],
+        "pl_sel_lnk_width": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "pl_ltssm_state": [ { "direction": "out", "size_left": "5", "size_right": "0" } ],
+        "pl_lane_reversal_mode": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "pl_phy_lnk_up": [ { "direction": "out" } ],
+        "pl_tx_pm_state": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "pl_rx_pm_state": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "pl_link_upcfg_cap": [ { "direction": "out" } ],
+        "pl_link_gen2_cap": [ { "direction": "out" } ],
+        "pl_link_partner_gen2_supported": [ { "direction": "out" } ],
+        "pl_initial_link_width": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "pl_directed_change_done": [ { "direction": "out" } ],
+        "pl_received_hot_rst": [ { "direction": "out" } ],
+        "pl_transmit_hot_rst": [ { "direction": "in", "driver_value": "0" } ],
+        "pl_downstream_deemph_source": [ { "direction": "in", "driver_value": "0" } ],
+        "cfg_err_aer_headerlog": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
+        "cfg_aer_interrupt_msgnum": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0" } ],
+        "cfg_err_aer_headerlog_set": [ { "direction": "out" } ],
+        "cfg_aer_ecrc_check_en": [ { "direction": "out" } ],
+        "cfg_aer_ecrc_gen_en": [ { "direction": "out" } ],
+        "cfg_vc_tcvc_map": [ { "direction": "out", "size_left": "6", "size_right": "0" } ],
+        "sys_clk": [ { "direction": "in" } ],
+        "sys_rst_n": [ { "direction": "in" } ]
+      },
+      "interfaces": {
+        "m_axis_rx": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "22", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_rx_tdata" } ],
+            "TKEEP": [ { "physical_name": "m_axis_rx_tkeep" } ],
+            "TLAST": [ { "physical_name": "m_axis_rx_tlast" } ],
+            "TREADY": [ { "physical_name": "m_axis_rx_tready" } ],
+            "TUSER": [ { "physical_name": "m_axis_rx_tuser" } ],
+            "TVALID": [ { "physical_name": "m_axis_rx_tvalid" } ]
+          }
+        },
+        "s_axis_tx": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "4", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_tx_tdata" } ],
+            "TKEEP": [ { "physical_name": "s_axis_tx_tkeep" } ],
+            "TLAST": [ { "physical_name": "s_axis_tx_tlast" } ],
+            "TREADY": [ { "physical_name": "s_axis_tx_tready" } ],
+            "TUSER": [ { "physical_name": "s_axis_tx_tuser" } ],
+            "TVALID": [ { "physical_name": "s_axis_tx_tvalid" } ]
+          }
+        },
+        "pcie_7x_mgt": {
+          "vlnv": "xilinx.com:interface:pcie_7x_mgt:1.0",
+          "abstraction_type": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0",
+          "mode": "master",
+          "port_maps": {
+            "rxn": [ { "physical_name": "pci_exp_rxn" } ],
+            "rxp": [ { "physical_name": "pci_exp_rxp" } ],
+            "txn": [ { "physical_name": "pci_exp_txn" } ],
+            "txp": [ { "physical_name": "pci_exp_txp" } ]
+          }
+        },
+        "CLK.sys_clk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "sys_clk" } ]
+          }
+        },
+        "CLK.user_clk_out": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "m_axis_rx:s_axis_tx", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "125000000", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "user_reset_out", "value_src": "constant", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "user_clk_out" } ]
+          }
+        },
+        "RST.sys_rst_n": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "sys_rst_n" } ]
+          }
+        },
+        "RST.user_reset_out": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "user_reset_out" } ]
+          }
+        },
+        "pcie2_cfg_err": {
+          "vlnv": "xilinx.com:interface:pcie2_cfg_err:1.0",
+          "abstraction_type": "xilinx.com:interface:pcie2_cfg_err_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "acs": [ { "physical_name": "cfg_err_acs" } ],
+            "aer_ecrc_check_en": [ { "physical_name": "cfg_aer_ecrc_check_en" } ],
+            "aer_ecrc_gen_en": [ { "physical_name": "cfg_aer_ecrc_gen_en" } ],
+            "aer_interrupt_msgnum": [ { "physical_name": "cfg_aer_interrupt_msgnum" } ],
+            "atomic_egress_blocked": [ { "physical_name": "cfg_err_atomic_egress_blocked" } ],
+            "cor": [ { "physical_name": "cfg_err_cor" } ],
+            "cpl_abort": [ { "physical_name": "cfg_err_cpl_abort" } ],
+            "cpl_rdy": [ { "physical_name": "cfg_err_cpl_rdy" } ],
+            "cpl_timeout": [ { "physical_name": "cfg_err_cpl_timeout" } ],
+            "cpl_unexpect": [ { "physical_name": "cfg_err_cpl_unexpect" } ],
+            "ecrc": [ { "physical_name": "cfg_err_ecrc" } ],
+            "err_aer_headerlog": [ { "physical_name": "cfg_err_aer_headerlog" } ],
+            "err_aer_headerlog_set": [ { "physical_name": "cfg_err_aer_headerlog_set" } ],
+            "internal_cor": [ { "physical_name": "cfg_err_internal_cor" } ],
+            "internal_uncor": [ { "physical_name": "cfg_err_internal_uncor" } ],
+            "locked": [ { "physical_name": "cfg_err_locked" } ],
+            "malformed": [ { "physical_name": "cfg_err_malformed" } ],
+            "mc_blocked": [ { "physical_name": "cfg_err_mc_blocked" } ],
+            "norecovery": [ { "physical_name": "cfg_err_norecovery" } ],
+            "poisoned": [ { "physical_name": "cfg_err_poisoned" } ],
+            "posted": [ { "physical_name": "cfg_err_posted" } ],
+            "tlp_cpl_header": [ { "physical_name": "cfg_err_tlp_cpl_header" } ],
+            "ur": [ { "physical_name": "cfg_err_ur" } ]
+          }
+        },
+        "pcie2_cfg_interrupt": {
+          "vlnv": "xilinx.com:interface:pcie2_cfg_interrupt:1.0",
+          "abstraction_type": "xilinx.com:interface:pcie2_cfg_interrupt_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "assert": [ { "physical_name": "cfg_interrupt_assert" } ],
+            "interrupt": [ { "physical_name": "cfg_interrupt" } ],
+            "mmenable": [ { "physical_name": "cfg_interrupt_mmenable" } ],
+            "msienable": [ { "physical_name": "cfg_interrupt_msienable" } ],
+            "msixenable": [ { "physical_name": "cfg_interrupt_msixenable" } ],
+            "msixfm": [ { "physical_name": "cfg_interrupt_msixfm" } ],
+            "pciecap_interrupt_msgnum": [ { "physical_name": "cfg_pciecap_interrupt_msgnum" } ],
+            "rdy": [ { "physical_name": "cfg_interrupt_rdy" } ],
+            "read_data": [ { "physical_name": "cfg_interrupt_do" } ],
+            "stat": [ { "physical_name": "cfg_interrupt_stat" } ],
+            "write_data": [ { "physical_name": "cfg_interrupt_di" } ]
+          }
+        },
+        "pcie2_cfg_status": {
+          "vlnv": "xilinx.com:interface:pcie2_cfg_status:1.0",
+          "abstraction_type": "xilinx.com:interface:pcie2_cfg_status_rtl:1.0",
+          "mode": "master",
+          "port_maps": {
+            "aer_rooterr_corr_err_received": [ { "physical_name": "cfg_aer_rooterr_corr_err_received" } ],
+            "aer_rooterr_corr_err_reporting_en": [ { "physical_name": "cfg_aer_rooterr_corr_err_reporting_en" } ],
+            "aer_rooterr_fatal_err_received": [ { "physical_name": "cfg_aer_rooterr_fatal_err_received" } ],
+            "aer_rooterr_fatal_err_reporting_en": [ { "physical_name": "cfg_aer_rooterr_fatal_err_reporting_en" } ],
+            "aer_rooterr_non_fatal_err_received": [ { "physical_name": "cfg_aer_rooterr_non_fatal_err_received" } ],
+            "aer_rooterr_non_fatal_err_reporting_en": [ { "physical_name": "cfg_aer_rooterr_non_fatal_err_reporting_en" } ],
+            "bridge_serr_en": [ { "physical_name": "cfg_bridge_serr_en" } ],
+            "bus_number": [ { "physical_name": "cfg_bus_number" } ],
+            "command": [ { "physical_name": "cfg_command" } ],
+            "dcommand": [ { "physical_name": "cfg_dcommand" } ],
+            "dcommand2": [ { "physical_name": "cfg_dcommand2" } ],
+            "device_number": [ { "physical_name": "cfg_device_number" } ],
+            "dstatus": [ { "physical_name": "cfg_dstatus" } ],
+            "function_number": [ { "physical_name": "cfg_function_number" } ],
+            "lcommand": [ { "physical_name": "cfg_lcommand" } ],
+            "lstatus": [ { "physical_name": "cfg_lstatus" } ],
+            "pcie_link_state": [ { "physical_name": "cfg_pcie_link_state" } ],
+            "pmcsr_pme_en": [ { "physical_name": "cfg_pmcsr_pme_en" } ],
+            "pmcsr_pme_status": [ { "physical_name": "cfg_pmcsr_pme_status" } ],
+            "pmcsr_powerstate": [ { "physical_name": "cfg_pmcsr_powerstate" } ],
+            "received_func_lvl_rst": [ { "physical_name": "cfg_received_func_lvl_rst" } ],
+            "root_control_pme_int_en": [ { "physical_name": "cfg_root_control_pme_int_en" } ],
+            "root_control_syserr_corr_err_en": [ { "physical_name": "cfg_root_control_syserr_corr_err_en" } ],
+            "root_control_syserr_fatal_err_en": [ { "physical_name": "cfg_root_control_syserr_fatal_err_en" } ],
+            "root_control_syserr_non_fatal_err_en": [ { "physical_name": "cfg_root_control_syserr_non_fatal_err_en" } ],
+            "slot_control_electromech_il_ctl_pulse": [ { "physical_name": "cfg_slot_control_electromech_il_ctl_pulse" } ],
+            "status": [ { "physical_name": "cfg_status" } ],
+            "turnoff": [ { "physical_name": "cfg_to_turnoff" } ],
+            "tx_buf_av": [ { "physical_name": "tx_buf_av" } ],
+            "tx_cfg_req": [ { "physical_name": "tx_cfg_req" } ],
+            "tx_err_drop": [ { "physical_name": "tx_err_drop" } ],
+            "vc_tcvc_map": [ { "physical_name": "cfg_vc_tcvc_map" } ]
+          }
+        },
+        "pcie_cfg_fc": {
+          "vlnv": "xilinx.com:interface:pcie_cfg_fc:1.0",
+          "abstraction_type": "xilinx.com:interface:pcie_cfg_fc_rtl:1.0",
+          "mode": "master",
+          "port_maps": {
+            "CPLD": [ { "physical_name": "fc_cpld" } ],
+            "CPLH": [ { "physical_name": "fc_cplh" } ],
+            "NPD": [ { "physical_name": "fc_npd" } ],
+            "NPH": [ { "physical_name": "fc_nph" } ],
+            "PD": [ { "physical_name": "fc_pd" } ],
+            "PH": [ { "physical_name": "fc_ph" } ],
+            "SEL": [ { "physical_name": "fc_sel" } ]
+          }
+        },
+        "pcie2_cfg_control": {
+          "vlnv": "xilinx.com:interface:pcie2_cfg_control:1.0",
+          "abstraction_type": "xilinx.com:interface:pcie2_cfg_control_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "ds_bus_number": [ { "physical_name": "cfg_ds_bus_number" } ],
+            "ds_device_number": [ { "physical_name": "cfg_ds_device_number" } ],
+            "ds_function_number": [ { "physical_name": "cfg_ds_function_number" } ],
+            "dsn": [ { "physical_name": "cfg_dsn" } ],
+            "pm_force_state": [ { "physical_name": "cfg_pm_force_state" } ],
+            "pm_force_state_en": [ { "physical_name": "cfg_pm_force_state_en" } ],
+            "pm_halt_aspm_l0s": [ { "physical_name": "cfg_pm_halt_aspm_l0s" } ],
+            "pm_halt_aspm_l1": [ { "physical_name": "cfg_pm_halt_aspm_l1" } ],
+            "pm_send_pme_to": [ { "physical_name": "cfg_pm_send_pme_to" } ],
+            "pm_wake": [ { "physical_name": "cfg_pm_wake" } ],
+            "rx_np_ok": [ { "physical_name": "rx_np_ok" } ],
+            "rx_np_req": [ { "physical_name": "rx_np_req" } ],
+            "trn_pending": [ { "physical_name": "cfg_trn_pending" } ],
+            "turnoff_ok": [ { "physical_name": "cfg_turnoff_ok" } ],
+            "tx_cfg_gnt": [ { "physical_name": "tx_cfg_gnt" } ]
+          }
+        },
+        "pcie2_cfg_msg_rcvd": {
+          "vlnv": "xilinx.com:interface:pcie2_cfg_msg_rcvd:1.0",
+          "abstraction_type": "xilinx.com:interface:pcie2_cfg_msg_rcvd_rtl:1.0",
+          "mode": "master",
+          "port_maps": {
+            "assert_int_a": [ { "physical_name": "cfg_msg_received_assert_int_a" } ],
+            "assert_int_b": [ { "physical_name": "cfg_msg_received_assert_int_b" } ],
+            "assert_int_c": [ { "physical_name": "cfg_msg_received_assert_int_c" } ],
+            "assert_int_d": [ { "physical_name": "cfg_msg_received_assert_int_d" } ],
+            "data": [ { "physical_name": "cfg_msg_data" } ],
+            "deassert_int_a": [ { "physical_name": "cfg_msg_received_deassert_int_a" } ],
+            "deassert_int_b": [ { "physical_name": "cfg_msg_received_deassert_int_b" } ],
+            "deassert_int_c": [ { "physical_name": "cfg_msg_received_deassert_int_c" } ],
+            "deassert_int_d": [ { "physical_name": "cfg_msg_received_deassert_int_d" } ],
+            "err_cor": [ { "physical_name": "cfg_msg_received_err_cor" } ],
+            "err_fatal": [ { "physical_name": "cfg_msg_received_err_fatal" } ],
+            "err_non_fatal": [ { "physical_name": "cfg_msg_received_err_non_fatal" } ],
+            "pm_pme": [ { "physical_name": "cfg_msg_received_pm_pme" } ],
+            "pme_to_ack": [ { "physical_name": "cfg_msg_received_pme_to_ack" } ],
+            "received": [ { "physical_name": "cfg_msg_received" } ],
+            "received_pm_as_nak": [ { "physical_name": "cfg_msg_received_pm_as_nak" } ],
+            "received_setslotpowerlimit": [ { "physical_name": "cfg_msg_received_setslotpowerlimit" } ]
+          }
+        },
+        "pcie_cfg_mgmt": {
+          "vlnv": "xilinx.com:interface:pcie_cfg_mgmt:1.0",
+          "abstraction_type": "xilinx.com:interface:pcie_cfg_mgmt_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "ADDR": [ { "physical_name": "cfg_mgmt_dwaddr" } ],
+            "BYTE_EN": [ { "physical_name": "cfg_mgmt_byte_en" } ],
+            "READ_DATA": [ { "physical_name": "cfg_mgmt_do" } ],
+            "READ_EN": [ { "physical_name": "cfg_mgmt_rd_en" } ],
+            "READ_WRITE_DONE": [ { "physical_name": "cfg_mgmt_rd_wr_done" } ],
+            "READONLY": [ { "physical_name": "cfg_mgmt_wr_readonly" } ],
+            "TYPE1_CFG_REG_ACCESS": [ { "physical_name": "cfg_mgmt_wr_rw1c_as_rw" } ],
+            "WRITE_DATA": [ { "physical_name": "cfg_mgmt_di" } ],
+            "WRITE_EN": [ { "physical_name": "cfg_mgmt_wr_en" } ]
+          }
+        },
+        "pcie2_pl": {
+          "vlnv": "xilinx.com:interface:pcie2_pl:1.0",
+          "abstraction_type": "xilinx.com:interface:pcie2_pl_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "directed_change_done": [ { "physical_name": "pl_directed_change_done" } ],
+            "directed_link_auton": [ { "physical_name": "pl_directed_link_auton" } ],
+            "directed_link_change": [ { "physical_name": "pl_directed_link_change" } ],
+            "directed_link_speed": [ { "physical_name": "pl_directed_link_speed" } ],
+            "directed_link_width": [ { "physical_name": "pl_directed_link_width" } ],
+            "downstream_deemph_source": [ { "physical_name": "pl_downstream_deemph_source" } ],
+            "initial_link_width": [ { "physical_name": "pl_initial_link_width" } ],
+            "lane_reversal_mode": [ { "physical_name": "pl_lane_reversal_mode" } ],
+            "link_gen2_cap": [ { "physical_name": "pl_link_gen2_cap" } ],
+            "link_partner_gen2_supported": [ { "physical_name": "pl_link_partner_gen2_supported" } ],
+            "link_upcfg_cap": [ { "physical_name": "pl_link_upcfg_cap" } ],
+            "ltssm_state": [ { "physical_name": "pl_ltssm_state" } ],
+            "phy_lnk_up": [ { "physical_name": "pl_phy_lnk_up" } ],
+            "received_hot_rst": [ { "physical_name": "pl_received_hot_rst" } ],
+            "rx_pm_state": [ { "physical_name": "pl_rx_pm_state" } ],
+            "sel_lnk_rate": [ { "physical_name": "pl_sel_lnk_rate" } ],
+            "sel_lnk_width": [ { "physical_name": "pl_sel_lnk_width" } ],
+            "transmit_hot_rst": [ { "physical_name": "pl_transmit_hot_rst" } ],
+            "tx_pm_state": [ { "physical_name": "pl_tx_pm_state" } ],
+            "upstream_prefer_deemph": [ { "physical_name": "pl_upstream_prefer_deemph" } ]
+          }
+        }
+      }
+    }
+  }
+}

src/ip/xdma_0/ip_1/sim/xdma_v4_1_8_blk_mem_64_reg_be.v

@@ -0,0 +1,230 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_v4_1_8_blk_mem_64_reg_be (
+  clka,
+  ena,
+  wea,
+  addra,
+  dina,
+  clkb,
+  enb,
+  addrb,
+  doutb
+);
+
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
+input wire clka;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
+input wire ena;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
+input wire [7 : 0] wea;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
+input wire [8 : 0] addra;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
+input wire [71 : 0] dina;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
+input wire clkb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
+input wire enb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
+input wire [8 : 0] addrb;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
+output wire [71 : 0] doutb;
+
+  blk_mem_gen_v8_4_4 #(
+    .C_FAMILY("artix7"),
+    .C_XDEVICEFAMILY("artix7"),
+    .C_ELABORATION_DIR("./"),
+    .C_INTERFACE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_USE_BRAM_BLOCK(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
+    .C_CTRL_ECC_ALGO("NONE"),
+    .C_HAS_AXI_ID(0),
+    .C_AXI_ID_WIDTH(4),
+    .C_MEM_TYPE(1),
+    .C_BYTE_SIZE(9),
+    .C_ALGORITHM(1),
+    .C_PRIM_TYPE(1),
+    .C_LOAD_INIT_FILE(0),
+    .C_INIT_FILE_NAME("no_coe_file_loaded"),
+    .C_INIT_FILE("xdma_v4_1_8_blk_mem_64_reg_be.mem"),
+    .C_USE_DEFAULT_DATA(0),
+    .C_DEFAULT_DATA("0"),
+    .C_HAS_RSTA(0),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RSTRAM_A(0),
+    .C_INITA_VAL("0"),
+    .C_HAS_ENA(1),
+    .C_HAS_REGCEA(0),
+    .C_USE_BYTE_WEA(1),
+    .C_WEA_WIDTH(8),
+    .C_WRITE_MODE_A("READ_FIRST"),
+    .C_WRITE_WIDTH_A(72),
+    .C_READ_WIDTH_A(72),
+    .C_WRITE_DEPTH_A(512),
+    .C_READ_DEPTH_A(512),
+    .C_ADDRA_WIDTH(9),
+    .C_HAS_RSTB(0),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RSTRAM_B(0),
+    .C_INITB_VAL("0"),
+    .C_HAS_ENB(1),
+    .C_HAS_REGCEB(0),
+    .C_USE_BYTE_WEB(1),
+    .C_WEB_WIDTH(8),
+    .C_WRITE_MODE_B("READ_FIRST"),
+    .C_WRITE_WIDTH_B(72),
+    .C_READ_WIDTH_B(72),
+    .C_WRITE_DEPTH_B(512),
+    .C_READ_DEPTH_B(512),
+    .C_ADDRB_WIDTH(9),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(1),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_USE_SOFTECC(0),
+    .C_USE_ECC(0),
+    .C_EN_ECC_PIPE(0),
+    .C_READ_LATENCY_A(1),
+    .C_READ_LATENCY_B(1),
+    .C_HAS_INJECTERR(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_COMMON_CLK(1),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_EN_SLEEP_PIN(0),
+    .C_USE_URAM(0),
+    .C_EN_RDADDRA_CHG(0),
+    .C_EN_RDADDRB_CHG(0),
+    .C_EN_DEEPSLEEP_PIN(0),
+    .C_EN_SHUTDOWN_PIN(0),
+    .C_EN_SAFETY_CKT(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_COUNT_36K_BRAM("1"),
+    .C_COUNT_18K_BRAM("0"),
+    .C_EST_POWER_SUMMARY("Estimated Power for IP     :     7.638025 mW")
+  ) inst (
+    .clka(clka),
+    .rsta(1'D0),
+    .ena(ena),
+    .regcea(1'D0),
+    .wea(wea),
+    .addra(addra),
+    .dina(dina),
+    .douta(),
+    .clkb(clkb),
+    .rstb(1'D0),
+    .enb(enb),
+    .regceb(1'D0),
+    .web(8'B0),
+    .addrb(addrb),
+    .dinb(72'B0),
+    .doutb(doutb),
+    .injectsbiterr(1'D0),
+    .injectdbiterr(1'D0),
+    .eccpipece(1'D0),
+    .sbiterr(),
+    .dbiterr(),
+    .rdaddrecc(),
+    .sleep(1'D0),
+    .deepsleep(1'D0),
+    .shutdown(1'D0),
+    .rsta_busy(),
+    .rstb_busy(),
+    .s_aclk(1'H0),
+    .s_aresetn(1'D0),
+    .s_axi_awid(4'B0),
+    .s_axi_awaddr(32'B0),
+    .s_axi_awlen(8'B0),
+    .s_axi_awsize(3'B0),
+    .s_axi_awburst(2'B0),
+    .s_axi_awvalid(1'D0),
+    .s_axi_awready(),
+    .s_axi_wdata(72'B0),
+    .s_axi_wstrb(8'B0),
+    .s_axi_wlast(1'D0),
+    .s_axi_wvalid(1'D0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'D0),
+    .s_axi_arid(4'B0),
+    .s_axi_araddr(32'B0),
+    .s_axi_arlen(8'B0),
+    .s_axi_arsize(3'B0),
+    .s_axi_arburst(2'B0),
+    .s_axi_arvalid(1'D0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'D0),
+    .s_axi_injectsbiterr(1'D0),
+    .s_axi_injectdbiterr(1'D0),
+    .s_axi_sbiterr(),
+    .s_axi_dbiterr(),
+    .s_axi_rdaddrecc()
+  );
+endmodule

src/ip/xdma_0/ip_1/xdma_v4_1_8_blk_mem_64_reg_be.xci

@@ -0,0 +1,279 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "xdma_v4_1_8_blk_mem_64_reg_be",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "4",
+    "gen_directory": ".",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "xdma_v4_1_8_blk_mem_64_reg_be", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
+        "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "Simple_Dual_Port_RAM", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
+        "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_Byte_Write_Enable": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Byte_Size": [ { "value": "9", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
+        "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Assume_Synchronous_Clk": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Width_A": [ { "value": "72", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Depth_A": [ { "value": "512", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Read_Width_A": [ { "value": "72", "value_src": "propagated", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Operating_Mode_A": [ { "value": "READ_FIRST", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Enable_A": [ { "value": "Use_ENA_Pin", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Write_Width_B": [ { "value": "72", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Read_Width_B": [ { "value": "72", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Operating_Mode_B": [ { "value": "READ_FIRST", "value_src": "propagated", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "propagated", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Clock": [ { "value": "100", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Enable_Rate": [ { "value": "100", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
+        "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
+        "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
+        "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
+        "EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
+        "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
+        "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
+        "C_INIT_FILE": [ { "value": "xdma_v4_1_8_blk_mem_64_reg_be.mem", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_A": [ { "value": "READ_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_A": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_A": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_A": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_A": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRA_WIDTH": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_B": [ { "value": "READ_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_B": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_B": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_B": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_B": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRB_WIDTH": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMMON_CLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_36K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     7.638025 mW", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "artix7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7a100t" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fgg484" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "4" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "." } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2020.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clka": [ { "direction": "in", "driver_value": "0" } ],
+        "ena": [ { "direction": "in", "driver_value": "0" } ],
+        "wea": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "addra": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
+        "dina": [ { "direction": "in", "size_left": "71", "size_right": "0", "driver_value": "0" } ],
+        "clkb": [ { "direction": "in", "driver_value": "0" } ],
+        "enb": [ { "direction": "in", "driver_value": "0" } ],
+        "addrb": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
+        "doutb": [ { "direction": "out", "size_left": "71", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "CLK.ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          }
+        },
+        "RST.ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          }
+        },
+        "BRAM_PORTA": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addra" } ],
+            "CLK": [ { "physical_name": "clka" } ],
+            "DIN": [ { "physical_name": "dina" } ],
+            "EN": [ { "physical_name": "ena" } ],
+            "WE": [ { "physical_name": "wea" } ]
+          }
+        },
+        "BRAM_PORTB": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addrb" } ],
+            "CLK": [ { "physical_name": "clkb" } ],
+            "DOUT": [ { "physical_name": "doutb" } ],
+            "EN": [ { "physical_name": "enb" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_1": {
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

src/ip/xdma_0/ip_1/xdma_v4_1_8_blk_mem_64_reg_be_ooc.xdc

@@ -0,0 +1,58 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ]
+    set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]
+  
+create_clock -name "TS_CLKB" -period 20.0 [ get_ports clkb ]
+    set_property HD.CLK_SRC BUFGCTRL_X0Y1 [ get_ports clkb ]
+################################################################################

src/ip/xdma_0/ip_2/sim/xdma_v4_1_8_blk_mem_64_noreg_be.v

@@ -0,0 +1,230 @@
+// (c) Copyright 1995-2024 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xdma_v4_1_8_blk_mem_64_noreg_be (
+  clka,
+  ena,
+  wea,
+  addra,
+  dina,
+  clkb,
+  enb,
+  addrb,
+  doutb
+);
+
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
+input wire clka;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
+input wire ena;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
+input wire [7 : 0] wea;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
+input wire [8 : 0] addra;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
+input wire [71 : 0] dina;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
+input wire clkb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
+input wire enb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
+input wire [8 : 0] addrb;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
+output wire [71 : 0] doutb;
+
+  blk_mem_gen_v8_4_4 #(
+    .C_FAMILY("artix7"),
+    .C_XDEVICEFAMILY("artix7"),
+    .C_ELABORATION_DIR("./"),
+    .C_INTERFACE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_USE_BRAM_BLOCK(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
+    .C_CTRL_ECC_ALGO("NONE"),
+    .C_HAS_AXI_ID(0),
+    .C_AXI_ID_WIDTH(4),
+    .C_MEM_TYPE(1),
+    .C_BYTE_SIZE(9),
+    .C_ALGORITHM(1),
+    .C_PRIM_TYPE(1),
+    .C_LOAD_INIT_FILE(0),
+    .C_INIT_FILE_NAME("no_coe_file_loaded"),
+    .C_INIT_FILE("xdma_v4_1_8_blk_mem_64_noreg_be.mem"),
+    .C_USE_DEFAULT_DATA(0),
+    .C_DEFAULT_DATA("0"),
+    .C_HAS_RSTA(0),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RSTRAM_A(0),
+    .C_INITA_VAL("0"),
+    .C_HAS_ENA(1),
+    .C_HAS_REGCEA(0),
+    .C_USE_BYTE_WEA(1),
+    .C_WEA_WIDTH(8),
+    .C_WRITE_MODE_A("READ_FIRST"),
+    .C_WRITE_WIDTH_A(72),
+    .C_READ_WIDTH_A(72),
+    .C_WRITE_DEPTH_A(512),
+    .C_READ_DEPTH_A(512),
+    .C_ADDRA_WIDTH(9),
+    .C_HAS_RSTB(0),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RSTRAM_B(0),
+    .C_INITB_VAL("0"),
+    .C_HAS_ENB(1),
+    .C_HAS_REGCEB(0),
+    .C_USE_BYTE_WEB(1),
+    .C_WEB_WIDTH(8),
+    .C_WRITE_MODE_B("READ_FIRST"),
+    .C_WRITE_WIDTH_B(72),
+    .C_READ_WIDTH_B(72),
+    .C_WRITE_DEPTH_B(512),
+    .C_READ_DEPTH_B(512),
+    .C_ADDRB_WIDTH(9),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_USE_SOFTECC(0),
+    .C_USE_ECC(0),
+    .C_EN_ECC_PIPE(0),
+    .C_READ_LATENCY_A(1),
+    .C_READ_LATENCY_B(1),
+    .C_HAS_INJECTERR(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_COMMON_CLK(1),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_EN_SLEEP_PIN(0),
+    .C_USE_URAM(0),
+    .C_EN_RDADDRA_CHG(0),
+    .C_EN_RDADDRB_CHG(0),
+    .C_EN_DEEPSLEEP_PIN(0),
+    .C_EN_SHUTDOWN_PIN(0),
+    .C_EN_SAFETY_CKT(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_COUNT_36K_BRAM("1"),
+    .C_COUNT_18K_BRAM("0"),
+    .C_EST_POWER_SUMMARY("Estimated Power for IP     :     7.638025 mW")
+  ) inst (
+    .clka(clka),
+    .rsta(1'D0),
+    .ena(ena),
+    .regcea(1'D0),
+    .wea(wea),
+    .addra(addra),
+    .dina(dina),
+    .douta(),
+    .clkb(clkb),
+    .rstb(1'D0),
+    .enb(enb),
+    .regceb(1'D0),
+    .web(8'B0),
+    .addrb(addrb),
+    .dinb(72'B0),
+    .doutb(doutb),
+    .injectsbiterr(1'D0),
+    .injectdbiterr(1'D0),
+    .eccpipece(1'D0),
+    .sbiterr(),
+    .dbiterr(),
+    .rdaddrecc(),
+    .sleep(1'D0),
+    .deepsleep(1'D0),
+    .shutdown(1'D0),
+    .rsta_busy(),
+    .rstb_busy(),
+    .s_aclk(1'H0),
+    .s_aresetn(1'D0),
+    .s_axi_awid(4'B0),
+    .s_axi_awaddr(32'B0),
+    .s_axi_awlen(8'B0),
+    .s_axi_awsize(3'B0),
+    .s_axi_awburst(2'B0),
+    .s_axi_awvalid(1'D0),
+    .s_axi_awready(),
+    .s_axi_wdata(72'B0),
+    .s_axi_wstrb(8'B0),
+    .s_axi_wlast(1'D0),
+    .s_axi_wvalid(1'D0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'D0),
+    .s_axi_arid(4'B0),
+    .s_axi_araddr(32'B0),
+    .s_axi_arlen(8'B0),
+    .s_axi_arsize(3'B0),
+    .s_axi_arburst(2'B0),
+    .s_axi_arvalid(1'D0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'D0),
+    .s_axi_injectsbiterr(1'D0),
+    .s_axi_injectdbiterr(1'D0),
+    .s_axi_sbiterr(),
+    .s_axi_dbiterr(),
+    .s_axi_rdaddrecc()
+  );
+endmodule

src/ip/xdma_0/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be.xci

@@ -0,0 +1,279 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "xdma_v4_1_8_blk_mem_64_noreg_be",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "4",
+    "gen_directory": ".",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "xdma_v4_1_8_blk_mem_64_noreg_be", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
+        "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "Simple_Dual_Port_RAM", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
+        "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_Byte_Write_Enable": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Byte_Size": [ { "value": "9", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
+        "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Assume_Synchronous_Clk": [ { "value": "true", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Width_A": [ { "value": "72", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Depth_A": [ { "value": "512", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Read_Width_A": [ { "value": "72", "value_src": "propagated", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Operating_Mode_A": [ { "value": "READ_FIRST", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Enable_A": [ { "value": "Use_ENA_Pin", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Write_Width_B": [ { "value": "72", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Read_Width_B": [ { "value": "72", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Operating_Mode_B": [ { "value": "READ_FIRST", "value_src": "propagated", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_B": [ { "value": "Use_ENB_Pin", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "propagated", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "propagated", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Clock": [ { "value": "100", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Enable_Rate": [ { "value": "100", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
+        "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
+        "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
+        "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
+        "EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
+        "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
+        "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
+        "C_INIT_FILE": [ { "value": "xdma_v4_1_8_blk_mem_64_noreg_be.mem", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_A": [ { "value": "READ_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_A": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_A": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_A": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_A": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRA_WIDTH": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITB_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_ENB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BYTE_WEB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WEB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_MODE_B": [ { "value": "READ_FIRST", "resolve_type": "generated", "usage": "all" } ],
+        "C_WRITE_WIDTH_B": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_WIDTH_B": [ { "value": "72", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_WRITE_DEPTH_B": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_DEPTH_B": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ADDRB_WIDTH": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_MUX_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MUX_PIPELINE_STAGES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_INPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_SOFTECC_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SOFTECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_ECC_PIPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_A": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_READ_LATENCY_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_INJECTERR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_COLLISION_CHECK": [ { "value": "ALL", "resolve_type": "generated", "usage": "all" } ],
+        "C_COMMON_CLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_COLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_URAM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRA_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_RDADDRB_CHG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_DEEPSLEEP_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SHUTDOWN_PIN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_COUNT_36K_BRAM": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP     :     7.638025 mW", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "artix7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7a100t" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "fgg484" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "4" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "." } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2020.2" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clka": [ { "direction": "in", "driver_value": "0" } ],
+        "ena": [ { "direction": "in", "driver_value": "0" } ],
+        "wea": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "addra": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
+        "dina": [ { "direction": "in", "size_left": "71", "size_right": "0", "driver_value": "0" } ],
+        "clkb": [ { "direction": "in", "driver_value": "0" } ],
+        "enb": [ { "direction": "in", "driver_value": "0" } ],
+        "addrb": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
+        "doutb": [ { "direction": "out", "size_left": "71", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "CLK.ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          }
+        },
+        "RST.ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
+          }
+        },
+        "BRAM_PORTA": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addra" } ],
+            "CLK": [ { "physical_name": "clka" } ],
+            "DIN": [ { "physical_name": "dina" } ],
+            "EN": [ { "physical_name": "ena" } ],
+            "WE": [ { "physical_name": "wea" } ]
+          }
+        },
+        "BRAM_PORTB": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addrb" } ],
+            "CLK": [ { "physical_name": "clkb" } ],
+            "DOUT": [ { "physical_name": "doutb" } ],
+            "EN": [ { "physical_name": "enb" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_1": {
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

src/ip/xdma_0/ip_2/xdma_v4_1_8_blk_mem_64_noreg_be_ooc.xdc

@@ -0,0 +1,58 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ]
+    set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]
+  
+create_clock -name "TS_CLKB" -period 20.0 [ get_ports clkb ]
+    set_property HD.CLK_SRC BUFGCTRL_X0Y1 [ get_ports clkb ]
+################################################################################