Испрвления в скрипте

script/recreate.tcl

@@ -1,7 +1,7 @@
 #*****************************************************************************************
 # Vivado (TM) v2024.1 (64-bit)
 #
-# recreate.tcl: Tcl script for re-creating project 'VNA_XDMA'
+# recreate.tcl: Tcl script for re-creating project 'VNA_XDMA_PROJ'
 #
 # Generated by Vivado on Fri Oct 11 11:13:01 +0700 2024
 # IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
@@ -126,7 +126,7 @@ if { [info exists ::origin_dir_loc] } {
 }
 
 # Set the project name
-set _xil_proj_name_ "VNA_XDMA"
+set _xil_proj_name_ "VNA_XDMA_PROJ"
 
 # Use project name variable, if specified in the tcl shell
 if { [info exists ::user_project_name] } {
@@ -645,6 +645,8 @@ set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $
 set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
 set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
 
+set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true $obj
+
 # set the current impl run
 current_run -implementation [get_runs impl_1]
 catch {
@@ -729,7 +731,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
 
 set list_projs [get_projects -quiet]
 if { $list_projs eq "" } {
-  create_project VNA_XDMA VNA_XDMA_PROJ -part xc7a100tfgg484-2
+  create_project VNA_XDMA_PROJ VNA_XDMA_PROJ -part xc7a100tfgg484-2
   set_property target_language Verilog [current_project]
   set_property simulator_language Verilog [current_project]
 }