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PciVnaEmul
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PciE
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hierarchy.txt

hierarchy.txt 2.4 KB
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  1.  xilinx_pcie_2_1_ep_7x
    2. 

  2.  |
    3. 

  3.  |--pcie1234_support
    4. 

  4.  |  |--pcie1234_pipe_clock                                      
    5. 

  5.  |  |--pcie1234 (Core Top level module Generated by Vivado in synth directory)
    6. 

  6.  |     |--pcie_7x_v3_3_14_top (Static Top level file) 
    7. 

  7.  |        |--pcie_7x_v3_3_14_core_top
    8. 

  8.  |           |
    9. 

  9.  |           |--pcie1234_pcie_top
    10. 

  10.  |           |  |
    11. 

  11.  |           |  |--pcie1234_axi_basic_top
    12. 

  12.  |           |  |  |
    13. 

  13.  |           |  |  |--pcie1234_axi_basic_rx
    14. 

  14.  |           |  |  |  |
    15. 

  15.  |           |  |  |  |--pcie1234_axi_basic_rx_pipeline
    16. 

  16.  |           |  |  |  |--pcie1234_axi_basic_rx_null_gen
    17. 

  17.  |           |  |  |
    18. 

  18.  |           |  |  |--pcie1234_axi_basic_tx
    19. 

  19.  |           |  |     |
    20. 

  20.  |           |  |     |--pcie1234_axi_basic_tx_pipeline
    21. 

  21.  |           |  |     |--pcie1234_axi_basic_tx_thrtl_ctl
    22. 

  22.  |           |  |
    23. 

  23.  |           |  |--pcie1234_pcie_7x
    24. 

  24.  |           |  |  |
    25. 

  25.  |           |  |  |--pcie1234_pcie_bram_top_7x
    26. 

  26.  |           |  |  |  |
    27. 

  27.  |           |  |  |  |--pcie1234_pcie_brams_7x (an instance each for Rx & Tx)
    28. 

  28.  |           |  |  |     |
    29. 

  29.  |           |  |  |     |--pcie1234_pcie_bram_7x
    30. 

  30.  |           |  |  |
    31. 

  31.  |           |  |  |--PCIE_2_1 (Integrated Block Instance)
    32. 

  32.  |           |  |
    33. 

  33.  |           |  |--pcie1234_pcie_pipe_pipeline
    34. 

  34.  |           |     |
    35. 

  35.  |           |     |--pcie1234_pcie_pipe_misc
    36. 

  36.  |           |     |--pcie1234_pcie_pipe_lane (per lane)
    37. 

  37.  |           |
    38. 

  38.  |           |--pcie1234_gt_top
    39. 

  39.  |              |
    40. 

  40.  |              |--pcie1234_gt_rx_valid_filter
    41. 

  41.  |              |
    42. 

  42.  |              |--pcie1234_pipe_wrapper
    43. 

  43.  |              |  |
    44. 

  44.  |              |  |--pcie1234_pipe_reset
    45. 

  45.  |              |  |--pcie1234_qpll_reset
    46. 

  46.  |              |  |--pcie1234_pipe_user
    47. 

  47.  |              |  |--pcie1234_pipe_rate
    48. 

  48.  |              |  |--pcie1234_pipe_sync
    49. 

  49.  |              |  |--pcie1234_pipe_drp
    50. 

  50.  |              |  |--pcie1234_pipe_eq
    51. 

  51.  |              |  |  |--pcie1234_rxeq_scan
    52. 

  52.  |              |  |  |
    53. 

  53.  |              |  |--pcie1234_gt_common
    54. 

  54.  |              |  |  |--pcie1234_qpll_drp
    55. 

  55.  |              |  |  |--pcie1234_qpll_wrapper
    56. 

  56.  |              |  |
    57. 

  57.  |              |  |--pcie1234_gt_wrapper
    58. 

  58.  |
    59. 

  59.  |--pcie_app_7x (PIO design, in example_design directory)
    60. 

  60.     |
    61. 

  61.     |--PIO
    62. 

  62.        |
    63. 

  63.        |--PIO_EP
    64. 

  64.        |  |
    65. 

  65.        |  |--PIO_EP_MEM_ACCESS
    66. 

  66.        |  |  |
    67. 

  67.        |  |  |--EP_MEM
    68. 

  68.        |  |     |
    69. 

  69.        |  |     |--RAMB36
    70. 

  70.        |  |
    71. 

  71.        |  |--PIO_RX_ENGINE
    72. 

  72.        |  |--PIO_TX_ENGINE
    73. 

  73.        |
    74. 

  74.        |--PIO_TO_CTRL
    75.