Изменения в топ файле. Много изменений при переходе с 4 на 2 порта

S5443_M/S5443.ip_user_files/ip/MeasDataFifo/MeasDataFifo_stub.v

@@ -0,0 +1,27 @@
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+// Date        : Wed May  3 12:25:17 2023
+// Host        : DESKTOP-E4ROCGJ running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v
+// Design      : MeasDataFifo
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7s25csga324-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "fifo_generator_v13_2_5,Vivado 2020.2" *)
+module MeasDataFifo(clk, srst, din, wr_en, rd_en, dout, full, empty)
+/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[255:0],wr_en,rd_en,dout[255:0],full,empty" */;
+  input clk;
+  input srst;
+  input [255:0]din;
+  input wr_en;
+  input rd_en;
+  output [255:0]dout;
+  output full;
+  output empty;
+endmodule

S5443_M/S5443.ip_user_files/ip/MeasDataFifo/MeasDataFifo_stub.vhdl

@@ -0,0 +1,37 @@
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+-- Date        : Wed May  3 12:25:17 2023
+-- Host        : DESKTOP-E4ROCGJ running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               c:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.vhdl
+-- Design      : MeasDataFifo
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7s25csga324-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity MeasDataFifo is
+  Port ( 
+    clk : in STD_LOGIC;
+    srst : in STD_LOGIC;
+    din : in STD_LOGIC_VECTOR ( 255 downto 0 );
+    wr_en : in STD_LOGIC;
+    rd_en : in STD_LOGIC;
+    dout : out STD_LOGIC_VECTOR ( 255 downto 0 );
+    full : out STD_LOGIC;
+    empty : out STD_LOGIC
+  );
+
+end MeasDataFifo;
+
+architecture stub of MeasDataFifo is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,srst,din[255:0],wr_en,rd_en,dout[255:0],full,empty";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "fifo_generator_v13_2_5,Vivado 2020.2";
+begin
+end;

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
@@ -96,7 +96,7 @@ map_setup_file()
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   else
-    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/activehdl"
+    lib_map_path="C:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.cache/compile_simlib/activehdl"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/activehdl/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/ies/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
@@ -98,7 +98,7 @@ copy_setup_file()
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   else
-    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/modelsim"
+    lib_map_path="C:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.cache/compile_simlib/modelsim"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/modelsim/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
@@ -105,7 +105,7 @@ copy_setup_file()
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   else
-    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/questa"
+    lib_map_path="C:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.cache/compile_simlib/questa"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/questa/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 
@@ -96,7 +96,7 @@ map_setup_file()
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
   else
-    lib_map_path="C:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_M/S5443.cache/compile_simlib/riviera"
+    lib_map_path="C:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.cache/compile_simlib/riviera"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/riviera/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/vcs/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xcelium/file_info.txt

@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
-xpm_memory.sv,systemverilog,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
+xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,
 MeasDataFifo_sim_netlist.v,verilog,xil_defaultlib,../../../../S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_sim_netlist.v,
 glbl.v,Verilog,xil_defaultlib,glbl.v

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/MeasDataFifo.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 03 12:02:59 +0700 2023
+# Generated by Vivado on Wed May 03 12:25:18 +0700 2023
 # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
 #
 # Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 

S5443_M/S5443.ip_user_files/sim_scripts/MeasDataFifo/xsim/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 03 12:02:59 +0700 2023
+# Generated by export_simulation on Wed May 03 12:25:18 +0700 2023
 #
 ################################################################################
 

S5443_M/S5443.srcs/constrs_1/new/S5243Top.xdc

@@ -261,6 +261,9 @@ set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh1_o]
 set_property PACKAGE_PIN V15 [get_ports DitherCtrlCh2_o]
 set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh2_o]
 
+set_property PACKAGE_PIN M1 [get_ports DspReadyForRx_i]
+set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRx_i]
+
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Sck_i_IBUF]
 
@@ -879,7 +882,6 @@ set_property MARK_DEBUG false [get_nets ExternalDspInterface/MeasDataFifoInst/fu
 set_property MARK_DEBUG false [get_nets ExternalDspInterface/MeasDataFifoInst/PpiBusy_i]
 set_property MARK_DEBUG false [get_nets ExternalDspInterface/MeasDataFifoInst/emptyFlag]
 set_property MARK_DEBUG false [get_nets ExternalDspInterface/MeasDataPpiOut/LpOutStart_i]
-set_property MARK_DEBUG false [get_nets InternalDsp/MeasEnd_o]
 set_property MARK_DEBUG false [get_nets ExternalDspInterface/MeasDataFifoInst/MeasDataVal_o]
 
 
@@ -940,7 +942,6 @@ set_property MARK_DEBUG false [get_nets {adc1ChT1Data[1]}]
 set_property MARK_DEBUG false [get_nets {adc1ChT1Data[7]}]
 set_property MARK_DEBUG false [get_nets {adc1ChT1Data[9]}]
 
-set_property MARK_DEBUG false [get_nets {adc1ImR1[22]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[12]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[4]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[17]}]
@@ -952,15 +953,12 @@ set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[13]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[20]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[5]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[19]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[9]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[24]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[7]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[15]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[26]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[0]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[14]}]
 set_property MARK_DEBUG false [get_nets InternalDsp/MeasDataRdy_o]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[18]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[13]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[9]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[4]}]
@@ -968,21 +966,15 @@ set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[26]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[12]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[13]}]
-set_property MARK_DEBUG false [get_nets InternalDsp/StartMeas_i]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[1]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[28]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[0]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[18]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[5]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[8]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[5]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[30]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/WindPointsNum_i[2]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[22]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[4]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[15]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[27]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[31]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[2]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[8]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[3]}]
@@ -990,8 +982,6 @@ set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[
 set_property MARK_DEBUG false [get_nets InternalDsp/MeasCtrlModule/measWindEnd]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[17]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[21]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[6]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[19]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[3]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[6]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[22]}]
@@ -1000,7 +990,6 @@ set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCo
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[19]}]
 set_property MARK_DEBUG false [get_nets InternalDsp/EndMeas_o]
 set_property MARK_DEBUG false [get_nets ExternalDspInterface/MeasDataFifoInst/MeasDataVal_i]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[17]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[10]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[8]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[11]}]
@@ -1008,54 +997,36 @@ set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[8]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[18]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[22]}]
 set_property MARK_DEBUG false [get_nets InternalDsp/MeasWind_o]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[4]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[8]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[7]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[10]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[31]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/WindPointsNum_i[1]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[14]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[7]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[16]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[29]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[11]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[2]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[5]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[14]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[15]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/WindPointsNum_i[0]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[9]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[21]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[23]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[6]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[14]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[16]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[26]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[12]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[0]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[29]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[6]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[20]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[23]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[11]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[12]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[25]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[7]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[10]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[4]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[20]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[18]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[9]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[21]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[0]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[7]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[1]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[11]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[28]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[1]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[3]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[5]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[13]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[21]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[30]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCosValues[2]}]
@@ -1063,7 +1034,6 @@ set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[1]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[3]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[12]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[0]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[1]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[9]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[23]}]
@@ -1074,7 +1044,6 @@ set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/tukeyFirstCo
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[2]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[11]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/measCtrlReg[23]}]
-set_property MARK_DEBUG false [get_nets {adc1ImR1[20]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[2]}]
 set_property MARK_DEBUG false [get_nets {LpOutData_o_OBUF[15]}]
 set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/pNumCnt_reg[15]}]
@@ -1195,5 +1164,106 @@ set_property MARK_DEBUG false [get_nets trigForIntTrig2]
 set_property MARK_DEBUG false [get_nets {PGen[1].PulseGenMux/IntTrig2_i}]
 set_property MARK_DEBUG false [get_nets MeasTrigMux/MuxOut_o]
 set_property MARK_DEBUG false [get_nets MeasStartEventGenInst/measTrigPos]
-set_property MARK_DEBUG false [get_nets InternalDsp/StartMeasDsp_i]
 set_property MARK_DEBUG false [get_nets IntTrig2GenInst/StartMeasDsp_i]
+
+
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[11]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[25]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[9]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[2]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[21]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[0]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[3]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[9]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[30]}]
+set_property MARK_DEBUG false [get_nets InternalDsp/StartMeasDsp_i]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[0]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[4]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[5]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[11]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[5]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[20]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[30]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[7]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[15]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[23]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[29]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[31]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[20]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[30]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[23]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[24]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[1]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[3]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[21]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[10]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[22]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[29]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[1]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[9]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[17]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[27]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[8]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[10]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[16]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[28]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[3]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[13]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[31]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[4]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[5]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[19]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[10]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[12]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[16]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[6]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[20]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[26]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[8]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[28]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[22]}]
+set_property MARK_DEBUG false [get_nets gclk_BUFG]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[6]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[12]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[15]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[4]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[7]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[18]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[21]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[13]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[16]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[24]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[26]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[26]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[8]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[28]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[31]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[17]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[19]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[25]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[29]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[12]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[18]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[23]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[15]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[0]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[1]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[27]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[25]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[6]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[27]}]
+set_property MARK_DEBUG false [get_nets InternalDsp/MeasEnd_o]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[14]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[22]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[14]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[18]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[7]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[13]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[19]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[2]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[2]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/measNumReg[24]}]
+set_property MARK_DEBUG false [get_nets InternalDsp/StartMeas_i]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[14]}]
+set_property MARK_DEBUG false [get_nets {InternalDsp/MeasCtrlModule/measCnt_reg[17]}]
+set_property MARK_DEBUG false [get_nets {adc1ImR1[11]}]

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.xci

@@ -504,7 +504,7 @@
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7s25</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csga225</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csga324</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">VERILOG</spirit:configurableElementValue>

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v

@@ -1,13 +1,13 @@
 // Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-// Date        : Wed Sep 14 10:24:19 2022
-// Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub -rename_top MeasDataFifo -prefix
-//               MeasDataFifo_ MeasDataFifo_stub.v
+// Date        : Wed May  3 12:25:17 2023
+// Host        : DESKTOP-E4ROCGJ running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               c:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v
 // Design      : MeasDataFifo
 // Purpose     : Stub declaration of top-level module interface
-// Device      : xc7s25csga225-2
+// Device      : xc7s25csga324-2
 // --------------------------------------------------------------------------------
 
 // This empty module with port declaration file causes synthesis tools to infer a black box for IP.

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.vhdl

@@ -1,13 +1,13 @@
 -- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+-- Date        : Wed May  3 12:25:17 2023
+-- Host        : DESKTOP-E4ROCGJ running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               c:/Users/work/Desktop/S5243PM_REPO/S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.vhdl
 -- Design      : MeasDataFifo
 -- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7s25csga324-2
 -- --------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

S5443_M/S5443.srcs/sources_1/new/S5243Top.v

@@ -120,7 +120,6 @@ module	S5243Top
 	
 	//fpga-dsp signals
 	input	StartMeas_i,		//"high"- start meas, "low"-stop meas
-	//output	StartMeas_o,
 	output	EndMeas_o,
 	
 	output	TimersClk_o,
@@ -133,20 +132,17 @@ module	S5243Top
 	output	DspTrigIn_o,		//Trig To DSP
 	
 	//overload lines
-	//input	OverloadS_i,
 	output	Overload_o,
 	
 	//modulation & active port selection
 	
 	output	[1:0]	PortSel_o,		//управление модулятором через ключ 
-	//output	[3:0]	PortSelDir_o,	//управление направлением двунаправленного буффера
 	
 	//mod out line
 	output	Mod_o,
 	
 	//gain lines
-	inout	SensEnM_io,
-	//output	StartMeasDsp_o,
+	input	DspReadyForRx_i,
 	output	[ChNum-1:0]	AmpEn_o,	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
 	
 	///test port for testbench
@@ -263,10 +259,6 @@ module	S5243Top
 	wire	[ChNum-1:0]	ampEnNewStates;
 	wire	[ChNum-1:0]	sensEn;
 	
-	// wire	sensEnAll	=	(gainCtrl[0])?	((|sensEn)|sensEnReg):1'b0;
-	reg		sensEnReg;
-	wire	sensEnNeg	=	(sensEnReg&!SensEnM_io);
-	
 	wire	[ChNum-1:0]	gainManual;
 	wire	[ChNum-1:0]	gainAutoEn;
 	
@@ -527,12 +519,8 @@ module	S5243Top
 	assign	Adc1InitRst_o	=	adcCtrl[0];
 	assign	Adc2InitRst_o	=	adcCtrl[0];
 	
-	// assign	Led_o	=	ledReg	&(adc1ImT1|adc1ReT1|adc1ImR1|adc1ReR1|adc2ImT2|adc2ReT2|adc2ImR2|adc2ReR2);
-	// assign	Led_o	=	ledReg	|(|ampEnNewStates);
 	assign	Led_o	=	ledReg	|(|ampEnNewStates);
 	
-	//assign	StartMeas_o	=	startMeasEvent;
-	
 	assign	EndMeas_o	=	stopMeas|stopMeasR; //stretching pulse for 1 more clk period
 	
 	assign	gainLowThresholdBus		[ChNum-4]	=	gainLowThreshT1;
@@ -550,17 +538,11 @@ module	S5243Top
 	assign	AmpEn_o	[1]	=	~ampEnNewStates[0];	
 	assign	AmpEn_o	[0]	=	~ampEnNewStates[1];		
 	
-	// assign	AmpEn_o	[3]	=	pulseBus[PGenNum-1];	
-	// assign	AmpEn_o	[2]	=	pulseBus[PGenNum-1];	
-	// assign	AmpEn_o	[1]	=	pulseBus[PGenNum-1];	
-	// assign	AmpEn_o	[0]	=	pulseBus[PGenNum-1];	
-	
-	assign	Overload_o	=	overCtrlR/*||OverloadS_i*/;
+	assign	Overload_o	=	overCtrlR;
 
 	assign	Mod_o	=	fastMod;
 	
 	assign	PortSel_o		=	~modKeyCtrl[1:0];
-	//assign	PortSelDir_o	=	4'd15;
 	
 	assign	Trig6to1Dir_o	[0]	=	!measCtrl[16];
 	assign	Trig6to1Dir_o	[1]	=	!measCtrl[17];
@@ -576,8 +558,6 @@ module	S5243Top
 	assign	Trig6to1_io	[4]	=	(measCtrl[20])	?	1'bz:extPortsMuxedOut[4];	//1 - in, 0 - out
 	assign	Trig6to1_io	[5]	=	(measCtrl[21])	?	1'bz:extPortsMuxedOut[5];	//1 - in, 0 - out
 
-	//assign	SensEnM_io	=	(|sensEn)?	1'b0:1'bz;
-	//assign	StartMeasDsp_o	=	StartMeas_i;
 //================================================================================
 //  CODING
 //================================================================================
@@ -587,20 +567,11 @@ always	@(posedge	gclk)	begin	//stretching pulse
 	stopMeasR	<=	stopMeas;
 end
 
-always	@(posedge	gclk)	begin	//stretching pulse
-	sensEnReg	<=	SensEnM_io;
-end
 
 //--------------------------------------------------------------------------------
 //	Data Receiving Interface
 //--------------------------------------------------------------------------------
 
-/*IBUF iob_50m_in
-(
-	.I    			(Clk_i),
-	.O         		(gclk)
-);*/
-
 IBUFDS 
 #(
 	.DIFF_TERM		("FALSE")
@@ -690,6 +661,8 @@ ExternalDspInterface
 	.Clk_i				(gclk),
 	.Rst_i				(initRst),
 	.OscWind_i			(oscWind),
+	.StartMeasDsp_i		(startMeasSync),
+	.DspReadyForRx_i	(DspReadyForRx_i),
 	.MeasNum_i			({measNum2[7:0],measNum1}),
 
 	.Mosi_i				(Mosi_i),
@@ -1395,7 +1368,7 @@ SampleStrobeMux
 
 	.DspTrigOut_i	(1'b0),
 	.DspStartCmd_i	(1'b0),
-	.IntTrig_i		(1'b0),
+	.IntTrig_i		(intTrig1),
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(pulseBus),
 	.ExtPortsBus_i	(Trig6to1_io),