Модуль генерации синуса и косинуса переписан табличным методом.

S5443_M/S5443.srcs/sources_1/new/InternalDsp/InternalDsp.v

@@ -35,7 +35,8 @@ module InternalDsp
 	parameter	CmdDataRegWith		=	24,
 	parameter	IntermediateWidth	=	18,
 	parameter	CorrAdcDataWidth	=	20,
-	parameter	AccWidth			=	80
+	parameter	AccWidth			=	80,
+	parameter	[8:0]	MaxAddr		=	9'h190
 )
 (
 	input	wire	Clk_i,
@@ -142,6 +143,27 @@ module InternalDsp
 	
 	wire	[WindNcoPhIncWidth-1:0]	ncoPhInc = {ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg};
 	
+	reg		[8:0]	memAddrFirstTone;
+	wire	[8:0]	memAddrNextFirstTone;
+	wire	[8:0]	memAddrNext_pFirstTone;									//аргументы для расчета следующего значения
+	wire	[9:0]	memAddrNext_mFirstTone;									//аргументы для расчета следующего значения
+	
+	reg		[8:0]	memAddrSecondTone;
+	wire	[8:0]	memAddrNextSecondTone;
+	wire	[8:0]	memAddrNext_pSecondTone;									//аргументы для расчета следующего значения
+	wire	[9:0]	memAddrNext_mSecondTone;									//аргументы для расчета следующего значения
+	
+	wire	[8:0]	addrStepFirstTone	=	9'h50;
+	wire	[8:0]	addrStepSecondTone	=	9'h64;
+	
+	wire	[35:0]	firstToneSinCosValues;
+	wire	[35:0]	secondToneSinCosValues;
+	
+	wire	[17:0]	sinFirstTone	=	firstToneSinCosValues [35:18];			//выделяем из вычитаных данных, значение Cos
+	wire	[17:0]	cosFirstTone	=	firstToneSinCosValues [17:0];			//выделяем из вычитаных данных, значение Sin
+	
+	wire	[17:0]	sinSecondTone	=	secondToneSinCosValues [35:18];			//выделяем из вычитаных данных, значение Cos
+	wire	[17:0]	cosSecondTone	=	secondToneSinCosValues [17:0];			//выделяем из вычитаных данных, значение Sin
 //================================================================================
 //  ASSIGNMENTS
 
@@ -185,6 +207,13 @@ module InternalDsp
 	
 	assign	CalModeDone_o	=	&calDone;
 	
+	assign	memAddrNextFirstTone		=	!memAddrNext_mFirstTone[9]	?	memAddrNext_mFirstTone	:	memAddrNext_pFirstTone;
+	assign	memAddrNext_pFirstTone	=	memAddrFirstTone	+ addrStepFirstTone;
+	assign	memAddrNext_mFirstTone	=	memAddrFirstTone	+ addrStepFirstTone - MaxAddr;
+	
+	assign	memAddrNextSecondTone		=	!memAddrNext_mSecondTone[9]	?	memAddrNext_mSecondTone	:	memAddrNext_pSecondTone;
+	assign	memAddrNext_pSecondTone	=	memAddrSecondTone	+ addrStepSecondTone;
+	assign	memAddrNext_mSecondTone	=	memAddrSecondTone	+ addrStepSecondTone - MaxAddr;
 //================================================================================
 //  INSTANTIATIONS
 
@@ -336,6 +365,36 @@ ncoSecondTone
 	.Val_o		()
 );
 
+always 	@(posedge Clk_i) begin
+	if	(!Rst_i)	begin
+		memAddrFirstTone	<=	memAddrNextFirstTone;
+	end	else	begin
+		memAddrFirstTone	<=	9'b0;
+	end
+end
+
+always 	@(posedge Clk_i) begin
+	if	(!Rst_i)	begin
+		memAddrSecondTone	<=	memAddrNextSecondTone;
+	end	else	begin
+		memAddrSecondTone	<=	9'b0;
+	end
+end
+	
+blk_mem_gen_0 sinCosMemFirstTone
+(
+	.clka	(Clk_i),    // input wire clka
+	.addra	(memAddrFirstTone),  // input wire [8 : 0] addra
+	.douta	(firstToneSinCosValues)  // output wire [35 : 0] douta
+);
+
+blk_mem_gen_0 sinCosMemSecondTone
+(
+	.clka	(Clk_i),    // input wire clka
+	.addra	(memAddrSecondTone),  // input wire [8 : 0] addra
+	.douta	(secondToneSinCosValues)  // output wire [35 : 0] douta
+);
+
 ComplPrng
 #(
 	.DataPrngWidth	(8),
@@ -399,8 +458,11 @@ generate
 			.AverageNoizeLvl_i	(averageNoizeLvl),
 			.AdcData_i			(gatedAdcDataBus[g]),
 			.Wind_i				(wind),
-			.NcoSin_i			(ncoSinFirstTone),
-			.NcoCos_i			(ncoCosFirstTone),	
+			// .NcoSin_i			(ncoSinFirstTone),
+			// .NcoCos_i			(ncoCosFirstTone),
+			
+			.NcoSin_i			(sinFirstTone),
+			.NcoCos_i			(cosFirstTone),	
 			.NormCoef_i			(windNormCoef),
 
 			.CorrResultIm_o		(resultImBus[g]),
@@ -430,8 +492,11 @@ generate
 			.AverageNoizeLvl_i	(averageNoizeLvl),
 			.AdcData_i			(gatedAdcDataBus[g]),
 			.Wind_i				(wind),
-			.NcoSin_i			(ncoSinSecondTone),
-			.NcoCos_i			(ncoCosSecondTone),	
+			// .NcoSin_i			(ncoSinSecondTone),
+			// .NcoCos_i			(ncoCosSecondTone),	
+			
+			.NcoSin_i			(sinSecondTone),
+			.NcoCos_i			(cosSecondTone),	
 			.NormCoef_i			(windNormCoef),
 
 			.CorrResultIm_o		(resultImBus[g+2]),

S5443_M/S5443.srcs/sources_1/new/InternalDsp/sincoscalues.coe

@@ -0,0 +1,402 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+011111111111111111000000000000000000,
+011111111111101111000000100000001010,
+011111111110111111000001000000010101,
+011111111101101110000001100000011110,
+011111111011111101000010000000100110,
+011111111001101011000010100000101011,
+011111110110111010000011000000101110,
+011111110011101000000011100000101111,
+011111101111110110000100000000101011,
+011111101011100100000100100000100100,
+011111100110110010000101000000011000,
+011111100001100000000101100000000111,
+011111011011101110000101111111110000,
+011111010101011100000110011111010011,
+011111001110101011000110111110110000,
+011111000111011010000111011110000110,
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+011100111101000101001101100111111111,
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+000001100000011110011111111101101110,
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+000000000000000000011111111111111111,
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+111101111111011010100000000100000011,
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+011111011011101110111010000000010000,
+011111100001100000111010011111111001,
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+011111101011100100111011011111011100,
+011111101111110110111011111111010101,
+011111110011101000111100011111010001,
+011111110110111010111100111111010010,
+011111111001101011111101011111010101,
+011111111011111101111101111111011010,
+011111111101101110111110011111100010,
+011111111110111111111110111111101011,
+011111111111101111111111011111110110;

S5443_M/S5443.srcs/sources_1/new/S5443TopPulseProfileTb.v

@@ -277,9 +277,10 @@ ncoInst
 );
 
 
-S5443Top MasterFpga 
+S5243Top MasterFpga 
 (
-	.Clk_i				(Clk50),
+	.ClkP_i				(Clk50),
+	.ClkN_i				(~Clk50),
 	.Led_o				(),
 //------------------------------------------	
     .Adc1FclkP_i		(),		
@@ -308,11 +309,11 @@ S5443Top MasterFpga
     .Adc2DataDb1P_i		(1'b1),
     .Adc2DataDb1N_i		(1'b0),
 //------------------------------------------
-	.AdcInitMosi_o		(),
-	.AdcInitClk_o		(),			
+	// .AdcInitMosi_o		(),
+	// .AdcInitClk_o		(),			
 	.Adc1InitCs_o		(),
 	.Adc2InitCs_o		(),
-	.AdcInitRst_o		(),
+	// .AdcInitRst_o		(),
 //------------------------------------------	
 	
 	.Mosi_i				(mosi_i),
@@ -325,7 +326,7 @@ S5443Top MasterFpga
 	
 	//fpga-dsp signals
 	.StartMeas_i		(startCalcCmdReg),
-	.StartMeasEvent_o	(startMeasS),
+	// .StartMeasEvent_o	(startMeasS),
 	.EndMeas_o			(endMeas),
 	.TimersClk_o		(),
 	
@@ -335,11 +336,11 @@ S5443Top MasterFpga
 	.DspTrigOut_i		(Clk41),				//Trig from DSP
 	.DspTrigIn_o		(),				//Trig To DSP
 	
-	.OverloadS_i		(1'b0),
+	// .OverloadS_i		(1'b0),
 	.Overload_o			(),
 	
 	.PortSel_o			(),
-	.PortSelDir_o		(),
+	// .PortSelDir_o		(),
 	
 	//mod out line
 	
@@ -347,7 +348,7 @@ S5443Top MasterFpga
 	
 	//gain lines
 	.DspReadyForRx_i		(1'b0),
-	.DspReadyForRxToFpgaS_o	(),
+	// .DspReadyForRxToFpgaS_o	(),
 	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
 	.AdcData_i				(sin_value[17-:14])
 	// .AdcData_i			(Data_i)