Merge branch 'S5243_merge_200MHz' into S5243

S5443_M/S5443.srcs/sources_1/new/Clk200Gen.v

@@ -4,7 +4,7 @@ module Clk200Gen
     input	Rst_i,
 	output	Clk200_o,
 	output	Clk10Timers_o,
-	output	Clk100_o,
+	output	Clk150_o,
 	
 	output	Locked_o
 );
@@ -24,7 +24,7 @@ PLLE2_ADV #(
       	.CLKOUT1_DIVIDE		(120),
       	.CLKOUT1_DUTY_CYCLE	(0.5),
       	.CLKOUT1_PHASE		(0.0),
-      	.CLKOUT2_DIVIDE		(8),
+      	.CLKOUT2_DIVIDE		(6),
       	.CLKOUT2_DUTY_CYCLE	(0.5),
       	.CLKOUT2_PHASE		(0.0),
       	.CLKOUT3_DIVIDE		(120),
@@ -43,7 +43,7 @@ CommonPll (
       	.CLKFBOUT		(ClkFb),
       	.CLKOUT0		(rx_mmcmout_200),
       	.CLKOUT1		(rx_mmcmout_10),
-      	.CLKOUT2		(rx_mmcmout_100),
+      	.CLKOUT2		(rx_mmcmout_150),
       	.CLKOUT3		(),
       	.CLKOUT4		(),
       	.CLKOUT5		(),
@@ -68,7 +68,7 @@ BUFG	bufg_mmcm_Fb (.I(ClkFb), .O(rxFb)) ;
 
 BUFG	ctrlClk200 (.I(rx_mmcmout_200), .O(Clk200_o)) ;
 BUFG	ctrlClk10 (.I(rx_mmcmout_10), .O(Clk10Timers_o)) ;
-BUFG	ctrlClk100 (.I(rx_mmcmout_100), .O(Clk100_o)) ;
+BUFG	ctrlClk150 (.I(rx_mmcmout_150), .O(Clk150_o)) ;
 
 endmodule
 

S5443_M/S5443.srcs/sources_1/new/FftDataFiltering/DecimFilterWrapper.v

@@ -167,8 +167,8 @@ ncoInst
 	.Clk_i		(Clk_i),
 	.Rst_i		(Rst_i),
 	.Val_i		(1'b1),
-	// .PhaseInc_i	({ifFtwHReg[0+:32-24],ifFtwLReg}),
-	.PhaseInc_i	(32'h3eb851eb),
+	.PhaseInc_i	({ifFtwHReg[0+:32-24],ifFtwLReg}),
+	// .PhaseInc_i	(32'h3eb851eb),
 	.WindVal_i	(1'b1),
 	.WinType_i	(),
 	.Wind_o		(),

S5443_M/S5443.srcs/sources_1/new/InternalDsp/InternalDsp.v

@@ -102,7 +102,6 @@ module InternalDsp
 	wire	[NcoWidth-1:0]	ncoSin;
 	
 	wire	[CorrAdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
-	// wire	[AdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	adcDataBusExt	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	gatedAdcDataBus	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	calAdcData		[ChNum-1:0];
@@ -133,11 +132,6 @@ module InternalDsp
 	
 	wire	[31:0]	windArg;
 	
-	// wire	[CorrAdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-4]:{CorrAdcDataWidth{1'b0}};
-	// wire	[CorrAdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-3]:{CorrAdcDataWidth{1'b0}};
-	// wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-2]:{CorrAdcDataWidth{1'b0}};
-	// wire	[CorrAdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-1]:{CorrAdcDataWidth{1'b0}};	
-	
 	wire	[CorrAdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-4]:{CorrAdcDataWidth{1'b0}};
 	wire	[CorrAdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-3]:{CorrAdcDataWidth{1'b0}};
 	wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-2]:{CorrAdcDataWidth{1'b0}};
@@ -147,12 +141,6 @@ module InternalDsp
 	
 //================================================================================
 //  ASSIGNMENTS
-	
-	
-	// assign	adcDataBus	[ChNum-1]	=	Adc2ChT2Data_i;
-	// assign	adcDataBus	[ChNum-2]	=	Adc2ChR2Data_i;
-	// assign	adcDataBus	[ChNum-3]	=	Adc1ChR1Data_i;
-	// assign	adcDataBus	[ChNum-4]	=	Adc1ChT1Data_i;
 
 	assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
 	assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
@@ -284,8 +272,7 @@ Win_calc	WinCalcInst
 	.MeasWind_i		(measWind),
 	.win_value_i	(windArg),
 	.win_type_i		(measCtrlReg[2:0]),
-	.win_o			(wind),
-	.sinWin_o		(sinwind)
+	.win_o			(wind)
 );
 
 
@@ -297,7 +284,7 @@ CordicNco
 	.ODatWidth	(NcoWidth),
 	.PhIncWidth	(WindNcoPhIncWidth),
 	.IterNum	(15),
-	.EnSinN		(1)
+	.EnSinN		(0)
 )
 ncoInst
 (
@@ -321,11 +308,9 @@ ComplPrng
 )
 ComplPrngAdderInst
 (
-	// .Data_i	(calAdcData[g]),
 	.Clk_i	(Clk_i),
 	.Rst_i	(Rst_i),
 
-	// .DataAndPrng_o	(adcDataBusExt[g]),
 	.PrngData_o		(prngData)
 );
 
@@ -342,7 +327,6 @@ generate
 	
 		AdcCalibration 
 		#(	
-			// .AccNum			(32),
 			.AccNum			(2097152),
 			.AdcDataWidth	(CorrAdcDataWidth)
 		)
@@ -351,7 +335,6 @@ generate
 			.Clk_i					(Clk_i),
 			.Rst_i					(Rst_i),
 			.CalModeEn_i			(CalModeEn_i),
-			// .AdcData_i				(adcDataBusExt[g]),
 			.AdcData_i				(adcDataBus[g]),
 			
 			.CalDone_o				(calDone[g]),

S5443_M/S5443.srcs/sources_1/new/InternalDsp/Win_calc.v

@@ -29,14 +29,13 @@ module Win_calc	(
 	input	[1:0]	TukeyCtrl_i,
 	input	[31:0]	win_value_i,
 	input	[2:0]	win_type_i,	
-	output	signed [17:0]	win_o,
-	output	reg	signed [17:0]	sinWin_o
+	output	signed [17:0]	win_o
 );
 //================================================================================
 //  REG/WIRE
 //================================================================================
 	
-	reg			[2:0]	calc_cycle;
+	reg			[3:0]	calc_cycle;
 	reg	signed	[17:0]	a1;		
 	reg signed	[17:0]	b; 	
 	reg signed	[17:0]	c1;
@@ -137,30 +136,36 @@ always	@(*)	begin
 	end
 end
 
-always	@(posedge	wind_clk)	begin
+always	@(negedge	wind_clk)	begin
 	if	(!reset_i)	begin
+		// if	(MeasWind_i)	begin
 			case	(calc_cycle)
-				3'd0: 	
+				4'd1: 	
 						begin
 							a1	<=	A5;
 							c1	<=	A4;
 							c2	<=	A3;
-							// b	<=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
 							b	<=	bCurr;
 						end
 						
-				3'd1:	
+				4'd2:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	A2;
 							c2	<=	A1;
 						end
-				3'd2:	
+				4'd3:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	b;
 						end
 			endcase
+		// end	else	begin
+			// a1	<=	18'b0;
+			// c1	<=	18'b0;
+			// c2	<=	18'b0;
+			// b	<=	18'b0;
+		// end
 	end	else	begin
 		a1	<=	18'b0;
 		c1	<=	18'b0;
@@ -168,6 +173,33 @@ always	@(posedge	wind_clk)	begin
 		b	<=	18'b0;
 	end
 end
+
+// always	@(*)	begin
+	// if	(!reset_i)	begin
+		// if	(MeasWind_i)	begin
+			// case	(calc_cycle)
+				// 3'd1: 	
+						// begin
+							// a1	=	A5;
+							// c1	=	A4;
+							// c2	=	A3;
+							// b	=	bCurr;
+						// end
+			// endcase
+		// end	else	begin
+			// a1	=	18'b0;
+			// c1	=	18'b0;
+			// c2	=	18'b0;
+			// b	=	18'b0;
+		// end
+	// end	else	begin
+		// a1	=	18'b0;
+		// c1	=	18'b0;
+		// c2	=	18'b0;
+		// b	=	18'b0;
+	// end
+// end
+
 		
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
@@ -210,13 +242,17 @@ end
 
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
-			if	(calc_cycle	!=	3'd2)	begin
-				calc_cycle	<=	calc_cycle	+	3'd1;
+		if	(MeasWind_i)	begin
+			if	(calc_cycle	!=	4'd3)	begin
+				calc_cycle	<=	calc_cycle	+	4'd1;
 			end	else	begin
-				calc_cycle	<=	3'd0;
+				calc_cycle	<=	4'd0;
 			end
+		end	else	begin
+			calc_cycle	<=	4'd0;
+		end
 	end	else	begin
-		calc_cycle	<=	3'd0;
+		calc_cycle	<=	4'd0;
 	end
 end
 
@@ -248,9 +284,9 @@ DSP48E1 #(
       .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
       .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
       .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
-      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
+      .PREG(1)                          // Number of pipeline stages for P (0 or 1)
    )
-DSP48E1_1inst (
+FirstStage (
       // Cascade: 30-bit (each) output: Cascade Ports
       .ACOUT(),                   // 30-bit output: A port cascade output
       .BCOUT(),                   // 18-bit output: B port cascade output
@@ -274,8 +310,8 @@ DSP48E1_1inst (
       // Control: 4-bit (each) input: Control Inputs/Status Bits
       .ALUMODE(4'b0000),               // 4-bit input: ALU control input
       .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
-      .CLK(1'b0),                       // 1-bit input: Clock input
-      // .CLK(wind_clk),                       // 1-bit input: Clock input
+      // .CLK(1'b0),                       // 1-bit input: Clock input
+      .CLK(wind_clk),                       // 1-bit input: Clock input
       .INMODE(5'b00000),                 // 5-bit input: INMODE control input
       .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
       // Data: 30-bit (each) input: Data Ports
@@ -296,7 +332,7 @@ DSP48E1_1inst (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
+      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
       .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
@@ -306,8 +342,8 @@ DSP48E1_1inst (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
-      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
+      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
+      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
 );
    
 DSP48E1 #(
@@ -340,7 +376,7 @@ DSP48E1 #(
       .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
       .PREG(0)                          // Number of pipeline stages for P (0 or 1)
    )
-DSP48E1_2inst (
+SecondStage (
       // Cascade: 30-bit (each) output: Cascade Ports
       .ACOUT(),                   // 30-bit output: A port cascade output
       .BCOUT(),                   // 18-bit output: B port cascade output
@@ -386,8 +422,8 @@ DSP48E1_2inst (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
-      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
+      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
+      .CEP(1'b0),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
       .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
@@ -396,8 +432,8 @@ DSP48E1_2inst (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
-      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
+      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
+      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
 );
 
 endmodule

S5443_M/S5443.srcs/sources_1/new/Math/FpCustomMultiplier.v

@@ -1,8 +1,17 @@
-module FpCustomMultiplier # (
+module FpCustomMultiplier 
+# (
 	parameter	ManWidth	=	16,
 	parameter	ExpWidth	=	6
 )
-(Rst_i,Clk_i,A_i,B_i,Nd_i,Result_o,ResultValid_o);	
+(
+	Rst_i,
+	Clk_i,
+	A_i,
+	B_i,
+	Nd_i,
+	Result_o,
+	ResultValid_o
+);	
 
 	localparam	InOutWidth	=	1+ExpWidth+ManWidth;
 	

S5443_M/S5443.srcs/sources_1/new/Math/MultModule.v

@@ -39,10 +39,12 @@ module	MultModule
 
 //================================================================================
 //  REG/WIRE
-	wire	signed	[IfNcoOutWidth-1:0]	adcDataCompl	=	{AdcData_i,4'b0};
+	reg	signed	[IfNcoOutWidth-1:0]	adcDataCompl;
+	reg	signed	[IfNcoOutWidth-1:0]	sinReg;
+	reg	signed	[IfNcoOutWidth-1:0]	cosReg;
 	
-	reg	[MultDataWidth-1:0]	AdcSinReg;
-	reg	[MultDataWidth-1:0]	AdcCosReg;
+	reg	signed	[MultDataWidth-1:0]	AdcSinReg;
+	reg	signed	[MultDataWidth-1:0]	AdcCosReg;
 //================================================================================
 //  ASSIGNMENTS
 	assign	AdcSin_o	=	AdcSinReg;
@@ -51,8 +53,20 @@ module	MultModule
 //  CODING
 	always	@(posedge	Clk_i)	begin
 		if	(!Rst_i)	begin
-			AdcSinReg	<=	adcDataCompl*Sin_i;
-			AdcCosReg	<=	adcDataCompl*Cos_i;
+			adcDataCompl	<=	{AdcData_i,4'b0};
+			sinReg	<=	Sin_i;
+			cosReg	<=	Cos_i;
+		end	else	begin
+			adcDataCompl	<=	0;
+			sinReg	<=	0;
+			cosReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			AdcSinReg	<=	adcDataCompl*sinReg;
+			AdcCosReg	<=	adcDataCompl*cosReg;
 		end	else	begin
 			AdcSinReg	<=	{MultDataWidth{1'b0}};
 			AdcCosReg	<=	{MultDataWidth{1'b0}};

S5443_M/S5443.srcs/sources_1/new/S5243Top.v

@@ -269,7 +269,7 @@ module	S5243Top
 	reg	[31:0]	testCnt;
 
 	wire	refClk;
-	wire	Clk100_o;
+	wire	windClk150;
 	
 	wire	measWind;
 	
@@ -591,7 +591,7 @@ Clk200Gen	Clk200Gen
     .Rst_i			(initRst),
 	.Clk200_o		(refClk),
 	.Clk10Timers_o	(TimersClk_o),
-	.Clk100_o		(Clk100_o),
+	.Clk150_o		(windClk150),
 	
 	.Locked_o		(Locked200)
 );
@@ -757,7 +757,7 @@ InternalDsp
 InternalDsp
 (
 	.Clk_i				(gclk),
-	.WindCalcClk_i		(Clk100_o),
+	.WindCalcClk_i		(windClk150),
 	.Rst_i				(initRst),
 	.NcoRst_i			(ncoRst),
 	.OscWind_o			(oscWind),

S5443_M/S5443.srcs/sources_1/new/S5443Top.v

@@ -165,8 +165,7 @@ module	S5443Top
 	wire	gatingPulse;
 	wire	sampleStrobe;
 	wire	[ChNum-1:0]	measStartBus;
-	// wire	measStart	=	&measStartBus;
-	reg		measStart;
+	wire	measStart;
 	
 	//spi signals for adc init
 	wire	adcInitRst;
@@ -269,7 +268,7 @@ module	S5443Top
 	reg	[31:0]	testCnt;
 
 	wire	refClk;
-	wire	Clk100_o;
+	wire	windClk150;
 	
 	wire	measWind;
 	
@@ -558,9 +557,7 @@ module	S5443Top
 	assign	Trig6to1Dir_o	[5]	=	!measCtrl[21];
 	
 	assign	Trig6to1_io	[0]	=	(measCtrl[16])	?	1'bz:extPortsMuxedOut[0];	//1 - in, 0 - out
-	// assign	Trig6to1_io	[0]	=	(measCtrl[16])	?	1'bz:LpOutFs_o;	//1 - in, 0 - out
 	assign	Trig6to1_io	[1]	=	(measCtrl[17])	?	1'bz:extPortsMuxedOut[1];	//1 - in, 0 - out
-	// assign	Trig6to1_io	[1]	=	(measCtrl[17])	?	1'bz:LpOutFs_o;	//1 - in, 0 - out
 	assign	Trig6to1_io	[2]	=	(measCtrl[18])	?	1'bz:extPortsMuxedOut[2];	//1 - in, 0 - out
 	assign	Trig6to1_io	[3]	=	(measCtrl[19])	?	1'bz:extPortsMuxedOut[3];	//1 - in, 0 - out
 	assign	Trig6to1_io	[4]	=	(measCtrl[20])	?	1'bz:extPortsMuxedOut[4];	//1 - in, 0 - out
@@ -607,13 +604,13 @@ IBUF iob_50m_in
 	.O         		(gclk)
 );
 	
-Clk200Gen	Clk200Gen 
+Clk200Gen	ClocksGenerator 
 (
     .Clk_i			(gclk),
     .Rst_i			(initRst),
 	.Clk200_o		(refClk),
 	.Clk10Timers_o	(TimersClk_o),
-	.Clk100_o		(Clk100_o),
+	.Clk150_o		(windClk150),
 	
 	.Locked_o		(Locked200)
 );
@@ -704,17 +701,7 @@ ExternalDspInterface
 	.Adc1ChT1Data_i		(adc1ChT1Data),	
 	.Adc1ChR1Data_i		(adc1ChR1Data),	
 	.Adc2ChR2Data_i		(adc2ChR2Data),	
-	.Adc2ChT2Data_i		(adc2ChT2Data),	
-
-	// .Adc1ChT1Data_i		(AdcData_i),	
-	// .Adc1ChR1Data_i		(AdcData_i),	
-	// .Adc2ChR2Data_i		(AdcData_i),	
-	// .Adc2ChT2Data_i		(AdcData_i),	
-	
-	// .Adc1ChT1Data_i		(14'h1fff),	
-	// .Adc1ChR1Data_i		(14'h257f),	
-	// .Adc2ChR2Data_i		(14'h1001),	
-	// .Adc2ChT2Data_i		(14'h25f8),	
+	.Adc2ChT2Data_i		(adc2ChT2Data),		
 	
 	.Mosi_o				(adcInitMosi),
 	.Sck_o				(adcInitSck),
@@ -771,7 +758,7 @@ InternalDsp
 InternalDsp
 (
 	.Clk_i					(gclk),
-	.WindCalcClk_i			(Clk100_o),
+	.WindCalcClk_i			(windClk150),
 	.Rst_i					(initRst),
 	.NcoRst_i				(ncoRst),
 	.OscWind_o				(oscWind),
@@ -1010,7 +997,6 @@ generate
 		.NcoCos_i			(ncoCos),
 		
 		.AdcData_i			(adcDataBus[g]),
-		// .AdcData_i			(AdcData_i),
 		
 		.GainLowThreshold_i	(gainLowThresholdBus[g]),
 		.GainHighThreshold_i(gainHighThresholdBus[g]),
@@ -1024,60 +1010,18 @@ generate
 	end
 endgenerate
 
-always	@(*)	begin
-	if	(!initRst)	begin
-		case(gainAutoEn)
-			4'd0:	begin
-						measStart	=	&measStartBus;
-					end
-			4'd1:	begin
-						measStart	=	measStartBus[0];
-					end
-			4'd2:	begin
-						measStart	=	measStartBus[1];
-					end
-			4'd3:	begin
-						measStart	=	measStartBus[0]&measStartBus[1];
-					end
-			4'd4:	begin
-						measStart	=	&measStartBus[2];
-					end
-			4'd5:	begin
-						measStart	=	measStartBus[0]&measStartBus[2];
-					end
-			4'd6:	begin
-						measStart	=	measStartBus[1]&measStartBus[2];
-					end
-			4'd7:	begin
-						measStart	=	measStartBus[0]&measStartBus[1]&measStartBus[2];
-					end
-			4'd8:	begin
-						measStart	=	measStartBus[3];
-					end
-			4'd9:	begin
-						measStart	=	measStartBus[0]&measStartBus[3];
-					end
-			4'd10:	begin
-						measStart	=	measStartBus[1]&measStartBus[3];
-					end
-			4'd11:	begin
-						measStart	=	measStartBus[0]&measStartBus[1]&measStartBus[3];
-					end
-			4'd12:	begin
-						measStart	=	measStartBus[2]&measStartBus[3];
-					end
-			4'd13:	begin
-						measStart	=	measStartBus[0]&measStartBus[2]&measStartBus[3];
-					end
-			4'd14:	begin
-						measStart	=	measStartBus[1]&measStartBus[2]&measStartBus[3];
-					end
-			4'd15:	begin
-						measStart	=	&measStartBus;
-					end		
-		endcase
-	end
-end
+StartAfterGainSel	
+#(	
+	.ChNum	(ChNum)
+)	
+StartAfterGainSelInst
+(
+	.Rst_i			(initRst),
+	.GainCtrl_i		(gainAutoEn),
+	.MeasStart_i	(measStartBus),
+	
+	.MeasStart_o	(measStart)
+);
 //--------------------------------------------------------------------------------
 //	Trig TO/FROM DSP	
 //--------------------------------------------------------------------------------	
@@ -1183,7 +1127,6 @@ MeasStartEventGen	IntTrig2GenInst
 	.Clk_i				(gclk),
 	
 	.MeasTrig_i			(trigForIntTrig2),
-	// .StartMeasDsp_i		(startMeasEvent),
 	.StartMeasDsp_i		(intTrig1),
 	
 	.StartMeasEvent_o	(),
@@ -1240,7 +1183,8 @@ PulseGen
 )
 PulseGenerator
 (
-	.Rst_i			(initRst|pGenRst[j]|pGenMeasRst[j]),
+	// .Rst_i			(initRst|pGenRst[j]|pGenMeasRst[j]),
+	.Rst_i			(initRst|pGenMeasRst[j]),
 	.Clk_i			(gclk),
 	.EnPulse_i		(pgMuxedOut[j]),
 	

S5443_M/S5443.srcs/sources_1/new/S5443TopPulseProfileTb.v

@@ -72,8 +72,8 @@ module S5443TopPulseProfileTb;
 	//COMMANDS	FOR REG_MAP
 	parameter	[31:0]	MeasCmdBypass	=	{8'h11,8'h0,8'h63,8'h1};
 	parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h63,7'h5,1'b1};
-	// parameter	[31:0]	MeasCmd 		=	{8'h11,8'h0,8'h53,8'h0};
-	parameter	[31:0]	MeasCmd =	{8'h11,8'h3e,8'h63,8'h0};
+	parameter	[31:0]	MeasCmd 		=	{8'h11,8'h0,8'h53,8'h0};
+	// parameter	[31:0]	MeasCmd =	{8'h11,8'h3e,8'h63,8'h0};
 	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};
 	parameter	[31:0]	SensCtrlCmd =	{1'b0,27'h0,4'b1};
 	// parameter	[31:0]	DitherCmd 	= {8'h0E,24'h100192};

S5443_M/S5443.srcs/sources_1/new/StartAfterGainSel.v

@@ -0,0 +1,103 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:  
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module StartAfterGainSel
+#(	
+	parameter	ChNum	=	4
+)	
+(
+	input	Rst_i,	
+	input	[ChNum-1:0]	MeasStart_i,
+	input	[ChNum-1:0]	GainCtrl_i,
+	
+	output	MeasStart_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+
+//================================================================================
+//  REG/WIRE
+	reg	measStart;
+//================================================================================
+//  ASSIGNMENTS
+	assign	MeasStart_o	=	measStart;
+//================================================================================
+//  CODING
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		case(GainCtrl_i)
+			4'd0:	begin
+						measStart	=	&MeasStart_i;
+					end
+			4'd1:	begin
+						measStart	=	MeasStart_i[0];
+					end
+			4'd2:	begin
+						measStart	=	MeasStart_i[1];
+					end
+			4'd3:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1];
+					end
+			4'd4:	begin
+						measStart	=	&MeasStart_i[2];
+					end
+			4'd5:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[2];
+					end
+			4'd6:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[2];
+					end
+			4'd7:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[2];
+					end
+			4'd8:	begin
+						measStart	=	MeasStart_i[3];
+					end
+			4'd9:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[3];
+					end
+			4'd10:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[3];
+					end
+			4'd11:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[3];
+					end
+			4'd12:	begin
+						measStart	=	MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd13:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd14:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd15:	begin
+						measStart	=	&MeasStart_i;
+					end		
+			default:	begin
+							measStart	=	&MeasStart_i;
+						end
+		endcase
+	end
+end
+
+endmodule

S5443_S/S5443.srcs/sources_1/new/Clk200Gen.v

@@ -4,7 +4,7 @@ module Clk200Gen
     input	Rst_i,
 	output	Clk200_o,
 	output	Clk10Timers_o,
-	output	Clk100_o,
+	output	Clk150_o,
 	
 	output	Locked_o
 );
@@ -24,10 +24,10 @@ PLLE2_ADV #(
       	.CLKOUT1_DIVIDE		(120),
       	.CLKOUT1_DUTY_CYCLE	(0.5),
       	.CLKOUT1_PHASE		(0.0),
-      	.CLKOUT2_DIVIDE		(8),
+      	.CLKOUT2_DIVIDE		(6),
       	.CLKOUT2_DUTY_CYCLE	(0.5),
       	.CLKOUT2_PHASE		(0.0),
-      	.CLKOUT3_DIVIDE		(7),
+      	.CLKOUT3_DIVIDE		(120),
       	.CLKOUT3_DUTY_CYCLE	(0.5),
       	.CLKOUT3_PHASE		(0.0),
       	.CLKOUT4_DIVIDE		(7),
@@ -43,7 +43,7 @@ CommonPll (
       	.CLKFBOUT		(ClkFb),
       	.CLKOUT0		(rx_mmcmout_200),
       	.CLKOUT1		(rx_mmcmout_10),
-      	.CLKOUT2		(rx_mmcmout_100),
+      	.CLKOUT2		(rx_mmcmout_150),
       	.CLKOUT3		(),
       	.CLKOUT4		(),
       	.CLKOUT5		(),
@@ -68,7 +68,7 @@ BUFG	bufg_mmcm_Fb (.I(ClkFb), .O(rxFb)) ;
 
 BUFG	ctrlClk200 (.I(rx_mmcmout_200), .O(Clk200_o)) ;
 BUFG	ctrlClk10 (.I(rx_mmcmout_10), .O(Clk10Timers_o)) ;
-BUFG	ctrlClk100 (.I(rx_mmcmout_100), .O(Clk100_o)) ;
+BUFG	ctrlClk150 (.I(rx_mmcmout_150), .O(Clk150_o)) ;
 
 endmodule
 

S5443_S/S5443.srcs/sources_1/new/FftDataFiltering/DecimFilterWrapper.v

@@ -23,7 +23,7 @@ module	DecimFilterWrapper
 	parameter	AdcDataWidth		=	14,
 	parameter	N	=	4,
 	parameter	M	=	1,
-	parameter	FilteredDataWidth	=	21,
+	parameter	FilteredDataWidth	=	29,
 	parameter	FirOutDataWidth		=	48,
 	parameter	FirOutCutBit		=	42
 )
@@ -38,8 +38,8 @@ module	DecimFilterWrapper
 	
 	input	signed	[AdcDataWidth-1:0]	AdcData_i,
 	
-	output	signed	[AdcDataWidth+1:0]	FilteredAdcDataI_o,
-	output	signed	[AdcDataWidth+1:0]	FilteredAdcDataQ_o,
+	output	signed	[16-1:0]	FilteredAdcDataI_o,
+	output	signed	[16-1:0]	FilteredAdcDataQ_o,
 	output	FilteredDataVal_o
 );
 //================================================================================
@@ -48,7 +48,9 @@ module	DecimFilterWrapper
 	wire	signed	[FilteredDataWidth-1:0]	decimDataI;
 	wire	signed	[FilteredDataWidth-1:0]	decimDataQ;
 	wire	decimDataValI;
+	reg		decimDataValIR;
 	wire	decimDataValQ;
+	reg		decimDataValQR;
 	
 	wire	signed	[FirOutDataWidth-1:0]	firDataOut;
 	wire	firDataOutVal;
@@ -56,25 +58,93 @@ module	DecimFilterWrapper
 	wire	[AdcDataWidth-1:0]	ncoCos;
 	wire	[AdcDataWidth-1:0]	ncoSin;
 	
-	wire	[FilteredDataWidth-1:0]	adcSinResult;
+	wire	[AdcDataWidth-1:0]	adcSinResult;
 	wire	adcSinVal;
-	wire	[FilteredDataWidth-1:0]	adcCosResult;
+	wire	[AdcDataWidth-1:0]	adcCosResult;
 	wire	adcCosVal;
 	
 	reg		[24-1:0]	ifFtwLReg;
 	reg		[24-1:0]	ifFtwHReg;
+	
+	reg		[15:0]	outDataI;
+	reg		[15:0]	outDataQ;
+	
+	localparam	maxWidthForR2	=	5'd18;	//msb for R = 2;
+	localparam	maxWidthForR3	=	5'd21;	//msb for R = 3;
+	localparam	maxWidthForR4	=	5'd22;	//msb for R = 4;
+	localparam	maxWidthForR5	=	5'd24;	//msb for R = 5;
+	localparam	maxWidthForR6	=	5'd25;	//msb for R = 6;
+	localparam	maxWidthForR7	=	5'd26;	//msb for R = 7;
+	// localparam	maxWidthForR8	=	5'd26;	//msb for R = 8;
+	// localparam	maxWidthForR9	=	5'd27;	//msb for R = 9;
+	// localparam	maxWidthForR10	=	5'd28;	//msb for R = 10;
+	
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
 
-	assign	FilteredAdcDataI_o		=	decimDataI[FilteredDataWidth-1-:AdcDataWidth+2];
-	assign	FilteredAdcDataQ_o		=	decimDataQ[FilteredDataWidth-1-:AdcDataWidth+2];
-	assign	FilteredDataVal_o		=	decimDataValI&decimDataValQ;
-	
+	assign	FilteredAdcDataI_o	=	outDataI;
+	// assign	FilteredAdcDataI_o	=	decimDataI;
+	assign	FilteredAdcDataQ_o	=	outDataQ;
+	// assign	FilteredAdcDataQ_o	=	decimDataQ;
+	// assign	FilteredDataVal_o	=	decimDataValIR&decimDataValQR;
+	assign	FilteredDataVal_o	=	decimDataValI&decimDataValQ;
+
+
+// {{14{AdcData_i[AdcDataWidth-1]}},AdcData_i}
+
 //================================================================================
 //	CODING
 //================================================================================
 
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case(DecimFactor_i)
+			3'd2:	begin
+						outDataI	<=	decimDataI[maxWidthForR2-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR2-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+			3'd3:	begin
+						outDataI	<=	decimDataI[maxWidthForR3-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR3-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+			3'd4:	begin
+						outDataI	<=	decimDataI[maxWidthForR4-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR4-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+			3'd5:	begin
+						outDataI	<=	decimDataI[maxWidthForR5-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR5-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+			3'd6:	begin
+						outDataI	<=	decimDataI[maxWidthForR6-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR6-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+			3'd7:	begin
+						outDataI	<=	decimDataI[maxWidthForR7-:16];
+						outDataQ	<=	decimDataQ[maxWidthForR7-:16];
+						decimDataValIR	<=	decimDataValI;
+						decimDataValQR	<=	decimDataValQ;
+					end
+		endcase
+	end	else	begin
+		outDataI	<=	16'd0;
+		outDataQ	<=	16'd0;
+		decimDataValIR	<=	1'b0;
+		decimDataValQR	<=	1'b0;
+	end
+end
+
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
 		ifFtwLReg	<=	IfFtwL_i;
@@ -98,6 +168,7 @@ ncoInst
 	.Rst_i		(Rst_i),
 	.Val_i		(1'b1),
 	.PhaseInc_i	({ifFtwHReg[0+:32-24],ifFtwLReg}),
+	// .PhaseInc_i	(32'h3eb851eb),
 	.WindVal_i	(1'b1),
 	.WinType_i	(),
 	.Wind_o		(),
@@ -110,7 +181,7 @@ SimpleMult
 #(	
 	.FactorAWidth	(AdcDataWidth),
 	.FactorBWidth	(AdcDataWidth),
-	.OutputWidth	(FilteredDataWidth)
+	.OutputWidth	(AdcDataWidth)
 )
 AdcNcoSinMult	
 (
@@ -119,6 +190,7 @@ AdcNcoSinMult
 	.Val_i		(1'b1),
 	.FactorA_i	(ncoSin),
 	.FactorB_i	(AdcData_i),	
+	// .FactorB_i	(ncoSin),	
 	.Result_o	(adcSinResult),
 	.ResultVal_o(adcSinVal)
 );
@@ -127,7 +199,7 @@ SimpleMult
 #(	
 	.FactorAWidth	(AdcDataWidth),
 	.FactorBWidth	(AdcDataWidth),
-	.OutputWidth	(FilteredDataWidth)
+	.OutputWidth	(AdcDataWidth)
 )
 AdcNcoCosMult	
 (
@@ -136,6 +208,7 @@ AdcNcoCosMult
 	.Val_i		(1'b1),
 	.FactorA_i	(ncoCos),
 	.FactorB_i	(AdcData_i),
+	// .FactorB_i	(ncoSin),
 	.Result_o	(adcCosResult),
 	.ResultVal_o(adcCosVal)
 );
@@ -153,8 +226,8 @@ cicFilterInstI
 	.Clk_i			(Clk_i),
 	.Rst_i			(Rst_i),
 	.DecimFactor_i	(DecimFactor_i),
-	// .Data_i			({{7{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
-	.Data_i			(adcCosResult),
+	.Data_i			({{15{adcCosResult[AdcDataWidth-1]}},adcCosResult}),
+	// .Data_i			({{15{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
 	.DataNd_i		(OscWind_i),
 	.Data_o			(decimDataI),
 	.DataValid_o	(decimDataValI)
@@ -173,9 +246,8 @@ cicFilterInstQ
 	.Clk_i			(Clk_i),
 	.Rst_i			(Rst_i),
 	.DecimFactor_i	(DecimFactor_i),
-	// .Data_i			(AdcData_i),
-	// .Data_i			({{7{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
-	.Data_i			(adcSinResult),
+	.Data_i			({{15{adcSinResult[AdcDataWidth-1]}},adcSinResult}),
+	// .Data_i			({{15{AdcData_i[AdcDataWidth-1]}},AdcData_i}),
 	.DataNd_i		(OscWind_i),
 	.Data_o			(decimDataQ),
 	.DataValid_o	(decimDataValQ)

S5443_S/S5443.srcs/sources_1/new/InternalDsp/InternalDsp.v

@@ -102,7 +102,6 @@ module InternalDsp
 	wire	[NcoWidth-1:0]	ncoSin;
 	
 	wire	[CorrAdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
-	// wire	[AdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	adcDataBusExt	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	gatedAdcDataBus	[ChNum-1:0];
 	wire	[CorrAdcDataWidth-1:0]	calAdcData		[ChNum-1:0];
@@ -133,11 +132,6 @@ module InternalDsp
 	
 	wire	[31:0]	windArg;
 	
-	// wire	[CorrAdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-4]:{CorrAdcDataWidth{1'b0}};
-	// wire	[CorrAdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-3]:{CorrAdcDataWidth{1'b0}};
-	// wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-2]:{CorrAdcDataWidth{1'b0}};
-	// wire	[CorrAdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	calAdcData[ChNum-1]:{CorrAdcDataWidth{1'b0}};	
-	
 	wire	[CorrAdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-4]:{CorrAdcDataWidth{1'b0}};
 	wire	[CorrAdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-3]:{CorrAdcDataWidth{1'b0}};
 	wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-2]:{CorrAdcDataWidth{1'b0}};
@@ -147,11 +141,6 @@ module InternalDsp
 	
 //================================================================================
 //  ASSIGNMENTS
-	
-	// assign	adcDataBus	[ChNum-1]	=	Adc2ChT2Data_i;
-	// assign	adcDataBus	[ChNum-2]	=	Adc2ChR2Data_i;
-	// assign	adcDataBus	[ChNum-3]	=	Adc1ChR1Data_i;
-	// assign	adcDataBus	[ChNum-4]	=	Adc1ChT1Data_i;
 
 	assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
 	assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
@@ -187,6 +176,7 @@ module InternalDsp
 	assign	MeasWind_o	=	measWind;
 	
 	assign	CalModeDone_o	=	&calDone;
+	
 //================================================================================
 //  INSTANTIATIONS
 
@@ -215,13 +205,6 @@ always	@(posedge	Clk_i)	begin
 	end 
 end
 
-// PseudoRandomGenerator	RandomGenInst
-// (
-	// .Rst_i	(Rst_i),
-	// .Clk_i	(Clk_i),
-	// .Data_o	()
-// );
-
 MeasCtrlModule	
 #(	
 	.WindPNumWidth	(WindPNumWidth)
@@ -289,8 +272,7 @@ Win_calc	WinCalcInst
 	.MeasWind_i		(measWind),
 	.win_value_i	(windArg),
 	.win_type_i		(measCtrlReg[2:0]),
-	.win_o			(wind),
-	.sinWin_o		(sinwind)
+	.win_o			(wind)
 );
 
 
@@ -314,11 +296,10 @@ ncoInst
 	.WinType_i	(),
 	.Wind_o		(),
 	.Sin_o		(ncoSin),
-	.Cos_o		(ncoCos),
+	.Cos_o		(ncoCos),	
 	.Val_o		()
 );
 
-
 ComplPrng
 #(
 	.DataPrngWidth	(8),
@@ -327,11 +308,9 @@ ComplPrng
 )
 ComplPrngAdderInst
 (
-	// .Data_i	(calAdcData[g]),
 	.Clk_i	(Clk_i),
 	.Rst_i	(Rst_i),
 
-	// .DataAndPrng_o	(adcDataBusExt[g]),
 	.PrngData_o		(prngData)
 );
 
@@ -348,7 +327,6 @@ generate
 	
 		AdcCalibration 
 		#(	
-			// .AccNum			(32),
 			.AccNum			(2097152),
 			.AdcDataWidth	(CorrAdcDataWidth)
 		)
@@ -357,7 +335,6 @@ generate
 			.Clk_i					(Clk_i),
 			.Rst_i					(Rst_i),
 			.CalModeEn_i			(CalModeEn_i),
-			// .AdcData_i				(adcDataBusExt[g]),
 			.AdcData_i				(adcDataBus[g]),
 			
 			.CalDone_o				(calDone[g]),
@@ -386,8 +363,8 @@ generate
 			.AverageNoizeLvl_i	(averageNoizeLvl),
 			.AdcData_i			(gatedAdcDataBus[g]),
 			.Wind_i				(wind),
-			.NcoSin_i			(ncoCos),
-			.NcoCos_i			(ncoSin),	
+			.NcoSin_i			(ncoSin),
+			.NcoCos_i			(ncoCos),	
 			.NormCoef_i			(windNormCoef),
 
 			.CorrResultIm_o		(resultImBus[g]),

S5443_S/S5443.srcs/sources_1/new/InternalDsp/Win_calc.v

@@ -29,14 +29,13 @@ module Win_calc	(
 	input	[1:0]	TukeyCtrl_i,
 	input	[31:0]	win_value_i,
 	input	[2:0]	win_type_i,	
-	output	signed [17:0]	win_o,
-	output	reg	signed [17:0]	sinWin_o
+	output	signed [17:0]	win_o
 );
 //================================================================================
 //  REG/WIRE
 //================================================================================
 	
-	reg			[2:0]	calc_cycle;
+	reg			[3:0]	calc_cycle;
 	reg	signed	[17:0]	a1;		
 	reg signed	[17:0]	b; 	
 	reg signed	[17:0]	c1;
@@ -53,6 +52,7 @@ module Win_calc	(
 	reg	[35:0]	sinWindPow2;
 	
 	wire	sinFilterFlag	=	(filterCmd_i>=8'h54	&	filterCmd_i<=8'h62);
+	// wire	rectFilterFlag	=	(filterCmd_i>=8'h63	&	filterCmd_i!=8'h70)|filterCmd_i==8'h30;
 	wire	rectFilterFlag	=	(filterCmd_i>=8'h63	&	filterCmd_i!=8'h70);
 	
 	wire	[17:0]	bSin	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
@@ -136,30 +136,36 @@ always	@(*)	begin
 	end
 end
 
-always	@(posedge	wind_clk)	begin
+always	@(negedge	wind_clk)	begin
 	if	(!reset_i)	begin
+		// if	(MeasWind_i)	begin
 			case	(calc_cycle)
-				3'd0: 	
+				4'd1: 	
 						begin
 							a1	<=	A5;
 							c1	<=	A4;
 							c2	<=	A3;
-							// b	<=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
 							b	<=	bCurr;
 						end
 						
-				3'd1:	
+				4'd2:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	A2;
 							c2	<=	A1;
 						end
-				3'd2:	
+				4'd3:	
 						begin
 							a1	<=	p2[34:17];
 							c1	<=	b;
 						end
 			endcase
+		// end	else	begin
+			// a1	<=	18'b0;
+			// c1	<=	18'b0;
+			// c2	<=	18'b0;
+			// b	<=	18'b0;
+		// end
 	end	else	begin
 		a1	<=	18'b0;
 		c1	<=	18'b0;
@@ -167,6 +173,33 @@ always	@(posedge	wind_clk)	begin
 		b	<=	18'b0;
 	end
 end
+
+// always	@(*)	begin
+	// if	(!reset_i)	begin
+		// if	(MeasWind_i)	begin
+			// case	(calc_cycle)
+				// 3'd1: 	
+						// begin
+							// a1	=	A5;
+							// c1	=	A4;
+							// c2	=	A3;
+							// b	=	bCurr;
+						// end
+			// endcase
+		// end	else	begin
+			// a1	=	18'b0;
+			// c1	=	18'b0;
+			// c2	=	18'b0;
+			// b	=	18'b0;
+		// end
+	// end	else	begin
+		// a1	=	18'b0;
+		// c1	=	18'b0;
+		// c2	=	18'b0;
+		// b	=	18'b0;
+	// end
+// end
+
 		
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
@@ -209,13 +242,17 @@ end
 
 always	@(posedge	wind_clk)	begin
 	if	(!reset_i)	begin
-			if	(calc_cycle	!=	3'd2)	begin
-				calc_cycle	<=	calc_cycle	+	3'd1;
+		if	(MeasWind_i)	begin
+			if	(calc_cycle	!=	4'd3)	begin
+				calc_cycle	<=	calc_cycle	+	4'd1;
 			end	else	begin
-				calc_cycle	<=	3'd0;
+				calc_cycle	<=	4'd0;
 			end
+		end	else	begin
+			calc_cycle	<=	4'd0;
+		end
 	end	else	begin
-		calc_cycle	<=	3'd0;
+		calc_cycle	<=	4'd0;
 	end
 end
 
@@ -247,9 +284,9 @@ DSP48E1 #(
       .INMODEREG(0),                    // Number of pipeline stages for INMODE (0 or 1)
       .MREG(0),                         // Number of multiplier pipeline stages (0 or 1)
       .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
-      .PREG(0)                          // Number of pipeline stages for P (0 or 1)
+      .PREG(1)                          // Number of pipeline stages for P (0 or 1)
    )
-DSP48E1_1inst (
+FirstStage (
       // Cascade: 30-bit (each) output: Cascade Ports
       .ACOUT(),                   // 30-bit output: A port cascade output
       .BCOUT(),                   // 18-bit output: B port cascade output
@@ -273,8 +310,8 @@ DSP48E1_1inst (
       // Control: 4-bit (each) input: Control Inputs/Status Bits
       .ALUMODE(4'b0000),               // 4-bit input: ALU control input
       .CARRYINSEL(3'b000),         // 3-bit input: Carry select input
-      .CLK(1'b0),                       // 1-bit input: Clock input
-      // .CLK(wind_clk),                       // 1-bit input: Clock input
+      // .CLK(1'b0),                       // 1-bit input: Clock input
+      .CLK(wind_clk),                       // 1-bit input: Clock input
       .INMODE(5'b00000),                 // 5-bit input: INMODE control input
       .OPMODE(7'b0110101),                 // 7-bit input: Operation mode input
       // Data: 30-bit (each) input: Data Ports
@@ -295,7 +332,7 @@ DSP48E1_1inst (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
+      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
       .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
@@ -305,8 +342,8 @@ DSP48E1_1inst (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
-      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
+      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
+      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
 );
    
 DSP48E1 #(
@@ -339,7 +376,7 @@ DSP48E1 #(
       .OPMODEREG(0),                    // Number of pipeline stages for OPMODE (0 or 1)
       .PREG(0)                          // Number of pipeline stages for P (0 or 1)
    )
-DSP48E1_2inst (
+SecondStage (
       // Cascade: 30-bit (each) output: Cascade Ports
       .ACOUT(),                   // 30-bit output: A port cascade output
       .BCOUT(),                   // 18-bit output: B port cascade output
@@ -385,8 +422,8 @@ DSP48E1_2inst (
       .CECTRL(1'b1),                 // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
       .CED(1'b1),                       // 1-bit input: Clock enable input for DREG
       .CEINMODE(1'b1),             // 1-bit input: Clock enable input for INMODEREG
-      .CEM(1'b1),                       // 1-bit input: Clock enable input for MREG
-      .CEP(1'b1),                       // 1-bit input: Clock enable input for PREG
+      .CEM(1'b0),                       // 1-bit input: Clock enable input for MREG
+      .CEP(1'b0),                       // 1-bit input: Clock enable input for PREG
       .RSTA(1'b0),                     // 1-bit input: Reset input for AREG
       .RSTALLCARRYIN(1'b0),   // 1-bit input: Reset input for CARRYINREG
       .RSTALUMODE(1'b0),         // 1-bit input: Reset input for ALUMODEREG
@@ -395,8 +432,8 @@ DSP48E1_2inst (
       .RSTCTRL(1'b0),               // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
       .RSTD(1'b0),                     // 1-bit input: Reset input for DREG and ADREG
       .RSTINMODE(1'b0),           // 1-bit input: Reset input for INMODEREG
-      .RSTM(1'b0),                     // 1-bit input: Reset input for MREG
-      .RSTP(1'b0)                      // 1-bit input: Reset input for PREG
+      .RSTM(reset_i),                     // 1-bit input: Reset input for MREG
+      .RSTP(reset_i)                      // 1-bit input: Reset input for PREG
 );
 
 endmodule

S5443_S/S5443.srcs/sources_1/new/Math/FpCustomMultiplier.v

@@ -1,8 +1,17 @@
-module FpCustomMultiplier # (
+module FpCustomMultiplier 
+# (
 	parameter	ManWidth	=	16,
 	parameter	ExpWidth	=	6
 )
-(Rst_i,Clk_i,A_i,B_i,Nd_i,Result_o,ResultValid_o);	
+(
+	Rst_i,
+	Clk_i,
+	A_i,
+	B_i,
+	Nd_i,
+	Result_o,
+	ResultValid_o
+);	
 
 	localparam	InOutWidth	=	1+ExpWidth+ManWidth;
 	

S5443_S/S5443.srcs/sources_1/new/Math/MultModule.v

@@ -39,10 +39,12 @@ module	MultModule
 
 //================================================================================
 //  REG/WIRE
-	wire	signed	[IfNcoOutWidth-1:0]	adcDataCompl	=	{AdcData_i,4'b0};
+	reg	signed	[IfNcoOutWidth-1:0]	adcDataCompl;
+	reg	signed	[IfNcoOutWidth-1:0]	sinReg;
+	reg	signed	[IfNcoOutWidth-1:0]	cosReg;
 	
-	reg	[MultDataWidth-1:0]	AdcSinReg;
-	reg	[MultDataWidth-1:0]	AdcCosReg;
+	reg	signed	[MultDataWidth-1:0]	AdcSinReg;
+	reg	signed	[MultDataWidth-1:0]	AdcCosReg;
 //================================================================================
 //  ASSIGNMENTS
 	assign	AdcSin_o	=	AdcSinReg;
@@ -51,8 +53,20 @@ module	MultModule
 //  CODING
 	always	@(posedge	Clk_i)	begin
 		if	(!Rst_i)	begin
-			AdcSinReg	<=	adcDataCompl*Sin_i;
-			AdcCosReg	<=	adcDataCompl*Cos_i;
+			adcDataCompl	<=	{AdcData_i,4'b0};
+			sinReg	<=	Sin_i;
+			cosReg	<=	Cos_i;
+		end	else	begin
+			adcDataCompl	<=	0;
+			sinReg	<=	0;
+			cosReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			AdcSinReg	<=	adcDataCompl*sinReg;
+			AdcCosReg	<=	adcDataCompl*cosReg;
 		end	else	begin
 			AdcSinReg	<=	{MultDataWidth{1'b0}};
 			AdcCosReg	<=	{MultDataWidth{1'b0}};

S5443_S/S5443.srcs/sources_1/new/S5443Top.v

@@ -140,7 +140,7 @@ module	S5443Top
 	wire	gatingPulse;
 	wire	sampleStrobe;
 	wire	[ChNum-1:0]	measStartBus;
-	reg		measStart;
+	wire		measStart;
 	
 	//spi signals for adc init
 	wire	adcInitRst;
@@ -243,7 +243,7 @@ module	S5443Top
 	reg	[31:0]	testCnt;
 
 	wire	refClk;
-	wire	Clk100_o;
+	wire	windClk150;
 	
 	wire	measWind;
 	
@@ -538,13 +538,13 @@ IBUF iob_50m_in
 	.O         		(gclk)
 );
 	
-Clk200Gen	Clk200Gen 
+Clk200Gen	ClocksGenerator 
 (
     .Clk_i			(gclk),
     .Rst_i			(initRst),
 	.Clk200_o		(refClk),
 	.Clk10Timers_o	(TimersClk_o),
-	.Clk100_o		(Clk100_o),
+	.Clk150_o		(windClk150),
 	
 	.Locked_o		(Locked200)
 );
@@ -615,7 +615,6 @@ ExternalDspInterface
 	.Rst_i				(initRst),
 	.OscWind_i			(oscWind),
 	.StartMeasDsp_i		(startMeasSync),
-	// .DspReadyForRx_i	(dspReadyForRxReg),
 	.DspReadyForRx_i	(dspReadyForRxReg),
 	.MeasNum_i			({measNum2[7:0],measNum1}),
 	
@@ -635,16 +634,6 @@ ExternalDspInterface
 	.Adc1ChR1Data_i		(adc1ChR1Data),	
 	.Adc2ChR2Data_i		(adc2ChT2Data),	
 	.Adc2ChT2Data_i		(adc2ChR2Data),	
-
-	// .Adc1ChT1Data_i		(AdcData_i),	
-	// .Adc1ChR1Data_i		(AdcData_i),	
-	// .Adc2ChR2Data_i		(AdcData_i),	
-	// .Adc2ChT2Data_i		(AdcData_i),	
-	
-	// .Adc1ChT1Data_i		(14'h1fff),	
-	// .Adc1ChR1Data_i		(14'h257f),	
-	// .Adc2ChR2Data_i		(14'h1001),	
-	// .Adc2ChT2Data_i		(14'h25f8),	
 	
 	.Mosi_o				(adcInitMosi),
 	.Sck_o				(adcInitSck),
@@ -750,7 +739,7 @@ InternalDsp
 InternalDsp
 (
 	.Clk_i				(gclk),
-	.WindCalcClk_i		(Clk100_o),
+	.WindCalcClk_i		(windClk150),
 	.Rst_i				(initRst),
 	.NcoRst_i			(ncoRst),
 	.OscWind_o			(oscWind),
@@ -989,7 +978,6 @@ generate
 		.NcoCos_i			(ncoCos),
 		
 		.AdcData_i			(adcDataBus[g]),
-		// .AdcData_i			(AdcData_i),
 		
 		.GainLowThreshold_i	(gainLowThresholdBus[g]),
 		.GainHighThreshold_i(gainHighThresholdBus[g]),
@@ -1003,62 +991,18 @@ generate
 	end
 endgenerate
 
-always	@(*)	begin
-	if	(!initRst)	begin
-		case(gainAutoEn)
-			4'd0:	begin
-						measStart	=	&measStartBus;
-					end
-			4'd1:	begin
-						measStart	=	measStartBus[0];
-					end
-			4'd2:	begin
-						measStart	=	measStartBus[1];
-					end
-			4'd3:	begin
-						measStart	=	measStartBus[0]&measStartBus[1];
-					end
-			4'd4:	begin
-						measStart	=	&measStartBus[2];
-					end
-			4'd5:	begin
-						measStart	=	measStartBus[0]&measStartBus[2];
-					end
-			4'd6:	begin
-						measStart	=	measStartBus[1]&measStartBus[2];
-					end
-			4'd7:	begin
-						measStart	=	measStartBus[0]&measStartBus[1]&measStartBus[2];
-					end
-			4'd8:	begin
-						measStart	=	measStartBus[3];
-					end
-			4'd9:	begin
-						measStart	=	measStartBus[0]&measStartBus[3];
-					end
-			4'd10:	begin
-						measStart	=	measStartBus[1]&measStartBus[3];
-					end
-			4'd11:	begin
-						measStart	=	measStartBus[0]&measStartBus[1]&measStartBus[3];
-					end
-			4'd12:	begin
-						measStart	=	measStartBus[2]&measStartBus[3];
-					end
-			4'd13:	begin
-						measStart	=	measStartBus[0]&measStartBus[2]&measStartBus[3];
-					end
-			4'd14:	begin
-						measStart	=	measStartBus[1]&measStartBus[2]&measStartBus[3];
-					end
-			4'd15:	begin
-						measStart	=	&measStartBus;
-					end		
-		endcase
-	end
-end
-
-
+StartAfterGainSel	
+#(	
+	.ChNum	(ChNum)
+)	
+StartAfterGainSelInst
+(
+	.Rst_i			(initRst),
+	.GainCtrl_i		(gainAutoEn),
+	.MeasStart_i	(measStartBus),
+	
+	.MeasStart_o	(measStart)
+);
 
 //--------------------------------------------------------------------------------
 //	Dither Gen 
@@ -1123,7 +1067,8 @@ PulseGen
 )
 PulseGenerator
 (
-	.Rst_i			(initRst|pGenRst[j]|pGenMeasRst[j]),
+	//.Rst_i			(initRst|pGenRst[j]|pGenMeasRst[j]),
+	.Rst_i			(initRst|pGenMeasRst[j]),
 	.Clk_i			(gclk),
 	.EnPulse_i		(pgMuxedOut[j]),
 	

S5443_S/S5443.srcs/sources_1/new/StartAfterGainSel.v

@@ -0,0 +1,103 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:  
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module StartAfterGainSel
+#(	
+	parameter	ChNum	=	4
+)	
+(
+	input	Rst_i,	
+	input	[ChNum-1:0]	MeasStart_i,
+	input	[ChNum-1:0]	GainCtrl_i,
+	
+	output	MeasStart_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+
+//================================================================================
+//  REG/WIRE
+	reg	measStart;
+//================================================================================
+//  ASSIGNMENTS
+	assign	MeasStart_o	=	measStart;
+//================================================================================
+//  CODING
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		case(GainCtrl_i)
+			4'd0:	begin
+						measStart	=	&MeasStart_i;
+					end
+			4'd1:	begin
+						measStart	=	MeasStart_i[0];
+					end
+			4'd2:	begin
+						measStart	=	MeasStart_i[1];
+					end
+			4'd3:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1];
+					end
+			4'd4:	begin
+						measStart	=	&MeasStart_i[2];
+					end
+			4'd5:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[2];
+					end
+			4'd6:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[2];
+					end
+			4'd7:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[2];
+					end
+			4'd8:	begin
+						measStart	=	MeasStart_i[3];
+					end
+			4'd9:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[3];
+					end
+			4'd10:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[3];
+					end
+			4'd11:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[3];
+					end
+			4'd12:	begin
+						measStart	=	MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd13:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd14:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd15:	begin
+						measStart	=	&MeasStart_i;
+					end		
+			default:	begin
+							measStart	=	&MeasStart_i;
+						end
+		endcase
+	end
+end
+
+endmodule