FIFO для хранения результатов измерений увеличино до 4096. Добавлен механизм квитирования для отравки данных FPGA-DSP. Исправления ошибок. В режиме ContPulseProfile есть баг с количеством отправляемых точек (проверить режим SinglePulseProfile) отправляется 4001 точка вместо запрашиваемых 4000.

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v

@@ -1,7 +1,7 @@
 // Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-// Date        : Fri Nov 19 10:12:01 2021
+// Date        : Wed Sep 14 10:24:19 2022
 // Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
 // Command     : write_verilog -force -mode synth_stub -rename_top MeasDataFifo -prefix
 //               MeasDataFifo_ MeasDataFifo_stub.v

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.vhdl

@@ -1,7 +1,7 @@
 -- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+-- Date        : Wed Sep 14 10:24:19 2022
 -- Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
 -- Command     : write_vhdl -force -mode synth_stub -rename_top MeasDataFifo -prefix
 --               MeasDataFifo_ MeasDataFifo_stub.vhdl

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/sim/MeasDataFifo.v

@@ -85,7 +85,7 @@ output wire empty;
     .C_COMMON_CLOCK(1),
     .C_SELECT_XPM(0),
     .C_COUNT_TYPE(0),
-    .C_DATA_COUNT_WIDTH(10),
+    .C_DATA_COUNT_WIDTH(12),
     .C_DEFAULT_VALUE("BlankString"),
     .C_DIN_WIDTH(256),
     .C_DOUT_RST_VAL("0"),
@@ -117,17 +117,17 @@ output wire empty;
     .C_OVERFLOW_LOW(0),
     .C_PRELOAD_LATENCY(1),
     .C_PRELOAD_REGS(0),
-    .C_PRIM_FIFO_TYPE("1kx36"),
+    .C_PRIM_FIFO_TYPE("4kx9"),
     .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
     .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
     .C_PROG_EMPTY_TYPE(0),
-    .C_PROG_FULL_THRESH_ASSERT_VAL(1022),
-    .C_PROG_FULL_THRESH_NEGATE_VAL(1021),
+    .C_PROG_FULL_THRESH_ASSERT_VAL(4094),
+    .C_PROG_FULL_THRESH_NEGATE_VAL(4093),
     .C_PROG_FULL_TYPE(0),
-    .C_RD_DATA_COUNT_WIDTH(10),
-    .C_RD_DEPTH(1024),
+    .C_RD_DATA_COUNT_WIDTH(12),
+    .C_RD_DEPTH(4096),
     .C_RD_FREQ(1),
-    .C_RD_PNTR_WIDTH(10),
+    .C_RD_PNTR_WIDTH(12),
     .C_UNDERFLOW_LOW(0),
     .C_USE_DOUT_RST(1),
     .C_USE_ECC(0),
@@ -138,10 +138,10 @@ output wire empty;
     .C_USE_FWFT_DATA_COUNT(0),
     .C_VALID_LOW(0),
     .C_WR_ACK_LOW(0),
-    .C_WR_DATA_COUNT_WIDTH(10),
-    .C_WR_DEPTH(1024),
+    .C_WR_DATA_COUNT_WIDTH(12),
+    .C_WR_DEPTH(4096),
     .C_WR_FREQ(1),
-    .C_WR_PNTR_WIDTH(10),
+    .C_WR_PNTR_WIDTH(12),
     .C_WR_RESPONSE_LATENCY(1),
     .C_MSGON_VAL(1),
     .C_ENABLE_RST_SYNC(1),
@@ -297,12 +297,12 @@ output wire empty;
     .din(din),
     .wr_en(wr_en),
     .rd_en(rd_en),
-    .prog_empty_thresh(10'B0),
-    .prog_empty_thresh_assert(10'B0),
-    .prog_empty_thresh_negate(10'B0),
-    .prog_full_thresh(10'B0),
-    .prog_full_thresh_assert(10'B0),
-    .prog_full_thresh_negate(10'B0),
+    .prog_empty_thresh(12'B0),
+    .prog_empty_thresh_assert(12'B0),
+    .prog_empty_thresh_negate(12'B0),
+    .prog_full_thresh(12'B0),
+    .prog_full_thresh_assert(12'B0),
+    .prog_full_thresh_negate(12'B0),
     .int_clk(1'D0),
     .injectdbiterr(1'D0),
     .injectsbiterr(1'D0),

S5443_M/S5443.srcs/constrs_1/new/S5443Top.xdc

@@ -144,8 +144,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports StartMeas_i]
 set_property PACKAGE_PIN M8 [get_ports EndMeas_o]
 set_property IOSTANDARD LVCMOS33 [get_ports EndMeas_o]
 
-set_property PACKAGE_PIN R9 [get_ports StartMeas_o]
-set_property IOSTANDARD LVCMOS33 [get_ports StartMeas_o]
+set_property PACKAGE_PIN R9 [get_ports StartMeasEvent_o]
+set_property IOSTANDARD LVCMOS33 [get_ports StartMeasEvent_o]
 
 set_property PACKAGE_PIN L13 [get_ports TimersClk_o]
 set_property IOSTANDARD LVCMOS33 [get_ports TimersClk_o]
@@ -177,8 +177,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[2]}]
 set_property PACKAGE_PIN M4 [get_ports {PortSelDir_o[3]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {PortSelDir_o[3]}]
 
-set_property PACKAGE_PIN R7 [get_ports SensEnM_io]
-set_property IOSTANDARD LVCMOS33 [get_ports SensEnM_io]
+set_property PACKAGE_PIN R7 [get_ports DspReadyForRxToFpgaS_o]
+set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRxToFpgaS_o]
+
+set_property PACKAGE_PIN R5 [get_ports DspReadyForRx_i]
+set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRx_i]
 
 set_property PACKAGE_PIN P7 [get_ports StartMeasDsp_o]
 set_property IOSTANDARD LVCMOS33 [get_ports StartMeasDsp_o]
@@ -320,6 +323,14 @@ connect_debug_port u_ila_0/probe9 [get_nets [list {InternalDsp/adcDataBusExt[1][
 
 
 
+
+connect_debug_port u_ila_0/probe7 [get_nets [list MeasStartEventGenInst/measTrigPos]]
+connect_debug_port u_ila_0/probe9 [get_nets [list MeasStartEventGenInst/startMeasEvent_reg_i_2_n_0]]
+
+connect_debug_port u_ila_0/probe7 [get_nets [list StartMeas_o_OBUF]]
+
+connect_debug_port u_ila_0/probe5 [get_nets [list intTrig2]]
+
 create_debug_core u_ila_0 ila
 set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
 set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
@@ -332,44 +343,60 @@ set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
 set_property port_width 1 [get_debug_ports u_ila_0/clk]
 connect_debug_port u_ila_0/clk [get_nets [list gclk_BUFG]]
 set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
-set_property port_width 3 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {InitTrig2Mux/MuxCtrl_i[0]} {InitTrig2Mux/MuxCtrl_i[1]} {InitTrig2Mux/MuxCtrl_i[2]}]]
+set_property port_width 23 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {muxCtrl3[0]} {muxCtrl3[1]} {muxCtrl3[2]} {muxCtrl3[3]} {muxCtrl3[4]} {muxCtrl3[5]} {muxCtrl3[6]} {muxCtrl3[7]} {muxCtrl3[8]} {muxCtrl3[9]} {muxCtrl3[10]} {muxCtrl3[11]} {muxCtrl3[12]} {muxCtrl3[13]} {muxCtrl3[14]} {muxCtrl3[15]} {muxCtrl3[16]} {muxCtrl3[17]} {muxCtrl3[18]} {muxCtrl3[19]} {muxCtrl3[20]} {muxCtrl3[21]} {muxCtrl3[22]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
-set_property port_width 23 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {muxCtrl3[0]} {muxCtrl3[1]} {muxCtrl3[2]} {muxCtrl3[3]} {muxCtrl3[4]} {muxCtrl3[5]} {muxCtrl3[6]} {muxCtrl3[7]} {muxCtrl3[8]} {muxCtrl3[9]} {muxCtrl3[10]} {muxCtrl3[11]} {muxCtrl3[12]} {muxCtrl3[13]} {muxCtrl3[14]} {muxCtrl3[15]} {muxCtrl3[16]} {muxCtrl3[17]} {muxCtrl3[18]} {muxCtrl3[19]} {muxCtrl3[20]} {muxCtrl3[21]} {muxCtrl3[22]}]]
+set_property port_width 1 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {pulseBus[3]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
 set_property port_width 6 [get_debug_ports u_ila_0/probe2]
 connect_debug_port u_ila_0/probe2 [get_nets [list {pulseBus__0[0]} {pulseBus__0[1]} {pulseBus__0[2]} {pulseBus__0[4]} {pulseBus__0[5]} {pulseBus__0[6]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
-set_property port_width 1 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {pulseBus[3]}]]
+set_property port_width 3 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {InitTrig2Mux/MuxCtrl_i[0]} {InitTrig2Mux/MuxCtrl_i[1]} {InitTrig2Mux/MuxCtrl_i[2]}]]
 create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe4]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
 set_property port_width 1 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list measTrig]]
+connect_debug_port u_ila_0/probe4 [get_nets [list intTrig1]]
 create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe5]
 set_property port_width 1 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list startMeasSync_reg_n_0]]
+connect_debug_port u_ila_0/probe5 [get_nets [list measTrig]]
 create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe6]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
 set_property port_width 1 [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list StartMeas_o_OBUF]]
+connect_debug_port u_ila_0/probe6 [get_nets [list MeasStartEventGenInst/MeasTrig_i]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
 set_property port_width 1 [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list intTrig1]]
+connect_debug_port u_ila_0/probe7 [get_nets [list MeasStartEventGenInst/measTrigReg_reg_n_0]]
 create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe8]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
 set_property port_width 1 [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list trigForIntTrig2]]
+connect_debug_port u_ila_0/probe8 [get_nets [list MeasStartEventGenInst/Rst_i]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
 set_property port_width 1 [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list intTrig2]]
+connect_debug_port u_ila_0/probe9 [get_nets [list MeasStartEventGenInst/StartMeasDsp_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list MeasStartEventGenInst/startMeasEvent_i_1_n_0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list MeasStartEventGenInst/StartMeasEvent_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list startMeasSync_reg_n_0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe13]
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list trigForIntTrig2]]
 set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
 set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
 set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.veo

@@ -1,72 +0,0 @@
-// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-// IP VLNV: xilinx.com:ip:fifo_generator:13.2
-// IP Revision: 5
-
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-MeasDataFifo your_instance_name (
-  .clk(clk),      // input wire clk
-  .srst(srst),    // input wire srst
-  .din(din),      // input wire [255 : 0] din
-  .wr_en(wr_en),  // input wire wr_en
-  .rd_en(rd_en),  // input wire rd_en
-  .dout(dout),    // output wire [255 : 0] dout
-  .full(full),    // output wire full
-  .empty(empty)  // output wire empty
-);
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file MeasDataFifo.v when simulating
-// the core, MeasDataFifo. When compiling the wrapper file, be sure to
-// reference the Verilog simulation library.
-

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.vho

@@ -1,89 +0,0 @@
-
-
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-COMPONENT MeasDataFifo
-  PORT (
-    clk : IN STD_LOGIC;
-    srst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END COMPONENT;
-
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : MeasDataFifo
-  PORT MAP (
-    clk => clk,
-    srst => srst,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty
-  );
-
-

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo.xdc

@@ -1,64 +0,0 @@
- 
- 
- 
- 
- 
-
-################################################################################
-# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-################################################################################
-
-#------------------------------------------------------------------------------#
-#                         Native FIFO Constraints                              #
-#------------------------------------------------------------------------------#
-
-
-
-
-################################################################################
-

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_clocks.xdc

@@ -1,69 +0,0 @@
-################################################################################
-# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-################################################################################
-#------------------------------------------------------------------------------#
-#                         Native FIFO Constraints                              #
-#------------------------------------------------------------------------------#
-
-#set wr_clock          [get_clocks -of_objects [get_ports wr_clk]]
-#set rd_clock          [get_clocks -of_objects [get_ports rd_clk]]
-#set wr_clk_period     [get_property PERIOD $wr_clock]
-#set rd_clk_period     [get_property PERIOD $rd_clock]
-#set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
-
-
-# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
-
-## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]
-## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] $skew_value
-
-## set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]
-## set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] $skew_value
-#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.sckt_wrst_i_reg}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_inst/Q_reg_reg[0]}]
-#set_false_path -from [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[3].rd_rst_inst/Q_reg_reg[0]}] -to [get_cells -hierarchical -filter {NAME =~ *gsckt_wrst.gic_rst.garst_sync_ic[1].rd_rst_wr_inst/Q_reg_reg[0]}]
-################################################################################

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_ooc.xdc

@@ -1,57 +0,0 @@
-# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-# DO NOT MODIFY THIS FILE.
-# #########################################################
-#
-# This XDC is used only in OOC mode for synthesis, implementation
-#
-# #########################################################
-
-
-create_clock -period 10 -name clk [get_ports clk]
-
-

S5443_M/S5443.srcs/sources_1/ip/MeasDataFifo/doc/fifo_generator_v13_2_changelog.txt

@@ -1,254 +0,0 @@
-2020.2:
- * Version 13.2 (Rev. 5)
- * No changes
-
-2020.1.1:
- * Version 13.2 (Rev. 5)
- * No changes
-
-2020.1:
- * Version 13.2 (Rev. 5)
- * No changes
-
-2019.2.2:
- * Version 13.2 (Rev. 5)
- * No changes
-
-2019.2.1:
- * Version 13.2 (Rev. 5)
- * No changes
-
-2019.2:
- * Version 13.2 (Rev. 5)
- * General: IP Waivers update in constraint files. No functional changes
- * Revision change in one or more subcores
-
-2019.1.3:
- * Version 13.2 (Rev. 4)
- * No changes
-
-2019.1.2:
- * Version 13.2 (Rev. 4)
- * No changes
-
-2019.1.1:
- * Version 13.2 (Rev. 4)
- * No changes
-
-2019.1:
- * Version 13.2 (Rev. 4)
- * Bug Fix: Destination Clock not connected properly for some XPM_CDC instances when in common clock mode. Conditions added to connect the correct clock
- * Other: IP Waivers added in constraint files. No functional changes
- * Revision change in one or more subcores
-
-2018.3.1:
- * Version 13.2 (Rev. 3)
- * No changes
-
-2018.3:
- * Version 13.2 (Rev. 3)
- * Feature Enhancement: None
- * Other: Reduced simulation warnings in Behavioral model. No functional changes
- * Revision change in one or more subcores
-
-2018.2:
- * Version 13.2 (Rev. 2)
- * No changes
-
-2018.1:
- * Version 13.2 (Rev. 2)
- * Bug Fix: Enable Safety Circuit option was unintentionally made available for user selection when Enable Reset Synchronization is not selected. This unintentional enablement is corrected and Enable Safety Circuit is available for user selection only if Enable Reset Synchronization option is selected
- * Bug Fix: REQP-1839 DRC warning removed from example test bench
- * Bug Fix: Read Data Count in behavioral model is updated to start with a valid value when Enable Reset Synchronization option is not selected
- * Other: As FIFO Generator core uses XPM_CDC module, user must ensure that the wr_rst and rd_rst overlap for at least C_SYNCHRONIZER_STAGE+1 slowest clock cycles if Enable Reset Synchronization option is disabled
-
-2017.4:
- * Version 13.2 (Rev. 1)
- * Revision change in one or more subcores
-
-2017.3:
- * Version 13.2
- * Feature Enhancement: Enable Safety Circuit option is made default for BRAM based FIFOs when Asynchronous Reset is selected
- * Feature Enhancement: All outputs are made synchronous to respective clock domain when Enable Safety Circuit option is selected
- * Feature Enhancement: All outputs are invalid for reset duration + 60 slowest clock cycles when Enable Safety Circuit option is selected
- * Feature Enhancement: All outputs are invalid for reset duration + 30 slowest clock cycles when Enable Safety Circuit option is not selected
- * Feature Enhancement: The outputs of FIFO Generator may be Xs for initial few clock cycles if the core is configured without reset. It is recommended to wait for 15 slowest clock cycles at the beginning of behavioral simulation (from time 0) before accessing the FIFO
-
-2017.2:
- * Version 13.1 (Rev. 4)
- * No changes
-
-2017.1:
- * Version 13.1 (Rev. 4)
- * Bug Fix: FIFO Generator core was constructing the buit-in FIFO sub-optimally for 2K-deep and 36-bit wide configuration. This is corrected to use the optimal FIFO structure
- * Bug Fix: In order to enable the tool to perform the recovery check on the reset, set_false_path for reset is kept only from the input port to the first flop where it connects to
- * Feature Enhancement: Updated the FIFO Generator's constraints to improve tool performance processing its XDC
- * Other: Internal device family change, no functional changes
- * Revision change in one or more subcores
-
-2016.4:
- * Version 13.1 (Rev. 3)
- * Port Change: None
- * Bug Fix: Supported features table in the first page of GUI updated to reflect the asymmetry support for common clock BRAM FIFO
- * Feature Enhancement: None
- * Revision change in one or more subcores
-
-2016.3:
- * Version 13.1 (Rev. 2)
- * Port Change: wr_rst_busy and rd_rst_busy ports made available if safety circuit is enabled
- * Bug Fix: Fixed issue which was causing the m_axis_tvalid to go high after the reset is released and no valid data written to the FIFO
- * Feature Enhancement: Safety circuit is made independent of Output Register and Enable Reset Synchronization options
- * Other: Added support for future devices
- * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
- * Revision change in one or more subcores
-
-2016.2:
- * Version 13.1 (Rev. 1)
- * Revision change in one or more subcores
-
-2016.1:
- * Version 13.1
- * Delivering only Verilog behavioral model.
- * Constraint(s) for Independent Clocks Distributed RAM FIFO is changed, which may issue a CDC-1 warning that can be safely ignored.
- * Output Register option is updated to offer either Embedded Register or Fabric Register or Both Embedded and Fabric Registers.
- * Updated the FIFO Generator GUI to provide Embedded Register option for Built-in FIFO when ECC mode in selected.
- * Programmable Full and Programmable Empty Threshold range has been reduced for UltraScale and UltraScale+ Built-in FIFO configurations. For more information on the exact threshold range change, refer the PG(057)
- * Programmable Full and Programmable Empty Threshold values were reset to its default values when the previous version of the core is upgraded to the latest version. This has been corrected
- * Revision change in one or more subcores
-
-2015.4.2:
- * Version 13.0 (Rev. 1)
- * No changes
-
-2015.4.1:
- * Version 13.0 (Rev. 1)
- * No changes
-
-2015.4:
- * Version 13.0 (Rev. 1)
- * Fixed safety circuit related warnings in Behavioral model
- * Revision change in one or more subcores
-
-2015.3:
- * Version 13.0
- * Additional safety circuit option provided for asynchronous reset configurations.
- * Delivering only VHDL behavioral model.
- * Added asymmetric port width support for 7-series Common Clock Block RAM FIFO
- * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
-
-2015.2.1:
- * Version 12.0 (Rev. 4)
- * No changes
-
-2015.2:
- * Version 12.0 (Rev. 4)
- * No changes
-
-2015.1:
- * Version 12.0 (Rev. 4)
- * Delivering  non encrypted behavioral models.
- * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports
- * Enabling behavioral simulation for Built-in FIFO configurations changes the simulation file names and delivery structure.
- * Supported devices and production status are now determined automatically, to simplify support for future devices
-
-2014.4.1:
- * Version 12.0 (Rev. 3)
- * No changes
-
-2014.4:
- * Version 12.0 (Rev. 3)
- * Reduced DRC warnings.
- * Internal device family change, no functional changes
- * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
-
-2014.3:
- * Version 12.0 (Rev. 2)
- * Added support for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
- * Added support for write data count and read data count for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
- * Added support for write data count and read data count for Common Clock Block RAM FIFO when Asymmetric Port Width option is enabled for UltraScale devices.
- * Added support for Low Latency Built-in FIFO for UltraScale devices.
-
-2014.2:
- * Version 12.0 (Rev. 1)
- * Repackaged to improve internal automation, no functional changes.
-
-2014.1:
- * Version 12.0
- * Asynchronous reset port (rst) for Built-in FIFO configurations is removed for UltraScale Built-in FIFO configurations. When upgrading from previously released core, 'rst' port will be replaced by 'srst' port.
- * Synchronous reset (srst) mechanism is changed now for UltraScale devices. FIFO Generator will now provide wr_rst_busy and rd_rst_busy output ports. When wr_rst_busy is active low, the core is ready for write operation and when rd_rst_busy is active low, the core is ready for read operation.
- * Added asymmetric port width support for Common Clock Block RAM FIFO, Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations for UltraScale Devices
- * Added 'sleep' input port for Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations only for UltraScale Devices
- * Internal device family name change, no functional changes
-
-2013.4:
- * Version 11.0 (Rev. 1)
- * Added support for Ultrascale devices
- * Common Clock Builtin FIFO is set as default implementation type only for UltraScale devices
- * Embedded Register option is always ON for Block RAM and Builtin FIFOs only for UltraScale devices
- * Reset is sampled with respect to wr_clk/clk and then synchronized before the use in FIFO Generator only for UltraScale devices
-
-2013.3:
- * Version 11.0
- * AXI ID Tags (s_axi_wid and m_axi_wid) are now determined by AXI protocol type (AXI4, AXI3). When upgrading from previously released core, these signals will be removed when AXI_Type = AXI4_Full.
- * AXI Lock signals (s_axi_awlock, m_axi_awlock, s_axi_arlock and m_axi_arlock) are now determined by AXI Protocol type (AXI4, AXI3). When upgrading from previously released core, these signals width will reduce from 2-bits to 1-bit when AXI_Type=AXI4_Full
- * Removed restriction on packet size in AXI4 Stream FIFO mode. Now, the packet size can be up to FIFO depth
- * Enhanced support for IP Integrator
- * Reduced warnings in synthesis and simulation
- * Added support for Cadence IES and Synopsys VCS simulators
- * Improved GUI speed and responsiveness, no functional changes
- * Increased the maximum number of synchronization stages from 4 to 8. The minimum FIFO depth is limited to 32 when number of synchronization stages is > 4
-
-2013.2:
- * Version 10.0 (Rev. 1)
- * Constraints processing order changed
-
-2013.1:
- * Version 10.0
- * Native Vivado Release
- * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.
-
-(c) Copyright 2002 - 2020 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
-
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
-
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-(individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
-
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.

S5443_M/S5443.srcs/sources_1/new/ExtDspInterface/DspInterface.v

@@ -33,9 +33,10 @@ module	DspInterface
 )
 (
 	input	Clk_i,
-	input	ClkPpiOut_i,
 	input	Rst_i,
 	input	OscWind_i,
+	input	StartMeasDsp_i,
+	input	DspReadyForRx_i,
 	input	[31:0]	MeasNum_i,
 	
 	input	Mosi_i,
@@ -227,33 +228,33 @@ DecimFilterWrapper	DecimFilter
 	.FilteredDataVal_o	(filteredDecimDataVal)
 );
 
-FftDataFormer	FftDataFormerInst
-(
-	.Clk_i				(Clk_i), 
-	.Rst_i				(Rst_i),	
-	.OscWind_i			(OscWind_i),
-	.MeasNum_i			(MeasNum_i),
-	
-	.AdcData_i			({filteredDecimDataI,filteredDecimDataQ}),
+// FftDataFormer	FftDataFormerInst
+// (
+	// .Clk_i				(Clk_i), 
+	// .Rst_i				(Rst_i),	
+	// .OscWind_i			(OscWind_i),
+	// .MeasNum_i			(MeasNum_i),
+	
+	// .AdcData_i			({filteredDecimDataI,filteredDecimDataQ}),
 	// .AdcData_i			({testPatternData,testPatternData}),
-	.AdcDataVal_i		(filteredDecimDataVal),
+	// .AdcDataVal_i		(filteredDecimDataVal),
 	
-	.OscDataBus_o		(fftDataBus),
-	.OscDataBusVal_o	(fftDataBusVal)
-);
+	// .OscDataBus_o		(fftDataBus),
+	// .OscDataBusVal_o	(fftDataBusVal)
+// );
 
-OscDataFormer	BypassDataFormer
-(
-	.Clk_i				(Clk_i), 
-	.Rst_i				(Rst_i),	
-	.OscWind_i			(OscWind_i),
-	.MeasNum_i			(MeasNum_i),
-	
-	.AdcData_i			(currDataChannel),	
-	
-	.OscDataBus_o		(bypassDataBus),
-	.OscDataBusVal_o	(bypassDataBusVal)
-);
+// OscDataFormer	BypassDataFormer
+// (
+	// .Clk_i				(Clk_i), 
+	// .Rst_i				(Rst_i),	
+	// .OscWind_i			(OscWind_i),
+	// .MeasNum_i			(MeasNum_i),
+	
+	// .AdcData_i			(currDataChannel),	
+	
+	// .OscDataBus_o		(bypassDataBus),
+	// .OscDataBusVal_o	(bypassDataBusVal)
+// );
 
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
@@ -283,13 +284,15 @@ MeasDataFifoWrapper
 MeasDataFifoInst
 (
 	.Clk_i			(Clk_i), 
-	.ClkPpiOut_i	(ClkPpiOut_i), 
 	.Rst_i			(Rst_i),	
 	.PpiBusy_i		(ppiBusy),	
-	// .MeasDataBus_i	(measDataBus),
-	.MeasDataBus_i	(dataForFifo),
-	// .MeasDataVal_i	(LpOutStart_i),	
-	.MeasDataVal_i	(dataForFifoVal),	
+	.MeasNum_i		(MeasNum_i),	
+	.StartMeasDsp_i	(StartMeasDsp_i),	
+	.DspReadyForRx_i(DspReadyForRx_i),	
+	.MeasDataBus_i	(measDataBus),
+	// .MeasDataBus_i	(dataForFifo),
+	.MeasDataVal_i	(LpOutStart_i),	
+	// .MeasDataVal_i	(dataForFifoVal),	
 	
 	.MeasDataBus_o	(measDataBusTx),
 	.MeasDataVal_o	(measDataValTx)

S5443_M/S5443.srcs/sources_1/new/MeasDataFifo/FifoController.v

@@ -1,11 +1,37 @@
 `timescale 1ns / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:12:30 06/03/2020 
+// Design Name: 
+// Module Name:    WinParameters 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: kek
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
 	
 module FifoController	
+#(
+	parameter	TxInPack		=	200,		
+	parameter	WorkTimeCycles	=	404000
+	// parameter	WorkTimeCycles	=	20000
+)
 (
 	input	Clk_i, 
-	input	ClkPpiOut_i, 
 	input	Rst_i,	
 	input	PpiBusy_i,	
+	input	DspReadyForRx_i,
 	input	MeasDataVal_i,
 	input	FullFlag_i,
 	input	EmptyFlag_i,
@@ -19,11 +45,13 @@ module FifoController
 //  REG/WIRE
 //================================================================================
 	reg	rdEn;
+	
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
 	assign	MeasDataVal_o	=	rdEn&(!PpiBusy_i);
 	assign	RdEn_o			=	rdEn&(!PpiBusy_i);
+	
 //================================================================================
 //  CODING
 //================================================================================		
@@ -46,9 +74,13 @@ end
 
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
-		if	(!PpiBusy_i)	begin
-			if	(!EmptyFlag_i)	begin
-				rdEn	<=	1'b1;
+		if	(!DspReadyForRx_i)	begin
+			if	(!PpiBusy_i)	begin
+				if	(!EmptyFlag_i)	begin
+					rdEn	<=	1'b1;
+				end	else	begin
+					rdEn	<=	1'b0;
+				end
 			end	else	begin
 				rdEn	<=	1'b0;
 			end

S5443_M/S5443.srcs/sources_1/new/MeasDataFifo/MeasDataFifoWrapper.v

@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`timescale 1ns / 1ns
 	
 module MeasDataFifoWrapper	
 #(	
@@ -7,9 +7,11 @@ module MeasDataFifoWrapper
 )
 (
 	input	Clk_i, 
-	input	ClkPpiOut_i, 
 	input	Rst_i,	
 	input	PpiBusy_i,	
+	input	StartMeasDsp_i,
+	input	DspReadyForRx_i,
+	input	[DataWidth-1:0]	MeasNum_i,
 	
 	input	[DataWidth*(ChNum*2)-1:0]	MeasDataBus_i,
 	input	MeasDataVal_i,
@@ -25,23 +27,40 @@ module MeasDataFifoWrapper
 	wire	emptyFlag;
 	wire	wrEn;
 	wire	rdEn;
-	wire	fifoRst;
 
+	reg		startMeasDspReg;
+	wire	startMeasDspNeg;
+	wire	startMeasDspPos;
+	
+	reg		ppiBusyReg;
+	
+	reg		rstFromDsp;
+	wire	trueRstFromDsp;
+	
+	integer	i;
+	reg	[0:0]	rstFromDspPipe	[49:0];
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
-	assign	MeasDataVal_o	=	rdEn;	
+	assign	MeasDataVal_o	=	rdEn;
+	assign	startMeasDspPos	=	(StartMeasDsp_i&(!startMeasDspReg));
 //================================================================================
 //  CODING
 //================================================================================		
 
-	
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		startMeasDspReg	<=	StartMeasDsp_i;
+	end	else	begin
+		startMeasDspReg	<=	1'b0;
+	end
+end
+
 MeasDataFifo	MeasDataFifoInst
 (
 	.clk	(Clk_i),
-	// .srst	(fifoRst),
-	// .srst	(Rst_i|fifoRst),
-	.srst	(Rst_i),
+	.srst	(Rst_i|startMeasDspPos),
 	.din	(MeasDataBus_i),
 	.wr_en	(wrEn),
 	.rd_en	(rdEn),
@@ -53,16 +72,17 @@ MeasDataFifo	MeasDataFifoInst
   
 FifoController	FifoControllerInst
 (
-	.Clk_i			(Clk_i), 
-	.Rst_i			(Rst_i),	
-	.PpiBusy_i		(PpiBusy_i),	
-	.MeasDataVal_i	(MeasDataVal_i),
-	.FullFlag_i		(fullFlag),
-	.EmptyFlag_i	(emptyFlag),
+	.Clk_i				(Clk_i), 
+	.Rst_i				(Rst_i|startMeasDspPos),	
+	.DspReadyForRx_i	(DspReadyForRx_i),	
+	.PpiBusy_i			(PpiBusy_i),	
+	.MeasDataVal_i		(MeasDataVal_i),
+	.FullFlag_i			(fullFlag),
+	.EmptyFlag_i		(emptyFlag),
 	
-	.MeasDataVal_o	(),
-	.WrEn_o			(wrEn),
-	.RdEn_o			(rdEn)
+	.MeasDataVal_o		(),
+	.WrEn_o				(wrEn),
+	.RdEn_o				(rdEn)
 );
 
 endmodule

S5443_M/S5443.srcs/sources_1/new/PulseMeas/MeasStartEventGen.v

@@ -65,17 +65,17 @@ module	MeasStartEventGen
 		end
 	end
 	
-	always	@(*)	begin
+	always	@(posedge	Clk_i)	begin
 		if	(!Rst_i)	begin
 			if	(StartMeasDsp_i)	begin
 				if	(measTrigPos)	begin
-					startMeasEvent	=	1'b1;
+					startMeasEvent	<=	1'b1;
 				end
 			end	else	begin
-				startMeasEvent	=	0;
+				startMeasEvent	<=	0;
 			end
 		end	else	begin
-			startMeasEvent	=	0;
+			startMeasEvent	<=	0;
 		end
 	end
 	

S5443_M/S5443.srcs/sources_1/new/S5443Top.v

@@ -112,7 +112,7 @@ module	S5443Top
 	
 	//fpga-dsp signals
 	input	StartMeas_i,		//"high"- start meas, "low"-stop meas
-	output	StartMeas_o,
+	output	StartMeasEvent_o,
 	output	EndMeas_o,
 	
 	output	TimersClk_o,
@@ -137,7 +137,9 @@ module	S5443Top
 	output	Mod_o,
 	
 	//gain lines
-	inout	SensEnM_io,
+	input	DspReadyForRx_i,
+	output	DspReadyForRxToFpgaS_o,
+	
 	output	StartMeasDsp_o,
 	output	[ChNum-1:0]	AmpEn_o,	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
 	
@@ -154,6 +156,8 @@ module	S5443Top
 	wire	[AdcDataWidth-1:0]	adc2ChT2Data;
 	
 	reg		startMeasSync;
+	reg		startMeasSyncR;
+	reg		startMeasSyncRR;
 	wire	startMeasEvent;
 	wire	intTrig1;
 	reg		startMeasEventReg;
@@ -255,10 +259,6 @@ module	S5443Top
 	wire	[ChNum-1:0]	ampEnNewStates;
 	wire	[ChNum-1:0]	sensEn;
 	
-	// wire	sensEnAll	=	(gainCtrl[0])?	((|sensEn)|sensEnReg):1'b0;
-	reg		sensEnReg;
-	wire	sensEnNeg	=	(sensEnReg&!SensEnM_io);
-	
 	wire	[ChNum-1:0]	gainManual;
 	wire	[ChNum-1:0]	gainAutoEn;
 	
@@ -396,6 +396,10 @@ module	S5443Top
 	wire	trigFromDspEvent;
 	wire	oscWind;
 	wire	oscDataRdFlag;
+	
+	reg		dspReadyForRxReg;
+	reg		dspReadyForRxRegR;
+	reg		dspReadyForRxRegRR;
 //================================================================================
 //  assignments
 //================================================================================	
@@ -515,12 +519,11 @@ module	S5443Top
 	assign	Adc1InitCs_o	=	adc0InitCs;
 	assign	Adc2InitCs_o	=	adc1InitCs;
 	assign	AdcInitRst_o	=	adcCtrl[0];
-	
-	// assign	Led_o	=	ledReg	&(adc1ImT1|adc1ReT1|adc1ImR1|adc1ReR1|adc2ImT2|adc2ReT2|adc2ImR2|adc2ReR2);
+
 	// assign	Led_o	=	ledReg	|(|ampEnNewStates);
 	assign	Led_o	=	ledReg	|(|ampEnNewStates);
 	
-	assign	StartMeas_o	=	startMeasEvent;
+	assign	StartMeasEvent_o	=	startMeasEvent;
 	
 	assign	EndMeas_o	=	stopMeas|stopMeasR; //stretching pulse for 1 more clk period
 	
@@ -559,9 +562,9 @@ module	S5443Top
 	assign	Trig6to1_io	[3]	=	(measCtrl[19])	?	1'bz:extPortsMuxedOut[3];	//1 - in, 0 - out
 	assign	Trig6to1_io	[4]	=	(measCtrl[20])	?	1'bz:extPortsMuxedOut[4];	//1 - in, 0 - out
 	assign	Trig6to1_io	[5]	=	(measCtrl[21])	?	1'bz:extPortsMuxedOut[5];	//1 - in, 0 - out
-
-	assign	SensEnM_io	=	(|sensEn)?	1'b0:1'bz;
-	assign	StartMeasDsp_o	=	StartMeas_i;
+	
+	assign	DspReadyForRxToFpgaS_o	=	dspReadyForRxRegR;
+	assign	StartMeasDsp_o	=	startMeasSyncR;
 //================================================================================
 //  CODING
 //================================================================================
@@ -571,8 +574,24 @@ always	@(posedge	gclk)	begin	//stretching pulse
 	stopMeasR	<=	stopMeas;
 end
 
-always	@(posedge	gclk)	begin	//stretching pulse
-	sensEnReg	<=	SensEnM_io;
+always	@(posedge	gclk)	begin
+	if	(!initRst)	begin
+		dspReadyForRxReg	<=	DspReadyForRx_i;
+		dspReadyForRxRegR	<=	dspReadyForRxReg;
+		dspReadyForRxRegRR	<=	dspReadyForRxRegR;
+		
+		startMeasSync	<=	StartMeas_i;
+		startMeasSyncR	<=	startMeasSync;
+		startMeasSyncRR	<=	startMeasSyncR;
+	end	else	begin
+		dspReadyForRxReg	<=	1'b0;
+		dspReadyForRxRegR	<=	1'b0;
+		dspReadyForRxRegRR	<=	1'b0;
+		
+		startMeasSync	<=	1'b0;
+		startMeasSyncR	<=	1'b0;
+		startMeasSyncRR	<=	1'b0;
+	end
 end
 
 //--------------------------------------------------------------------------------
@@ -663,6 +682,8 @@ ExternalDspInterface
 	.Clk_i				(gclk),
 	.Rst_i				(initRst),
 	.OscWind_i			(oscWind),
+	.StartMeasDsp_i		(startMeasSyncRR),
+	.DspReadyForRx_i	(dspReadyForRxRegRR),
 	.MeasNum_i			({measNum2[7:0],measNum1}),
 	
 	.Mosi_i				(Mosi_i),
@@ -726,14 +747,6 @@ ExternalDspInterface
 //--------------------------------------------------------------------------------
 //	Internal DSP calculation module
 //--------------------------------------------------------------------------------
-always	@(posedge	gclk)	begin
-	if	(!initRst)	begin
-		startMeasSync	<=	StartMeas_i;
-	end	else	begin
-		startMeasSync	<=	1'b0;
-	end
-end
-
 NcoRstGen	NcoRstGenInst
 (
 	.Clk_i				(gclk),
@@ -773,7 +786,7 @@ InternalDsp
 	.GatingPulse_i		(gatingPulse),
 	
 	.StartMeas_i		(measStart),
-	.StartMeasDsp_i		(startMeasSync),
+	.StartMeasDsp_i		(startMeasSyncRR),
 	.OscDataRdFlag_i	(oscDataRdFlag),
 	
 	.MeasNum_i			({measNum2[7:0],measNum1}),
@@ -1116,7 +1129,7 @@ MeasTrigMux
 	.MuxCtrl_i		(muxCtrl3[14:10]),
 
 	.DspTrigOut_i	(1'b0),
-	.DspStartCmd_i	(startMeasSync),
+	.DspStartCmd_i	(startMeasSyncRR),
 	.IntTrig_i		(1'b0),
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(7'b0),
@@ -1134,7 +1147,7 @@ MeasStartEventGen	MeasStartEventGenInst
 	.Clk_i				(gclk),
 	
 	.MeasTrig_i			(measTrig),
-	.StartMeasDsp_i		(startMeasSync),
+	.StartMeasDsp_i		(startMeasSyncRR),
 	
 	.StartMeasEvent_o	(startMeasEvent),
 	.InitTrig_o			()
@@ -1288,7 +1301,7 @@ ExtPortsMux
 	.MuxCtrl_i		(extTrigMuxCtrlArray[l]),
 
 	.DspTrigOut_i	(DspTrigOut_i),
-	.DspStartCmd_i	(startMeasSync), //tut nichego nebilo 14.02.2023 zamknul suda startMeasSync
+	.DspStartCmd_i	(startMeasSyncRR), //tut nichego nebilo 14.02.2023 zamknul suda startMeasSync
 	.IntTrig_i		(intTrig1),
 	.IntTrig2_i		(intTrig2),
 	.PulseBus_i		(pulseBus),

S5443_S/S5443.srcs/constrs_1/new/S5443Top.xdc

@@ -144,8 +144,8 @@ set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[2]}]
 set_property PACKAGE_PIN B15 [get_ports {AmpEn_o[3]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[3]}]
 
-set_property PACKAGE_PIN N15 [get_ports SensEnS_io]
-set_property IOSTANDARD LVCMOS33 [get_ports SensEnS_io]
+set_property PACKAGE_PIN N15 [get_ports DspReadyForRx_i]
+set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRx_i]
 
 set_property PACKAGE_PIN L15 [get_ports StartMeasDsp_i]
 set_property IOSTANDARD LVCMOS33 [get_ports StartMeasDsp_i]

S5443_S/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v

@@ -1,10 +1,10 @@
 // Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-// Date        : Mon Feb 20 11:34:29 2023
+// Date        : Mon Feb 20 11:34:27 2023
 // Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub
-//               c:/Users/Stepan/Desktop/4portCompact/S5443Current/S5443_S/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.v
+// Command     : write_verilog -force -mode synth_stub -rename_top MeasDataFifo -prefix
+//               MeasDataFifo_ MeasDataFifo_stub.v
 // Design      : MeasDataFifo
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7s25csga225-2

S5443_S/S5443.srcs/sources_1/ip/MeasDataFifo/MeasDataFifo_stub.vhdl

@@ -1,10 +1,10 @@
 -- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+-- Date        : Mon Feb 20 11:34:27 2023
 -- Host        : DESKTOP-RMARCDV running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top MeasDataFifo -prefix
+--               MeasDataFifo_ MeasDataFifo_stub.vhdl
 -- Design      : MeasDataFifo
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7s25csga225-2

S5443_S/S5443.srcs/sources_1/new/ExtDspInterface/DspInterface.v

@@ -33,9 +33,10 @@ module	DspInterface
 )
 (
 	input	Clk_i,
-	input	ClkPpiOut_i,
 	input	Rst_i,
 	input	OscWind_i,
+	input	StartMeasDsp_i,
+	input	DspReadyForRx_i,
 	input	[31:0]	MeasNum_i,
 	
 	input	Mosi_i,
@@ -227,33 +228,33 @@ DecimFilterWrapper	DecimFilter
 	.FilteredDataVal_o	(filteredDecimDataVal)
 );
 
-FftDataFormer	FftDataFormerInst
-(
-	.Clk_i				(Clk_i), 
-	.Rst_i				(Rst_i),	
-	.OscWind_i			(OscWind_i),
-	.MeasNum_i			(MeasNum_i),
-	
-	.AdcData_i			({filteredDecimDataI,filteredDecimDataQ}),
+// FftDataFormer	FftDataFormerInst
+// (
+	// .Clk_i				(Clk_i), 
+	// .Rst_i				(Rst_i),	
+	// .OscWind_i			(OscWind_i),
+	// .MeasNum_i			(MeasNum_i),
+	
+	// .AdcData_i			({filteredDecimDataI,filteredDecimDataQ}),
 	// .AdcData_i			({testPatternData,testPatternData}),
-	.AdcDataVal_i		(filteredDecimDataVal),
+	// .AdcDataVal_i		(filteredDecimDataVal),
 	
-	.OscDataBus_o		(fftDataBus),
-	.OscDataBusVal_o	(fftDataBusVal)
-);
+	// .OscDataBus_o		(fftDataBus),
+	// .OscDataBusVal_o	(fftDataBusVal)
+// );
 
-OscDataFormer	BypassDataFormer
-(
-	.Clk_i				(Clk_i), 
-	.Rst_i				(Rst_i),	
-	.OscWind_i			(OscWind_i),
-	.MeasNum_i			(MeasNum_i),
-	
-	.AdcData_i			(currDataChannel),	
-	
-	.OscDataBus_o		(bypassDataBus),
-	.OscDataBusVal_o	(bypassDataBusVal)
-);
+// OscDataFormer	BypassDataFormer
+// (
+	// .Clk_i				(Clk_i), 
+	// .Rst_i				(Rst_i),	
+	// .OscWind_i			(OscWind_i),
+	// .MeasNum_i			(MeasNum_i),
+	
+	// .AdcData_i			(currDataChannel),	
+	
+	// .OscDataBus_o		(bypassDataBus),
+	// .OscDataBusVal_o	(bypassDataBusVal)
+// );
 
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
@@ -283,13 +284,15 @@ MeasDataFifoWrapper
 MeasDataFifoInst
 (
 	.Clk_i			(Clk_i), 
-	.ClkPpiOut_i	(ClkPpiOut_i), 
 	.Rst_i			(Rst_i),	
 	.PpiBusy_i		(ppiBusy),	
-	// .MeasDataBus_i	(measDataBus),
-	.MeasDataBus_i	(dataForFifo),
-	// .MeasDataVal_i	(LpOutStart_i),	
-	.MeasDataVal_i	(dataForFifoVal),	
+	.MeasNum_i		(MeasNum_i),	
+	.StartMeasDsp_i	(StartMeasDsp_i),	
+	.DspReadyForRx_i(DspReadyForRx_i),	
+	.MeasDataBus_i	(measDataBus),
+	// .MeasDataBus_i	(dataForFifo),
+	.MeasDataVal_i	(LpOutStart_i),	
+	// .MeasDataVal_i	(dataForFifoVal),	
 	
 	.MeasDataBus_o	(measDataBusTx),
 	.MeasDataVal_o	(measDataValTx)

S5443_S/S5443.srcs/sources_1/new/MeasDataFifo/FifoController.v

@@ -1,11 +1,37 @@
 `timescale 1ns / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:12:30 06/03/2020 
+// Design Name: 
+// Module Name:    WinParameters 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: kek
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
 	
 module FifoController	
+#(
+	parameter	TxInPack		=	200,		
+	parameter	WorkTimeCycles	=	404000
+	// parameter	WorkTimeCycles	=	20000
+)
 (
 	input	Clk_i, 
-	input	ClkPpiOut_i, 
 	input	Rst_i,	
 	input	PpiBusy_i,	
+	input	DspReadyForRx_i,
 	input	MeasDataVal_i,
 	input	FullFlag_i,
 	input	EmptyFlag_i,
@@ -19,11 +45,13 @@ module FifoController
 //  REG/WIRE
 //================================================================================
 	reg	rdEn;
+	
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
 	assign	MeasDataVal_o	=	rdEn&(!PpiBusy_i);
 	assign	RdEn_o			=	rdEn&(!PpiBusy_i);
+	
 //================================================================================
 //  CODING
 //================================================================================		
@@ -46,9 +74,13 @@ end
 
 always	@(posedge	Clk_i)	begin
 	if	(!Rst_i)	begin
-		if	(!PpiBusy_i)	begin
-			if	(!EmptyFlag_i)	begin
-				rdEn	<=	1'b1;
+		if	(!DspReadyForRx_i)	begin
+			if	(!PpiBusy_i)	begin
+				if	(!EmptyFlag_i)	begin
+					rdEn	<=	1'b1;
+				end	else	begin
+					rdEn	<=	1'b0;
+				end
 			end	else	begin
 				rdEn	<=	1'b0;
 			end

S5443_S/S5443.srcs/sources_1/new/MeasDataFifo/MeasDataFifoWrapper.v

@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`timescale 1ns / 1ns
 	
 module MeasDataFifoWrapper	
 #(	
@@ -7,9 +7,11 @@ module MeasDataFifoWrapper
 )
 (
 	input	Clk_i, 
-	input	ClkPpiOut_i, 
 	input	Rst_i,	
 	input	PpiBusy_i,	
+	input	StartMeasDsp_i,
+	input	DspReadyForRx_i,
+	input	[DataWidth-1:0]	MeasNum_i,
 	
 	input	[DataWidth*(ChNum*2)-1:0]	MeasDataBus_i,
 	input	MeasDataVal_i,
@@ -25,23 +27,40 @@ module MeasDataFifoWrapper
 	wire	emptyFlag;
 	wire	wrEn;
 	wire	rdEn;
-	wire	fifoRst;
 
+	reg		startMeasDspReg;
+	wire	startMeasDspNeg;
+	wire	startMeasDspPos;
+	
+	reg		ppiBusyReg;
+	
+	reg		rstFromDsp;
+	wire	trueRstFromDsp;
+	
+	integer	i;
+	reg	[0:0]	rstFromDspPipe	[49:0];
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
-	assign	MeasDataVal_o	=	rdEn;	
+	assign	MeasDataVal_o	=	rdEn;
+	assign	startMeasDspPos	=	(StartMeasDsp_i&(!startMeasDspReg));
 //================================================================================
 //  CODING
 //================================================================================		
 
-	
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		startMeasDspReg	<=	StartMeasDsp_i;
+	end	else	begin
+		startMeasDspReg	<=	1'b0;
+	end
+end
+
 MeasDataFifo	MeasDataFifoInst
 (
 	.clk	(Clk_i),
-	// .srst	(fifoRst),
-	// .srst	(Rst_i|fifoRst),
-	.srst	(Rst_i),
+	.srst	(Rst_i|startMeasDspPos),
 	.din	(MeasDataBus_i),
 	.wr_en	(wrEn),
 	.rd_en	(rdEn),
@@ -53,16 +72,17 @@ MeasDataFifo	MeasDataFifoInst
   
 FifoController	FifoControllerInst
 (
-	.Clk_i			(Clk_i), 
-	.Rst_i			(Rst_i),	
-	.PpiBusy_i		(PpiBusy_i),	
-	.MeasDataVal_i	(MeasDataVal_i),
-	.FullFlag_i		(fullFlag),
-	.EmptyFlag_i	(emptyFlag),
+	.Clk_i				(Clk_i), 
+	.Rst_i				(Rst_i|startMeasDspPos),	
+	.DspReadyForRx_i	(DspReadyForRx_i),	
+	.PpiBusy_i			(PpiBusy_i),	
+	.MeasDataVal_i		(MeasDataVal_i),
+	.FullFlag_i			(fullFlag),
+	.EmptyFlag_i		(emptyFlag),
 	
-	.MeasDataVal_o	(),
-	.WrEn_o			(wrEn),
-	.RdEn_o			(rdEn)
+	.MeasDataVal_o		(),
+	.WrEn_o				(wrEn),
+	.RdEn_o				(rdEn)
 );
 
 endmodule

S5443_S/S5443.srcs/sources_1/new/PulseMeas/MeasStartEventGen.v

@@ -65,17 +65,17 @@ module	MeasStartEventGen
 		end
 	end
 	
-	always	@(*)	begin
+	always	@(posedge	Clk_i)	begin
 		if	(!Rst_i)	begin
 			if	(StartMeasDsp_i)	begin
 				if	(measTrigPos)	begin
-					startMeasEvent	=	1'b1;
+					startMeasEvent	<=	1'b1;
 				end
 			end	else	begin
-				startMeasEvent	=	0;
+				startMeasEvent	<=	0;
 			end
 		end	else	begin
-			startMeasEvent	=	0;
+			startMeasEvent	<=	0;
 		end
 	end
 	

S5443_S/S5443.srcs/sources_1/new/S5443Top.v

@@ -113,7 +113,7 @@ module	S5443Top
 	output	Overload_o,
 	
 	//gain lines
-	inout	SensEnS_io,	
+	input	DspReadyForRx_i,	
 	output	[ChNum-1:0]	AmpEn_o,	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
 	
 	///test port for testbench
@@ -233,9 +233,6 @@ module	S5443Top
 	wire	[ChNum-1:0]	ampEnNewStates;
 	wire	[ChNum-1:0]	sensEn;
 	
-	reg		sensEnReg;
-	wire	sensEnNeg	=	(sensEnReg&!SensEnS_io);
-	
 	wire	[ChNum-1:0]	gainManual;
 	wire	[ChNum-1:0]	gainAutoEn;
 	
@@ -372,6 +369,7 @@ module	S5443Top
 	wire	oscDataRdFlag;
 	wire	dspBusy;
 	wire	fifoEn;
+	reg		dspReadyForRxReg;
 //================================================================================
 //  assignments
 //================================================================================	
@@ -512,7 +510,7 @@ module	S5443Top
 	assign	AmpEn_o	[0]	=	~ampEnNewStates[1];	
 	
 	assign	Overload_o	=	overCtrlR;
-	assign	SensEnS_io	=	(|sensEn)?	1'b0:1'bz;
+	// assign	Overload_o	=	intTrig2;
 //================================================================================
 //  CODING
 //================================================================================
@@ -522,10 +520,13 @@ always	@(posedge	gclk)	begin
 	stopMeasR	<=	stopMeas;
 end
 
-always	@(posedge	gclk)	begin	
-	sensEnReg	<=	SensEnS_io;
+always	@(posedge	gclk)	begin
+	if	(!initRst)	begin
+		dspReadyForRxReg	<=	DspReadyForRx_i;
+	end	else	begin
+		dspReadyForRxReg	<=	1'b0;
+	end
 end
-
 //--------------------------------------------------------------------------------
 //	Data Receiving Interface
 //--------------------------------------------------------------------------------
@@ -612,6 +613,9 @@ ExternalDspInterface
 	.Clk_i				(gclk),
 	.Rst_i				(initRst),
 	.OscWind_i			(oscWind),
+	.StartMeasDsp_i		(startMeasSync),
+	// .DspReadyForRx_i	(dspReadyForRxReg),
+	.DspReadyForRx_i	(dspReadyForRxReg),
 	.MeasNum_i			({measNum2[7:0],measNum1}),
 	
 	.Mosi_i				(Mosi_i),
@@ -731,7 +735,8 @@ MeasStartEventGen	IntTrig2GenInst
 	.MeasTrig_i			(trigForIntTrig2),
 	.StartMeasDsp_i		(intTrig1),
 	
-	.StartMeasEvent_o	(intTrig2)
+	.StartMeasEvent_o	(),
+	.InitTrig_o			(intTrig2)
 );
 
 InternalDsp