Поправлена линия Sck_o при Stop = 0. Исправлено ложнео срабатывание линии Sck_0 при Stop!=0.

sources_1/new/QuadSPI/QuadSPIm.v

@@ -123,11 +123,11 @@ module QuadSPIm
     end
 	
 	reg [2:0] clkCtrlReg;
-	always @(posedge Clk_i) begin
+	always @(*) begin
 		if (Rst_i) 	begin
-			clkCtrlReg <= 0;
+			clkCtrlReg = 0;
 		end else begin
-			clkCtrlReg <= {SelSt_i,PulsePol_i,ClockPhase_i};
+			clkCtrlReg = {SelSt_i,PulsePol_i,ClockPhase_i};
 		end
 	end
 	
@@ -387,50 +387,46 @@ module QuadSPIm
 						end
 				endcase
 			end else begin
-				if (startFlag) begin
-					if (SelSt_i) begin
-						if (!ss) begin
-							if (PulsePol_i) begin 
-								if (ClockPhase_i) begin
-									Sck_o = ~(~Clk_i);
-								end
-								else begin 
-									Sck_o = ~Clk_i;
-								end
-							end else begin
-								if (ClockPhase_i) begin
-									Sck_o = ~(Clk_i);
-								end
-								else begin 
-									Sck_o = ~(~Clk_i);
-								end
+				if (SelSt_i) begin
+					if (!ss) begin
+						if (PulsePol_i) begin 
+							if (ClockPhase_i) begin
+								Sck_o = Clk_i;
+							end
+							else begin 
+								Sck_o = ~Clk_i;
 							end
 						end else begin
-							Sck_o = 1'b0;
+							if (ClockPhase_i) begin
+								Sck_o = ~Clk_i;
+							end
+							else begin 
+								Sck_o = Clk_i;
+							end
 						end
 					end else begin
-						if (ss) begin
-							if (PulsePol_i) begin 
-								if (ClockPhase_i) begin
-									Sck_o = ~(~Clk_i);
-								end
-								else begin 
-									Sck_o = ~Clk_i;
-								end
-							end else begin
-								if (ClockPhase_i) begin
-									Sck_o = ~(Clk_i);
-								end
-								else begin 
-									Sck_o = ~(~Clk_i);
-								end
+						Sck_o = 1'b0;
+					end
+				end else begin
+					if (ss) begin
+						if (PulsePol_i) begin 
+							if (ClockPhase_i) begin
+								Sck_o = Clk_i;
+							end
+							else begin 
+								Sck_o = ~Clk_i;
 							end
 						end else begin
-							Sck_o = 1'b0;
+							if (ClockPhase_i) begin
+								Sck_o = ~Clk_i;
+							end
+							else begin 
+								Sck_o = Clk_i;
+							end
 						end
+					end else begin
+						Sck_o = 1'b0;
 					end
-				end else begin
-					Sck_o = 0;
 				end
 			end
 		end

sources_1/new/QuadSPI/QuadSPImTb.v

@@ -17,7 +17,7 @@ localparam [31:0] startData = 32'h01010101;
 reg [31:0] data;
 reg [31:0] dataS;
 
-wire [1:0] widthSel  = 2'h3;
+wire [1:0] widthSel  = 2'h2;
 wire clockPol = 1'b0;
 wire clockPhase = 1'b0;
 wire endianSel = 1'b0;
@@ -31,7 +31,7 @@ wire valS;
 reg [31:0] tbCnt;
 
 wire start = (tbCnt>=100);
-wire fifoEmpty = (tbCnt >= 500);
+wire fifoEmpty = (tbCnt >= 199);
 
 //================================================================================
 //  ASSIGNMENTS

sources_1/new/S5443_3_tb.v

@@ -48,7 +48,7 @@ localparam ClockPolarity0 = 1'b0;//0 for active high, 1 for active low
 localparam Assel0 = 1'b1;//0 for software control, 1 for hardware control
 localparam SelSt0 = 1'b1; //1 - assert slave select(low), 0 - deassert slave select(high)
 localparam Size0 = 2'd2; //0 - 8 bits, 1 - 16 bits, 2 - 24 bits, 3 - 32 bits
-localparam Mode0 = 1'b1; // 1 - 4 Mosi, 0 - 1 Mosi
+localparam Mode0 = 1'b0; // 1 - 4 Mosi, 0 - 1 Mosi
 localparam LSBF0 = 1'b0; // 1 - LSB first, 0 - MSB first
 
 localparam [15:0] Spi0CtrlRegData = {8'h0,LSBF0, Mode0, Size0, SelSt0, Assel0, ClockPolarity0, ClockPhase0, SpiEn0};
@@ -70,7 +70,7 @@ localparam Spi0ClkRegData = {8'h0, Mux1, Mux0, Div};
 //***********************************************
 localparam Lag0 = 1'b0; //Extended SPI clock lag control, 0 - Disable, 1 - Enable
 localparam Lead0 = 1'b0; //Extended SPI clock lead control, 0 - Disable, 1 - Enable
-localparam Stop0 = 6'd0; //Number of clock cycles to wait after CS is deasserted
+localparam Stop0 = 6'd1; //Number of clock cycles to wait after CS is deasserted
 
 localparam [15:0] Spi0CsDelayRegData = {8'h0, Stop0, Lead0, Lag0};
 
@@ -222,7 +222,7 @@ localparam GPIOAddr = 11'hFF0;
 assign SmcBe_i = (tb_cnt >0 && tb_cnt <=44) ? 2'b00 : 2'b11;
 assign SmcAmsN_i = (tb_cnt > 0 && tb_cnt <= 44) ? 1'b0 : 1'b1;
 assign smcData = SmcData_i;
-assign mosi1_io = (!Mode0) ? mosi0_o : 1'bz;
+// assign mosi1_io = (!Mode0) ? mosi0_o : 1'bz;
 
 //***********************************************
 //	           CLOCK GENERATION
@@ -360,8 +360,7 @@ always @(posedge Clk_i) begin
             endcase
         end
         else begin 
-                // SmcData_i <= $urandom_range(0, 8'hFF);
-                SmcData_i <= 16'hffaa;
+                SmcData_i <= $urandom_range(0, 8'hFF);
             end
     end
 end

sources_1/new/SpiR/SPIm.v

@@ -120,11 +120,11 @@ module SPIm
     end
     
 	reg [2:0] clkCtrlReg;
-	always @(posedge Clk_i) begin
+	always @(*) begin
 		if (Rst_i) 	begin
-			clkCtrlReg <= 0;
+			clkCtrlReg = 0;
 		end else begin
-			clkCtrlReg <= {SelSt_i,PulsePol_i,ClockPhase_i};
+			clkCtrlReg = {SelSt_i,PulsePol_i,ClockPhase_i};
 		end
 	end
 	
@@ -384,50 +384,46 @@ module SPIm
 						end
 				endcase
 			end else begin
-				if (startFlag) begin
-					if (SelSt_i) begin
-						if (!ss) begin
-							if (PulsePol_i) begin 
-								if (ClockPhase_i) begin
-									Sck_o = Clk_i;
-								end
-								else begin 
-									Sck_o = ~Clk_i;
-								end
-							end else begin
-								if (ClockPhase_i) begin
-									Sck_o = ~Clk_i;
-								end
-								else begin 
-									Sck_o = Clk_i;
-								end
+				if (SelSt_i) begin
+					if (!ss) begin
+						if (PulsePol_i) begin 
+							if (ClockPhase_i) begin
+								Sck_o = Clk_i;
+							end
+							else begin 
+								Sck_o = ~Clk_i;
 							end
 						end else begin
-							Sck_o = 1'b0;
+							if (ClockPhase_i) begin
+								Sck_o = ~Clk_i;
+							end
+							else begin 
+								Sck_o = Clk_i;
+							end
 						end
 					end else begin
-						if (ss) begin
-							if (PulsePol_i) begin 
-								if (ClockPhase_i) begin
-									Sck_o = Clk_i;
-								end
-								else begin 
-									Sck_o = ~Clk_i;
-								end
-							end else begin
-								if (ClockPhase_i) begin
-									Sck_o = ~Clk_i;
-								end
-								else begin 
-									Sck_o = Clk_i;
-								end
+						Sck_o = 1'b0;
+					end
+				end else begin
+					if (ss) begin
+						if (PulsePol_i) begin 
+							if (ClockPhase_i) begin
+								Sck_o = Clk_i;
+							end
+							else begin 
+								Sck_o = ~Clk_i;
 							end
 						end else begin
-							Sck_o = 1'b0;
+							if (ClockPhase_i) begin
+								Sck_o = ~Clk_i;
+							end
+							else begin 
+								Sck_o = Clk_i;
+							end
 						end
+					end else begin
+						Sck_o = 1'b0;
 					end
-				end else begin
-					Sck_o = 0;
 				end
 			end
 		end