Восстановлены изменения в xdc и Top

SRAM/QuadSPIm.v

@@ -31,10 +31,10 @@ reg startFlag;
 reg [2:0] ssCnt;
 reg Ss;
 reg SSr;
-reg [6:0] mosiReg0;
-reg [6:0] mosiReg1;
-reg [6:0] mosiReg2;
-reg [6:0] mosiReg3;
+reg [7:0] mosiReg0;
+reg [7:0] mosiReg1;
+reg [7:0] mosiReg2;
+reg [7:0] mosiReg3;
 reg [3:0] ssNum;
 reg [2:0] delayCnt;
 reg stopFlag;

constrs_1/new/S5443_3.xdc

@@ -87,6 +87,8 @@ set_property PACKAGE_PIN K1 [get_ports {Sck_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[0]}]
 set_property PACKAGE_PIN H1 [get_ports {Ss_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[0]}]
+set_property PACKAGE_PIN K2 [get_ports {SsFlash_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[0]}]
 set_property PACKAGE_PIN J1 [get_ports {Mosi0_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[0]}]
 set_property PACKAGE_PIN J3 [get_ports {Mosi1_o[0]}]
@@ -107,6 +109,8 @@ set_property PACKAGE_PIN N2 [get_ports {Sck_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[1]}]
 set_property PACKAGE_PIN N4 [get_ports {Ss_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[1]}]
+set_property PACKAGE_PIN P1 [get_ports {SsFlash_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[1]}]
 set_property PACKAGE_PIN N3 [get_ports {Mosi0_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[1]}]
 set_property PACKAGE_PIN R2 [get_ports {Mosi1_o[1]}]
@@ -127,6 +131,8 @@ set_property PACKAGE_PIN E2 [get_ports {Sck_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[2]}]
 set_property PACKAGE_PIN E1 [get_ports {Ss_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[2]}]
+set_property PACKAGE_PIN F1 [get_ports {SsFlash_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[2]}]
 set_property PACKAGE_PIN D1 [get_ports {Mosi0_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[2]}]
 set_property PACKAGE_PIN D2 [get_ports {Mosi1_o[2]}]
@@ -146,6 +152,8 @@ set_property PACKAGE_PIN R10 [get_ports {Sck_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[3]}]
 set_property PACKAGE_PIN P10 [get_ports {Ss_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[3]}]
+set_property PACKAGE_PIN N10 [get_ports {SsFlash_o[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[3]}]
 set_property PACKAGE_PIN N8 [get_ports {Mosi0_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[3]}]
 set_property PACKAGE_PIN R8 [get_ports {Mosi1_o[3]}]
@@ -167,6 +175,8 @@ set_property PACKAGE_PIN R14 [get_ports {Sck_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[4]}]
 set_property PACKAGE_PIN N14 [get_ports {Ss_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[4]}]
+set_property PACKAGE_PIN P14 [get_ports {SsFlash_o[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[4]}]
 set_property PACKAGE_PIN R13 [get_ports {Mosi0_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[4]}]
 set_property PACKAGE_PIN P12 [get_ports {Mosi1_o[4]}]
@@ -187,6 +197,8 @@ set_property PACKAGE_PIN P6 [get_ports {Sck_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[5]}]
 set_property PACKAGE_PIN R5 [get_ports {Ss_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[5]}]
+set_property PACKAGE_PIN R6 [get_ports {SsFlash_o[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[5]}]
 set_property PACKAGE_PIN R4 [get_ports {Mosi0_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[5]}]
 set_property PACKAGE_PIN R3 [get_ports {Mosi1_o[5]}]
@@ -206,6 +218,8 @@ set_property PACKAGE_PIN B5 [get_ports {Sck_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[6]}]
 set_property PACKAGE_PIN B3 [get_ports {Ss_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[6]}]
+set_property PACKAGE_PIN A4 [get_ports {SsFlash_o[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[6]}]
 set_property PACKAGE_PIN B1 [get_ports {Mosi0_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[6]}]
 set_property PACKAGE_PIN C4 [get_ports {Mosi1_o[6]}]
@@ -231,8 +245,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports Clk123_i]
 create_clock -period 8.130 -name Clk123_i -waveform {0.000 4.065} -add [get_ports Clk123_i]
 
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk123_i_IBUF]
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets writeEn_i_IBUF]
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets readEn_i_IBUF]
+# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets writeEn_i_IBUF]
+# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets readEn_i_IBUF]
 
 
 

sources_1/new/DspSmc/SmcRx.v

@@ -22,9 +22,9 @@
 
 module	SmcRx
 #(
-	parameter	DataOutWidth	=	32,
+	parameter	DataOutWidth	=	16,
 	parameter	DataInWidth		=	16,
-	parameter	AddrWidth		=	25
+	parameter	AddrWidth		=	12
 )
 (
 	input	Clk_i,                       

sources_1/new/MMCM/MmcmWrapper.v

@@ -56,28 +56,28 @@ MMCME2_ADV
    .CLKOUT0_DUTY_CYCLE  (0.5),
    .CLKOUT0_PHASE       (0.0),
    .CLKOUT0_USE_FINE_PS ("FALSE"),
-   .CLKOUT1_DIVIDE      (6),
+   .CLKOUT1_DIVIDE      (12.3),
    .CLKOUT1_DUTY_CYCLE  (0.5),
    .CLKOUT1_PHASE       (0.0),
    .CLKOUT1_USE_FINE_PS ("FALSE"),
-   .CLKOUT2_DIVIDE      (6),
+   .CLKOUT2_DIVIDE      (12.3),
    .CLKOUT2_DUTY_CYCLE  (0.5),
    .CLKOUT2_PHASE       (0.0),
    .CLKOUT2_USE_FINE_PS ("FALSE"),
-   .CLKOUT3_DIVIDE      (6),
+   .CLKOUT3_DIVIDE      (12.3),
    .CLKOUT3_DUTY_CYCLE  (0.5),
    .CLKOUT3_PHASE       (0.0),
    .CLKOUT3_USE_FINE_PS ("FALSE"),
-   .CLKOUT4_DIVIDE      (6),
+   .CLKOUT4_DIVIDE      (12.3),
    .CLKOUT4_DUTY_CYCLE  (0.5),
    .CLKOUT4_PHASE       (0.0),
    .CLKOUT4_USE_FINE_PS ("FALSE"),
    .CLKOUT4_CASCADE     ("FALSE"),
-   .CLKOUT5_DIVIDE      (6),
+   .CLKOUT5_DIVIDE      (12.3),
    .CLKOUT5_DUTY_CYCLE  (0.5),
    .CLKOUT5_PHASE       (0.0),
    .CLKOUT5_USE_FINE_PS ("FALSE"),
-   .CLKOUT6_DIVIDE      (6),
+   .CLKOUT6_DIVIDE      (12.3),
    .CLKOUT6_DUTY_CYCLE  (0.5),
    .CLKOUT6_PHASE       (0.0),
    .CLKOUT6_USE_FINE_PS ("FALSE"),
@@ -123,12 +123,12 @@ mmcme2_test_inst
 
 BUFG BUFG_FB    (.O (clkfb_bufgout),    .I (clkfb_bufgin));
 BUFG BUFG_CLK0  (.O (SpiCLk_o[0]),     .I (clk0_bufgin));
-BUFG BUFG_CLK1  (.O (SpiCLk_o[1]),     .I (clk1_bufgin));
-BUFG BUFG_CLK2  (.O (SpiCLk_o[2]),     .I (clk2_bufgin));
-BUFG BUFG_CLK3  (.O (SpiCLk_o[3]),     .I (clk3_bufgin));
-BUFG BUFG_CLK4  (.O (SpiCLk_o[4]),     .I (clk4_bufgin));
-BUFG BUFG_CLK5  (.O (SpiCLk_o[5]),     .I (clk5_bufgin));
-BUFG BUFG_CLK6  (.O (SpiCLk_o[6]),     .I (clk6_bufgin));
+BUFG BUFG_CLK1  (.O (SpiCLk_o[1]),     .I (clk0_bufgin));
+BUFG BUFG_CLK2  (.O (SpiCLk_o[2]),     .I (clk0_bufgin));
+BUFG BUFG_CLK3  (.O (SpiCLk_o[3]),     .I (clk0_bufgin));
+BUFG BUFG_CLK4  (.O (SpiCLk_o[4]),     .I (clk0_bufgin));
+BUFG BUFG_CLK5  (.O (SpiCLk_o[5]),     .I (clk0_bufgin));
+BUFG BUFG_CLK6  (.O (SpiCLk_o[6]),     .I (clk0_bufgin));
 
 
 endmodule

sources_1/new/S5443_3Top.v

@@ -35,7 +35,6 @@ module S5443_3Top #(
     input SmcAmsN_i,
 	
     input SmcAre_i,
-    // input DspRst_i,
     input [1:0] SmcBe_i,
     input SmcAoe_i,
     output [SpiNum-1:0] LD_i,
@@ -47,6 +46,7 @@ module S5443_3Top #(
     output  [SpiNum-1:0] Mosi2_o,
     output  [SpiNum-1:0] Mosi3_o,
     output  [SpiNum-1:0] Ss_o,
+    output  [SpiNum-1:0] SsFlash_o,
     output  [SpiNum-1:0] Sck_o,
     output  [SpiNum-1:0] SpiRst_o,
     output  LD_o
@@ -58,6 +58,7 @@ module S5443_3Top #(
 //================================================================================
 wire Clk100_i;
 wire [SpiNum-1:0]Sck;
+wire [AddrRegWidth-1:0] addr;
 wire [SpiNum-1:0] Ss; 
 wire [SpiNum-1:0]Mosi0;
 wire [SpiNum-1:0]Mosi1;
@@ -163,6 +164,11 @@ wire [SpiNum-1:0] FifoTxRst;
 wire [0:7]  WordCntTx [SpiNum-1:0];
 wire [0:7]  WordCntRx [SpiNum-1:0];
 
+wire [SpiNum-1:0] CS0;
+wire [SpiNum-1:0] CS1;
+
+wire [SpiNum-1:0] Assel;
+
 wire	[SpiNum-1:0]	spiClkBus;
 wire	[SpiNum-1:0]	spiSyncRst;
 
@@ -173,13 +179,27 @@ wire	smcVal;
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
+assign addr = {SmcAddr_i, 1'b0};
 assign Data_i = (!SmcAoe_i) ? data : 16'bz;
 assign ten = SpiTxRxEn[6:0];
 assign Mosi0_o = Mosi0;
 assign Mosi1_o = Mosi1;
 assign Mosi2_o = Mosi2;
 assign Mosi3_o = Mosi3;
-assign Ss_o = Ss;
+assign Ss_o[0] = (Assel[0])? ((CS0[0])? Ss[0]:~Ss[0]):CS0[0];
+assign Ss_o[1] = (Assel[1])? ((CS0[1])? Ss[1]:~Ss[1]):CS0[1];
+assign Ss_o[2] = (Assel[2])? ((CS0[2])? Ss[2]:~Ss[2]):CS0[2];
+assign Ss_o[3] = (Assel[3])? ((CS0[3])? Ss[3]:~Ss[3]):CS0[3];
+assign Ss_o[4] = (Assel[4])? ((CS0[4])? Ss[4]:~Ss[4]):CS0[4];
+assign Ss_o[5] = (Assel[5])? ((CS0[5])? Ss[5]:~Ss[5]):CS0[5];
+assign Ss_o[6] = (Assel[6])? ((CS0[6])? Ss[6]:~Ss[6]):CS0[6];
+assign SsFlash_o[0] = (Assel[0])?(CS1[0]? Ss[0]:~Ss[0]):CS1[0];
+assign SsFlash_o[1] = (Assel[1])?(CS1[1]? Ss[1]:~Ss[1]):CS1[1];
+assign SsFlash_o[2] = (Assel[2])?(CS1[2]? Ss[2]:~Ss[2]):CS1[2];
+assign SsFlash_o[3] = (Assel[3])?(CS1[3]? Ss[3]:~Ss[3]):CS1[3];
+assign SsFlash_o[4] = (Assel[4])?(CS1[4]? Ss[4]:~Ss[4]):CS1[4];
+assign SsFlash_o[5] = (Assel[5])?(CS1[5]? Ss[5]:~Ss[5]):CS1[5];
+assign SsFlash_o[6] = (Assel[6])?(CS1[6]? Ss[6]:~Ss[6]):CS1[6];
 assign Sck_o = Sck;
 
 assign widthSel[0] = Spi0Ctrl[6:5];
@@ -222,6 +242,14 @@ assign selSt[4] = Spi4Ctrl[4];
 assign selSt[5] = Spi5Ctrl[4];
 assign selSt[6] = Spi6Ctrl[4];
 
+assign Assel[0] = Spi0Ctrl[3];
+assign Assel[1] = Spi1Ctrl[3];
+assign Assel[2] = Spi2Ctrl[3];
+assign Assel[3] = Spi3Ctrl[3];
+assign Assel[4] = Spi4Ctrl[3];
+assign Assel[5] = Spi5Ctrl[3];
+assign Assel[6] = Spi6Ctrl[3];
+
 assign stopDelay[0] = Spi0CsDelay[7:2];
 assign stopDelay[1] = Spi1CsDelay[7:2];
 assign stopDelay[2] = Spi2CsDelay[7:2];
@@ -305,6 +333,22 @@ assign WordCntTx[5] = Spi5TxFifoCtrl[15:8];
 assign WordCntTx[6] = Spi6TxFifoCtrl[15:8];
 
 
+assign CS0[0] = Spi0CsCtrl[0];
+assign CS0[1] = Spi1CsCtrl[0];
+assign CS0[2] = Spi2CsCtrl[0];
+assign CS0[3] = Spi3CsCtrl[0];
+assign CS0[4] = Spi4CsCtrl[0];
+assign CS0[5] = Spi5CsCtrl[0];
+assign CS0[6] = Spi6CsCtrl[0];
+
+assign CS1[0] = Spi0CsCtrl[1];
+assign CS1[1] = Spi1CsCtrl[1];
+assign CS1[2] = Spi2CsCtrl[1];
+assign CS1[3] = Spi3CsCtrl[1];
+assign CS1[4] = Spi4CsCtrl[1];
+assign CS1[5] = Spi5CsCtrl[1];
+assign CS1[6] = Spi6CsCtrl[1];
+
 //================================================================================
 //  CODING
 //================================================================================	
@@ -320,8 +364,8 @@ SmcRx	SmcRx
 	.RstN_i		(!initRst),
 	.ForceRstN_i(1'b0),
 
-	.SmcD_i		(SmcD_i),
-	.SmcA_i		(SmcA_i),
+	.SmcD_i		(SmcData_i),
+	.SmcA_i		(addr),
 	.SmcAwe_i	(SmcAwe_i),
 	.SmcAmsN_i	(SmcAmsN_i),
 	.SmcAoe_i	(SmcAoe_i),
@@ -338,9 +382,9 @@ SmcDataMux SmcDataMuxer
     .Clk_i	(gclk),
     .Rst_i	(initRst),
 
-	.SmcVal_i	(smcVal),
-	.SmcData_i	(smcData),
-    .SmcAddr_i	({smcAddr,1'b0}),
+	.SmcVal_i	(1'b1),
+	.SmcData_i	({SmcData_i,SmcData_i}),
+    .SmcAddr_i	({SmcAddr_i,1'b0}),
 
 	.ToRegMapVal_o	(toRegMapVal),
 	.ToRegMapData_o	(toRegMapData),