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@@ -227,12 +227,12 @@ module RegMap #(
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localparam SPI_TX_RX_EN_SET = 12'hF04;
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/* Clear register */
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localparam SPI_TX_RX_EN_CLR = 12'hF08;
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+ /*Spi Tx/Rx FIFO Flags */
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+ localparam SPI_TX_RX_FLAGS = 12'hF0C;
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localparam GPIO_CTRL_ADDR = 12'hFF0;
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localparam GPIO_CTRL_ADDR_S = 12'hFF2;
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-
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- localparam DEBUG_0_ADDR = 12'hFF8;
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- localparam DEBUG_1_ADDR = 12'hFFC;
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+
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//================================================================================
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// CODING
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@@ -442,9 +442,6 @@ module RegMap #(
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GPIO_CTRL_ADDR_S : begin
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GPIOARegS <= Data_i;
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end
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- DEBUG_0_ADDR : begin
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- ledReg <= Data_i;
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- end
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endcase
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end
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1 : begin
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@@ -590,9 +587,6 @@ module RegMap #(
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GPIO_CTRL_ADDR_S : begin
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GPIOARegS[15:8] <= Data_i[15:8];
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end
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- DEBUG_0_ADDR : begin
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- ledReg[15:8] <= Data_i[15:8];
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- end
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endcase
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end
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2 : begin
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@@ -738,9 +732,6 @@ module RegMap #(
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GPIO_CTRL_ADDR_S : begin
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GPIOARegS[7:0] <= Data_i[7:0];
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end
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- DEBUG_0_ADDR : begin
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- ledReg[7:0] <= Data_i[7:0];
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- end
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endcase
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end
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endcase
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@@ -930,15 +921,15 @@ module RegMap #(
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SPI_TX_RX_EN_CLR : begin
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ansReg = SpiTxRxEnClrReg_o;
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end
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+ SPI_TX_RX_FLAGS : begin
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+ ansReg = {1'h0, RxFifoCtrlReg6_i[2], RxFifoCtrlReg5_i[2], RxFifoCtrlReg4_i[2], RxFifoCtrlReg3_i[2], RxFifoCtrlReg2_i[2], RxFifoCtrlReg1_i[2], RxFifoCtrlReg0_i[2], 1'h0, TxFifoCtrlReg6_i[2], TxFifoCtrlReg5_i[2], TxFifoCtrlReg4_i[2], TxFifoCtrlReg3_i[2], TxFifoCtrlReg2_i[2], TxFifoCtrlReg1_i[2], TxFifoCtrlReg0_i[2]};
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+ end
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GPIO_CTRL_ADDR : begin
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ansReg = GPIOAReg;
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end
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GPIO_CTRL_ADDR_S : begin
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ansReg = {9'd0,LdReg_i};
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end
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- DEBUG_0_ADDR : begin
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- ansReg = ledReg;
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- end
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default : begin
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ansReg = 0;
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end
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