Добавил описание модулей

sources_1/new/CDC/Cdc.v

@@ -10,7 +10,8 @@
 // Tool Versions:
 // Description: 	
 // 
-// Dependencies: 
+// Dependencies: 	This module synchronizes commands from RegMap to the 
+//					respective clock domain.
 // 
 // Revision:
 // Revision 1.0 - File Created

sources_1/new/CDC/Sync1bit.v

@@ -8,7 +8,7 @@
 // Project Name:	S5443_V3_FPGA3
 // Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description: 	
+// Description: 	This module synchronizes Spi enable command
 // 
 // Dependencies: 
 // 
@@ -25,10 +25,8 @@ module Sync1bit #(
 	input ClkFast_i,
 	input ClkSlow_i,
 	input TxEn_i,
-	input RstReg_i,
 
-	output [WIDTH-1:0] TxEn_o,
-	output [WIDTH-1:0] RstReg_o
+	output [WIDTH-1:0] TxEn_o
 );
 
 //================================================================================
@@ -36,16 +34,13 @@ module Sync1bit #(
 //================================================================================
 //lauch registers 
 reg spiTxEnReg;
-reg rstReg;
 // capture registers
 (* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] spiTxEnReg_c;
-(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rstReg_c;
 
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
 assign TxEn_o = spiTxEnReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign RstReg_o = rstReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 
 //================================================================================
 //  LOCALPARAMS
@@ -56,12 +51,10 @@ assign RstReg_o = rstReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 //================================================================================
 always @(posedge ClkFast_i) begin
 	spiTxEnReg <= TxEn_i;
-	rstReg <= RstReg_i;
 end
 
 always @(posedge ClkSlow_i) begin 
 	spiTxEnReg_c <= {spiTxEnReg_c[(STAGES-1)*WIDTH-1:0], spiTxEnReg};
-	rstReg_c <= {rstReg_c[(STAGES-1)*WIDTH-1:0], rstReg};
 end
 
 endmodule

sources_1/new/ClkManager/ClkDivider.v

@@ -8,7 +8,7 @@
 // Project Name:    S5443_V3_FPGA3
 // Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description:     
+// Description:     This modules is clock divider that divides clock frequency based on an input divider value. 
 // 
 // Dependencies: 
 // 

sources_1/new/ClkManager/ClkManager.v

@@ -8,7 +8,9 @@
 // Project Name:    S5443_V3_FPGA3
 // Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description:     
+// Description: 	This module is a clock distributor. Based on a setting it 
+//					multiplexing cloks that generated either from MMCM or from 
+//					a custom divider.     
 // 
 // Dependencies: 
 // 
@@ -89,14 +91,6 @@ module ClkManager
 	assign clkCh[5] = BaudRate5_i[4];
 	assign clkCh[6] = BaudRate6_i[4];
 
-	// assign SpiClk_o[0] = spiClk[0];
-	// assign SpiClk_o[1] = spiClk[1];
-	// assign SpiClk_o[2] = spiClk[2];
-	// assign SpiClk_o[3] = spiClk[3];
-	// assign SpiClk_o[4] = spiClk[4];
-	// assign SpiClk_o[5] = spiClk[5];
-	// assign SpiClk_o[6] = spiClk[6];
-
 	assign SpiClk_o = spiClk; 
 	assign Clk100_o = clk0out;
 	assign Clk80_o = clk1out;

sources_1/new/ClkManager/CmdSync.v

@@ -8,7 +8,8 @@
 // Project Name:    S5443_V3_FPGA3
 // Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description:     
+// Description:     This module synchronize command that determines output clock 
+//					frequency to the respective clock domain 
 // 
 // Dependencies: 
 // 

sources_1/new/ClkManager/MmcmClkMux.v

@@ -8,7 +8,8 @@
 // Project Name:    S5443_V3_FPGA3
 // Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description:     
+// Description:     This module determines which of the MMCM should be muxed based 
+//					on a input setting
 // 
 // Dependencies: 
 // 

sources_1/new/ClkManager/SpiClkMux.v

@@ -8,7 +8,8 @@
 // Project Name:    S5443_V3_FPGA3
 // Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description:     
+// Description:     This module muxes clock based on a clkCh signal - MMCM or 
+//					from a custom divider.
 // 
 // Dependencies: 
 // 

sources_1/new/DataFifo/DataFifoWrapper.v

@@ -8,7 +8,8 @@
 // Project Name:	S5443_V3_FPGA3
 // Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description: 	
+// Description: 	This is a wrapper module that contains FIFO controller and 
+//					FIFO modules 
 // 
 // Dependencies: 
 // 

sources_1/new/DataFifo/FifoCtrl.v

@@ -8,7 +8,7 @@
 // Project Name:    S5443_V3_FPGA3
 // Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description:     
+// Description:     This module generate controll signals for FIFO's 
 // 
 // Dependencies: 
 // 

sources_1/new/QuadSPI/QuadSPIm.v

@@ -1,4 +1,24 @@
 
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		QuadSPIm
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	This is module implements QuadSpi Master protocol. For more info refer 
+//					to the techincal reference manual. 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 module QuadSPIm
 (
     input Clk_i,

sources_1/new/RegMap/RegMap.v

@@ -8,7 +8,8 @@
 // Project Name:	S5443_V3_FPGA3
 // Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description: 	
+// Description: 	This module contains settings for Spi modules.Registers can 
+// 					be read by an external host setting a SmcAre low and address to adress bus.  
 // 
 // Dependencies: 
 // 

sources_1/new/SmcAnsMux/SmcAnsMux.v

@@ -8,7 +8,8 @@
 // Project Name:	S5443_V3_FPGA3
 // Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description: 	
+// Description: 	This module multiplexing the data either from FIFO or a RegMap 
+//					based on an address
 // 
 // Dependencies: 
 // 

sources_1/new/SmcInDataMux/SmcInDataMux.v

@@ -8,7 +8,8 @@
 // Project Name:	S5443_V3_FPGA3
 // Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description: 	
+// Description: 	This module determines which entity is referred(FIFO or a RegMap)
+//					based on an adrress and sets a validity signal	
 // 
 // Dependencies: 
 // 

sources_1/new/SpiR/SPIm.v

@@ -1,3 +1,23 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		SPIm
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	This is module implements Spi Master protocol. For more info refer 
+//					to the techincal reference manual. 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 module SPIm 
 (
     input Clk_i,

sources_1/new/SpiR/SPIs.v

@@ -1,3 +1,22 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		SPIs
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	This is module implements an Spi Slave protocol.
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 module SPIs (
     input Clk_i,
     input Rst_i,

sources_1/new/SpiSubSystem/SpiLinesMuxer.v

@@ -8,7 +8,7 @@
 // Project Name:    S5443_V3_FPGA3
 // Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description:     
+// Description:     This module multiplexing Spi output signals based on an settings.
 // 
 // Dependencies: 
 // 
@@ -16,7 +16,7 @@
 // Revision 1.0 - File Created
 // Additional Comments:
 // 
-//////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////////
 
 module SpiLinesMuxer (
     input SsR_i,

sources_1/new/SpiSubSystem/SpiSubSystem.v

@@ -8,7 +8,8 @@
 // Project Name:	S5443_V3_FPGA3
 // Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
 // Tool Versions:
-// Description: 	
+// Description: 	This is wrapper that encapsulates FIFO's, Spi modules and 
+//					modules that multiplex Spi output lines 
 // 
 // Dependencies: 
 //