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@@ -11,24 +11,25 @@ parameter CLK_PERIOD = 8.13; // Clock period in ns
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reg rst;
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reg clk;
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-localparam [31:0] startData = 32'h1;
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+// localparam [31:0] startData = 32'h1;
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+localparam [31:0] startData = 32'h0A0B0C0D;
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reg [31:0] data;
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-wire [1:0] widthSel = 2'h2;
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+wire [1:0] widthSel = 2'h3;
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wire clockPol = 1'b0;
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wire clockPhase = 1'b0;
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wire endianSel = 1'b0;
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wire lag = 1'b0;
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wire leadx = 1'b0;
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-wire [5:0] stopDelay = 6'h0;
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+wire [5:0] stopDelay = 6'h1;
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wire selSt = 1'b1;
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wire val;
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reg [31:0] tbCnt;
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wire start = (tbCnt>=100);
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-wire fifoEmpty = (data > 32'h29);
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+wire fifoEmpty = (tbCnt >= 500);
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//================================================================================
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// ASSIGNMENTS
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@@ -62,7 +63,8 @@ always @(posedge clk) begin
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if (rst) begin
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data <= startData;
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end else if (val) begin
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- data <= data+10;
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+ // data <= data+32'h1000;
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+ data <= data;
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end
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end
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