Начало

sources_1/new/QuadSPI/QuadSPImTb.v

@@ -11,24 +11,25 @@ parameter CLK_PERIOD = 8.13; // Clock period in ns
 reg rst;
 reg clk;
 
-localparam [31:0] startData = 32'h1;
+// localparam [31:0] startData = 32'h1;
+localparam [31:0] startData = 32'h0A0B0C0D;
 
 reg [31:0] data;
 
-wire [1:0] widthSel  = 2'h2;
+wire [1:0] widthSel  = 2'h3;
 wire clockPol = 1'b0;
 wire clockPhase = 1'b0;
 wire endianSel = 1'b0;
 wire lag = 1'b0;
 wire leadx = 1'b0;
-wire [5:0] stopDelay = 6'h0;
+wire [5:0] stopDelay = 6'h1;
 wire selSt = 1'b1;
 wire val;
 
 reg [31:0] tbCnt;
 
 wire start = (tbCnt>=100);
-wire fifoEmpty = (data > 32'h29);
+wire fifoEmpty = (tbCnt >= 500);
 
 //================================================================================
 //  ASSIGNMENTS
@@ -62,7 +63,8 @@ always @(posedge clk) begin
 	if (rst) begin
 		data <= startData;
 	end else if (val) begin
-		data <= data+10;
+		// data <= data+32'h1000;
+		data <= data;
 	end
 end