Рефакторинг модулей группы ClkManager

sources_1/new/ClkManager/ClkDivider.v

@@ -1,3 +1,23 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     ClkDivider
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
 module ClkDivider (
   input Clk_i,
   input [3:0] ClkDiv_i,
@@ -5,25 +25,38 @@ module ClkDivider (
   output Clk_o
 );
 
+//================================================================================
+//  REG/WIRE
+//================================================================================
 reg [16:0] cnt;
 
 reg clk;
 wire clk_o;
 
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign Clk_o = (cnt < ClkDiv_i / 2) ? 1 : 0;
+
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
+
+//================================================================================
+//  CODING
+//================================================================================   
 always @(posedge Clk_i) begin 
-    if (Rst_i) begin 
-        cnt <= 0;
-    end
-    else begin 
-        if (cnt >= ClkDiv_i-1) begin 
-            cnt <= 0;
-        end
-        else begin 
-            cnt <= cnt + 1;
-        end
-    end
+	if (Rst_i) begin 
+		cnt <= 0;
+	end
+	else begin 
+		if (cnt >= ClkDiv_i - 1) begin 
+			cnt <= 0;
+		end
+		else begin 
+			cnt <= cnt + 1;
+		end
+	end
 end
 
-assign Clk_o = (cnt < ClkDiv_i/2) ? 1 : 0;
-
 endmodule

sources_1/new/ClkManager/ClkGen_tb.v

@@ -1,47 +1,29 @@
 `timescale 1ns / 1ps
 module ClkGen_tb();
 
-
-
-
-
-
 reg Clk_i;
 reg Rst_i;
 
 reg [3:0] clkDiv_i;
 
-
-
-
-
-
 always #(1.667/2) Clk_i = ~Clk_i;
 
-
-
-
 ClkGenGowin ClkGen_inst (
-    .Clk_i(Clk_i), 
-    .Rst_i(Rst_i), 
-    .Clk75_o(),
-    .Clk40_o(),
-    .Clk30_o(),
-    .Clk5_o()
+	.Clk_i(Clk_i),
+	.Rst_i(Rst_i),
+	.Clk75_o(),
+	.Clk40_o(),
+	.Clk30_o(),
+	.Clk5_o()
 );
 
-
-
 initial begin 
-    Clk_i = 0;
-    Rst_i = 1;
-    clkDiv_i = 3;
-    #1000;
-    Rst_i = 0;
+	Clk_i = 0;
+	Rst_i = 1;
+	clkDiv_i = 3;
+	#1000;
+	Rst_i = 0;
 
 end
 
-
-
-
 endmodule

sources_1/new/ClkManager/ClkManager.v

@@ -1,155 +1,173 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     ClkManager
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 
 module ClkManager 
 #(
-	parameter	SpiNum	=	7,
-   parameter   STAGES   =  3
+	parameter	SPI_NUM	=	7,
+	parameter	STAGES	=	3
 )
 (
-   input	Clk_i,
-   input	Rst_i,
-   input Rst80_i,
-   input [7:0] BaudRate0_i,
-   input [7:0] BaudRate1_i,
-   input [7:0] BaudRate2_i,
-   input [7:0] BaudRate3_i,
-   input [7:0] BaudRate4_i,
-   input [7:0] BaudRate5_i,
-   input [7:0] BaudRate6_i,
-
-
-   output   Clk80_o,
-	output 	[SpiNum-1:0]	SpiClk_o
-   
+	input Clk_i,
+	input Rst_i,
+	input Rst80_i,
+	input [7:0] BaudRate0_i,
+	input [7:0] BaudRate1_i,
+	input [7:0] BaudRate2_i,
+	input [7:0] BaudRate3_i,
+	input [7:0] BaudRate4_i,
+	input [7:0] BaudRate5_i,
+	input [7:0] BaudRate6_i,
+
+	output	Clk80_o,
+	output	[SPI_NUM-1:0]	SpiClk_o
 );
+
 //================================================================================
 //	REG/WIRE
 //================================================================================
+	wire clk0out;
+	wire clk1out;
+	wire clk2out;
+	wire clk3out;
+	wire clk4out;
+	wire clk5out;
+	wire clk6out;
 	
-wire    clk0out;
-wire    clk1out;
-wire    clk2out;
-wire    clk3out;
-wire    clk4out;
-wire    clk5out;
-wire    clk6out;
-wire    locked;
-
-wire [SpiNum-1:0] clkOutMMCM;
-
-
-wire [SpiNum-1:0] clkMan;
-
-wire [0:2] clkNum [SpiNum-1:0];
-wire [0:3] clkDiv [SpiNum-1:0];
-wire [0:3] clkDivSync [SpiNum-1:0];
-wire [SpiNum-1:0] clkCh; 
-wire [SpiNum-1:0] spiClk;
+	wire locked;
+	
+	wire [SPI_NUM-1:0] clkOutMMCM;
+	
+	wire [SPI_NUM-1:0] clkMan;
+	
+	wire [0:2] clkNum [SPI_NUM-1:0];
+	wire [0:3] clkDiv [SPI_NUM-1:0];
+	wire [0:3] clkDivSync [SPI_NUM-1:0];
+	wire [SPI_NUM-1:0] clkCh; 
+	wire [SPI_NUM-1:0] spiClk;
 
 //================================================================================
 //	ASSIGNMENTS
 //===============================================================================
-   assign clkNum[0] = BaudRate0_i[7:5];
-   assign clkNum[1] = BaudRate1_i[7:5];
-   assign clkNum[2] = BaudRate2_i[7:5];
-   assign clkNum[3] = BaudRate3_i[7:5];
-   assign clkNum[4] = BaudRate4_i[7:5];
-   assign clkNum[5] = BaudRate5_i[7:5];
-   assign clkNum[6] = BaudRate6_i[7:5];
-
-   assign clkDiv[0] = BaudRate0_i[3:0];
-   assign clkDiv[1] = BaudRate1_i[3:0];
-   assign clkDiv[2] = BaudRate2_i[3:0];
-   assign clkDiv[3] = BaudRate3_i[3:0];
-   assign clkDiv[4] = BaudRate4_i[3:0];
-   assign clkDiv[5] = BaudRate5_i[3:0];
-   assign clkDiv[6] = BaudRate6_i[3:0];
+	assign clkNum[0] = BaudRate0_i[7:5];
+	assign clkNum[1] = BaudRate1_i[7:5];
+	assign clkNum[2] = BaudRate2_i[7:5];
+	assign clkNum[3] = BaudRate3_i[7:5];
+	assign clkNum[4] = BaudRate4_i[7:5];
+	assign clkNum[5] = BaudRate5_i[7:5];
+	assign clkNum[6] = BaudRate6_i[7:5];
+
+	assign clkDiv[0] = BaudRate0_i[3:0];
+	assign clkDiv[1] = BaudRate1_i[3:0];
+	assign clkDiv[2] = BaudRate2_i[3:0];
+	assign clkDiv[3] = BaudRate3_i[3:0];
+	assign clkDiv[4] = BaudRate4_i[3:0];
+	assign clkDiv[5] = BaudRate5_i[3:0];
+	assign clkDiv[6] = BaudRate6_i[3:0];
+
+	assign clkCh[0] = BaudRate0_i[4];
+	assign clkCh[1] = BaudRate1_i[4];
+	assign clkCh[2] = BaudRate2_i[4];
+	assign clkCh[3] = BaudRate3_i[4];
+	assign clkCh[4] = BaudRate4_i[4];
+	assign clkCh[5] = BaudRate5_i[4];
+	assign clkCh[6] = BaudRate6_i[4];
+
+	// assign SpiClk_o[0] = spiClk[0];
+	// assign SpiClk_o[1] = spiClk[1];
+	// assign SpiClk_o[2] = spiClk[2];
+	// assign SpiClk_o[3] = spiClk[3];
+	// assign SpiClk_o[4] = spiClk[4];
+	// assign SpiClk_o[5] = spiClk[5];
+	// assign SpiClk_o[6] = spiClk[6];
+
+	assign SpiClk_o = spiClk; 
+	assign Clk100_o = clk0out;
+	assign Clk80_o = clk1out;
 
-   assign clkCh[0] = BaudRate0_i[4];
-   assign clkCh[1] = BaudRate1_i[4];
-   assign clkCh[2] = BaudRate2_i[4];
-   assign clkCh[3] = BaudRate3_i[4];
-   assign clkCh[4] = BaudRate4_i[4];
-   assign clkCh[5] = BaudRate5_i[4];
-   assign clkCh[6] = BaudRate6_i[4];
-
-   // assign SpiClk_o[0] = spiClk[0];
-   // assign SpiClk_o[1] = spiClk[1];
-   // assign SpiClk_o[2] = spiClk[2];
-   // assign SpiClk_o[3] = spiClk[3];
-   // assign SpiClk_o[4] = spiClk[4];
-   // assign SpiClk_o[5] = spiClk[5];
-   // assign SpiClk_o[6] = spiClk[6];
-
-   assign SpiClk_o = spiClk; 
-   assign Clk100_o = clk0out;
-   assign Clk80_o = clk1out;
-
-   //================================================================================
-   //	LOCALPARAMS
-   //================================================================================
-   
-   
-   //================================================================================
-   //	CODING
-   //================================================================================   
-   genvar i;
-
-   generate
-      for (i=0; i < SpiNum; i = i +1) begin : ClkGen
-         ClkDivider ClkDivider (
-            .Clk_i(clk1out),
-            .ClkDiv_i(clkDivSync[i]),
-            .Rst_i(Rst80_i),
-            .Clk_o(clkMan[i])
-         );
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
 
-         CmdSync #(
-            .WIDTH(4),
-            .STAGES(STAGES)
-         ) CmdSync (
-            .ClkFast_i(Clk_i),
-            .ClkSlow_i(clk1out),
-            .ClkDiv_i(clkDiv[i]),
-            .ClkDiv_o(clkDivSync[i])
-         );
 
-         MmcmClkMux MmcmClkMux (
-            .Rst_i(Rst_i),
-            .clkNum(clkNum[i]),
-            .Clk0_i(clk0out),
-            .Clk1_i(clk1out),
-            .Clk2_i(clk2out),
-            .Clk3_i(clk3out),
-            .Clk4_i(clk4out),
-            .Clk5_i(clk5out),
-            .Clk6_i(clk6out),
-            .ClkOutMMCM_o(clkOutMMCM[i])
-         );
-   
-         SpiClkMux SpiClkMux (
-            .Rst_i(Rst_i),
-            .clkCh(clkCh[i]),
-            .clkOutMMCM(clkOutMMCM[i]),
-            .clkMan(clkMan[i]),
-            .SpiClk_o(spiClk[i])
-         );
-      end
-   endgenerate
-   
-   MMCM MMCM
-    (
-     // Clock out ports
-     .clk_out1(clk0out),     //100 MHz
-     .clk_out2(clk1out),     // 80 MHz
-     .clk_out3(clk2out),     // 70 MHz
-     .clk_out4(clk3out),     // 60MHz
-     .clk_out5(clk4out),     // 50MHz
-     .clk_out6(clk5out),     // 40MHz
-     .clk_out7(clk6out),     // 30MHz 
-     // Status and control signals
-     .reset(Rst_i), // input reset
-     .locked(locked),// output locked
-    // Clock in ports
-     .clk_in1(Clk_i));      // input clk_in1
-   
-   endmodule
+//================================================================================
+//	CODING
+//================================================================================   
+	genvar i;
+
+	generate
+		for (i = 0; i < SPI_NUM; i = i + 1) begin : ClkGen
+			ClkDivider ClkDivider (
+				.Clk_i		(clk1out),
+				.ClkDiv_i	(clkDivSync[i]),
+				.Rst_i		(Rst80_i),
+				.Clk_o		(clkMan[i])
+			);
+
+			CmdSync #(
+				.WIDTH		(4),
+				.STAGES		(STAGES)
+			) CmdSync (
+				.ClkFast_i	(Clk_i),
+				.ClkSlow_i	(clk1out),
+				.ClkDiv_i	(clkDiv[i]),
+				.ClkDiv_o	(clkDivSync[i])
+			);
+
+			MmcmClkMux MmcmClkMux (
+				.Rst_i			(Rst_i),
+				.clkNum			(clkNum[i]),
+				.Clk0_i			(clk0out),
+				.Clk1_i			(clk1out),
+				.Clk2_i			(clk2out),
+				.Clk3_i			(clk3out),
+				.Clk4_i			(clk4out),
+				.Clk5_i			(clk5out),
+				.Clk6_i			(clk6out),
+				.ClkOutMMCM_o	(clkOutMMCM[i])
+			);
+	
+			SpiClkMux SpiClkMux (
+				.Rst_i		(Rst_i),
+				.clkCh		(clkCh[i]),
+				.clkOutMMCM	(clkOutMMCM[i]),
+				.clkMan		(clkMan[i]),
+				.SpiClk_o	(spiClk[i])
+			);
+		end
+	endgenerate
+	
+	MMCM MMCM
+	(
+		// Clock out ports
+		.clk_out1(clk0out),	//100 MHz
+		.clk_out2(clk1out),	// 80 MHz
+		.clk_out3(clk2out),	// 70 MHz
+		.clk_out4(clk3out),	// 60MHz
+		.clk_out5(clk4out),	// 50MHz
+		.clk_out6(clk5out),	// 40MHz
+		.clk_out7(clk6out),	// 30MHz 
+		// Status and control signals
+		.reset(Rst_i),		// input reset
+		.locked(locked),	// output locked
+		// Clock in ports
+		.clk_in1(Clk_i)		// input clk_in1
+	);
+	
+endmodule

sources_1/new/ClkManager/CmdSync.v

@@ -1,34 +1,58 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     CmdSync
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
 module CmdSync #(
-    parameter WIDTH = 4,
-    parameter STAGES = 3
+	parameter WIDTH = 4,
+	parameter STAGES = 3
 )
 (
-    input ClkFast_i,
-    input ClkSlow_i,
-    input [WIDTH-1:0] ClkDiv_i,
+	input ClkFast_i,
+	input ClkSlow_i,
+	input [WIDTH-1:0] ClkDiv_i,
 
-    output [WIDTH-1:0] ClkDiv_o
+	output [WIDTH-1:0] ClkDiv_o
 );
+
 //================================================================================
 //	REG/WIRE
 //================================================================================
 //lauch registers 
 reg [WIDTH-1:0] clkDivReg;
+
 // capture registers
 (* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] clkDivReg_c;
+
 //================================================================================
 //	ASSIGNMENTS
 //===============================================================================
 assign ClkDiv_o = clkDivReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
 //================================================================================
 //	CODING
 //================================================================================ 
 always @(posedge ClkFast_i) begin
-    clkDivReg <= ClkDiv_i;
+	clkDivReg <= ClkDiv_i;
 end
 
 always @(posedge ClkSlow_i) begin
-    clkDivReg_c <= {clkDivReg_c[(STAGES-1)*WIDTH-1:0], clkDivReg};
+	clkDivReg_c <= {clkDivReg_c[(STAGES-1)*WIDTH-1:0], clkDivReg};
 end
 
 endmodule

sources_1/new/ClkManager/MmcmClkMux.v

@@ -1,51 +1,73 @@
-module MmcmClkMux(
-input Rst_i,
-input [2:0]clkNum,
-input Clk0_i,
-input Clk1_i,
-input Clk2_i,
-input Clk3_i,
-input Clk4_i,
-input Clk5_i,
-input Clk6_i, 
-
-output   ClkOutMMCM_o
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     MmcmClkMux
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 
+module MmcmClkMux(
+	input Rst_i,
+	input [2:0] clkNum,
+	input Clk0_i,
+	input Clk1_i,
+	input Clk2_i,
+	input Clk3_i,
+	input Clk4_i,
+	input Clk5_i,
+	input Clk6_i, 
+	
+	output ClkOutMMCM_o
 );
+
 //================================================================================
 //	REG/WIRE
 //================================================================================
 reg clkOutMMCMReg;
 
 wire clkOutMMCM;
+
 //================================================================================
 //	ASSIGNMENTS
 //===============================================================================
 assign clkOutMMCM = clkOutMMCMReg;
+
 //================================================================================
 //	CODING
 //================================================================================ 
 always @(*) begin 
-    if (Rst_i) begin 
-        clkOutMMCMReg = 0;
-    end
-    else begin 
-        case (clkNum) 
-            0: clkOutMMCMReg = Clk0_i;
-            1: clkOutMMCMReg = Clk1_i;
-            2: clkOutMMCMReg = Clk2_i;
-            3: clkOutMMCMReg = Clk3_i;
-            4: clkOutMMCMReg = Clk4_i;
-            5: clkOutMMCMReg = Clk5_i;
-            6: clkOutMMCMReg = Clk6_i;
-            default: clkOutMMCMReg = 0;
-        endcase
-    end
+	if (Rst_i) begin 
+		clkOutMMCMReg = 0;
+	end
+	else begin 
+		case (clkNum) 
+			0: clkOutMMCMReg = Clk0_i;
+			1: clkOutMMCMReg = Clk1_i;
+			2: clkOutMMCMReg = Clk2_i;
+			3: clkOutMMCMReg = Clk3_i;
+			4: clkOutMMCMReg = Clk4_i;
+			5: clkOutMMCMReg = Clk5_i;
+			6: clkOutMMCMReg = Clk6_i;
+			default: clkOutMMCMReg = 0;
+		endcase
+	end
 end
 
 BUFG BUFG_inst (
-   .O(ClkOutMMCM_o), // 1-bit output: Clock output
-   .I(clkOutMMCM)  // 1-bit input: Clock input
+	.O(ClkOutMMCM_o),	// 1-bit output: Clock output
+	.I(clkOutMMCM)		// 1-bit input: Clock input
 );
 
 endmodule

sources_1/new/ClkManager/SpiClkMux.v

@@ -1,10 +1,30 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     SpiClkMux
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
 module SpiClkMux (
-    input Rst_i,
-    input clkCh,
-    input clkOutMMCM,
-    input clkMan,
+	input Rst_i,
+	input clkCh,
+	input clkOutMMCM,
+	input clkMan,
 
-    output SpiClk_o
+	output SpiClk_o
 );
 //================================================================================
 //	REG/WIRE
@@ -22,22 +42,22 @@ assign spiClk = spiClkReg;
 //	CODING
 //================================================================================ 
 always @(*) begin 
-    if (Rst_i) begin 
-        spiClkReg = 0;
-    end
-    else begin 
-        if (clkCh) begin 
-            spiClkReg = clkOutMMCM;
-        end
-        else begin 
-            spiClkReg = clkMan;
-        end
-    end
+	if (Rst_i) begin 
+		spiClkReg = 0;
+	end
+	else begin 
+		if (clkCh) begin 
+			spiClkReg = clkOutMMCM;
+		end
+		else begin 
+			spiClkReg = clkMan;
+		end
+	end
 end
 
 BUFG BUFG_inst (
-   .O(SpiClk_o), // 1-bit output: Clock output
-   .I(spiClk)  // 1-bit input: Clock input
+	.O(SpiClk_o),	// 1-bit output: Clock output
+	.I(spiClk)		// 1-bit input: Clock input
 );
 
 endmodule