Исправлены ошибки при слиянии

SRAM/RegMap.v

@@ -157,8 +157,8 @@ reg [CmdRegWidth/2-1:0] SpiTxRxEnReg;
 reg [CmdRegWidth/2-1:0] GPIOAReg;
 
 
-reg [CmdRegWidth/2-1:0] ansReg;
-reg [CmdRegWidth/2-1:0] LedReg;
+(* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] ansReg;
+(* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] LedReg;
 
 //================================================================================
 //	ASSIGNMENTS

sources_1/new/DataFifo/DataFifoWrapper.v

@@ -9,7 +9,8 @@ module DataFifoWrapper
 (
     input	WrClk_i,
 	input	RdClk_i,
-    input	Rst_i,
+    input	FifoRxRst_i,
+	input	FifoTxRst_i,
 	input   SmcAre_i,
 	input	SmcAwe_i,
 
@@ -50,7 +51,7 @@ module DataFifoWrapper
 //================================================================================
 
 FifoCtrl FifoCtrl_inst (
-	.ToFifoTxWriteVal_i	(!SmcAwe_i && toFifoVal_i),
+	.ToFifoTxWriteVal_i	(!SmcAwe_i && ToFifoVal_i),
 	.ToFifoTxReadVal_i (ToFifoTxReadVal_i),
 	.ToFifoRxWriteVal_i	(ToFifoRxWriteVal_i),
 	.ToFifoRxReadVal_i	(!SmcAre_i),

sources_1/new/Mux/DataMuxer.v

@@ -15,20 +15,20 @@ module SmcDataMux
 	// parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
 	// parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
 	
-	parameter	Fifo0WriteLsbAddr	=	12'h0+12'h0,
-	parameter	Fifo0WriteMsbAddr	=	12'h0+12'h2,
-	parameter	Fifo1WriteLsbAddr	=	12'h0+12'h4,
-	parameter	Fifo1WriteMsbAddr	=	12'h0+12'h6,
-	parameter	Fifo2WriteLsbAddr	=	12'h0+12'h8,
-	parameter	Fifo2WriteMsbAddr	=	12'h00+12'ha,
-	parameter	Fifo3WriteLsbAddr	=	12'h0+12'hc,
-	parameter	Fifo3WriteMsbAddr	=	12'h0+12'he,
-	parameter	Fifo4WriteLsbAddr	=	12'h0+12'h10,
-	parameter	Fifo4WriteMsbAddr	=	12'h190+12'h9,
-	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h10,
-	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'h11,
-	parameter	Fifo6WriteLsbAddr	=	12'h230+12'h12,
-	parameter	Fifo6WriteMsbAddr	=	12'h230+12'h13
+	parameter	Fifo0WriteLsbAddr	=	12'h0+12'h24,
+	parameter	Fifo0WriteMsbAddr	=	12'h0+12'h26,
+	parameter	Fifo1WriteLsbAddr	=	12'h50+12'h24,
+	parameter	Fifo1WriteMsbAddr	=	12'h50+12'h26,
+	parameter	Fifo2WriteLsbAddr	=	12'hf0+12'h24,
+	parameter	Fifo2WriteMsbAddr	=	12'hf0+12'h26,
+	parameter	Fifo3WriteLsbAddr	=	12'h140+12'h24,
+	parameter	Fifo3WriteMsbAddr	=	12'h140+12'h26,
+	parameter	Fifo4WriteLsbAddr	=	12'h190+12'h24,
+	parameter	Fifo4WriteMsbAddr	=	12'h190+12'h26,
+	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
+	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'h26,
+	parameter	Fifo6WriteLsbAddr	=	12'h230+12'h24,
+	parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
 )
 (
     input	Clk_i,
@@ -100,6 +100,7 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 				Fifo2WriteLsbAddr:	begin
 									ToFifoVal_o[2]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
+								end
 				Fifo2WriteMsbAddr:	begin
 									ToFifoVal_o[2]	<=	SmcVal_i;
 									ToFifoVal_o[3]	<=	1'b0;
@@ -120,6 +121,7 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 				Fifo5WriteLsbAddr:	begin
 									ToFifoVal_o[5]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
+								end
 				Fifo5WriteMsbAddr:	begin
 									ToFifoVal_o[5]	<=	SmcVal_i;
 									ToFifoVal_o[6]	<=	1'b0;

sources_1/new/S5443_3Top.v

@@ -638,7 +638,8 @@ generate
 			.WrClk_i	(gclk),
 			.RdClk_i	(spiClkBus[i]),
 			// .Rst_i		(spiSyncRst[i] | FifoRxRst[i]),
-			.Rst_i		(FifoRxRst[i]),
+			.FifoRxRst_i    (fifoRxRst[i]),
+            .FifoTxRst_i    (fifoTxRst[i]),
             .SmcAre_i   (SmcAre_i),
             .SmcAwe_i   (SmcAwe_i),
 	

sources_1/new/SpiR/SPIm.v

@@ -33,7 +33,7 @@ reg valToRxFifo1;
 reg [2:0] ssCnt;
 reg Ss;
 reg SSr;
-reg [7:0] mosiReg0;
+reg [31:0] mosiReg0;
 reg [3:0] ssNum;
 reg [2:0] delayCnt;
 reg stopFlag;