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@@ -111,21 +111,6 @@ reg [CmdRegWidth/2-1:0] Spi0RxFifoCtrlReg;
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reg [CmdRegWidth/2-1:0] Spi0TxFifoReg;
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reg [CmdRegWidth/2-1:0] Spi0RxFifoReg;
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-// (* dont_touch = "yes" *) reg [CmdRegWidth-1:0] TxFifoCtrlReg0Reg;
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-// reg [CmdRegWidth-1:0] RxFifoCtrlReg0Reg;
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-// reg [CmdRegWidth-1:0] TxFifoCtrlReg1Reg;
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-// reg [CmdRegWidth-1:0] RxFifoCtrlReg1Reg;
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-// reg [CmdRegWidth-1:0] TxFifoCtrlReg2Reg;
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-// reg [CmdRegWidth-1:0] RxFifoCtrlReg2Reg;
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-// reg [CmdRegWidth-1:0] TxFifoCtrlReg3Reg;
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-// reg [CmdRegWidth-1:0] RxFifoCtrlReg3Reg;
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-// reg [CmdRegWidth-1:0] TxFifoCtrlReg4Reg;
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-// reg [CmdRegWidth-1:0] RxFifoCtrlReg4Reg;
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-// reg [CmdRegWidth-1:0] TxFifoCtrlReg5Reg;
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-// reg [CmdRegWidth-1:0] RxFifoCtrlReg5Reg;
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-// reg [CmdRegWidth-1:0] TxFifoCtrlReg6Reg;
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-// reg [CmdRegWidth-1:0] RxFifoCtrlReg6Reg;
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-
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reg [CmdRegWidth/2-1:0] Spi1CtrlReg;
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reg [CmdRegWidth/2-1:0] Spi1ClkReg;
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@@ -357,44 +342,6 @@ localparam Debug0Addr = 12'hFF8;
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localparam Debug1Addr = 12'hFFC;
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//================================================================================
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-// always @(posedge Clk_i) begin
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-// if (Rst_i) begin
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-// TxFifoCtrlReg0Reg <= 0;
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-// RxFifoCtrlReg0Reg <= 0;
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-// TxFifoCtrlReg1Reg <= 0;
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-// RxFifoCtrlReg1Reg <= 0;
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-// TxFifoCtrlReg2Reg <= 0;
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-// RxFifoCtrlReg2Reg <= 0;
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-// TxFifoCtrlReg3Reg <= 0;
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-// RxFifoCtrlReg3Reg <= 0;
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-// TxFifoCtrlReg4Reg <= 0;
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-// RxFifoCtrlReg4Reg <= 0;
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-// TxFifoCtrlReg5Reg <= 0;
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-// RxFifoCtrlReg5Reg <= 0;
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-// TxFifoCtrlReg6Reg <= 0;
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-// RxFifoCtrlReg6Reg <= 0;
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-// end
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-// else begin
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-// TxFifoCtrlReg0Reg <= TxFifoCtrlReg0_i;
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-// RxFifoCtrlReg0Reg <= RxFifoCtrlReg0_i;
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-// TxFifoCtrlReg1Reg <= TxFifoCtrlReg1_i;
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-// RxFifoCtrlReg1Reg <= RxFifoCtrlReg1_i;
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-// TxFifoCtrlReg2Reg <= TxFifoCtrlReg2_i;
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-// RxFifoCtrlReg2Reg <= RxFifoCtrlReg2_i;
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-// TxFifoCtrlReg3Reg <= TxFifoCtrlReg3_i;
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-// RxFifoCtrlReg3Reg <= RxFifoCtrlReg3_i;
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-// TxFifoCtrlReg4Reg <= TxFifoCtrlReg4_i;
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-// RxFifoCtrlReg4Reg <= RxFifoCtrlReg4_i;
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-// TxFifoCtrlReg5Reg <= TxFifoCtrlReg5_i;
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-// RxFifoCtrlReg5Reg <= RxFifoCtrlReg5_i;
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-// TxFifoCtrlReg6Reg <= TxFifoCtrlReg6_i;
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-// RxFifoCtrlReg6Reg <= RxFifoCtrlReg6_i;
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-// end
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-// end
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-
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-
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-
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-
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always @(posedge Clk_i) begin
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if (!Rst_i) begin
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@@ -1032,692 +979,233 @@ always @(*) begin
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if (Rst_i) begin
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ansReg = 0;
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end else begin
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- case(beReg)
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- 0 : begin
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- case (Addr_i)
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- Spi0CtrlAddr : begin
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- ansReg = Spi0CtrlReg;
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- end
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- Spi0ClkAddr : begin
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- ansReg = Spi0ClkReg;
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- end
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- Spi0CsDelayAddr : begin
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- ansReg = Spi0CsDelayReg;
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- end
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- Spi0CsCtrlAddr : begin
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- ansReg = Spi0CsCtrlReg;
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- end
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- Spi0TxFifoCtrlAddrLsb : begin
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- ansReg = TxFifoCtrlReg0_i[15:0];
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- end
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- Spi0TxFifoCtrlAddrMsb : begin
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- ansReg = TxFifoCtrlReg0_i[31:16];
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- end
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- Spi0RxFifoCtrlAddrLsb : begin
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- ansReg = RxFifoCtrlReg0_i[15:0];
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- end
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- Spi0RxFifoCtrlAddrMsb : begin
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- ansReg = RxFifoCtrlReg0_i[31:16];
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- end
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- Spi0TxFifo : begin
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- ansReg = Spi0TxFifoReg;
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- end
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- Spi0RxFifo : begin
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- ansReg = Spi0RxFifoReg;
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- end
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- Spi1CtrlAddr : begin
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- ansReg = Spi1CtrlReg;
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- end
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- Spi1ClkAddr : begin
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- ansReg = Spi1ClkReg;
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- end
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- Spi1CsDelayAddr : begin
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- ansReg = Spi1CsDelayReg;
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- end
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- Spi1CsCtrlAddr : begin
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- ansReg = Spi1CsCtrlReg;
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- end
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- Spi1TxFifoCtrlAddrLsb : begin
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- ansReg = TxFifoCtrlReg1_i[15:0];
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- end
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- Spi1TxFifoCtrlAddrMsb : begin
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- ansReg = TxFifoCtrlReg1_i[31:16];
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- end
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- Spi1RxFifoCtrlAddrLsb : begin
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- ansReg = RxFifoCtrlReg1_i[15:0];
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- end
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- Spi1RxFifoCtrlAddrMsb : begin
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- ansReg = RxFifoCtrlReg1_i[31:16];
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- end
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- Spi1TxFifo : begin
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- ansReg = Spi1TxFifoReg;
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- end
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- Spi1RxFifo : begin
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- ansReg = Spi1RxFifoReg;
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- end
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- Spi2CtrlAddr : begin
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- ansReg = Spi2CtrlReg;
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- end
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- Spi2ClkAddr : begin
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- ansReg = Spi2ClkReg;
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- end
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- Spi2CsDelayAddr : begin
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- ansReg = Spi2CsDelayReg;
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- end
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- Spi2CsCtrlAddr : begin
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- ansReg = Spi2CsCtrlReg;
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- end
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- Spi2TxFifoCtrlAddrLsb : begin
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- ansReg = TxFifoCtrlReg2_i[15:0];
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- end
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- Spi2TxFifoCtrlAddrMsb : begin
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- ansReg = TxFifoCtrlReg2_i[31:16];
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- end
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- Spi2RxFifoCtrlAddrLsb : begin
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- ansReg = RxFifoCtrlReg2_i[15:0];
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- end
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- Spi2RxFifoCtrlAddrMsb : begin
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- ansReg = RxFifoCtrlReg2_i[31:16];
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- end
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- Spi2TxFifo : begin
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- ansReg = Spi2TxFifoReg;
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- end
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- Spi2RxFifo : begin
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- ansReg = Spi2RxFifoReg;
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- end
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- Spi3CtrlAddr : begin
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- ansReg = Spi3CtrlReg;
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- end
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- Spi3ClkAddr : begin
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- ansReg = Spi3ClkReg;
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- end
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- Spi3CsDelayAddr : begin
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- ansReg = Spi3CsDelayReg;
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- end
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- Spi3CsCtrlAddr : begin
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- ansReg = Spi3CsCtrlReg;
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- end
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- Spi3TxFifoCtrlAddrLsb : begin
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- ansReg = TxFifoCtrlReg3_i[15:0];
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- end
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- Spi3TxFifoCtrlAddrMsb : begin
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- ansReg = TxFifoCtrlReg3_i[31:16];
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- end
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- Spi3RxFifoCtrlAddrLsb : begin
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- ansReg = RxFifoCtrlReg3_i[15:0];
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- end
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- Spi3RxFifoCtrlAddrMsb : begin
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- ansReg = RxFifoCtrlReg3_i[31:16];
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- end
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- Spi3TxFifo : begin
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- ansReg = Spi3TxFifoReg;
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- end
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- Spi3RxFifo : begin
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- ansReg = Spi3RxFifoReg;
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- end
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- Spi4CtrlAddr : begin
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- ansReg = Spi4CtrlReg;
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- end
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- Spi4ClkAddr : begin
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- ansReg = Spi4ClkReg;
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- end
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- Spi4CsDelayAddr : begin
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- ansReg = Spi4CsDelayReg;
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- end
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- Spi4CsCtrlAddr : begin
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- ansReg = Spi4CsCtrlReg;
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- end
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- Spi4TxFifoCtrlAddrLsb : begin
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- ansReg = TxFifoCtrlReg4_i[15:0];
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- end
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- Spi4TxFifoCtrlAddrMsb : begin
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- ansReg = TxFifoCtrlReg4_i[31:16];
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- end
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- Spi4RxFifoCtrlAddrLsb : begin
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- ansReg = RxFifoCtrlReg4_i[15:0];
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- end
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- Spi4RxFifoCtrlAddrMsb : begin
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- ansReg = RxFifoCtrlReg4_i[31:16];
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- end
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- Spi4TxFifo : begin
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- ansReg = Spi4TxFifoReg;
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- end
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- Spi4RxFifo : begin
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- ansReg = Spi4RxFifoReg;
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- end
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- Spi5CtrlAddr : begin
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- ansReg = Spi5CtrlReg;
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- end
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- Spi5ClkAddr : begin
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- ansReg = Spi5ClkReg;
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- end
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- Spi5CsDelayAddr : begin
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- ansReg = Spi5CsDelayReg;
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- end
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- Spi5CsCtrlAddr : begin
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- ansReg = Spi5CsCtrlReg;
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- end
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- Spi5TxFifoCtrlAddrLsb : begin
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- ansReg = TxFifoCtrlReg5_i[15:0];
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- end
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- Spi5TxFifoCtrlAddrMsb : begin
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- ansReg = TxFifoCtrlReg5_i[31:16];
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- end
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- Spi5RxFifoCtrlAddrLsb : begin
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- ansReg = RxFifoCtrlReg5_i[15:0];
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- end
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- Spi5RxFifoCtrlAddrMsb : begin
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- ansReg = RxFifoCtrlReg5_i[31:16];
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- end
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- Spi5TxFifo : begin
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- ansReg = Spi5TxFifoReg;
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- end
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- Spi5RxFifo : begin
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- ansReg = Spi5RxFifoReg;
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- end
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- Spi6CtrlAddr : begin
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- ansReg = Spi6CtrlReg;
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- end
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- Spi6ClkAddr : begin
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- ansReg = Spi6ClkReg;
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- end
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- Spi6CsDelayAddr : begin
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- ansReg = Spi6CsDelayReg;
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- end
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- Spi6CsCtrlAddr : begin
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- ansReg = Spi6CsCtrlReg;
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- end
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- Spi6TxFifoCtrlAddrLsb : begin
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- ansReg = TxFifoCtrlReg6_i[15:0];
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- end
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- Spi6TxFifoCtrlAddrMsb : begin
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- ansReg = TxFifoCtrlReg6_i[31:16];
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- end
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- Spi6RxFifoCtrlAddrLsb : begin
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- ansReg = RxFifoCtrlReg6_i[15:0];
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- end
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- Spi6RxFifoCtrlAddrMsb : begin
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- ansReg = RxFifoCtrlReg6_i[31:16];
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- end
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- Spi6TxFifo : begin
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- ansReg = Spi6TxFifoReg;
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- end
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- Spi6RxFifo : begin
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- ansReg = Spi6RxFifoReg;
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- end
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- SpiTxRxEn : begin
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- ansReg = SpiTxRxEnReg;
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- end
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- GPIOCtrlAddr : begin
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- ansReg = GPIOAReg;
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- end
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- GPIOCtrlAddrS : begin
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- ansReg = GPIOARegS;
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- end
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- Debug0Addr : begin
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- ansReg = LedReg;
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- end
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- endcase
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- end
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- 1 : begin
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- case (Addr_i)
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- Spi0CtrlAddr : begin
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- ansReg = Spi0CtrlReg[15:8];
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- end
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- Spi0ClkAddr : begin
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- ansReg = Spi0ClkReg[15:8];
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- end
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- Spi0CsDelayAddr : begin
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- ansReg = Spi0CsDelayReg[15:8];
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- end
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- Spi0CsCtrlAddr : begin
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- ansReg = Spi0CsCtrlReg[15:8];
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- end
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- Spi0TxFifoCtrlAddrLsb : begin
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- ansReg = TxFifoCtrlReg0_i[15:8];
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- end
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- Spi0TxFifoCtrlAddrMsb : begin
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- ansReg = TxFifoCtrlReg0_i[31:24];
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- end
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- Spi0RxFifoCtrlAddrLsb : begin
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- ansReg = RxFifoCtrlReg0_i[15:8];
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- end
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- Spi0RxFifoCtrlAddrMsb : begin
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- ansReg = RxFifoCtrlReg0_i[31:24];
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- end
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- Spi0TxFifo : begin
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- ansReg = Spi0TxFifoReg[15:8];
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- end
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- Spi0RxFifo : begin
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- ansReg = Spi0RxFifoReg[15:8];
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- end
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- Spi1CtrlAddr : begin
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- ansReg = Spi1CtrlReg[15:8];
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- end
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- Spi1ClkAddr : begin
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- ansReg = Spi1ClkReg[15:8];
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- end
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- Spi1CsDelayAddr : begin
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- ansReg = Spi1CsDelayReg[15:8];
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- end
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- Spi1CsCtrlAddr : begin
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- ansReg = Spi1CsCtrlReg[15:8];
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- end
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- Spi1TxFifoCtrlAddrLsb : begin
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- ansReg = TxFifoCtrlReg1_i[15:8];
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- end
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- Spi1TxFifoCtrlAddrMsb : begin
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- ansReg = TxFifoCtrlReg1_i[31:24];
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- end
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- Spi1RxFifoCtrlAddrLsb : begin
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- ansReg = RxFifoCtrlReg1_i[15:8];
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- end
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- Spi1RxFifoCtrlAddrMsb : begin
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- ansReg = RxFifoCtrlReg1_i[31:24];
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- end
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- Spi1TxFifo : begin
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- ansReg = Spi1TxFifoReg[15:8];
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- end
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- Spi1RxFifo : begin
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- ansReg = Spi1RxFifoReg[15:8];
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- end
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- Spi2CtrlAddr : begin
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- ansReg = Spi2CtrlReg[15:8];
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- end
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- Spi2ClkAddr : begin
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- ansReg = Spi2ClkReg[15:8];
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- end
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- Spi2CsDelayAddr : begin
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- ansReg = Spi2CsDelayReg[15:8];
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- end
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- Spi2CsCtrlAddr : begin
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- ansReg = Spi2CsCtrlReg[15:8];
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- end
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- Spi2TxFifoCtrlAddrLsb : begin
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- ansReg = TxFifoCtrlReg2_i[15:8];
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- end
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- Spi2TxFifoCtrlAddrMsb : begin
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- ansReg = TxFifoCtrlReg2_i[31:24];
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- end
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- Spi2RxFifoCtrlAddrLsb : begin
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- ansReg = RxFifoCtrlReg2_i[15:8];
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- end
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- Spi2RxFifoCtrlAddrMsb : begin
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- ansReg = RxFifoCtrlReg2_i[31:24];
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- end
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- Spi2TxFifo : begin
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- ansReg = Spi2TxFifoReg[15:8];
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- end
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- Spi2RxFifo : begin
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- ansReg = Spi2RxFifoReg[15:8];
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- end
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- Spi3CtrlAddr : begin
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- ansReg = Spi3CtrlReg[15:8];
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- end
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- Spi3ClkAddr : begin
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- ansReg = Spi3ClkReg[15:8];
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- end
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|
|
- Spi3CsDelayAddr : begin
|
|
|
- ansReg = Spi3CsDelayReg[15:8];
|
|
|
- end
|
|
|
- Spi3CsCtrlAddr : begin
|
|
|
- ansReg = Spi3CsCtrlReg[15:8];
|
|
|
- end
|
|
|
- Spi3TxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = TxFifoCtrlReg3_i[15:8];
|
|
|
- end
|
|
|
- Spi3TxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = TxFifoCtrlReg3_i[31:24];
|
|
|
- end
|
|
|
- Spi3RxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = RxFifoCtrlReg3_i[15:8];
|
|
|
- end
|
|
|
- Spi3RxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = RxFifoCtrlReg3_i[31:24];
|
|
|
- end
|
|
|
- Spi3TxFifo : begin
|
|
|
- ansReg = Spi3TxFifoReg[15:8];
|
|
|
- end
|
|
|
- Spi3RxFifo : begin
|
|
|
- ansReg = Spi3RxFifoReg[15:8];
|
|
|
- end
|
|
|
- Spi4CtrlAddr : begin
|
|
|
- ansReg = Spi4CtrlReg[15:8];
|
|
|
- end
|
|
|
- Spi4ClkAddr : begin
|
|
|
- ansReg = Spi4ClkReg[15:8];
|
|
|
- end
|
|
|
- Spi4CsDelayAddr : begin
|
|
|
- ansReg = Spi4CsDelayReg[15:8];
|
|
|
- end
|
|
|
- Spi4CsCtrlAddr : begin
|
|
|
- ansReg = Spi4CsCtrlReg[15:8];
|
|
|
- end
|
|
|
- Spi4TxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = TxFifoCtrlReg4_i[15:8];
|
|
|
- end
|
|
|
- Spi4TxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = TxFifoCtrlReg4_i[31:24];
|
|
|
- end
|
|
|
- Spi4RxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = RxFifoCtrlReg4_i[15:8];
|
|
|
- end
|
|
|
- Spi4RxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = RxFifoCtrlReg4_i[31:24];
|
|
|
- end
|
|
|
- Spi4TxFifo : begin
|
|
|
- ansReg = Spi4TxFifoReg[15:8];
|
|
|
- end
|
|
|
- Spi4RxFifo : begin
|
|
|
- ansReg = Spi4RxFifoReg[15:8];
|
|
|
- end
|
|
|
- Spi5CtrlAddr : begin
|
|
|
- ansReg = Spi5CtrlReg[15:8];
|
|
|
- end
|
|
|
- Spi5ClkAddr : begin
|
|
|
- ansReg = Spi5ClkReg[15:8];
|
|
|
- end
|
|
|
- Spi5CsDelayAddr : begin
|
|
|
- ansReg = Spi5CsDelayReg[15:8];
|
|
|
- end
|
|
|
- Spi5CsCtrlAddr : begin
|
|
|
- ansReg = Spi5CsCtrlReg[15:8];
|
|
|
- end
|
|
|
- Spi5TxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = TxFifoCtrlReg5_i[15:8];
|
|
|
- end
|
|
|
- Spi5TxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = TxFifoCtrlReg5_i[31:24];
|
|
|
- end
|
|
|
- Spi5RxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = RxFifoCtrlReg5_i[15:8];
|
|
|
- end
|
|
|
- Spi5RxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = RxFifoCtrlReg5_i[31:24];
|
|
|
- end
|
|
|
- Spi5TxFifo : begin
|
|
|
- ansReg = Spi5TxFifoReg[15:8];
|
|
|
- end
|
|
|
- Spi5RxFifo : begin
|
|
|
- ansReg = Spi5RxFifoReg[15:8];
|
|
|
- end
|
|
|
- Spi6CtrlAddr : begin
|
|
|
- ansReg = Spi6CtrlReg[15:8];
|
|
|
- end
|
|
|
- Spi6ClkAddr : begin
|
|
|
- ansReg = Spi6ClkReg[15:8];
|
|
|
- end
|
|
|
- Spi6CsDelayAddr : begin
|
|
|
- ansReg = Spi6CsDelayReg[15:8];
|
|
|
- end
|
|
|
- Spi6CsCtrlAddr : begin
|
|
|
- ansReg = Spi6CsCtrlReg[15:8];
|
|
|
- end
|
|
|
- Spi6TxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = TxFifoCtrlReg6_i[15:8];
|
|
|
- end
|
|
|
- Spi6TxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = TxFifoCtrlReg6_i[31:24];
|
|
|
- end
|
|
|
- Spi6RxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = RxFifoCtrlReg6_i[15:8];
|
|
|
- end
|
|
|
- Spi6RxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = RxFifoCtrlReg6_i[31:24];
|
|
|
- end
|
|
|
- Spi6TxFifo : begin
|
|
|
- ansReg = Spi6TxFifoReg[15:8];
|
|
|
- end
|
|
|
- Spi6RxFifo : begin
|
|
|
- ansReg = Spi6RxFifoReg[15:8];
|
|
|
- end
|
|
|
- SpiTxRxEn : begin
|
|
|
- ansReg = SpiTxRxEnReg[15:8];
|
|
|
- end
|
|
|
- GPIOCtrlAddr : begin
|
|
|
- ansReg = GPIOAReg[15:8];
|
|
|
- end
|
|
|
- GPIOCtrlAddrS : begin
|
|
|
- ansReg = GPIOARegS[15:8];
|
|
|
- end
|
|
|
- Debug0Addr : begin
|
|
|
- ansReg = LedReg[15:8];
|
|
|
- end
|
|
|
- endcase
|
|
|
- end
|
|
|
- 2 : begin
|
|
|
- case (Addr_i)
|
|
|
- Spi0CtrlAddr : begin
|
|
|
- ansReg = Spi0CtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi0ClkAddr : begin
|
|
|
- ansReg = Spi0ClkReg[7:0];
|
|
|
- end
|
|
|
- Spi0CsDelayAddr : begin
|
|
|
- ansReg = Spi0CsDelayReg[7:0];
|
|
|
- end
|
|
|
- Spi0CsCtrlAddr : begin
|
|
|
- ansReg = Spi0CsCtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi0TxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = TxFifoCtrlReg0_i[7:0];
|
|
|
- end
|
|
|
- Spi0TxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = TxFifoCtrlReg0_i[23:16];
|
|
|
- end
|
|
|
- Spi0RxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = RxFifoCtrlReg0_i[7:0];
|
|
|
- end
|
|
|
- Spi0RxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = RxFifoCtrlReg0_i[23:16];
|
|
|
- end
|
|
|
- Spi0TxFifo : begin
|
|
|
- ansReg = Spi0TxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi0RxFifo : begin
|
|
|
- ansReg = Spi0RxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi1CtrlAddr : begin
|
|
|
- ansReg = Spi1CtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi1ClkAddr : begin
|
|
|
- ansReg = Spi1ClkReg[7:0];
|
|
|
- end
|
|
|
- Spi1CsDelayAddr : begin
|
|
|
- ansReg = Spi1CsDelayReg[7:0];
|
|
|
- end
|
|
|
- Spi1CsCtrlAddr : begin
|
|
|
- ansReg = Spi1CsCtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi1TxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = TxFifoCtrlReg1_i[7:0];
|
|
|
- end
|
|
|
- Spi1TxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = TxFifoCtrlReg1_i[23:16];
|
|
|
- end
|
|
|
- Spi1RxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = RxFifoCtrlReg1_i[7:0];
|
|
|
- end
|
|
|
- Spi1RxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = RxFifoCtrlReg1_i[23:16];
|
|
|
- end
|
|
|
- Spi1TxFifo : begin
|
|
|
- ansReg = Spi1TxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi1RxFifo : begin
|
|
|
- ansReg = Spi1RxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi2CtrlAddr : begin
|
|
|
- ansReg = Spi2CtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi2ClkAddr : begin
|
|
|
- ansReg = Spi2ClkReg[7:0];
|
|
|
- end
|
|
|
- Spi2CsDelayAddr : begin
|
|
|
- ansReg = Spi2CsDelayReg[7:0];
|
|
|
- end
|
|
|
- Spi2CsCtrlAddr : begin
|
|
|
- ansReg = Spi2CsCtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi2TxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = TxFifoCtrlReg2_i[7:0];
|
|
|
- end
|
|
|
- Spi2TxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = TxFifoCtrlReg2_i[23:16];
|
|
|
- end
|
|
|
- Spi2RxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = RxFifoCtrlReg2_i[7:0];
|
|
|
- end
|
|
|
- Spi2RxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = RxFifoCtrlReg2_i[23:16];
|
|
|
- end
|
|
|
- Spi2TxFifo : begin
|
|
|
- ansReg = Spi2TxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi2RxFifo : begin
|
|
|
- ansReg = Spi2RxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi3CtrlAddr : begin
|
|
|
- ansReg = Spi3CtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi3ClkAddr : begin
|
|
|
- ansReg = Spi3ClkReg[7:0];
|
|
|
- end
|
|
|
- Spi3CsDelayAddr : begin
|
|
|
- ansReg = Spi3CsDelayReg[7:0];
|
|
|
- end
|
|
|
- Spi3CsCtrlAddr : begin
|
|
|
- ansReg = Spi3CsCtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi3TxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = TxFifoCtrlReg3_i[7:0];
|
|
|
- end
|
|
|
- Spi3TxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = TxFifoCtrlReg3_i[23:16];
|
|
|
- end
|
|
|
- Spi3RxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = RxFifoCtrlReg3_i[7:0];
|
|
|
- end
|
|
|
- Spi3RxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = RxFifoCtrlReg3_i[23:16];
|
|
|
- end
|
|
|
- Spi3TxFifo : begin
|
|
|
- ansReg = Spi3TxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi3RxFifo : begin
|
|
|
- ansReg = Spi3RxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi4CtrlAddr : begin
|
|
|
- ansReg = Spi4CtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi4ClkAddr : begin
|
|
|
- ansReg = Spi4ClkReg[7:0];
|
|
|
- end
|
|
|
- Spi4CsDelayAddr : begin
|
|
|
- ansReg = Spi4CsDelayReg[7:0];
|
|
|
- end
|
|
|
- Spi4CsCtrlAddr : begin
|
|
|
- ansReg = Spi4CsCtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi4TxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = TxFifoCtrlReg4_i[7:0];
|
|
|
- end
|
|
|
- Spi4TxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = TxFifoCtrlReg4_i[23:16];
|
|
|
- end
|
|
|
- Spi4RxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = RxFifoCtrlReg4_i[7:0];
|
|
|
- end
|
|
|
- Spi4RxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = RxFifoCtrlReg4_i[23:16];
|
|
|
- end
|
|
|
- Spi4TxFifo : begin
|
|
|
- ansReg = Spi4TxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi4RxFifo : begin
|
|
|
- ansReg = Spi4RxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi5CtrlAddr : begin
|
|
|
- ansReg = Spi5CtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi5ClkAddr : begin
|
|
|
- ansReg = Spi5ClkReg[7:0];
|
|
|
- end
|
|
|
- Spi5CsDelayAddr : begin
|
|
|
- ansReg = Spi5CsDelayReg[7:0];
|
|
|
- end
|
|
|
- Spi5CsCtrlAddr : begin
|
|
|
- ansReg = Spi5CsCtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi5TxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = TxFifoCtrlReg5_i[7:0];
|
|
|
- end
|
|
|
- Spi5TxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = TxFifoCtrlReg5_i[23:16];
|
|
|
- end
|
|
|
- Spi5RxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = RxFifoCtrlReg5_i[7:0];
|
|
|
- end
|
|
|
- Spi5RxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = RxFifoCtrlReg5_i[23:16];
|
|
|
- end
|
|
|
- Spi5TxFifo : begin
|
|
|
- ansReg = Spi5TxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi5RxFifo : begin
|
|
|
- ansReg = Spi5RxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi6CtrlAddr : begin
|
|
|
- ansReg = Spi6CtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi6ClkAddr : begin
|
|
|
- ansReg = Spi6ClkReg[7:0];
|
|
|
- end
|
|
|
- Spi6CsDelayAddr : begin
|
|
|
- ansReg = Spi6CsDelayReg[7:0];
|
|
|
- end
|
|
|
- Spi6CsCtrlAddr : begin
|
|
|
- ansReg = Spi6CsCtrlReg[7:0];
|
|
|
- end
|
|
|
- Spi6TxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = TxFifoCtrlReg6_i[7:0];
|
|
|
- end
|
|
|
- Spi6TxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = TxFifoCtrlReg6_i[23:16];
|
|
|
- end
|
|
|
- Spi6RxFifoCtrlAddrLsb : begin
|
|
|
- ansReg = RxFifoCtrlReg6_i[7:0];
|
|
|
- end
|
|
|
- Spi6RxFifoCtrlAddrMsb : begin
|
|
|
- ansReg = RxFifoCtrlReg6_i[23:16];
|
|
|
- end
|
|
|
- Spi6TxFifo : begin
|
|
|
- ansReg = Spi6TxFifoReg[7:0];
|
|
|
- end
|
|
|
- Spi6RxFifo : begin
|
|
|
- ansReg = Spi6RxFifoReg[7:0];
|
|
|
- end
|
|
|
- SpiTxRxEn : begin
|
|
|
- ansReg = SpiTxRxEnReg[7:0];
|
|
|
- end
|
|
|
- GPIOCtrlAddr : begin
|
|
|
- ansReg = GPIOAReg[7:0];
|
|
|
- end
|
|
|
- GPIOCtrlAddrS : begin
|
|
|
- ansReg = GPIOARegS[7:0];
|
|
|
- end
|
|
|
- Debug0Addr : begin
|
|
|
- ansReg = LedReg[7:0];
|
|
|
- end
|
|
|
- default : begin
|
|
|
- ansReg = 0;
|
|
|
- end
|
|
|
- endcase
|
|
|
- end
|
|
|
- default:begin
|
|
|
- ansReg = 0;
|
|
|
- end
|
|
|
- endcase
|
|
|
+ case (Addr_i)
|
|
|
+ Spi0CtrlAddr : begin
|
|
|
+ ansReg = Spi0CtrlReg;
|
|
|
+ end
|
|
|
+ Spi0ClkAddr : begin
|
|
|
+ ansReg = Spi0ClkReg;
|
|
|
+ end
|
|
|
+ Spi0CsDelayAddr : begin
|
|
|
+ ansReg = Spi0CsDelayReg;
|
|
|
+ end
|
|
|
+ Spi0CsCtrlAddr : begin
|
|
|
+ ansReg = Spi0CsCtrlReg;
|
|
|
+ end
|
|
|
+ Spi0TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg0_i[15:0];
|
|
|
+ end
|
|
|
+ Spi0TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg0_i[31:16];
|
|
|
+ end
|
|
|
+ Spi0RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg0_i[15:0];
|
|
|
+ end
|
|
|
+ Spi0RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg0_i[31:16];
|
|
|
+ end
|
|
|
+ Spi0TxFifo : begin
|
|
|
+ ansReg = Spi0TxFifoReg;
|
|
|
+ end
|
|
|
+ Spi0RxFifo : begin
|
|
|
+ ansReg = Spi0RxFifoReg;
|
|
|
+ end
|
|
|
+ Spi1CtrlAddr : begin
|
|
|
+ ansReg = Spi1CtrlReg;
|
|
|
+ end
|
|
|
+ Spi1ClkAddr : begin
|
|
|
+ ansReg = Spi1ClkReg;
|
|
|
+ end
|
|
|
+ Spi1CsDelayAddr : begin
|
|
|
+ ansReg = Spi1CsDelayReg;
|
|
|
+ end
|
|
|
+ Spi1CsCtrlAddr : begin
|
|
|
+ ansReg = Spi1CsCtrlReg;
|
|
|
+ end
|
|
|
+ Spi1TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg1_i[15:0];
|
|
|
+ end
|
|
|
+ Spi1TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg1_i[31:16];
|
|
|
+ end
|
|
|
+ Spi1RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg1_i[15:0];
|
|
|
+ end
|
|
|
+ Spi1RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg1_i[31:16];
|
|
|
+ end
|
|
|
+ Spi1TxFifo : begin
|
|
|
+ ansReg = Spi1TxFifoReg;
|
|
|
+ end
|
|
|
+ Spi1RxFifo : begin
|
|
|
+ ansReg = Spi1RxFifoReg;
|
|
|
+ end
|
|
|
+ Spi2CtrlAddr : begin
|
|
|
+ ansReg = Spi2CtrlReg;
|
|
|
+ end
|
|
|
+ Spi2ClkAddr : begin
|
|
|
+ ansReg = Spi2ClkReg;
|
|
|
+ end
|
|
|
+ Spi2CsDelayAddr : begin
|
|
|
+ ansReg = Spi2CsDelayReg;
|
|
|
+ end
|
|
|
+ Spi2CsCtrlAddr : begin
|
|
|
+ ansReg = Spi2CsCtrlReg;
|
|
|
+ end
|
|
|
+ Spi2TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg2_i[15:0];
|
|
|
+ end
|
|
|
+ Spi2TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg2_i[31:16];
|
|
|
+ end
|
|
|
+ Spi2RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg2_i[15:0];
|
|
|
+ end
|
|
|
+ Spi2RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg2_i[31:16];
|
|
|
+ end
|
|
|
+ Spi2TxFifo : begin
|
|
|
+ ansReg = Spi2TxFifoReg;
|
|
|
+ end
|
|
|
+ Spi2RxFifo : begin
|
|
|
+ ansReg = Spi2RxFifoReg;
|
|
|
+ end
|
|
|
+ Spi3CtrlAddr : begin
|
|
|
+ ansReg = Spi3CtrlReg;
|
|
|
+ end
|
|
|
+ Spi3ClkAddr : begin
|
|
|
+ ansReg = Spi3ClkReg;
|
|
|
+ end
|
|
|
+ Spi3CsDelayAddr : begin
|
|
|
+ ansReg = Spi3CsDelayReg;
|
|
|
+ end
|
|
|
+ Spi3CsCtrlAddr : begin
|
|
|
+ ansReg = Spi3CsCtrlReg;
|
|
|
+ end
|
|
|
+ Spi3TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg3_i[15:0];
|
|
|
+ end
|
|
|
+ Spi3TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg3_i[31:16];
|
|
|
+ end
|
|
|
+ Spi3RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg3_i[15:0];
|
|
|
+ end
|
|
|
+ Spi3RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg3_i[31:16];
|
|
|
+ end
|
|
|
+ Spi3TxFifo : begin
|
|
|
+ ansReg = Spi3TxFifoReg;
|
|
|
+ end
|
|
|
+ Spi3RxFifo : begin
|
|
|
+ ansReg = Spi3RxFifoReg;
|
|
|
+ end
|
|
|
+ Spi4CtrlAddr : begin
|
|
|
+ ansReg = Spi4CtrlReg;
|
|
|
+ end
|
|
|
+ Spi4ClkAddr : begin
|
|
|
+ ansReg = Spi4ClkReg;
|
|
|
+ end
|
|
|
+ Spi4CsDelayAddr : begin
|
|
|
+ ansReg = Spi4CsDelayReg;
|
|
|
+ end
|
|
|
+ Spi4CsCtrlAddr : begin
|
|
|
+ ansReg = Spi4CsCtrlReg;
|
|
|
+ end
|
|
|
+ Spi4TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg4_i[15:0];
|
|
|
+ end
|
|
|
+ Spi4TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg4_i[31:16];
|
|
|
+ end
|
|
|
+ Spi4RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg4_i[15:0];
|
|
|
+ end
|
|
|
+ Spi4RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg4_i[31:16];
|
|
|
+ end
|
|
|
+ Spi4TxFifo : begin
|
|
|
+ ansReg = Spi4TxFifoReg;
|
|
|
+ end
|
|
|
+ Spi4RxFifo : begin
|
|
|
+ ansReg = Spi4RxFifoReg;
|
|
|
+ end
|
|
|
+ Spi5CtrlAddr : begin
|
|
|
+ ansReg = Spi5CtrlReg;
|
|
|
+ end
|
|
|
+ Spi5ClkAddr : begin
|
|
|
+ ansReg = Spi5ClkReg;
|
|
|
+ end
|
|
|
+ Spi5CsDelayAddr : begin
|
|
|
+ ansReg = Spi5CsDelayReg;
|
|
|
+ end
|
|
|
+ Spi5CsCtrlAddr : begin
|
|
|
+ ansReg = Spi5CsCtrlReg;
|
|
|
+ end
|
|
|
+ Spi5TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg5_i[15:0];
|
|
|
+ end
|
|
|
+ Spi5TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg5_i[31:16];
|
|
|
+ end
|
|
|
+ Spi5RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg5_i[15:0];
|
|
|
+ end
|
|
|
+ Spi5RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg5_i[31:16];
|
|
|
+ end
|
|
|
+ Spi5TxFifo : begin
|
|
|
+ ansReg = Spi5TxFifoReg;
|
|
|
+ end
|
|
|
+ Spi5RxFifo : begin
|
|
|
+ ansReg = Spi5RxFifoReg;
|
|
|
+ end
|
|
|
+ Spi6CtrlAddr : begin
|
|
|
+ ansReg = Spi6CtrlReg;
|
|
|
+ end
|
|
|
+ Spi6ClkAddr : begin
|
|
|
+ ansReg = Spi6ClkReg;
|
|
|
+ end
|
|
|
+ Spi6CsDelayAddr : begin
|
|
|
+ ansReg = Spi6CsDelayReg;
|
|
|
+ end
|
|
|
+ Spi6CsCtrlAddr : begin
|
|
|
+ ansReg = Spi6CsCtrlReg;
|
|
|
+ end
|
|
|
+ Spi6TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg6_i[15:0];
|
|
|
+ end
|
|
|
+ Spi6TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg6_i[31:16];
|
|
|
+ end
|
|
|
+ Spi6RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg6_i[15:0];
|
|
|
+ end
|
|
|
+ Spi6RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg6_i[31:16];
|
|
|
+ end
|
|
|
+ Spi6TxFifo : begin
|
|
|
+ ansReg = Spi6TxFifoReg;
|
|
|
+ end
|
|
|
+ Spi6RxFifo : begin
|
|
|
+ ansReg = Spi6RxFifoReg;
|
|
|
+ end
|
|
|
+ SpiTxRxEn : begin
|
|
|
+ ansReg = SpiTxRxEnReg;
|
|
|
+ end
|
|
|
+ GPIOCtrlAddr : begin
|
|
|
+ ansReg = GPIOAReg;
|
|
|
+ end
|
|
|
+ GPIOCtrlAddrS : begin
|
|
|
+ ansReg = GPIOARegS;
|
|
|
+ end
|
|
|
+ Debug0Addr : begin
|
|
|
+ ansReg = LedReg;
|
|
|
+ end
|
|
|
+ default : begin
|
|
|
+ ansReg = 0;
|
|
|
+ end
|
|
|
+ endcase
|
|
|
end
|
|
|
end
|
|
|
|
Anatoliy Chigirinskiy