RegMap and Top changes

AdcInit/AdcInitInterface.v

@@ -1,94 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// company: 
-// engineer: 
-// 
-// create date:    11:56:45 07/11/2019 
-// design name: 
-// module name:    adc_init_interface 
-// project name: 
-// target devices: 
-// tool versions: 
-// description: 
-//
-// dependencies: 
-//
-// revision: 
-// revision 0.01 - file created
-// additional comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-module	AdcInitInterface	
-#(
-	parameter	DelayValue		=	24000,
-	parameter	LengthWidth		=	2000,
-	parameter	DataWidth		=	24,
-	parameter	DataNum			=	26
-)
-(
-    input	wire	Clk_i,
-	input	wire	Rst_i,
-	
-	output	wire	AdcMosi_o,
-	output	wire	AdcClk_o,
-	output	wire	AdcCs_o,
-	output	wire	AdcRst_o
-);
-//================================================================================
-//  reg/wire
-//================================================================================	
-	wire			adcRstDone;
-	wire			adcFilteredRst;
-//================================================================================
-//  instantiations
-//================================================================================	
-
-ResetFilter #(
-    .STAGE_NUM      (4),
-    .RESET_FRONT    ("RISING")
-) 
-adcResetFilter 
-(
-    .clk_i          (Clk_i),
-    .rst_i          (Rst_i),
-    .perm_i         (1'b0),
-    .filtered_rst_o (adcFilteredRst)
-);
-
-AdcInitRst
-#(
-	.DELAY_VALUE    (DelayValue),	//задержка перед выдачей reset'а
-	.LENGTH_WIDTH   (LengthWidth)		//длительность сигнала reset
-) 
-AdcInitRst 
-(
-	.clk_i      (Clk_i),
-	.rst_i      (adcFilteredRst),
-	.signal_o   (AdcRst_o),
-	.done_o     (adcRstDone)
-);
-
-PeriphSpiInit 
-#(
-	.DATA_WIDTH             (DataWidth),
-	.DATA_NUM               (DataNum), 
-	.ROM_INIT_FILE          ("C:/Users/User/Desktop/4portCompact/S5443/S5443_M/S5443.srcs/sources_1/new/AdcInit/initFiles/AdcInitData.txt"),
-	.FILE_DATA_BASE         ("HEX"),
-	.SPI_CLK_DIVISOR_POWER  (4),
-	.SPI_CPOL               (0),
-	.SPI_CPHA               (0),
-	.SPI_DATA_DIRECTION     ("MSB"),
-	.SPI_EN_START_DELAY     ("YES")
-) 
-PeriphSpiInitController 
-(
-	.clk_i                  (Clk_i),
-	.rst_i                  (adcFilteredRst),
-	.enable_i               (adcRstDone),
-	.mosi_o                 (AdcMosi_o),
-	.sck_o                  (AdcClk_o),
-	.ss_o                   (AdcCs_o),
-	.done_o                 ()
-);
-
-endmodule

AdcInit/AdcInitRst.v

@@ -1,130 +0,0 @@
-module AdcInitRst (
-    clk_i,
-    rst_i,
-
-    signal_o,
-    done_o
-);
-
-//================================================================================
-//
-//  FUNCTIONS
-//
-//================================================================================
-
-    function integer bit_num;
-        input integer value;
-        begin
-            bit_num = 0;
-            while (value > 0) begin
-                value   = value >> 1;
-                bit_num = bit_num + 1;
-            end
-        end
-    endfunction
-
-//================================================================================
-//
-//  PARAMETER/LOCALPARAM
-//
-//================================================================================
-
-    parameter   DELAY_VALUE     = 24000;
-    parameter   LENGTH_WIDTH    = 2;
-
-    localparam  DELAY_CNT_W = bit_num(DELAY_VALUE);
-
-//================================================================================
-//
-//  PORTS
-//
-//================================================================================
-
-    input           clk_i;
-    input           rst_i;
-    output  reg     signal_o;
-    output  reg     done_o;
-
-//================================================================================
-//
-//  STATE MACHINE STATES
-//
-//================================================================================
-
-    localparam  [1:0]   SM_RST_S    = 2'b00;
-    localparam  [1:0]   SM_DELAY_S  = 2'b01;
-    localparam  [1:0]   SM_SIGNAL_S = 2'b10;
-    localparam  [1:0]   SM_DONE_S   = 2'b11;
-
-//================================================================================
-//
-//  REG/WIRE
-//
-//================================================================================
-
-    reg     [1:0]               curr_state;
-    reg     [1:0]               next_state;
-
-    reg     [DELAY_CNT_W-1:0]   delay_cnt;
-    reg     [DELAY_CNT_W-1:0]   delay_cnt_next;
-    reg                         signal_next;
-    reg                         done_next;
-
-//================================================================================
-//
-//  CODING
-//
-//================================================================================
-
-always @(posedge clk_i or posedge rst_i) begin
-    if (rst_i) begin
-        curr_state  <= SM_RST_S;
-        delay_cnt   <= {DELAY_CNT_W{1'b0}};
-        signal_o    <= 1'b0;
-        done_o      <= 1'b0;
-    end else begin
-        curr_state  <= next_state;
-        delay_cnt   <= delay_cnt_next;
-        signal_o    <= signal_next;
-        done_o      <= done_next;
-    end
-end
-
-always @(*) begin
-    next_state      = SM_RST_S;
-    delay_cnt_next  = {DELAY_CNT_W{1'b0}};
-    signal_next     = 1'b0;
-    done_next       = 1'b0;
-    case(curr_state)
-        SM_RST_S    : begin
-            next_state  = SM_DELAY_S;
-        end
-
-        SM_DELAY_S  : begin
-            if (delay_cnt == DELAY_VALUE[DELAY_CNT_W-1:0]) begin
-                next_state      = SM_SIGNAL_S;
-                delay_cnt_next  = {DELAY_CNT_W{1'b0}};
-            end else begin
-                next_state      = SM_DELAY_S;
-                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
-            end
-        end
-
-        SM_SIGNAL_S : begin
-            signal_next = 1'b1;
-            if (delay_cnt == LENGTH_WIDTH[DELAY_CNT_W-1:0]) begin
-                next_state      = SM_DONE_S;
-            end else begin
-                next_state      = SM_SIGNAL_S;
-                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
-            end
-        end
-
-        SM_DONE_S   : begin
-            done_next   = 1'b1;
-            next_state  = SM_DONE_S;
-        end
-    endcase
-end
-
-endmodule

AdcInit/PeriphSpiInit.v

@@ -1,217 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////////
-// Company                  :   NPK TAIR
-// Engineer                 :   Yuri Donskoy
-// 
-// Create Date (dd/mm/yyyy) :   16.05.2019
-// Design Name              :
-// Module Name              :
-// Project Name             :
-// Target Devices           :
-// Tool versions            :
-// Description              :
-//
-// Dependencies             : 
-// 
-// Revision                 :   0.01 - File Created
-// Additional Comments      :
-//        
-//////////////////////////////////////////////////////////////////////////////////
-
-module PeriphSpiInit (
-    clk_i,
-    rst_i,
-
-    enable_i,
-
-    mosi_o,
-    sck_o,
-    ss_o,
-
-    done_o
-);
-
-//================================================================================
-//
-//  FUNCTIONS
-//
-//================================================================================
-
-    function integer bit_num;
-        input integer value;
-        begin
-            bit_num = 0;
-            while (value > 0) begin
-                value   = value >> 1;
-                bit_num = bit_num + 1;
-            end
-        end
-    endfunction
-
-//================================================================================
-//
-//  PARAMETER/LOCALPARAM
-//
-//================================================================================
-
-    parameter   DATA_WIDTH              = 24;
-    parameter   DATA_NUM                = 26; 
-    parameter   ROM_INIT_FILE           = "./initFiles/AdcInitData.txt";
-    parameter   FILE_DATA_BASE          = "HEX";
-    parameter   SPI_CLK_DIVISOR_POWER   = 4;
-    parameter   SPI_CPOL                = 0;
-    parameter   SPI_CPHA                = 0;
-    parameter   SPI_DATA_DIRECTION      = "MSB";   //  MSB or LSB
-    parameter   SPI_EN_START_DELAY      = "NO";     //  YES or NO
-
-    localparam  ROM_ADDR_WIDTH          = bit_num(DATA_NUM);
-
-//================================================================================
-//
-//  STATE MACHINE STATES
-//
-//================================================================================
-
-    localparam  [7:0]   SM_RST_S        = 8'd0;
-    localparam  [7:0]   SM_SEND_DATA_S  = 8'd2;
-    localparam  [7:0]   SM_READ_DATA_S  = 8'd3;
-    localparam  [7:0]   SM_WAIT_SPI_S   = 8'd4;
-    localparam  [7:0]   SM_DONE_S       = 8'd5;
-
-//================================================================================
-//
-//  PORTS
-//
-//================================================================================
-
-    input       clk_i;
-    input       rst_i;
-    input       enable_i;
-    output      mosi_o;
-    output      sck_o;
-    output      ss_o;
-    output      done_o;
-
-//================================================================================
-//
-//  REG/WIRE
-//
-//================================================================================
-
-    reg     [ROM_ADDR_WIDTH-1:0]    rom_addr;
-    reg                             rom_valid;
-    wire    [DATA_WIDTH-1:0]        rom_data;
-    reg     [ROM_ADDR_WIDTH-1:0]    rom_addr_next;
-    wire                            spi_ready;
-    reg     [7:0]                   sm_curr_state;
-    reg     [7:0]                   sm_next_state;
-    wire                            data_end_flag;
-
-//================================================================================
-//
-//  INTEGER/GENVAR
-//
-//================================================================================
-
-
-
-//================================================================================
-//
-//  ASSIGN
-//
-//================================================================================
-
-    assign  data_end_flag   = (rom_addr == DATA_NUM);
-    assign  done_o          = sm_curr_state == SM_DONE_S;
-
-//================================================================================
-//
-//  CODING
-//
-//================================================================================
-
-SpiMaster #(
-    .CLK_DIVISOR_POWER  (SPI_CLK_DIVISOR_POWER),
-    .DATA_WIDTH         (DATA_WIDTH),
-    .CPOL               (SPI_CPOL),
-    .CPHA               (SPI_CPHA),
-    .DATA_DIRECTION     (SPI_DATA_DIRECTION),
-    .EN_START_DELAY     (SPI_EN_START_DELAY)
-) SpiMaster (
-    .clk_i      (clk_i),
-    .rst_i      (rst_i),
-
-    .data_i     (rom_data),
-    .valid_i    (rom_valid),
-    .ready_o    (spi_ready),
-    .mosi_o     (mosi_o),
-    .sck_o      (sck_o),
-    .ss_o       (ss_o)
-);
-
-SinglePortRom #(
-    .DATA_WIDTH     (DATA_WIDTH), 
-    .ADDR_WIDTH     (ROM_ADDR_WIDTH),
-    .INIT_FILE_NAME (ROM_INIT_FILE),
-    .DATA_BASE      (FILE_DATA_BASE)
-) Rom (
-    .clk_i  (clk_i),
-    .addr_i (rom_addr),
-    .q_o    (rom_data)
-    );
-
-always @(posedge clk_i or posedge rst_i) begin
-    if (rst_i) begin
-        sm_curr_state   <= 0;
-        rom_addr        <= SM_RST_S;
-    end else begin
-        sm_curr_state   <= sm_next_state;
-        rom_addr        <= rom_addr_next;
-    end
-end
-
-always @(*) begin
-    sm_next_state   = 0;
-    rom_addr_next   = rom_addr;
-    rom_valid       = 1'b0;
-    case(sm_curr_state)
-        SM_RST_S        :   begin
-            if (enable_i) begin
-                sm_next_state   = SM_SEND_DATA_S;
-            end else begin
-                sm_next_state   = SM_RST_S;
-            end
-        end
-
-        SM_SEND_DATA_S  :   begin
-            rom_valid       = 1'b1;
-            sm_next_state   = SM_SEND_DATA_S;
-            if (spi_ready) begin
-                rom_addr_next   = rom_addr + {{(ROM_ADDR_WIDTH-1){1'b0}}, 1'b1};
-                sm_next_state   = SM_READ_DATA_S;
-            end
-        end
-
-        SM_READ_DATA_S  :   begin
-            if (data_end_flag) begin
-                sm_next_state   = SM_WAIT_SPI_S;
-            end else begin
-                sm_next_state   = SM_SEND_DATA_S;
-            end
-        end
-
-        SM_WAIT_SPI_S   : begin
-            if (spi_ready) begin
-                sm_next_state   = SM_DONE_S;
-            end else begin
-                sm_next_state   = SM_WAIT_SPI_S;
-            end
-        end
-
-        SM_DONE_S       :   begin
-            sm_next_state   = SM_DONE_S;
-        end
-
-    endcase
-end
-
-endmodule

AdcInit/Power2ClkDivider.v

@@ -1,90 +0,0 @@
-`timescale 1ns / 1ps
-module Power2ClkDivider (
-    clk_i,
-    rst_i,
-    valid_i,
-    signal_o,
-    rising_edge_o,
-    falling_edge_o
-);
-
-//================================================================================
-//
-//  PARAMETER/LOCALPARAM
-//
-//================================================================================
-
-    parameter   DIVISOR_POWER   = 2;
-
-//================================================================================
-//
-//  PORTS
-//
-//================================================================================
-
-    input           clk_i;
-    input           rst_i;
-    input           valid_i;
-    output  reg     signal_o;
-    output  reg     rising_edge_o;
-    output  reg     falling_edge_o;
-
-//================================================================================
-//
-//  REG/WIRE
-//
-//================================================================================
-
-    wire    clk_div_flag;
-
-//================================================================================
-//
-//  CODING
-//
-//================================================================================
-
-//initial begin
-//    if (DIVISOR_POWER < 1) begin
-//        $error("parameter DIVISOR_POWER of module power2_clk_divider must be greater then 0");
-//        $stop;
-//    end
-//end
-
-generate
-    if (DIVISOR_POWER < 2) begin
-        assign  clk_div_flag    = 1'b1;
-    end else begin
-        reg     [DIVISOR_POWER-2:0] clk_div_cnt;
-        always @(posedge clk_i or posedge rst_i) begin
-            if (rst_i) begin
-                clk_div_cnt <= {DIVISOR_POWER{1'b1}};
-            end else if (valid_i) begin
-                clk_div_cnt <= clk_div_cnt + 1;
-            end else begin
-                clk_div_cnt <= {DIVISOR_POWER{1'b1}};
-            end
-        end
-
-        assign  clk_div_flag    = &clk_div_cnt;
-    end
-endgenerate
-
-always @(posedge clk_i or posedge rst_i) begin
-    if (rst_i) begin
-        signal_o        <= 1'b0;
-        rising_edge_o   <= 1'b0;
-        falling_edge_o  <= 1'b0;
-    end else if (valid_i) begin
-        if (clk_div_flag) begin
-            signal_o    <= ~signal_o;
-        end
-        rising_edge_o   <= ~signal_o & clk_div_flag;
-        falling_edge_o  <= signal_o & clk_div_flag;
-    end else begin
-        signal_o        <= 1'b0;
-        rising_edge_o   <= 1'b0;
-        falling_edge_o  <= 1'b0;
-    end
-end
-
-endmodule

AdcInit/ResetFilter.v

@@ -1,60 +0,0 @@
-module ResetFilter (
-    clk_i,
-    rst_i,
-    perm_i,
-    filtered_rst_o
-);
-
-    parameter   STAGE_NUM   = 1;
-    parameter   RESET_FRONT = "RISING"; //  FALLING
-
-    input   clk_i;
-    input   rst_i;
-    input   perm_i;
-    output  filtered_rst_o;
-
-    reg [STAGE_NUM-1:0] rst_filter;
-
-    assign  filtered_rst_o  = rst_filter[STAGE_NUM-1];
-
-generate
-    if (RESET_FRONT == "RISING") begin
-        if (STAGE_NUM < 2) begin
-            always @(posedge clk_i or posedge rst_i) begin
-                if (rst_i) begin
-                    rst_filter  <= 1'b1;
-                end else begin
-                    rst_filter  <= perm_i;
-                end
-            end
-        end else begin
-            always @(posedge clk_i or posedge rst_i) begin
-                if (rst_i) begin
-                    rst_filter  <= {STAGE_NUM{1'b1}};
-                end else begin
-                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
-                end
-            end        
-        end
-    end else begin
-        if (STAGE_NUM < 2) begin
-            always @(posedge clk_i or negedge rst_i) begin
-                if (!rst_i) begin
-                    rst_filter  <= 1'b1;
-                end else begin
-                    rst_filter  <= perm_i;
-                end
-            end
-        end else begin
-            always @(posedge clk_i or negedge rst_i) begin
-                if (!rst_i) begin
-                    rst_filter  <= {STAGE_NUM{1'b1}};
-                end else begin
-                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
-                end
-            end        
-        end    
-    end
-endgenerate
-
-endmodule

AdcInit/SinglePortRom.v

@@ -1,30 +0,0 @@
-module SinglePortRom (
-    clk_i, 
-    addr_i,
-    q_o
-);
-
-    parameter   DATA_WIDTH      = 16; 
-    parameter   ADDR_WIDTH      = 5;
-    parameter   INIT_FILE_NAME  = "./initFiles/AdcInitData.txt";
-    parameter   DATA_BASE       = "HEX";    //  HEX or BIN
-
-    input                                   clk_i;
-    input           [(ADDR_WIDTH-1):0]      addr_i;
-    output  reg     [(DATA_WIDTH-1):0]      q_o;
-
-    reg     [DATA_WIDTH-1:0]    rom[2**ADDR_WIDTH-1:0];
-
-initial begin
-    if (DATA_BASE == "HEX") begin
-        $readmemh(INIT_FILE_NAME, rom);
-    end else begin
-        $readmemb(INIT_FILE_NAME, rom);
-    end
-end
-
-always @ (posedge clk_i) begin
-    q_o <=  rom[addr_i];
-end
-
-endmodule

AdcInit/SpiMaster.v

@@ -1,273 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////////
-// Company                  :   NPK TAIR
-// Engineer                 :   Yuri Donskoy
-// 
-// Create Date (dd/mm/yyyy) :
-// Design Name              :
-// Module Name              :
-// Project Name             :
-// Target Devices           :
-// Tool versions            :
-// Description              :
-//
-// Dependencies             : 
-// 
-// Revision                 :   1.0 - It only send data (no miso port)
-// Additional Comments      :   MISO port need to be add. What about multiple slave select?
-//        
-//////////////////////////////////////////////////////////////////////////////////
-
-module SpiMaster (
-    clk_i,
-    rst_i,
-
-    data_i,
-    valid_i,
-    ready_o,
-
-    mosi_o,
-    sck_o,
-    ss_o
-);
-
-//================================================================================
-//
-//  FUNCTIONS
-//
-//================================================================================
-
-    function integer bit_num;
-        input integer value;
-        begin
-            bit_num = 0;
-            while (value > 0) begin
-                value   = value >> 1;
-                bit_num = bit_num + 1;
-            end
-        end
-    endfunction
-
-//================================================================================
-//
-//  PARAMETER/LOCALPARAM
-//
-//================================================================================
-
-    parameter   CLK_DIVISOR_POWER   = 4; //WAS 2 !! DONT FORGET TO CHANGE!
-    parameter   DATA_WIDTH          = 24;
-    parameter   CPOL                = 0;
-    parameter   CPHA                = 0;
-    parameter   DATA_DIRECTION      = "MSBT";   //  MSB or LSB
-    parameter   EN_START_DELAY      = "NO";     //  YES or NO
-
-    localparam  BIT_CNT_W           = bit_num(DATA_WIDTH);
-
-//================================================================================
-//
-//  STATE MACHINE STATES
-//
-//================================================================================
-
-    localparam  SM_IDLE_S   = 2'b00;
-    localparam  SM_START_S  = 2'b01;
-    localparam  SM_DATA_S   = 2'b10;
-    localparam  SM_STOP_S   = 2'b11;
-
-//================================================================================
-//
-//  PORTS
-//
-//================================================================================
-
-    input                               clk_i;
-    input                               rst_i;
-
-    input           [DATA_WIDTH-1:0]    data_i;
-    input                               valid_i;
-    output                              ready_o;
-
-    output  reg                         mosi_o;
-    output  reg                         sck_o;
-    output  reg                         ss_o;
-
-//================================================================================
-//
-//  REG/WIRE
-//
-//================================================================================
-
-    reg     [1:0]               sm_curr_state;
-    reg     [1:0]               sm_next_state;
-
-    reg                         sm_clk_div_en;
-
-    //  Clock divider outputs
-
-    wire                        clk_divider_redge;
-    wire                        clk_divider_fedge;
-
-    //  Bits counter
-
-    reg     [BIT_CNT_W-1:0]     bit_cnt_r;
-    reg     [BIT_CNT_W-1:0]     bit_cnt_next;
-
-    //  Data buffers
-
-    reg     [DATA_WIDTH-1:0]    tx_buffer_r;
-    reg     [DATA_WIDTH-1:0]    tx_buffer_next;
-    wire    [DATA_WIDTH-1:0]    tx_buffer_shifted;
-    wire                        tx_curr_bit;
-
-    //  Output data next
-    reg                         mosi_next;
-    reg                         sck_next;
-    reg                         ss_next;
-
-    //  Edges
-
-    wire                        mosi_shift_edge;
-
-    wire                        ss_start_edge;
-    wire                        ss_stop_edge;
-
-    wire                        sck_leading_edge;
-    wire                        sck_trailing_edge;
-
-//================================================================================
-//
-//  INTEGER/GENVAR
-//
-//================================================================================
-
-
-
-//================================================================================
-//
-//  ASSIGN
-//
-//================================================================================
-
-    assign  mosi_shift_edge     = (CPHA[0] == 1'b1) && (EN_START_DELAY != "YES") || (CPHA[0] == 1'b0) && (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
-    assign  ss_start_edge       = (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
-    assign  ss_stop_edge        = (EN_START_DELAY == "YES") ? clk_divider_redge : clk_divider_fedge;
-    assign  sck_leading_edge    = (EN_START_DELAY == "YES") ? clk_divider_redge : clk_divider_fedge;
-    assign  sck_trailing_edge   = (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
-    assign  tx_buffer_shifted   = (DATA_DIRECTION == "MSB") ? tx_buffer_r << 1 : tx_buffer_r >> 1;
-    assign  tx_curr_bit         = (DATA_DIRECTION == "MSB") ? tx_buffer_r[DATA_WIDTH-1] : tx_buffer_r[0];
-
-    assign  ready_o             = sm_curr_state == SM_IDLE_S;
-
-//================================================================================
-//
-//  CODING
-//
-//================================================================================
-
-//  Sequential logic
-
-always @(posedge clk_i or posedge rst_i) begin
-    if (rst_i) begin
-        sm_curr_state   <= 0;
-        tx_buffer_r     <= {DATA_WIDTH{1'b0}};
-        bit_cnt_r       <= {BIT_CNT_W{1'b0}};
-        mosi_o          <= 1'b0;
-        sck_o           <= CPOL[0];
-        ss_o            <= 1'b1;
-    end else begin
-        sm_curr_state   <= sm_next_state;
-        tx_buffer_r     <= tx_buffer_next;
-        bit_cnt_r       <= bit_cnt_next;
-        mosi_o          <= mosi_next;
-        sck_o           <= sck_next;
-        ss_o            <= ss_next;
-    end
-end
-
-//  Combinational logic
-
-always @(*) begin
-    sm_next_state   = SM_IDLE_S;
-    tx_buffer_next  = tx_buffer_r;
-    mosi_next       = mosi_o;
-    sck_next        = sck_o;
-    ss_next         = ss_o;
-    sm_clk_div_en   = 1'b1;
-    bit_cnt_next    = bit_cnt_r;
-
-    case(sm_curr_state)
-
-        SM_IDLE_S   : begin
-            if (valid_i) begin
-                sm_next_state   = SM_START_S;
-            end else begin
-                sm_next_state   = SM_IDLE_S;
-            end
-            tx_buffer_next  = data_i;
-            sm_clk_div_en   = 1'b0;
-            bit_cnt_next    = {BIT_CNT_W{1'b0}};
-        end
-
-        SM_START_S  : begin
-            if (ss_start_edge) begin
-                sm_next_state   = SM_DATA_S;
-                ss_next         = 1'b0;
-                if (!CPHA[0]) begin
-                    mosi_next       = tx_curr_bit;
-                    tx_buffer_next  = tx_buffer_shifted;
-                    bit_cnt_next    = bit_cnt_r + {{(BIT_CNT_W-1){1'b0}}, 1'b1};
-                end
-            end else begin
-                sm_next_state   = SM_START_S;
-            end
-        end
-
-        SM_DATA_S   : begin
-            sm_next_state   = SM_DATA_S;
-            if (sck_leading_edge) begin
-                sck_next    = ~CPOL[0];
-            end
-
-            if  (sck_trailing_edge) begin
-                sck_next    = CPOL[0];
-                if (bit_cnt_r == DATA_WIDTH[BIT_CNT_W-1:0]) begin
-                    sm_next_state   = SM_STOP_S;
-                end
-            end
-
-            if (mosi_shift_edge) begin
-                mosi_next       = tx_curr_bit;
-                tx_buffer_next  = tx_buffer_shifted;
-                bit_cnt_next    = bit_cnt_r + {{(BIT_CNT_W-1){1'b0}}, 1'b1};
-            end
-
-        end
-
-        SM_STOP_S   : begin
-            if (ss_stop_edge) begin
-                if (CPHA[0]) begin
-                    mosi_next   = tx_curr_bit;
-                end
-                sm_next_state   = SM_IDLE_S;
-                ss_next         = 1'b1;
-            end else begin
-                sm_next_state   = SM_STOP_S;
-            end
-        end
-
-    endcase
-end
-
-//  Clock divider
-
-Power2ClkDivider #(
-    .DIVISOR_POWER      (CLK_DIVISOR_POWER)
-) ClkDividerInst (
-    .clk_i              (clk_i),
-    .rst_i              (rst_i),
-    .valid_i            (sm_clk_div_en),
-    .signal_o           (),
-    .rising_edge_o      (clk_divider_redge),
-    .falling_edge_o     (clk_divider_fedge)
-);
-
-endmodule

AdcInit/initFiles/AdcInitData.txt

@@ -1,26 +0,0 @@
-400601
-40013C
-400300
-400400
-400533
-400602 
-400700
-400900
-400A02
-400B20
-400ED1
-400FD4
-401300
-401500
-402500
-402700
-441D00
-442202
-443428
-443908
-451D00
-452202
-453428
-453908
-460800
-470A00

QuadSPI/InitRst.v

@@ -1,104 +0,0 @@
-module InitRst (
-    clk_i,
-    signal_o
-);
-
-//================================================================================
-//
-//  FUNCTIONS
-//
-//================================================================================
-
-    function integer bit_num;
-        input integer value;
-        begin
-            bit_num = 0;
-            while (value > 0) begin
-                value   = value >> 1;
-                bit_num = bit_num + 1;
-            end
-        end
-    endfunction
-
-//================================================================================
-//
-//  PARAMETER/LOCALPARAM
-//
-//================================================================================
-
-    parameter   DELAY_VALUE     = 20;
-    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
-
-//================================================================================
-//
-//  PORTS
-//
-//================================================================================
-
-    input           clk_i;
-    output  reg     signal_o;
-
-//================================================================================
-//
-//  STATE MACHINE STATES
-//
-//================================================================================
-
-    localparam      SM_RST_S    = 1'b0;
-    localparam      SM_DONE_S   = 1'b1;
-
-//================================================================================
-//
-//  REG/WIRE
-//
-//================================================================================
-
-    reg                         curr_state  = SM_RST_S;
-    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
-    reg                         delay_flag  = 1'b0;
-
-    reg                         next_state;
-    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
-    reg                         signal_next;
-
-//================================================================================
-//
-//  CODING
-//
-//================================================================================
-
-initial begin
-    curr_state  = SM_RST_S;
-    delay_cnt   = {DELAY_CNT_W{1'b0}};
-    signal_o    = 1'b1;
-    delay_flag  = 1'b0;
-end
-
-always @(posedge clk_i) begin
-    curr_state  <= next_state;
-    delay_cnt   <= delay_cnt_next;
-    signal_o    <= signal_next;
-    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
-end
-
-always @(*) begin
-    next_state      = SM_RST_S;
-    delay_cnt_next  = delay_cnt;
-    signal_next     = 1'b1;
-    case(curr_state)
-        SM_RST_S    : begin
-            if (delay_flag) begin
-                next_state      = SM_DONE_S;
-            end else begin
-                next_state      = SM_RST_S;
-                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
-            end
-        end
-        SM_DONE_S   : begin
-            signal_next = 1'b0;
-            next_state  = SM_DONE_S;
-        end
-    endcase
-end
-
-endmodule

QuadSPI/QuadSPIs.v

@@ -1,221 +0,0 @@
-module QuadSPIs (
-    input Clk_i,
-    input Rst_i,
-
-    input Sck_i,
-    input Ss_i,
-    input Mosi0_i,
-    input Mosi1_i,
-    input Mosi2_i,
-    input Mosi3_i,
-
-    input [1:0] WidthSel_i,
-    input EnEdge_i,
-    input PulsePol_i,
-
-    output reg [23:0] Data_o,
-    output reg [7:0] Addr_o,
-    output reg Val_o
-);
-
-//================================================================================
-//	REG/WIRE
-//================================================================================
-
-reg ssReg;
-reg ssRegR; 
-reg SckReg; 
-reg [7:0] addrReg;
-reg [7:0] shiftReg0;
-reg [7:0] shiftReg1;
-reg [7:0] shiftReg2;
-
-reg [7:0] shiftReg0M;
-reg [7:0] shiftReg1M;
-reg [7:0] shiftReg2M;
-reg [7:0] addrRegM;
-
-reg Sck;
-
-//===============================================================================
-//  ASSIGNMENTS
-
-
-
-
-//================================================================================
-//	CODING
-//================================================================================
-always @(*) begin 
-    if (PulsePol_i) begin 
-        if (EnEdge_i) begin 
-            assign Sck = ~Sck_i;
-        end
-        else begin 
-            assign Sck = Sck_i;
-        end
-    end
-    else begin 
-        if (EnEdge_i) begin 
-            assign Sck = Sck_i;
-        end
-        else begin 
-            assign Sck = ~Sck_i;
-        end
-    end
-end
-always @(posedge Sck) begin 
-    if (Rst_i) begin 
-        SckReg <= 1'b0;
-    end
-    else begin 
-        SckReg <= Sck;
-    end
-end
-
-
-always	@(posedge	Clk_i)	begin
-	ssReg	<=	Ss_i;
-	ssRegR	<=	ssReg;
-end
-
-
-always @(*) begin 
-    if (Rst_i) begin
-        addrRegM = 8'h0; 
-        shiftReg0M = 8'h0;
-        shiftReg1M = 8'h0;
-        shiftReg2M = 8'h0;
-    end
-    else begin 
-        case(WidthSel_i)  
-             0: begin 
-                addrRegM   = addrReg  [1:0];
-                shiftReg0M = shiftReg0[1:0];
-                shiftReg1M = shiftReg1[1:0];
-                shiftReg2M = shiftReg2[1:0];
-            end
-            1: begin 
-                addrRegM   = addrReg  [3:0];
-                shiftReg0M = shiftReg0[3:0];
-                shiftReg1M = shiftReg1[3:0];
-                shiftReg2M = shiftReg2[3:0];
-            end
-            2: begin 
-                addrRegM   = addrReg  [5:0];
-                shiftReg0M = shiftReg0[5:0];
-                shiftReg1M = shiftReg1[5:0];
-                shiftReg2M = shiftReg2[5:0];
-            end
-            3: begin 
-                addrRegM   = addrReg  [7:0];
-                shiftReg0M = shiftReg0[7:0];
-                shiftReg1M = shiftReg1[7:0];
-                shiftReg2M = shiftReg2[7:0];
-            end
-        endcase
-    end
-end
-
-
-
-always @(posedge Clk_i) begin 
-    if (Rst_i) begin 
-        Data_o <= 24'h0;
-    end
-    else begin 
-        if (ssReg && !ssRegR) begin 
-            Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
-        end
-        else begin 
-            Data_o <= 24'h0;
-        end
-    end
-end
-
-always @(posedge Clk_i) begin 
-    if (Rst_i) begin 
-        Addr_o <= 8'h0;
-    end
-    else begin 
-        if (ssReg && !ssRegR) begin 
-            Addr_o <= addrRegM;
-        end
-    end
-end
-
-
-always @(posedge Sck) begin 
-    if (Rst_i) begin 
-        shiftReg0 <= 8'h0;
-    end
-    else begin 
-        if (!Ss_i) begin 
-            shiftReg0 <= {shiftReg0[6:0], Mosi0_i};
-        end
-        else begin 
-            shiftReg0 <= 8'h0;
-        end
-    end
-end
-
-
-always @(posedge Sck ) begin 
-    if (Rst_i) begin 
-        shiftReg1 <= 8'h0;
-    end
-    else begin 
-        if (!Ss_i) begin 
-            shiftReg1 <= {shiftReg1[6:0], Mosi1_i};
-        end
-        else begin 
-            shiftReg1 <= 8'h0;
-        end
-    end
-end
-
-
-always @(posedge Sck ) begin 
-    if (Rst_i) begin 
-        shiftReg2 <= 8'h0;
-    end
-    else begin 
-        if (!Ss_i) begin 
-            shiftReg2 <= {shiftReg2[6:0], Mosi2_i};
-        end
-        else begin 
-            shiftReg2 <= 8'h0;
-        end
-    end
-end
-
-
-always @(posedge Sck ) begin 
-    if (Rst_i) begin 
-        addrReg <= 8'h0;
-    end
-    else begin 
-        if (!Ss_i) begin 
-            addrReg <= {addrReg[6:0], Mosi3_i};
-        end
-        else begin 
-            addrReg <= 8'h0;
-        end
-    end
-end
-
-
-
-always @(posedge Clk_i) begin 
-    if (ssReg && !ssRegR) begin 
-        Val_o <= 1'b1;
-    end
-    else begin 
-        Val_o <= 1'b0;
-    end
-end
-
-
-
-
-endmodule

QuadSPI/QuadSPIs_tb.v

@@ -1,275 +0,0 @@
-`timescale 1ns / 1ps
-module QuadSPIs_tb ();
-
-reg Clk70_i;
-reg Clk50_i;
-wire Sck_i;
-wire Rst_i;
-
-reg[7:0] mosiReg0_tb;
-reg[7:0] mosiReg1_tb;
-reg[7:0] mosiReg2_tb;
-reg[7:0] mosiReg3_tb;
-
-
-reg [7:0] Mosi0_i;
-reg [7:0] Mosi1_i;
-reg [7:0] Mosi2_i;
-reg [7:0] Mosi3_i;
-reg EnEdge_i;
-reg Ss;
-reg SSr;
-reg SSm;
-reg Start_i;
-reg startFlag;
-reg [5:0] ssCnt; 
-reg [3:0] ssNum;
-reg [1:0] WidthSel_i;
-
-reg [31:0] SPIdata;
-
-
-// assign Mosi0_i = (!Ss) ? (mosiReg3_tb[7]):1'b0;
-// assign Mosi1_i = (!Ss) ? (mosiReg2_tb[7]):1'b0;
-// assign Mosi2_i = (!Ss) ? (mosiReg1_tb[7]):1'b0;
-// assign Mosi3_i = (!Ss) ? (mosiReg0_tb[7]):1'b0;
-assign Sck_i = (!Ss) ? (Clk70_i) : 1'b0;
-
-
-
-
-// always #(24.390243902439/2) Clk70_i = ~Clk70_i;// 41Mhz
-always #(14.285714285714/2) Clk70_i = ~Clk70_i;// 70Mhz
-// always #10 Clk70_i = ~Clk70_i;// 50 Mhz
-
-always #10 Clk50_i = ~Clk50_i;
-
-
-
-
-always @(*) begin 
-    case (WidthSel_i) 
-        0 : begin 
-            Mosi0_i = (!Ss) ? (mosiReg3_tb[1]):1'b0;
-            Mosi1_i = (!Ss) ? (mosiReg2_tb[1]):1'b0;
-            Mosi2_i = (!Ss) ? (mosiReg1_tb[1]):1'b0;
-            Mosi3_i = (!Ss) ? (mosiReg0_tb[1]):1'b0;
-        end
-        1 : begin 
-            Mosi0_i = (!Ss) ? (mosiReg3_tb[3]):1'b0;
-            Mosi1_i = (!Ss) ? (mosiReg2_tb[3]):1'b0;
-            Mosi2_i = (!Ss) ? (mosiReg1_tb[3]):1'b0;
-            Mosi3_i = (!Ss) ? (mosiReg0_tb[3]):1'b0;
-        end
-        2 : begin 
-            Mosi0_i = (!Ss) ? (mosiReg3_tb[5]):1'b0;
-            Mosi1_i = (!Ss) ? (mosiReg2_tb[5]):1'b0;
-            Mosi2_i = (!Ss) ? (mosiReg1_tb[5]):1'b0;
-            Mosi3_i = (!Ss) ? (mosiReg0_tb[5]):1'b0;
-        end
-        3 : begin 
-            Mosi0_i = (!Ss) ? (mosiReg3_tb[7]):1'b0;
-            Mosi1_i = (!Ss) ? (mosiReg2_tb[7]):1'b0;
-            Mosi2_i = (!Ss) ? (mosiReg1_tb[7]):1'b0;
-            Mosi3_i = (!Ss) ? (mosiReg0_tb[7]):1'b0;
-        end
-    endcase
-end
-
-
-
-
-
-
-
-initial begin 
-    Clk70_i = 1'b1;
-    // Clk70_i = 1'b0;//50 Mhz out of phase with src clk
-    Clk50_i = 1'b1;
-    Start_i = 1'b0;
-    EnEdge_i = 1'b1;
-    SPIdata = {1'h0, 7'h2a, 8'haa,8'h00,8'haa};
-    WidthSel_i = 2'b11;
-    #100Start_i = 1'b1;
-    #500 Start_i = 1'b0;
-    #600 Start_i = 1'b1;
-     SPIdata = {1'h1, 7'h29, 24'd520050};
-    #100 Start_i = 1'b0;
-    #1500 Start_i = 1'b1;
-     SPIdata = {1'h0, 7'h2a, 24'd10};
-    #100 Start_i = 1'b0;
-
-end
-
-
-always @(posedge Clk70_i) begin
-    if (Rst_i) begin
-        SSr <=1'b0;
-    end
-    else begin 
-        SSr <= Ss;
-    end
-end
-
-
-always @(posedge Clk70_i) begin 
-    if (Rst_i) begin 
-        startFlag <= 1'b0;
-    end
-    else begin 
-        if (!Start_i) begin 
-            startFlag <= 1'b1;
-        end
-        else begin 
-            startFlag <= 1'b0;
-        end
-    end
-end
-
-
-always @(*) begin 
-    if (Rst_i) begin 
-        ssNum = 1'b0;
-    end
-    else begin 
-        case (WidthSel_i) 
-            0 : begin 
-                ssNum = 2;
-            end
-            1 : begin 
-                ssNum = 4;
-            end
-            2 : begin 
-                ssNum = 6;
-            end
-            3 : begin 
-                ssNum = 8;
-            end
-        endcase
-    end
-end
-
-
-always @(posedge Clk70_i) begin 
-    if (Rst_i) begin 
-        ssCnt <= 1'b0;
-    end
-    else if (ssCnt < ssNum && startFlag  ) begin 
-        ssCnt <= ssCnt + 1'b1;
-    end
-    else begin
-        if (ssCnt == ssNum-1 || !startFlag) begin 
-            ssCnt <= 1'b0;
-        end
-    end
-end
-
-always @(negedge Clk70_i) begin 
-    if (Rst_i) begin 
-        Ss <= 1'b1;
-    end
-    else begin 
-        if (ssCnt < ssNum && startFlag ) begin 
-            Ss <= 1'b0;
-        end
-        else begin 
-            Ss <= 1'b1;
-        end
-    end
-end
-
-
-always @(negedge Clk70_i) begin 
-    if (Rst_i) begin 
-        mosiReg0_tb <= SPIdata[31:24];
-    end
-    else begin 
-        if (!SSr) begin
-            mosiReg0_tb <= { mosiReg0_tb[6:0],1'b0 };
-        end
-        else begin 
-            mosiReg0_tb <= SPIdata[31:24];
-        end
-    end
-end
-
-always @(negedge Clk70_i) begin 
-    if (Rst_i) begin 
-        mosiReg1_tb <= SPIdata[23:16];
-    end
-    else begin 
-        if (!SSr) begin
-            mosiReg1_tb <= { mosiReg1_tb[6:0],1'b0 };
-        end
-        else begin 
-            mosiReg1_tb <= SPIdata[23:16];
-        end
-    end
-end
-
-always @(negedge Clk70_i) begin 
-    if (Rst_i) begin 
-        mosiReg2_tb <= SPIdata[15:8];
-    end
-    else begin 
-        if (!SSr) begin
-            mosiReg2_tb <= { mosiReg2_tb[6:0],1'b0 };
-        end
-        else begin 
-            mosiReg2_tb <= SPIdata[15:8];
-        end
-    end
-end
-
-always @(negedge Clk70_i) begin 
-    if (Rst_i) begin 
-        mosiReg3_tb <= SPIdata[7:0];
-    end
-    else begin 
-        if (!SSr) begin
-            mosiReg3_tb <= { mosiReg3_tb[6:0],1'b0 };
-        end
-        else begin 
-            mosiReg3_tb <= SPIdata[7:0];
-        end
-    end
-end
-
-
-
-
-
-
-QuadSPIs QuadSPI_inst (
-    .Sck_i(Sck_i),
-    .Clk_i(Clk50_i),
-    .Rst_i(Rst_i),
-    .Ss_i(Ss),
-    .WidthSel_i(WidthSel_i),
-    .Mosi0_i(Mosi0_i),
-    .Mosi1_i(Mosi1_i),
-    .Mosi2_i(Mosi2_i),
-    .Mosi3_i(Mosi3_i),
-    .EnEdge_i(EnEdge_i),
-    .PulsePol_i(1'b0)
-
-);
-
-
-
-InitRst InitRst_inst (
-    .clk_i(Clk50_i),
-    .signal_o(Rst_i)
-
-);
-
-
-
-
-
-
-
-
-
-
-endmodule

SRAM/QuadSPIm.v

@@ -31,10 +31,10 @@ reg startFlag;
 reg [2:0] ssCnt;
 reg Ss;
 reg SSr;
-reg [6:0] mosiReg0;
-reg [6:0] mosiReg1;
-reg [6:0] mosiReg2;
-reg [6:0] mosiReg3;
+reg [7:0] mosiReg0;
+reg [7:0] mosiReg1;
+reg [7:0] mosiReg2;
+reg [7:0] mosiReg3;
 reg [3:0] ssNum;
 reg [2:0] delayCnt;
 reg stopFlag;

SRAM/RegMap.v

@@ -158,6 +158,7 @@ reg [CmdRegWidth/2-1:0] GPIOAReg;
 
 
 reg [CmdRegWidth/2-1:0] ansReg;
+reg [CmdRegWidth/2-1:0] LedReg;
 
 //================================================================================
 //	ASSIGNMENTS
@@ -233,6 +234,7 @@ assign GPIOAReg_o = GPIOAReg;
 
 
 assign AnsDataReg_o = ansReg;
+assign Led_o = LedReg[0];
 //================================================================================
 //	LOCALPARAMS
 //================================================================================
@@ -301,6 +303,9 @@ localparam Spi6RxFifo = 12'h24c;
 
 localparam SpiTxRxEn = 12'hF00;
 localparam GPIOCtrlAddr = 12'hFF0;
+
+localparam Debug0Addr = 12'hFF8;
+localparam Debug1Addr = 12'hFFC;
 //================================================================================
 
 
@@ -365,6 +370,7 @@ always @(posedge Clk_i) begin
         Spi6RxFifoReg <= 0;
         SpiTxRxEnReg <= 0;
         GPIOAReg <= 0;
+        LedReg <= 0;
     end
     else begin 
         if (!wrEn_i) begin 
@@ -545,6 +551,9 @@ always @(posedge Clk_i) begin
                         GPIOCtrlAddr : begin 
                             GPIOAReg <= Data_i;
                         end
+                        Debug0Addr : begin 
+                            LedReg <= Data_i;
+                        end
                     endcase
                 end
                 1 : begin 
@@ -723,6 +732,9 @@ always @(posedge Clk_i) begin
                         GPIOCtrlAddr : begin 
                             GPIOAReg[15:8] <= Data_i[15:8];
                         end
+                        Debug0Addr : begin 
+                            LedReg[15:8] <= Data_i[15:8];
+                        end
                     endcase 
                 end
                 2 : begin 
@@ -901,6 +913,9 @@ always @(posedge Clk_i) begin
                         GPIOCtrlAddr : begin 
                             GPIOAReg[7:0] <= Data_i[7:0];
                         end
+                        Debug0Addr : begin 
+                            LedReg[7:0] <= Data_i[7:0];
+                        end
                     endcase
                 end
             endcase
@@ -1091,6 +1106,9 @@ always @(*) begin
                         GPIOCtrlAddr : begin 
                             ansReg = GPIOAReg;
                         end
+                        Debug0Addr : begin 
+                            ansReg = LedReg;
+                        end
                     endcase
                 end
                 1 : begin 
@@ -1269,6 +1287,9 @@ always @(*) begin
                         GPIOCtrlAddr : begin 
                             ansReg = GPIOAReg[15:8];
                         end
+                        Debug0Addr : begin 
+                            ansReg = LedReg[15:8];
+                        end
                     endcase
                 end
                 2 : begin 
@@ -1447,6 +1468,9 @@ always @(*) begin
                         GPIOCtrlAddr : begin 
                             ansReg = GPIOAReg[7:0];
                         end
+                        Debug0Addr : begin 
+                            ansReg = LedReg[7:0];
+                        end
                     endcase
                 end
             endcase

SRAM/SRAM_tb.v

@@ -1,208 +0,0 @@
-`timescale 1ns / 1ps
-module SRAM_tb;
-
-reg Clk123;
-reg Clk50;
-wire Rst_i;
-reg writeEn_i;
-reg readEn_i;
-reg Start_i;
-
-
-reg [27:0] sramData;
-
-wire [15:0] sramDataOut;
-wire [11:0] sramAddrOut;
-wire fullFlag;
-wire emptyFlag;
-
-
-reg [4:0] cnt; 
-reg [2:0] trCnt;
-reg SS;
-reg outputEn_i;
-
-
-
-
-assign sramDataOut =sramData[15:0];
-// assign sramDataOut = (!outputEn_i)?16'bz:sramData[15:0];
-assign sramAddrOut = sramData[27:16];
-
-
-
-
-always #(4.065) Clk123 = ~Clk123;
-always #(10) Clk50 = ~Clk50;
-
-
-initial begin 
-    Clk123 = 1'b1;
-    Clk50 = 1'b1;
-    Start_i = 1'b0;
-    #1500 Start_i = 1'b1;
-    #500 Start_i = 1'b0;
-end
-
-
-
-
-
-always @(posedge Clk123) begin 
-    if (Rst_i) begin 
-        cnt <= 1'b0;
-    end
-    else begin  
-        if (cnt < 20 ) begin 
-            cnt <= cnt + 1'b1;
-        end
-        else begin 
-            cnt <= 1'b0;
-        end
-    end
-end
-
-
-always @(posedge Clk123) begin 
-    if (Rst_i) begin 
-        trCnt <= 1'b0;
-    end
-    else begin 
-        if (cnt == 20 ) begin 
-            trCnt <= trCnt + 1'b1;
-        end
-    end
-end
-
-
-always @(posedge Clk123) begin 
-    if (Rst_i) begin 
-        sramData <= 28'h00000000;
-    end
-    else begin 
-        case (trCnt) 
-            0 : begin 
-                sramData <= {11'h0, 16'h01};
-            end
-            1 : begin 
-                sramData <= {11'h02, 16'h00};
-            end
-        endcase
-    end
-end
-
-
-
-
-always @(negedge Clk123) begin 
-    if (Rst_i) begin 
-        SS <= 1'b1;
-    end
-    else begin 
-        if ( cnt >= 0 && cnt !== 9 ) begin 
-            SS <= 1'b0;
-        end
-        else begin 
-            SS <= 1'b1;
-        end
-    end
-end
-
-
-
-always @(negedge Clk123) begin 
-    if (Rst_i) begin 
-        writeEn_i <= 1'b1;
-    end
-    else begin 
-        if (cnt >= 2 && cnt <= 6 ) begin 
-            writeEn_i <= 1'b0;
-        end
-        else begin 
-            writeEn_i <= 1'b1;
-        end
-    end
-end
-
-
-always @(negedge Clk123) begin 
-    if (Rst_i) begin 
-        outputEn_i <= 1'b1;
-    end
-    else begin 
-        if (cnt >= 10 && cnt <= 19 ) begin 
-            outputEn_i <= 1'b0;
-        end
-        else begin 
-            outputEn_i <= 1'b1;
-        end
-    end
-end
-
-
-always @(negedge Clk123) begin 
-    if (Rst_i) begin 
-        readEn_i <= 1'b1;
-    end
-    else begin 
-        if ((cnt >= 13 && cnt <= 18) ) begin 
-            readEn_i <= 1'b0;
-        end
-        else begin 
-            readEn_i <= 1'b1;
-        end
-    end
-end
-
-
-
-
-// always @(posedge Clk_i) begin 
-//     if (Rst_i) begin 
-//         CE_i <= 1'b0;
-//     end
-//     else begin
-//         if (!fullFlag && ) begin
-//             CE_i <= 1'b1;
-//         end
-//         else begin
-//             CE_i <= 1'b0;
-//         end
-//     end
-// end
-
-
-SRAMr SRAMr_inst (
-    .Clk123_i(Clk123),
-    // .Clk50_i(Clk50),
-    // .Rst_i(Rst_i),
-    // .Start_i(Start_i),
-    .Addr_i(sramAddrOut),
-    .Data_i(),
-    .writeEn_i(writeEn_i),
-    .readEn_i(readEn_i)
-    // .fullFlag(fullFlag),
-    // .emptyFlag(emptyFlag),
-
-);
-
-
-
-
-InitRst InitRst_inst (
-    .clk_i(Clk123),
-    .signal_o(Rst_i)
-
-);
-
-
-
-
-
-
-
-
-
-endmodule
-
-

SRAM/SRAMr.v

@@ -1,92 +0,0 @@
-
-module SRAMr #(
-    parameter CmdRegWidth = 32,
-    parameter AddrRegWidth = 12
-
-) (
-    input Clk123_i,
-    // input Clk50_i,
-    input [AddrRegWidth-2:0] Addr_i,
-    inout [CmdRegWidth/2-1:0] Data_i,
-    // input Start_i,
-    input writeEn_i,
-    input readEn_i,
-    input [1:0] BE_i,
-    input outputEn_i,
-
-    // output wire fullFlag,
-    // output wire emptyFlag,
-    output  Led_o
-   
-
-
-
-
-
-
-
-
-);
-//testComment
-//================================================================================
-//  REG/WIRE
-//================================================================================
-
-    wire wrEn;
-    wire rdEn;
-    wire Rst_i;
-    wire [CmdRegWidth/2-1:0] data;
-    wire [AddrRegWidth-1:0] addr; 
-
-    wire mosi0;
-    wire mosi1;
-    wire mosi2;
-    wire mosi3;
-    wire sck;
-    wire ss;
-
-//================================================================================
-//  ASSIGNMENTS
-//================================================================================
-assign addr = {Addr_i, 1'b0};
-assign Data_i = (!outputEn_i) ? data : 16'bz;
-
-
-
-
-
-//================================================================================
-//  CODING
-//================================================================================	
-
-
-
-RegMap #(
-    .CmdRegWidth(32),
-    .AddrRegWidth(12)
-)
-RegMap_inst (
-    .Clk_i(Clk123_i),
-    .Rst_i(Rst_i),
-    .Data_i(Data_i),
-    .Addr_i(addr),
-    .wrEn_i(writeEn_i),
-    .rdEn_i(readEn_i),
-    .BE_i(BE_i),
-    .Led_o(Led_o),
-    .AnsDataReg_o(data)
-
-);
-
-
-InitRst InitRst_inst (
-    .clk_i(Clk123_i),
-    .signal_o(Rst_i)
-
-);
-
-
-
-
-
-endmodule

constrs_1/new/S5443_3.xdc

@@ -87,6 +87,8 @@ set_property PACKAGE_PIN K1 [get_ports {Sck_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[0]}]
 set_property PACKAGE_PIN H1 [get_ports {Ss_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[0]}]
+set_property PACKAGE_PIN K2 [get_ports {SsFlash_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[0]}]
 set_property PACKAGE_PIN J1 [get_ports {Mosi0_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[0]}]
 set_property PACKAGE_PIN J3 [get_ports {Mosi1_o[0]}]
@@ -107,6 +109,8 @@ set_property PACKAGE_PIN N2 [get_ports {Sck_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[1]}]
 set_property PACKAGE_PIN N4 [get_ports {Ss_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[1]}]
+set_property PACKAGE_PIN P1 [get_ports {SsFlash_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[1]}]
 set_property PACKAGE_PIN N3 [get_ports {Mosi0_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[1]}]
 set_property PACKAGE_PIN R2 [get_ports {Mosi1_o[1]}]
@@ -127,6 +131,8 @@ set_property PACKAGE_PIN E2 [get_ports {Sck_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[2]}]
 set_property PACKAGE_PIN E1 [get_ports {Ss_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[2]}]
+set_property PACKAGE_PIN F1 [get_ports {SsFlash_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[2]}]
 set_property PACKAGE_PIN D1 [get_ports {Mosi0_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[2]}]
 set_property PACKAGE_PIN D2 [get_ports {Mosi1_o[2]}]
@@ -146,6 +152,8 @@ set_property PACKAGE_PIN R10 [get_ports {Sck_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[3]}]
 set_property PACKAGE_PIN P10 [get_ports {Ss_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[3]}]
+set_property PACKAGE_PIN N10 [get_ports {SsFlash_o[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[3]}]
 set_property PACKAGE_PIN N8 [get_ports {Mosi0_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[3]}]
 set_property PACKAGE_PIN R8 [get_ports {Mosi1_o[3]}]
@@ -167,6 +175,8 @@ set_property PACKAGE_PIN R14 [get_ports {Sck_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[4]}]
 set_property PACKAGE_PIN N14 [get_ports {Ss_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[4]}]
+set_property PACKAGE_PIN P14 [get_ports {SsFlash_o[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[4]}]
 set_property PACKAGE_PIN R13 [get_ports {Mosi0_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[4]}]
 set_property PACKAGE_PIN P12 [get_ports {Mosi1_o[4]}]
@@ -187,6 +197,8 @@ set_property PACKAGE_PIN P6 [get_ports {Sck_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[5]}]
 set_property PACKAGE_PIN R5 [get_ports {Ss_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[5]}]
+set_property PACKAGE_PIN R6 [get_ports {SsFlash_o[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[5]}]
 set_property PACKAGE_PIN R4 [get_ports {Mosi0_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[5]}]
 set_property PACKAGE_PIN R3 [get_ports {Mosi1_o[5]}]
@@ -206,6 +218,8 @@ set_property PACKAGE_PIN B5 [get_ports {Sck_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[6]}]
 set_property PACKAGE_PIN B3 [get_ports {Ss_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[6]}]
+set_property PACKAGE_PIN A4 [get_ports {SsFlash_o[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[6]}]
 set_property PACKAGE_PIN B1 [get_ports {Mosi0_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[6]}]
 set_property PACKAGE_PIN C4 [get_ports {Mosi1_o[6]}]

sources_1/new/S5443_3Top.v

@@ -33,7 +33,6 @@ module S5443_3Top #(
     
     input writeEn_i,
     input readEn_i,
-    // input DspRst_i,
     input [1:0] BE_i,
     input outputEn_i,
     output [SpiNum-1:0] LD_i,
@@ -45,6 +44,7 @@ module S5443_3Top #(
     output  [SpiNum-1:0] Mosi2_o,
     output  [SpiNum-1:0] Mosi3_o,
     output  [SpiNum-1:0] Ss_o,
+    output  [SpiNum-1:0] SsFlash_o,
     output  [SpiNum-1:0] Sck_o,
     output  [SpiNum-1:0] SpiRst_o,
     output  LD_o
@@ -161,6 +161,11 @@ wire [SpiNum-1:0] FifoTxRst;
 wire [0:7]  WordCntTx [SpiNum-1:0];
 wire [0:7]  WordCntRx [SpiNum-1:0];
 
+wire [SpiNum-1:0] CS0;
+wire [SpiNum-1:0] CS1;
+
+wire [SpiNum-1:0] Assel;
+
 
 
 //================================================================================
@@ -173,7 +178,20 @@ assign Mosi0_o = Mosi0;
 assign Mosi1_o = Mosi1;
 assign Mosi2_o = Mosi2;
 assign Mosi3_o = Mosi3;
-assign Ss_o = Ss;
+assign Ss_o[0] = (Assel[0])? ((CS0[0])? Ss[0]:~Ss[0]):CS0[0];
+assign Ss_o[1] = (Assel[1])? ((CS0[1])? Ss[1]:~Ss[1]):CS0[1];
+assign Ss_o[2] = (Assel[2])? ((CS0[2])? Ss[2]:~Ss[2]):CS0[2];
+assign Ss_o[3] = (Assel[3])? ((CS0[3])? Ss[3]:~Ss[3]):CS0[3];
+assign Ss_o[4] = (Assel[4])? ((CS0[4])? Ss[4]:~Ss[4]):CS0[4];
+assign Ss_o[5] = (Assel[5])? ((CS0[5])? Ss[5]:~Ss[5]):CS0[5];
+assign Ss_o[6] = (Assel[6])? ((CS0[6])? Ss[6]:~Ss[6]):CS0[6];
+assign SsFlash_o[0] = (Assel[0])?(CS1[0]? Ss[0]:~Ss[0]):CS1[0];
+assign SsFlash_o[1] = (Assel[1])?(CS1[1]? Ss[1]:~Ss[1]):CS1[1];
+assign SsFlash_o[2] = (Assel[2])?(CS1[2]? Ss[2]:~Ss[2]):CS1[2];
+assign SsFlash_o[3] = (Assel[3])?(CS1[3]? Ss[3]:~Ss[3]):CS1[3];
+assign SsFlash_o[4] = (Assel[4])?(CS1[4]? Ss[4]:~Ss[4]):CS1[4];
+assign SsFlash_o[5] = (Assel[5])?(CS1[5]? Ss[5]:~Ss[5]):CS1[5];
+assign SsFlash_o[6] = (Assel[6])?(CS1[6]? Ss[6]:~Ss[6]):CS1[6];
 assign Sck_o = Sck;
 
 assign widthSel[0] = Spi0Ctrl[6:5];
@@ -216,6 +234,15 @@ assign selSt[4] = Spi4Ctrl[4];
 assign selSt[5] = Spi5Ctrl[4];
 assign selSt[6] = Spi6Ctrl[4];
 
+assign Assel[0] = Spi0Ctrl[3];
+assign Assel[1] = Spi1Ctrl[3];
+assign Assel[2] = Spi2Ctrl[3];
+assign Assel[3] = Spi3Ctrl[3];
+assign Assel[4] = Spi4Ctrl[3];
+assign Assel[5] = Spi5Ctrl[3];
+assign Assel[6] = Spi6Ctrl[3];
+
+
 assign stopDelay[0] = Spi0CsDelay[7:2];
 assign stopDelay[1] = Spi1CsDelay[7:2];
 assign stopDelay[2] = Spi2CsDelay[7:2];
@@ -298,6 +325,25 @@ assign WordCntTx[4] = Spi4TxFifoCtrl[15:8];
 assign WordCntTx[5] = Spi5TxFifoCtrl[15:8];
 assign WordCntTx[6] = Spi6TxFifoCtrl[15:8];
 
+assign CS0[0] = Spi0CsCtrl[0];
+assign CS0[1] = Spi1CsCtrl[0];
+assign CS0[2] = Spi2CsCtrl[0];
+assign CS0[3] = Spi3CsCtrl[0];
+assign CS0[4] = Spi4CsCtrl[0];
+assign CS0[5] = Spi5CsCtrl[0];
+assign CS0[6] = Spi6CsCtrl[0];
+
+assign CS1[0] = Spi0CsCtrl[1];
+assign CS1[1] = Spi1CsCtrl[1];
+assign CS1[2] = Spi2CsCtrl[1];
+assign CS1[3] = Spi3CsCtrl[1];
+assign CS1[4] = Spi4CsCtrl[1];
+assign CS1[5] = Spi5CsCtrl[1];
+assign CS1[6] = Spi6CsCtrl[1];
+
+
+
+
 
 //================================================================================
 //  CODING