Repo init

AdcInit/AdcInitInterface.v

@@ -0,0 +1,94 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    11:56:45 07/11/2019 
+// design name: 
+// module name:    adc_init_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	AdcInitInterface	
+#(
+	parameter	DelayValue		=	24000,
+	parameter	LengthWidth		=	2000,
+	parameter	DataWidth		=	24,
+	parameter	DataNum			=	26
+)
+(
+    input	wire	Clk_i,
+	input	wire	Rst_i,
+	
+	output	wire	AdcMosi_o,
+	output	wire	AdcClk_o,
+	output	wire	AdcCs_o,
+	output	wire	AdcRst_o
+);
+//================================================================================
+//  reg/wire
+//================================================================================	
+	wire			adcRstDone;
+	wire			adcFilteredRst;
+//================================================================================
+//  instantiations
+//================================================================================	
+
+ResetFilter #(
+    .STAGE_NUM      (4),
+    .RESET_FRONT    ("RISING")
+) 
+adcResetFilter 
+(
+    .clk_i          (Clk_i),
+    .rst_i          (Rst_i),
+    .perm_i         (1'b0),
+    .filtered_rst_o (adcFilteredRst)
+);
+
+AdcInitRst
+#(
+	.DELAY_VALUE    (DelayValue),	//задержка перед выдачей reset'а
+	.LENGTH_WIDTH   (LengthWidth)		//длительность сигнала reset
+) 
+AdcInitRst 
+(
+	.clk_i      (Clk_i),
+	.rst_i      (adcFilteredRst),
+	.signal_o   (AdcRst_o),
+	.done_o     (adcRstDone)
+);
+
+PeriphSpiInit 
+#(
+	.DATA_WIDTH             (DataWidth),
+	.DATA_NUM               (DataNum), 
+	.ROM_INIT_FILE          ("C:/Users/User/Desktop/4portCompact/S5443/S5443_M/S5443.srcs/sources_1/new/AdcInit/initFiles/AdcInitData.txt"),
+	.FILE_DATA_BASE         ("HEX"),
+	.SPI_CLK_DIVISOR_POWER  (4),
+	.SPI_CPOL               (0),
+	.SPI_CPHA               (0),
+	.SPI_DATA_DIRECTION     ("MSB"),
+	.SPI_EN_START_DELAY     ("YES")
+) 
+PeriphSpiInitController 
+(
+	.clk_i                  (Clk_i),
+	.rst_i                  (adcFilteredRst),
+	.enable_i               (adcRstDone),
+	.mosi_o                 (AdcMosi_o),
+	.sck_o                  (AdcClk_o),
+	.ss_o                   (AdcCs_o),
+	.done_o                 ()
+);
+
+endmodule

AdcInit/AdcInitRst.v

@@ -0,0 +1,130 @@
+module AdcInitRst (
+    clk_i,
+    rst_i,
+
+    signal_o,
+    done_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 24000;
+    parameter   LENGTH_WIDTH    = 2;
+
+    localparam  DELAY_CNT_W = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    input           rst_i;
+    output  reg     signal_o;
+    output  reg     done_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam  [1:0]   SM_RST_S    = 2'b00;
+    localparam  [1:0]   SM_DELAY_S  = 2'b01;
+    localparam  [1:0]   SM_SIGNAL_S = 2'b10;
+    localparam  [1:0]   SM_DONE_S   = 2'b11;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg     [1:0]               curr_state;
+    reg     [1:0]               next_state;
+
+    reg     [DELAY_CNT_W-1:0]   delay_cnt;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next;
+    reg                         signal_next;
+    reg                         done_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        curr_state  <= SM_RST_S;
+        delay_cnt   <= {DELAY_CNT_W{1'b0}};
+        signal_o    <= 1'b0;
+        done_o      <= 1'b0;
+    end else begin
+        curr_state  <= next_state;
+        delay_cnt   <= delay_cnt_next;
+        signal_o    <= signal_next;
+        done_o      <= done_next;
+    end
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = {DELAY_CNT_W{1'b0}};
+    signal_next     = 1'b0;
+    done_next       = 1'b0;
+    case(curr_state)
+        SM_RST_S    : begin
+            next_state  = SM_DELAY_S;
+        end
+
+        SM_DELAY_S  : begin
+            if (delay_cnt == DELAY_VALUE[DELAY_CNT_W-1:0]) begin
+                next_state      = SM_SIGNAL_S;
+                delay_cnt_next  = {DELAY_CNT_W{1'b0}};
+            end else begin
+                next_state      = SM_DELAY_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+
+        SM_SIGNAL_S : begin
+            signal_next = 1'b1;
+            if (delay_cnt == LENGTH_WIDTH[DELAY_CNT_W-1:0]) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_SIGNAL_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+
+        SM_DONE_S   : begin
+            done_next   = 1'b1;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

AdcInit/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 20;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

AdcInit/PeriphSpiInit.v

@@ -0,0 +1,217 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company                  :   NPK TAIR
+// Engineer                 :   Yuri Donskoy
+// 
+// Create Date (dd/mm/yyyy) :   16.05.2019
+// Design Name              :
+// Module Name              :
+// Project Name             :
+// Target Devices           :
+// Tool versions            :
+// Description              :
+//
+// Dependencies             : 
+// 
+// Revision                 :   0.01 - File Created
+// Additional Comments      :
+//        
+//////////////////////////////////////////////////////////////////////////////////
+
+module PeriphSpiInit (
+    clk_i,
+    rst_i,
+
+    enable_i,
+
+    mosi_o,
+    sck_o,
+    ss_o,
+
+    done_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DATA_WIDTH              = 24;
+    parameter   DATA_NUM                = 26; 
+    parameter   ROM_INIT_FILE           = "./initFiles/AdcInitData.txt";
+    parameter   FILE_DATA_BASE          = "HEX";
+    parameter   SPI_CLK_DIVISOR_POWER   = 4;
+    parameter   SPI_CPOL                = 0;
+    parameter   SPI_CPHA                = 0;
+    parameter   SPI_DATA_DIRECTION      = "MSB";   //  MSB or LSB
+    parameter   SPI_EN_START_DELAY      = "NO";     //  YES or NO
+
+    localparam  ROM_ADDR_WIDTH          = bit_num(DATA_NUM);
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam  [7:0]   SM_RST_S        = 8'd0;
+    localparam  [7:0]   SM_SEND_DATA_S  = 8'd2;
+    localparam  [7:0]   SM_READ_DATA_S  = 8'd3;
+    localparam  [7:0]   SM_WAIT_SPI_S   = 8'd4;
+    localparam  [7:0]   SM_DONE_S       = 8'd5;
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input       clk_i;
+    input       rst_i;
+    input       enable_i;
+    output      mosi_o;
+    output      sck_o;
+    output      ss_o;
+    output      done_o;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg     [ROM_ADDR_WIDTH-1:0]    rom_addr;
+    reg                             rom_valid;
+    wire    [DATA_WIDTH-1:0]        rom_data;
+    reg     [ROM_ADDR_WIDTH-1:0]    rom_addr_next;
+    wire                            spi_ready;
+    reg     [7:0]                   sm_curr_state;
+    reg     [7:0]                   sm_next_state;
+    wire                            data_end_flag;
+
+//================================================================================
+//
+//  INTEGER/GENVAR
+//
+//================================================================================
+
+
+
+//================================================================================
+//
+//  ASSIGN
+//
+//================================================================================
+
+    assign  data_end_flag   = (rom_addr == DATA_NUM);
+    assign  done_o          = sm_curr_state == SM_DONE_S;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+SpiMaster #(
+    .CLK_DIVISOR_POWER  (SPI_CLK_DIVISOR_POWER),
+    .DATA_WIDTH         (DATA_WIDTH),
+    .CPOL               (SPI_CPOL),
+    .CPHA               (SPI_CPHA),
+    .DATA_DIRECTION     (SPI_DATA_DIRECTION),
+    .EN_START_DELAY     (SPI_EN_START_DELAY)
+) SpiMaster (
+    .clk_i      (clk_i),
+    .rst_i      (rst_i),
+
+    .data_i     (rom_data),
+    .valid_i    (rom_valid),
+    .ready_o    (spi_ready),
+    .mosi_o     (mosi_o),
+    .sck_o      (sck_o),
+    .ss_o       (ss_o)
+);
+
+SinglePortRom #(
+    .DATA_WIDTH     (DATA_WIDTH), 
+    .ADDR_WIDTH     (ROM_ADDR_WIDTH),
+    .INIT_FILE_NAME (ROM_INIT_FILE),
+    .DATA_BASE      (FILE_DATA_BASE)
+) Rom (
+    .clk_i  (clk_i),
+    .addr_i (rom_addr),
+    .q_o    (rom_data)
+    );
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        sm_curr_state   <= 0;
+        rom_addr        <= SM_RST_S;
+    end else begin
+        sm_curr_state   <= sm_next_state;
+        rom_addr        <= rom_addr_next;
+    end
+end
+
+always @(*) begin
+    sm_next_state   = 0;
+    rom_addr_next   = rom_addr;
+    rom_valid       = 1'b0;
+    case(sm_curr_state)
+        SM_RST_S        :   begin
+            if (enable_i) begin
+                sm_next_state   = SM_SEND_DATA_S;
+            end else begin
+                sm_next_state   = SM_RST_S;
+            end
+        end
+
+        SM_SEND_DATA_S  :   begin
+            rom_valid       = 1'b1;
+            sm_next_state   = SM_SEND_DATA_S;
+            if (spi_ready) begin
+                rom_addr_next   = rom_addr + {{(ROM_ADDR_WIDTH-1){1'b0}}, 1'b1};
+                sm_next_state   = SM_READ_DATA_S;
+            end
+        end
+
+        SM_READ_DATA_S  :   begin
+            if (data_end_flag) begin
+                sm_next_state   = SM_WAIT_SPI_S;
+            end else begin
+                sm_next_state   = SM_SEND_DATA_S;
+            end
+        end
+
+        SM_WAIT_SPI_S   : begin
+            if (spi_ready) begin
+                sm_next_state   = SM_DONE_S;
+            end else begin
+                sm_next_state   = SM_WAIT_SPI_S;
+            end
+        end
+
+        SM_DONE_S       :   begin
+            sm_next_state   = SM_DONE_S;
+        end
+
+    endcase
+end
+
+endmodule

AdcInit/Power2ClkDivider.v

@@ -0,0 +1,90 @@
+`timescale 1ns / 1ps
+module Power2ClkDivider (
+    clk_i,
+    rst_i,
+    valid_i,
+    signal_o,
+    rising_edge_o,
+    falling_edge_o
+);
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DIVISOR_POWER   = 2;
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    input           rst_i;
+    input           valid_i;
+    output  reg     signal_o;
+    output  reg     rising_edge_o;
+    output  reg     falling_edge_o;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    wire    clk_div_flag;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+//initial begin
+//    if (DIVISOR_POWER < 1) begin
+//        $error("parameter DIVISOR_POWER of module power2_clk_divider must be greater then 0");
+//        $stop;
+//    end
+//end
+
+generate
+    if (DIVISOR_POWER < 2) begin
+        assign  clk_div_flag    = 1'b1;
+    end else begin
+        reg     [DIVISOR_POWER-2:0] clk_div_cnt;
+        always @(posedge clk_i or posedge rst_i) begin
+            if (rst_i) begin
+                clk_div_cnt <= {DIVISOR_POWER{1'b1}};
+            end else if (valid_i) begin
+                clk_div_cnt <= clk_div_cnt + 1;
+            end else begin
+                clk_div_cnt <= {DIVISOR_POWER{1'b1}};
+            end
+        end
+
+        assign  clk_div_flag    = &clk_div_cnt;
+    end
+endgenerate
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        signal_o        <= 1'b0;
+        rising_edge_o   <= 1'b0;
+        falling_edge_o  <= 1'b0;
+    end else if (valid_i) begin
+        if (clk_div_flag) begin
+            signal_o    <= ~signal_o;
+        end
+        rising_edge_o   <= ~signal_o & clk_div_flag;
+        falling_edge_o  <= signal_o & clk_div_flag;
+    end else begin
+        signal_o        <= 1'b0;
+        rising_edge_o   <= 1'b0;
+        falling_edge_o  <= 1'b0;
+    end
+end
+
+endmodule

AdcInit/ResetFilter.v

@@ -0,0 +1,60 @@
+module ResetFilter (
+    clk_i,
+    rst_i,
+    perm_i,
+    filtered_rst_o
+);
+
+    parameter   STAGE_NUM   = 1;
+    parameter   RESET_FRONT = "RISING"; //  FALLING
+
+    input   clk_i;
+    input   rst_i;
+    input   perm_i;
+    output  filtered_rst_o;
+
+    reg [STAGE_NUM-1:0] rst_filter;
+
+    assign  filtered_rst_o  = rst_filter[STAGE_NUM-1];
+
+generate
+    if (RESET_FRONT == "RISING") begin
+        if (STAGE_NUM < 2) begin
+            always @(posedge clk_i or posedge rst_i) begin
+                if (rst_i) begin
+                    rst_filter  <= 1'b1;
+                end else begin
+                    rst_filter  <= perm_i;
+                end
+            end
+        end else begin
+            always @(posedge clk_i or posedge rst_i) begin
+                if (rst_i) begin
+                    rst_filter  <= {STAGE_NUM{1'b1}};
+                end else begin
+                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
+                end
+            end        
+        end
+    end else begin
+        if (STAGE_NUM < 2) begin
+            always @(posedge clk_i or negedge rst_i) begin
+                if (!rst_i) begin
+                    rst_filter  <= 1'b1;
+                end else begin
+                    rst_filter  <= perm_i;
+                end
+            end
+        end else begin
+            always @(posedge clk_i or negedge rst_i) begin
+                if (!rst_i) begin
+                    rst_filter  <= {STAGE_NUM{1'b1}};
+                end else begin
+                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
+                end
+            end        
+        end    
+    end
+endgenerate
+
+endmodule

AdcInit/SinglePortRom.v

@@ -0,0 +1,30 @@
+module SinglePortRom (
+    clk_i, 
+    addr_i,
+    q_o
+);
+
+    parameter   DATA_WIDTH      = 16; 
+    parameter   ADDR_WIDTH      = 5;
+    parameter   INIT_FILE_NAME  = "./initFiles/AdcInitData.txt";
+    parameter   DATA_BASE       = "HEX";    //  HEX or BIN
+
+    input                                   clk_i;
+    input           [(ADDR_WIDTH-1):0]      addr_i;
+    output  reg     [(DATA_WIDTH-1):0]      q_o;
+
+    reg     [DATA_WIDTH-1:0]    rom[2**ADDR_WIDTH-1:0];
+
+initial begin
+    if (DATA_BASE == "HEX") begin
+        $readmemh(INIT_FILE_NAME, rom);
+    end else begin
+        $readmemb(INIT_FILE_NAME, rom);
+    end
+end
+
+always @ (posedge clk_i) begin
+    q_o <=  rom[addr_i];
+end
+
+endmodule

AdcInit/SpiMaster.v

@@ -0,0 +1,273 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company                  :   NPK TAIR
+// Engineer                 :   Yuri Donskoy
+// 
+// Create Date (dd/mm/yyyy) :
+// Design Name              :
+// Module Name              :
+// Project Name             :
+// Target Devices           :
+// Tool versions            :
+// Description              :
+//
+// Dependencies             : 
+// 
+// Revision                 :   1.0 - It only send data (no miso port)
+// Additional Comments      :   MISO port need to be add. What about multiple slave select?
+//        
+//////////////////////////////////////////////////////////////////////////////////
+
+module SpiMaster (
+    clk_i,
+    rst_i,
+
+    data_i,
+    valid_i,
+    ready_o,
+
+    mosi_o,
+    sck_o,
+    ss_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   CLK_DIVISOR_POWER   = 4; //WAS 2 !! DONT FORGET TO CHANGE!
+    parameter   DATA_WIDTH          = 24;
+    parameter   CPOL                = 0;
+    parameter   CPHA                = 0;
+    parameter   DATA_DIRECTION      = "MSBT";   //  MSB or LSB
+    parameter   EN_START_DELAY      = "NO";     //  YES or NO
+
+    localparam  BIT_CNT_W           = bit_num(DATA_WIDTH);
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam  SM_IDLE_S   = 2'b00;
+    localparam  SM_START_S  = 2'b01;
+    localparam  SM_DATA_S   = 2'b10;
+    localparam  SM_STOP_S   = 2'b11;
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input                               clk_i;
+    input                               rst_i;
+
+    input           [DATA_WIDTH-1:0]    data_i;
+    input                               valid_i;
+    output                              ready_o;
+
+    output  reg                         mosi_o;
+    output  reg                         sck_o;
+    output  reg                         ss_o;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg     [1:0]               sm_curr_state;
+    reg     [1:0]               sm_next_state;
+
+    reg                         sm_clk_div_en;
+
+    //  Clock divider outputs
+
+    wire                        clk_divider_redge;
+    wire                        clk_divider_fedge;
+
+    //  Bits counter
+
+    reg     [BIT_CNT_W-1:0]     bit_cnt_r;
+    reg     [BIT_CNT_W-1:0]     bit_cnt_next;
+
+    //  Data buffers
+
+    reg     [DATA_WIDTH-1:0]    tx_buffer_r;
+    reg     [DATA_WIDTH-1:0]    tx_buffer_next;
+    wire    [DATA_WIDTH-1:0]    tx_buffer_shifted;
+    wire                        tx_curr_bit;
+
+    //  Output data next
+    reg                         mosi_next;
+    reg                         sck_next;
+    reg                         ss_next;
+
+    //  Edges
+
+    wire                        mosi_shift_edge;
+
+    wire                        ss_start_edge;
+    wire                        ss_stop_edge;
+
+    wire                        sck_leading_edge;
+    wire                        sck_trailing_edge;
+
+//================================================================================
+//
+//  INTEGER/GENVAR
+//
+//================================================================================
+
+
+
+//================================================================================
+//
+//  ASSIGN
+//
+//================================================================================
+
+    assign  mosi_shift_edge     = (CPHA[0] == 1'b1) && (EN_START_DELAY != "YES") || (CPHA[0] == 1'b0) && (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
+    assign  ss_start_edge       = (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
+    assign  ss_stop_edge        = (EN_START_DELAY == "YES") ? clk_divider_redge : clk_divider_fedge;
+    assign  sck_leading_edge    = (EN_START_DELAY == "YES") ? clk_divider_redge : clk_divider_fedge;
+    assign  sck_trailing_edge   = (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
+    assign  tx_buffer_shifted   = (DATA_DIRECTION == "MSB") ? tx_buffer_r << 1 : tx_buffer_r >> 1;
+    assign  tx_curr_bit         = (DATA_DIRECTION == "MSB") ? tx_buffer_r[DATA_WIDTH-1] : tx_buffer_r[0];
+
+    assign  ready_o             = sm_curr_state == SM_IDLE_S;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+//  Sequential logic
+
+always @(posedge clk_i or posedge rst_i) begin
+    if (rst_i) begin
+        sm_curr_state   <= 0;
+        tx_buffer_r     <= {DATA_WIDTH{1'b0}};
+        bit_cnt_r       <= {BIT_CNT_W{1'b0}};
+        mosi_o          <= 1'b0;
+        sck_o           <= CPOL[0];
+        ss_o            <= 1'b1;
+    end else begin
+        sm_curr_state   <= sm_next_state;
+        tx_buffer_r     <= tx_buffer_next;
+        bit_cnt_r       <= bit_cnt_next;
+        mosi_o          <= mosi_next;
+        sck_o           <= sck_next;
+        ss_o            <= ss_next;
+    end
+end
+
+//  Combinational logic
+
+always @(*) begin
+    sm_next_state   = SM_IDLE_S;
+    tx_buffer_next  = tx_buffer_r;
+    mosi_next       = mosi_o;
+    sck_next        = sck_o;
+    ss_next         = ss_o;
+    sm_clk_div_en   = 1'b1;
+    bit_cnt_next    = bit_cnt_r;
+
+    case(sm_curr_state)
+
+        SM_IDLE_S   : begin
+            if (valid_i) begin
+                sm_next_state   = SM_START_S;
+            end else begin
+                sm_next_state   = SM_IDLE_S;
+            end
+            tx_buffer_next  = data_i;
+            sm_clk_div_en   = 1'b0;
+            bit_cnt_next    = {BIT_CNT_W{1'b0}};
+        end
+
+        SM_START_S  : begin
+            if (ss_start_edge) begin
+                sm_next_state   = SM_DATA_S;
+                ss_next         = 1'b0;
+                if (!CPHA[0]) begin
+                    mosi_next       = tx_curr_bit;
+                    tx_buffer_next  = tx_buffer_shifted;
+                    bit_cnt_next    = bit_cnt_r + {{(BIT_CNT_W-1){1'b0}}, 1'b1};
+                end
+            end else begin
+                sm_next_state   = SM_START_S;
+            end
+        end
+
+        SM_DATA_S   : begin
+            sm_next_state   = SM_DATA_S;
+            if (sck_leading_edge) begin
+                sck_next    = ~CPOL[0];
+            end
+
+            if  (sck_trailing_edge) begin
+                sck_next    = CPOL[0];
+                if (bit_cnt_r == DATA_WIDTH[BIT_CNT_W-1:0]) begin
+                    sm_next_state   = SM_STOP_S;
+                end
+            end
+
+            if (mosi_shift_edge) begin
+                mosi_next       = tx_curr_bit;
+                tx_buffer_next  = tx_buffer_shifted;
+                bit_cnt_next    = bit_cnt_r + {{(BIT_CNT_W-1){1'b0}}, 1'b1};
+            end
+
+        end
+
+        SM_STOP_S   : begin
+            if (ss_stop_edge) begin
+                if (CPHA[0]) begin
+                    mosi_next   = tx_curr_bit;
+                end
+                sm_next_state   = SM_IDLE_S;
+                ss_next         = 1'b1;
+            end else begin
+                sm_next_state   = SM_STOP_S;
+            end
+        end
+
+    endcase
+end
+
+//  Clock divider
+
+Power2ClkDivider #(
+    .DIVISOR_POWER      (CLK_DIVISOR_POWER)
+) ClkDividerInst (
+    .clk_i              (clk_i),
+    .rst_i              (rst_i),
+    .valid_i            (sm_clk_div_en),
+    .signal_o           (),
+    .rising_edge_o      (clk_divider_redge),
+    .falling_edge_o     (clk_divider_fedge)
+);
+
+endmodule

AdcInit/initFiles/AdcInitData.txt

@@ -0,0 +1,26 @@
+400601
+40013C
+400300
+400400
+400533
+400602 
+400700
+400900
+400A02
+400B20
+400ED1
+400FD4
+401300
+401500
+402500
+402700
+441D00
+442202
+443428
+443908
+451D00
+452202
+453428
+453908
+460800
+470A00

SRAM/QuadSPIm.v

@@ -0,0 +1,165 @@
+module QuadSPIm(
+    input Clk_i,
+    input Rst_i,
+    input [27:0] Data_i,
+    input Start_i,
+
+
+
+
+
+
+    output Mosi0_i,
+    output Mosi1_i,
+    output Mosi2_i,
+    output Mosi3_i,
+    output Sck_o,
+    output Ss_o
+
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+reg startFlag;
+reg [2:0] ssCnt;
+reg Ss;
+reg SSr;
+reg [6:0] mosiReg0;
+reg [6:0] mosiReg1;
+reg [6:0] mosiReg2;
+reg [6:0] mosiReg3;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign Mosi0_i = (!Ss) ? (mosiReg3[6]):1'b0;
+assign Mosi1_i = (!Ss) ? (mosiReg2[6]):1'b0;
+assign Mosi2_i = (!Ss) ? (mosiReg1[6]):1'b0;
+assign Mosi3_i = (!Ss) ? (mosiReg0[6]):1'b0;
+assign Ss_o    = Ss; 
+assign Sck_i   = (!Ss) ? (~Clk_i) : 1'b0;
+
+//================================================================================
+//  CODING
+//================================================================================	
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        SSr <=1'b0;
+    end
+    else begin 
+        SSr <= Ss;
+    end
+end
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        startFlag <= 1'b0;
+    end
+    else begin 
+        if (!Start_i) begin 
+            startFlag <= 1'b1;
+        end
+        else begin 
+            startFlag <= 1'b0;
+        end
+    end
+end
+
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        ssCnt <= 1'b0;
+    end
+    else if (ssCnt < 7 && startFlag  ) begin 
+        ssCnt <= ssCnt + 1'b1;
+    end
+    else begin
+        if (ssCnt == 6 || !startFlag) begin 
+            ssCnt <= 1'b0;
+        end
+    end
+end
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        Ss <= 1'b1;
+    end
+    else begin 
+        if (ssCnt < 7 && startFlag ) begin 
+            Ss <= 1'b0;
+        end
+        else begin 
+            Ss <= 1'b1;
+        end
+    end
+end
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        mosiReg0 <= Data_i[27:21];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg0 <= { mosiReg0[5:0],1'b0 };
+        end
+        else begin 
+            mosiReg0 <= Data_i[27:21];
+        end
+    end
+end
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        mosiReg1 <= Data_i[20:14];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg1 <= { mosiReg1[5:0],1'b0 };
+        end
+        else begin 
+            mosiReg1 <= Data_i[20:14];
+        end
+    end
+end
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        mosiReg2 <= Data_i[13:7];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg2 <= { mosiReg2[5:0],1'b0 };
+        end
+        else begin 
+            mosiReg2 <= Data_i[13:7];
+        end
+    end
+end
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        mosiReg3<= Data_i[6:0];
+    end
+    else begin 
+        if (!SSr) begin
+            mosiReg3 <= { mosiReg3[5:0],1'b0 };
+        end
+        else begin 
+            mosiReg3<= Data_i[6:0];
+        end
+    end
+end
+
+
+
+
+
+
+
+
+
+
+endmodule

SRAM/QuadSPIs.v

@@ -0,0 +1,150 @@
+module QuadSPIs (
+    input Clk_i,
+    input Rst_i,
+
+    input Sck_i,
+    input Ss_i,
+    input Mosi0_i,
+    input Mosi1_i,
+    input Mosi2_i,
+    input Mosi3_i,
+
+    output reg [23:0] Data_o,
+    output reg [7:0] Addr_o,
+    output reg Val_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+reg ssReg;
+reg ssRegR;
+reg RorWFlag;
+
+reg [3:0] cnt; 
+reg [7:0] addrReg;
+reg [7:0] shiftReg0R;
+reg [7:0] shiftReg1R;
+reg [7:0] shiftReg2R;
+reg [7:0] shiftReg0RR;
+reg [7:0] shiftReg1RR;
+reg [7:0] shiftReg2RR;
+reg [7:0] shiftReg0;
+reg [7:0] shiftReg1;
+reg [7:0] shiftReg2;
+//================================================================================
+//	CODING
+//================================================================================
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Data_o <= 24'h0;
+    end
+    else begin 
+        if (ssReg && !ssRegR) begin 
+            Data_o <= {shiftReg2, shiftReg1, shiftReg0};
+        end
+        else begin 
+            Data_o <= 24'h0;
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Addr_o <= 8'h0;
+    end
+    else begin 
+        if (ssReg && !ssRegR) begin 
+            Addr_o <= addrReg;
+        end
+    end
+end
+
+
+always @(posedge Sck_i) begin 
+    if (Rst_i) begin 
+        shiftReg0 <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg0 <= {shiftReg0[6:0], Mosi0_i};
+        end
+        else begin 
+            shiftReg0 <= 8'h0;
+        end
+    end
+end
+
+
+always @(posedge Sck_i ) begin 
+    if (Rst_i) begin 
+        shiftReg1 <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg1 <= {shiftReg1[6:0], Mosi1_i};
+        end
+        else begin 
+            shiftReg1 <= 8'h0;
+        end
+    end
+end
+
+
+always @(posedge Sck_i ) begin 
+    if (Rst_i) begin 
+        shiftReg2 <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg2 <= {shiftReg2[6:0], Mosi2_i};
+        end
+        else begin 
+            shiftReg2 <= 8'h0;
+        end
+    end
+end
+
+
+always @(posedge Sck_i ) begin 
+    if (Rst_i) begin 
+        addrReg <= 8'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            addrReg <= {addrReg[6:0], Mosi3_i};
+        end
+        else begin 
+            addrReg <= 8'h0;
+        end
+    end
+end
+
+
+always	@(posedge	Clk_i)	begin
+	ssReg	<=	Ss_i;
+	ssRegR	<=	ssReg;
+    shiftReg0R <= shiftReg0;
+    shiftReg1R <= shiftReg1;
+    shiftReg2R <= shiftReg2;
+    shiftReg0RR <= shiftReg0R;
+    shiftReg1RR <= shiftReg1R;
+    shiftReg2RR <= shiftReg2R;
+end
+
+
+always @(posedge Clk_i) begin 
+    if (ssReg && !ssRegR) begin 
+        Val_o <= 1'b1;
+    end
+    else begin 
+        Val_o <= 1'b0;
+    end
+end
+
+
+
+
+endmodule

SRAM/RegMap.v

@@ -0,0 +1,204 @@
+module RegMap #(
+    parameter CmdRegWidth = 32,
+    parameter AddrRegWidth = 12
+)
+(
+    input [CmdRegWidth/2-1:0] Data_i,
+    input [AddrRegWidth-1:0] Addr_i,
+    input Clk_i,
+    input Rst_i,
+    input wrEn_i,
+    input rdEn_i,  
+    input [1:0] BE_i,        
+
+
+    output   [CmdRegWidth/2-1:0] AnsDataReg_o,
+    output Led_o
+
+);
+
+
+
+
+
+
+
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+(* dont_touch = "TRUE" *)reg [CmdRegWidth-1:0] LedReg;
+(* dont_touch = "TRUE" *)reg [CmdRegWidth/2-1:0] debugReg1;
+(* dont_touch = "TRUE" *)reg [CmdRegWidth/2-1:0] debugReg2;
+(* dont_touch = "TRUE" *)reg [CmdRegWidth/2-1:0] ansReg;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+
+assign Led_o = LedReg[0];
+assign AnsDataReg_o = ansReg;
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
+
+localparam LedAddr = 12'h00;
+localparam LedAddrS = 12'h02; 
+localparam DebugAddr1 = 12'h04;
+localparam DebugAddr2 = 12'h06;
+//================================================================================
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        LedReg <= 0;
+        debugReg1 <= 0;
+        debugReg2 <= 0;
+    end
+    else begin 
+        if (!wrEn_i) begin 
+            case (BE_i)  
+                0 : begin 
+                    case (Addr_i) 
+                        LedAddr : begin 
+                            LedReg[15:0] <= Data_i;
+                        end
+                        LedAddrS : begin 
+                            LedReg[31:16] <= Data_i;
+                        end
+                        DebugAddr1 : begin
+                                debugReg1 <= Data_i;
+                        end 
+                        DebugAddr2 : begin 
+                                debugReg2 <= Data_i;
+                            end
+                    endcase
+                end
+                1 : begin 
+                    case (Addr_i)
+                        LedAddr : begin 
+                            LedReg[15:0] <= Data_i[15:8];
+                        end
+                        LedAddrS : begin 
+                            LedReg[31:16] <= Data_i[15:8];
+                        end
+                        DebugAddr1 : begin
+                                debugReg1[15:8] <= Data_i[15:8];
+                        end 
+                        DebugAddr2 : begin 
+                                debugReg2[15:8] <= Data_i[15:8];
+                            end
+                    endcase 
+                end
+                2 : begin 
+                    case (Addr_i) 
+                        LedAddr : begin 
+                            LedReg[15:0] <= Data_i[7:0];
+                        end
+                        LedAddrS : begin 
+                            LedReg[31:16] <= Data_i[7:0];
+                        end
+                        DebugAddr1 : begin
+                                debugReg1[7:0] <= Data_i[7:0];
+                        end 
+                        DebugAddr2 : begin 
+                                debugReg2[7:0] <= Data_i[7:0];
+                            end
+                    endcase
+                end
+            endcase
+        end
+    end
+end
+
+
+// always @(*) begin 
+//     if (Rst_i) begin 
+//         ansReg = 0;
+//     end
+//     else begin 
+//         if (rdEn_i) begin 
+//             case (Addr_i)
+//                 LedAddrS : begin 
+//                     ansReg = LedReg; 
+//                 end
+//                 DebugAddr1 : begin 
+//                     ansReg = debugReg1;
+//                 end
+//                 DebugAddr2 : begin 
+//                     ansReg = debugReg2;
+//                 end
+//                 endcase
+//         end
+//         else begin 
+//             ansReg = 0;
+//         end
+//     end
+// end
+
+always @(*) begin 
+    if (Rst_i) begin 
+        ansReg = 0;
+    end
+    else begin 
+        if (!rdEn_i) begin 
+            case(BE_i) 
+                0 : begin 
+                    case (Addr_i)
+                        LedAddr : begin
+                            ansReg = LedReg[15:0];
+                        end  
+                        LedAddrS : begin 
+                            ansReg = LedReg[31:16]; 
+                        end
+                        DebugAddr1 : begin 
+                            ansReg = debugReg1;
+                        end
+                        DebugAddr2 : begin 
+                            ansReg = debugReg2;
+                        end
+                    endcase
+                end
+                1 : begin 
+                    case (Addr_i)
+                        LedAddr : begin
+                            ansReg = LedReg[15:8];
+                        end
+                        LedAddrS : begin 
+                            ansReg = LedReg[31:24]; 
+                        end
+                        DebugAddr1 : begin 
+                            ansReg = debugReg1[15:8];
+                        end
+                        DebugAddr2 : begin 
+                            ansReg = debugReg2[15:8];
+                        end
+                    endcase
+                end
+                2 : begin 
+                    case (Addr_i)
+                        LedAddr : begin
+                             ansReg = LedReg[7:0];
+                         end
+                        LedAddrS : begin 
+                            ansReg = LedReg[23:16]; 
+                        end
+                        DebugAddr1 : begin 
+                            ansReg = debugReg1[7:0];
+                        end
+                        DebugAddr2 : begin 
+                            ansReg = debugReg2[7:0];
+                        end
+                    endcase
+                end
+            endcase
+        end
+        else begin 
+            ansReg = 0;
+        end
+    end
+end
+
+
+
+endmodule

SRAM/SRAM_tb.v

@@ -0,0 +1,208 @@
+`timescale 1ns / 1ps
+module SRAM_tb;
+
+reg Clk123;
+reg Clk50;
+wire Rst_i;
+reg writeEn_i;
+reg readEn_i;
+reg Start_i;
+
+
+reg [27:0] sramData;
+
+wire [15:0] sramDataOut;
+wire [11:0] sramAddrOut;
+wire fullFlag;
+wire emptyFlag;
+
+
+reg [4:0] cnt; 
+reg [2:0] trCnt;
+reg SS;
+reg outputEn_i;
+
+
+
+
+assign sramDataOut =sramData[15:0];
+// assign sramDataOut = (!outputEn_i)?16'bz:sramData[15:0];
+assign sramAddrOut = sramData[27:16];
+
+
+
+
+always #(4.065) Clk123 = ~Clk123;
+always #(10) Clk50 = ~Clk50;
+
+
+initial begin 
+    Clk123 = 1'b1;
+    Clk50 = 1'b1;
+    Start_i = 1'b0;
+    #1500 Start_i = 1'b1;
+    #500 Start_i = 1'b0;
+end
+
+
+
+
+
+always @(posedge Clk123) begin 
+    if (Rst_i) begin 
+        cnt <= 1'b0;
+    end
+    else begin  
+        if (cnt < 20 ) begin 
+            cnt <= cnt + 1'b1;
+        end
+        else begin 
+            cnt <= 1'b0;
+        end
+    end
+end
+
+
+always @(posedge Clk123) begin 
+    if (Rst_i) begin 
+        trCnt <= 1'b0;
+    end
+    else begin 
+        if (cnt == 20 ) begin 
+            trCnt <= trCnt + 1'b1;
+        end
+    end
+end
+
+
+always @(posedge Clk123) begin 
+    if (Rst_i) begin 
+        sramData <= 28'h00000000;
+    end
+    else begin 
+        case (trCnt) 
+            0 : begin 
+                sramData <= {11'h0, 16'h01};
+            end
+            1 : begin 
+                sramData <= {11'h02, 16'h00};
+            end
+        endcase
+    end
+end
+
+
+
+
+always @(negedge Clk123) begin 
+    if (Rst_i) begin 
+        SS <= 1'b1;
+    end
+    else begin 
+        if ( cnt >= 0 && cnt !== 9 ) begin 
+            SS <= 1'b0;
+        end
+        else begin 
+            SS <= 1'b1;
+        end
+    end
+end
+
+
+
+always @(negedge Clk123) begin 
+    if (Rst_i) begin 
+        writeEn_i <= 1'b1;
+    end
+    else begin 
+        if (cnt >= 2 && cnt <= 6 ) begin 
+            writeEn_i <= 1'b0;
+        end
+        else begin 
+            writeEn_i <= 1'b1;
+        end
+    end
+end
+
+
+always @(negedge Clk123) begin 
+    if (Rst_i) begin 
+        outputEn_i <= 1'b1;
+    end
+    else begin 
+        if (cnt >= 10 && cnt <= 19 ) begin 
+            outputEn_i <= 1'b0;
+        end
+        else begin 
+            outputEn_i <= 1'b1;
+        end
+    end
+end
+
+
+always @(negedge Clk123) begin 
+    if (Rst_i) begin 
+        readEn_i <= 1'b1;
+    end
+    else begin 
+        if ((cnt >= 13 && cnt <= 18) ) begin 
+            readEn_i <= 1'b0;
+        end
+        else begin 
+            readEn_i <= 1'b1;
+        end
+    end
+end
+
+
+
+
+// always @(posedge Clk_i) begin 
+//     if (Rst_i) begin 
+//         CE_i <= 1'b0;
+//     end
+//     else begin
+//         if (!fullFlag && ) begin
+//             CE_i <= 1'b1;
+//         end
+//         else begin
+//             CE_i <= 1'b0;
+//         end
+//     end
+// end
+
+
+SRAMr SRAMr_inst (
+    .Clk123_i(Clk123),
+    // .Clk50_i(Clk50),
+    // .Rst_i(Rst_i),
+    // .Start_i(Start_i),
+    .Addr_i(sramAddrOut),
+    .Data_i(),
+    .writeEn_i(writeEn_i),
+    .readEn_i(readEn_i)
+    // .fullFlag(fullFlag),
+    // .emptyFlag(emptyFlag),
+
+);
+
+
+
+
+InitRst InitRst_inst (
+    .clk_i(Clk123),
+    .signal_o(Rst_i)
+
+);
+
+
+
+
+
+
+
+
+
+endmodule
+
+

SRAM/SRAMr.v

@@ -0,0 +1,91 @@
+
+module SRAMr #(
+    parameter CmdRegWidth = 32,
+    parameter AddrRegWidth = 12
+
+) (
+    input Clk123_i,
+    // input Clk50_i,
+    input [AddrRegWidth-2:0] Addr_i,
+    inout [CmdRegWidth/2-1:0] Data_i,
+    // input Start_i,
+    input writeEn_i,
+    input readEn_i,
+    input [1:0] BE_i,
+    input outputEn_i,
+
+    // output wire fullFlag,
+    // output wire emptyFlag,
+    output  Led_o
+   
+
+
+
+
+
+
+
+
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+    wire wrEn;
+    wire rdEn;
+    wire Rst_i;
+    wire [CmdRegWidth/2-1:0] data;
+    wire [AddrRegWidth-1:0] addr; 
+
+    wire mosi0;
+    wire mosi1;
+    wire mosi2;
+    wire mosi3;
+    wire sck;
+    wire ss;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign addr = {Addr_i, 1'b0};
+assign Data_i = (!outputEn_i) ? data : 16'bz;
+
+
+
+
+
+//================================================================================
+//  CODING
+//================================================================================	
+
+
+
+RegMap #(
+    .CmdRegWidth(32),
+    .AddrRegWidth(12)
+)
+RegMap_inst (
+    .Clk_i(Clk123_i),
+    .Rst_i(Rst_i),
+    .Data_i(Data_i),
+    .Addr_i(addr),
+    .wrEn_i(writeEn_i),
+    .rdEn_i(readEn_i),
+    .BE_i(BE_i),
+    .Led_o(Led_o),
+    .AnsDataReg_o(data)
+
+);
+
+
+InitRst InitRst_inst (
+    .clk_i(Clk123_i),
+    .signal_o(Rst_i)
+
+);
+
+
+
+
+
+endmodule

constrs_1/new/S5443_3.xdc

@@ -0,0 +1,175 @@
+
+
+
+set_property PACKAGE_PIN C15 [get_ports {Addr_i[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[0]}]
+set_property PACKAGE_PIN C13 [get_ports {Addr_i[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[1]}]
+set_property PACKAGE_PIN D15 [get_ports {Addr_i[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[2]}]
+set_property PACKAGE_PIN C14 [get_ports {Addr_i[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[3]}]
+set_property PACKAGE_PIN E15 [get_ports {Addr_i[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[4]}]
+set_property PACKAGE_PIN D13 [get_ports {Addr_i[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[5]}]
+set_property PACKAGE_PIN F15 [get_ports {Addr_i[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[6]}]
+set_property PACKAGE_PIN E14 [get_ports {Addr_i[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[7]}]
+set_property PACKAGE_PIN J15 [get_ports {Addr_i[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[8]}]
+set_property PACKAGE_PIN F14 [get_ports {Addr_i[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[9]}]
+set_property PACKAGE_PIN K15 [get_ports {Addr_i[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Addr_i[10]}]
+
+
+
+set_property PACKAGE_PIN B15 [get_ports {Data_i[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[0]}]
+set_property PACKAGE_PIN B14 [get_ports {Data_i[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[1]}]
+set_property PACKAGE_PIN B11 [get_ports {Data_i[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[2]}]
+set_property PACKAGE_PIN B12 [get_ports {Data_i[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[3]}]
+set_property PACKAGE_PIN A12 [get_ports {Data_i[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[4]}]
+set_property PACKAGE_PIN B9 [get_ports {Data_i[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[5]}]
+set_property PACKAGE_PIN K14 [get_ports {Data_i[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[6]}]
+set_property PACKAGE_PIN A11 [get_ports {Data_i[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[7]}]
+set_property PACKAGE_PIN A6 [get_ports {Data_i[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[8]}]
+set_property PACKAGE_PIN A13 [get_ports {Data_i[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[9]}]
+set_property PACKAGE_PIN A10 [get_ports {Data_i[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[10]}]
+set_property PACKAGE_PIN B6 [get_ports {Data_i[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[11]}]
+set_property PACKAGE_PIN A5 [get_ports {Data_i[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[12]}]
+set_property PACKAGE_PIN B10 [get_ports {Data_i[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[13]}]
+set_property PACKAGE_PIN A8 [get_ports {Data_i[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[14]}]
+set_property PACKAGE_PIN A14 [get_ports {Data_i[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Data_i[15]}]
+
+
+
+set_property PACKAGE_PIN C6 [get_ports Led_o]
+set_property IOSTANDARD LVCMOS33 [get_ports Led_o]
+
+set_property PACKAGE_PIN A9 [get_ports writeEn_i]
+set_property IOSTANDARD LVCMOS33 [get_ports writeEn_i]
+
+set_property PACKAGE_PIN C5 [get_ports readEn_i]
+set_property IOSTANDARD LVCMOS33 [get_ports readEn_i]
+
+set_property PACKAGE_PIN C8 [get_ports outputEn_i]
+set_property IOSTANDARD LVCMOS33 [get_ports outputEn_i]
+
+set_property PACKAGE_PIN L15 [get_ports {BE_i[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {BE_i[1]}]
+set_property PACKAGE_PIN L14 [get_ports {BE_i[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {BE_i[0]}]
+
+
+
+
+
+#==========================================================================
+#	INPUT CLOCKS
+
+set_property PACKAGE_PIN M10 [get_ports Clk123_i]
+set_property IOSTANDARD LVCMOS33 [get_ports Clk123_i]
+create_clock -period 8.130 -name Clk123_i -waveform {0.000 4.065} -add [get_ports Clk123_i]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk123_i_IBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets writeEn_i_IBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets readEn_i_IBUF]
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+connect_debug_port u_ila_0/probe0 [get_nets [list {RegMap_inst/debugReg2[0]} {RegMap_inst/debugReg2[1]} {RegMap_inst/debugReg2[2]} {RegMap_inst/debugReg2[3]} {RegMap_inst/debugReg2[4]} {RegMap_inst/debugReg2[5]} {RegMap_inst/debugReg2[6]} {RegMap_inst/debugReg2[7]} {RegMap_inst/debugReg2[8]} {RegMap_inst/debugReg2[9]} {RegMap_inst/debugReg2[10]} {RegMap_inst/debugReg2[11]} {RegMap_inst/debugReg2[12]} {RegMap_inst/debugReg2[13]} {RegMap_inst/debugReg2[14]} {RegMap_inst/debugReg2[15]}]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {RegMap_inst/debugReg1[0]} {RegMap_inst/debugReg1[1]} {RegMap_inst/debugReg1[2]} {RegMap_inst/debugReg1[3]} {RegMap_inst/debugReg1[4]} {RegMap_inst/debugReg1[5]} {RegMap_inst/debugReg1[6]} {RegMap_inst/debugReg1[7]} {RegMap_inst/debugReg1[8]} {RegMap_inst/debugReg1[9]} {RegMap_inst/debugReg1[10]} {RegMap_inst/debugReg1[11]} {RegMap_inst/debugReg1[12]} {RegMap_inst/debugReg1[13]} {RegMap_inst/debugReg1[14]} {RegMap_inst/debugReg1[15]}]]
+
+
+
+connect_debug_port u_ila_0/probe0 [get_nets [list {RegMap_inst/debugReg2[0]} {RegMap_inst/debugReg2[1]} {RegMap_inst/debugReg2[2]} {RegMap_inst/debugReg2[3]} {RegMap_inst/debugReg2[4]} {RegMap_inst/debugReg2[5]} {RegMap_inst/debugReg2[6]} {RegMap_inst/debugReg2[7]} {RegMap_inst/debugReg2[8]} {RegMap_inst/debugReg2[9]} {RegMap_inst/debugReg2[10]} {RegMap_inst/debugReg2[11]} {RegMap_inst/debugReg2[12]} {RegMap_inst/debugReg2[13]} {RegMap_inst/debugReg2[14]} {RegMap_inst/debugReg2[15]}]]
+connect_debug_port u_ila_0/probe2 [get_nets [list {RegMap_inst/debugReg1[0]} {RegMap_inst/debugReg1[1]} {RegMap_inst/debugReg1[2]} {RegMap_inst/debugReg1[3]} {RegMap_inst/debugReg1[4]} {RegMap_inst/debugReg1[5]} {RegMap_inst/debugReg1[6]} {RegMap_inst/debugReg1[7]} {RegMap_inst/debugReg1[8]} {RegMap_inst/debugReg1[9]} {RegMap_inst/debugReg1[10]} {RegMap_inst/debugReg1[11]} {RegMap_inst/debugReg1[12]} {RegMap_inst/debugReg1[13]} {RegMap_inst/debugReg1[14]} {RegMap_inst/debugReg1[15]}]]
+
+
+connect_debug_port u_ila_0/probe9 [get_nets [list {RegMap_inst/LedReg_reg[0]_i_2_n_0}]]
+
+connect_debug_port u_ila_0/probe6 [get_nets [list {RegMap_inst/LedReg_reg[0]_i_1_n_0}]]
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list Clk123_i_IBUF_BUFG]]
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
+set_property port_width 2 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {BE_i_IBUF[0]} {BE_i_IBUF[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
+set_property port_width 11 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {Addr_i_IBUF[0]} {Addr_i_IBUF[1]} {Addr_i_IBUF[2]} {Addr_i_IBUF[3]} {Addr_i_IBUF[4]} {Addr_i_IBUF[5]} {Addr_i_IBUF[6]} {Addr_i_IBUF[7]} {Addr_i_IBUF[8]} {Addr_i_IBUF[9]} {Addr_i_IBUF[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
+set_property port_width 16 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {Data_i_IBUF[0]} {Data_i_IBUF[1]} {Data_i_IBUF[2]} {Data_i_IBUF[3]} {Data_i_IBUF[4]} {Data_i_IBUF[5]} {Data_i_IBUF[6]} {Data_i_IBUF[7]} {Data_i_IBUF[8]} {Data_i_IBUF[9]} {Data_i_IBUF[10]} {Data_i_IBUF[11]} {Data_i_IBUF[12]} {Data_i_IBUF[13]} {Data_i_IBUF[14]} {Data_i_IBUF[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
+set_property port_width 16 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {Data_i_OBUF[0]} {Data_i_OBUF[1]} {Data_i_OBUF[2]} {Data_i_OBUF[3]} {Data_i_OBUF[4]} {Data_i_OBUF[5]} {Data_i_OBUF[6]} {Data_i_OBUF[7]} {Data_i_OBUF[8]} {Data_i_OBUF[9]} {Data_i_OBUF[10]} {Data_i_OBUF[11]} {Data_i_OBUF[12]} {Data_i_OBUF[13]} {Data_i_OBUF[14]} {Data_i_OBUF[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe4]
+set_property port_width 16 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {RegMap_inst/debugReg1[0]} {RegMap_inst/debugReg1[1]} {RegMap_inst/debugReg1[2]} {RegMap_inst/debugReg1[3]} {RegMap_inst/debugReg1[4]} {RegMap_inst/debugReg1[5]} {RegMap_inst/debugReg1[6]} {RegMap_inst/debugReg1[7]} {RegMap_inst/debugReg1[8]} {RegMap_inst/debugReg1[9]} {RegMap_inst/debugReg1[10]} {RegMap_inst/debugReg1[11]} {RegMap_inst/debugReg1[12]} {RegMap_inst/debugReg1[13]} {RegMap_inst/debugReg1[14]} {RegMap_inst/debugReg1[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe5]
+set_property port_width 16 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {RegMap_inst/debugReg2[0]} {RegMap_inst/debugReg2[1]} {RegMap_inst/debugReg2[2]} {RegMap_inst/debugReg2[3]} {RegMap_inst/debugReg2[4]} {RegMap_inst/debugReg2[5]} {RegMap_inst/debugReg2[6]} {RegMap_inst/debugReg2[7]} {RegMap_inst/debugReg2[8]} {RegMap_inst/debugReg2[9]} {RegMap_inst/debugReg2[10]} {RegMap_inst/debugReg2[11]} {RegMap_inst/debugReg2[12]} {RegMap_inst/debugReg2[13]} {RegMap_inst/debugReg2[14]} {RegMap_inst/debugReg2[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list readEn_i_IBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 1 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list writeEn_i_IBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 1 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {RegMap_inst/LedReg[31]_i_1_n_0}]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets Clk123_i_IBUF_BUFG]