Проведён рефакторинг кода

.gitignore

@@ -30,4 +30,7 @@ _ReSharper*/
 [Tt]est[Rr]esult*
 .vs/
 #Nuget packages folder
-packages/
+packages/
+/sources_1/new/MMCM/ClkGen_tb.v
+/sources_1/new/MMCM/ClkGen_tb.v
+/sources_1/new/MMCM/ClkGen_tb.v

sources_1/new/AdcInit/AdcInitInterface.v

@@ -1,94 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// company: 
-// engineer: 
-// 
-// create date:    11:56:45 07/11/2019 
-// design name: 
-// module name:    adc_init_interface 
-// project name: 
-// target devices: 
-// tool versions: 
-// description: 
-//
-// dependencies: 
-//
-// revision: 
-// revision 0.01 - file created
-// additional comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-module	AdcInitInterface	
-#(
-	parameter	DelayValue		=	24000,
-	parameter	LengthWidth		=	2000,
-	parameter	DataWidth		=	24,
-	parameter	DataNum			=	26
-)
-(
-    input	wire	Clk_i,
-	input	wire	Rst_i,
-	
-	output	wire	AdcMosi_o,
-	output	wire	AdcClk_o,
-	output	wire	AdcCs_o,
-	output	wire	AdcRst_o
-);
-//================================================================================
-//  reg/wire
-//================================================================================	
-	wire			adcRstDone;
-	wire			adcFilteredRst;
-//================================================================================
-//  instantiations
-//================================================================================	
-
-ResetFilter #(
-    .STAGE_NUM      (4),
-    .RESET_FRONT    ("RISING")
-) 
-adcResetFilter 
-(
-    .clk_i          (Clk_i),
-    .rst_i          (Rst_i),
-    .perm_i         (1'b0),
-    .filtered_rst_o (adcFilteredRst)
-);
-
-AdcInitRst
-#(
-	.DELAY_VALUE    (DelayValue),	//задержка перед выдачей reset'а
-	.LENGTH_WIDTH   (LengthWidth)		//длительность сигнала reset
-) 
-AdcInitRst 
-(
-	.clk_i      (Clk_i),
-	.rst_i      (adcFilteredRst),
-	.signal_o   (AdcRst_o),
-	.done_o     (adcRstDone)
-);
-
-PeriphSpiInit 
-#(
-	.DATA_WIDTH             (DataWidth),
-	.DATA_NUM               (DataNum), 
-	.ROM_INIT_FILE          ("C:/Users/User/Desktop/4portCompact/S5443/S5443_M/S5443.srcs/sources_1/new/AdcInit/initFiles/AdcInitData.txt"),
-	.FILE_DATA_BASE         ("HEX"),
-	.SPI_CLK_DIVISOR_POWER  (4),
-	.SPI_CPOL               (0),
-	.SPI_CPHA               (0),
-	.SPI_DATA_DIRECTION     ("MSB"),
-	.SPI_EN_START_DELAY     ("YES")
-) 
-PeriphSpiInitController 
-(
-	.clk_i                  (Clk_i),
-	.rst_i                  (adcFilteredRst),
-	.enable_i               (adcRstDone),
-	.mosi_o                 (AdcMosi_o),
-	.sck_o                  (AdcClk_o),
-	.ss_o                   (AdcCs_o),
-	.done_o                 ()
-);
-
-endmodule

sources_1/new/AdcInit/AdcInitRst.v

@@ -1,130 +0,0 @@
-module AdcInitRst (
-    clk_i,
-    rst_i,
-
-    signal_o,
-    done_o
-);
-
-//================================================================================
-//
-//  FUNCTIONS
-//
-//================================================================================
-
-    function integer bit_num;
-        input integer value;
-        begin
-            bit_num = 0;
-            while (value > 0) begin
-                value   = value >> 1;
-                bit_num = bit_num + 1;
-            end
-        end
-    endfunction
-
-//================================================================================
-//
-//  PARAMETER/LOCALPARAM
-//
-//================================================================================
-
-    parameter   DELAY_VALUE     = 24000;
-    parameter   LENGTH_WIDTH    = 2;
-
-    localparam  DELAY_CNT_W = bit_num(DELAY_VALUE);
-
-//================================================================================
-//
-//  PORTS
-//
-//================================================================================
-
-    input           clk_i;
-    input           rst_i;
-    output  reg     signal_o;
-    output  reg     done_o;
-
-//================================================================================
-//
-//  STATE MACHINE STATES
-//
-//================================================================================
-
-    localparam  [1:0]   SM_RST_S    = 2'b00;
-    localparam  [1:0]   SM_DELAY_S  = 2'b01;
-    localparam  [1:0]   SM_SIGNAL_S = 2'b10;
-    localparam  [1:0]   SM_DONE_S   = 2'b11;
-
-//================================================================================
-//
-//  REG/WIRE
-//
-//================================================================================
-
-    reg     [1:0]               curr_state;
-    reg     [1:0]               next_state;
-
-    reg     [DELAY_CNT_W-1:0]   delay_cnt;
-    reg     [DELAY_CNT_W-1:0]   delay_cnt_next;
-    reg                         signal_next;
-    reg                         done_next;
-
-//================================================================================
-//
-//  CODING
-//
-//================================================================================
-
-always @(posedge clk_i or posedge rst_i) begin
-    if (rst_i) begin
-        curr_state  <= SM_RST_S;
-        delay_cnt   <= {DELAY_CNT_W{1'b0}};
-        signal_o    <= 1'b0;
-        done_o      <= 1'b0;
-    end else begin
-        curr_state  <= next_state;
-        delay_cnt   <= delay_cnt_next;
-        signal_o    <= signal_next;
-        done_o      <= done_next;
-    end
-end
-
-always @(*) begin
-    next_state      = SM_RST_S;
-    delay_cnt_next  = {DELAY_CNT_W{1'b0}};
-    signal_next     = 1'b0;
-    done_next       = 1'b0;
-    case(curr_state)
-        SM_RST_S    : begin
-            next_state  = SM_DELAY_S;
-        end
-
-        SM_DELAY_S  : begin
-            if (delay_cnt == DELAY_VALUE[DELAY_CNT_W-1:0]) begin
-                next_state      = SM_SIGNAL_S;
-                delay_cnt_next  = {DELAY_CNT_W{1'b0}};
-            end else begin
-                next_state      = SM_DELAY_S;
-                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
-            end
-        end
-
-        SM_SIGNAL_S : begin
-            signal_next = 1'b1;
-            if (delay_cnt == LENGTH_WIDTH[DELAY_CNT_W-1:0]) begin
-                next_state      = SM_DONE_S;
-            end else begin
-                next_state      = SM_SIGNAL_S;
-                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
-            end
-        end
-
-        SM_DONE_S   : begin
-            done_next   = 1'b1;
-            next_state  = SM_DONE_S;
-        end
-    endcase
-end
-
-endmodule

sources_1/new/AdcInit/PeriphSpiInit.v

@@ -1,217 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////////
-// Company                  :   NPK TAIR
-// Engineer                 :   Yuri Donskoy
-// 
-// Create Date (dd/mm/yyyy) :   16.05.2019
-// Design Name              :
-// Module Name              :
-// Project Name             :
-// Target Devices           :
-// Tool versions            :
-// Description              :
-//
-// Dependencies             : 
-// 
-// Revision                 :   0.01 - File Created
-// Additional Comments      :
-//        
-//////////////////////////////////////////////////////////////////////////////////
-
-module PeriphSpiInit (
-    clk_i,
-    rst_i,
-
-    enable_i,
-
-    mosi_o,
-    sck_o,
-    ss_o,
-
-    done_o
-);
-
-//================================================================================
-//
-//  FUNCTIONS
-//
-//================================================================================
-
-    function integer bit_num;
-        input integer value;
-        begin
-            bit_num = 0;
-            while (value > 0) begin
-                value   = value >> 1;
-                bit_num = bit_num + 1;
-            end
-        end
-    endfunction
-
-//================================================================================
-//
-//  PARAMETER/LOCALPARAM
-//
-//================================================================================
-
-    parameter   DATA_WIDTH              = 24;
-    parameter   DATA_NUM                = 26; 
-    parameter   ROM_INIT_FILE           = "./initFiles/AdcInitData.txt";
-    parameter   FILE_DATA_BASE          = "HEX";
-    parameter   SPI_CLK_DIVISOR_POWER   = 4;
-    parameter   SPI_CPOL                = 0;
-    parameter   SPI_CPHA                = 0;
-    parameter   SPI_DATA_DIRECTION      = "MSB";   //  MSB or LSB
-    parameter   SPI_EN_START_DELAY      = "NO";     //  YES or NO
-
-    localparam  ROM_ADDR_WIDTH          = bit_num(DATA_NUM);
-
-//================================================================================
-//
-//  STATE MACHINE STATES
-//
-//================================================================================
-
-    localparam  [7:0]   SM_RST_S        = 8'd0;
-    localparam  [7:0]   SM_SEND_DATA_S  = 8'd2;
-    localparam  [7:0]   SM_READ_DATA_S  = 8'd3;
-    localparam  [7:0]   SM_WAIT_SPI_S   = 8'd4;
-    localparam  [7:0]   SM_DONE_S       = 8'd5;
-
-//================================================================================
-//
-//  PORTS
-//
-//================================================================================
-
-    input       clk_i;
-    input       rst_i;
-    input       enable_i;
-    output      mosi_o;
-    output      sck_o;
-    output      ss_o;
-    output      done_o;
-
-//================================================================================
-//
-//  REG/WIRE
-//
-//================================================================================
-
-    reg     [ROM_ADDR_WIDTH-1:0]    rom_addr;
-    reg                             rom_valid;
-    wire    [DATA_WIDTH-1:0]        rom_data;
-    reg     [ROM_ADDR_WIDTH-1:0]    rom_addr_next;
-    wire                            spi_ready;
-    reg     [7:0]                   sm_curr_state;
-    reg     [7:0]                   sm_next_state;
-    wire                            data_end_flag;
-
-//================================================================================
-//
-//  INTEGER/GENVAR
-//
-//================================================================================
-
-
-
-//================================================================================
-//
-//  ASSIGN
-//
-//================================================================================
-
-    assign  data_end_flag   = (rom_addr == DATA_NUM);
-    assign  done_o          = sm_curr_state == SM_DONE_S;
-
-//================================================================================
-//
-//  CODING
-//
-//================================================================================
-
-SpiMaster #(
-    .CLK_DIVISOR_POWER  (SPI_CLK_DIVISOR_POWER),
-    .DATA_WIDTH         (DATA_WIDTH),
-    .CPOL               (SPI_CPOL),
-    .CPHA               (SPI_CPHA),
-    .DATA_DIRECTION     (SPI_DATA_DIRECTION),
-    .EN_START_DELAY     (SPI_EN_START_DELAY)
-) SpiMaster (
-    .clk_i      (clk_i),
-    .rst_i      (rst_i),
-
-    .data_i     (rom_data),
-    .valid_i    (rom_valid),
-    .ready_o    (spi_ready),
-    .mosi_o     (mosi_o),
-    .sck_o      (sck_o),
-    .ss_o       (ss_o)
-);
-
-SinglePortRom #(
-    .DATA_WIDTH     (DATA_WIDTH), 
-    .ADDR_WIDTH     (ROM_ADDR_WIDTH),
-    .INIT_FILE_NAME (ROM_INIT_FILE),
-    .DATA_BASE      (FILE_DATA_BASE)
-) Rom (
-    .clk_i  (clk_i),
-    .addr_i (rom_addr),
-    .q_o    (rom_data)
-    );
-
-always @(posedge clk_i or posedge rst_i) begin
-    if (rst_i) begin
-        sm_curr_state   <= 0;
-        rom_addr        <= SM_RST_S;
-    end else begin
-        sm_curr_state   <= sm_next_state;
-        rom_addr        <= rom_addr_next;
-    end
-end
-
-always @(*) begin
-    sm_next_state   = 0;
-    rom_addr_next   = rom_addr;
-    rom_valid       = 1'b0;
-    case(sm_curr_state)
-        SM_RST_S        :   begin
-            if (enable_i) begin
-                sm_next_state   = SM_SEND_DATA_S;
-            end else begin
-                sm_next_state   = SM_RST_S;
-            end
-        end
-
-        SM_SEND_DATA_S  :   begin
-            rom_valid       = 1'b1;
-            sm_next_state   = SM_SEND_DATA_S;
-            if (spi_ready) begin
-                rom_addr_next   = rom_addr + {{(ROM_ADDR_WIDTH-1){1'b0}}, 1'b1};
-                sm_next_state   = SM_READ_DATA_S;
-            end
-        end
-
-        SM_READ_DATA_S  :   begin
-            if (data_end_flag) begin
-                sm_next_state   = SM_WAIT_SPI_S;
-            end else begin
-                sm_next_state   = SM_SEND_DATA_S;
-            end
-        end
-
-        SM_WAIT_SPI_S   : begin
-            if (spi_ready) begin
-                sm_next_state   = SM_DONE_S;
-            end else begin
-                sm_next_state   = SM_WAIT_SPI_S;
-            end
-        end
-
-        SM_DONE_S       :   begin
-            sm_next_state   = SM_DONE_S;
-        end
-
-    endcase
-end
-
-endmodule

sources_1/new/AdcInit/Power2ClkDivider.v

@@ -1,90 +0,0 @@
-`timescale 1ns / 1ps
-module Power2ClkDivider (
-    clk_i,
-    rst_i,
-    valid_i,
-    signal_o,
-    rising_edge_o,
-    falling_edge_o
-);
-
-//================================================================================
-//
-//  PARAMETER/LOCALPARAM
-//
-//================================================================================
-
-    parameter   DIVISOR_POWER   = 2;
-
-//================================================================================
-//
-//  PORTS
-//
-//================================================================================
-
-    input           clk_i;
-    input           rst_i;
-    input           valid_i;
-    output  reg     signal_o;
-    output  reg     rising_edge_o;
-    output  reg     falling_edge_o;
-
-//================================================================================
-//
-//  REG/WIRE
-//
-//================================================================================
-
-    wire    clk_div_flag;
-
-//================================================================================
-//
-//  CODING
-//
-//================================================================================
-
-//initial begin
-//    if (DIVISOR_POWER < 1) begin
-//        $error("parameter DIVISOR_POWER of module power2_clk_divider must be greater then 0");
-//        $stop;
-//    end
-//end
-
-generate
-    if (DIVISOR_POWER < 2) begin
-        assign  clk_div_flag    = 1'b1;
-    end else begin
-        reg     [DIVISOR_POWER-2:0] clk_div_cnt;
-        always @(posedge clk_i or posedge rst_i) begin
-            if (rst_i) begin
-                clk_div_cnt <= {DIVISOR_POWER{1'b1}};
-            end else if (valid_i) begin
-                clk_div_cnt <= clk_div_cnt + 1;
-            end else begin
-                clk_div_cnt <= {DIVISOR_POWER{1'b1}};
-            end
-        end
-
-        assign  clk_div_flag    = &clk_div_cnt;
-    end
-endgenerate
-
-always @(posedge clk_i or posedge rst_i) begin
-    if (rst_i) begin
-        signal_o        <= 1'b0;
-        rising_edge_o   <= 1'b0;
-        falling_edge_o  <= 1'b0;
-    end else if (valid_i) begin
-        if (clk_div_flag) begin
-            signal_o    <= ~signal_o;
-        end
-        rising_edge_o   <= ~signal_o & clk_div_flag;
-        falling_edge_o  <= signal_o & clk_div_flag;
-    end else begin
-        signal_o        <= 1'b0;
-        rising_edge_o   <= 1'b0;
-        falling_edge_o  <= 1'b0;
-    end
-end
-
-endmodule

sources_1/new/AdcInit/ResetFilter.v

@@ -1,60 +0,0 @@
-module ResetFilter (
-    clk_i,
-    rst_i,
-    perm_i,
-    filtered_rst_o
-);
-
-    parameter   STAGE_NUM   = 1;
-    parameter   RESET_FRONT = "RISING"; //  FALLING
-
-    input   clk_i;
-    input   rst_i;
-    input   perm_i;
-    output  filtered_rst_o;
-
-    reg [STAGE_NUM-1:0] rst_filter;
-
-    assign  filtered_rst_o  = rst_filter[STAGE_NUM-1];
-
-generate
-    if (RESET_FRONT == "RISING") begin
-        if (STAGE_NUM < 2) begin
-            always @(posedge clk_i or posedge rst_i) begin
-                if (rst_i) begin
-                    rst_filter  <= 1'b1;
-                end else begin
-                    rst_filter  <= perm_i;
-                end
-            end
-        end else begin
-            always @(posedge clk_i or posedge rst_i) begin
-                if (rst_i) begin
-                    rst_filter  <= {STAGE_NUM{1'b1}};
-                end else begin
-                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
-                end
-            end        
-        end
-    end else begin
-        if (STAGE_NUM < 2) begin
-            always @(posedge clk_i or negedge rst_i) begin
-                if (!rst_i) begin
-                    rst_filter  <= 1'b1;
-                end else begin
-                    rst_filter  <= perm_i;
-                end
-            end
-        end else begin
-            always @(posedge clk_i or negedge rst_i) begin
-                if (!rst_i) begin
-                    rst_filter  <= {STAGE_NUM{1'b1}};
-                end else begin
-                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
-                end
-            end        
-        end    
-    end
-endgenerate
-
-endmodule

sources_1/new/AdcInit/SinglePortRom.v

@@ -1,30 +0,0 @@
-module SinglePortRom (
-    clk_i, 
-    addr_i,
-    q_o
-);
-
-    parameter   DATA_WIDTH      = 16; 
-    parameter   ADDR_WIDTH      = 5;
-    parameter   INIT_FILE_NAME  = "./initFiles/AdcInitData.txt";
-    parameter   DATA_BASE       = "HEX";    //  HEX or BIN
-
-    input                                   clk_i;
-    input           [(ADDR_WIDTH-1):0]      addr_i;
-    output  reg     [(DATA_WIDTH-1):0]      q_o;
-
-    reg     [DATA_WIDTH-1:0]    rom[2**ADDR_WIDTH-1:0];
-
-initial begin
-    if (DATA_BASE == "HEX") begin
-        $readmemh(INIT_FILE_NAME, rom);
-    end else begin
-        $readmemb(INIT_FILE_NAME, rom);
-    end
-end
-
-always @ (posedge clk_i) begin
-    q_o <=  rom[addr_i];
-end
-
-endmodule

sources_1/new/AdcInit/SpiMaster.v

@@ -1,273 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////////
-// Company                  :   NPK TAIR
-// Engineer                 :   Yuri Donskoy
-// 
-// Create Date (dd/mm/yyyy) :
-// Design Name              :
-// Module Name              :
-// Project Name             :
-// Target Devices           :
-// Tool versions            :
-// Description              :
-//
-// Dependencies             : 
-// 
-// Revision                 :   1.0 - It only send data (no miso port)
-// Additional Comments      :   MISO port need to be add. What about multiple slave select?
-//        
-//////////////////////////////////////////////////////////////////////////////////
-
-module SpiMaster (
-    clk_i,
-    rst_i,
-
-    data_i,
-    valid_i,
-    ready_o,
-
-    mosi_o,
-    sck_o,
-    ss_o
-);
-
-//================================================================================
-//
-//  FUNCTIONS
-//
-//================================================================================
-
-    function integer bit_num;
-        input integer value;
-        begin
-            bit_num = 0;
-            while (value > 0) begin
-                value   = value >> 1;
-                bit_num = bit_num + 1;
-            end
-        end
-    endfunction
-
-//================================================================================
-//
-//  PARAMETER/LOCALPARAM
-//
-//================================================================================
-
-    parameter   CLK_DIVISOR_POWER   = 4; //WAS 2 !! DONT FORGET TO CHANGE!
-    parameter   DATA_WIDTH          = 24;
-    parameter   CPOL                = 0;
-    parameter   CPHA                = 0;
-    parameter   DATA_DIRECTION      = "MSBT";   //  MSB or LSB
-    parameter   EN_START_DELAY      = "NO";     //  YES or NO
-
-    localparam  BIT_CNT_W           = bit_num(DATA_WIDTH);
-
-//================================================================================
-//
-//  STATE MACHINE STATES
-//
-//================================================================================
-
-    localparam  SM_IDLE_S   = 2'b00;
-    localparam  SM_START_S  = 2'b01;
-    localparam  SM_DATA_S   = 2'b10;
-    localparam  SM_STOP_S   = 2'b11;
-
-//================================================================================
-//
-//  PORTS
-//
-//================================================================================
-
-    input                               clk_i;
-    input                               rst_i;
-
-    input           [DATA_WIDTH-1:0]    data_i;
-    input                               valid_i;
-    output                              ready_o;
-
-    output  reg                         mosi_o;
-    output  reg                         sck_o;
-    output  reg                         ss_o;
-
-//================================================================================
-//
-//  REG/WIRE
-//
-//================================================================================
-
-    reg     [1:0]               sm_curr_state;
-    reg     [1:0]               sm_next_state;
-
-    reg                         sm_clk_div_en;
-
-    //  Clock divider outputs
-
-    wire                        clk_divider_redge;
-    wire                        clk_divider_fedge;
-
-    //  Bits counter
-
-    reg     [BIT_CNT_W-1:0]     bit_cnt_r;
-    reg     [BIT_CNT_W-1:0]     bit_cnt_next;
-
-    //  Data buffers
-
-    reg     [DATA_WIDTH-1:0]    tx_buffer_r;
-    reg     [DATA_WIDTH-1:0]    tx_buffer_next;
-    wire    [DATA_WIDTH-1:0]    tx_buffer_shifted;
-    wire                        tx_curr_bit;
-
-    //  Output data next
-    reg                         mosi_next;
-    reg                         sck_next;
-    reg                         ss_next;
-
-    //  Edges
-
-    wire                        mosi_shift_edge;
-
-    wire                        ss_start_edge;
-    wire                        ss_stop_edge;
-
-    wire                        sck_leading_edge;
-    wire                        sck_trailing_edge;
-
-//================================================================================
-//
-//  INTEGER/GENVAR
-//
-//================================================================================
-
-
-
-//================================================================================
-//
-//  ASSIGN
-//
-//================================================================================
-
-    assign  mosi_shift_edge     = (CPHA[0] == 1'b1) && (EN_START_DELAY != "YES") || (CPHA[0] == 1'b0) && (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
-    assign  ss_start_edge       = (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
-    assign  ss_stop_edge        = (EN_START_DELAY == "YES") ? clk_divider_redge : clk_divider_fedge;
-    assign  sck_leading_edge    = (EN_START_DELAY == "YES") ? clk_divider_redge : clk_divider_fedge;
-    assign  sck_trailing_edge   = (EN_START_DELAY == "YES") ? clk_divider_fedge : clk_divider_redge;
-    assign  tx_buffer_shifted   = (DATA_DIRECTION == "MSB") ? tx_buffer_r << 1 : tx_buffer_r >> 1;
-    assign  tx_curr_bit         = (DATA_DIRECTION == "MSB") ? tx_buffer_r[DATA_WIDTH-1] : tx_buffer_r[0];
-
-    assign  ready_o             = sm_curr_state == SM_IDLE_S;
-
-//================================================================================
-//
-//  CODING
-//
-//================================================================================
-
-//  Sequential logic
-
-always @(posedge clk_i or posedge rst_i) begin
-    if (rst_i) begin
-        sm_curr_state   <= 0;
-        tx_buffer_r     <= {DATA_WIDTH{1'b0}};
-        bit_cnt_r       <= {BIT_CNT_W{1'b0}};
-        mosi_o          <= 1'b0;
-        sck_o           <= CPOL[0];
-        ss_o            <= 1'b1;
-    end else begin
-        sm_curr_state   <= sm_next_state;
-        tx_buffer_r     <= tx_buffer_next;
-        bit_cnt_r       <= bit_cnt_next;
-        mosi_o          <= mosi_next;
-        sck_o           <= sck_next;
-        ss_o            <= ss_next;
-    end
-end
-
-//  Combinational logic
-
-always @(*) begin
-    sm_next_state   = SM_IDLE_S;
-    tx_buffer_next  = tx_buffer_r;
-    mosi_next       = mosi_o;
-    sck_next        = sck_o;
-    ss_next         = ss_o;
-    sm_clk_div_en   = 1'b1;
-    bit_cnt_next    = bit_cnt_r;
-
-    case(sm_curr_state)
-
-        SM_IDLE_S   : begin
-            if (valid_i) begin
-                sm_next_state   = SM_START_S;
-            end else begin
-                sm_next_state   = SM_IDLE_S;
-            end
-            tx_buffer_next  = data_i;
-            sm_clk_div_en   = 1'b0;
-            bit_cnt_next    = {BIT_CNT_W{1'b0}};
-        end
-
-        SM_START_S  : begin
-            if (ss_start_edge) begin
-                sm_next_state   = SM_DATA_S;
-                ss_next         = 1'b0;
-                if (!CPHA[0]) begin
-                    mosi_next       = tx_curr_bit;
-                    tx_buffer_next  = tx_buffer_shifted;
-                    bit_cnt_next    = bit_cnt_r + {{(BIT_CNT_W-1){1'b0}}, 1'b1};
-                end
-            end else begin
-                sm_next_state   = SM_START_S;
-            end
-        end
-
-        SM_DATA_S   : begin
-            sm_next_state   = SM_DATA_S;
-            if (sck_leading_edge) begin
-                sck_next    = ~CPOL[0];
-            end
-
-            if  (sck_trailing_edge) begin
-                sck_next    = CPOL[0];
-                if (bit_cnt_r == DATA_WIDTH[BIT_CNT_W-1:0]) begin
-                    sm_next_state   = SM_STOP_S;
-                end
-            end
-
-            if (mosi_shift_edge) begin
-                mosi_next       = tx_curr_bit;
-                tx_buffer_next  = tx_buffer_shifted;
-                bit_cnt_next    = bit_cnt_r + {{(BIT_CNT_W-1){1'b0}}, 1'b1};
-            end
-
-        end
-
-        SM_STOP_S   : begin
-            if (ss_stop_edge) begin
-                if (CPHA[0]) begin
-                    mosi_next   = tx_curr_bit;
-                end
-                sm_next_state   = SM_IDLE_S;
-                ss_next         = 1'b1;
-            end else begin
-                sm_next_state   = SM_STOP_S;
-            end
-        end
-
-    endcase
-end
-
-//  Clock divider
-
-Power2ClkDivider #(
-    .DIVISOR_POWER      (CLK_DIVISOR_POWER)
-) ClkDividerInst (
-    .clk_i              (clk_i),
-    .rst_i              (rst_i),
-    .valid_i            (sm_clk_div_en),
-    .signal_o           (),
-    .rising_edge_o      (clk_divider_redge),
-    .falling_edge_o     (clk_divider_fedge)
-);
-
-endmodule

sources_1/new/AdcInit/initFiles/AdcInitData.txt

@@ -1,26 +0,0 @@
-400601
-40013C
-400300
-400400
-400533
-400602 
-400700
-400900
-400A02
-400B20
-400ED1
-400FD4
-401300
-401500
-402500
-402700
-441D00
-442202
-443428
-443908
-451D00
-452202
-453428
-453908
-460800
-470A00

sources_1/new/DataFifo/DataFifoWrapper.v

@@ -54,9 +54,7 @@ module DataFifoWrapper
 	assign DataFromRxFifo_o = dataFromRxFifo;
 
 	assign TxFifoCtrlReg_o = {16'h0, txFifoUpDnCnt,5'h0,emptyFlagTx,fullFlagTx, FifoTxRst_i};
-	// assign TxFifoCtrlReg_o = {FifoTxRst_i, fullFlagTx, emptyFlagTx, 5'h0, txFifoUpDnCnt, 16'h0};
 	assign RxFifoCtrlReg_o = {16'h0, rxFifoUpDnCnt,5'h0,emptyFlagRx,fullFlagRx, FifoRxRst_i};
-	// assign RxFifoCtrlReg_o = {FifoRxRst_i, fullFlagRx, emptyFlagRx, 5'h0, rxFifoUpDnCnt, 16'h0};
 //================================================================================
 //	LOCALPARAMS
 //================================================================================

sources_1/new/DataFifo/FifoCtrl.v

@@ -45,10 +45,10 @@ module FifoCtrl #(
 );
 
 
-reg FifoTxWriteEn;
-reg FifoTxReadEn;
-reg FifoRxWriteEn;
-reg FifoRxReadEn;
+reg fifoTxWriteEn;
+reg fifoTxReadEn;
+reg fifoRxWriteEn;
+reg fifoRxReadEn;
 
 (* dont_touch = "true" *)reg [7:0] txFifoWrPtr;
 (* dont_touch = "true" *)reg [7:0] txFifoRdPtr;
@@ -76,10 +76,10 @@ wire	requestToFifo	=	(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo
 // //================================================================================
 // //	ASSIGNMENTS
 
-assign FifoTxWriteEn_o = FifoTxWriteEn;
-assign FifoTxReadEn_o = FifoTxReadEn;
-assign FifoRxWriteEn_o = FifoRxWriteEn;
-assign FifoRxReadEn_o = FifoRxReadEn;
+assign FifoTxWriteEn_o = fifoTxWriteEn;
+assign FifoTxReadEn_o = fifoTxReadEn;
+assign FifoRxWriteEn_o = fifoRxWriteEn;
+assign FifoRxReadEn_o = fifoRxReadEn;
 
 
 assign RxFifoUpDnCnt_o = rxFifoUpDnCnt;
@@ -107,40 +107,40 @@ end
 
 always @(posedge FifoTxWrClock_i) begin 
     if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
-        FifoTxWriteEn <= 1'b1;
+        fifoTxWriteEn <= 1'b1;
     end
     else begin 
-        FifoTxWriteEn <= 1'b0;
+        fifoTxWriteEn <= 1'b0;
     end
 end
 
 
 always @(posedge FifoTxRdClock_i ) begin 
     if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
-        FifoTxReadEn <= 1'b1;
+        fifoTxReadEn <= 1'b1;
     end
     else begin 
-        FifoTxReadEn <= 1'b0;
+        fifoTxReadEn <= 1'b0;
     end
 end
 
 
 always @(posedge FifoRxWrClock_i) begin 
     if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
-        FifoRxWriteEn <= 1'b1;
+        fifoRxWriteEn <= 1'b1;
     end
     else begin 
-        FifoRxWriteEn <= 1'b0;
+        fifoRxWriteEn <= 1'b0;
     end
 end
 
 
 always @(posedge FifoRxRdClock_i) begin 
     if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo && readEnCnt < 1 ) begin 
-        FifoRxReadEn <= 1'b1;
+        fifoRxReadEn <= 1'b1;
     end
     else begin 
-        FifoRxReadEn <= 1'b0;
+        fifoRxReadEn <= 1'b0;
     end
 end
 
@@ -150,7 +150,7 @@ always @(posedge FifoTxWrClock_i ) begin
         txFifoWrPtr <= 8'h0;
     end
     else begin 
-        if (FifoTxWriteEn  ) begin 
+        if (fifoTxWriteEn  ) begin 
             txFifoWrPtr <= txFifoWrPtr + 1'b1;
         end
     end
@@ -161,7 +161,7 @@ always @(posedge FifoTxRdClock_i ) begin
         txFifoRdPtr <= 8'h0;
     end
     else begin 
-        if (FifoTxReadEn ) begin 
+        if (fifoTxReadEn ) begin 
             txFifoRdPtr <= txFifoRdPtr + 1'b1;
         end
     end
@@ -173,7 +173,7 @@ always @(posedge FifoRxWrClock_i) begin
         rxFifoWrPtr <= 8'h0;
     end
     else begin
-        if (FifoRxWriteEn ) begin 
+        if (fifoRxWriteEn ) begin 
             rxFifoWrPtr <= rxFifoWrPtr + 1'b1;
         end
     end
@@ -184,7 +184,7 @@ always @(posedge FifoRxRdClock_i) begin
         rxFifoRdPtr <= 8'h0;
     end
     else begin 
-        if (FifoRxReadEn ) begin 
+        if (fifoRxReadEn ) begin 
             rxFifoRdPtr <= rxFifoRdPtr + 1'b1;
         end
     end

sources_1/new/MMCM/.idea/.gitignore

@@ -1,8 +0,0 @@
-# Default ignored files
-/shelf/
-/workspace.xml
-# Editor-based HTTP Client requests
-/httpRequests/
-# Datasource local storage ignored files
-/dataSources/
-/dataSources.local.xml

sources_1/new/MMCM/.idea/MMCM.iml

@@ -1,6 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<module classpath="CMake" type="CPP_MODULE" version="4">
-  <component name="SonarLintModuleSettings">
-    <option name="uniqueId" value="2a230afb-35f1-403e-a433-548af2d8ebe0" />
-  </component>
-</module>

sources_1/new/MMCM/.idea/misc.xml

@@ -1,4 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<project version="4">
-  <component name="CMakeWorkspace" PROJECT_DIR="$PROJECT_DIR$" />
-</project>

sources_1/new/MMCM/.idea/modules.xml

@@ -1,8 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<project version="4">
-  <component name="ProjectModuleManager">
-    <modules>
-      <module fileurl="file://$PROJECT_DIR$/.idea/MMCM.iml" filepath="$PROJECT_DIR$/.idea/MMCM.iml" />
-    </modules>
-  </component>
-</project>

sources_1/new/MMCM/.idea/sonarlint/issuestore/index.pb

@@ -1,5 +0,0 @@
-
->
-CMakeLists.txt,9\a\9a2aa4db38d3115ed60da621e012c0efc0172aae
-=
-
MmcmWrapper.v,d\a\da020c612d0c4048d719bfbe42bb8803a425696a

sources_1/new/MMCM/.idea/sonarlint/securityhotspotstore/index.pb

@@ -1,5 +0,0 @@
-
->
-CMakeLists.txt,9\a\9a2aa4db38d3115ed60da621e012c0efc0172aae
-=
-
MmcmWrapper.v,d\a\da020c612d0c4048d719bfbe42bb8803a425696a

sources_1/new/MMCM/.idea/vcs.xml

@@ -1,6 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<project version="4">
-  <component name="VcsDirectoryMappings">
-    <mapping directory="$PROJECT_DIR$/../../.." vcs="Git" />
-  </component>
-</project>

sources_1/new/MMCM/CMakeLists.txt

@@ -1,9 +0,0 @@
-cmake_minimum_required(VERSION 3.25)
-project(MMCM C)
-
-set(CMAKE_C_STANDARD 11)
-
-include_directories(.)
-
-add_executable(MMCM
-        mmcme2_drp_func.h)

sources_1/new/MMCM/ClkCh.v

@@ -4,35 +4,50 @@ module ClkCh (
     input clkOutMMCM,
     input clkMan,
 
-    output reg SpiClk_o
+    output SpiClk_o
 
 
 
 );
 
 
+reg spiClkReg;
+
+wire spiClk;
+
+assign spiClk = spiClkReg;
+
+
 
 always @(*) begin 
     if (Rst_i) begin 
-        SpiClk_o = 0;
+        spiClkReg = 0;
     end
     else begin 
         if (clkCh) begin 
-            SpiClk_o = clkOutMMCM;
+            spiClkReg = clkOutMMCM;
         end
         else begin 
-            SpiClk_o = clkMan;
+            spiClkReg = clkMan;
         end
     end
 end
 
 
 
+BUFG BUFG_inst (
+   .O(SpiClk_o), // 1-bit output: Clock output
+   .I(spiClk)  // 1-bit input: Clock input
+);
+
+
+
+
 
 
 
 
+endmodule
 
 
 
-endmodule

sources_1/new/MMCM/ClkGen_tb.v

@@ -1,3 +1,4 @@
+`timescale 1ns / 1ps
 module ClkGen_tb();
 
 
@@ -15,16 +16,18 @@ reg [3:0] clkDiv_i;
 
 
 
-always #(12.5/2) Clk_i = ~Clk_i;
+always #(1.667/2) Clk_i = ~Clk_i;
 
 
 
 
-ClkGen ClkGen_inst (
+ClkGenGowin ClkGen_inst (
     .Clk_i(Clk_i), 
     .Rst_i(Rst_i), 
-    .ClkDiv_i(clkDiv_i), 
-    .Clk_o()
+    .Clk75_o(),
+    .Clk40_o(),
+    .Clk30_o(),
+    .Clk5_o()
 );
 
 

sources_1/new/MMCM/Division.c

@@ -1,37 +0,0 @@
-#include <stdio.h>
-#include <math.h>
-
-int main() {
-    double dividend, divisor;
-    double quotient, fractional_part;
-    int whole_part, count_0125;
-
-    printf("Введите делимое: ");
-    scanf("%lf", &dividend);
-    printf("Введите делитель: ");
-    scanf("%lf", &divisor);
-
-    if (divisor == 0) {
-        printf("Ошибка: Деление на ноль!\n");
-        return 1;
-    }
-
-    
-    quotient = dividend / divisor;
-    whole_part = (int)quotient; // целая часть
-    fractional_part = quotient - whole_part; // дробная часть
-
-   
-    double count_0125_exact = fractional_part * 8;
-    if (count_0125_exact - floor(count_0125_exact) < 0.5) {
-        count_0125 = (int)floor(count_0125_exact);
-    } else {
-        count_0125 = (int)ceil(count_0125_exact);
-    }
-
-    printf("Целая часть: %d\n", whole_part);
-    printf("Дробная часть: %lf\n", fractional_part);
-    printf("Округленное количество единиц 0.125 в дробной части: %d\n", count_0125);
-
-    return 0;
-}

sources_1/new/MMCM/MmcmWrapper.v

@@ -152,7 +152,7 @@ endgenerate
     .clk_out3(clk2out),     // 70 MHz
     .clk_out4(clk3out),     // 60MHz
     .clk_out5(clk4out),     // 50MHz
-   //  .clk_out6(clk5out),     // 40MHz
+    .clk_out6(clk5out),     // 40MHz
     .clk_out7(clk6out),     // 30MHz 
     // Status and control signals
     .reset(Rst_i), // input reset

sources_1/new/MMCM/cmake-build-debug/CMakeCache.txt

@@ -1,363 +0,0 @@
-# This is the CMakeCache file.
-# For build in directory: c:/Projects/S5443_3/S5443_3.srcs/sources_1/new/MMCM/cmake-build-debug
-# It was generated by CMake: C:/Program Files/JetBrains/CLion 2023.1.4/bin/cmake/win/x64/bin/cmake.exe
-# You can edit this file to change values found and used by cmake.
-# If you do not want to change any of the values, simply exit the editor.
-# If you do want to change a value, simply edit, save, and exit the editor.
-# The syntax for the file is as follows:
-# KEY:TYPE=VALUE
-# KEY is the name of a variable in the cache.
-# TYPE is a hint to GUIs for the type of VALUE, DO NOT EDIT TYPE!.
-# VALUE is the current value for the KEY.
-
-########################
-# EXTERNAL cache entries
-########################
-
-//Path to a program.
-CMAKE_ADDR2LINE:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/addr2line.exe
-
-//Path to a program.
-CMAKE_AR:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/ar.exe
-
-//Choose the type of build, options are: None Debug Release RelWithDebInfo
-// MinSizeRel ...
-CMAKE_BUILD_TYPE:STRING=Debug
-
-//Enable colored diagnostics throughout.
-CMAKE_COLOR_DIAGNOSTICS:BOOL=ON
-
-//C compiler
-CMAKE_C_COMPILER:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/gcc.exe
-
-//A wrapper around 'ar' adding the appropriate '--plugin' option
-// for the GCC compiler
-CMAKE_C_COMPILER_AR:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/gcc-ar.exe
-
-//A wrapper around 'ranlib' adding the appropriate '--plugin' option
-// for the GCC compiler
-CMAKE_C_COMPILER_RANLIB:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/gcc-ranlib.exe
-
-//Flags used by the C compiler during all build types.
-CMAKE_C_FLAGS:STRING=
-
-//Flags used by the C compiler during DEBUG builds.
-CMAKE_C_FLAGS_DEBUG:STRING=-g
-
-//Flags used by the C compiler during MINSIZEREL builds.
-CMAKE_C_FLAGS_MINSIZEREL:STRING=-Os -DNDEBUG
-
-//Flags used by the C compiler during RELEASE builds.
-CMAKE_C_FLAGS_RELEASE:STRING=-O3 -DNDEBUG
-
-//Flags used by the C compiler during RELWITHDEBINFO builds.
-CMAKE_C_FLAGS_RELWITHDEBINFO:STRING=-O2 -g -DNDEBUG
-
-//Libraries linked by default with all C applications.
-CMAKE_C_STANDARD_LIBRARIES:STRING=-lkernel32 -luser32 -lgdi32 -lwinspool -lshell32 -lole32 -loleaut32 -luuid -lcomdlg32 -ladvapi32
-
-//Path to a program.
-CMAKE_DLLTOOL:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/dlltool.exe
-
-//Flags used by the linker during all build types.
-CMAKE_EXE_LINKER_FLAGS:STRING=
-
-//Flags used by the linker during DEBUG builds.
-CMAKE_EXE_LINKER_FLAGS_DEBUG:STRING=
-
-//Flags used by the linker during MINSIZEREL builds.
-CMAKE_EXE_LINKER_FLAGS_MINSIZEREL:STRING=
-
-//Flags used by the linker during RELEASE builds.
-CMAKE_EXE_LINKER_FLAGS_RELEASE:STRING=
-
-//Flags used by the linker during RELWITHDEBINFO builds.
-CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO:STRING=
-
-//Enable/Disable output of compile commands during generation.
-CMAKE_EXPORT_COMPILE_COMMANDS:BOOL=
-
-//Value Computed by CMake.
-CMAKE_FIND_PACKAGE_REDIRECTS_DIR:STATIC=C:/Projects/S5443_3/S5443_3.srcs/sources_1/new/MMCM/cmake-build-debug/CMakeFiles/pkgRedirects
-
-//Convert GNU import libraries to MS format (requires Visual Studio)
-CMAKE_GNUtoMS:BOOL=OFF
-
-//Install path prefix, prepended onto install directories.
-CMAKE_INSTALL_PREFIX:PATH=C:/Program Files (x86)/MMCM
-
-//Path to a program.
-CMAKE_LINKER:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/ld.exe
-
-//make program
-CMAKE_MAKE_PROGRAM:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/ninja/win/x64/ninja.exe
-
-//Flags used by the linker during the creation of modules during
-// all build types.
-CMAKE_MODULE_LINKER_FLAGS:STRING=
-
-//Flags used by the linker during the creation of modules during
-// DEBUG builds.
-CMAKE_MODULE_LINKER_FLAGS_DEBUG:STRING=
-
-//Flags used by the linker during the creation of modules during
-// MINSIZEREL builds.
-CMAKE_MODULE_LINKER_FLAGS_MINSIZEREL:STRING=
-
-//Flags used by the linker during the creation of modules during
-// RELEASE builds.
-CMAKE_MODULE_LINKER_FLAGS_RELEASE:STRING=
-
-//Flags used by the linker during the creation of modules during
-// RELWITHDEBINFO builds.
-CMAKE_MODULE_LINKER_FLAGS_RELWITHDEBINFO:STRING=
-
-//Path to a program.
-CMAKE_NM:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/nm.exe
-
-//Path to a program.
-CMAKE_OBJCOPY:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/objcopy.exe
-
-//Path to a program.
-CMAKE_OBJDUMP:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/objdump.exe
-
-//Value Computed by CMake
-CMAKE_PROJECT_DESCRIPTION:STATIC=
-
-//Value Computed by CMake
-CMAKE_PROJECT_HOMEPAGE_URL:STATIC=
-
-//Value Computed by CMake
-CMAKE_PROJECT_NAME:STATIC=MMCM
-
-//Path to a program.
-CMAKE_RANLIB:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/ranlib.exe
-
-//RC compiler
-CMAKE_RC_COMPILER:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/windres.exe
-
-//Flags for Windows Resource Compiler during all build types.
-CMAKE_RC_FLAGS:STRING=
-
-//Flags for Windows Resource Compiler during DEBUG builds.
-CMAKE_RC_FLAGS_DEBUG:STRING=
-
-//Flags for Windows Resource Compiler during MINSIZEREL builds.
-CMAKE_RC_FLAGS_MINSIZEREL:STRING=
-
-//Flags for Windows Resource Compiler during RELEASE builds.
-CMAKE_RC_FLAGS_RELEASE:STRING=
-
-//Flags for Windows Resource Compiler during RELWITHDEBINFO builds.
-CMAKE_RC_FLAGS_RELWITHDEBINFO:STRING=
-
-//Path to a program.
-CMAKE_READELF:FILEPATH=C:/Program Files/JetBrains/CLion 2023.1.4/bin/mingw/bin/readelf.exe
-
-//Flags used by the linker during the creation of shared libraries
-// during all build types.
-CMAKE_SHARED_LINKER_FLAGS:STRING=
-
-//Flags used by the linker during the creation of shared libraries
-// during DEBUG builds.
-CMAKE_SHARED_LINKER_FLAGS_DEBUG:STRING=
-
-//Flags used by the linker during the creation of shared libraries
-// during MINSIZEREL builds.
-CMAKE_SHARED_LINKER_FLAGS_MINSIZEREL:STRING=
-
-//Flags used by the linker during the creation of shared libraries
-// during RELEASE builds.
-CMAKE_SHARED_LINKER_FLAGS_RELEASE:STRING=
-
-//Flags used by the linker during the creation of shared libraries
-// during RELWITHDEBINFO builds.
-CMAKE_SHARED_LINKER_FLAGS_RELWITHDEBINFO:STRING=
-
-//If set, runtime paths are not added when installing shared libraries,
-// but are added when building.
-CMAKE_SKIP_INSTALL_RPATH:BOOL=NO
-
-//If set, runtime paths are not added when using shared libraries.
-CMAKE_SKIP_RPATH:BOOL=NO
-
-//Flags used by the linker during the creation of static libraries
-// during all build types.
-CMAKE_STATIC_LINKER_FLAGS:STRING=
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-//Flags used by the linker during the creation of static libraries
-// during DEBUG builds.
-CMAKE_STATIC_LINKER_FLAGS_DEBUG:STRING=
-
-//Flags used by the linker during the creation of static libraries
-// during MINSIZEREL builds.
-CMAKE_STATIC_LINKER_FLAGS_MINSIZEREL:STRING=
-
-//Flags used by the linker during the creation of static libraries
-// during RELEASE builds.
-CMAKE_STATIC_LINKER_FLAGS_RELEASE:STRING=
-
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-  /* __IBMC__ = VRP */
-# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
-# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
-# define COMPILER_VERSION_PATCH DEC(__IBMC__    % 10)
-
-#elif defined(__open_xl__) && defined(__clang__)
-# define COMPILER_ID "IBMClang"
-# define COMPILER_VERSION_MAJOR DEC(__open_xl_version__)
-# define COMPILER_VERSION_MINOR DEC(__open_xl_release__)
-# define COMPILER_VERSION_PATCH DEC(__open_xl_modification__)
-# define COMPILER_VERSION_TWEAK DEC(__open_xl_ptf_fix_level__)
-
-
-#elif defined(__ibmxl__) && defined(__clang__)
-# define COMPILER_ID "XLClang"
-# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__)
-# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__)
-# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__)
-# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__)
-
-
-#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ >= 800
-# define COMPILER_ID "XL"
-  /* __IBMC__ = VRP */
-# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
-# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
-# define COMPILER_VERSION_PATCH DEC(__IBMC__    % 10)
-
-#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ < 800
-# define COMPILER_ID "VisualAge"
-  /* __IBMC__ = VRP */
-# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
-# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
-# define COMPILER_VERSION_PATCH DEC(__IBMC__    % 10)
-
-#elif defined(__NVCOMPILER)
-# define COMPILER_ID "NVHPC"
-# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__)
-# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__)
-# if defined(__NVCOMPILER_PATCHLEVEL__)
-#  define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__)
-# endif
-
-#elif defined(__PGI)
-# define COMPILER_ID "PGI"
-# define COMPILER_VERSION_MAJOR DEC(__PGIC__)
-# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__)
-# if defined(__PGIC_PATCHLEVEL__)
-#  define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__)
-# endif
-
-#elif defined(_CRAYC)
-# define COMPILER_ID "Cray"
-# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR)
-# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR)
-
-#elif defined(__TI_COMPILER_VERSION__)
-# define COMPILER_ID "TI"
-  /* __TI_COMPILER_VERSION__ = VVVRRRPPP */
-# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000)
-# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000   % 1000)
-# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__        % 1000)
-
-#elif defined(__CLANG_FUJITSU)
-# define COMPILER_ID "FujitsuClang"
-# define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
-# define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
-# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
-# define COMPILER_VERSION_INTERNAL_STR __clang_version__
-
-
-#elif defined(__FUJITSU)
-# define COMPILER_ID "Fujitsu"
-# if defined(__FCC_version__)
-#   define COMPILER_VERSION __FCC_version__
-# elif defined(__FCC_major__)
-#   define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
-#   define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
-#   define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
-# endif
-# if defined(__fcc_version)
-#   define COMPILER_VERSION_INTERNAL DEC(__fcc_version)
-# elif defined(__FCC_VERSION)
-#   define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION)
-# endif
-
-
-#elif defined(__ghs__)
-# define COMPILER_ID "GHS"
-/* __GHS_VERSION_NUMBER = VVVVRP */
-# ifdef __GHS_VERSION_NUMBER
-# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100)
-# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10)
-# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER      % 10)
-# endif
-
-#elif defined(__TASKING__)
-# define COMPILER_ID "Tasking"
-  # define COMPILER_VERSION_MAJOR DEC(__VERSION__/1000)
-  # define COMPILER_VERSION_MINOR DEC(__VERSION__ % 100)
-# define COMPILER_VERSION_INTERNAL DEC(__VERSION__)
-
-#elif defined(__TINYC__)
-# define COMPILER_ID "TinyCC"
-
-#elif defined(__BCC__)
-# define COMPILER_ID "Bruce"
-
-#elif defined(__SCO_VERSION__)
-# define COMPILER_ID "SCO"
-
-#elif defined(__ARMCC_VERSION) && !defined(__clang__)
-# define COMPILER_ID "ARMCC"
-#if __ARMCC_VERSION >= 1000000
-  /* __ARMCC_VERSION = VRRPPPP */
-  # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000)
-  # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100)
-  # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION     % 10000)
-#else
-  /* __ARMCC_VERSION = VRPPPP */
-  # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000)
-  # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10)
-  # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION    % 10000)
-#endif
-
-
-#elif defined(__clang__) && defined(__apple_build_version__)
-# define COMPILER_ID "AppleClang"
-# if defined(_MSC_VER)
-#  define SIMULATE_ID "MSVC"
-# endif
-# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
-# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
-# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
-# if defined(_MSC_VER)
-   /* _MSC_VER = VVRR */
-#  define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
-#  define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
-# endif
-# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__)
-
-#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION)
-# define COMPILER_ID "ARMClang"
-  # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000)
-  # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100)
-  # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION     % 10000)
-# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION)
-
-#elif defined(__clang__)
-# define COMPILER_ID "Clang"
-# if defined(_MSC_VER)
-#  define SIMULATE_ID "MSVC"
-# endif
-# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
-# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
-# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
-# if defined(_MSC_VER)
-   /* _MSC_VER = VVRR */
-#  define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
-#  define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
-# endif
-
-#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__))
-# define COMPILER_ID "LCC"
-# define COMPILER_VERSION_MAJOR DEC(1)
-# if defined(__LCC__)
-#  define COMPILER_VERSION_MINOR DEC(__LCC__- 100)
-# endif
-# if defined(__LCC_MINOR__)
-#  define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__)
-# endif
-# if defined(__GNUC__) && defined(__GNUC_MINOR__)
-#  define SIMULATE_ID "GNU"
-#  define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
-#  define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
-#  if defined(__GNUC_PATCHLEVEL__)
-#   define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
-#  endif
-# endif
-
-#elif defined(__GNUC__)
-# define COMPILER_ID "GNU"
-# define COMPILER_VERSION_MAJOR DEC(__GNUC__)
-# if defined(__GNUC_MINOR__)
-#  define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__)
-# endif
-# if defined(__GNUC_PATCHLEVEL__)
-#  define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
-# endif
-
-#elif defined(_MSC_VER)
-# define COMPILER_ID "MSVC"
-  /* _MSC_VER = VVRR */
-# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100)
-# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100)
-# if defined(_MSC_FULL_VER)
-#  if _MSC_VER >= 1400
-    /* _MSC_FULL_VER = VVRRPPPPP */
-#   define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000)
-#  else
-    /* _MSC_FULL_VER = VVRRPPPP */
-#   define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000)
-#  endif
-# endif
-# if defined(_MSC_BUILD)
-#  define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD)
-# endif
-
-#elif defined(_ADI_COMPILER)
-# define COMPILER_ID "ADSP"
-#if defined(__VERSIONNUM__)
-  /* __VERSIONNUM__ = 0xVVRRPPTT */
-#  define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF)
-#  define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF)
-#  define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF)
-#  define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF)
-#endif
-
-#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
-# define COMPILER_ID "IAR"
-# if defined(__VER__) && defined(__ICCARM__)
-#  define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000)
-#  define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000)
-#  define COMPILER_VERSION_PATCH DEC((__VER__) % 1000)
-#  define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
-# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__))
-#  define COMPILER_VERSION_MAJOR DEC((__VER__) / 100)
-#  define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100))
-#  define COMPILER_VERSION_PATCH DEC(__SUBVERSION__)
-#  define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
-# endif
-
-#elif defined(__SDCC_VERSION_MAJOR) || defined(SDCC)
-# define COMPILER_ID "SDCC"
-# if defined(__SDCC_VERSION_MAJOR)
-#  define COMPILER_VERSION_MAJOR DEC(__SDCC_VERSION_MAJOR)
-#  define COMPILER_VERSION_MINOR DEC(__SDCC_VERSION_MINOR)
-#  define COMPILER_VERSION_PATCH DEC(__SDCC_VERSION_PATCH)
-# else
-  /* SDCC = VRP */
-#  define COMPILER_VERSION_MAJOR DEC(SDCC/100)
-#  define COMPILER_VERSION_MINOR DEC(SDCC/10 % 10)
-#  define COMPILER_VERSION_PATCH DEC(SDCC    % 10)
-# endif
-
-
-/* These compilers are either not known or too old to define an
-  identification macro.  Try to identify the platform and guess that
-  it is the native compiler.  */
-#elif defined(__hpux) || defined(__hpua)
-# define COMPILER_ID "HP"
-
-#else /* unknown compiler */
-# define COMPILER_ID ""
-#endif
-
-/* Construct the string literal in pieces to prevent the source from
-   getting matched.  Store it in a pointer rather than an array
-   because some compilers will just produce instructions to fill the
-   array rather than assigning a pointer to a static array.  */
-char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]";
-#ifdef SIMULATE_ID
-char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]";
-#endif
-
-#ifdef __QNXNTO__
-char const* qnxnto = "INFO" ":" "qnxnto[]";
-#endif
-
-#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
-char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]";
-#endif
-
-#define STRINGIFY_HELPER(X) #X
-#define STRINGIFY(X) STRINGIFY_HELPER(X)
-
-/* Identify known platforms by name.  */
-#if defined(__linux) || defined(__linux__) || defined(linux)
-# define PLATFORM_ID "Linux"
-
-#elif defined(__MSYS__)
-# define PLATFORM_ID "MSYS"
-
-#elif defined(__CYGWIN__)
-# define PLATFORM_ID "Cygwin"
-
-#elif defined(__MINGW32__)
-# define PLATFORM_ID "MinGW"
-
-#elif defined(__APPLE__)
-# define PLATFORM_ID "Darwin"
-
-#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32)
-# define PLATFORM_ID "Windows"
-
-#elif defined(__FreeBSD__) || defined(__FreeBSD)
-# define PLATFORM_ID "FreeBSD"
-
-#elif defined(__NetBSD__) || defined(__NetBSD)
-# define PLATFORM_ID "NetBSD"
-
-#elif defined(__OpenBSD__) || defined(__OPENBSD)
-# define PLATFORM_ID "OpenBSD"
-
-#elif defined(__sun) || defined(sun)
-# define PLATFORM_ID "SunOS"
-
-#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__)
-# define PLATFORM_ID "AIX"
-
-#elif defined(__hpux) || defined(__hpux__)
-# define PLATFORM_ID "HP-UX"
-
-#elif defined(__HAIKU__)
-# define PLATFORM_ID "Haiku"
-
-#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS)
-# define PLATFORM_ID "BeOS"
-
-#elif defined(__QNX__) || defined(__QNXNTO__)
-# define PLATFORM_ID "QNX"
-
-#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__)
-# define PLATFORM_ID "Tru64"
-
-#elif defined(__riscos) || defined(__riscos__)
-# define PLATFORM_ID "RISCos"
-
-#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__)
-# define PLATFORM_ID "SINIX"
-
-#elif defined(__UNIX_SV__)
-# define PLATFORM_ID "UNIX_SV"
-
-#elif defined(__bsdos__)
-# define PLATFORM_ID "BSDOS"
-
-#elif defined(_MPRAS) || defined(MPRAS)
-# define PLATFORM_ID "MP-RAS"
-
-#elif defined(__osf) || defined(__osf__)
-# define PLATFORM_ID "OSF1"
-
-#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv)
-# define PLATFORM_ID "SCO_SV"
-
-#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX)
-# define PLATFORM_ID "ULTRIX"
-
-#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX)
-# define PLATFORM_ID "Xenix"
-
-#elif defined(__WATCOMC__)
-# if defined(__LINUX__)
-#  define PLATFORM_ID "Linux"
-
-# elif defined(__DOS__)
-#  define PLATFORM_ID "DOS"
-
-# elif defined(__OS2__)
-#  define PLATFORM_ID "OS2"
-
-# elif defined(__WINDOWS__)
-#  define PLATFORM_ID "Windows3x"
-
-# elif defined(__VXWORKS__)
-#  define PLATFORM_ID "VxWorks"
-
-# else /* unknown platform */
-#  define PLATFORM_ID
-# endif
-
-#elif defined(__INTEGRITY)
-# if defined(INT_178B)
-#  define PLATFORM_ID "Integrity178"
-
-# else /* regular Integrity */
-#  define PLATFORM_ID "Integrity"
-# endif
-
-# elif defined(_ADI_COMPILER)
-#  define PLATFORM_ID "ADSP"
-
-#else /* unknown platform */
-# define PLATFORM_ID
-
-#endif
-
-/* For windows compilers MSVC and Intel we can determine
-   the architecture of the compiler being used.  This is because
-   the compilers do not have flags that can change the architecture,
-   but rather depend on which compiler is being used
-*/
-#if defined(_WIN32) && defined(_MSC_VER)
-# if defined(_M_IA64)
-#  define ARCHITECTURE_ID "IA64"
-
-# elif defined(_M_ARM64EC)
-#  define ARCHITECTURE_ID "ARM64EC"
-
-# elif defined(_M_X64) || defined(_M_AMD64)
-#  define ARCHITECTURE_ID "x64"
-
-# elif defined(_M_IX86)
-#  define ARCHITECTURE_ID "X86"
-
-# elif defined(_M_ARM64)
-#  define ARCHITECTURE_ID "ARM64"
-
-# elif defined(_M_ARM)
-#  if _M_ARM == 4
-#   define ARCHITECTURE_ID "ARMV4I"
-#  elif _M_ARM == 5
-#   define ARCHITECTURE_ID "ARMV5I"
-#  else
-#   define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM)
-#  endif
-
-# elif defined(_M_MIPS)
-#  define ARCHITECTURE_ID "MIPS"
-
-# elif defined(_M_SH)
-#  define ARCHITECTURE_ID "SHx"
-
-# else /* unknown architecture */
-#  define ARCHITECTURE_ID ""
-# endif
-
-#elif defined(__WATCOMC__)
-# if defined(_M_I86)
-#  define ARCHITECTURE_ID "I86"
-
-# elif defined(_M_IX86)
-#  define ARCHITECTURE_ID "X86"
-
-# else /* unknown architecture */
-#  define ARCHITECTURE_ID ""
-# endif
-
-#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
-# if defined(__ICCARM__)
-#  define ARCHITECTURE_ID "ARM"
-
-# elif defined(__ICCRX__)
-#  define ARCHITECTURE_ID "RX"
-
-# elif defined(__ICCRH850__)
-#  define ARCHITECTURE_ID "RH850"
-
-# elif defined(__ICCRL78__)
-#  define ARCHITECTURE_ID "RL78"
-
-# elif defined(__ICCRISCV__)
-#  define ARCHITECTURE_ID "RISCV"
-
-# elif defined(__ICCAVR__)
-#  define ARCHITECTURE_ID "AVR"
-
-# elif defined(__ICC430__)
-#  define ARCHITECTURE_ID "MSP430"
-
-# elif defined(__ICCV850__)
-#  define ARCHITECTURE_ID "V850"
-
-# elif defined(__ICC8051__)
-#  define ARCHITECTURE_ID "8051"
-
-# elif defined(__ICCSTM8__)
-#  define ARCHITECTURE_ID "STM8"
-
-# else /* unknown architecture */
-#  define ARCHITECTURE_ID ""
-# endif
-
-#elif defined(__ghs__)
-# if defined(__PPC64__)
-#  define ARCHITECTURE_ID "PPC64"
-
-# elif defined(__ppc__)
-#  define ARCHITECTURE_ID "PPC"
-
-# elif defined(__ARM__)
-#  define ARCHITECTURE_ID "ARM"
-
-# elif defined(__x86_64__)
-#  define ARCHITECTURE_ID "x64"
-
-# elif defined(__i386__)
-#  define ARCHITECTURE_ID "X86"
-
-# else /* unknown architecture */
-#  define ARCHITECTURE_ID ""
-# endif
-
-#elif defined(__TI_COMPILER_VERSION__)
-# if defined(__TI_ARM__)
-#  define ARCHITECTURE_ID "ARM"
-
-# elif defined(__MSP430__)
-#  define ARCHITECTURE_ID "MSP430"
-
-# elif defined(__TMS320C28XX__)
-#  define ARCHITECTURE_ID "TMS320C28x"
-
-# elif defined(__TMS320C6X__) || defined(_TMS320C6X)
-#  define ARCHITECTURE_ID "TMS320C6x"
-
-# else /* unknown architecture */
-#  define ARCHITECTURE_ID ""
-# endif
-
-# elif defined(__ADSPSHARC__)
-#  define ARCHITECTURE_ID "SHARC"
-
-# elif defined(__ADSPBLACKFIN__)
-#  define ARCHITECTURE_ID "Blackfin"
-
-#elif defined(__TASKING__)
-
-# if defined(__CTC__) || defined(__CPTC__)
-#  define ARCHITECTURE_ID "TriCore"
-
-# elif defined(__CMCS__)
-#  define ARCHITECTURE_ID "MCS"
-
-# elif defined(__CARM__)
-#  define ARCHITECTURE_ID "ARM"
-
-# elif defined(__CARC__)
-#  define ARCHITECTURE_ID "ARC"
-
-# elif defined(__C51__)
-#  define ARCHITECTURE_ID "8051"
-
-# elif defined(__CPCP__)
-#  define ARCHITECTURE_ID "PCP"
-
-# else
-#  define ARCHITECTURE_ID ""
-# endif
-
-#else
-#  define ARCHITECTURE_ID
-#endif
-
-/* Convert integer to decimal digit literals.  */
-#define DEC(n)                   \
-  ('0' + (((n) / 10000000)%10)), \
-  ('0' + (((n) / 1000000)%10)),  \
-  ('0' + (((n) / 100000)%10)),   \
-  ('0' + (((n) / 10000)%10)),    \
-  ('0' + (((n) / 1000)%10)),     \
-  ('0' + (((n) / 100)%10)),      \
-  ('0' + (((n) / 10)%10)),       \
-  ('0' +  ((n) % 10))
-
-/* Convert integer to hex digit literals.  */
-#define HEX(n)             \
-  ('0' + ((n)>>28 & 0xF)), \
-  ('0' + ((n)>>24 & 0xF)), \
-  ('0' + ((n)>>20 & 0xF)), \
-  ('0' + ((n)>>16 & 0xF)), \
-  ('0' + ((n)>>12 & 0xF)), \
-  ('0' + ((n)>>8  & 0xF)), \
-  ('0' + ((n)>>4  & 0xF)), \
-  ('0' + ((n)     & 0xF))
-
-/* Construct a string literal encoding the version number. */
-#ifdef COMPILER_VERSION
-char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]";
-
-/* Construct a string literal encoding the version number components. */
-#elif defined(COMPILER_VERSION_MAJOR)
-char const info_version[] = {
-  'I', 'N', 'F', 'O', ':',
-  'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[',
-  COMPILER_VERSION_MAJOR,
-# ifdef COMPILER_VERSION_MINOR
-  '.', COMPILER_VERSION_MINOR,
-#  ifdef COMPILER_VERSION_PATCH
-   '.', COMPILER_VERSION_PATCH,
-#   ifdef COMPILER_VERSION_TWEAK
-    '.', COMPILER_VERSION_TWEAK,
-#   endif
-#  endif
-# endif
-  ']','\0'};
-#endif
-
-/* Construct a string literal encoding the internal version number. */
-#ifdef COMPILER_VERSION_INTERNAL
-char const info_version_internal[] = {
-  'I', 'N', 'F', 'O', ':',
-  'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_',
-  'i','n','t','e','r','n','a','l','[',
-  COMPILER_VERSION_INTERNAL,']','\0'};
-#elif defined(COMPILER_VERSION_INTERNAL_STR)
-char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]";
-#endif
-
-/* Construct a string literal encoding the version number components. */
-#ifdef SIMULATE_VERSION_MAJOR
-char const info_simulate_version[] = {
-  'I', 'N', 'F', 'O', ':',
-  's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[',
-  SIMULATE_VERSION_MAJOR,
-# ifdef SIMULATE_VERSION_MINOR
-  '.', SIMULATE_VERSION_MINOR,
-#  ifdef SIMULATE_VERSION_PATCH
-   '.', SIMULATE_VERSION_PATCH,
-#   ifdef SIMULATE_VERSION_TWEAK
-    '.', SIMULATE_VERSION_TWEAK,
-#   endif
-#  endif
-# endif
-  ']','\0'};
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-#else
-# if defined(__CLASSIC_C__)
-int main(argc, argv) int argc; char *argv[];
-# else
-int main(int argc, char* argv[])
-# endif
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sources_1/new/MMCM/mmcme2_drp.v

@@ -1,867 +0,0 @@
-//-------------------------------------------------------------------------------------------
-//   ____  ____
-//  /   /\/   /
-// /___/  \  /
-// \   \   \/    � Copyright 2019 Xilinx, Inc. All rights reserved.
-//  \   \        This file contains confidential and proprietary information of Xilinx, Inc.
-//  /   /        and is protected under U.S. and international copyright and other
-// /___/   /\    intellectual property laws.
-// \   \  /  \
-//  \___\/\___\
-//
-//-------------------------------------------------------------------------------------------
-// Device:              7_Series
-// Author:              Tatsukawa, Kruger, Ribbing, Defossez
-// Entity Name:         mmcme2_drp
-// Purpose:             This calls the DRP register calculation functions and
-//                      provides a state machine to perform MMCM reconfiguration
-//                      based on the calculated values stored in a initialized
-//                      ROM.
-//                      7-Series MMCM is called:            MMCME2
-//                          Ultrascale MMCM is called:      MMCME3
-//                          UltrascalePlus MMCM is called:  MMCME4
-//                      MMCME3 attributes
-//                          CLKINx_PERIOD:      0.968 to 100.000 (x = 1 or 2)
-//                          REF_JITTERx:        0.001 to 0.999 (x = 1 or 2)
-//                          BANDWIDTH:          LOW, HIGH, OPTIMIZED and POSTCRC
-//                          COMPENSATION:       AUTO, ZHOLD, EXTERNAL, INTERNAL and BUF_IN
-//                          DIVCLK_DIVIDE:      1 to 106
-//                          CLKFBOUT_MULT_F:    2 to 64
-//                          CLKFBOUT_PHASE:     -360 to 360
-//                          CLKOUTn_DIVIDE:     1 to 128 (n = 0 to 6)
-//                          CLKOUTn_PHASE:      -360 to 360 (n = 0 to 6)
-//                          CLKOUTn_DUTY_CYCLE: 0.01 to 0.99 (n = 0 to 6)
-//
-// Tools:               Vivado_2019.1 or newer
-// Limitations:         None
-//
-// Vendor:              Xilinx Inc.
-// Version:             1.40
-// Filename:            mmcme3_drp.v
-// Date Created:        22-Oct-2014
-// Date Last Modified:  25-Jun-2019
-//-------------------------------------------------------------------------------------------
-// Disclaimer:
-//        This disclaimer is not a license and does not grant any rights to the materials
-//        distributed herewith. Except as otherwise provided in a valid license issued to you
-//        by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
-//        ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
-//        WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
-//        TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
-//        PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
-//        negligence, or under any other theory of liability) for any loss or damage of any
-//        kind or nature related to, arising under or in connection with these materials,
-//        including for any direct, or any indirect, special, incidental, or consequential
-//        loss or damage (including loss of data, profits, goodwill, or any type of loss or
-//        damage suffered as a result of any action brought by a third party) even if such
-//        damage or loss was reasonably foreseeable or Xilinx had been advised of the
-//        possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//        Xilinx products are not designed or intended to be fail-safe, or for use in any
-//        application requiring fail-safe performance, such as life-support or safety devices
-//        or systems, Class III medical devices, nuclear facilities, applications related to
-//        the deployment of airbags, or any other applications that could lead to death,
-//        personal injury, or severe property or environmental damage (individually and
-//        collectively, "Critical Applications"). Customer assumes the sole risk and
-//        liability of any use of Xilinx products in Critical Applications, subject only to
-//        applicable laws and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
-//
-// Contact:    e-mail  hotline@xilinx.com        phone   + 1 800 255 7778
-//-------------------------------------------------------------------------------------------
-// Revision History:
-//  Rev: 13-Jan-2011 - Tatsukawa
-//      Updated ROM[18,41] LOCKED bitmask to 16'HFC00
-//  Rev: 30-May-2013 - Tatsukawa
-//      Adding Fractional support for CLKFBOUT_MULT_F, CLKOUT0_DIVIDE_F
-//  Rev: 30-Apr-2014 - Tatsukawa
-//      For fractional multiply changed order to enable fractional
-//      before the multiply is applied to prevent false VCO DRCs
-//      (e.g. DADDR 7'h15 must be set before updating 7'h14)
-//  Rev: 24-Oct-2014 - Ribbing
-//      Parameters have been added to clarify Reg1/Reg2/Shared registers
-//  Rev: 08-Jun-2015 - Kruger
-//      WAIT_LOCK update
-//  Rev: 02-May-2016 - Kruger
-//      Reordering FRAC_EN bits DADDR(7'h09, 7'h15)
-//      Registers before frac settings (7'h08, 7'h14)
-//  Rev: 19-Sep-2018 - Defossez
-//      Updated comments of BANDWIDTH.
-//      Corrected some typos.
-//  Rev: 25-Jun-2019 - Defossez
-//      Adding registering possibility for LOCKE signal.
-//-------------------------------------------------------------------------------------------
-//
-`timescale 1ps/1ps
-//
-module mmcme2_drp
-    #(
-        // Register the LOCKED signal with teh MMCME3_ADV input clock.
-        // The LOCKED_IN (LOCKED from the MMCME3_ADV) is fed into a register and then
-        // passed the LOCKED_OUT when REGISTER_LOCKED is set to "Reg" or when set to
-        // "NoReg" LOCKED_IN is just passed on to LOCKED_OUT without being registered.
-        parameter REGISTER_LOCKED       = "Reg",
-        // Use the registered LOCKED signal from the MMCME3 also for the DRP state machine.
-        parameter USE_REG_LOCKED        = "No",
-        // Possible/allowed combinations of above two parameters:
-        // | REGISTER_LOCKED | USE_REG_LOCKED |                                            |
-        // |-----------------|----------------|--------------------------------------------|
-        // |      "NoReg"    |     "No"       | LOCKED is just passed through mmcme3_drp   |
-        // |                 |                | and is used as is with the state machine   |
-        // |      "NoReg"    |     "Yes"      | NOT ALLOWED                                |
-        // |       "Reg"     |     "No"       | LOCKED is registered but the unregistered  |
-        // |                 |                | version is used for the state machine.     |
-        // |       "Reg"     |     "Yes"      | LOCKED is registered and the registered    |
-        // |                 |                | version is also used by the state machine. |
-        //
-        //***********************************************************************
-        // State 1 Parameters - These are for the first reconfiguration state.
-        //***********************************************************************
-        //
-        // These parameters have an effect on the feedback path. A change on
-        // these parameters will effect all of the clock outputs.
-        //
-        // The parameters are composed of:
-        //    _MULT: This can be from 2 to 64. It has an effect on the VCO
-        //          frequency which consequently, effects all of the clock
-        //          outputs.
-        //    _PHASE: This is the phase multiplied by 1000. For example if
-        //          a phase of 24.567 deg was desired the input value would be
-        //          24567. The range for the phase is from -360000 to 360000.
-        //    _FRAC: This can be from 0 to 875. This represents the fractional
-        //          divide multiplied by 1000.
-        //          M = _MULT + _FRAC / 1000
-        //          e.g. M=8.125
-        //               _MULT = 8
-        //               _FRAC = 125
-        //    _FRAC_EN: This indicates fractional divide has been enabled. If 1
-        //          then the fractional divide algorithm will be used to calculate
-        //          register settings. If 0 then default calculation to be used.
-        parameter S1_CLKFBOUT_MULT          = 13,
-        parameter S1_CLKFBOUT_PHASE         = 0,
-        parameter S1_CLKFBOUT_FRAC          = 125,
-        parameter S1_CLKFBOUT_FRAC_EN       = 1,
-        //
-        // The bandwidth parameter effects the phase error and the jitter filter
-        // capability of the MMCM. For more information on this parameter see the
-        // Device user guide.
-        // Possible values are: "LOW", "LOW_SS", "HIGH" and "OPTIMIZED"
-        parameter S1_BANDWIDTH              = "LOW",
-        //
-        // The divclk parameter allows the input clock to be divided before it
-        // reaches the phase and frequency comparator. This can be set between
-        // 1 and 128.
-        parameter S1_DIVCLK_DIVIDE          = 1,
-
-        // The following parameters describe the configuration that each clock
-        // output should have once the reconfiguration for state one has
-        // completed.
-        //
-        // The parameters are composed of:
-        //    _DIVIDE: This can be from 1 to 128
-        //    _PHASE: This is the phase multiplied by 1000. For example if
-        //          a phase of 24.567 deg was desired the input value would be
-        //          24567. The range for the phase is from -360000 to 360000.
-        //    _DUTY: This is the duty cycle multiplied by 100,000.  For example if
-        //          a duty cycle of .24567 was desired the input would be
-        //          24567.
-        //
-        parameter S1_CLKOUT0_DIVIDE         = 2,
-        parameter S1_CLKOUT0_PHASE          = 0,
-        parameter S1_CLKOUT0_DUTY           = 50000,
-        parameter S1_CLKOUT0_FRAC          = 125,
-        parameter S1_CLKOUT0_FRAC_EN       = 1,
-        //
-        parameter S1_CLKOUT1_DIVIDE         = 1,
-        parameter S1_CLKOUT1_PHASE          = 0,
-        parameter S1_CLKOUT1_DUTY           = 50000,
-        //
-        parameter S1_CLKOUT2_DIVIDE         = 1,
-        parameter S1_CLKOUT2_PHASE          = 0,
-        parameter S1_CLKOUT2_DUTY           = 50000,
-        //
-        parameter S1_CLKOUT3_DIVIDE         = 1,
-        parameter S1_CLKOUT3_PHASE          = 0,
-        parameter S1_CLKOUT3_DUTY           = 50000,
-        //
-        parameter S1_CLKOUT4_DIVIDE         = 1,
-        parameter S1_CLKOUT4_PHASE          = 0,
-        parameter S1_CLKOUT4_DUTY           = 50000,
-        //
-        parameter S1_CLKOUT5_DIVIDE         = 1,
-        parameter S1_CLKOUT5_PHASE          = 0,
-        parameter S1_CLKOUT5_DUTY           = 50000,
-        //
-        parameter S1_CLKOUT6_DIVIDE         = 1,
-        parameter S1_CLKOUT6_PHASE          = 0,
-        parameter S1_CLKOUT6_DUTY           = 50000,
-        //
-        //***********************************************************************
-        // State 2 Parameters - These are for the second reconfiguration state.
-        //***********************************************************************
-        //
-        // These parameters have an effect on the feedback path. A change on
-        // these parameters will effect all of the clock outputs.
-        //
-        // The parameters are composed of:
-        //    _MULT: This can be from 2 to 64. It has an effect on the VCO
-        //          frequency which consequently, effects all of the clock
-        //          outputs.
-        //    _PHASE: This is the phase multiplied by 1000. For example if
-        //          a phase of 24.567 deg was desired the input value would be
-        //          24567.  The range for the phase is from -360000 to 360000.
-        //    _FRAC: This can be from 0 to 875. This represents the fractional
-        //          divide multiplied by 1000.
-        //          M = _MULT + _FRAC / 1000
-        //          e.g. M=8.125
-        //               _MULT = 8
-        //               _FRAC = 125
-        //    _FRAC_EN: This indicates fractional divide has been enabled. If 1
-        //          then the fractional divide algorithm will be used to calculate
-        //          register settings. If 0 then default calculation to be used.
-        parameter S2_CLKFBOUT_MULT          = 1,
-        parameter S2_CLKFBOUT_PHASE         = 0,
-        parameter S2_CLKFBOUT_FRAC          = 125,
-        parameter S2_CLKFBOUT_FRAC_EN       = 1,
-        //
-        // The bandwidth parameter effects the phase error and the jitter filter
-        // capability of the MMCM. For more information on this parameter see the
-        // Device user guide.
-        // Possible values are: "LOW", "LOW_SS", "HIGH" and "OPTIMIZED"
-        parameter S2_BANDWIDTH              = "LOW",
-        //
-        // The divclk parameter allows the input clock to be divided before it
-        // reaches the phase and frequency comparator. This can be set between
-        // 1 and 128.
-        parameter S2_DIVCLK_DIVIDE          = 1,
-        //
-        // The following parameters describe the configuration that each clock
-        // output should have once the reconfiguration for state one has
-        // completed.
-        //
-        // The parameters are composed of:
-        //    _DIVIDE: This can be from 1 to 128
-        //    _PHASE: This is the phase multiplied by 1000. For example if
-        //          a phase of 24.567 deg was desired the input value would be
-        //          24567. The range for the phase is from -360000 to 360000
-        //    _DUTY: This is the duty cycle multiplied by 100,000. For example if
-        //          a duty cycle of .24567 was desired the input would be
-        //          24567.
-        //
-        parameter S2_CLKOUT0_DIVIDE         = 1,
-        parameter S2_CLKOUT0_PHASE          = 0,
-        parameter S2_CLKOUT0_DUTY           = 50000,
-        parameter S2_CLKOUT0_FRAC          = 125,
-        parameter S2_CLKOUT0_FRAC_EN       = 1,
-        //
-        parameter S2_CLKOUT1_DIVIDE         = 2,
-        parameter S2_CLKOUT1_PHASE          = 0,
-        parameter S2_CLKOUT1_DUTY           = 50000,
-        //
-        parameter S2_CLKOUT2_DIVIDE         = 3,
-        parameter S2_CLKOUT2_PHASE          = 0,
-        parameter S2_CLKOUT2_DUTY           = 50000,
-        //
-        parameter S2_CLKOUT3_DIVIDE         = 4,
-        parameter S2_CLKOUT3_PHASE          = 0,
-        parameter S2_CLKOUT3_DUTY           = 50000,
-        //
-        parameter S2_CLKOUT4_DIVIDE         = 5,
-        parameter S2_CLKOUT4_PHASE          = 0,
-        parameter S2_CLKOUT4_DUTY           = 50000,
-        //
-        parameter S2_CLKOUT5_DIVIDE         = 5,
-        parameter S2_CLKOUT5_PHASE          = 0,
-        parameter S2_CLKOUT5_DUTY           = 50000,
-        //
-        parameter S2_CLKOUT6_DIVIDE         = 5,
-        parameter S2_CLKOUT6_PHASE          = -90,
-        parameter S2_CLKOUT6_DUTY           = 50000
-    ) (
-        // These signals are controlled by user logic interface and are covered
-        // in more detail within the XAPP.
-        input             SADDR,
-        input             SEN,
-        input             SCLK,
-        input             RST,
-        output reg        SRDY,
-
-
-         // input [7:0]     ClkDiv1_i,
-         // input [7:0]     ClkDiv2_i,
-         // input [7:0]     ClkDiv3_i,
-         // input [7:0]     ClkDiv4_i,
-         // input [7:0]     ClkDiv5_i,
-         // input [7:0]     ClkDiv6_i,
-         // input [7:0]     ClkDiv7_i,
-
-
-
-        //
-        // These signals are to be connected to the MMCM_ADV by port name.
-        // Their use matches the MMCM port description in the Device User Guide.
-        input      [15:0] DO,
-        input             DRDY,
-        input             LOCK_REG_CLK_IN,
-        input             LOCKED_IN,
-        output reg        DWE,
-        output reg        DEN,
-        output reg [6:0]  DADDR,
-        output reg [15:0] DI,
-        output            DCLK,
-        output reg        RST_MMCM,
-        output            LOCKED_OUT
-    );
-//----------------------------------------------------------------------------------------
-    //
-    wire        IntLocked;
-    wire        IntRstMmcm;
-    wire  [15:0] clkVal; 
-    wire  [15:0] fracPart;
-    assign clkVal = 16'h208;
-   
-
-
-    //
-    // 100 ps delay for behavioral simulations
-    localparam  TCQ = 100;
-
-    // Make sure the memory is implemented as distributed
-    (* rom_style = "distributed" *)
-    //
-    // ROM of:  39 bit word 64 words deep
-    reg [38:0]  rom [63:0];
-    reg [5:0]   rom_addr;
-    reg [38:0]  rom_do;
-    reg         next_srdy;
-    reg [5:0]   next_rom_addr;
-    reg [6:0]   next_daddr;
-    reg         next_dwe;
-    reg         next_den;
-    reg         next_rst_mmcm;
-    reg [15:0]  next_di;
-    //
-    // Insert a register in LOCKED or not depending on the value given to the parameters
-    // REGISTER_LOCKED. When REGISTER_LOCKED is set to "Reg" insert a register, when set
-    // to "NoReg" don't insert a register but just pass the LOCKED signal from input to
-    // output.
-    // Use or not, under USE_REG_LOCKED parameter control, the registered version of the
-    // LOCKED signal for the DRP state machine.
-    // Possible/allowed combinations of the two LOCKED related parameters:
-    //
-    // | REGISTER_LOCKED | USE_REG_LOCKED |                                            |
-    // |-----------------|----------------|--------------------------------------------|
-    // |      "NoReg"    |     "No"       | LOCKED is just passed through mmcme3_drp   |
-    // |                 |                | and is used as is with the state machine   |
-    // |      "NoReg"    |     "Yes"      | NOT ALLOWED                                |
-    // |       "Reg"     |     "No"       | LOCKED is registered but the unregistered  |
-    // |                 |                | version is used for the state machine.     |
-    // |       "Reg"     |     "Yes"      | LOCKED is registered and the registered    |
-    // |                 |                | version is also used by the state machine. |
-    //
-    generate
-        if (REGISTER_LOCKED == "NoReg" && USE_REG_LOCKED == "No") begin
-            assign LOCKED_OUT = LOCKED_IN;
-            assign IntLocked = LOCKED_IN;
-        end else if (REGISTER_LOCKED == "Reg" && USE_REG_LOCKED == "No") begin
-            FDRE #(
-                .INIT           (0),
-                .IS_C_INVERTED  (0),
-                .IS_D_INVERTED  (0),
-                .IS_R_INVERTED  (0)
-            ) mmcme3_drp_I_Fdrp (
-                .D      (LOCKED_IN),
-                .CE     (1'b1),
-                .R      (IntRstMmcm),
-                .C      (LOCK_REG_CLK_IN),
-                .Q      (LOCKED_OUT)
-            );
-            //
-            assign IntLocked = LOCKED_IN;
-        end else if (REGISTER_LOCKED == "Reg" && USE_REG_LOCKED == "Yes") begin
-            FDRE #(
-                .INIT           (0),
-                .IS_C_INVERTED  (0),
-                .IS_D_INVERTED  (0),
-                .IS_R_INVERTED  (0)
-            ) mmcme3_drp_I_Fdrp (
-                .D  (LOCKED_IN),
-                .CE (1'b1),
-                .R  (IntRstMmcm),
-                .C  (LOCK_REG_CLK_IN),
-                .Q  (LOCKED_OUT)
-            );
-            //
-            assign IntLocked = LOCKED_OUT;
-        end
-    endgenerate
-
-    // Integer used to initialize remainder of unused ROM
-    integer     ii;
-
-    // Pass SCLK to DCLK for the MMCM
-    assign DCLK = SCLK;
-     assign IntRstMmcm = RST_MMCM;
-
-    // Include the MMCM reconfiguration functions.  This contains the constant
-    // functions that are used in the calculations below.  This file is
-    // required.
-    `include "mmcme2_drp_func.h"
-
-    //**************************************************************************
-    // State 1 Calculations
-    //**************************************************************************
-    // Please see header for information.
-    localparam [37:0] S1_CLKFBOUT       =
-       mmcm_count_calc(S1_CLKFBOUT_MULT, S1_CLKFBOUT_PHASE, 50000);
-
-    localparam [37:0] S1_CLKFBOUT_FRAC_CALC       =
-       mmcm_frac_count_calc(S1_CLKFBOUT_MULT, S1_CLKFBOUT_PHASE, 50000, S1_CLKFBOUT_FRAC);
-
-    localparam [9:0]  S1_DIGITAL_FILT   =
-       mmcm_filter_lookup(S1_CLKFBOUT_MULT, S1_BANDWIDTH);
-
-    localparam [39:0] S1_LOCK           =
-       mmcm_lock_lookup(S1_CLKFBOUT_MULT);
-
-    localparam [37:0] S1_DIVCLK         =
-       mmcm_count_calc(S1_DIVCLK_DIVIDE, 0, 50000);
-
-    localparam [37:0] S1_CLKOUT0        =
-       mmcm_count_calc(S1_CLKOUT0_DIVIDE, S1_CLKOUT0_PHASE, S1_CLKOUT0_DUTY);
-       localparam [15:0] S1_CLKOUT0_REG1        = S1_CLKOUT0[15:0]; //See log file for 16 bit reporting of the register
-       localparam [15:0] S1_CLKOUT0_REG2        = S1_CLKOUT0[31:16]; //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S1_CLKOUT0_FRAC_CALC        =
-       mmcm_frac_count_calc(S1_CLKOUT0_DIVIDE, S1_CLKOUT0_PHASE, 50000, S1_CLKOUT0_FRAC);
-        localparam [15:0] S1_CLKOUT0_FRAC_REG1        = S1_CLKOUT0_FRAC_CALC[15:0];  //See log file for 16 bit reporting of the register
-        localparam [15:0] S1_CLKOUT0_FRAC_REG2        = S1_CLKOUT0_FRAC_CALC[31:16];  //See log file for 16 bit reporting of the register
-        localparam [5:0] S1_CLKOUT0_FRAC_REGSHARED        = S1_CLKOUT0_FRAC_CALC[37:32];  //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S1_CLKOUT1        =
-       mmcm_count_calc(S1_CLKOUT1_DIVIDE, S1_CLKOUT1_PHASE, S1_CLKOUT1_DUTY);
-        localparam [15:0] S1_CLKOUT1_REG1        = S1_CLKOUT1[15:0];  //See log file for 16 bit reporting of the register
-        localparam [15:0] S1_CLKOUT1_REG2        = S1_CLKOUT1[31:16];  //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S1_CLKOUT2        =
-       mmcm_count_calc(S1_CLKOUT2_DIVIDE, S1_CLKOUT2_PHASE, S1_CLKOUT2_DUTY);
-       localparam [15:0] S1_CLKOUT2_REG1        = S1_CLKOUT2[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S1_CLKOUT2_REG2        = S1_CLKOUT2[31:16];  //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S1_CLKOUT3        =
-       mmcm_count_calc(S1_CLKOUT3_DIVIDE, S1_CLKOUT3_PHASE, S1_CLKOUT3_DUTY);
-       localparam [15:0] S1_CLKOUT3_REG1        = S1_CLKOUT3[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S1_CLKOUT3_REG2        = S1_CLKOUT3[31:16];  //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S1_CLKOUT4        =
-       mmcm_count_calc(S1_CLKOUT4_DIVIDE, S1_CLKOUT4_PHASE, S1_CLKOUT4_DUTY);
-       localparam [15:0] S1_CLKOUT4_REG1        = S1_CLKOUT4[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S1_CLKOUT4_REG2        = S1_CLKOUT4[31:16];  //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S1_CLKOUT5        =
-       mmcm_count_calc(S1_CLKOUT5_DIVIDE, S1_CLKOUT5_PHASE, S1_CLKOUT5_DUTY);
-       localparam [15:0] S1_CLKOUT5_REG1        = S1_CLKOUT5[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S1_CLKOUT5_REG2        = S1_CLKOUT5[31:16];  //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S1_CLKOUT6        =
-       mmcm_count_calc(S1_CLKOUT6_DIVIDE, S1_CLKOUT6_PHASE, S1_CLKOUT6_DUTY);
-       localparam [15:0] S1_CLKOUT6_REG1        = S1_CLKOUT6[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S1_CLKOUT6_REG2        = S1_CLKOUT6[31:16]; //See log file for 16 bit reporting of the register
-
-    //**************************************************************************
-    // State 2 Calculations
-    //**************************************************************************
-    localparam [37:0] S2_CLKFBOUT       =
-       mmcm_count_calc(S2_CLKFBOUT_MULT, S2_CLKFBOUT_PHASE, 50000);
-
-    localparam [37:0] S2_CLKFBOUT_FRAC_CALC       =
-       mmcm_frac_count_calc(S2_CLKFBOUT_MULT, S2_CLKFBOUT_PHASE, 50000, S2_CLKFBOUT_FRAC);
-
-    localparam [9:0] S2_DIGITAL_FILT    =
-       mmcm_filter_lookup(S2_CLKFBOUT_MULT, S2_BANDWIDTH);
-
-    localparam [39:0] S2_LOCK           =
-       mmcm_lock_lookup(S2_CLKFBOUT_MULT);
-
-    localparam [37:0] S2_DIVCLK         =
-       mmcm_count_calc(S2_DIVCLK_DIVIDE, 0, 50000);
-
-    localparam [37:0] S2_CLKOUT0        =
-       mmcm_count_calc(S2_CLKOUT0_DIVIDE, S2_CLKOUT0_PHASE, S2_CLKOUT0_DUTY);
-       localparam [15:0] S2_CLKOUT0_REG1        = S2_CLKOUT0[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S2_CLKOUT0_REG2        = S2_CLKOUT0[31:16]; //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S2_CLKOUT0_FRAC_CALC        =
-       mmcm_frac_count_calc(S2_CLKOUT0_DIVIDE, S2_CLKOUT0_PHASE, 50000, S2_CLKOUT0_FRAC);
-       localparam [15:0] S2_CLKOUT0_FRAC_CALC_REG1        = S2_CLKOUT0_FRAC_CALC[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S2_CLKOUT0_FRAC_CALC_REG2        = S2_CLKOUT0_FRAC_CALC[31:16]; //See log file for 16 bit reporting of the register
-       localparam [15:0] S2_CLKOUT0_FRAC_CALC_REGSHARED        = S2_CLKOUT0_FRAC_CALC[31:16]; //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S2_CLKOUT1        =
-       mmcm_count_calc(S2_CLKOUT1_DIVIDE, S2_CLKOUT1_PHASE, S2_CLKOUT1_DUTY);
-       localparam [15:0] S2_CLKOUT1_REG1        = S2_CLKOUT1[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S2_CLKOUT1_REG2        = S2_CLKOUT1[31:16]; //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S2_CLKOUT2        =
-       mmcm_count_calc(S2_CLKOUT2_DIVIDE, S2_CLKOUT2_PHASE, S2_CLKOUT2_DUTY);
-       localparam [15:0] S2_CLKOUT2_REG1        = S2_CLKOUT2[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S2_CLKOUT2_REG2        = S2_CLKOUT2[31:16]; //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S2_CLKOUT3        =
-       mmcm_count_calc(S2_CLKOUT3_DIVIDE, S2_CLKOUT3_PHASE, S2_CLKOUT3_DUTY);
-       localparam [15:0] S2_CLKOUT3_REG1        = S2_CLKOUT3[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S2_CLKOUT3_REG2        = S2_CLKOUT3[31:16]; //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S2_CLKOUT4        =
-       mmcm_count_calc(S2_CLKOUT4_DIVIDE, S2_CLKOUT4_PHASE, S2_CLKOUT4_DUTY);
-       localparam [15:0] S2_CLKOUT4_REG1        = S2_CLKOUT4[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S2_CLKOUT4_REG2        = S2_CLKOUT4[31:16]; //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S2_CLKOUT5        =
-       mmcm_count_calc(S2_CLKOUT5_DIVIDE, S2_CLKOUT5_PHASE, S2_CLKOUT5_DUTY);
-       localparam [15:0] S2_CLKOUT5_REG1        = S2_CLKOUT5[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S2_CLKOUT5_REG2        = S2_CLKOUT5[31:16]; //See log file for 16 bit reporting of the register
-
-    localparam [37:0] S2_CLKOUT6        =
-       mmcm_count_calc(S2_CLKOUT6_DIVIDE, S2_CLKOUT6_PHASE, S2_CLKOUT6_DUTY);
-       localparam [15:0] S2_CLKOUT6_REG1        = S2_CLKOUT6[15:0];  //See log file for 16 bit reporting of the register
-       localparam [15:0] S2_CLKOUT6_REG2        = S2_CLKOUT6[31:16]; //See log file for 16 bit reporting of the register
-
-    initial begin
-       // rom entries contain (in order) the address, a bitmask, and a bitset
-       //***********************************************************************
-       // State 1 Initialization
-       //***********************************************************************
-
-       // Store the power bits
-       rom[0] = {7'h28, 16'h0000, 16'hFFFF};
-
-       // Store CLKOUT0 divide and phase
-       rom[1]  = (S1_CLKOUT0_FRAC_EN == 0) ?
-                         {7'h09, 16'h8000, 16'h0480}:
-                         {7'h09, 16'h8000, 16'h0480};
-       rom[2]  = (S1_CLKOUT0_FRAC_EN == 0) ?
-                         {7'h08, 16'h1000, clkVal}:
-                         {7'h08, 16'h1000, clkVal};
-
-       // Store CLKOUT1 divide and phase
-       rom[3]  = {7'h0A, 16'h1000, S1_CLKOUT1[15:0]};
-       rom[4]  = {7'h0B, 16'hFC00, S1_CLKOUT1[31:16]};
-
-       // Store CLKOUT2 divide and phase
-       rom[5]  = {7'h0C, 16'h1000, S1_CLKOUT2[15:0]};
-       rom[6]  = {7'h0D, 16'hFC00, S1_CLKOUT2[31:16]};
-
-       // Store CLKOUT3 divide and phase
-       rom[7]  = {7'h0E, 16'h1000, S1_CLKOUT3[15:0]};
-       rom[8]  = {7'h0F, 16'hFC00, S1_CLKOUT3[31:16]};
-
-       // Store CLKOUT4 divide and phase
-       rom[9]  = {7'h10, 16'h1000, S1_CLKOUT4[15:0]};
-       rom[10]  = {7'h11, 16'hFC00, S1_CLKOUT4[31:16]};
-
-       // Store CLKOUT5 divide and phase
-       rom[11] = {7'h06, 16'h1000, S1_CLKOUT5[15:0]};
-       rom[12] = (S1_CLKOUT0_FRAC_EN == 0) ?
-                 {7'h07, 16'hC000, S1_CLKOUT5[31:16]}:
-                 {7'h07, 16'hC000, S1_CLKOUT5[31:30], S1_CLKOUT0_FRAC_CALC[35:32],S1_CLKOUT5[25:16]};
-
-       // Store CLKOUT6 divide and phase
-       rom[13] = {7'h12, 16'h1000, S1_CLKOUT6[15:0]};
-       rom[14] = (S1_CLKFBOUT_FRAC_EN == 0) ?
-                 {7'h13, 16'hC000, S1_CLKOUT6[31:16]}:
-                 {7'h13, 16'hC000, S1_CLKOUT6[31:30], S1_CLKFBOUT_FRAC_CALC[35:32],S1_CLKOUT6[25:16]};
-
-       // Store the input divider
-       rom[15] = {7'h16, 16'hC000, {2'h0, S1_DIVCLK[23:22], S1_DIVCLK[11:0]} };
-
-       // Store the feedback divide and phase
-       rom[16] = (S1_CLKFBOUT_FRAC_EN == 0) ?
-                 {7'h14, 16'h1000, S1_CLKFBOUT[15:0]}:
-                 {7'h14, 16'h1000, S1_CLKFBOUT_FRAC_CALC[15:0]};
-       rom[17] = (S1_CLKFBOUT_FRAC_EN == 0) ?
-                 {7'h15, 16'h8000, S1_CLKFBOUT[31:16]}:
-                 {7'h15, 16'h8000, S1_CLKFBOUT_FRAC_CALC[31:16]};
-
-       // Store the lock settings
-       rom[18] = {7'h18, 16'hFC00, {6'h00, S1_LOCK[29:20]} };
-       rom[19] = {7'h19, 16'h8000, {1'b0 , S1_LOCK[34:30], S1_LOCK[9:0]} };
-       rom[20] = {7'h1A, 16'h8000, {1'b0 , S1_LOCK[39:35], S1_LOCK[19:10]} };
-
-       // Store the filter settings
-       rom[21] = {7'h4E, 16'h66FF,
-                 S1_DIGITAL_FILT[9], 2'h0, S1_DIGITAL_FILT[8:7], 2'h0,
-                 S1_DIGITAL_FILT[6], 8'h00 };
-       rom[22] = {7'h4F, 16'h666F,
-                 S1_DIGITAL_FILT[5], 2'h0, S1_DIGITAL_FILT[4:3], 2'h0,
-                 S1_DIGITAL_FILT[2:1], 2'h0, S1_DIGITAL_FILT[0], 4'h0 };
-
-       //***********************************************************************
-       // State 2 Initialization
-       //***********************************************************************
-
-       // Store the power bits
-       rom[23] = {7'h28, 16'h0000, 16'hFFFF};
-
-       // Store CLKOUT0 divide and phase
-       rom[24] = (S2_CLKOUT0_FRAC_EN == 0) ?
-                 {7'h09, 16'h8000, 16'h0480}:
-                 {7'h09, 16'h8000, 16'h0480};
-       rom[25] = (S2_CLKOUT0_FRAC_EN == 0) ?
-                 {7'h08, 16'h1000, clkVal}:
-                 {7'h08, 16'h1000, clkVal};
-
-       // Store CLKOUT1 divide and phase
-       rom[26] = {7'h0A, 16'h1000, S2_CLKOUT1[15:0]};
-       rom[27] = {7'h0B, 16'hFC00, S2_CLKOUT1[31:16]};
-
-       // Store CLKOUT2 divide and phase
-       rom[28] = {7'h0C, 16'h1000, S2_CLKOUT2[15:0]};
-       rom[29] = {7'h0D, 16'hFC00, S2_CLKOUT2[31:16]};
-
-       // Store CLKOUT3 divide and phase
-       rom[30] = {7'h0E, 16'h1000, S2_CLKOUT3[15:0]};
-       rom[31] = {7'h0F, 16'hFC00, S2_CLKOUT3[31:16]};
-
-       // Store CLKOUT4 divide and phase
-       rom[32] = {7'h10, 16'h1000, S2_CLKOUT4[15:0]};
-       rom[33] = {7'h11, 16'hFC00, S2_CLKOUT4[31:16]};
-
-       // Store CLKOUT5 divide and phase
-       rom[34] = {7'h06, 16'h1000, S2_CLKOUT5[15:0]};
-       rom[35] = (S2_CLKOUT0_FRAC_EN == 0) ?
-                 {7'h07, 16'hC000, S2_CLKOUT5[31:16]}:
-                 {7'h07, 16'hC000, S2_CLKOUT5[31:30], S2_CLKOUT0_FRAC_CALC[35:32],S2_CLKOUT5[25:16]};
-
-       // Store CLKOUT6 divide and phase
-       rom[36] = {7'h12, 16'h1000, S2_CLKOUT6[15:0]};
-       rom[37] = (S2_CLKFBOUT_FRAC_EN == 0) ?
-                 {7'h13, 16'hC000, S2_CLKOUT6[31:16]}:
-                 {7'h13, 16'hC000, S2_CLKOUT6[31:30], S2_CLKFBOUT_FRAC_CALC[35:32],S2_CLKOUT6[25:16]};
-
-       // Store the input divider
-       rom[38] = {7'h16, 16'hC000, {2'h0, S2_DIVCLK[23:22], S2_DIVCLK[11:0]} };
-
-       // Store the feedback divide and phase
-       rom[39] = (S2_CLKFBOUT_FRAC_EN == 0) ?
-                 {7'h14, 16'h1000, S2_CLKFBOUT[15:0]}:
-                 {7'h14, 16'h1000, S2_CLKFBOUT_FRAC_CALC[15:0]};
-       rom[40] = (S2_CLKFBOUT_FRAC_EN == 0) ?
-                 {7'h15, 16'h8000, S2_CLKFBOUT[31:16]}:
-                 {7'h15, 16'h8000, S2_CLKFBOUT_FRAC_CALC[31:16]};
-
-       // Store the lock settings
-       rom[41] = {7'h18, 16'hFC00, {6'h00, S2_LOCK[29:20]} };
-       rom[42] = {7'h19, 16'h8000, {1'b0 , S2_LOCK[34:30], S2_LOCK[9:0]} };
-       rom[43] = {7'h1A, 16'h8000, {1'b0 , S2_LOCK[39:35], S2_LOCK[19:10]} };
-
-       // Store the filter settings
-       rom[44] = {7'h4E, 16'h66FF,
-                 S2_DIGITAL_FILT[9], 2'h0, S2_DIGITAL_FILT[8:7], 2'h0,
-                 S2_DIGITAL_FILT[6], 8'h00 };
-       rom[45] = {7'h4F, 16'h666F,
-                 S2_DIGITAL_FILT[5], 2'h0, S2_DIGITAL_FILT[4:3], 2'h0,
-                 S2_DIGITAL_FILT[2:1], 2'h0, S2_DIGITAL_FILT[0], 4'h0 };
-
-       // Initialize the rest of the ROM
-       rom[46] = {7'h28,32'h0000_0000};
-       for(ii = 47; ii < 64; ii = ii +1) begin
-          rom[ii] = 0;
-       end
-    end
-
-    // Output the initialized rom value based on rom_addr each clock cycle
-    always @(posedge SCLK) begin
-       rom_do<= #TCQ rom[rom_addr];
-    end
-
-    //**************************************************************************
-    // Everything below is associated whith the state machine that is used to
-    // Read/Modify/Write to the MMCM.
-    //**************************************************************************
-
-    // State Definitions
-    localparam RESTART      = 4'h1;
-    localparam WAIT_LOCK    = 4'h2;
-    localparam WAIT_SEN     = 4'h3;
-    localparam ADDRESS      = 4'h4;
-    localparam WAIT_A_DRDY  = 4'h5;
-    localparam BITMASK      = 4'h6;
-    localparam BITSET       = 4'h7;
-    localparam WRITE        = 4'h8;
-    localparam WAIT_DRDY    = 4'h9;
-
-    // State sync
-    reg [3:0]  current_state   = RESTART;
-    reg [3:0]  next_state      = RESTART;
-
-    // These variables are used to keep track of the number of iterations that
-    //    each state takes to reconfigure.
-    // STATE_COUNT_CONST is used to reset the counters and should match the
-    //    number of registers necessary to reconfigure each state.
-    localparam STATE_COUNT_CONST  = 4;
-    reg [4:0] state_count         = STATE_COUNT_CONST;
-    reg [4:0] next_state_count    = STATE_COUNT_CONST;
-
-    // This block assigns the next register value from the state machine below
-    always @(posedge SCLK) begin
-       DADDR       <= #TCQ next_daddr;
-       DWE         <= #TCQ next_dwe;
-       DEN         <= #TCQ next_den;
-       RST_MMCM    <= #TCQ next_rst_mmcm;
-       DI          <= #TCQ next_di;
-
-       SRDY        <= #TCQ next_srdy;
-
-       rom_addr    <= #TCQ next_rom_addr;
-       state_count <= #TCQ next_state_count;
-    end
-
-    // This block assigns the next state, reset is syncronous.
-    always @(posedge SCLK) begin
-       if(RST) begin
-          current_state <= #TCQ RESTART;
-       end else begin
-          current_state <= #TCQ next_state;
-       end
-    end
-
-    always @* begin
-       // Setup the default values
-       next_srdy         = 1'b0;
-       next_daddr        = DADDR;
-       next_dwe          = 1'b0;
-       next_den          = 1'b0;
-       next_rst_mmcm     = RST_MMCM;
-       next_di           = DI;
-       next_rom_addr     = rom_addr;
-       next_state_count  = state_count;
-
-       case (current_state)
-          // If RST is asserted reset the machine
-          RESTART: begin
-             next_daddr     = 7'h00;
-             next_di        = 16'h0000;
-             next_rom_addr  = 6'h00;
-             next_rst_mmcm  = 1'b1;
-             next_state     = WAIT_LOCK;
-          end
-
-          // Waits for the MMCM to assert IntLocked - once it does asserts SRDY
-          WAIT_LOCK: begin
-             // Make sure reset is de-asserted
-             next_rst_mmcm   = 1'b0;
-             // Reset the number of registers left to write for the next
-             // reconfiguration event.
-             next_state_count = STATE_COUNT_CONST ;
-             next_rom_addr = SADDR ? STATE_COUNT_CONST : 8'h00;
-
-             if(IntLocked) begin
-                // MMCM is IntLocked, go on to wait for the SEN signal
-                next_state  = WAIT_SEN;
-                // Assert SRDY to indicate that the reconfiguration module is
-                // ready
-                next_srdy   = 1'b1;
-             end else begin
-                // Keep waiting, IntLocked has not asserted yet
-                next_state  = WAIT_LOCK;
-             end
-          end
-
-          // Wait for the next SEN pulse and set the ROM addr appropriately
-          //    based on SADDR
-          WAIT_SEN: begin
-             next_rom_addr = SADDR ? STATE_COUNT_CONST : 8'h00;
-             if (SEN) begin
-                next_rom_addr = SADDR ? STATE_COUNT_CONST : 8'h00;
-                // Go on to address the MMCM
-                next_state = ADDRESS;
-             end else begin
-                // Keep waiting for SEN to be asserted
-                next_state = WAIT_SEN;
-             end
-          end
-
-          // Set the address on the MMCM and assert DEN to read the value
-          ADDRESS: begin
-             // Reset the DCM through the reconfiguration
-             next_rst_mmcm  = 1'b1;
-             // Enable a read from the MMCM and set the MMCM address
-             next_den       = 1'b1;
-             next_daddr     = rom_do[38:32];
-
-             // Wait for the data to be ready
-             next_state     = WAIT_A_DRDY;
-          end
-
-          // Wait for DRDY to assert after addressing the MMCM
-          WAIT_A_DRDY: begin
-             if (DRDY) begin
-                // Data is ready, mask out the bits to save
-                next_state = BITMASK;
-             end else begin
-                // Keep waiting till data is ready
-                next_state = WAIT_A_DRDY;
-             end
-          end
-
-          // Zero out the bits that are not set in the mask stored in rom
-          BITMASK: begin
-             // Do the mask
-             next_di     = rom_do[31:16] & DO;
-             // Go on to set the bits
-             next_state  = BITSET;
-          end
-
-          // After the input is masked, OR the bits with calculated value in rom
-          BITSET: begin
-             // Set the bits that need to be assigned
-             next_di           = rom_do[15:0] | DI;
-             // Set the next address to read from ROM
-             next_rom_addr     = rom_addr + 1'b1;
-             // Go on to write the data to the MMCM
-             next_state        = WRITE;
-          end
-
-          // DI is setup so assert DWE, DEN, and RST_MMCM.  Subtract one from the
-          //    state count and go to wait for DRDY.
-          WRITE: begin
-             // Set WE and EN on MMCM
-             next_dwe          = 1'b1;
-             next_den          = 1'b1;
-
-             // Decrement the number of registers left to write
-             next_state_count  = state_count - 1'b1;
-             // Wait for the write to complete
-             next_state        = WAIT_DRDY;
-          end
-
-          // Wait for DRDY to assert from the MMCM.  If the state count is not 0
-          //    jump to ADDRESS (continue reconfiguration).  If state count is
-          //    0 wait for lock.
-          WAIT_DRDY: begin
-             if(DRDY) begin
-                // Write is complete
-                if(state_count > 0) begin
-                   // If there are more registers to write keep going
-                   next_state  = ADDRESS;
-                end else begin
-                   // There are no more registers to write so wait for the MMCM
-                   // to lock
-                   next_state  = WAIT_LOCK;
-                end
-             end else begin
-                // Keep waiting for write to complete
-                next_state     = WAIT_DRDY;
-             end
-          end
-
-          // If in an unknown state reset the machine
-          default: begin
-             next_state = RESTART;
-          end
-       endcase
-    end
-endmodule

sources_1/new/MMCM/mmcme2_drp_func.h

@@ -1,830 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//
-//    Company:          Xilinx
-//    Engineer:         Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
-//                      Updated by Marc Defossez
-//    Date:             19 Sep 2018
-//    Design Name:      MMCME2 DRP
-//    Module Name:      mmcme2_drp_func.h
-//    Version:          1.31
-//    Target Devices:   7 Series
-//    Tool versions:    2014.3 or later
-//    Description:      This header provides the functions necessary to
-//                      calculate the DRP register values for the V6 MMCM.
-//
-//	Revision Notes:
-//      3/12       - Updating lookup_low/lookup_high (CR)
-//			4/13       - Fractional divide function in mmcm_frac_count_calc function. CRS610807
-//			10/24      - Adjusting settings for clarity
-//      19 Sep 18  - Update of CP_RES_LFHF tables -- CR1010263
-//
-//    Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
-//                 INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-//                 PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
-//                 PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-//                 ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-//                 APPLICATION OR STANDARD, XILINX IS MAKING NO
-//                 REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-//                 FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-//                 RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-//                 REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
-//                 EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-//                 RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-//                 INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-//                 REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-//                 FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-//                 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-//                 PURPOSE.
-//
-//                 (c) Copyright 2009-2010 Xilinx, Inc.
-//                 All rights reserved.
-//
-///////////////////////////////////////////////////////////////////////////////
-
-// These are user functions that should not be modified.  Changes to the defines
-// or code within the functions may alter the accuracy of the calculations.
-
-// Define debug to provide extra messages durring elaboration
-`define DEBUG 1
-
-// FRAC_PRECISION describes the width of the fractional portion of the fixed
-//    point numbers.  These should not be modified, they are for development
-//    only
-`define FRAC_PRECISION  10
-// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
-// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
-//    greater than 32
-`define FIXED_WIDTH     32
-
-// This function takes a fixed point number and rounds it to the nearest
-//    fractional precision bit.
-function [`FIXED_WIDTH:1] round_frac
-   (
-      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
-      input [`FIXED_WIDTH:1] decimal,
-
-      // This describes the precision of the fraction, for example a value
-      //    of 1 would modify the fractional so that instead of being a .16
-      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
-      input [`FIXED_WIDTH:1] precision
-   );
-
-   begin
-
-   `ifdef DEBUG
-      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
-   `endif
-      // If the fractional precision bit is high then round up
-      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
-         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
-      end else begin
-         round_frac = decimal;
-      end
-   `ifdef DEBUG
-      $display("round_frac: %h", round_frac);
-   `endif
-   end
-endfunction
-
-// This function calculates high_time, low_time, w_edge, and no_count
-//    of a non-fractional counter based on the divide and duty cycle
-//
-// NOTE: high_time and low_time are returned as integers between 0 and 63
-//    inclusive.  64 should equal 6'b000000 (in other words it is okay to
-//    ignore the overflow)
-function [13:0] mmcm_divider
-   (
-      input [7:0] divide,        // Max divide is 128
-      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
-   );
-
-   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
-      // min/max allowed duty cycle range calc for divide => 64
-   reg [`FIXED_WIDTH:1]    duty_cycle_min;
-   reg [`FIXED_WIDTH:1]    duty_cycle_max;
-
-
-   // High/Low time is initially calculated with a wider integer to prevent a
-   // calculation error when it overflows to 64.
-   reg [6:0]               high_time;
-   reg [6:0]               low_time;
-   reg                     w_edge;
-   reg                     no_count;
-
-   reg [`FIXED_WIDTH:1]    temp;
-
-   begin
-      // Duty Cycle must be between 0 and 1,000
-      if(duty_cycle <=0 || duty_cycle >= 100000) begin
-         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
-         $finish;
-      end
-      if (divide >= 64) begin     // DCD and frequency generation fix if O divide => 64
-           duty_cycle_min = ((divide - 64) * 100_000) / divide;
-           duty_cycle_max = (64.5 / divide) * 100_000;
-           if (duty_cycle > duty_cycle_max)  duty_cycle = duty_cycle_max;
-           if (duty_cycle < duty_cycle_min)  duty_cycle = duty_cycle_min;
-       end
-      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
-      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
-
-   `ifdef DEBUG
-      $display("duty_cycle_fix: %h", duty_cycle_fix);
-   `endif
-
-      // If the divide is 1 nothing needs to be set except the no_count bit.
-      //    Other values are dummies
-      if(divide == 7'h01) begin
-         high_time   = 7'h01;
-         w_edge      = 1'b0;
-         low_time    = 7'h01;
-         no_count    = 1'b1;
-      end else begin
-         temp = round_frac(duty_cycle_fix*divide, 1);
-
-         // comes from above round_frac
-         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
-         // If the duty cycle * divide rounded is .5 or greater then this bit
-         //    is set.
-         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
-
-         // If the high time comes out to 0, it needs to be set to at least 1
-         // and w_edge set to 0
-         if(high_time == 7'h00) begin
-            high_time   = 7'h01;
-            w_edge      = 1'b0;
-         end
-
-         if(high_time == divide) begin
-            high_time   = divide - 1;
-            w_edge      = 1'b1;
-         end
-
-         // Calculate low_time based on the divide setting and set no_count to
-         //    0 as it is only used when divide is 1.
-         low_time    = divide - high_time;
-         no_count    = 1'b0;
-      end
-
-      // Set the return value.
-      mmcm_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
-   end
-endfunction
-
-// This function calculates mx, delay_time, and phase_mux
-//  of a non-fractional counter based on the divide and phase
-//
-// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
-//    is used.
-function [10:0] mmcm_phase
-   (
-      // divide must be an integer (use fractional if not)
-      //  assumed that divide already checked to be valid
-      input [7:0] divide, // Max divide is 128
-
-      // Phase is given in degrees (-360,000 to 360,000)
-      input signed [31:0] phase
-   );
-
-   reg [`FIXED_WIDTH:1] phase_in_cycles;
-   reg [`FIXED_WIDTH:1] phase_fixed;
-   reg [1:0]            mx;
-   reg [5:0]            delay_time;
-   reg [2:0]            phase_mux;
-
-   reg [`FIXED_WIDTH:1] temp;
-
-   begin
-`ifdef DEBUG
-      $display("mmcm_phase-divide:%d,phase:%d",
-         divide, phase);
-`endif
-
-      if ((phase < -360000) || (phase > 360000)) begin
-         $display("ERROR: phase of $phase is not between -360000 and 360000");
-         $finish;
-      end
-
-      // If phase is less than 0, convert it to a positive phase shift
-      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
-      if(phase < 0) begin
-         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
-      end else begin
-         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
-      end
-
-      // Put phase in terms of decimal number of vco clock cycles
-      phase_in_cycles = ( phase_fixed * divide ) / 360;
-
-`ifdef DEBUG
-      $display("phase_in_cycles: %h", phase_in_cycles);
-`endif
-
-
-	 temp  =  round_frac(phase_in_cycles, 3);
-
-	 // set mx to 2'b00 that the phase mux from the VCO is enabled
-	 mx    			=  2'b00;
-	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
-	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
-
-   `ifdef DEBUG
-      $display("temp: %h", temp);
-   `endif
-
-      // Setup the return value
-      mmcm_phase={mx, phase_mux, delay_time};
-   end
-endfunction
-
-// This function takes the divide value and outputs the necessary lock values
-function [39:0] mmcm_lock_lookup
-   (
-      input [6:0] divide // Max divide is 64
-   );
-
-   reg [2559:0]   lookup;
-
-   begin
-      lookup = {
-         // This table is composed of:
-         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
-         40'b00110_00110_1111101000_1111101001_0000000001,
-         40'b00110_00110_1111101000_1111101001_0000000001,
-         40'b01000_01000_1111101000_1111101001_0000000001,
-         40'b01011_01011_1111101000_1111101001_0000000001,
-         40'b01110_01110_1111101000_1111101001_0000000001,
-         40'b10001_10001_1111101000_1111101001_0000000001,
-         40'b10011_10011_1111101000_1111101001_0000000001,
-         40'b10110_10110_1111101000_1111101001_0000000001,
-         40'b11001_11001_1111101000_1111101001_0000000001,
-         40'b11100_11100_1111101000_1111101001_0000000001,
-         40'b11111_11111_1110000100_1111101001_0000000001,
-         40'b11111_11111_1100111001_1111101001_0000000001,
-         40'b11111_11111_1011101110_1111101001_0000000001,
-         40'b11111_11111_1010111100_1111101001_0000000001,
-         40'b11111_11111_1010001010_1111101001_0000000001,
-         40'b11111_11111_1001110001_1111101001_0000000001,
-         40'b11111_11111_1000111111_1111101001_0000000001,
-         40'b11111_11111_1000100110_1111101001_0000000001,
-         40'b11111_11111_1000001101_1111101001_0000000001,
-         40'b11111_11111_0111110100_1111101001_0000000001,
-         40'b11111_11111_0111011011_1111101001_0000000001,
-         40'b11111_11111_0111000010_1111101001_0000000001,
-         40'b11111_11111_0110101001_1111101001_0000000001,
-         40'b11111_11111_0110010000_1111101001_0000000001,
-         40'b11111_11111_0110010000_1111101001_0000000001,
-         40'b11111_11111_0101110111_1111101001_0000000001,
-         40'b11111_11111_0101011110_1111101001_0000000001,
-         40'b11111_11111_0101011110_1111101001_0000000001,
-         40'b11111_11111_0101000101_1111101001_0000000001,
-         40'b11111_11111_0101000101_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100101100_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0100010011_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001,
-         40'b11111_11111_0011111010_1111101001_0000000001
-      };
-
-      // Set lookup_entry with the explicit bits from lookup with a part select
-      mmcm_lock_lookup = lookup[ ((64-divide)*40) +: 40];
-   `ifdef DEBUG
-      $display("lock_lookup: %b", mmcm_lock_lookup);
-   `endif
-   end
-endfunction
-
-// This function takes the divide value and the bandwidth setting of the MMCM
-//  and outputs the digital filter settings necessary.
-function [9:0] mmcm_filter_lookup
-  (
-     input [6:0] divide, // Max divide is 64
-     input [8*9:0] BANDWIDTH
-  );
-
-  reg [639:0] lookup_low;
-  reg [639:0] lookup_low_ss;
-  reg [639:0] lookup_high;
-  reg [639:0] lookup_optimized;
-
-  reg [9:0] lookup_entry;
-
-  begin
-    lookup_low = {
-      // CP_RES_LFHF
-      10'b0010_1111_00, // 1
-      10'b0010_1111_00, // 2
-      10'b0010_1111_00, // 3
-      10'b0010_1111_00, // 4
-      10'b0010_0111_00, // ....
-      10'b0010_1011_00,
-      10'b0010_1101_00,
-      10'b0010_0011_00,
-      10'b0010_0101_00,
-      10'b0010_0101_00,
-      10'b0010_1001_00,
-      10'b0010_1110_00,
-      10'b0010_1110_00,
-      10'b0010_1110_00,
-      10'b0010_1110_00,
-      10'b0010_0001_00,
-      10'b0010_0001_00,
-      10'b0010_0001_00,
-      10'b0010_0110_00,
-      10'b0010_0110_00,
-      10'b0010_0110_00,
-      10'b0010_0110_00,
-      10'b0010_0110_00,
-      10'b0010_0110_00,
-      10'b0010_0110_00,
-      10'b0010_1010_00,
-      10'b0010_1010_00,
-      10'b0010_1010_00,
-      10'b0010_1010_00,
-      10'b0010_1010_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_1100_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00,
-      10'b0010_0010_00, // ....
-      10'b0010_0010_00, // 61
-      10'b0010_0010_00, // 62
-      10'b0010_0010_00, // 63
-      10'b0010_0010_00  // 64
-    };
-
-    lookup_low_ss = {
-      // CP_RES_LFHF
-      10'b0010_1111_11, // 1
-      10'b0010_1111_11, // 2
-      10'b0010_1111_11, // 3
-      10'b0010_1111_11, // 4
-      10'b0010_0111_11, // ....
-      10'b0010_1011_11,
-      10'b0010_1101_11,
-      10'b0010_0011_11,
-      10'b0010_0101_11,
-      10'b0010_0101_11,
-      10'b0010_1001_11,
-      10'b0010_1110_11,
-      10'b0010_1110_11,
-      10'b0010_1110_11,
-      10'b0010_1110_11,
-      10'b0010_0001_11,
-      10'b0010_0001_11,
-      10'b0010_0001_11,
-      10'b0010_0110_11,
-      10'b0010_0110_11,
-      10'b0010_0110_11,
-      10'b0010_0110_11,
-      10'b0010_0110_11,
-      10'b0010_0110_11,
-      10'b0010_0110_11,
-      10'b0010_1010_11,
-      10'b0010_1010_11,
-      10'b0010_1010_11,
-      10'b0010_1010_11,
-      10'b0010_1010_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_1100_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11,
-      10'b0010_0010_11, // ....
-      10'b0010_0010_11, // 61
-      10'b0010_0010_11, // 62
-      10'b0010_0010_11, // 63
-      10'b0010_0010_11  // 64
-    };
-
-    lookup_high = {
-      // CP_RES_LFHF
-      10'b0010_1111_00, // 1
-      10'b0100_1111_00, // 2
-      10'b0101_1011_00, // 3
-      10'b0111_0111_00, // 4
-      10'b1101_0111_00, // ....
-      10'b1110_1011_00,
-      10'b1110_1101_00,
-      10'b1111_0011_00,
-      10'b1110_0101_00,
-      10'b1111_0101_00,
-      10'b1111_1001_00,
-      10'b1101_0001_00,
-      10'b1111_1001_00,
-      10'b1111_1001_00,
-      10'b1111_1001_00,
-      10'b1111_1001_00,
-      10'b1111_0101_00,
-      10'b1111_0101_00,
-      10'b1100_0001_00,
-      10'b1100_0001_00,
-      10'b1100_0001_00,
-      10'b0101_1100_00,
-      10'b0101_1100_00,
-      10'b0101_1100_00,
-      10'b0101_1100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0010_1000_00,
-      10'b0010_1000_00,
-      10'b0010_1000_00,
-      10'b0010_1000_00,
-      10'b0010_1000_00,
-      10'b0111_0001_00,
-      10'b0111_0001_00,
-      10'b0100_1100_00,
-      10'b0100_1100_00,
-      10'b0100_1100_00,
-      10'b0100_1100_00,
-      10'b0110_0001_00,
-      10'b0110_0001_00,
-      10'b0101_0110_00,
-      10'b0101_0110_00,
-      10'b0101_0110_00,
-      10'b0010_0100_00,
-      10'b0010_0100_00,
-      10'b0010_0100_00, // ....
-      10'b0010_0100_00, // 61
-      10'b0100_1010_00, // 62
-      10'b0011_1100_00, // 63
-      10'b0011_1100_00  // 64
-    };
-
-    lookup_optimized = {
-      // CP_RES_LFHF
-      10'b0010_1111_00, // 1
-      10'b0100_1111_00, // 2
-      10'b0101_1011_00, // 3
-      10'b0111_0111_00, // 4
-      10'b1101_0111_00, // ....
-      10'b1110_1011_00,
-      10'b1110_1101_00,
-      10'b1111_0011_00,
-      10'b1110_0101_00,
-      10'b1111_0101_00,
-      10'b1111_1001_00,
-      10'b1101_0001_00,
-      10'b1111_1001_00,
-      10'b1111_1001_00,
-      10'b1111_1001_00,
-      10'b1111_1001_00,
-      10'b1111_0101_00,
-      10'b1111_0101_00,
-      10'b1100_0001_00,
-      10'b1100_0001_00,
-      10'b1100_0001_00,
-      10'b0101_1100_00,
-      10'b0101_1100_00,
-      10'b0101_1100_00,
-      10'b0101_1100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0011_0100_00,
-      10'b0010_1000_00,
-      10'b0010_1000_00,
-      10'b0010_1000_00,
-      10'b0010_1000_00,
-      10'b0010_1000_00,
-      10'b0111_0001_00,
-      10'b0111_0001_00,
-      10'b0100_1100_00,
-      10'b0100_1100_00,
-      10'b0100_1100_00,
-      10'b0100_1100_00,
-      10'b0110_0001_00,
-      10'b0110_0001_00,
-      10'b0101_0110_00,
-      10'b0101_0110_00,
-      10'b0101_0110_00,
-      10'b0010_0100_00,
-      10'b0010_0100_00,
-      10'b0010_0100_00, // ....
-      10'b0010_0100_00, // 61
-      10'b0100_1010_00, // 62
-      10'b0011_1100_00, // 63
-      10'b0011_1100_00  // 64
-    };
-
-    // Set lookup_entry with the explicit bits from lookup with a part select
-    if(BANDWIDTH == "LOW") begin
-      // Low Bandwidth
-      mmcm_filter_lookup = lookup_low[((64-divide)*10) +: 10];
-    end
-    else if (BANDWIDTH == "LOW_SS") begin
-      // low Spread spectrum bandwidth
-      mmcm_filter_lookup = lookup_low_ss[((64-divide)*10) +: 10];
-    end
-    else if (BANDWIDTH == "HIGH") begin
-      // High bandwidth
-      mmcm_filter_lookup = lookup_high[((64-divide)*10) +: 10];
-    end
-    else if (BANDWIDTH == "OPTIMIZED") begin
-      // Optimized bandwidth
-      mmcm_filter_lookup = lookup_optimized[((64-divide)*10) +: 10];
-    end
-
-    `ifdef DEBUG
-        $display("filter_lookup: %b", mmcm_filter_lookup);
-    `endif
-  end
-endfunction
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-function [37:0] mmcm_count_calc
-   (
-      input [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle // Multiplied by 100,000
-   );
-
-   reg [13:0] div_calc;
-   reg [16:0] phase_calc;
-
-   begin
-   `ifdef DEBUG
-      $display("mmcm_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-         divide, phase, duty_cycle);
-   `endif
-
-      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
-      div_calc = mmcm_divider(divide, duty_cycle);
-      // mx[10:9], pm[8:6], dt[5:0]
-      phase_calc = mmcm_phase(divide, phase);
-
-      // Return value is the upper and lower address of counter
-      //    Upper address is:
-      //       RESERVED    [31:26]
-      //       MX          [25:24]
-      //       EDGE        [23]
-      //       NOCOUNT     [22]
-      //       DELAY_TIME  [21:16]
-      //    Lower Address is:
-      //       PHASE_MUX   [15:13]
-      //       RESERVED    [12]
-      //       HIGH_TIME   [11:6]
-      //       LOW_TIME    [5:0]
-
-   `ifdef DEBUG
-      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
-         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
-         div_calc[13], div_calc[12],
-         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
-   `endif
-
-      mmcm_count_calc =
-         {
-            // Upper Address
-            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
-            // Lower Address
-            phase_calc[8:6], 1'b0, div_calc[11:0]
-         };
-   end
-endfunction
-
-
-// This function takes in the divide, phase, and duty cycle
-// setting to calculate the upper and lower counter registers.
-// for fractional multiply/divide functions.
-//
-//
-function [37:0] mmcm_frac_count_calc
-   (
-      input  [7:0] divide, // Max divide is 128
-      input signed [31:0] phase,
-      input [31:0] duty_cycle, // Multiplied by 1,000
-      input [9:0] frac // Multiplied by 1000
-   );
-
-	//Required for fractional divide calculations
-			  reg  [7:0]     lt_frac;
-			  reg  [7:0]     ht_frac;
-
-			  reg            wf_fall_frac;
-			  reg            wf_rise_frac;
-
-			  reg [31:0]     a;
-			  reg  [7:0]     pm_rise_frac_filtered ;
-			  reg  [7:0]     pm_fall_frac_filtered ;
-			  reg  [7:0]     clkout0_divide_int;
-			  reg  [2:0]     clkout0_divide_frac;
-			  reg  [7:0]     even_part_high;
-			  reg  [7:0]     even_part_low;
-			  reg [15:0]     drp_reg1;
-			  reg [15:0]     drp_reg2;
-			  reg  [5:0]     drp_regshared;
-
-			  reg  [7:0]     odd;
-			  reg  [7:0]     odd_and_frac;
-
-			  reg  [7:0]     pm_fall;
-			  reg  [7:0]     pm_rise;
-			  reg  [7:0]     dt;
-			  reg  [7:0]     dt_int;
-			  reg [63:0]     dt_calc;
-
-			  reg  [7:0]     pm_rise_frac;
-			  reg  [7:0]     pm_fall_frac;
-
-			  reg [31:0]     a_per_in_octets;
-			  reg [31:0]     a_phase_in_cycles;
-
-			                 parameter precision = 0.125;
-			  reg [31:0]     phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
-			  reg [31:0]     phase_pos;
-			  reg [31:0]     phase_vco;
-			  reg [31:0]     temp;// changed to 31:0 from 32:1 jt 5/2/11
-			  reg [13:0]     div_calc;
-			  reg [16:0]     phase_calc;
-
-   begin
-	`ifdef DEBUG
-			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
-				divide, phase, duty_cycle);
-	`endif
-
-   //convert phase to fixed
-   if ((phase < -360000) || (phase > 360000)) begin
-      $display("ERROR: phase of $phase is not between -360000 and 360000");
-      $finish;
-   end
-
-
-      // Return value is
-      //    Shared data
-      //       RESERVED     [37:36]
-      //       FRAC_TIME    [35:33]
-      //       FRAC_WF_FALL [32]
-      //    Register 2 - Upper address is:
-      //       RESERVED     [31:26]
-      //       MX           [25:24]
-      //       EDGE         [23]
-      //       NOCOUNT      [22]
-      //       DELAY_TIME   [21:16]
-      //    Register 1 - Lower Address is:
-      //       PHASE_MUX    [15:13]
-      //       RESERVED     [12]
-      //       HIGH_TIME    [11:6]
-      //       LOW_TIME     [5:0]
-
-
-
-	clkout0_divide_frac = frac / 125;
-	clkout0_divide_int = divide;
-
-	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
-	even_part_low = even_part_high;
-
-	odd = clkout0_divide_int - even_part_high - even_part_low;
-	odd_and_frac = (8*odd) + clkout0_divide_frac;
-
-	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
-	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
-
-	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
-	pm_rise = 0; //0
-
-	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
-	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
-
-
-
-	//Calculate phase in fractional cycles
-	a_per_in_octets		= (8 * divide) + (frac / 125) ;
-	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
-	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
-
-	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
-	dt 	= dt_calc[7:0];
-
-	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
-
-	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
-	pm_fall_frac		= pm_fall + pm_rise_frac;
-	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
-
-	div_calc	= mmcm_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
-	phase_calc	= mmcm_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
-
-
-
-      drp_regshared[5:0] = { 2'b11, pm_fall_frac_filtered[2:0], wf_fall_frac};
-      drp_reg2[15:0] = { 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, 4'h0, dt[5:0] };
-      drp_reg1[15:0] = { pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] };
-      mmcm_frac_count_calc[37:0] =   {drp_regshared, drp_reg2, drp_reg1} ;
-
-   `ifdef DEBUG
-      $display("DADDR Reg1 %h", drp_reg1);
-      $display("DADDR Reg2 %h", drp_reg2);
-      $display("DADDR Reg Shared %h", drp_regshared);
-      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
-   `endif
-
-   end
-endfunction

sources_1/new/MMCM/top_mmcme2.tcl

@@ -1,691 +0,0 @@
-##################################################################################################
-# This TCL script is used to do basic project setup and clarify the DRP settings
-#
-# XAPP888 TCL commands:
-#       xapp888_create_project <> - Basic project setup. Adjust as needed
-#       xapp888_help <>           - Descriptions of added TCL commands
-#
-# XAPP888 TCL DRP Settings:
-#       xapp888_drp_settings <CLKFBOUT_MULT>  <DIVCLK_DIVIDE> <PHASE> <HIGH|LOW|high|low>
-#            - Displays & Returns the ordered pairs of DRP addresses & Data
-#
-#       xapp888_drp_clkout <DIVIDE>  <Duty Cycle e.g. 0.5> <Phase e.g.11.25> <CLKOUT0 to CLKOUT6>
-#            - Displays & Returns the ordered pairs of DRP addresses & Data
-#
-#       xapp888_merge_drp_clkout <list>
-#            - Returns the ordered DRP addresses/data merging fractional address 07 & 13
-#
-# Revision History:
-#       10/22/14 - Added TCL DRP commands
-#        3/17/16 - Added min/max duty cycle checks
-#        7/10/18 - Fixed duty cycles for divide > 64
-#       19 Sep 2018 - Add new lookup tables for CP RES LFHF
-#       05 Oct 2018 - Cosmetic updates to text.
-#
-##################################################################################################
-
-
-
-proc xapp888_create_project {} {
-create_project xapp888_mmcme2  -force xapp888_mmcme2 -part xc7k325tffg900-2
-add_files -norecurse {mmcme2_drp_func.h mmcme2_drp.v top_mmcme2.v  top_mmcme2.xdc}
-import_files -force -norecurse
-import_files -fileset sim_1 -norecurse {top_mmcme2_tb.v}
-update_compile_order -fileset sim_1
-}
-proc xapp888_merge_drp {list} {
-    set count_07 0
-    set merge_07 ""
-    set count_13 0
-    set merge_13 ""
-    set drp_merged ""
-    for {set i 0} { $i <= [expr [llength $list]/2] } {incr i} {
-        if {[string match [lindex $list [expr $i*2]] 07]} {
-            incr count_07; set merge_07 "$merge_07 [lindex $list [expr 2*$i + 1] ]"
-        } elseif {[string match [lindex $list [expr $i*2]] 13]} {
-            incr count_13; set merge_13 "$merge_13 [lindex $list [expr 2*$i + 1] ]"
-        } else {
-            set drp_merged "$drp_merged [lindex $list [expr $i * 2]] [lindex $list [expr $i * 2 + 1]]"
-        }
-    }
-
-    if {[llength $merge_07] > 1 } {set drp_07_merged [format %x [expr 0x[lindex $merge_07 0] | 0x[lindex $merge_07 1]]]} else {set drp_07_merged [lindex $merge_07 0]}
-    if {[llength $merge_13] > 1} {set drp_13_merged  [format %x [expr 0x[lindex $merge_13 0] | 0x[lindex $merge_13 1]]]} else {set drp_13_merged [lindex $merge_13 0]}
-    if {$count_07 >2} {
-            puts "ERROR: Too many shared addresses for 07. Only the first 2 terms are being marged. $merge_07"
-    } elseif {$count_07 > 0} {
-        set drp_merged "$drp_merged  07 $drp_07_merged"
-    }
-    if {$count_13 >2} {
-        puts "ERROR: Too many shared addresses for 13. Only the first 2 terms are being merged. $merge_13"
-    } elseif {$count_13 > 0} {
-        set drp_merged "$drp_merged 13 $drp_13_merged"
-    }
-    puts "$list has been changed to $drp_merged"
-    return $drp_merged
-}
-proc xapp888_drp_clkout_frac {divide phase} {
-    set divide_frac [expr fmod($divide, 1)]
-    set divide_frac_8ths [scan [expr $divide_frac * 8] %d]
-    set divide_int [scan [expr floor($divide)] %d]
-
-    set even_part_high [scan [expr floor($divide_int / 2)] %d]
-    set even_part_low $even_part_high
-
-    set odd [expr $divide_int - $even_part_high - $even_part_low]
-    set odd_and_frac [scan [expr 8 * $odd + $divide_frac_8ths] %d]
-
-    if {$odd_and_frac <=9} {set lt_frac [expr $even_part_high - 1]} else {set lt_frac $even_part_high}
-    if {$odd_and_frac <=8} {set ht_frac [expr $even_part_low - 1]} else {set ht_frac $even_part_low}
-
-    set pmfall [scan [expr $odd * 4 + floor($divide_frac_8ths / 2)] %d]
-    set pmrise 0
-    set dt [scan [expr floor($phase * $divide / 360)] %d]
-    set pmrise [scan [expr floor( 8 * (($phase * $divide /360 ) - $dt)+ 0.5 )] %d]
-    set pmfall [scan [expr $pmfall + $pmrise] %d]
-
-    if {$odd_and_frac <=9 && $odd_and_frac >=2 || $divide == 2.125} {set wf_fall 1} else {set wf_fall 0}
-    if {$odd_and_frac <=8 && $odd_and_frac >=1} {set wf_rise 1} else {set wf_rise 0}
-
-    set dt [scan [expr $dt + floor($pmrise / 8)] %d]
-    set pmrise [scan [expr fmod($pmrise , 8)] %d]
-    set pmfall [scan [expr fmod($pmfall , 8)] %d]
-
-    set reg1       "[xapp888_dec2bin $pmrise 3]1[xapp888_dec2bin $ht_frac 6][xapp888_dec2bin $lt_frac 6]"
-    set reg2       "0[xapp888_dec2bin $divide_frac_8ths 3]1[expr $wf_rise]0000[xapp888_dec2bin $dt 6]"
-    set regshared  "00[xapp888_dec2bin $pmfall 3][expr $wf_fall]"
-
-    return "$reg1 $reg2 $regshared "
-}
-
-proc xapp888_drp_clkout {divide dutycycle phase clkout} {
-    set clkout_lower [string tolower $clkout]
-        switch -glob -- $clkout_lower {
-            clkout0  {  set daddr_reg1 08
-                        set daddr_reg2 09
-                        }
-            clkout1  {  set daddr_reg1 0A
-                        set daddr_reg2 0B
-                        }
-            clkout2  {  set daddr_reg1 0C
-                        set daddr_reg2 0D
-                        }
-            clkout3  {  set daddr_reg1 0E
-                        set daddr_reg2 0F
-                        }
-            clkout4  {  set daddr_reg1 10
-                        set daddr_reg2 11
-                        }
-            clkout5  {  set daddr_reg1 06
-                        set daddr_reg2 07
-                        }
-            clkout6  {  set daddr_reg1 12
-                        set daddr_reg2 13
-                        }
-    }
-
-        if {$phase < 0} {set phase [expr 360 + $phase]}
-
-# Calculate phase for PM and O counter.
-# Round counter phase setting up if => 0.5 to closes possible phase
-        set phase_in_cycles [expr $phase / 360.0 * $divide]
-        set phasecycles_dec [expr (8 * $phase_in_cycles)]
-        set phasecycles_int [expr int($phasecycles_dec)]
-        set phasecycles_rem [expr ($phasecycles_dec - $phasecycles_int )]
-        if {$phasecycles_rem >= 0.5} {set phasecycles_int [expr ($phasecycles_int + 1)]}
-        set phasecycles [expr int($phasecycles_int / 8)]
-        set pmphasecycles [expr ($phasecycles_int - $phasecycles * 8)]
-# Duty cycle stuff
-         if {$divide < 64} {
-            set min_dc [expr 1.0 / $divide]
-            set max_dc [expr ($divide - 0.5) / $divide]
-       } else {
-            set min_dc [expr ($divide - 64.0) / $divide]
-            set max_dc [expr (64 + 0.5) / $divide]
-       }
-        if {$dutycycle < $min_dc} {puts "\n\tWARNING: Min duty cycle violation $dutycycle < $min_dc\n\t         Changing dutycycle to $min_dc\n"; set dutycycle $min_dc}
-        if {$dutycycle > $max_dc} {puts "\n\tWARNING: Max duty cycle is $dutycycle > $max_dc\n\t         Changing dutycycle to $max_dc\n"; set dutycycle $max_dc}
-
-    puts "Requested phase is: $phase; Given divide=$divide then phase increments in [format %f [expr 45.000/$divide ]  ];  "
-    #puts "DT will be $phasecycles, PM will be $pmphasecycles"
-    #puts "Phase will be shifted by VCO period * $phasecycles.[expr 1000*$pmphasecycles / 8]"
-    #puts "Phase will be shifted by [format %f [expr $phasecycles * 360.000 / $divide]] + [format %f  [expr $pmphasecycles * 45.000 / $divide]] = [format %f [expr ( $phasecycles * 360.000 / $divide) + ($pmphasecycles * 45.000 / $divide) ] ]"
-    puts "Requested Phase is: $phase; Actual: [format %f [expr ( $phasecycles * 360.000 / $divide) + ($pmphasecycles * 45.000 / $divide) ] ];  "
-
-#puts "[expr $pmphasecycles * 45 / $divide]"
-
-
-        set ht [scan [expr int($dutycycle * [expr ($divide ) ])] %d]
-        set lt [scan [expr $divide - $ht] %d]
-        set even_high [scan [expr $divide / 2] %d]
-        set odd [expr $divide - $even_high * 2]
-
-        if {$divide == 1} {
-             set drp_reg1 "[xapp888_bin2hex [binary scan [binary format I $pmphasecycles] B32 var;string range $var end-2 end]1000001000001]"
-             set drp_reg2 "[xapp888_bin2hex 00000000[expr $odd]1[xapp888_dec2bin $phasecycles 6] ]"
-             puts "DADDR_$daddr_reg1: $drp_reg1\t-[string toupper $clkout] Register 1"
-             puts "DADDR_$daddr_reg2: $drp_reg2\t-[string toupper $clkout] Register 2"
-             return "$daddr_reg1 $drp_reg1 $daddr_reg2 $drp_reg2"
-        } elseif {[expr fmod($divide,1)] == 0  }  {
-             set drp_reg1 "[xapp888_bin2hex [binary scan [binary format I $pmphasecycles] B32 var;string range $var end-2 end]1[xapp888_dec2bin4ltht $ht][xapp888_dec2bin4ltht $lt]]"
-             set drp_reg2 "[xapp888_bin2hex 00000000[expr $odd]0[xapp888_dec2bin $phasecycles 6] ]"
-             puts "DADDR_$daddr_reg1: $drp_reg1\t-[string toupper $clkout] Register 1"
-             puts "DADDR_$daddr_reg2: $drp_reg2\t-[string toupper $clkout] Register 2"
-             return "$daddr_reg1 $drp_reg1 $daddr_reg2 $drp_reg2"
-        } elseif {[string tolower $clkout] == "clkout0" } {
-            set drp_frac_registers [xapp888_drp_clkout_frac $divide $phase ]
-            set drp_reg1 [xapp888_bin2hex [lindex $drp_frac_registers 0]]
-            set drp_reg2 [xapp888_bin2hex [lindex $drp_frac_registers 1]]
-            set drp_regshared [xapp888_bin2hex [lindex $drp_frac_registers 2]0000000000]
-            puts "DADDR_$daddr_reg2: $drp_reg2\t-[string toupper $clkout] Register 1"
-            puts "DADDR_$daddr_reg1: $drp_reg1\t-[string toupper $clkout] Register 2"
-            puts "DADDR_07: $drp_regshared\t-[string toupper $clkout] Register Shared with CLKOUT5"
-            return "08 $drp_reg1 09 $drp_reg2 07 $drp_regshared"
-        }  else {puts "\nERROR: Fractional divide setting only supported for CLKOUT0. Output clock set to [string toupper $clkout] \n"
-    }
-}
-
-proc xapp888_drp_calc_m {divide phase} {
-    set phasecycles [expr int(($divide*$phase)/360)]
-    set pmphase [expr ($phase - ($phasecycles *360)/$divide)]
-    set pmphasecycles [scan [expr int(($pmphase *$divide)/ 45)] %d]
-
-    set ht [scan [expr ($divide ) / 2] %d]
-    set lt [scan [expr $divide - $ht] %d]
-    set odd [expr $lt - $ht]
-    set daddr_reg1 14
-    set daddr_reg2 15
-    set daddr_regshared 13
-    if {$divide == 1} {
-            set drp_reg1 "[xapp888_bin2hex [binary scan [binary format I $pmphasecycles] B32 var;string range $var end-2 end]1000001000001]"
-            set drp_reg2 "[xapp888_bin2hex 00000000[expr $odd]1[xapp888_dec2bin $phasecycles 6] ]"
-            puts "DADDR_$daddr_reg1: $drp_reg1\t-CLKFBOUT Register 1- "
-            puts "DADDR_$daddr_reg2: $drp_reg2\t-CLKFBOUT Register 2- "
-            return "$daddr_reg1 $drp_reg1 $daddr_reg2 $drp_reg2"
-    } elseif {$divide >=64  } {
-        puts "DADDR_14: ERROR: M must be 2 to 64\t-CLKFBOUT Register 2-"
-        puts "DADDR_15: ERROR: M must be 2 to 64\t-CLKFBOUT Register 2-\tNOTE: The calculations are only for the non-fractional settings. CLKFBOUT must use an integer divide value for these DRP settings to work"
-        return "14 ERROR 15 ERROR "
-    } elseif {[expr fmod($divide,1)] > 0} {
-        set drp_frac_registers [xapp888_drp_clkout_frac $divide $phase ]
-        set drp_reg1 [xapp888_bin2hex [lindex $drp_frac_registers 0]]
-        set drp_reg2 [xapp888_bin2hex [lindex $drp_frac_registers 1]]
-        set drp_regshared [xapp888_bin2hex [lindex $drp_frac_registers 2]0000000000]
-        puts "DADDR_$daddr_reg1: $drp_reg1\t-CLKFBOUT Register 1- "
-        puts "DADDR_$daddr_reg2: $drp_reg2\t-CLKFBOUT Register 2- "
-        puts "DADDR_$daddr_regshared: $drp_regshared\t-CLKFBOUT Register Shared with CLKOUT6- "
-        return "$daddr_reg1  $drp_reg1 $daddr_reg2  $drp_reg2 13 $drp_regshared"
-    } else {
-        puts "DADDR_$daddr_reg1: [xapp888_bin2hex [binary scan [binary format I $pmphasecycles] B32 var;string range $var end-2 end]1[xapp888_dec2bin4ltht $ht][xapp888_dec2bin4ltht $lt]]\t-CLKFBOUT Register 1- "
-        puts "DADDR_$daddr_reg2: [xapp888_bin2hex 00000000[expr $odd]0[binary scan [binary format I $phasecycles] B32 var;string range $var end-5 end] ]\t-CLKFBOUT Register 2- "
-        return "$daddr_reg1  [xapp888_bin2hex [binary scan [binary format I $pmphasecycles] B32 var;string range $var end-2 end]1[xapp888_dec2bin4ltht $ht][xapp888_dec2bin4ltht $lt]] $daddr_reg2  [xapp888_bin2hex 00000000[expr $odd]0[binary scan [binary format I $phasecycles] B32 var;string range $var end-5 end] ]"
-    }
-}
-
-proc xapp888_drp_calc_d {divide} {
-    set ht [scan [expr ($divide ) / 2] %d]
-    set lt [scan [expr $divide - $ht] %d]
-    if {$divide == 1} {
-        puts "DADDR_16: [xapp888_bin2hex 0001000001000001]\t-DIVCLK Register $divide-"
-        return "16 [xapp888_bin2hex 0001000001000001]"
-    } elseif { $divide > 19} {
-        puts "DADDR_16: ERROR D must be 1 to 19"
-        return "16 ERROR"
-    } else {
-        puts "DADDR_16: [xapp888_bin2hex 0000[xapp888_dec2bin4ltht $ht][xapp888_dec2bin4ltht $lt] ]\t-DIVCLK Register $divide-" }
-        return "16 [xapp888_bin2hex 0000[xapp888_dec2bin4ltht $ht][xapp888_dec2bin4ltht $lt] ] "
-}
-
-proc xapp888_dec2bin4ltht {dec} {
-     binary scan [binary format c $dec] B* bin
-     string range $bin end-5 end
-}
-
-proc xapp888_cpres {div bw} {
-    #CP_RES_LFHF
-    set div [scan $div %d]
-    set bw_lower [string tolower $bw]
-    if {$bw_lower == "low" } then {
-        switch -glob -- $div {
-            1   {set CP 0010 ; set RES 1111 ; set LFHF 00 }
-            2   {set CP 0010 ; set RES 1111 ; set LFHF 00 }
-            3   {set CP 0010 ; set RES 1111 ; set LFHF 00 }
-            4   {set CP 0010 ; set RES 1111 ; set LFHF 00 }
-            5   {set CP 0010 ; set RES 0111 ; set LFHF 00 }
-            6   {set CP 0010 ; set RES 1011 ; set LFHF 00 }
-            7   {set CP 0010 ; set RES 1101 ; set LFHF 00 }
-            8   {set CP 0010 ; set RES 0011 ; set LFHF 00 }
-            9   {set CP 0010 ; set RES 0101 ; set LFHF 00 }
-            10  {set CP 0010 ; set RES 0101 ; set LFHF 00 }
-            11  {set CP 0010 ; set RES 1001 ; set LFHF 00 }
-            12  {set CP 0010 ; set RES 1110 ; set LFHF 00 }
-            13  {set CP 0010 ; set RES 1110 ; set LFHF 00 }
-            14  {set CP 0010 ; set RES 1110 ; set LFHF 00 }
-            15  {set CP 0010 ; set RES 1110 ; set LFHF 00 }
-            16  {set CP 0010 ; set RES 0001 ; set LFHF 00 }
-            17  {set CP 0010 ; set RES 0001 ; set LFHF 00 }
-            18  {set CP 0010 ; set RES 0001 ; set LFHF 00 }
-            19  {set CP 0010 ; set RES 0110 ; set LFHF 00 }
-            20  {set CP 0010 ; set RES 0110 ; set LFHF 00 }
-            21  {set CP 0010 ; set RES 0110 ; set LFHF 00 }
-            22  {set CP 0010 ; set RES 0110 ; set LFHF 00 }
-            23  {set CP 0010 ; set RES 0110 ; set LFHF 00 }
-            24  {set CP 0010 ; set RES 0110 ; set LFHF 00 }
-            25  {set CP 0010 ; set RES 0110 ; set LFHF 00 }
-            26  {set CP 0010 ; set RES 1010 ; set LFHF 00 }
-            27  {set CP 0010 ; set RES 1010 ; set LFHF 00 }
-            28  {set CP 0010 ; set RES 1010 ; set LFHF 00 }
-            29  {set CP 0010 ; set RES 1010 ; set LFHF 00 }
-            30  {set CP 0010 ; set RES 1010 ; set LFHF 00 }
-            31  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            32  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            33  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            34  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            35  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            36  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            37  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            38  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            39  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            40  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            41  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            42  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            43  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            44  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            45  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            46  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            47  {set CP 0010 ; set RES 1100 ; set LFHF 00 }
-            48  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            49  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            50  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            51  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            52  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            53  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            54  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            55  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            56  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            57  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            58  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            59  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            60  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            61  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            62  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            63  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-            64  {set CP 0010 ; set RES 0010 ; set LFHF 00 }
-        }
-    } elseif {$bw_lower == "low_ss"} then {
-        switch -glob -- $div {
-            1   {set CP 0010 ; set RES 1111 ; set LFHF 11 }
-            2   {set CP 0010 ; set RES 1111 ; set LFHF 11 }
-            3   {set CP 0010 ; set RES 1111 ; set LFHF 11 }
-            4   {set CP 0010 ; set RES 1111 ; set LFHF 11 }
-            5   {set CP 0010 ; set RES 0111 ; set LFHF 11 }
-            6   {set CP 0010 ; set RES 1011 ; set LFHF 11 }
-            7   {set CP 0010 ; set RES 1101 ; set LFHF 11 }
-            8   {set CP 0010 ; set RES 0011 ; set LFHF 11 }
-            9   {set CP 0010 ; set RES 0101 ; set LFHF 11 }
-            10  {set CP 0010 ; set RES 0101 ; set LFHF 11 }
-            11  {set CP 0010 ; set RES 1001 ; set LFHF 11 }
-            12  {set CP 0010 ; set RES 1110 ; set LFHF 11 }
-            13  {set CP 0010 ; set RES 1110 ; set LFHF 11 }
-            14  {set CP 0010 ; set RES 1110 ; set LFHF 11 }
-            15  {set CP 0010 ; set RES 1110 ; set LFHF 11 }
-            16  {set CP 0010 ; set RES 0001 ; set LFHF 11 }
-            17  {set CP 0010 ; set RES 0001 ; set LFHF 11 }
-            18  {set CP 0010 ; set RES 0001 ; set LFHF 11 }
-            19  {set CP 0010 ; set RES 0110 ; set LFHF 11 }
-            20  {set CP 0010 ; set RES 0110 ; set LFHF 11 }
-            21  {set CP 0010 ; set RES 0110 ; set LFHF 11 }
-            22  {set CP 0010 ; set RES 0110 ; set LFHF 11 }
-            23  {set CP 0010 ; set RES 0110 ; set LFHF 11 }
-            24  {set CP 0010 ; set RES 0110 ; set LFHF 11 }
-            25  {set CP 0010 ; set RES 0110 ; set LFHF 11 }
-            26  {set CP 0010 ; set RES 1010 ; set LFHF 11 }
-            27  {set CP 0010 ; set RES 1010 ; set LFHF 11 }
-            28  {set CP 0010 ; set RES 1010 ; set LFHF 11 }
-            29  {set CP 0010 ; set RES 1010 ; set LFHF 11 }
-            30  {set CP 0010 ; set RES 1010 ; set LFHF 11 }
-            31  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            32  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            33  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            34  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            35  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            36  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            37  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            38  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            39  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            40  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            41  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            42  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            43  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            44  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            45  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            46  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            47  {set CP 0010 ; set RES 1100 ; set LFHF 11 }
-            48  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            49  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            50  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            51  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            52  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            53  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            54  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            55  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            56  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            57  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            58  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            59  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            60  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            61  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            62  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            63  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-            64  {set CP 0010 ; set RES 0010 ; set LFHF 11 }
-        }
-    } elseif {$bw_lower == "high"} then {
-        switch -glob -- $div {
-            1   {set CP 0010 ; set RES 1111 ; set LFHF 00 }
-            2   {set CP 0100 ; set RES 1111 ; set LFHF 00 }
-            3   {set CP 0101 ; set RES 1011 ; set LFHF 00 }
-            4   {set CP 0111 ; set RES 0111 ; set LFHF 00 }
-            5   {set CP 1101 ; set RES 0111 ; set LFHF 00 }
-            6   {set CP 1110 ; set RES 1011 ; set LFHF 00 }
-            7   {set CP 1110 ; set RES 1101 ; set LFHF 00 }
-            8   {set CP 1111 ; set RES 0011 ; set LFHF 00 }
-            9   {set CP 1110 ; set RES 0101 ; set LFHF 00 }
-            10  {set CP 1111 ; set RES 0101 ; set LFHF 00 }
-            11  {set CP 1111 ; set RES 1001 ; set LFHF 00 }
-            12  {set CP 1101 ; set RES 0001 ; set LFHF 00 }
-            13  {set CP 1111 ; set RES 1001 ; set LFHF 00 }
-            14  {set CP 1111 ; set RES 1001 ; set LFHF 00 }
-            15  {set CP 1111 ; set RES 1001 ; set LFHF 00 }
-            16  {set CP 1111 ; set RES 1001 ; set LFHF 00 }
-            17  {set CP 1111 ; set RES 0101 ; set LFHF 00 }
-            18  {set CP 1111 ; set RES 0101 ; set LFHF 00 }
-            19  {set CP 1100 ; set RES 0001 ; set LFHF 00 }
-            20  {set CP 1100 ; set RES 0001 ; set LFHF 00 }
-            21  {set CP 1100 ; set RES 0001 ; set LFHF 00 }
-            22  {set CP 0101 ; set RES 1100 ; set LFHF 00 }
-            23  {set CP 0101 ; set RES 1100 ; set LFHF 00 }
-            24  {set CP 0101 ; set RES 1100 ; set LFHF 00 }
-            25  {set CP 0101 ; set RES 1100 ; set LFHF 00 }
-            26  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            27  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            28  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            29  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            30  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            31  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            32  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            33  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            34  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            35  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            36  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            37  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            38  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            39  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            40  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            41  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            42  {set CP 0010 ; set RES 1000 ; set LFHF 00 }
-            43  {set CP 0010 ; set RES 1000 ; set LFHF 00 }
-            44  {set CP 0010 ; set RES 1000 ; set LFHF 00 }
-            45  {set CP 0010 ; set RES 1000 ; set LFHF 00 }
-            46  {set CP 0010 ; set RES 1000 ; set LFHF 00 }
-            47  {set CP 0111 ; set RES 0001 ; set LFHF 00 }
-            48  {set CP 0111 ; set RES 0001 ; set LFHF 00 }
-            49  {set CP 0100 ; set RES 1100 ; set LFHF 00 }
-            50  {set CP 0100 ; set RES 1100 ; set LFHF 00 }
-            51  {set CP 0100 ; set RES 1100 ; set LFHF 00 }
-            52  {set CP 0100 ; set RES 1100 ; set LFHF 00 }
-            53  {set CP 0110 ; set RES 0001 ; set LFHF 00 }
-            54  {set CP 0110 ; set RES 0001 ; set LFHF 00 }
-            55  {set CP 0101 ; set RES 0110 ; set LFHF 00 }
-            56  {set CP 0101 ; set RES 0110 ; set LFHF 00 }
-            57  {set CP 0101 ; set RES 0110 ; set LFHF 00 }
-            58  {set CP 0010 ; set RES 0100 ; set LFHF 00 }
-            59  {set CP 0010 ; set RES 0100 ; set LFHF 00 }
-            60  {set CP 0010 ; set RES 0100 ; set LFHF 00 }
-            61  {set CP 0010 ; set RES 0100 ; set LFHF 00 }
-            62  {set CP 0100 ; set RES 1010 ; set LFHF 00 }
-            63  {set CP 0011 ; set RES 1100 ; set LFHF 00 }
-            64  {set CP 0011 ; set RES 1100 ; set LFHF 00 }
-        }
-    } else {
-      # OPTIMIZED
-        switch -glob -- $div {
-            1   {set CP 0010 ; set RES 1111 ; set LFHF 00 }
-            2   {set CP 0100 ; set RES 1111 ; set LFHF 00 }
-            3   {set CP 0101 ; set RES 1011 ; set LFHF 00 }
-            4   {set CP 0111 ; set RES 0111 ; set LFHF 00 }
-            5   {set CP 1101 ; set RES 0111 ; set LFHF 00 }
-            6   {set CP 1110 ; set RES 1011 ; set LFHF 00 }
-            7   {set CP 1110 ; set RES 1101 ; set LFHF 00 }
-            8   {set CP 1111 ; set RES 0011 ; set LFHF 00 }
-            9   {set CP 1110 ; set RES 0101 ; set LFHF 00 }
-            10  {set CP 1111 ; set RES 0101 ; set LFHF 00 }
-            11  {set CP 1111 ; set RES 1001 ; set LFHF 00 }
-            12  {set CP 1101 ; set RES 0001 ; set LFHF 00 }
-            13  {set CP 1111 ; set RES 1001 ; set LFHF 00 }
-            14  {set CP 1111 ; set RES 1001 ; set LFHF 00 }
-            15  {set CP 1111 ; set RES 1001 ; set LFHF 00 }
-            16  {set CP 1111 ; set RES 1001 ; set LFHF 00 }
-            17  {set CP 1111 ; set RES 0101 ; set LFHF 00 }
-            18  {set CP 1111 ; set RES 0101 ; set LFHF 00 }
-            19  {set CP 1100 ; set RES 0001 ; set LFHF 00 }
-            20  {set CP 1100 ; set RES 0001 ; set LFHF 00 }
-            21  {set CP 1100 ; set RES 0001 ; set LFHF 00 }
-            22  {set CP 0101 ; set RES 1100 ; set LFHF 00 }
-            23  {set CP 0101 ; set RES 1100 ; set LFHF 00 }
-            24  {set CP 0101 ; set RES 1100 ; set LFHF 00 }
-            25  {set CP 0101 ; set RES 1100 ; set LFHF 00 }
-            26  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            27  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            28  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            29  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            30  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            31  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            32  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            33  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            34  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            35  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            36  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            37  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            38  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            39  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            40  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            41  {set CP 0011 ; set RES 0100 ; set LFHF 00 }
-            42  {set CP 0010 ; set RES 1000 ; set LFHF 00 }
-            43  {set CP 0010 ; set RES 1000 ; set LFHF 00 }
-            44  {set CP 0010 ; set RES 1000 ; set LFHF 00 }
-            45  {set CP 0010 ; set RES 1000 ; set LFHF 00 }
-            46  {set CP 0010 ; set RES 1000 ; set LFHF 00 }
-            47  {set CP 0111 ; set RES 0001 ; set LFHF 00 }
-            48  {set CP 0111 ; set RES 0001 ; set LFHF 00 }
-            49  {set CP 0100 ; set RES 1100 ; set LFHF 00 }
-            50  {set CP 0100 ; set RES 1100 ; set LFHF 00 }
-            51  {set CP 0100 ; set RES 1100 ; set LFHF 00 }
-            52  {set CP 0100 ; set RES 1100 ; set LFHF 00 }
-            53  {set CP 0110 ; set RES 0001 ; set LFHF 00 }
-            54  {set CP 0110 ; set RES 0001 ; set LFHF 00 }
-            55  {set CP 0101 ; set RES 0110 ; set LFHF 00 }
-            56  {set CP 0101 ; set RES 0110 ; set LFHF 00 }
-            57  {set CP 0101 ; set RES 0110 ; set LFHF 00 }
-            58  {set CP 0010 ; set RES 0100 ; set LFHF 00 }
-            59  {set CP 0010 ; set RES 0100 ; set LFHF 00 }
-            60  {set CP 0010 ; set RES 0100 ; set LFHF 00 }
-            61  {set CP 0010 ; set RES 0100 ; set LFHF 00 }
-            62  {set CP 0100 ; set RES 1010 ; set LFHF 00 }
-            63  {set CP 0011 ; set RES 1100 ; set LFHF 00 }
-            64  {set CP 0011 ; set RES 1100 ; set LFHF 00 }
-          }
-    }
-        puts "DADDR_4E: [xapp888_bin2hex "[string index $CP 0]00[string range $CP 1 2]00[string index $CP 3]00000000"]\t-Filter Register 1: M set to $div with $bw bandwidth-"
-        puts "DADDR_4F: [xapp888_bin2hex "[string index $RES 0]00[string range $RES 1 2]00[string index $RES 3][string index $LFHF 0]00[string index $LFHF 1]0000"]\t-Filter Register 2: M set to $div with $bw bandwidth-"
-        return "4F [xapp888_bin2hex "[string index $RES 0]00[string range $RES 1 2]00[string index $RES 3][string index $LFHF 0]00[string index $LFHF 1]0000"] 4E [xapp888_bin2hex "[string index $CP 0]00[string range $CP 1 2]00[string index $CP 3]00000000"]"
-}
-
-proc xapp888_locking {div} {
-        # LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
-        set div [scan $div %d]
-        switch -glob -- $div {
-            1 {set LockRefDly 00110 ; set LockFBDly 00110 ; set LockCnt 0111101000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            2 {set LockRefDly 00110 ; set LockFBDly 00110 ; set LockCnt 0111101000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            3 {set LockRefDly 01000 ; set LockFBDly 01000 ; set LockCnt 0111101000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            4 {set LockRefDly 01011 ; set LockFBDly 01011 ; set LockCnt 0111101000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            5 {set LockRefDly 01110 ; set LockFBDly 01110 ; set LockCnt 0111101000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            6 {set LockRefDly 10001 ; set LockFBDly 10001 ; set LockCnt 0111101000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            7 {set LockRefDly 10011 ; set LockFBDly 10011 ; set LockCnt 0111101000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            8 {set LockRefDly 10110 ; set LockFBDly 10110 ; set LockCnt 0111101000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            9 {set LockRefDly 11001 ; set LockFBDly 11001 ; set LockCnt 0111101000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            10 {set LockRefDly 11100 ; set LockFBDly 11100 ; set LockCnt 0111101000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            11 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0110000100 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            12 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0100111001 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            13 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0111101110 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            14 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0110111100 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            15 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0110001010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            16 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0101110001 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            17 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0100111111 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            18 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0100100110 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            19 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0100001101 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            20 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011110100 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            21 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011011011 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            22 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011000010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            23 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0010101001 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            24 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0010010000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            25 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0010010000 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            26 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0001110111 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            27 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0001011110 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            28 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0001011110 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            29 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0001000101 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            30 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0001000101 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            31 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0000101100 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            32 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0000101100 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            33 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0000101100 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            34 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0000010011 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            35 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0000010011 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            36 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0000010011 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            37 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            38 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            39 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            40 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            41 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            42 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            43 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            44 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            45 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            46 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            47 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            48 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            49 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            50 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            51 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            52 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            53 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            54 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            55 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            56 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            57 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            58 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            59 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            60 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            61 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            62 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            63 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-            64 {set LockRefDly 11111 ; set LockFBDly 11111 ; set LockCnt 0011111010 ;set LockSatHigh 0111101001 ;set UnlockCnt 0000000001}
-         }
-
-        puts "DADDR_28: FFFF\t-Power register leaving all interpolators on - "
-        puts "DADDR_18: [xapp888_bin2hex 000000$LockCnt]\t-Lock Register 1: for M set to $div -"
-        puts "DADDR_19: [xapp888_bin2hex 0$LockFBDly$UnlockCnt]\t-Lock Register 2: for M set to $div"
-        puts "DADDR_1A: [xapp888_bin2hex 0$LockRefDly$LockSatHigh]\t-Lock Register 3: for M set to $div"
-        return "28 FFFF 18 [xapp888_bin2hex 000000$LockCnt] 19 [xapp888_bin2hex 0$LockFBDly$UnlockCnt] 1A [xapp888_bin2hex 0$LockRefDly$LockSatHigh]"
-}
-
-proc xapp888_bin2hex {bits} {
-    set abits ""
-    for {set i 0} {$i <= [expr 15 - [string length $bits]] } {incr i} {
-        append abits 0}
-    append abits "$bits"
-    set binValue [binary format B16 $abits]
-    binary scan $binValue H4 hex
-    return $hex
-    }
-
-proc xapp888_hex2bin {hex} {
-    for {set i 0} { $i <= [string length $hex]} { incr i 1} {
-        append convert2bin [xapp888_hex2bin_ [string range $hex $i $i] ]
-        }
-    return $convert2bin
-
-}
-proc xapp888_hex2bin_ {hex} {
-        return [string map -nocase {
-            0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111
-            8 1000 9 1001 a 1010 b 1011 c 1100 d 1101 e 1110 f 1111
-            } $hex ]
-
-}
-
-proc xapp888_dec2hex {value} {
-   # Creates a 16 bit hex number from a signed decimal number
-   # Replace all non-decimal characters
-   regsub -all {[^0-9\.\-]} $value {} newtemp
-   set value [string trim $newtemp]
-   if {$value < 65535 && $value >= 0} {
-      set tempvalue [format "%#010X" [expr $value]]
-      return [string range $tempvalue 6 9]
-   } elseif {$value < 0} {
-      puts "Unsigned value"
-      return "0000"
-   } else {
-      puts "Violates 16 bit range"
-      return "FFFF"
-   }
-}
-proc xapp888_drp_settings {m d phase bw} {
-    if {$phase < 0} {set phase [expr 360 + $phase]}
-    set data_m [xapp888_drp_calc_m $m $phase]
-    set data_d [xapp888_drp_calc_d $d]
-    set data_cpres [xapp888_cpres $m $bw]
-    set data_locking [xapp888_locking $m]
-    return "$data_m $data_d $data_cpres $data_locking"
-}
-
-proc xapp888_dec2bin {dec bits} {return [binary scan [binary format I $dec] B32 var;string range $var end-[expr $bits-1] end]}
-
-proc xapp888_dec2bindt {dec} {
-        return [string map { 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111} $dec]
-}
-
-proc xapp888_help {} {
-    puts "\n\n-----------------------------------------------------------------------------------------------\
-    \nXAPP888 TCL commands:\
-    \n      xapp888_create_project <> - Basic project setup. Adjust as needed\
-    \n      xapp888_help <>           - Descriptions of added TCL commands\
-    \n\nXAPP888 TCL DRP Settings:\n   The following TCL commands are being added to give example calculations\
-    \n   for drp programming values for MMCME2 (7 series). For other architectures care\
-    \n   should be taken due to VCO and programming addresses. This script can be altered\
-    \n   to adjust for those differences but exact settings should be reviewed.\
-    \n\n   Also please note that this is a subset of the full programming options.\
-    \n   Fine phase shifting and dynamic phase shifting is not directly supported by\
-    \n   these scripts.\
-    \n\n      xapp888_drp_settings <CLKFBOUT_MULT>  <DIVCLK_DIVIDE> <PHASE> <BANDWIDTH>\
-    \n           - BANDWIDTH can be: LOW, LOW_SS, HIGH, OPTIMIZED (case insensitive). \
-    \n           - Displays & Returns the ordered pairs of DRP addresses & Data
-    \n      xapp888_drp_clkout <DIVIDE>  <Duty Cycle e.g. 0.5> <Phase e.g.11.25> <CLKOUT0 to CLKOUT6> \
-    \n           - Displays & Returns the ordered pairs of DRP addresses & Data
-    \n      xapp888_merge_drp_clkout <list>\
-    \n           - Returns the ordered DRP addresses/data merging fractional address 07 & 13
-    \n\n   For Example:\
-    \n\t   xapp888_drp_settings <m> <d> <phase> <bw>;\
-    \n\t   xapp888_drp_clkout <div> <dc> <phase> clkout0;\
-    \n\t   xapp888_drp_clkout <div> <dc> <phase> clkout1;\
-    \n\t   xapp888_drp_clkout <div> <dc> <phase> clkout2;\
-    \n\t   xapp888_drp_clkout <div> <dc> <phase> clkout3;\
-    \n\t   xapp888_drp_clkout <div> <dc> <phase> clkout4;\
-    \n\t   xapp888_drp_clkout <div> <dc> <phase> clkout5;\
-    \n\t   xapp888_drp_clkout <div> <dc> <phase> clkout6;\
-    \n\n   To show how to use the xapp888_merg_drp command the following is an arbitrary example"
-    puts {          set drp "[xapp888_drp_settings 2.125 2 0 high]"}
-    puts {          set drp "$drp [xapp888_drp_clkout 3.75 0.5 90 clkout0]"}
-    puts {          for {set i 1} {$i <= 6} {incr i} {set drp "$drp [xapp888_drp_clkout 7 0.5 90 clkout$i]"} }
-    puts {          xapp888_merge_drp $drp}
-    puts "-----------------------------------------------------------------------------------------------"
-}
-xapp888_help

sources_1/new/MMCM/top_mmcme2.v

@@ -1,400 +0,0 @@
-//------------------------------------------------------------------------------------------
-//   ____  ____
-//  /   /\/   /
-// /___/  \  /
-// \   \   \/    � Copyright 2019 Xilinx, Inc. All rights reserved.
-//  \   \        This file contains confidential and proprietary information of Xilinx, Inc.
-//  /   /        and is protected under U.S. and international copyright and other
-// /___/   /\    intellectual property laws.
-// \   \  /  \
-//  \___\/\___\
-//
-//-------------------------------------------------------------------------------------------
-// Device:              7-Series
-// Author:              Tatsukawa, Kruger, Defossez
-// Entity Name:         top_mmcme2
-// Purpose:             This is a basic demonstration of the MMCM_DRP
-//                      connectivity to the MMCM_ADV.
-// Tools:               Vivado_2019.1 or newer
-// Limitations:
-//
-// Vendor:              Xilinx Inc.
-// Version:             1.40
-// Filename:            top_mmcme2.v
-// Date Created:        30-Jul-2014
-// Date Last Modified:  25-Jun-2019
-//-------------------------------------------------------------------------------------------
-// Disclaimer:
-//		This disclaimer is not a license and does not grant any rights to the materials
-//		distributed herewith. Except as otherwise provided in a valid license issued to you
-//		by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
-//		ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
-//		WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
-//		TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
-//		PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
-//		negligence, or under any other theory of liability) for any loss or damage of any
-//		kind or nature related to, arising under or in connection with these materials,
-//		including for any direct, or any indirect, special, incidental, or consequential
-//		loss or damage (including loss of data, profits, goodwill, or any type of loss or
-//		damage suffered as a result of any action brought by a third party) even if such
-//		damage or loss was reasonably foreseeable or Xilinx had been advised of the
-//		possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//		Xilinx products are not designed or intended to be fail-safe, or for use in any
-//		application requiring fail-safe performance, such as life-support or safety devices
-//		or systems, Class III medical devices, nuclear facilities, applications related to
-//		the deployment of airbags, or any other applications that could lead to death,
-//		personal injury, or severe property or environmental damage (individually and
-//		collectively, "Critical Applications"). Customer assumes the sole risk and
-//		liability of any use of Xilinx products in Critical Applications, subject only to
-//		applicable laws and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
-//
-// Contact:    e-mail  hotline@xilinx.com        phone   + 1 800 255 7778
-//-------------------------------------------------------------------------------------------
-// Revision History:
-//  Rev: 30-Apr-2014 - Tatsukawa
-//      Initial code release
-//  Rev: 25-Jun-2019 - Defossez
-//      Add possibility to register the LOCKED signal.
-//-------------------------------------------------------------------------------------------
-//
-`timescale 1ps/1ps
-//
-//-------------------------------------------------------------------------------------------
-// Entity pin description
-//-------------------------------------------------------------------------------------------
-// Inputs
-//      SSTEP:      Start a reconfiguration. It should only be pulsed for one clock cycle.
-//      STATE:      Determines which state the MMCM_ADV will be reconfigured to. A value
-//                  of 0 correlates to state 1, and a value of 1 correlates to state 2.
-//      RST:        RST will reset the entire reference design including the MMCM_ADV.
-//      CLKIN:      Clock for the MMCM_ADV CLKIN as well as the clock for the MMCM_DRP module
-//      SRDY:       Pulses for one clock cycle after the MMCM_ADV is locked and the
-//                  MMCM_DRP module is ready to start another re-configuration.
-// Outputs
-//      LOCKED_OUT: MMCM is locked after configuration or reconfiguration.
-//      CLK0OUT:    These are the clock outputs from the MMCM_ADV.
-//      CLK1OUT:    These are the clock outputs from the MMCM_ADV.
-//      CLK2OUT:    These are the clock outputs from the MMCM_ADV.
-//      CLK3OUT:    These are the clock outputs from the MMCM_ADV.
-//      CLK4OUT:    These are the clock outputs from the MMCM_ADV.
-//      CLK5OUT:    These are the clock outputs from the MMCM_ADV.
-//      CLK6OUT:    These are the clock outputs from the MMCM_ADV.
-//-------------------------------------------------------------------------------------------
-module top_mmcme2
-    (
-        input    SSTEP,
-        input    STATE,
-        input    RST,
-        input    CLKIN,
-        input   [7:0] ClkDiv1_i,
-        input   [7:0] ClkDiv2_i,
-        input   [7:0] ClkDiv3_i,
-        input   [7:0] ClkDiv4_i,
-        input   [7:0] ClkDiv5_i,
-        input   [7:0] ClkDiv6_i,
-        input   [7:0] ClkDiv7_i,
-        output   SRDY,
- 		output 	 LOCKED_OUT,
-        output   CLK0OUT,
-        output   CLK1OUT,
-        output   CLK2OUT,
-        output   CLK3OUT,
-        output   CLK4OUT,
-        output   CLK5OUT,
-        output   CLK6OUT
-    );
-//-------------------------------------------------------------------------------------------
-// These signals are used as direct connections between the MMCM_ADV and the
-// MMCM_DRP.
-(* mark_debug = "true" *) wire [15:0]    di;
-(* mark_debug = "true" *) wire [6:0]     daddr;
-(* mark_debug = "true" *) wire [15:0]    dout;
-(* mark_debug = "true" *) wire           den;
-(* mark_debug = "true" *) wire           dwe;
-wire            dclk;
-wire            rst_mmcm;
-wire            drdy;
-reg				current_state;
-reg [7:0]		sstep_int ;
-reg				init_drp_state = 1;
-// These signals are used for the BUFG's necessary for the design.
-wire            CLKIN_ibuf;
-wire            clkin_bufgout;
-wire            clkfb_bufgout;
-wire            clkfb_bufgin;
-wire            clk0_bufgin;
-wire            clk0_bufgout;
-wire            clk1_bufgin;
-wire            clk1_bufgout;
-wire            clk2_bufgin;
-wire            clk2_bufgout;
-wire            clk3_bufgin;
-wire            clk3_bufgout;
-wire            clk4_bufgin;
-wire            clk4_bufgout;
-wire            clk5_bufgin;
-wire            clk5_bufgout;
-wire            clk6_bufgin;
-wire            clk6_bufgout;
-wire            LOCKED;
-//-------------------------------------------------------------------------------------------
-assign CLKIN_ibuf = CLKIN;
-//
-BUFG BUFG_IN    (.O (clkin_bufgout),    .I (CLKIN_ibuf));
-BUFG BUFG_FB    (.O (clkfb_bufgout),    .I (clkfb_bufgin));
-BUFG BUFG_CLK0  (.O (clk0_bufgout),     .I (clk0_bufgin));
-BUFG BUFG_CLK1  (.O (clk1_bufgout),     .I (clk1_bufgin));
-BUFG BUFG_CLK2  (.O (clk2_bufgout),     .I (clk2_bufgin));
-BUFG BUFG_CLK3  (.O (clk3_bufgout),     .I (clk3_bufgin));
-BUFG BUFG_CLK4  (.O (clk4_bufgout),     .I (clk4_bufgin));
-BUFG BUFG_CLK5  (.O (clk5_bufgout),     .I (clk5_bufgin));
-BUFG BUFG_CLK6  (.O (clk6_bufgout),     .I (clk6_bufgin));
-//
-// ODDR registers used to output clocks
-ODDR ODDR_CLK0 (.Q(CLK0OUT), .C(clk0_bufgout), .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(RST), .S(1'b0));
-ODDR ODDR_CLK1 (.Q(CLK1OUT), .C(clk1_bufgout), .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(RST), .S(1'b0));
-ODDR ODDR_CLK2 (.Q(CLK2OUT), .C(clk2_bufgout), .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(RST), .S(1'b0));
-ODDR ODDR_CLK3 (.Q(CLK3OUT), .C(clk3_bufgout), .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(RST), .S(1'b0));
-ODDR ODDR_CLK4 (.Q(CLK4OUT), .C(clk4_bufgout), .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(RST), .S(1'b0));
-ODDR ODDR_CLK5 (.Q(CLK5OUT), .C(clk5_bufgout), .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(RST), .S(1'b0));
-ODDR ODDR_CLK6 (.Q(CLK6OUT), .C(clk6_bufgout), .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(RST), .S(1'b0));
-//
-// MMCM_ADV that reconfiguration will take place on
-//
-//  BANDWIDTH:              : "HIGH", "LOW" or "OPTIMIZED"
-//  DIVCLK_DIVIDE           : Value from 1 to 106
-//  CLKFBOUT_MULT_F         : Value from 2 to 64
-//  CLKFBOUT_PHASE          :
-//  CLKFBOUT_USE_FINE_PS    : "TRUE" or "FALSE",
-//  CLKIN1_PERIOD           : Value from 0.968 to 100.000. Set the period (ns) of input clocks
-//  REF_JITTER1             :
-//  CLKIN2_PERIOD           :
-//  REF_JITTER2             :
-//  CLKOUT parameters:
-//  DIVIDE                  : Value from 1 to 128
-//  DUTY_CYCLE              : 0.01 to 0.99 - This is dependent on the divide value.
-//  PHASE                   : 0.0 to 360.0 - This is dependent on the divide value.
-//  USE_FINE_PS             : TRUE or FALSE
-//  Misc parameters
-//  COMPENSATION
-//  STARTUP_WAIT
-//
-MMCME2_ADV #(
-   .BANDWIDTH           ("OPTIMIZED"),
-   .DIVCLK_DIVIDE       (1),
-   .CLKFBOUT_MULT_F     (13),
-   .CLKFBOUT_PHASE      (0.0),
-   .CLKFBOUT_USE_FINE_PS("FALSE"),
-   .CLKIN1_PERIOD       (8.130081300813),
-   .REF_JITTER1         (0.010),
-   .CLKIN2_PERIOD       (10.000),
-   .REF_JITTER2         (0.010),
-   .CLKOUT0_DIVIDE_F    (6),
-   .CLKOUT0_DUTY_CYCLE  (0.5),
-   .CLKOUT0_PHASE       (0.0),
-   .CLKOUT0_USE_FINE_PS ("FALSE"),
-   .CLKOUT1_DIVIDE      (6),
-   .CLKOUT1_DUTY_CYCLE  (0.5),
-   .CLKOUT1_PHASE       (0.0),
-   .CLKOUT1_USE_FINE_PS ("FALSE"),
-   .CLKOUT2_DIVIDE      (6),
-   .CLKOUT2_DUTY_CYCLE  (0.5),
-   .CLKOUT2_PHASE       (0.0),
-   .CLKOUT2_USE_FINE_PS ("FALSE"),
-   .CLKOUT3_DIVIDE      (6),
-   .CLKOUT3_DUTY_CYCLE  (0.5),
-   .CLKOUT3_PHASE       (0.0),
-   .CLKOUT3_USE_FINE_PS ("FALSE"),
-   .CLKOUT4_DIVIDE      (6),
-   .CLKOUT4_DUTY_CYCLE  (0.5),
-   .CLKOUT4_PHASE       (0.0),
-   .CLKOUT4_USE_FINE_PS ("FALSE"),
-   .CLKOUT4_CASCADE     ("FALSE"),
-   .CLKOUT5_DIVIDE      (6),
-   .CLKOUT5_DUTY_CYCLE  (0.5),
-   .CLKOUT5_PHASE       (0.0),
-   .CLKOUT5_USE_FINE_PS ("FALSE"),
-   .CLKOUT6_DIVIDE      (6),
-   .CLKOUT6_DUTY_CYCLE  (0.5),
-   .CLKOUT6_PHASE       (0.0),
-   .CLKOUT6_USE_FINE_PS ("FALSE"),
-   .COMPENSATION        ("ZHOLD"),
-   .STARTUP_WAIT        ("FALSE")
-) mmcme2_test_inst (
-   .CLKFBOUT            (clkfb_bufgin),
-   .CLKFBOUTB           (),
-   .CLKFBSTOPPED        (),
-   .CLKINSTOPPED        (),
-//    .ClkDiv1_i           (ClkDiv1_i),
-//    .ClkDiv2_i           (ClkDiv2_i),
-//    .ClkDiv3_i           (ClkDiv3_i),
-//    .ClkDiv4_i           (ClkDiv4_i),
-//    .ClkDiv5_i           (ClkDiv5_i),
-//    .ClkDiv6_i           (ClkDiv6_i),
-//    .ClkDiv7_i           (ClkDiv7_i),
-
-   .CLKOUT0             (clk0_bufgin),
-   .CLKOUT0B            (),
-   .CLKOUT1             (clk1_bufgin),
-   .CLKOUT1B            (),
-   .CLKOUT2             (clk2_bufgin),
-   .CLKOUT2B            (),
-   .CLKOUT3             (clk3_bufgin),
-   .CLKOUT3B            (),
-   .CLKOUT4             (clk4_bufgin),
-   .CLKOUT5             (clk5_bufgin),
-   .CLKOUT6             (clk6_bufgin),
-   .DO                  (dout),
-   .DRDY                (drdy),
-   .DADDR               (daddr),
-   .DCLK                (dclk),
-   .DEN                 (den),
-   .DI                  (di),
-   .DWE                 (dwe),
-   .LOCKED              (LOCKED),
-   .CLKFBIN             (clkfb_bufgout),
-   .CLKIN1              (clkin_bufgout),
-   .CLKIN2              (),
-   .CLKINSEL            (1'b1),
-   .PSDONE              (),
-   .PSCLK               (1'b0),
-   .PSEN                (1'b0),
-   .PSINCDEC            (1'b0),
-   .PWRDWN              (1'b0),
-   .RST                 (rst_mmcm)
-);
-// MMCM_DRP instance that will perform the reconfiguration operations
-mmcme2_drp #(
-    // Register the LOCKED signal with teh MMCME3_ADV input clock.
-    // The LOCKED_IN (LOCKED from the MMCME3_ADV) is fed into a register and then
-    // passed the LOCKED_OUT when REGISTER_LOCKED is set to "Reg" or when set to
-    // "NoReg" LOCKED_IN is just passed on to LOCKED_OUT without being registered.
-    .REGISTER_LOCKED       ("Reg"),
-    // Use the registered LOCKED signal from the MMCME3 also for the DRP state machine.
-    .USE_REG_LOCKED        ("No"),
-    // Possible combination of above two parameters:
-    // | REGISTER_LOCKED | USE_REG_LOCKED |                                            |
-    // |-----------------|----------------|--------------------------------------------|
-    // |      "NoReg"    |     "No"       | LOCKED is just passed through mmcme3_drp   |
-    // |                 |                | and is used as is with the state machine   |
-    // |      "NoReg"    |     "Yes"      | NOT ALLOWED                                |
-    // |       "Reg"     |     "No"       | LOCKED is registered but the unregistered  |
-    // |                 |                | version is used for the state machine.     |
-    // |       "Reg"     |     "Yes"      | LOCKED is registered and the registered    |
-    // |                 |                | version is also used by the state machine. |
-    //
-    //***********************************************************************
-    // State 1 Parameters - These are for the first reconfiguration state.
-    //***********************************************************************
-    // Set the multiply to 6.0 with 0 deg phase offset, optimized bandwidth, input divide of 1
-    .S1_CLKFBOUT_MULT(13),
-    .S1_CLKFBOUT_PHASE(000_000),
-    .S1_CLKFBOUT_FRAC(000),
-    .S1_CLKFBOUT_FRAC_EN(0),
-    .S1_BANDWIDTH("OPTIMIZED"),
-    .S1_DIVCLK_DIVIDE(1),
-    // Set clockout0 to a divide of 6.0 (unity gain), 0 deg phase offset, 50/50 duty cycle
-    .S1_CLKOUT0_DIVIDE(6),
-    .S1_CLKOUT0_PHASE(000_000),
-    .S1_CLKOUT0_DUTY(50000),
-    .S1_CLKOUT0_FRAC(000),
-    .S1_CLKOUT0_FRAC_EN(0),
-    // Set clockout 1 to a divide of 1, 0 deg phase offset, 50/50 duty cycle
-    .S1_CLKOUT1_DIVIDE(1),
-    .S1_CLKOUT1_PHASE(000_000),
-    .S1_CLKOUT1_DUTY(50000),
-    // Set clockout 2 to a divide of 2, 0 deg phase offset, 50/50 duty cycle
-    .S1_CLKOUT2_DIVIDE(2),
-    .S1_CLKOUT2_PHASE(000_000),
-    .S1_CLKOUT2_DUTY(50000),
-    // Set clockout 3 to a divide of 3, 0 deg phase offset, 50/50 duty cycle
-    .S1_CLKOUT3_DIVIDE(3),
-    .S1_CLKOUT3_PHASE(000_000),
-    .S1_CLKOUT3_DUTY(50000),
-    // Set clockout 4 to a divide of 4, 0 deg phase offset, 50/50 duty cycle
-    .S1_CLKOUT4_DIVIDE(4),
-    .S1_CLKOUT4_PHASE(000_000),
-    .S1_CLKOUT4_DUTY(50000),
-    // Set clockout 5 to a divide of 5, 0 deg phase offset, 50/50 duty cycle
-    .S1_CLKOUT5_DIVIDE(5),
-    .S1_CLKOUT5_PHASE(000_000),
-    .S1_CLKOUT5_DUTY(50000),
-    // Set clockout 6 to a divide of 10, 0 deg phase offset, 50/50 duty cycle
-    .S1_CLKOUT6_DIVIDE(10),
-    .S1_CLKOUT6_PHASE(000_000),
-    .S1_CLKOUT6_DUTY(50000),
-    //***********************************************************************
-    // State 2 Parameters - These are for the second reconfiguration state.
-    //***********************************************************************
-    .S2_CLKFBOUT_MULT(13),
-    .S2_CLKFBOUT_PHASE(000_000),
-    .S2_CLKFBOUT_FRAC(000),
-    .S2_CLKFBOUT_FRAC_EN(0),
-    .S2_BANDWIDTH("OPTIMIZED"),
-    .S2_DIVCLK_DIVIDE(1),
-    // Set clockout 0 to a divide of 4.750, 0 deg phase offset, 50/50 duty cycle
-    .S2_CLKOUT0_DIVIDE(7),
-    .S2_CLKOUT0_PHASE(000_000),
-    .S2_CLKOUT0_DUTY(50000),
-    .S2_CLKOUT0_FRAC(000),
-    .S2_CLKOUT0_FRAC_EN(0),
-    // Set clockout 1 to a divide of 1, 45.0 deg phase offset, 50/50 duty cycle
-    .S2_CLKOUT1_DIVIDE(1),
-    .S2_CLKOUT1_PHASE(045_000),
-    .S2_CLKOUT1_DUTY(50000),
-    // Set clock out 0 to a divide of 1, 90.0 deg phase offset, 50/50 duty cycle
-    .S2_CLKOUT2_DIVIDE(1),
-    .S2_CLKOUT2_PHASE(090_000),
-    .S2_CLKOUT2_DUTY(90000),
-    // Set clockout3 to a divide of 1, 135.0 deg phase offset, 50/50 duty cycle
-    .S2_CLKOUT3_DIVIDE(1),
-    .S2_CLKOUT3_PHASE(135_000),
-    .S2_CLKOUT3_DUTY(50000),
-    // Set clockout4 to a divide of 1, 180.0 deg phase offset, 50/50 duty cycle
-    .S2_CLKOUT4_DIVIDE(1),
-    .S2_CLKOUT4_PHASE(180_000),
-    .S2_CLKOUT4_DUTY(50000),
-    // Set clockout5 to a divide of 1, 225.0 deg phase offset, 50/50 duty cycle
-    .S2_CLKOUT5_DIVIDE(1),
-    .S2_CLKOUT5_PHASE(225_000),
-    .S2_CLKOUT5_DUTY(50000),
-    // Set clockout6 to a divide of 1, 270.0 deg phase offset, 50/50 duty cycle
-    .S2_CLKOUT6_DIVIDE(1),
-    .S2_CLKOUT6_PHASE(270_000),
-    .S2_CLKOUT6_DUTY(50000)
-) mmcme2_drp_inst (
-    .SADDR              (STATE),
-    .SEN                (sstep_int[0]),
-    .RST                (RST),
-    .SRDY               (SRDY),
-    .SCLK               (clkin_bufgout),
-    .DO                 (dout),
-    .DRDY               (drdy),
-    .LOCK_REG_CLK_IN    (clkin_bufgout),
-    .LOCKED_IN          (LOCKED),
-    .DWE                (dwe),
-    .DEN                (den),
-    .DADDR              (daddr),
-    .DI                 (di),
-    .DCLK               (dclk),
-    .RST_MMCM           (rst_mmcm),
-    .LOCKED_OUT         (LOCKED_OUT)
-);
-   //***********************************************************************
-   // Additional STATE and SSTEP logic for push buttons and switches
-   //***********************************************************************
-// The following logic is not required but is being used to allow the DRP
-// circuitry work more effectively with boards that use toggle switches or
-// buttons that may not adhere to the single clock requirement.
-//
-// Only start DRP after initial lock and when STATE has changed
-always @ (posedge clkin_bufgout or posedge SSTEP)
-    if (SSTEP) sstep_int <=  8'h80;
-    else sstep_int <= {1'b0, sstep_int[7:1]};
-//
-//-------------------------------------------------------------------------------------------
-endmodule

sources_1/new/MMCM/top_mmcme2.xdc

@@ -1,2 +0,0 @@
-create_clock -period 10.000 -name CLKIN -waveform {0.000 5.000} [get_ports CLKIN]
-

sources_1/new/MMCM/top_mmcme2_tb.v

@@ -1,140 +0,0 @@
-//------------------------------------------------------------------------------------------
-//   ____  ____
-//  /   /\/   /
-// /___/  \  /
-// \   \   \/    � Copyright 2019 Xilinx, Inc. All rights reserved.
-//  \   \        This file contains confidential and proprietary information of Xilinx, Inc.
-//  /   /        and is protected under U.S. and international copyright and other
-// /___/   /\    intellectual property laws.
-// \   \  /  \
-//  \___\/\___\
-//
-//-------------------------------------------------------------------------------------------
-// Device:              7-Series
-// Author:              Tatsukawa, Defossez
-// Entity Name:         top_mmcme2_tb
-// Purpose:            This is a basic demonstration that drives the MMCM_DRP
-//                      ports to trigger two reconfiguration events, one for
-//                      each state.
-// Tools:               QuestaSim_10.7d or newer
-// Limitations:
-//
-// Vendor:              Xilinx Inc.
-// Version:             0.01
-// Filename:            top_mmcme2_tb.v
-// Date Created:        30-Jul-2014
-// Date Last Modified:  26-Jun-2019
-//-------------------------------------------------------------------------------------------
-// Disclaimer:
-//        This disclaimer is not a license and does not grant any rights to the materials
-//        distributed herewith. Except as otherwise provided in a valid license issued to you
-//        by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
-//        ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
-//        WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
-//        TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
-//        PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
-//        negligence, or under any other theory of liability) for any loss or damage of any
-//        kind or nature related to, arising under or in connection with these materials,
-//        including for any direct, or any indirect, special, incidental, or consequential
-//        loss or damage (including loss of data, profits, goodwill, or any type of loss or
-//        damage suffered as a result of any action brought by a third party) even if such
-//        damage or loss was reasonably foreseeable or Xilinx had been advised of the
-//        possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//        Xilinx products are not designed or intended to be fail-safe, or for use in any
-//        application requiring fail-safe performance, such as life-support or safety devices
-//        or systems, Class III medical devices, nuclear facilities, applications related to
-//        the deployment of airbags, or any other applications that could lead to death,
-//        personal injury, or severe property or environmental damage (individually and
-//        collectively, "Critical Applications"). Customer assumes the sole risk and
-//        liability of any use of Xilinx products in Critical Applications, subject only to
-//        applicable laws and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
-//
-// Contact:    e-mail  hotline@xilinx.com        phone   + 1 800 255 7778
-//-------------------------------------------------------------------------------------------
-// Revision History:
-//  Rev: 30-Jul-20149 - Tatsukawa
-//      Initial version of this design - source code.
-//  Rev: 26-Jun-2019 - Defossez
-//      Make sure the simulation works after modifications to the design.
-//-------------------------------------------------------------------------------------------
-//
-`timescale 1ps / 1ps
-//-------------------------------------------------------------------------------------------
-module top_tb  ();
-    reg SSTEP, RST, CLKin, STATE;
-    wire SRDY, clk0out, clk1out, clk2out, clk3out, clk4out, clk5out, clk6out;
-//-------------------------------------------------------------------------------------------
-    top_mmcme2 U1
-    (
-        .SSTEP      (SSTEP),
-        .STATE      (STATE),
-        .RST        (RST),
-        .CLKIN      (CLKin),
-        .SRDY       (SRDY),
-        .LOCKED_OUT (locked),
-        .CLK0OUT    (clk0out),
-        .CLK1OUT    (clk1out),
-        .CLK2OUT    (clk2out),
-        .CLK3OUT    (clk3out),
-        .CLK4OUT    (clk4out),
-        .CLK5OUT    (clk5out),
-        .CLK6OUT    (clk6out)
-    );
-//-------------------------------------------------------------------------------------------
-    localparam one_ns = 1000;
-    localparam clock_period = 8.13;
-    parameter [1:0]    STARTUP = 0, STATE0 = 1, STATE1 = 2, UNDEFINED = 3;
-    reg [1:0] SM = STARTUP ;
-
-always @ (posedge CLKin)
-    begin
-        if (RST)
-               SM = STARTUP;
-        else
-            case (SM)
-                STARTUP:
-                    begin
-                        SM = STATE0;
-                        SSTEP=1'b0;
-                        STATE=1'b0;
-                    end
-                STATE0:
-                    begin
-                        if (locked == 1 )
-                            begin
-                                #(1 * clock_period * one_ns) SSTEP= 1'b1;
-                                #(1 * clock_period * one_ns) SSTEP=1'b0;
-                                #(2000 * clock_period * one_ns) SM = STATE1 ;
-                                STATE=1'b1;
-                            end
-                    end
-                STATE1:
-                    begin
-                        if (locked == 1 )
-                            begin
-                                #(1 * clock_period * one_ns) SSTEP= 1'b1;
-                                #(1 * clock_period * one_ns) SSTEP=1'b0;
-                                #(100 * clock_period * one_ns) SM = STATE0;
-                                STATE=1'b0;
-                            end
-                    end
-                UNDEFINED:   SM= STARTUP;
-            endcase
-        end
-//
-    initial
-        begin
-                CLKin = 0;
-                RST = 1;
-                #50000 RST = 0;
-        end
-    always
-        # (clock_period * one_ns / 2) CLKin = ~CLKin;
-//
-//-------------------------------------------------------------------------------------------
-endmodule
-//

sources_1/new/QuadSPI/InitRst.v

@@ -1,104 +0,0 @@
-module InitRst (
-    clk_i,
-    signal_o
-);
-
-//================================================================================
-//
-//  FUNCTIONS
-//
-//================================================================================
-
-    function integer bit_num;
-        input integer value;
-        begin
-            bit_num = 0;
-            while (value > 0) begin
-                value   = value >> 1;
-                bit_num = bit_num + 1;
-            end
-        end
-    endfunction
-
-//================================================================================
-//
-//  PARAMETER/LOCALPARAM
-//
-//================================================================================
-
-    parameter   DELAY_VALUE     = 20;
-    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
-
-//================================================================================
-//
-//  PORTS
-//
-//================================================================================
-
-    input           clk_i;
-    output  reg     signal_o;
-
-//================================================================================
-//
-//  STATE MACHINE STATES
-//
-//================================================================================
-
-    localparam      SM_RST_S    = 1'b0;
-    localparam      SM_DONE_S   = 1'b1;
-
-//================================================================================
-//
-//  REG/WIRE
-//
-//================================================================================
-
-    reg                         curr_state  = SM_RST_S;
-    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
-    reg                         delay_flag  = 1'b0;
-
-    reg                         next_state;
-    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
-    reg                         signal_next;
-
-//================================================================================
-//
-//  CODING
-//
-//================================================================================
-
-initial begin
-    curr_state  = SM_RST_S;
-    delay_cnt   = {DELAY_CNT_W{1'b0}};
-    signal_o    = 1'b1;
-    delay_flag  = 1'b0;
-end
-
-always @(posedge clk_i) begin
-    curr_state  <= next_state;
-    delay_cnt   <= delay_cnt_next;
-    signal_o    <= signal_next;
-    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
-end
-
-always @(*) begin
-    next_state      = SM_RST_S;
-    delay_cnt_next  = delay_cnt;
-    signal_next     = 1'b1;
-    case(curr_state)
-        SM_RST_S    : begin
-            if (delay_flag) begin
-                next_state      = SM_DONE_S;
-            end else begin
-                next_state      = SM_RST_S;
-                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
-            end
-        end
-        SM_DONE_S   : begin
-            signal_next = 1'b0;
-            next_state  = SM_DONE_S;
-        end
-    endcase
-end
-
-endmodule

sources_1/new/SRAM/QuadSPIm.v

@@ -5,24 +5,21 @@ module QuadSPIm(
     input Start_i,
     input CPHA_i,
     input [31:0] SPIdata,
-	input SpiDataVal_i,
+    input SpiDataVal_i,
     input SELST_i,
     input [1:0] WidthSel_i,
     input  LAG_i,
     input  LEAD_i,
     input EndianSel_i,
     input [5:0] Stop_i,
-    input PulsePol_i,
-
-
+    input PulsePol_i,   
     output reg Mosi0_i,
     output reg Mosi1_i,
     output reg Mosi2_i,
     output reg Mosi3_i,
     output reg  Sck_o,
     output reg Val_o,
-    output Ss_o
-
+    output Ss_o 
 );
 //================================================================================
 //  REG/WIRE
@@ -34,8 +31,8 @@ reg [31:0] trCnt;
 reg valReg;
 reg lineBusy;
 reg [5:0] ssCnt;
-reg Ss;
-reg SSr;
+reg ss;
+reg ssR;
 reg [31:0] spiDataR;
 reg oldDataFlag;
 reg [7:0] mosiReg0;
@@ -45,15 +42,11 @@ reg [7:0] mosiReg3;
 reg [3:0] ssNum;
 reg [2:0] delayCnt;
 reg stopFlag;
-
-wire SsPol = SELST_i ? Ss : ~Ss;
-
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
 
-assign Ss_o = Ss; 
-// assign Val_o = (trCnt < 1 ) ?!lineBusy:valReg;
+assign Ss_o = ss; 
 //================================================================================
 //  CODING
 //================================================================================	
@@ -61,11 +54,7 @@ assign Ss_o = Ss;
 
 always @(*) begin 
     if (Start_i) begin 
-        // if (trCnt < 1) begin 
-        //     Val_o = !lineBusy;
-        // end
-        // else begin 
-            Val_o = valReg;
+        Val_o = valReg;
     end
     else begin 
         Val_o = 1'b0;
@@ -76,7 +65,7 @@ end
 
 always @(*) begin 
     if (SELST_i) begin 
-        if (!Ss) begin 
+        if (!ss) begin 
             lineBusy = 1'b1;
         end
         else begin 
@@ -84,7 +73,7 @@ always @(*) begin
         end
     end
     else begin 
-        if (Ss) begin 
+        if (ss) begin 
             lineBusy = 1'b1;
         end
         else begin 
@@ -130,7 +119,7 @@ always @(posedge Clk_i) begin
     end
     else begin
         if (SELST_i) begin 
-            if (Ss && !SSr) begin 
+            if (ss && !ssR) begin 
                 stopFlag <= 1'b1;
             end
             else if ( delayCnt == Stop_i) begin 
@@ -138,7 +127,7 @@ always @(posedge Clk_i) begin
             end
         end
         else begin 
-            if (!Ss && SSr) begin 
+            if (!ss && ssR) begin 
                 stopFlag <= 1'b1;
             end
             else if (delayCnt == Stop_i) begin 
@@ -155,7 +144,7 @@ always @(*) begin
         if (PulsePol_i) begin 
             if (CPHA_i) begin
                 if (LEAD_i == 0) begin 
-                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                if (!ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                     Sck_o = ~(~Clk_i);
                 end
                 else begin 
@@ -163,7 +152,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (!Ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+                    if (!ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(~Clk_i);
                     end
                     else begin 
@@ -173,7 +162,7 @@ always @(*) begin
             end
             else begin
                 if (LEAD_i == 0) begin 
-                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    if (!ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -181,7 +170,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                    if (!ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -193,7 +182,7 @@ always @(*) begin
         else begin 
             if (CPHA_i) begin
                 if (LEAD_i == 0) begin  
-                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    if (!ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -201,7 +190,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (!Ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
+                    if (!ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -211,7 +200,7 @@ always @(*) begin
             end 
             else begin
                 if (LEAD_i == 0) begin 
-                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    if (!ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                         Sck_o = ~(~Clk_i);
                     end
                     else begin 
@@ -219,7 +208,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                    if (!ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(~Clk_i);
                     end
                     else begin 
@@ -233,7 +222,7 @@ always @(*) begin
           if (PulsePol_i) begin 
             if (CPHA_i) begin
                 if (LEAD_i == 0) begin 
-                if (Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                if (ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                     Sck_o = ~(~Clk_i);
                 end
                 else begin 
@@ -241,7 +230,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (Ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+                    if (ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(~Clk_i);
                     end
                     else begin 
@@ -251,7 +240,7 @@ always @(*) begin
             end
             else begin
                 if (LEAD_i == 0) begin 
-                    if (Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    if (ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -259,7 +248,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                    if (ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -271,7 +260,7 @@ always @(*) begin
         else begin 
             if (CPHA_i) begin
                 if (LEAD_i == 0) begin  
-                    if (Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    if (ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -279,7 +268,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (Ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
+                    if (ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -289,7 +278,7 @@ always @(*) begin
             end 
             else begin
                 if (LEAD_i == 0) begin 
-                    if (Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    if (ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                         Sck_o = ~(~Clk_i);
                     end
                     else begin 
@@ -297,7 +286,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                    if (ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(~Clk_i);
                     end
                     else begin 
@@ -316,56 +305,56 @@ always @(*) begin
         if (EndianSel_i) begin 
             case (WidthSel_i) 
                 0 : begin 
-                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i) ) ? (mosiReg0[0]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i) ) ? (mosiReg3[0]):1'b0;
+                    Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
                 end
                 1 : begin 
-                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
                 end
                 2 : begin 
-                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
                 end
                 3 : begin 
-                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
                 end
             endcase
         end
         else begin 
             case (WidthSel_i)
                 0 : begin
-                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
+                    Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
+                    Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
+                    Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
+                    Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
                 end
                 1 : begin
-                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
+                    Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
+                    Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
+                    Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
+                    Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
                 end
                 2 : begin
-                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
+                    Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
+                    Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
+                    Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
+                    Mosi3_i = (!ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
                 end
                 3 : begin
-                    Mosi0_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
-                    Mosi1_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
-                    Mosi2_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
-                    Mosi3_i = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
+                    Mosi0_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                    Mosi1_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
+                    Mosi2_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
+                    Mosi3_i = (!ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
                 end
             endcase
         end
@@ -374,56 +363,56 @@ always @(*) begin
         if (EndianSel_i) begin 
             case (WidthSel_i) 
                 0 : begin 
-                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i) ) ? (mosiReg0[0]):1'b0;
-                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
-                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
-                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i) )?(mosiReg3[0]):1'b0;
+                    Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
                 end
                 1 : begin 
-                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
-                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
-                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
-                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
                 end
                 2 : begin
-                    Mosi0_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
-                    Mosi1_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
-                    Mosi2_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
-                    Mosi3_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi0_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi1_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi2_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi3_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
                 end
                 3 : begin 
-                    Mosi0_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
-                    Mosi1_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
-                    Mosi2_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
-                    Mosi3_i = (Ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi0_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg3[0]):1'b0;
+                    Mosi1_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg2[0]):1'b0;
+                    Mosi2_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg1[0]):1'b0;
+                    Mosi3_i = (ss && (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i)) ? (mosiReg0[0]):1'b0;
                 end
             endcase
         end
         else begin 
             case (WidthSel_i)
                 0 : begin
-                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
-                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
-                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
-                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
+                    Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[1]):1'b0;
+                    Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[1]):1'b0;
+                    Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[1]):1'b0;
+                    Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[1]):1'b0;
                 end
                 1 : begin
-                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
-                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
-                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
-                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
+                    Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[3]):1'b0;
+                    Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[3]):1'b0;
+                    Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[3]):1'b0;
+                    Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt >LAG_i))? (mosiReg3[3]):1'b0;
                 end
                 2 : begin
-                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
-                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
-                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
-                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
+                    Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[5]):1'b0;
+                    Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[5]):1'b0;
+                    Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[5]):1'b0;
+                    Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[5]):1'b0;
                 end
                 3 : begin
-                    Mosi0_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
-                    Mosi1_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
-                    Mosi2_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
-                    Mosi3_i = (Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
+                    Mosi0_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                    Mosi1_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg1[7]):1'b0;
+                    Mosi2_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg2[7]):1'b0;
+                    Mosi3_i = (ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg3[7]):1'b0;
                 end
             endcase
         end
@@ -433,13 +422,13 @@ end
 
 
 always @(posedge Clk_i) begin
-    SSr <= Ss;
+    ssR <= ss;
 end
 
 
 always @(*) begin
     if (SELST_i) begin 
-        if (Ss && !SSr) begin 
+        if (ss && !ssR) begin 
             valReg = 1'b1;
         end
         else begin 
@@ -447,7 +436,7 @@ always @(*) begin
         end
     end
     else begin 
-        if (!Ss&& SSr) begin 
+        if (!ss&& ssR) begin 
             valReg = 1'b1;
         end
         else begin 
@@ -537,27 +526,27 @@ end
 always @(negedge Clk_i) begin
     if (SELST_i) begin  
         if (Rst_i) begin 
-            Ss <= 1'b1;
+            ss <= 1'b1;
         end
         else begin 
             if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag ) begin 
-                Ss <= 1'b0;
+                ss <= 1'b0;
             end
             else begin 
-                Ss <= 1'b1;
+                ss <= 1'b1;
             end
         end
     end
     else begin 
         if (Rst_i) begin 
-            Ss <= 1'b0;
+            ss <= 1'b0;
         end
         else begin 
             if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag ) begin 
-                Ss <= 1'b1;
+                ss <= 1'b1;
             end
             else begin 
-                Ss <= 1'b0;
+                ss <= 1'b0;
             end
         end
     end
@@ -571,7 +560,7 @@ always @(negedge Clk_i) begin
     else begin
         if (!EndianSel_i) begin 
             if (SELST_i) begin 
-                if (!SSr && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (!ssR && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg0 <= { mosiReg0[6:0],1'b0 };
                 end
                 else begin 
@@ -579,7 +568,7 @@ always @(negedge Clk_i) begin
                 end
             end
             else begin 
-                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg0 <= { mosiReg0[6:0],1'b0 };
                 end
                 else begin 
@@ -589,7 +578,7 @@ always @(negedge Clk_i) begin
         end
         else begin 
             if (SELST_i) begin 
-                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg0 <= {1'b0, mosiReg0[7:1] };
                 end
                 else begin 
@@ -597,7 +586,7 @@ always @(negedge Clk_i) begin
                 end
             end
             else begin 
-                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg0 <= {1'b0, mosiReg0[7:1] };
                 end
                 else begin 
@@ -615,7 +604,7 @@ always @(negedge Clk_i) begin
     else begin
         if (!EndianSel_i) begin 
             if (SELST_i) begin 
-                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg1 <= { mosiReg1[6:0],1'b0 };
                 end
                 else begin 
@@ -623,7 +612,7 @@ always @(negedge Clk_i) begin
                 end
             end
             else begin 
-                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg1 <= { mosiReg1[6:0],1'b0 };
                 end
                 else begin 
@@ -633,7 +622,7 @@ always @(negedge Clk_i) begin
         end
         else begin 
             if (SELST_i) begin 
-                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg1 <= {1'b0, mosiReg1[7:1] };
                 end
                 else begin 
@@ -641,7 +630,7 @@ always @(negedge Clk_i) begin
                 end
             end
             else begin 
-                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg1 <= {1'b0, mosiReg1[7:1] };
                 end
                 else begin 
@@ -659,7 +648,7 @@ always @(negedge Clk_i) begin
     else begin
         if (!EndianSel_i) begin
             if (SELST_i) begin  
-                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg2 <= { mosiReg2[6:0],1'b0 };
                 end
                 else begin 
@@ -667,7 +656,7 @@ always @(negedge Clk_i) begin
                 end
             end
             else begin 
-                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg2 <= { mosiReg2[6:0],1'b0 };
                 end
                 else begin 
@@ -677,7 +666,7 @@ always @(negedge Clk_i) begin
         end
         else begin 
             if (SELST_i) begin 
-                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg2 <= {1'b0, mosiReg2[7:1] };
                 end
                 else begin 
@@ -685,7 +674,7 @@ always @(negedge Clk_i) begin
                 end
             end
             else begin 
-                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg2 <= {1'b0, mosiReg2[7:1] };
                 end
                 else begin 
@@ -703,7 +692,7 @@ always @(negedge Clk_i) begin
     else begin
         if (!EndianSel_i) begin 
             if (SELST_i) begin 
-                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg3 <= { mosiReg3[6:0],1'b0 };
                 end
                 else begin 
@@ -711,7 +700,7 @@ always @(negedge Clk_i) begin
                 end
             end
             else begin 
-                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg3 <= { mosiReg3[6:0],1'b0 };
                 end
                 else begin 
@@ -721,7 +710,7 @@ always @(negedge Clk_i) begin
         end
         else begin 
             if (SELST_i) begin 
-                if (!SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (!ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg3 <= {1'b0, mosiReg3[7:1] };
                 end
                 else begin 
@@ -729,7 +718,7 @@ always @(negedge Clk_i) begin
                 end
             end
             else begin 
-                if (SSr&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                if (ssR&& (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
                     mosiReg3 <= {1'b0, mosiReg3[7:1] };
                 end
                 else begin 

sources_1/new/QuadSPI/QuadSPIs.v

@@ -10,11 +10,13 @@ module QuadSPIs (
     input Mosi3_i,
 
     input [1:0] WidthSel_i,
-    input EnEdge_i,
-    input PulsePol_i,
+    input SELST_i,
+    input EndianSel_i,
+   
 
     output reg [23:0] Data_o,
     output reg [7:0] Addr_o,
+      output [31:0] DataToRxFifo_o,
     output reg Val_o
 );
 
@@ -30,49 +32,26 @@ reg [7:0] shiftReg0;
 reg [7:0] shiftReg1;
 reg [7:0] shiftReg2;
 
+reg [7:0] addrRegLSB;
+reg [7:0] shiftReg0LSB;
+reg [7:0] shiftReg1LSB;
+reg [7:0] shiftReg2LSB;
+
 reg [7:0] shiftReg0M;
 reg [7:0] shiftReg1M;
 reg [7:0] shiftReg2M;
 reg [7:0] addrRegM;
 
-reg Sck;
 
 //===============================================================================
 //  ASSIGNMENTS
 
 
-
+assign DataToRxFifo_o = {Addr_o, Data_o};
 
 //================================================================================
 //	CODING
 //================================================================================
-always @(*) begin 
-    if (PulsePol_i) begin 
-        if (EnEdge_i) begin 
-            assign Sck = ~Sck_i;
-        end
-        else begin 
-            assign Sck = Sck_i;
-        end
-    end
-    else begin 
-        if (EnEdge_i) begin 
-            assign Sck = Sck_i;
-        end
-        else begin 
-            assign Sck = ~Sck_i;
-        end
-    end
-end
-always @(posedge Sck) begin 
-    if (Rst_i) begin 
-        SckReg <= 1'b0;
-    end
-    else begin 
-        SckReg <= Sck;
-    end
-end
-
 
 always	@(posedge	Clk_i)	begin
 	ssReg	<=	Ss_i;
@@ -87,48 +66,95 @@ always @(*) begin
         shiftReg1M = 8'h0;
         shiftReg2M = 8'h0;
     end
-    else begin 
-        case(WidthSel_i)  
-             0: begin 
-                addrRegM   = addrReg  [1:0];
-                shiftReg0M = shiftReg0[1:0];
-                shiftReg1M = shiftReg1[1:0];
-                shiftReg2M = shiftReg2[1:0];
-            end
-            1: begin 
-                addrRegM   = addrReg  [3:0];
-                shiftReg0M = shiftReg0[3:0];
-                shiftReg1M = shiftReg1[3:0];
-                shiftReg2M = shiftReg2[3:0];
-            end
-            2: begin 
-                addrRegM   = addrReg  [5:0];
-                shiftReg0M = shiftReg0[5:0];
-                shiftReg1M = shiftReg1[5:0];
-                shiftReg2M = shiftReg2[5:0];
-            end
-            3: begin 
-                addrRegM   = addrReg  [7:0];
-                shiftReg0M = shiftReg0[7:0];
-                shiftReg1M = shiftReg1[7:0];
-                shiftReg2M = shiftReg2[7:0];
-            end
-        endcase
+    else begin
+        if (!EndianSel_i) begin  
+            case(WidthSel_i)  
+                 0: begin 
+                    addrRegM   = addrReg  [1:0];
+                    shiftReg0M = shiftReg0[1:0];
+                    shiftReg1M = shiftReg1[1:0];
+                    shiftReg2M = shiftReg2[1:0];
+                end
+                1: begin 
+                    addrRegM   = addrReg  [3:0];
+                    shiftReg0M = shiftReg0[3:0];
+                    shiftReg1M = shiftReg1[3:0];
+                    shiftReg2M = shiftReg2[3:0];
+                end
+                2: begin 
+                    addrRegM   = addrReg  [5:0];
+                    shiftReg0M = shiftReg0[5:0];
+                    shiftReg1M = shiftReg1[5:0];
+                    shiftReg2M = shiftReg2[5:0];
+                end
+                3: begin 
+                    addrRegM   = addrReg  [7:0];
+                    shiftReg0M = shiftReg0[7:0];
+                    shiftReg1M = shiftReg1[7:0];
+                    shiftReg2M = shiftReg2[7:0];
+                end
+            endcase
+        end
+        else begin 
+            case(WidthSel_i) 
+                    0: begin 
+                        addrRegM   = addrRegLSB[1:0];
+                        shiftReg0M = shiftReg0LSB[1:0];
+                        shiftReg1M = shiftReg1LSB[1:0];
+                        shiftReg2M = shiftReg2LSB[1:0];
+                    end
+                    1: begin 
+                        addrRegM   = addrRegLSB[3:0];
+                        shiftReg0M = shiftReg0LSB[3:0];
+                        shiftReg1M = shiftReg1LSB[3:0];
+                        shiftReg2M = shiftReg2LSB[3:0];
+                    end
+                    2: begin 
+                        addrRegM   = addrRegLSB[5:0];
+                        shiftReg0M = shiftReg0LSB[5:0];
+                        shiftReg1M = shiftReg1LSB[5:0];
+                        shiftReg2M = shiftReg2LSB[5:0];
+                    end
+                    3: begin 
+                        addrRegM   = addrRegLSB[7:0];
+                        shiftReg0M = shiftReg0LSB[7:0];
+                        shiftReg1M = shiftReg1LSB[7:0];
+                        shiftReg2M = shiftReg2LSB[7:0];
+                    end
+            endcase
+        end
     end
 end
 
 
-
 always @(posedge Clk_i) begin 
     if (Rst_i) begin 
         Data_o <= 24'h0;
     end
-    else begin 
-        if (ssReg && !ssRegR) begin 
-            Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
+    else begin
+        if (!EndianSel_i) begin 
+            if (SELST_i) begin  
+                if (ssReg && !ssRegR) begin 
+                    Data_o <= {shiftReg0M, shiftReg1M, shiftReg2M};
+                end
+            end
+            else begin 
+                if (!ssReg && ssRegR) begin 
+                    Data_o <= {shiftReg0M, shiftReg1M, shiftReg2M};
+                end
+            end
         end
         else begin 
-            Data_o <= 24'h0;
+            if (SELST_i) begin  
+                if (ssReg && !ssRegR) begin 
+                    Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
+                end
+            end
+            else begin 
+                if (!ssReg && ssRegR) begin 
+                    Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
+                end
+            end
         end
     end
 end
@@ -137,81 +163,236 @@ always @(posedge Clk_i) begin
     if (Rst_i) begin 
         Addr_o <= 8'h0;
     end
-    else begin 
-        if (ssReg && !ssRegR) begin 
-            Addr_o <= addrRegM;
+    else begin
+        if (SELST_i) begin 
+            if (ssReg && !ssRegR) begin 
+                Addr_o <= addrRegM;
+            end
+        end
+        else begin 
+            if (!ssReg && ssRegR) begin 
+                Addr_o <= addrRegM;
+            end
         end
     end
 end
 
 
-always @(posedge Sck) begin 
+
+
+always @(posedge Sck_i) begin 
     if (Rst_i) begin 
         shiftReg0 <= 8'h0;
     end
-    else begin 
-        if (!Ss_i) begin 
-            shiftReg0 <= {shiftReg0[6:0], Mosi0_i};
+    else begin
+        if (SELST_i) begin   
+            if (!Ss_i) begin 
+                shiftReg0 <= {shiftReg0[6:0], Mosi1_i};
+            end
+            else begin 
+                shiftReg0 <= 8'h0;
+            end
         end
         else begin 
-            shiftReg0 <= 8'h0;
+            if (Ss_i) begin 
+                shiftReg0 <= {shiftReg0[6:0], Mosi1_i};
+            end
+            else begin 
+                shiftReg0<= 8'h0;
+            end
         end
     end
 end
 
 
-always @(posedge Sck ) begin 
+always @(posedge Sck_i ) begin 
     if (Rst_i) begin 
         shiftReg1 <= 8'h0;
     end
-    else begin 
-        if (!Ss_i) begin 
-            shiftReg1 <= {shiftReg1[6:0], Mosi1_i};
+    else begin
+        if (SELST_i) begin   
+            if (!Ss_i) begin 
+                shiftReg1 <= {shiftReg1[6:0], Mosi2_i};
+            end
+            else begin 
+                shiftReg1 <= 8'h0;
+            end
         end
         else begin 
-            shiftReg1 <= 8'h0;
+            if (Ss_i) begin 
+                shiftReg1 <= {shiftReg1[6:0], Mosi2_i};
+            end
+            else begin 
+                shiftReg1 <= 8'h0;
+            end
         end
     end
 end
 
 
-always @(posedge Sck ) begin 
+always @(posedge Sck_i ) begin 
     if (Rst_i) begin 
         shiftReg2 <= 8'h0;
     end
-    else begin 
-        if (!Ss_i) begin 
-            shiftReg2 <= {shiftReg2[6:0], Mosi2_i};
+    else begin
+        if (SELST_i) begin   
+            if (!Ss_i) begin 
+                shiftReg2 <= {shiftReg2[6:0], Mosi3_i};
+            end
+            else begin 
+                shiftReg2 <= 8'h0;
+            end
         end
         else begin 
-            shiftReg2 <= 8'h0;
+            if (Ss_i) begin 
+                shiftReg2 <= {shiftReg2[6:0], Mosi3_i};
+            end
+            else begin 
+                shiftReg2 <= 8'h0;
+            end
         end
     end
 end
 
 
-always @(posedge Sck ) begin 
+always @(posedge Sck_i or posedge Rst_i ) begin 
     if (Rst_i) begin 
         addrReg <= 8'h0;
     end
+    else begin
+        if (SELST_i) begin 
+            if (!Ss_i) begin 
+                addrReg <={addrReg[6:0], Mosi0_i};
+            end
+            else begin 
+                addrReg <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                addrReg <= {addrReg[6:0], Mosi0_i};
+            end
+            else begin 
+                addrReg <= 8'h0;
+            end
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin
+    if (Rst_i) begin 
+        addrRegLSB <= 8'h0;
+    end
     else begin 
-        if (!Ss_i) begin 
-            addrReg <= {addrReg[6:0], Mosi3_i};
+        if (SELST_i) begin 
+            if (!Ss_i) begin 
+                addrRegLSB <= {Mosi3_i, addrRegLSB[7:1]};
+            end
+            else begin 
+                addrRegLSB <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                addrRegLSB <= {Mosi3_i, addrRegLSB[7:1]};
+            end
+            else begin 
+                addrRegLSB <= 8'h0;
+            end
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg0LSB <= 8'h0;
+    end
+    else begin
+        if (SELST_i) begin   
+            if (!Ss_i) begin 
+                shiftReg0LSB <= {Mosi0_i, shiftReg0LSB[7:1]};
+            end
+            else begin 
+                shiftReg0LSB <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                shiftReg0LSB <= {Mosi0_i, shiftReg0LSB[7:1]};
+            end
+            else begin 
+                shiftReg0LSB <= 8'h0;
+            end
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg1LSB <= 8'h0;
+    end
+    else begin
+        if (SELST_i) begin   
+            if (!Ss_i) begin 
+                shiftReg1LSB <= {Mosi1_i, shiftReg1LSB[7:1]};
+            end
+            else begin 
+                shiftReg1LSB <= 8'h0;
+            end
         end
         else begin 
-            addrReg <= 8'h0;
+            if (Ss_i) begin 
+                shiftReg1LSB <= {Mosi1_i, shiftReg1LSB[7:1]};
+            end
+            else begin 
+                shiftReg1LSB <= 8'h0;
+            end
         end
     end
 end
 
 
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg2LSB <= 8'h0;
+    end
+    else begin
+        if (SELST_i) begin   
+            if (!Ss_i) begin 
+                shiftReg2LSB <= {Mosi2_i, shiftReg2LSB[7:1]};
+            end
+            else begin 
+                shiftReg2LSB <= 8'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                shiftReg2LSB <= {Mosi2_i, shiftReg2LSB[7:1]};
+            end
+            else begin 
+                shiftReg2LSB <= 8'h0;
+            end
+        end
+    end
+end
+
 
-always @(posedge Clk_i) begin 
-    if (ssReg && !ssRegR) begin 
-        Val_o <= 1'b1;
+always @(posedge Clk_i) begin
+    if (SELST_i) begin 
+        if (ssReg && !ssRegR) begin 
+            Val_o <= 1'b1;
+        end
+        else begin 
+            Val_o <= 1'b0;
+        end
     end
     else begin 
-        Val_o <= 1'b0;
+        if (!ssReg&& ssRegR) begin 
+            Val_o <= 1'b1;
+        end
+        else begin 
+            Val_o <= 1'b0;
+        end
     end
 end
 

sources_1/new/QuadSPI/QuadSPIs_tb.v

@@ -1,275 +0,0 @@
-`timescale 1ns / 1ps
-module QuadSPIs_tb ();
-
-reg Clk70_i;
-reg Clk50_i;
-wire Sck_i;
-wire Rst_i;
-
-reg[7:0] mosiReg0_tb;
-reg[7:0] mosiReg1_tb;
-reg[7:0] mosiReg2_tb;
-reg[7:0] mosiReg3_tb;
-
-
-reg [7:0] Mosi0_i;
-reg [7:0] Mosi1_i;
-reg [7:0] Mosi2_i;
-reg [7:0] Mosi3_i;
-reg EnEdge_i;
-reg Ss;
-reg SSr;
-reg SSm;
-reg Start_i;
-reg startFlag;
-reg [5:0] ssCnt; 
-reg [3:0] ssNum;
-reg [1:0] WidthSel_i;
-
-reg [31:0] SPIdata;
-
-
-// assign Mosi0_i = (!Ss) ? (mosiReg3_tb[7]):1'b0;
-// assign Mosi1_i = (!Ss) ? (mosiReg2_tb[7]):1'b0;
-// assign Mosi2_i = (!Ss) ? (mosiReg1_tb[7]):1'b0;
-// assign Mosi3_i = (!Ss) ? (mosiReg0_tb[7]):1'b0;
-assign Sck_i = (!Ss) ? (Clk70_i) : 1'b0;
-
-
-
-
-// always #(24.390243902439/2) Clk70_i = ~Clk70_i;// 41Mhz
-always #(14.285714285714/2) Clk70_i = ~Clk70_i;// 70Mhz
-// always #10 Clk70_i = ~Clk70_i;// 50 Mhz
-
-always #10 Clk50_i = ~Clk50_i;
-
-
-
-
-always @(*) begin 
-    case (WidthSel_i) 
-        0 : begin 
-            Mosi0_i = (!Ss) ? (mosiReg3_tb[1]):1'b0;
-            Mosi1_i = (!Ss) ? (mosiReg2_tb[1]):1'b0;
-            Mosi2_i = (!Ss) ? (mosiReg1_tb[1]):1'b0;
-            Mosi3_i = (!Ss) ? (mosiReg0_tb[1]):1'b0;
-        end
-        1 : begin 
-            Mosi0_i = (!Ss) ? (mosiReg3_tb[3]):1'b0;
-            Mosi1_i = (!Ss) ? (mosiReg2_tb[3]):1'b0;
-            Mosi2_i = (!Ss) ? (mosiReg1_tb[3]):1'b0;
-            Mosi3_i = (!Ss) ? (mosiReg0_tb[3]):1'b0;
-        end
-        2 : begin 
-            Mosi0_i = (!Ss) ? (mosiReg3_tb[5]):1'b0;
-            Mosi1_i = (!Ss) ? (mosiReg2_tb[5]):1'b0;
-            Mosi2_i = (!Ss) ? (mosiReg1_tb[5]):1'b0;
-            Mosi3_i = (!Ss) ? (mosiReg0_tb[5]):1'b0;
-        end
-        3 : begin 
-            Mosi0_i = (!Ss) ? (mosiReg3_tb[7]):1'b0;
-            Mosi1_i = (!Ss) ? (mosiReg2_tb[7]):1'b0;
-            Mosi2_i = (!Ss) ? (mosiReg1_tb[7]):1'b0;
-            Mosi3_i = (!Ss) ? (mosiReg0_tb[7]):1'b0;
-        end
-    endcase
-end
-
-
-
-
-
-
-
-initial begin 
-    Clk70_i = 1'b1;
-    // Clk70_i = 1'b0;//50 Mhz out of phase with src clk
-    Clk50_i = 1'b1;
-    Start_i = 1'b0;
-    EnEdge_i = 1'b1;
-    SPIdata = {1'h0, 7'h2a, 8'haa,8'h00,8'haa};
-    WidthSel_i = 2'b11;
-    #100Start_i = 1'b1;
-    #500 Start_i = 1'b0;
-    #600 Start_i = 1'b1;
-     SPIdata = {1'h1, 7'h29, 24'd520050};
-    #100 Start_i = 1'b0;
-    #1500 Start_i = 1'b1;
-     SPIdata = {1'h0, 7'h2a, 24'd10};
-    #100 Start_i = 1'b0;
-
-end
-
-
-always @(posedge Clk70_i) begin
-    if (Rst_i) begin
-        SSr <=1'b0;
-    end
-    else begin 
-        SSr <= Ss;
-    end
-end
-
-
-always @(posedge Clk70_i) begin 
-    if (Rst_i) begin 
-        startFlag <= 1'b0;
-    end
-    else begin 
-        if (!Start_i) begin 
-            startFlag <= 1'b1;
-        end
-        else begin 
-            startFlag <= 1'b0;
-        end
-    end
-end
-
-
-always @(*) begin 
-    if (Rst_i) begin 
-        ssNum = 1'b0;
-    end
-    else begin 
-        case (WidthSel_i) 
-            0 : begin 
-                ssNum = 2;
-            end
-            1 : begin 
-                ssNum = 4;
-            end
-            2 : begin 
-                ssNum = 6;
-            end
-            3 : begin 
-                ssNum = 8;
-            end
-        endcase
-    end
-end
-
-
-always @(posedge Clk70_i) begin 
-    if (Rst_i) begin 
-        ssCnt <= 1'b0;
-    end
-    else if (ssCnt < ssNum && startFlag  ) begin 
-        ssCnt <= ssCnt + 1'b1;
-    end
-    else begin
-        if (ssCnt == ssNum-1 || !startFlag) begin 
-            ssCnt <= 1'b0;
-        end
-    end
-end
-
-always @(negedge Clk70_i) begin 
-    if (Rst_i) begin 
-        Ss <= 1'b1;
-    end
-    else begin 
-        if (ssCnt < ssNum && startFlag ) begin 
-            Ss <= 1'b0;
-        end
-        else begin 
-            Ss <= 1'b1;
-        end
-    end
-end
-
-
-always @(negedge Clk70_i) begin 
-    if (Rst_i) begin 
-        mosiReg0_tb <= SPIdata[31:24];
-    end
-    else begin 
-        if (!SSr) begin
-            mosiReg0_tb <= { mosiReg0_tb[6:0],1'b0 };
-        end
-        else begin 
-            mosiReg0_tb <= SPIdata[31:24];
-        end
-    end
-end
-
-always @(negedge Clk70_i) begin 
-    if (Rst_i) begin 
-        mosiReg1_tb <= SPIdata[23:16];
-    end
-    else begin 
-        if (!SSr) begin
-            mosiReg1_tb <= { mosiReg1_tb[6:0],1'b0 };
-        end
-        else begin 
-            mosiReg1_tb <= SPIdata[23:16];
-        end
-    end
-end
-
-always @(negedge Clk70_i) begin 
-    if (Rst_i) begin 
-        mosiReg2_tb <= SPIdata[15:8];
-    end
-    else begin 
-        if (!SSr) begin
-            mosiReg2_tb <= { mosiReg2_tb[6:0],1'b0 };
-        end
-        else begin 
-            mosiReg2_tb <= SPIdata[15:8];
-        end
-    end
-end
-
-always @(negedge Clk70_i) begin 
-    if (Rst_i) begin 
-        mosiReg3_tb <= SPIdata[7:0];
-    end
-    else begin 
-        if (!SSr) begin
-            mosiReg3_tb <= { mosiReg3_tb[6:0],1'b0 };
-        end
-        else begin 
-            mosiReg3_tb <= SPIdata[7:0];
-        end
-    end
-end
-
-
-
-
-
-
-QuadSPIs QuadSPI_inst (
-    .Sck_i(Sck_i),
-    .Clk_i(Clk50_i),
-    .Rst_i(Rst_i),
-    .Ss_i(Ss),
-    .WidthSel_i(WidthSel_i),
-    .Mosi0_i(Mosi0_i),
-    .Mosi1_i(Mosi1_i),
-    .Mosi2_i(Mosi2_i),
-    .Mosi3_i(Mosi3_i),
-    .EnEdge_i(EnEdge_i),
-    .PulsePol_i(1'b0)
-
-);
-
-
-
-InitRst InitRst_inst (
-    .clk_i(Clk50_i),
-    .signal_o(Rst_i)
-
-);
-
-
-
-
-
-
-
-
-
-
-endmodule

sources_1/new/SRAM/RegMap.v

@@ -108,8 +108,6 @@ reg [CmdRegWidth/2-1:0] Spi0CsDelayReg;
 reg [CmdRegWidth/2-1:0] Spi0CsCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi0TxFifoCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi0RxFifoCtrlReg;
-reg [CmdRegWidth/2-1:0] Spi0TxFifoReg;
-reg [CmdRegWidth/2-1:0] Spi0RxFifoReg;
 
 
 reg [CmdRegWidth/2-1:0] Spi1CtrlReg;
@@ -118,8 +116,7 @@ reg [CmdRegWidth/2-1:0] Spi1CsDelayReg;
 reg [CmdRegWidth/2-1:0] Spi1CsCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi1TxFifoCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi1RxFifoCtrlReg;
-reg [CmdRegWidth/2-1:0] Spi1TxFifoReg;
-reg [CmdRegWidth/2-1:0] Spi1RxFifoReg;
+
 
 reg [CmdRegWidth/2-1:0] Spi2CtrlReg;
 reg [CmdRegWidth/2-1:0] Spi2ClkReg;
@@ -127,8 +124,6 @@ reg [CmdRegWidth/2-1:0] Spi2CsDelayReg;
 reg [CmdRegWidth/2-1:0] Spi2CsCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi2TxFifoCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi2RxFifoCtrlReg;
-reg [CmdRegWidth/2-1:0] Spi2TxFifoReg;
-reg [CmdRegWidth/2-1:0] Spi2RxFifoReg;
 
 
 reg [CmdRegWidth/2-1:0] Spi3CtrlReg;
@@ -137,8 +132,6 @@ reg [CmdRegWidth/2-1:0] Spi3CsDelayReg;
 reg [CmdRegWidth/2-1:0] Spi3CsCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi3TxFifoCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi3RxFifoCtrlReg;
-reg [CmdRegWidth/2-1:0] Spi3TxFifoReg;
-reg [CmdRegWidth/2-1:0] Spi3RxFifoReg;
 
 
 reg [CmdRegWidth/2-1:0] Spi4CtrlReg;
@@ -147,8 +140,7 @@ reg [CmdRegWidth/2-1:0] Spi4CsDelayReg;
 reg [CmdRegWidth/2-1:0] Spi4CsCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi4TxFifoCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi4RxFifoCtrlReg;
-reg [CmdRegWidth/2-1:0] Spi4TxFifoReg;
-reg [CmdRegWidth/2-1:0] Spi4RxFifoReg;
+
 
 
 reg [CmdRegWidth/2-1:0] Spi5CtrlReg;
@@ -157,8 +149,6 @@ reg [CmdRegWidth/2-1:0] Spi5CsDelayReg;
 reg [CmdRegWidth/2-1:0] Spi5CsCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi5TxFifoCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi5RxFifoCtrlReg;
-reg [CmdRegWidth/2-1:0] Spi5TxFifoReg;
-reg [CmdRegWidth/2-1:0] Spi5RxFifoReg;
 
 
 reg [CmdRegWidth/2-1:0] Spi6CtrlReg;
@@ -167,16 +157,14 @@ reg [CmdRegWidth/2-1:0] Spi6CsDelayReg;
 reg [CmdRegWidth/2-1:0] Spi6CsCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi6TxFifoCtrlReg;
 reg [CmdRegWidth/2-1:0] Spi6RxFifoCtrlReg;
-reg [CmdRegWidth/2-1:0] Spi6TxFifoReg;
-reg [CmdRegWidth/2-1:0] Spi6RxFifoReg;
 
-(* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] SpiTxRxEnReg;
+(* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] spiTxRxEnReg;
 reg [CmdRegWidth/2-1:0] GPIOAReg;
 reg [CmdRegWidth/2-1:0] GPIOARegS;
 
 
 (* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] ansReg;
-(* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] LedReg;
+(* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] ledReg;
 
 reg	[1:0]	beReg;
 //================================================================================
@@ -188,8 +176,6 @@ assign Spi0CsDelayReg_o = Spi0CsDelayReg;
 assign Spi0CsCtrlReg_o = Spi0CsCtrlReg;
 assign Spi0TxFifoCtrlReg_o = Spi0TxFifoCtrlReg;
 assign Spi0RxFifoCtrlReg_o = Spi0RxFifoCtrlReg;
-assign Spi0TxFifoReg_o = Spi0TxFifoReg;
-assign Spi0RxFifoReg_o = Spi0RxFifoReg;
 
 assign Spi1CtrlReg_o = Spi1CtrlReg;
 assign Spi1ClkReg_o = Spi1ClkReg;
@@ -197,8 +183,6 @@ assign Spi1CsDelayReg_o = Spi1CsDelayReg;
 assign Spi1CsCtrlReg_o = Spi1CsCtrlReg;
 assign Spi1TxFifoCtrlReg_o = Spi1TxFifoCtrlReg;
 assign Spi1RxFifoCtrlReg_o = Spi1RxFifoCtrlReg;
-assign Spi1TxFifoReg_o = Spi1TxFifoReg;
-assign Spi1RxFifoReg_o = Spi1RxFifoReg;
 
 assign Spi2CtrlReg_o = Spi2CtrlReg;
 assign Spi2ClkReg_o = Spi2ClkReg;
@@ -206,8 +190,6 @@ assign Spi2CsDelayReg_o = Spi2CsDelayReg;
 assign Spi2CsCtrlReg_o = Spi2CsCtrlReg;
 assign Spi2TxFifoCtrlReg_o = Spi2TxFifoCtrlReg;
 assign Spi2RxFifoCtrlReg_o = Spi2RxFifoCtrlReg;
-assign Spi2TxFifoReg_o = Spi2TxFifoReg;
-assign Spi2RxFifoReg_o = Spi2RxFifoReg;
 
 assign Spi3CtrlReg_o = Spi3CtrlReg;
 assign Spi3ClkReg_o = Spi3ClkReg;
@@ -215,8 +197,7 @@ assign Spi3CsDelayReg_o = Spi3CsDelayReg;
 assign Spi3CsCtrlReg_o = Spi3CsCtrlReg;
 assign Spi3TxFifoCtrlReg_o = Spi3TxFifoCtrlReg;
 assign Spi3RxFifoCtrlReg_o = Spi3RxFifoCtrlReg;
-assign Spi3TxFifoReg_o = Spi3TxFifoReg;
-assign Spi3RxFifoReg_o = Spi3RxFifoReg;
+
 
 assign Spi4CtrlReg_o = Spi4CtrlReg;
 assign Spi4ClkReg_o = Spi4ClkReg;
@@ -224,8 +205,7 @@ assign Spi4CsDelayReg_o = Spi4CsDelayReg;
 assign Spi4CsCtrlReg_o = Spi4CsCtrlReg;
 assign Spi4TxFifoCtrlReg_o = Spi4TxFifoCtrlReg;
 assign Spi4RxFifoCtrlReg_o = Spi4RxFifoCtrlReg;
-assign Spi4TxFifoReg_o = Spi4TxFifoReg;
-assign Spi4RxFifoReg_o = Spi4RxFifoReg;
+
 
 assign Spi5CtrlReg_o = Spi5CtrlReg;
 assign Spi5ClkReg_o = Spi5ClkReg;
@@ -233,8 +213,7 @@ assign Spi5CsDelayReg_o = Spi5CsDelayReg;
 assign Spi5CsCtrlReg_o = Spi5CsCtrlReg;
 assign Spi5TxFifoCtrlReg_o = Spi5TxFifoCtrlReg;
 assign Spi5RxFifoCtrlReg_o = Spi5RxFifoCtrlReg;
-assign Spi5TxFifoReg_o = Spi5TxFifoReg;
-assign Spi5RxFifoReg_o = Spi5RxFifoReg;
+
 
 assign Spi6CtrlReg_o = Spi6CtrlReg;
 assign Spi6ClkReg_o = Spi6ClkReg;
@@ -242,10 +221,9 @@ assign Spi6CsDelayReg_o = Spi6CsDelayReg;
 assign Spi6CsCtrlReg_o = Spi6CsCtrlReg;
 assign Spi6TxFifoCtrlReg_o = Spi6TxFifoCtrlReg;
 assign Spi6RxFifoCtrlReg_o = Spi6RxFifoCtrlReg;
-assign Spi6TxFifoReg_o = Spi6TxFifoReg;
-assign Spi6RxFifoReg_o = Spi6RxFifoReg;
 
-assign SpiTxRxEnReg_o = SpiTxRxEnReg;
+
+assign SpiTxRxEnReg_o = spiTxRxEnReg;
 assign GPIOAReg_o = {GPIOARegS, GPIOAReg};
 
 
@@ -253,7 +231,7 @@ assign GPIOAReg_o = {GPIOARegS, GPIOAReg};
 
 
 assign AnsDataReg_o = ansReg;
-assign Led_o = LedReg[0];
+assign Led_o = ledReg[0];
 //================================================================================
 //	LOCALPARAMS
 //================================================================================
@@ -360,60 +338,46 @@ always @(posedge Clk_i) begin
         Spi0CsCtrlReg <= 0;
         Spi0TxFifoCtrlReg <= 0;
         Spi0RxFifoCtrlReg <= 0;
-        Spi0TxFifoReg <= 0;
-        Spi0RxFifoReg <= 0;
         Spi1ClkReg <= 0;
         Spi1CtrlReg <= 0;
         Spi1CsDelayReg <= 0;
         Spi1CsCtrlReg <= 0;
         Spi1TxFifoCtrlReg <= 0;
         Spi1RxFifoCtrlReg <= 0;
-        Spi1TxFifoReg <= 0;
-        Spi1RxFifoReg <= 0;
         Spi2ClkReg <= 0;
         Spi2CtrlReg <= 0;
         Spi2CsDelayReg <= 0;
         Spi2CsCtrlReg <= 0;
         Spi2TxFifoCtrlReg <= 0;
         Spi2RxFifoCtrlReg <= 0;
-        Spi2TxFifoReg <= 0;
-        Spi2RxFifoReg <= 0;
         Spi3ClkReg <= 0;
         Spi3CtrlReg <= 0;
         Spi3CsDelayReg <= 0;
         Spi3CsCtrlReg <= 0;
         Spi3TxFifoCtrlReg <= 0;
         Spi3RxFifoCtrlReg <= 0;
-        Spi3TxFifoReg <= 0;
-        Spi3RxFifoReg <= 0;
         Spi4ClkReg <= 0;
         Spi4CtrlReg <= 0;
         Spi4CsDelayReg <= 0;
         Spi4CsCtrlReg <= 0;
         Spi4TxFifoCtrlReg <= 0;
         Spi4RxFifoCtrlReg <= 0;
-        Spi4TxFifoReg <= 0;
-        Spi4RxFifoReg <= 0;
         Spi5ClkReg <= 0;
         Spi5CtrlReg <= 0;
         Spi5CsDelayReg <= 0;
         Spi5CsCtrlReg <= 0;
         Spi5TxFifoCtrlReg <= 0;
         Spi5RxFifoCtrlReg <= 0;
-        Spi5TxFifoReg <= 0;
-        Spi5RxFifoReg <= 0;
         Spi6ClkReg <= 0;
         Spi6CtrlReg <= 0;
         Spi6CsDelayReg <= 0;
         Spi6CsCtrlReg <= 0;
         Spi6TxFifoCtrlReg <= 0;
         Spi6RxFifoCtrlReg <= 0;
-        Spi6TxFifoReg <= 0;
-        Spi6RxFifoReg <= 0;
-        SpiTxRxEnReg <= 0;
+        spiTxRxEnReg <= 0;
         GPIOAReg <= 0;
         GPIOARegS <= 0;
-        LedReg <= 0;
+        ledReg <= 0;
     end
     else begin 
         if (Val_i) begin 
@@ -438,12 +402,6 @@ always @(posedge Clk_i) begin
                         Spi0RxFifoCtrlAddrLsb : begin 
                             Spi0RxFifoCtrlReg <= Data_i;
                         end
-                        Spi0TxFifo : begin 
-                            Spi0TxFifoReg <= Data_i;
-                        end
-                        Spi0RxFifo : begin 
-                            Spi0RxFifoReg <= Data_i;
-                        end
                         Spi1CtrlAddr : begin 
                             Spi1CtrlReg <= Data_i;
                         end
@@ -462,12 +420,6 @@ always @(posedge Clk_i) begin
                         Spi1RxFifoCtrlAddrLsb : begin 
                             Spi1RxFifoCtrlReg <= Data_i;
                         end
-                        Spi1TxFifo : begin 
-                            Spi1TxFifoReg <= Data_i;
-                        end
-                        Spi1RxFifo : begin 
-                            Spi1RxFifoReg <= Data_i;
-                        end
                         Spi2CtrlAddr : begin 
                             Spi2CtrlReg <= Data_i;
                         end
@@ -486,12 +438,6 @@ always @(posedge Clk_i) begin
                         Spi2RxFifoCtrlAddrLsb : begin 
                             Spi2RxFifoCtrlReg <= Data_i;
                         end
-                        Spi2TxFifo : begin 
-                            Spi2TxFifoReg <= Data_i;
-                        end
-                        Spi2RxFifo : begin 
-                            Spi2RxFifoReg <= Data_i;
-                        end
                         Spi3CtrlAddr : begin 
                             Spi3CtrlReg <= Data_i;
                         end
@@ -510,12 +456,6 @@ always @(posedge Clk_i) begin
                         Spi3RxFifoCtrlAddrLsb : begin 
                             Spi3RxFifoCtrlReg <= Data_i;
                         end
-                        Spi3TxFifo : begin 
-                            Spi3TxFifoReg <= Data_i;
-                        end
-                        Spi3RxFifo : begin 
-                            Spi3RxFifoReg <= Data_i;
-                        end
                         Spi4CtrlAddr : begin 
                             Spi4CtrlReg <= Data_i;
                         end
@@ -534,12 +474,6 @@ always @(posedge Clk_i) begin
                         Spi4RxFifoCtrlAddrLsb : begin 
                             Spi4RxFifoCtrlReg <= Data_i;
                         end
-                        Spi4TxFifo : begin 
-                            Spi4TxFifoReg <= Data_i;
-                        end
-                        Spi4RxFifo : begin 
-                            Spi4RxFifoReg <= Data_i;
-                        end
                         Spi5CtrlAddr : begin 
                             Spi5CtrlReg <= Data_i;
                         end
@@ -558,12 +492,6 @@ always @(posedge Clk_i) begin
                         Spi5RxFifoCtrlAddrLsb : begin 
                             Spi5RxFifoCtrlReg <= Data_i;
                         end
-                        Spi5TxFifo : begin 
-                            Spi5TxFifoReg <= Data_i;
-                        end
-                        Spi5RxFifo : begin 
-                            Spi5RxFifoReg <= Data_i;
-                        end
                         Spi6CtrlAddr : begin 
                             Spi6CtrlReg <= Data_i;
                         end
@@ -582,14 +510,8 @@ always @(posedge Clk_i) begin
                         Spi6RxFifoCtrlAddrLsb : begin 
                             Spi6RxFifoCtrlReg <= Data_i;
                         end
-                        Spi6TxFifo : begin 
-                            Spi6TxFifoReg <= Data_i;
-                        end
-                        Spi6RxFifo : begin 
-                            Spi6RxFifoReg <= Data_i;
-                        end
                         SpiTxRxEn : begin 
-                            SpiTxRxEnReg <= Data_i;
+                            spiTxRxEnReg <= Data_i;
                         end
                         GPIOCtrlAddr : begin 
                             GPIOAReg <= Data_i;
@@ -598,7 +520,7 @@ always @(posedge Clk_i) begin
                             GPIOARegS <= Data_i;
                         end
                         Debug0Addr : begin 
-                            LedReg <= Data_i;
+                            ledReg <= Data_i;
                         end
                     endcase
                 end
@@ -622,12 +544,6 @@ always @(posedge Clk_i) begin
                         Spi0RxFifoCtrlAddrLsb : begin 
                             Spi0RxFifoCtrlReg[15:8] <= Data_i[15:8];
                         end
-                        Spi0TxFifo : begin 
-                            Spi0TxFifoReg[15:8] <= Data_i[15:8];
-                        end
-                        Spi0RxFifo : begin 
-                            Spi0RxFifoReg[15:8] <= Data_i[15:8];
-                        end
                         Spi1CtrlAddr : begin 
                             Spi1CtrlReg[15:8] <= Data_i[15:8];
                         end
@@ -646,12 +562,6 @@ always @(posedge Clk_i) begin
                         Spi1RxFifoCtrlAddrLsb : begin 
                             Spi1RxFifoCtrlReg[15:8] <= Data_i[15:8];
                         end
-                        Spi1TxFifo : begin 
-                            Spi1TxFifoReg[15:8] <= Data_i[15:8];
-                        end
-                        Spi1RxFifo : begin 
-                            Spi1RxFifoReg[15:8] <= Data_i[15:8];
-                        end
                         Spi2CtrlAddr : begin 
                             Spi2CtrlReg[15:8] <= Data_i[15:8];
                         end
@@ -670,12 +580,6 @@ always @(posedge Clk_i) begin
                         Spi2RxFifoCtrlAddrLsb : begin 
                             Spi2RxFifoCtrlReg[15:8] <= Data_i[15:8];
                         end
-                        Spi2TxFifo : begin 
-                            Spi2TxFifoReg[15:8] <= Data_i[15:8];
-                        end
-                        Spi2RxFifo : begin 
-                            Spi2RxFifoReg[15:8] <= Data_i[15:8];
-                        end
                         Spi3CtrlAddr : begin 
                             Spi3CtrlReg[15:8] <= Data_i[15:8];
                         end
@@ -694,12 +598,6 @@ always @(posedge Clk_i) begin
                         Spi3RxFifoCtrlAddrLsb : begin 
                             Spi3RxFifoCtrlReg[15:8] <= Data_i[15:8];
                         end
-                        Spi3TxFifo : begin 
-                            Spi3TxFifoReg[15:8] <= Data_i[15:8];
-                        end
-                        Spi3RxFifo : begin 
-                            Spi3RxFifoReg[15:8] <= Data_i[15:8];
-                        end
                         Spi4CtrlAddr : begin 
                             Spi4CtrlReg[15:8] <= Data_i[15:8];
                         end
@@ -718,12 +616,6 @@ always @(posedge Clk_i) begin
                         Spi4RxFifoCtrlAddrLsb : begin 
                             Spi4RxFifoCtrlReg[15:8] <= Data_i[15:8];
                         end
-                        Spi4TxFifo : begin 
-                            Spi4TxFifoReg[15:8] <= Data_i[15:8];
-                        end
-                        Spi4RxFifo : begin 
-                            Spi4RxFifoReg[15:8] <= Data_i[15:8];
-                        end
                         Spi5CtrlAddr : begin 
                             Spi5CtrlReg[15:8] <= Data_i[15:8];
                         end
@@ -742,12 +634,6 @@ always @(posedge Clk_i) begin
                         Spi5RxFifoCtrlAddrLsb : begin 
                             Spi5RxFifoCtrlReg[15:8] <= Data_i[15:8];
                         end
-                        Spi5TxFifo : begin 
-                            Spi5TxFifoReg[15:8] <= Data_i[15:8];
-                        end
-                        Spi5RxFifo : begin 
-                            Spi5RxFifoReg[15:8] <= Data_i[15:8];
-                        end
                         Spi6CtrlAddr : begin 
                             Spi6CtrlReg[15:8] <= Data_i[15:8];
                         end
@@ -766,14 +652,8 @@ always @(posedge Clk_i) begin
                         Spi6RxFifoCtrlAddrLsb : begin 
                             Spi6RxFifoCtrlReg[15:8] <= Data_i[15:8];
                         end
-                        Spi6TxFifo : begin 
-                            Spi6TxFifoReg[15:8] <= Data_i[15:8];
-                        end
-                        Spi6RxFifo : begin 
-                            Spi6RxFifoReg[15:8] <= Data_i[15:8];
-                        end
                         SpiTxRxEn : begin 
-                            SpiTxRxEnReg[15:8] <= Data_i[15:8];
+                            spiTxRxEnReg[15:8] <= Data_i[15:8];
                         end
                         GPIOCtrlAddr : begin 
                             GPIOAReg[15:8] <= Data_i[15:8];
@@ -782,7 +662,7 @@ always @(posedge Clk_i) begin
                             GPIOARegS[15:8] <= Data_i[15:8];
                         end
                         Debug0Addr : begin 
-                            LedReg[15:8] <= Data_i[15:8];
+                            ledReg[15:8] <= Data_i[15:8];
                         end
                     endcase 
                 end
@@ -806,12 +686,6 @@ always @(posedge Clk_i) begin
                         Spi0RxFifoCtrlAddrLsb : begin 
                             Spi0RxFifoCtrlReg[7:0] <= Data_i[7:0];
                         end
-                        Spi0TxFifo : begin 
-                            Spi0TxFifoReg[7:0] <= Data_i[7:0];
-                        end
-                        Spi0RxFifo : begin 
-                            Spi0RxFifoReg[7:0] <= Data_i[7:0];
-                        end
                         Spi1CtrlAddr : begin 
                             Spi1CtrlReg[7:0] <= Data_i[7:0];
                         end
@@ -830,12 +704,6 @@ always @(posedge Clk_i) begin
                         Spi1RxFifoCtrlAddrLsb : begin 
                             Spi1RxFifoCtrlReg[7:0] <= Data_i[7:0];
                         end
-                        Spi1TxFifo : begin 
-                            Spi1TxFifoReg[7:0] <= Data_i[7:0];
-                        end
-                        Spi1RxFifo : begin 
-                            Spi1RxFifoReg[7:0] <= Data_i[7:0];
-                        end
                         Spi2CtrlAddr : begin 
                             Spi2CtrlReg[7:0] <= Data_i[7:0];
                         end
@@ -854,12 +722,6 @@ always @(posedge Clk_i) begin
                         Spi2RxFifoCtrlAddrLsb : begin 
                             Spi2RxFifoCtrlReg[7:0] <= Data_i[7:0];
                         end
-                        Spi2TxFifo : begin 
-                            Spi2TxFifoReg[7:0] <= Data_i[7:0];
-                        end
-                        Spi2RxFifo : begin 
-                            Spi2RxFifoReg[7:0] <= Data_i[7:0];
-                        end
                         Spi3CtrlAddr : begin 
                             Spi3CtrlReg[7:0] <= Data_i[7:0];
                         end
@@ -878,12 +740,6 @@ always @(posedge Clk_i) begin
                         Spi3RxFifoCtrlAddrLsb : begin 
                             Spi3RxFifoCtrlReg[7:0] <= Data_i[7:0];
                         end
-                        Spi3TxFifo : begin 
-                            Spi3TxFifoReg[7:0] <= Data_i[7:0];
-                        end
-                        Spi3RxFifo : begin 
-                            Spi3RxFifoReg[7:0] <= Data_i[7:0];
-                        end
                         Spi4CtrlAddr : begin 
                             Spi4CtrlReg[7:0] <= Data_i[7:0];
                         end
@@ -902,12 +758,6 @@ always @(posedge Clk_i) begin
                         Spi4RxFifoCtrlAddrLsb : begin 
                             Spi4RxFifoCtrlReg[7:0] <= Data_i[7:0];
                         end
-                        Spi4TxFifo : begin 
-                            Spi4TxFifoReg[7:0] <= Data_i[7:0];
-                        end
-                        Spi4RxFifo : begin 
-                            Spi4RxFifoReg[7:0] <= Data_i[7:0];
-                        end
                         Spi5CtrlAddr : begin 
                             Spi5CtrlReg[7:0] <= Data_i[7:0];
                         end
@@ -926,12 +776,6 @@ always @(posedge Clk_i) begin
                         Spi5RxFifoCtrlAddrLsb : begin 
                             Spi5RxFifoCtrlReg[7:0] <= Data_i[7:0];
                         end
-                        Spi5TxFifo : begin 
-                            Spi5TxFifoReg[7:0] <= Data_i[7:0];
-                        end
-                        Spi5RxFifo : begin 
-                            Spi5RxFifoReg[7:0] <= Data_i[7:0];
-                        end
                         Spi6CtrlAddr : begin 
                             Spi6CtrlReg[7:0] <= Data_i[7:0];
                         end
@@ -950,14 +794,8 @@ always @(posedge Clk_i) begin
                         Spi6RxFifoCtrlAddrLsb : begin 
                             Spi6RxFifoCtrlReg[7:0] <= Data_i[7:0];
                         end
-                        Spi6TxFifo : begin 
-                            Spi6TxFifoReg[7:0] <= Data_i[7:0];
-                        end
-                        Spi6RxFifo : begin 
-                            Spi6RxFifoReg[7:0] <= Data_i[7:0];
-                        end
                         SpiTxRxEn : begin 
-                            SpiTxRxEnReg[7:0] <= Data_i[7:0];
+                            spiTxRxEnReg[7:0] <= Data_i[7:0];
                         end
                         GPIOCtrlAddr : begin 
                             GPIOAReg[7:0] <= Data_i[7:0];
@@ -966,7 +804,7 @@ always @(posedge Clk_i) begin
                             GPIOARegS[7:0] <= Data_i[7:0];
                         end
                         Debug0Addr : begin 
-                            LedReg[7:0] <= Data_i[7:0];
+                            ledReg[7:0] <= Data_i[7:0];
                         end
                     endcase
                 end
@@ -1004,12 +842,6 @@ always @(*) begin
             Spi0RxFifoCtrlAddrMsb : begin 
                 ansReg = RxFifoCtrlReg0_i[31:16];
             end
-			Spi0TxFifo : begin 
-				ansReg = Spi0TxFifoReg;
-			end
-			Spi0RxFifo : begin 
-				ansReg = Spi0RxFifoReg;
-			end
 			Spi1CtrlAddr : begin 
 				ansReg = Spi1CtrlReg;
 			end
@@ -1034,12 +866,6 @@ always @(*) begin
             Spi1RxFifoCtrlAddrMsb : begin 
                 ansReg = RxFifoCtrlReg1_i[31:16];
             end
-			Spi1TxFifo : begin 
-				ansReg = Spi1TxFifoReg;
-			end
-			Spi1RxFifo : begin 
-				ansReg = Spi1RxFifoReg;
-			end
 			Spi2CtrlAddr : begin 
 				ansReg = Spi2CtrlReg;
 			end
@@ -1064,12 +890,6 @@ always @(*) begin
             Spi2RxFifoCtrlAddrMsb : begin 
                 ansReg = RxFifoCtrlReg2_i[31:16];
             end
-			Spi2TxFifo : begin 
-				ansReg = Spi2TxFifoReg;
-			end
-			Spi2RxFifo : begin 
-				ansReg = Spi2RxFifoReg;
-			end
 			Spi3CtrlAddr : begin 
 				ansReg = Spi3CtrlReg;
 			end
@@ -1094,12 +914,6 @@ always @(*) begin
             Spi3RxFifoCtrlAddrMsb : begin 
                 ansReg = RxFifoCtrlReg3_i[31:16];
             end
-			Spi3TxFifo : begin 
-				ansReg = Spi3TxFifoReg;
-			end
-			Spi3RxFifo : begin 
-				ansReg = Spi3RxFifoReg;
-			end
 			Spi4CtrlAddr : begin 
 				ansReg = Spi4CtrlReg;
 			end
@@ -1124,12 +938,6 @@ always @(*) begin
             Spi4RxFifoCtrlAddrMsb : begin 
                 ansReg = RxFifoCtrlReg4_i[31:16];
             end
-			Spi4TxFifo : begin 
-				ansReg = Spi4TxFifoReg;
-			end
-			Spi4RxFifo : begin 
-				ansReg = Spi4RxFifoReg;
-			end
 			Spi5CtrlAddr : begin 
 				ansReg = Spi5CtrlReg;
 			end
@@ -1154,12 +962,6 @@ always @(*) begin
             Spi5RxFifoCtrlAddrMsb : begin 
                 ansReg = RxFifoCtrlReg5_i[31:16];
             end
-			Spi5TxFifo : begin 
-				ansReg = Spi5TxFifoReg;
-			end
-			Spi5RxFifo : begin 
-				ansReg = Spi5RxFifoReg;
-			end
 			Spi6CtrlAddr : begin 
 				ansReg = Spi6CtrlReg;
 			end
@@ -1184,14 +986,8 @@ always @(*) begin
             Spi6RxFifoCtrlAddrMsb : begin 
                 ansReg = RxFifoCtrlReg6_i[31:16];
             end
-			Spi6TxFifo : begin 
-				ansReg = Spi6TxFifoReg;
-			end
-			Spi6RxFifo : begin 
-				ansReg = Spi6RxFifoReg;
-			end
 			SpiTxRxEn : begin 
-				ansReg = SpiTxRxEnReg;
+				ansReg = spiTxRxEnReg;
 			end
 			GPIOCtrlAddr : begin 
 				ansReg = GPIOAReg;
@@ -1200,7 +996,7 @@ always @(*) begin
                 ansReg = GPIOARegS;
             end
 			Debug0Addr : begin 
-				ansReg = LedReg;
+				ansReg = ledReg;
 			end
             default : begin 
                 ansReg = 0;

sources_1/new/S5443_3Top.v

@@ -30,7 +30,7 @@ module S5443_3Top
 (
     input Clk123_i,
     input [AddrRegWidth-2:0] SmcAddr_i,
-    inout [CmdRegWidth/2-1:0] SmcData_i,
+    inout [CmdRegWidth/2-1:0] SmcData_io,
     
     input SmcAwe_i,
     input SmcAmsN_i,
@@ -38,12 +38,12 @@ module S5443_3Top
     input SmcAre_i,
     input [1:0] SmcBe_i,
     input SmcAoe_i,
-    output [SpiNum-1:0] Ld_i,
+    output [SpiNum-1:0] Ld_o,
 
     output  Led_o,
    
     output  [SpiNum-1:0] Mosi0_o, 
-    inout  [SpiNum-1:0] Mosi1_io,//inout: when RSPI mode, input; when QSPI mode output; 
+    inout   [SpiNum-1:0] Mosi1_io,//inout: when RSPI mode, input; when QSPI mode output; 
     output  [SpiNum-1:0] Mosi2_o,
     output  [SpiNum-1:0] Mosi3_o,
     output  [SpiNum-1:0] Ss_o,
@@ -59,16 +59,14 @@ module S5443_3Top
 //  REG/WIRE
 //================================================================================
 wire Clk100_i;
-wire [SpiNum-1:0]Sck;
+wire [SpiNum-1:0]sck;
 wire [AddrRegWidth-1:0] addr;
-wire [SpiNum-1:0] Ss; 
-wire [SpiNum-1:0]Mosi0;
-wire [SpiNum-1:0]Mosi1;
-wire [SpiNum-1:0]Mosi2;
-wire [SpiNum-1:0]Mosi3;
+wire [SpiNum-1:0] ss; 
+wire [SpiNum-1:0]mosi0;
+wire [SpiNum-1:0]mosi1;
+wire [SpiNum-1:0]mosi2;
+wire [SpiNum-1:0]mosi3;
 wire [SpiNum-1:0] ten;
-wire clk80;
-wire clk61;
 wire initRst;
 wire gclk;
 wire [0:7] baudRate [SpiNum-1:0];
@@ -124,8 +122,6 @@ wire [CmdRegWidth-1:0] spi2CsDelay;
 wire [CmdRegWidth-1:0] spi2CsCtrl;
 wire [CmdRegWidth-1:0] spi2TxFifoCtrl;
 wire [CmdRegWidth-1:0] spi2RxFifoCtrl;
-wire [CmdRegWidth-1:0] spi2TxFifo;
-wire [CmdRegWidth-1:0] Spi2RxFifo;
 wire [CmdRegWidth-1:0] spi2TxFifoCtrlReg;
 wire [CmdRegWidth-1:0] spi2RxFifoCtrlReg;
 
@@ -137,8 +133,6 @@ wire [CmdRegWidth-1:0] spi3CsDelay;
 wire [CmdRegWidth-1:0] spi3CsCtrl;
 wire [CmdRegWidth-1:0] spi3TxFifoCtrl;
 wire [CmdRegWidth-1:0] spi3RxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi3TxFifo;
-wire [CmdRegWidth-1:0] Spi3RxFifo;
 wire [CmdRegWidth-1:0] spi3TxFifoCtrlReg;
 wire [CmdRegWidth-1:0] spi3RxFifoCtrlReg;
 
@@ -149,8 +143,6 @@ wire [CmdRegWidth-1:0] spi4CsDelay;
 wire [CmdRegWidth-1:0] spi4CsCtrl;
 wire [CmdRegWidth-1:0] spi4TxFifoCtrl;
 wire [CmdRegWidth-1:0] spi4RxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi4TxFifo;
-wire [CmdRegWidth-1:0] Spi4RxFifo;
 wire [CmdRegWidth-1:0] spi4TxFifoCtrlReg;
 wire [CmdRegWidth-1:0] spi4RxFifoCtrlReg;
 
@@ -161,8 +153,6 @@ wire [CmdRegWidth-1:0] spi5CsDelay;
 wire [CmdRegWidth-1:0] spi5CsCtrl;
 wire [CmdRegWidth-1:0] spi5TxFifoCtrl;
 wire [CmdRegWidth-1:0] spi5RxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi5TxFifo;
-wire [CmdRegWidth-1:0] Spi5RxFifo;
 wire [CmdRegWidth-1:0] spi5TxFifoCtrlReg;
 wire [CmdRegWidth-1:0] spi5RxFifoCtrlReg;
 
@@ -173,13 +163,11 @@ wire [CmdRegWidth-1:0] spi6CsDelay;
 wire [CmdRegWidth-1:0] spi6CsCtrl;
 wire [CmdRegWidth-1:0] spi6TxFifoCtrl;
 wire [CmdRegWidth-1:0] spi6RxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi6TxFifo;
-wire [CmdRegWidth-1:0] Spi6RxFifo;
 wire [CmdRegWidth-1:0] spi6TxFifoCtrlReg;
 wire [CmdRegWidth-1:0] spi6RxFifoCtrlReg;
 
 
-wire [CmdRegWidth-1:0] SpiTxRxEn;
+wire [CmdRegWidth-1:0] spiTxRxEn;
 wire [CmdRegWidth-1:0] GPIOA;
 
 
@@ -213,7 +201,7 @@ wire [0:7]  wordCntRx [SpiNum-1:0];
 wire [SpiNum-1:0] CS0;
 wire [SpiNum-1:0] CS1;
 
-wire [SpiNum-1:0] Assel;
+wire [SpiNum-1:0] assel;
 
 wire	[SpiNum-1:0]	spiClkBus;
 wire	[SpiNum-1:0]	spiSyncRst;
@@ -229,18 +217,18 @@ wire [SpiNum-1:0] valToTxFifoRead;
 
 
 // SPI mode choice 
-wire [SpiNum-1:0] SckR; 
-wire [SpiNum-1:0] SsR;
-wire [SpiNum-1:0] Mosi0R;
+wire [SpiNum-1:0] sckR; 
+wire [SpiNum-1:0] ssR;
+wire [SpiNum-1:0] mosi0R;
 wire [SpiNum-1:0] valReg;
 wire [SpiNum-1:0] valToTxR;
 wire [SpiNum-1:0] valToRxR;
 wire [0:31] dataToRxFifoR [SpiNum-1:0];
 
 
-wire [SpiNum-1:0] SckQ;
-wire [SpiNum-1:0] SsQ;
-wire [SpiNum-1:0] Mosi0Q;
+wire [SpiNum-1:0] sckQ;
+wire [SpiNum-1:0] ssQ;
+wire [SpiNum-1:0] mosi0Q;
 wire [SpiNum-1:0] valToTxQ;
 wire [SpiNum-1:0] valToRxQ;
 wire [0:31] dataToRxFifoQ [SpiNum-1:0];
@@ -251,47 +239,39 @@ wire Clk100_o;
 wire Clk40_o;
 
 wire smcValComb; 
-
-
-
-
-
-
-
-	
 wire	[CmdRegWidth/2-1:0]	ansData;
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
 assign addr = {SmcAddr_i, 1'b0};
 assign smcValComb = (!SmcAmsN_i && !SmcAwe_i) ? 1'b1 : 1'b0;
-assign ten = SpiTxRxEn[6:0];
-assign Mosi1_io[0] =(SpiDir_o[0])?Mosi1[0]:1'bz;
-assign Mosi1_io[1] =(SpiDir_o[1])?Mosi1[1]:1'bz;
-assign Mosi1_io[2] =(SpiDir_o[2])?Mosi1[2]:1'bz;
-assign Mosi1_io[3] =(SpiDir_o[3])?Mosi1[3]:1'bz;
-assign Mosi1_io[4] =(SpiDir_o[4])?Mosi1[4]:1'bz;
-assign Mosi1_io[5] =(SpiDir_o[5])?Mosi1[5]:1'bz;
-assign Mosi1_io[6] =(SpiDir_o[6])?Mosi1[6]:1'bz;
-assign Mosi2_o = Mosi2;
-assign Mosi3_o = Mosi3;
-assign Ss_o[0] = (Assel[0])? ((CS0[0])? Ss[0]:~Ss[0]):CS0[0];
-assign Ss_o[1] = (Assel[1])? ((CS0[1])? Ss[1]:~Ss[1]):CS0[1];
-assign Ss_o[2] = (Assel[2])? ((CS0[2])? Ss[2]:~Ss[2]):CS0[2];
-assign Ss_o[3] = (Assel[3])? ((CS0[3])? Ss[3]:~Ss[3]):CS0[3];
-assign Ss_o[4] = (Assel[4])? ((CS0[4])? Ss[4]:~Ss[4]):CS0[4];
-assign Ss_o[5] = (Assel[5])? ((CS0[5])? Ss[5]:~Ss[5]):CS0[5];
-assign Ss_o[6] = (Assel[6])? ((CS0[6])? Ss[6]:~Ss[6]):CS0[6];
-assign SsFlash_o[0] = (Assel[0])?(CS1[0]? Ss[0]:~Ss[0]):CS1[0];
-assign SsFlash_o[1] = (Assel[1])?(CS1[1]? Ss[1]:~Ss[1]):CS1[1];
-assign SsFlash_o[2] = (Assel[2])?(CS1[2]? Ss[2]:~Ss[2]):CS1[2];
-assign SsFlash_o[3] = (Assel[3])?(CS1[3]? Ss[3]:~Ss[3]):CS1[3];
-assign SsFlash_o[4] = (Assel[4])?(CS1[4]? Ss[4]:~Ss[4]):CS1[4];
-assign SsFlash_o[5] = (Assel[5])?(CS1[5]? Ss[5]:~Ss[5]):CS1[5];
-assign SsFlash_o[6] = (Assel[6])?(CS1[6]? Ss[6]:~Ss[6]):CS1[6];
-assign Sck_o = Sck;
-
-assign widthSel[0] = spi0CtrlRR[6:5];
+assign ten = spiTxRxEn[6:0];
+assign Mosi1_io[0] =(SpiDir_o[0])?mosi1[0]:1'bz;
+assign Mosi1_io[1] =(SpiDir_o[1])?mosi1[1]:1'bz;
+assign Mosi1_io[2] =(SpiDir_o[2])?mosi1[2]:1'bz;
+assign Mosi1_io[3] =(SpiDir_o[3])?mosi1[3]:1'bz;
+assign Mosi1_io[4] =(SpiDir_o[4])?mosi1[4]:1'bz;
+assign Mosi1_io[5] =(SpiDir_o[5])?mosi1[5]:1'bz;
+assign Mosi1_io[6] =(SpiDir_o[6])?mosi1[6]:1'bz;
+assign Mosi2_o = mosi2;
+assign Mosi3_o = mosi3;
+assign Ss_o[0] = (assel[0])? ((CS0[0])? ss[0]:~ss[0]):CS0[0];
+assign Ss_o[1] = (assel[1])? ((CS0[1])? ss[1]:~ss[1]):CS0[1];
+assign Ss_o[2] = (assel[2])? ((CS0[2])? ss[2]:~ss[2]):CS0[2];
+assign Ss_o[3] = (assel[3])? ((CS0[3])? ss[3]:~ss[3]):CS0[3];
+assign Ss_o[4] = (assel[4])? ((CS0[4])? ss[4]:~ss[4]):CS0[4];
+assign Ss_o[5] = (assel[5])? ((CS0[5])? ss[5]:~ss[5]):CS0[5];
+assign Ss_o[6] = (assel[6])? ((CS0[6])? ss[6]:~ss[6]):CS0[6];
+assign SsFlash_o[0] = (assel[0])?(CS1[0]? ss[0]:~ss[0]):CS1[0];
+assign SsFlash_o[1] = (assel[1])?(CS1[1]? ss[1]:~ss[1]):CS1[1];
+assign SsFlash_o[2] = (assel[2])?(CS1[2]? ss[2]:~ss[2]):CS1[2];
+assign SsFlash_o[3] = (assel[3])?(CS1[3]? ss[3]:~ss[3]):CS1[3];
+assign SsFlash_o[4] = (assel[4])?(CS1[4]? ss[4]:~ss[4]):CS1[4];
+assign SsFlash_o[5] = (assel[5])?(CS1[5]? ss[5]:~ss[5]):CS1[5];
+assign SsFlash_o[6] = (assel[6])?(CS1[6]? ss[6]:~ss[6]):CS1[6];
+assign Sck_o = sck;
+
+assign widthSel[0] = spi0Ctrl[6:5];
 assign widthSel[1] = spi1Ctrl[6:5];
 assign widthSel[2] = spi2Ctrl[6:5];
 assign widthSel[3] = spi3Ctrl[6:5];
@@ -299,7 +279,7 @@ assign widthSel[4] = spi4Ctrl[6:5];
 assign widthSel[5] = spi5Ctrl[6:5];
 assign widthSel[6] = spi6Ctrl[6:5];
 
-assign spiMode[0] = spi0CtrlRR[7];
+assign spiMode[0] = spi0Ctrl[7];
 assign spiMode[1] = spi1Ctrl[7];
 assign spiMode[2] = spi2Ctrl[7];
 assign spiMode[3] = spi3Ctrl[7];
@@ -308,7 +288,7 @@ assign spiMode[5] = spi5Ctrl[7];
 assign spiMode[6] = spi6Ctrl[7];
 
 
-assign CPOL[0] = spi0CtrlRR[2];
+assign CPOL[0] = spi0Ctrl[2];
 assign CPOL[1] = spi1Ctrl[2];
 assign CPOL[2] = spi2Ctrl[2];
 assign CPOL[3] = spi3Ctrl[2];
@@ -316,7 +296,7 @@ assign CPOL[4] = spi4Ctrl[2];
 assign CPOL[5] = spi5Ctrl[2];
 assign CPOL[6] = spi6Ctrl[2];
 
-assign CPHA[0] = spi0CtrlRR[1];
+assign CPHA[0] = spi0Ctrl[1];
 assign CPHA[1] = spi1Ctrl[1];
 assign CPHA[2] = spi2Ctrl[1];
 assign CPHA[3] = spi3Ctrl[1];
@@ -324,7 +304,7 @@ assign CPHA[4] = spi4Ctrl[1];
 assign CPHA[5] = spi5Ctrl[1];
 assign CPHA[6] = spi6Ctrl[1];
 
-assign endianSel[0] = spi0CtrlRR[8];
+assign endianSel[0] = spi0Ctrl[8];
 assign endianSel[1] = spi1Ctrl[8];
 assign endianSel[2] = spi2Ctrl[8];
 assign endianSel[3] = spi3Ctrl[8];
@@ -332,7 +312,7 @@ assign endianSel[4] = spi4Ctrl[8];
 assign endianSel[5] = spi5Ctrl[8];
 assign endianSel[6] = spi6Ctrl[8];
 
-assign selSt[0] = spi0CtrlRR[4];
+assign selSt[0] = spi0Ctrl[4];
 assign selSt[1] = spi1Ctrl[4];
 assign selSt[2] = spi2Ctrl[4];
 assign selSt[3] = spi3Ctrl[4];
@@ -340,15 +320,15 @@ assign selSt[4] = spi4Ctrl[4];
 assign selSt[5] = spi5Ctrl[4];
 assign selSt[6] = spi6Ctrl[4];
 
-assign Assel[0] = spi0CtrlRR[3];
-assign Assel[1] = spi1Ctrl[3];
-assign Assel[2] = spi2Ctrl[3];
-assign Assel[3] = spi3Ctrl[3];
-assign Assel[4] = spi4Ctrl[3];
-assign Assel[5] = spi5Ctrl[3];
-assign Assel[6] = spi6Ctrl[3];
+assign assel[0] = spi0Ctrl[3];
+assign assel[1] = spi1Ctrl[3];
+assign assel[2] = spi2Ctrl[3];
+assign assel[3] = spi3Ctrl[3];
+assign assel[4] = spi4Ctrl[3];
+assign assel[5] = spi5Ctrl[3];
+assign assel[6] = spi6Ctrl[3];
 
-assign stopDelay[0] = spi0CsDelayRR[7:2];
+assign stopDelay[0] = spi0CsDelay[7:2];
 assign stopDelay[1] = spi1CsDelay[7:2];
 assign stopDelay[2] = spi2CsDelay[7:2];
 assign stopDelay[3] = spi3CsDelay[7:2];
@@ -356,7 +336,7 @@ assign stopDelay[4] = spi4CsDelay[7:2];
 assign stopDelay[5] = spi5CsDelay[7:2];
 assign stopDelay[6] = spi6CsDelay[7:2];
 
-assign leadx[0] = spi0CsDelayRR[1];
+assign leadx[0] = spi0CsDelay[1];
 assign leadx[1] = spi1CsDelay[1];
 assign leadx[2] = spi2CsDelay[1];
 assign leadx[3] = spi3CsDelay[1];
@@ -364,7 +344,7 @@ assign leadx[4] = spi4CsDelay[1];
 assign leadx[5] = spi5CsDelay[1];
 assign leadx[6] = spi6CsDelay[1];
 
-assign lag[0] = spi0CsDelayRR[0];
+assign lag[0] = spi0CsDelay[0];
 assign lag[1] = spi1CsDelay[0];
 assign lag[2] = spi2CsDelay[0];
 assign lag[3] = spi3CsDelay[0];
@@ -372,7 +352,7 @@ assign lag[4] = spi4CsDelay[0];
 assign lag[5] = spi5CsDelay[0];
 assign lag[6] = spi6CsDelay[0];
 
-assign baudRate[0] = spi0ClkRR[7:0];
+assign baudRate[0] = spi0Clk[7:0];
 assign baudRate[1] = spi1Clk[7:0];
 assign baudRate[2] = spi2Clk[7:0];
 assign baudRate[3] = spi3Clk[7:0];
@@ -389,7 +369,7 @@ assign SpiRst_o[4] = GPIOA[4];
 assign SpiRst_o[5] = GPIOA[5];
 assign SpiRst_o[6] = GPIOA[6];
 
-assign fifoRxRst[0] = spi0RxFifoCtrlRR[0];
+assign fifoRxRst[0] = spi0RxFifoCtrl[0];
 assign fifoRxRst[1] = spi1RxFifoCtrl[0];
 assign fifoRxRst[2] = spi2RxFifoCtrl[0];
 assign fifoRxRst[3] = spi3RxFifoCtrl[0];
@@ -397,7 +377,7 @@ assign fifoRxRst[4] = spi4RxFifoCtrl[0];
 assign fifoRxRst[5] = spi5RxFifoCtrl[0];
 assign fifoRxRst[6] = spi6RxFifoCtrl[0];
 
-assign fifoTxRst[0] = spi0TxFifoCtrlRR[0];
+assign fifoTxRst[0] = spi0TxFifoCtrl[0];
 assign fifoTxRst[1] = spi1TxFifoCtrl[0];
 assign fifoTxRst[2] = spi2TxFifoCtrl[0];
 assign fifoTxRst[3] = spi3TxFifoCtrl[0];
@@ -405,16 +385,16 @@ assign fifoTxRst[4] = spi4TxFifoCtrl[0];
 assign fifoTxRst[5] = spi5TxFifoCtrl[0];
 assign fifoTxRst[6] = spi6TxFifoCtrl[0];
 
-assign Ld_i[0] = GPIOA[16];
-assign Ld_i[1] = GPIOA[17];
-assign Ld_i[2] = GPIOA[18];
-assign Ld_i[3] = GPIOA[19];
-assign Ld_i[4] = GPIOA[20];
-assign Ld_i[5] = GPIOA[21];
-assign Ld_i[6] = GPIOA[22];
-assign LD_o = Ld_i[0]&Ld_i[1]&Ld_i[2]&Ld_i[3]&Ld_i[4]&Ld_i[5]&Ld_i[6];
+assign Ld_o[0] = GPIOA[16];
+assign Ld_o[1] = GPIOA[17];
+assign Ld_o[2] = GPIOA[18];
+assign Ld_o[3] = GPIOA[19];
+assign Ld_o[4] = GPIOA[20];
+assign Ld_o[5] = GPIOA[21];
+assign Ld_o[6] = GPIOA[22];
+assign LD_o = Ld_o[0]&Ld_o[1]&Ld_o[2]&Ld_o[3]&Ld_o[4]&Ld_o[5]&Ld_o[6];
 
-assign wordCntRx[0] = spi0RxFifoCtrlRR[15:8];
+assign wordCntRx[0] = spi0RxFifoCtrl[15:8];
 assign wordCntRx[1] = spi1RxFifoCtrl[15:8];
 assign wordCntRx[2] = spi2RxFifoCtrl[15:8];
 assign wordCntRx[3] = spi3RxFifoCtrl[15:8];
@@ -422,7 +402,7 @@ assign wordCntRx[4] = spi4RxFifoCtrl[15:8];
 assign wordCntRx[5] = spi5RxFifoCtrl[15:8];
 assign wordCntRx[6] = spi6RxFifoCtrl[15:8];
 
-assign wordCntTx[0] = spi0TxFifoCtrlRR[15:8];
+assign wordCntTx[0] = spi0TxFifoCtrl[15:8];
 assign wordCntTx[1] = spi1TxFifoCtrl[15:8];
 assign wordCntTx[2] = spi2TxFifoCtrl[15:8];
 assign wordCntTx[3] = spi3TxFifoCtrl[15:8];
@@ -431,7 +411,7 @@ assign wordCntTx[5] = spi5TxFifoCtrl[15:8];
 assign wordCntTx[6] = spi6TxFifoCtrl[15:8];
 
 
-assign CS0[0] = spi0CsCtrlRR[0];
+assign CS0[0] = spi0CsCtrl[0];
 assign CS0[1] = spi1CsCtrl[0];
 assign CS0[2] = spi2CsCtrl[0];
 assign CS0[3] = spi3CsCtrl[0];
@@ -439,7 +419,7 @@ assign CS0[4] = spi4CsCtrl[0];
 assign CS0[5] = spi5CsCtrl[0];
 assign CS0[6] = spi6CsCtrl[0];
 
-assign CS1[0] = spi0CsCtrlRR[1];
+assign CS1[0] = spi0CsCtrl[1];
 assign CS1[1] = spi1CsCtrl[1];
 assign CS1[2] = spi2CsCtrl[1];
 assign CS1[3] = spi3CsCtrl[1];
@@ -448,13 +428,13 @@ assign CS1[5] = spi5CsCtrl[1];
 assign CS1[6] = spi6CsCtrl[1];
 
 
-assign Ss[0] = (spiMode[0])? SsQ[0]:SsR[0];
-assign Ss[1] = (spiMode[1])? SsQ[1]:SsR[1];
-assign Ss[2] = (spiMode[2])? SsQ[2]:SsR[2];
-assign Ss[3] = (spiMode[3])? SsQ[3]:SsR[3];
-assign Ss[4] = (spiMode[4])? SsQ[4]:SsR[4];
-assign Ss[5] = (spiMode[5])? SsQ[5]:SsR[5];
-assign Ss[6] = (spiMode[6])? SsQ[6]:SsR[6];
+assign ss[0] = (spiMode[0])? ssQ[0]:ssR[0];
+assign ss[1] = (spiMode[1])? ssQ[1]:ssR[1];
+assign ss[2] = (spiMode[2])? ssQ[2]:ssR[2];
+assign ss[3] = (spiMode[3])? ssQ[3]:ssR[3];
+assign ss[4] = (spiMode[4])? ssQ[4]:ssR[4];
+assign ss[5] = (spiMode[5])? ssQ[5]:ssR[5];
+assign ss[6] = (spiMode[6])? ssQ[6]:ssR[6];
 
 assign SpiDir_o[0] = (spiMode[0])? 1'b1 : 1'b0 ;
 assign SpiDir_o[1] = (spiMode[1])? 1'b1 : 1'b0 ;
@@ -465,29 +445,29 @@ assign SpiDir_o[5] = (spiMode[5])? 1'b1 : 1'b0 ;
 assign SpiDir_o[6] = (spiMode[6])? 1'b1 : 1'b0 ;
 
 
-assign Sck[0] =  (spiMode[0])?SckQ[0]:SckR[0];
-assign Sck[1] =  (spiMode[1])?SckQ[1]:SckR[1];
-assign Sck[2] =  (spiMode[2])?SckQ[2]:SckR[2];
-assign Sck[3] =  (spiMode[3])?SckQ[3]:SckR[3];
-assign Sck[4] =  (spiMode[4])?SckQ[4]:SckR[4];
-assign Sck[5] =  (spiMode[5])?SckQ[5]:SckR[5];
-assign Sck[6] =  (spiMode[6])?SckQ[6]:SckR[6];
+assign sck[0] =  (spiMode[0])?sckQ[0]:sckR[0];
+assign sck[1] =  (spiMode[1])?sckQ[1]:sckR[1];
+assign sck[2] =  (spiMode[2])?sckQ[2]:sckR[2];
+assign sck[3] =  (spiMode[3])?sckQ[3]:sckR[3];
+assign sck[4] =  (spiMode[4])?sckQ[4]:sckR[4];
+assign sck[5] =  (spiMode[5])?sckQ[5]:sckR[5];
+assign sck[6] =  (spiMode[6])?sckQ[6]:sckR[6];
 
-assign Mosi0[0] =  (spiMode[0])?Mosi0Q[0]:Mosi0R[0];
-assign Mosi0[1] =  (spiMode[1])?Mosi0Q[1]:Mosi0R[1];
-assign Mosi0[2] =  (spiMode[2])?Mosi0Q[2]:Mosi0R[2];
-assign Mosi0[3] =  (spiMode[3])?Mosi0Q[3]:Mosi0R[3];
-assign Mosi0[4] =  (spiMode[4])?Mosi0Q[4]:Mosi0R[4];
-assign Mosi0[5] =  (spiMode[5])?Mosi0Q[5]:Mosi0R[5];
-assign Mosi0[6] =  (spiMode[6])?Mosi0Q[6]:Mosi0R[6];
+assign mosi0[0] =  (spiMode[0])?mosi0Q[0]:mosi0R[0];
+assign mosi0[1] =  (spiMode[1])?mosi0Q[1]:mosi0R[1];
+assign mosi0[2] =  (spiMode[2])?mosi0Q[2]:mosi0R[2];
+assign mosi0[3] =  (spiMode[3])?mosi0Q[3]:mosi0R[3];
+assign mosi0[4] =  (spiMode[4])?mosi0Q[4]:mosi0R[4];
+assign mosi0[5] =  (spiMode[5])?mosi0Q[5]:mosi0R[5];
+assign mosi0[6] =  (spiMode[6])?mosi0Q[6]:mosi0R[6];
 
-assign Mosi0_o[0] = Mosi0[0];
-assign Mosi0_o[1] = Mosi0[1];
-assign Mosi0_o[2] = Mosi0[2];
-assign Mosi0_o[3] = Mosi0[3];
-assign Mosi0_o[4] = Mosi0[4];
-assign Mosi0_o[5] = Mosi0[5];
-assign Mosi0_o[6] = Mosi0[6];
+assign Mosi0_o[0] = mosi0[0];
+assign Mosi0_o[1] = mosi0[1];
+assign Mosi0_o[2] = mosi0[2];
+assign Mosi0_o[3] = mosi0[3];
+assign Mosi0_o[4] = mosi0[4];
+assign Mosi0_o[5] = mosi0[5];
+assign Mosi0_o[6] = mosi0[6];
 
 
 assign valToTxFifoRead[0] =  (spiMode[0])?valToTxQ[0]:valToTxR[0];
@@ -506,14 +486,6 @@ assign valToRxFifo[4] = valToRxR[4];
 assign valToRxFifo[5] = valToRxR[5];
 assign valToRxFifo[6] = valToRxR[6];
 
-// assign dataToRxFifo[0] = (spiMode)? dataToRxFifoQ[0]:dataToRxFifoR[0];
-// assign dataToRxFifo[1] = (spiMode)? dataToRxFifoQ[1]:dataToRxFifoR[1];
-// assign dataToRxFifo[2] = (spiMode)? dataToRxFifoQ[2]:dataToRxFifoR[2];
-// assign dataToRxFifo[3] = (spiMode)? dataToRxFifoQ[3]:dataToRxFifoR[3];
-// assign dataToRxFifo[4] = (spiMode)? dataToRxFifoQ[4]:dataToRxFifoR[4];
-// assign dataToRxFifo[5] = (spiMode)? dataToRxFifoQ[5]:dataToRxFifoR[5];
-// assign dataToRxFifo[6] = (spiMode)? dataToRxFifoQ[6]:dataToRxFifoR[6];
-
 assign dataToRxFifo[0] = dataToRxFifoR[0];
 assign dataToRxFifo[1] = dataToRxFifoR[1];
 assign dataToRxFifo[2] = dataToRxFifoR[2];
@@ -540,7 +512,7 @@ assign spi6RxFifoCtrlReg = rxFifoCtrlReg[6];
 
 
 
-	assign	SmcData_i	=	(!SmcAre_i && !SmcAoe_i)?muxedData:16'bz;
+assign	SmcData_io	=	(!SmcAre_i && !SmcAoe_i)?muxedData:16'bz;
 
 //================================================================================
 //  CODING
@@ -573,25 +545,6 @@ BUFG BUFG_inst (
    .I(Clk123_i)  // 1-bit input: Clock input
 );
 
-// SmcRx	SmcRx
-// (
-// 	.Clk_i		(gclk),
-// 	.Rst_i		(initRst),
-
-// 	.SmcD_i		(SmcData_i),
-// 	.SmcA_i		(SmcAddr_i),
-// 	.SmcAwe_i	(SmcAwe_i),
-// 	.SmcAmsN_i	(SmcAmsN_i),
-// 	.SmcAoe_i	(SmcAoe_i),
-// 	.SmcAre_i	(SmcAre_i),
-// 	.SmcBe_i	(SmcBe_i),
-	
-// 	.AnsData_i	(muxedData),
-	
-// 	.Data_o		(smcData),
-// 	.Addr_o		(smcAddr),
-// 	.Val_o		(smcVal)
-// );
 
 DataMuxer DataMuxer
 (
@@ -599,7 +552,7 @@ DataMuxer DataMuxer
     .Rst_i	(initRst),
 
 	.SmcVal_i	(smcValComb),
-	.SmcData_i	(SmcData_i),
+	.SmcData_i	(SmcData_io),
     .SmcAddr_i	(addr),
 
 	.ToRegMapVal_o	(toRegMapVal),
@@ -647,8 +600,6 @@ RegMap_inst
     .Spi0CsCtrlReg_o(spi0CsCtrl),
     .Spi0TxFifoCtrlReg_o(spi0TxFifoCtrl),
     .Spi0RxFifoCtrlReg_o(spi0RxFifoCtrl),
-    .Spi0TxFifoReg_o(spi0TxFifo),
-    .Spi0RxFifoReg_o(spi0RxFifo),
     //Spi1
     .Spi1CtrlReg_o(spi1Ctrl),
     .Spi1ClkReg_o(spi1Clk),
@@ -656,8 +607,6 @@ RegMap_inst
     .Spi1CsCtrlReg_o(spi1CsCtrl),
     .Spi1TxFifoCtrlReg_o(spi1TxFifoCtrl),
     .Spi1RxFifoCtrlReg_o(spi1RxFifoCtrl),
-    .Spi1TxFifoReg_o(spi1TxFifo),
-    .Spi1RxFifoReg_o(spi1RxFifo),
     //Spi2
     .Spi2CtrlReg_o(spi2Ctrl),
     .Spi2ClkReg_o(spi2Clk),
@@ -665,8 +614,6 @@ RegMap_inst
     .Spi2CsCtrlReg_o(spi2CsCtrl),
     .Spi2TxFifoCtrlReg_o(spi2TxFifoCtrl),
     .Spi2RxFifoCtrlReg_o(spi2RxFifoCtrl),
-    .Spi2TxFifoReg_o(spi2TxFifo),
-    .Spi2RxFifoReg_o(Spi2RxFifo),
     //Spi3
     .Spi3CtrlReg_o(spi3Ctrl),
     .Spi3ClkReg_o(spi3Clk),
@@ -674,8 +621,6 @@ RegMap_inst
     .Spi3CsCtrlReg_o(spi3CsCtrl),
     .Spi3TxFifoCtrlReg_o(spi3TxFifoCtrl),
     .Spi3RxFifoCtrlReg_o(spi3RxFifoCtrl),
-    .Spi3TxFifoReg_o(Spi3TxFifo),
-    .Spi3RxFifoReg_o(Spi3RxFifo),
     //Spi4
     .Spi4CtrlReg_o(spi4Ctrl),
     .Spi4ClkReg_o(spi4Clk),
@@ -683,8 +628,6 @@ RegMap_inst
     .Spi4CsCtrlReg_o(spi4CsCtrl),
     .Spi4TxFifoCtrlReg_o(spi4TxFifoCtrl),
     .Spi4RxFifoCtrlReg_o(spi4RxFifoCtrl),
-    .Spi4TxFifoReg_o(Spi4TxFifo),
-    .Spi4RxFifoReg_o(Spi4RxFifo),
     //Spi5
     .Spi5CtrlReg_o(spi5Ctrl),
     .Spi5ClkReg_o(spi5Clk),
@@ -692,8 +635,6 @@ RegMap_inst
     .Spi5CsCtrlReg_o(spi5CsCtrl),
     .Spi5TxFifoCtrlReg_o(spi5TxFifoCtrl),
     .Spi5RxFifoCtrlReg_o(spi5RxFifoCtrl),
-    .Spi5TxFifoReg_o(Spi5TxFifo),
-    .Spi5RxFifoReg_o(Spi5RxFifo),
     //Spi6
     .Spi6CtrlReg_o(spi6Ctrl),
     .Spi6ClkReg_o(spi6Clk),
@@ -701,36 +642,11 @@ RegMap_inst
     .Spi6CsCtrlReg_o(spi6CsCtrl),
     .Spi6TxFifoCtrlReg_o(spi6TxFifoCtrl),
     .Spi6RxFifoCtrlReg_o(spi6RxFifoCtrl),
-    .Spi6TxFifoReg_o(Spi6TxFifo),
-    .Spi6RxFifoReg_o(Spi6RxFifo),
-
-    .SpiTxRxEnReg_o(SpiTxRxEn),
+    .SpiTxRxEnReg_o(spiTxRxEn),
     .GPIOAReg_o(GPIOA)
 );
 
 
-        Cdc Sync (
-    .Clk_i(gclk),
-    .Spi0CtrlReg_i(spi0Ctrl),
-    .Spi0ClkReg_i(spi0Clk),
-    .Spi0CsDelayReg_i(spi0CsDelay),
-    .Spi0CsCtrlReg_i(spi0CsCtrl),
-    .Spi0TxFifoCtrlReg_i(spi0TxFifoCtrl),
-    .Spi0RxFifoCtrlReg_i(spi0RxFifoCtrl),
-    .AnsData_i(ansData),
-    .Spi0CtrlRR_o(spi0CtrlRR),
-    .Spi0ClkRR_o(spi0ClkRR),
-    .Spi0CsDelayRR_o(spi0CsDelayRR),
-    .Spi0CsCtrlRR_o(spi0CsCtrlRR),
-    .Spi0TxFifoCtrlRR_o(spi0TxFifoCtrlRR),
-    .Spi0RxFifoCtrlRR_o(spi0RxFifoCtrlRR),
-    .AnsDataRR_o(ansDataRR)
-
-
-);
-
-
-
 MmcmWrapper #(
     .SpiNum(SpiNum) 
 
@@ -796,9 +712,9 @@ generate
             .Start_i(ten[i]),
             .Rst_i(initRstGen[i]| spiMode[i]),
             .SPIdata(toSpiData[i]),
-            .Sck_o(SckR[i]),
-            .Ss_o(SsR[i]),
-            .Mosi0_o(Mosi0R[i]),
+            .Sck_o(sckR[i]),
+            .Ss_o(ssR[i]),
+            .Mosi0_o(mosi0R[i]),
             .WidthSel_i(widthSel[i]),
             .PulsePol_i(CPOL[i]),
             .CPHA_i(CPHA[i]),
@@ -820,8 +736,8 @@ generate
         SPIs SPIs_inst (
             .Clk_i(spiClkBus[i]),
             .Rst_i(initRstGen[i]|SpiRst_o[i]| spiMode[i]),
-            .Sck_i(SckR[i]),
-            .Ss_i(SsR[i]),
+            .Sck_i(sckR[i]),
+            .Ss_i(ssR[i]),
             .Mosi0_i(Mosi1_io[i]),
             .WidthSel_i(widthSel[i]),
             .SELST_i(selSt[i]),
@@ -837,12 +753,12 @@ generate
 			.SpiDataVal_i	(toSpiVal),
             // .SPIdata(32'h2aaa00aa),
             .SPIdata(toSpiData[i]),
-            .Sck_o(SckQ[i]),
-            .Ss_o(SsQ[i]),
-            .Mosi0_i(Mosi0Q[i]),
-            .Mosi1_i(Mosi1[i]),
-            .Mosi2_i(Mosi2[i]),
-            .Mosi3_i(Mosi3[i]),
+            .Sck_o(sckQ[i]),
+            .Ss_o(ssQ[i]),
+            .Mosi0_i(mosi0Q[i]),
+            .Mosi1_i(mosi1[i]),
+            .Mosi2_i(mosi2[i]),
+            .Mosi3_i(mosi3[i]),
             .WidthSel_i(widthSel[i]),
             .PulsePol_i(CPOL[i]),
             .CPHA_i(CPHA[i]),
@@ -856,12 +772,12 @@ generate
         // QuadSPIs QuadSPIs_inst (
         //     .Clk_i(Clk40_o),
         //     .Rst_i(initRstGen[i]|SpiRst_o[i]| !spiMode[i]),
-        //     .Sck_i(SckQ[i]),
-        //     .Ss_i(SsQ[i]),
-        //     .Mosi0_i(Mosi0Q[i]),
-        //     .Mosi1_i(Mosi1[i]),
-        //     .Mosi2_i(Mosi2[i]),
-        //     .Mosi3_i(Mosi3[i]),
+        //     .Sck_i(sckQ[i]),
+        //     .Ss_i(ssQ[i]),
+        //     .Mosi0_i(mosi0Q[i]),
+        //     .Mosi1_i(mosi1[i]),
+        //     .Mosi2_i(mosi2[i]),
+        //     .Mosi3_i(mosi3[i]),
         //     .WidthSel_i(widthSel[i]),
         //     .SELST_i(selSt[i]),
         //     .DataToRxFifo_o(dataToRxFifoQ[i]),

sources_1/new/SRAM/QuadSPIs.v

@@ -1,258 +0,0 @@
-module QuadSPIs (
-    input Clk_i,
-    input Rst_i,
-
-    input Sck_i,
-    input Ss_i,
-    input Mosi0_i,
-    input Mosi1_i,
-    input Mosi2_i,
-    input Mosi3_i,
-
-    input [1:0] WidthSel_i,
-    input SELST_i,
-    input EndianSel_i,
-   
-
-    output reg [23:0] Data_o,
-    output reg [7:0] Addr_o,
-      output [31:0] DataToRxFifo_o,
-    output reg Val_o
-);
-
-//================================================================================
-//	REG/WIRE
-//================================================================================
-
-reg ssReg;
-reg ssRegR; 
-reg SckReg; 
-reg [7:0] addrReg;
-reg [7:0] shiftReg0;
-reg [7:0] shiftReg1;
-reg [7:0] shiftReg2;
-
-reg [7:0] shiftReg0M;
-reg [7:0] shiftReg1M;
-reg [7:0] shiftReg2M;
-reg [7:0] addrRegM;
-
-
-//===============================================================================
-//  ASSIGNMENTS
-
-
-assign DataToRxFifo_o = {Addr_o, Data_o};
-
-//================================================================================
-//	CODING
-//================================================================================
-
-always	@(posedge	Clk_i)	begin
-	ssReg	<=	Ss_i;
-	ssRegR	<=	ssReg;
-end
-
-
-always @(*) begin 
-    if (Rst_i) begin
-        addrRegM = 8'h0; 
-        shiftReg0M = 8'h0;
-        shiftReg1M = 8'h0;
-        shiftReg2M = 8'h0;
-    end
-    else begin 
-        case(WidthSel_i)  
-             0: begin 
-                addrRegM   = addrReg  [1:0];
-                shiftReg0M = shiftReg0[1:0];
-                shiftReg1M = shiftReg1[1:0];
-                shiftReg2M = shiftReg2[1:0];
-            end
-            1: begin 
-                addrRegM   = addrReg  [3:0];
-                shiftReg0M = shiftReg0[3:0];
-                shiftReg1M = shiftReg1[3:0];
-                shiftReg2M = shiftReg2[3:0];
-            end
-            2: begin 
-                addrRegM   = addrReg  [5:0];
-                shiftReg0M = shiftReg0[5:0];
-                shiftReg1M = shiftReg1[5:0];
-                shiftReg2M = shiftReg2[5:0];
-            end
-            3: begin 
-                addrRegM   = addrReg  [7:0];
-                shiftReg0M = shiftReg0[7:0];
-                shiftReg1M = shiftReg1[7:0];
-                shiftReg2M = shiftReg2[7:0];
-            end
-        endcase
-    end
-end
-
-
-
-always @(posedge Clk_i) begin 
-    if (Rst_i) begin 
-        Data_o <= 24'h0;
-    end
-    else begin
-        if (SELST_i) begin  
-            if (ssReg && !ssRegR) begin 
-                Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
-            end
-        end
-        else begin 
-            if (!ssReg && ssRegR) begin 
-                Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
-            end
-        end
-    end
-end
-
-always @(posedge Clk_i) begin 
-    if (Rst_i) begin 
-        Addr_o <= 8'h0;
-    end
-    else begin
-        if (SELST_i) begin 
-            if (ssReg && !ssRegR) begin 
-                Addr_o <= addrRegM;
-            end
-        end
-        else begin 
-            if (!ssReg && ssRegR) begin 
-                Addr_o <= addrRegM;
-            end
-        end
-    end
-end
-
-
-
-
-always @(posedge Sck_i) begin 
-    if (Rst_i) begin 
-        shiftReg0 <= 8'h0;
-    end
-    else begin
-        if (SELST_i) begin   
-            if (!Ss_i) begin 
-                shiftReg0 <= {shiftReg0[6:0], Mosi1_i};
-            end
-            else begin 
-                shiftReg0 <= 8'h0;
-            end
-        end
-        else begin 
-            if (Ss_i) begin 
-                shiftReg0 <= {shiftReg0[6:0], Mosi1_i};
-            end
-            else begin 
-                shiftReg0<= 8'h0;
-            end
-        end
-    end
-end
-
-
-always @(posedge Sck_i ) begin 
-    if (Rst_i) begin 
-        shiftReg1 <= 8'h0;
-    end
-    else begin
-        if (SELST_i) begin   
-            if (!Ss_i) begin 
-                shiftReg1 <= {shiftReg1[6:0], Mosi2_i};
-            end
-            else begin 
-                shiftReg1 <= 8'h0;
-            end
-        end
-        else begin 
-            if (Ss_i) begin 
-                shiftReg1 <= {shiftReg1[6:0], Mosi2_i};
-            end
-            else begin 
-                shiftReg1 <= 8'h0;
-            end
-        end
-    end
-end
-
-
-always @(posedge Sck_i ) begin 
-    if (Rst_i) begin 
-        shiftReg2 <= 8'h0;
-    end
-    else begin
-        if (SELST_i) begin   
-            if (!Ss_i) begin 
-                shiftReg2 <= {shiftReg2[6:0], Mosi3_i};
-            end
-            else begin 
-                shiftReg2 <= 8'h0;
-            end
-        end
-        else begin 
-            if (Ss_i) begin 
-                shiftReg2 <= {shiftReg2[6:0], Mosi3_i};
-            end
-            else begin 
-                shiftReg2 <= 8'h0;
-            end
-        end
-    end
-end
-
-
-always @(posedge Sck_i ) begin 
-    if (Rst_i) begin 
-        addrReg <= 8'h0;
-    end
-    else begin
-        if (SELST_i) begin 
-            if (!Ss_i) begin 
-                addrReg <= {addrReg[6:0], Mosi0_i};
-            end
-            else begin 
-                addrReg <= 8'h0;
-            end
-        end
-        else begin 
-            if (Ss_i) begin 
-                addrReg <= {addrReg[6:0], Mosi0_i};
-            end
-            else begin 
-                addrReg <= 8'h0;
-            end
-        end
-    end
-end
-
-
-
-always @(posedge Clk_i) begin
-    if (SELST_i) begin 
-        if (ssReg && !ssRegR) begin 
-            Val_o <= 1'b1;
-        end
-        else begin 
-            Val_o <= 1'b0;
-        end
-    end
-    else begin 
-        if (!ssReg&& ssRegR) begin 
-            Val_o <= 1'b1;
-        end
-        else begin 
-            Val_o <= 1'b0;
-        end
-    end
-end
-
-
-
-
-endmodule

sources_1/new/SRAM/SRAM_tb.v

@@ -1,208 +0,0 @@
-`timescale 1ns / 1ps
-module SRAM_tb;
-
-reg Clk123;
-reg Clk50;
-wire Rst_i;
-reg writeEn_i;
-reg readEn_i;
-reg Start_i;
-
-
-reg [27:0] sramData;
-
-wire [15:0] sramDataOut;
-wire [11:0] sramAddrOut;
-wire fullFlag;
-wire emptyFlag;
-
-
-reg [4:0] cnt; 
-reg [2:0] trCnt;
-reg SS;
-reg outputEn_i;
-
-
-
-
-assign sramDataOut =sramData[15:0];
-// assign sramDataOut = (!outputEn_i)?16'bz:sramData[15:0];
-assign sramAddrOut = sramData[27:16];
-
-
-
-
-always #(4.065) Clk123 = ~Clk123;
-always #(10) Clk50 = ~Clk50;
-
-
-initial begin 
-    Clk123 = 1'b1;
-    Clk50 = 1'b1;
-    Start_i = 1'b0;
-    #1500 Start_i = 1'b1;
-    #500 Start_i = 1'b0;
-end
-
-
-
-
-
-always @(posedge Clk123) begin 
-    if (Rst_i) begin 
-        cnt <= 1'b0;
-    end
-    else begin  
-        if (cnt < 20 ) begin 
-            cnt <= cnt + 1'b1;
-        end
-        else begin 
-            cnt <= 1'b0;
-        end
-    end
-end
-
-
-always @(posedge Clk123) begin 
-    if (Rst_i) begin 
-        trCnt <= 1'b0;
-    end
-    else begin 
-        if (cnt == 20 ) begin 
-            trCnt <= trCnt + 1'b1;
-        end
-    end
-end
-
-
-always @(posedge Clk123) begin 
-    if (Rst_i) begin 
-        sramData <= 28'h00000000;
-    end
-    else begin 
-        case (trCnt) 
-            0 : begin 
-                sramData <= {11'h0, 16'h01};
-            end
-            1 : begin 
-                sramData <= {11'h02, 16'h00};
-            end
-        endcase
-    end
-end
-
-
-
-
-always @(negedge Clk123) begin 
-    if (Rst_i) begin 
-        SS <= 1'b1;
-    end
-    else begin 
-        if ( cnt >= 0 && cnt !== 9 ) begin 
-            SS <= 1'b0;
-        end
-        else begin 
-            SS <= 1'b1;
-        end
-    end
-end
-
-
-
-always @(negedge Clk123) begin 
-    if (Rst_i) begin 
-        writeEn_i <= 1'b1;
-    end
-    else begin 
-        if (cnt >= 2 && cnt <= 6 ) begin 
-            writeEn_i <= 1'b0;
-        end
-        else begin 
-            writeEn_i <= 1'b1;
-        end
-    end
-end
-
-
-always @(negedge Clk123) begin 
-    if (Rst_i) begin 
-        outputEn_i <= 1'b1;
-    end
-    else begin 
-        if (cnt >= 10 && cnt <= 19 ) begin 
-            outputEn_i <= 1'b0;
-        end
-        else begin 
-            outputEn_i <= 1'b1;
-        end
-    end
-end
-
-
-always @(negedge Clk123) begin 
-    if (Rst_i) begin 
-        readEn_i <= 1'b1;
-    end
-    else begin 
-        if ((cnt >= 13 && cnt <= 18) ) begin 
-            readEn_i <= 1'b0;
-        end
-        else begin 
-            readEn_i <= 1'b1;
-        end
-    end
-end
-
-
-
-
-// always @(posedge Clk_i) begin 
-//     if (Rst_i) begin 
-//         CE_i <= 1'b0;
-//     end
-//     else begin
-//         if (!fullFlag && ) begin
-//             CE_i <= 1'b1;
-//         end
-//         else begin
-//             CE_i <= 1'b0;
-//         end
-//     end
-// end
-
-
-SRAMr SRAMr_inst (
-    .Clk123_i(Clk123),
-    // .Clk50_i(Clk50),
-    // .Rst_i(Rst_i),
-    // .Start_i(Start_i),
-    .Addr_i(sramAddrOut),
-    .Data_i(),
-    .writeEn_i(writeEn_i),
-    .readEn_i(readEn_i)
-    // .fullFlag(fullFlag),
-    // .emptyFlag(emptyFlag),
-
-);
-
-
-
-
-InitRst InitRst_inst (
-    .clk_i(Clk123),
-    .signal_o(Rst_i)
-
-);
-
-
-
-
-
-
-
-
-
-endmodule
-
-

sources_1/new/SRAM/SRAMr.v

@@ -1,92 +0,0 @@
-
-module SRAMr #(
-    parameter CmdRegWidth = 32,
-    parameter AddrRegWidth = 12
-
-) (
-    input Clk123_i,
-    // input Clk50_i,
-    input [AddrRegWidth-2:0] Addr_i,
-    inout [CmdRegWidth/2-1:0] Data_i,
-    // input Start_i,
-    input writeEn_i,
-    input readEn_i,
-    input [1:0] BE_i,
-    input outputEn_i,
-
-    // output wire fullFlag,
-    // output wire emptyFlag,
-    output  Led_o
-   
-
-
-
-
-
-
-
-
-);
-//testComment
-//================================================================================
-//  REG/WIRE
-//================================================================================
-
-    wire wrEn;
-    wire rdEn;
-    wire Rst_i;
-    wire [CmdRegWidth/2-1:0] data;
-    wire [AddrRegWidth-1:0] addr; 
-
-    wire mosi0;
-    wire mosi1;
-    wire mosi2;
-    wire mosi3;
-    wire sck;
-    wire ss;
-
-//================================================================================
-//  ASSIGNMENTS
-//================================================================================
-assign addr = {Addr_i, 1'b0};
-assign Data_i = (!outputEn_i) ? data : 16'bz;
-
-
-
-
-
-//================================================================================
-//  CODING
-//================================================================================	
-
-
-
-RegMap #(
-    .CmdRegWidth(32),
-    .AddrRegWidth(12)
-)
-RegMap_inst (
-    .Clk_i(Clk123_i),
-    .Rst_i(Rst_i),
-    .Data_i(Data_i),
-    .Addr_i(addr),
-    .wrEn_i(writeEn_i),
-    .rdEn_i(readEn_i),
-    .BE_i(BE_i),
-    .Led_o(Led_o),
-    .AnsDataReg_o(data)
-
-);
-
-
-InitRst InitRst_inst (
-    .clk_i(Clk123_i),
-    .signal_o(Rst_i)
-
-);
-
-
-
-
-
-endmodule

sources_1/new/SpiR/SPIm.v

@@ -4,7 +4,6 @@ module SPIm (
     input Start_i,
     input CPHA_i,
     input [31:0] SPIdata,
-	input SpiDataVal_i,
     input SELST_i,
     input [1:0] WidthSel_i,
     input  LAG_i,
@@ -36,14 +35,14 @@ reg Ss;
 reg [31:0]spiDataR;
 reg oldDataFlag;
 
-reg SSr;
+reg ssR;
 reg SSR;
 reg [31:0] mosiReg0;
 reg [5:0] ssNum;
 reg [2:0] delayCnt;
 reg stopFlag;
 
-wire SsPol = SELST_i ? Ss : ~Ss;
+wire ssPol = SELST_i ? Ss : ~Ss;
 
 
 //================================================================================
@@ -51,22 +50,15 @@ wire SsPol = SELST_i ? Ss : ~Ss;
 //================================================================================
 
 
-assign Ss_o = SsPol; 
+assign Ss_o = ssPol; 
 
-
-
-// assign Val_o = (trCnt < 1 ) ?!lineBusy:valReg;
 //================================================================================
 //	CODING
 //================================================================================
 
 always @(*) begin 
-    if (Start_i) begin 
-        // if (trCnt < 1) begin 
-        //     Val_o = !lineBusy;
-        // end
-        // else begin 
-            Val_o = valReg;
+    if (Start_i) begin  
+        Val_o = valReg;
     end
     else begin 
         Val_o = 1'b0;
@@ -117,9 +109,6 @@ always @(*) begin
 end
 
 
-
-
-
 always @(posedge Clk_i) begin 
     startR <= Start_i;
 end
@@ -138,23 +127,6 @@ always @(*) begin
     end
 end
 
-always @(posedge Clk_i) begin 
-    if (Rst_i) begin 
-        trCnt <= 1'b0;
-    end
-    else begin 
-        if ( ssCnt == (ssNum + LEAD_i + LAG_i)) begin 
-            trCnt <= trCnt + 1'b1;
-        end
-        else if (oldDataFlag) begin 
-            trCnt <= 1'b0;
-        end
-    end
-end
-
-
-
-
 always @(negedge Clk_i) begin 
     if (Rst_i) begin 
         delayCnt <= 1'b0;
@@ -175,7 +147,7 @@ always @(posedge Clk_i) begin
     end
     else begin
         if (SELST_i) begin 
-            if (SsPol && !SSr) begin 
+            if (ssPol && !ssR) begin 
                 stopFlag <= 1'b1;
             end
             else if ( delayCnt == Stop_i) begin 
@@ -183,7 +155,7 @@ always @(posedge Clk_i) begin
             end
         end
         else begin 
-            if (!SsPol && SSr) begin 
+            if (!ssPol && ssR) begin 
                 stopFlag <= 1'b1;
             end
             else if (delayCnt == Stop_i) begin 
@@ -279,7 +251,7 @@ always @(*) begin
           if (PulsePol_i) begin 
             if (CPHA_i) begin
                 if (LEAD_i == 0) begin 
-                if (SsPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                if (ssPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                     Sck_o = ~(~Clk_i);
                 end
                 else begin 
@@ -287,7 +259,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (SsPol && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+                    if (ssPol && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(~Clk_i);
                     end
                     else begin 
@@ -297,7 +269,7 @@ always @(*) begin
             end
             else begin
                 if (LEAD_i == 0) begin 
-                    if (SsPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    if (ssPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -305,7 +277,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (SsPol && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                    if (ssPol && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -317,7 +289,7 @@ always @(*) begin
         else begin 
             if (CPHA_i) begin
                 if (LEAD_i == 0) begin  
-                    if (SsPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    if (ssPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -325,7 +297,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (SsPol && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
+                    if (ssPol && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(Clk_i);
                     end
                     else begin 
@@ -335,7 +307,7 @@ always @(*) begin
             end 
             else begin
                 if (LEAD_i == 0) begin 
-                    if (SsPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    if (ssPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
                         Sck_o = ~(~Clk_i);
                     end
                     else begin 
@@ -343,7 +315,7 @@ always @(*) begin
                     end
                 end
                 else begin 
-                    if (SsPol && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                    if (ssPol && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
                         Sck_o = ~(~Clk_i);
                     end
                     else begin 
@@ -400,32 +372,32 @@ always @(*) begin
             if (!EndianSel_i) begin 
                 case (WidthSel_i)  
                     0 : begin
-                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
                     end
                     1 : begin
-                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
+                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
                     end
                     2 : begin
-                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
+                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
                     end
                     3 : begin
-                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
+                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
                     end
                 endcase
             end
             else begin 
                 case (WidthSel_i)  
                     0 : begin
-                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                     1 : begin
-                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                     2 : begin
-                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                     3 : begin
-                        Mosi0_o = (SsPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
                     end
                 endcase
             end
@@ -436,7 +408,7 @@ end
 
 
 always @(posedge Clk_i) begin
-    SSr <= SsPol;
+    ssR <= ssPol;
     SSR <= Ss;
 end
 
@@ -457,7 +429,7 @@ end
 
 always @(*) begin
     if (SELST_i) begin 
-        if (Ss_o && !SSr) begin 
+        if (Ss_o && !ssR) begin 
             valReg = 1'b1;
         end
         else begin 
@@ -465,7 +437,7 @@ always @(*) begin
         end
     end
     else begin 
-        if (!Ss_o&& SSr) begin 
+        if (!Ss_o&& ssR) begin 
             valReg = 1'b1;
         end
         else begin 

sources_1/new/SpiR/SPIm_tb.v

@@ -29,11 +29,47 @@ module tb_SPIm;
     wire Ss_o;
     wire Val_o;
 
-    // SPIm SPIm_inst (
-    //     .Clk_i(Clk_i), 
-    //     .Rst_i(Rst_i), 
-    //     .Start_i(Start_i), 
-    //     .CPHA_i(CPHA_i), 
+    SPIm SPIm_inst (
+        .Clk_i(Clk_i), 
+        .Rst_i(Rst_i), 
+        .Start_i(Start_i), 
+        .CPHA_i(CPHA_i), 
+        .SPIdata(SPIdata),
+        .SELST_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .LAG_i(LAG_i),
+        .LEAD_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(Stop_i),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_o(Mosi0_o),
+        .Sck_o(Sck_o),
+        .Ss_o(Ss_o),
+        .Val_o(Val_o)
+    );
+
+
+    SPIs SPIs_inst (
+        .Clk_i(Clk_i), 
+        .Rst_i(Rst_i), 
+        .Sck_i(Sck_o), 
+        .Ss_i(Ss_o), 
+        .Mosi0_i(Mosi0_o), 
+        .WidthSel_i(WidthSel_i), 
+        .EndianSel_i(EndianSel_i),
+        .SELST_i(SELST_i), 
+        .Data_o(), 
+        .Addr_o(), 
+        .DataToRxFifo_o(), 
+        .Val_o()
+    );
+
+
+    // QuadSPIm QuadSPIm_inst (
+    //     .Clk_i(Clk_i),
+    //     .Rst_i(Rst_i),
+    //     .Start_i(Start_i),
+    //     .CPHA_i(CPHA_i),
     //     .SPIdata(SPIdata),
     //     .SpiDataVal_i(SpiDataVal_i),
     //     .SELST_i(SELST_i),
@@ -43,71 +79,34 @@ module tb_SPIm;
     //     .EndianSel_i(EndianSel_i),
     //     .Stop_i(Stop_i),
     //     .PulsePol_i(PulsePol_i),
-    //     .Mosi0_o(Mosi0_o),
+    //     .Mosi0_i(Mosi0_o),
+    //     .Mosi1_i(Mosi1_o),
+    //     .Mosi2_i(Mosi2_o),
+    //     .Mosi3_i(Mosi3_o),
     //     .Sck_o(Sck_o),
     //     .Ss_o(Ss_o),
     //     .Val_o(Val_o)
     // );
 
 
-    // SPIs SPIs_inst (
-    //     .Clk_i(Clk_i), 
-    //     .Rst_i(Rst_i), 
-    //     .Sck_i(Sck_o), 
-    //     .Ss_i(Ss_o), 
-    //     .Mosi0_i(Mosi0_o), 
-    //     .WidthSel_i(WidthSel_i), 
-    //     .EndianSel_i(EndianSel_i),
-    //     .SELST_i(SELST_i), 
-    //     .Data_o(), 
-    //     .Addr_o(), 
-    //     .DataToRxFifo_o(), 
+
+    // QuadSPIs QuadSPIs_inst (
+    //     .Clk_i(Clk_i),
+    //     .Rst_i(Rst_i),
+    //     .Sck_i(Sck_o),
+    //     .Ss_i(Ss_o),
+    //     .Mosi0_i(Mosi0_o),
+    //     .Mosi1_i(Mosi1_o),
+    //     .Mosi2_i(Mosi2_o),
+    //     .Mosi3_i(Mosi3_o),
+    //     .WidthSel_i(WidthSel_i),
+    //     .SELST_i(SELST_i),
+    //     .Data_o(),
+    //     .Addr_o(),
+    //     .DataToRxFifo_o(),
     //     .Val_o()
     // );
 
-
-    QuadSPIm QuadSPIm_inst (
-        .Clk_i(Clk_i),
-        .Rst_i(Rst_i),
-        .Start_i(Start_i),
-        .CPHA_i(CPHA_i),
-        .SPIdata(SPIdata),
-        .SpiDataVal_i(SpiDataVal_i),
-        .SELST_i(SELST_i),
-        .WidthSel_i(WidthSel_i),
-        .LAG_i(LAG_i),
-        .LEAD_i(LEAD_i),
-        .EndianSel_i(EndianSel_i),
-        .Stop_i(Stop_i),
-        .PulsePol_i(PulsePol_i),
-        .Mosi0_i(Mosi0_o),
-        .Mosi1_i(Mosi1_o),
-        .Mosi2_i(Mosi2_o),
-        .Mosi3_i(Mosi3_o),
-        .Sck_o(Sck_o),
-        .Ss_o(Ss_o),
-        .Val_o(Val_o)
-    );
-
-
-
-    QuadSPIs QuadSPIs_inst (
-        .Clk_i(Clk_i),
-        .Rst_i(Rst_i),
-        .Sck_i(Sck_o),
-        .Ss_i(Ss_o),
-        .Mosi0_i(Mosi0_o),
-        .Mosi1_i(Mosi1_o),
-        .Mosi2_i(Mosi2_o),
-        .Mosi3_i(Mosi3_o),
-        .WidthSel_i(WidthSel_i),
-        .SELST_i(SELST_i),
-        .Data_o(),
-        .Addr_o(),
-        .DataToRxFifo_o(),
-        .Val_o()
-    );
-
     // Clock generation
     always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
 
@@ -136,6 +135,7 @@ module tb_SPIm;
 
     
         #(CLK_PERIOD*100);
+           SPIdata = {1'h0, 7'h2a, 24'd10};
 
         // EndianSel_i = 1; // LSB first
         // SPIdata = {1'h0, 7'h2a, 8'haa,8'h00,8'haa};