#1 Script

Open
tchigirinskyanatoly wants to merge 32 commits from ChStepan/Anatoliy/feature_Script into ChStepan/master
41 changed files with 6276 additions and 4866 deletions
  1. 1 0
      .gitignore
  2. BIN
      Docs/BY5443v_новая_шина_вер_3 (2).vsd
  3. BIN
      Docs/Структурная схема BY5443v новая шина вер_3.vsd
  4. 187 211
      constrs_1/new/S5443_3.xdc
  5. 837 0
      scripts/recreate.tcl
  6. 0 0
      sources_1/ip/.Xil/.DataFifoTx.xcix.lock
  7. 10 25
      sources_1/ip/DataFifoTx/DataFifoTx.xci
  8. 8 10
      sources_1/ip/ClkDiv/ClkDiv.xci
  9. 254 228
      sources_1/new/CDC/Cdc.v
  10. 40 27
      sources_1/new/CDC/Sync1bit.v
  11. 62 0
      sources_1/new/ClkManager/ClkDivider.v
  12. 29 0
      sources_1/new/ClkManager/ClkGen_tb.v
  13. 167 0
      sources_1/new/ClkManager/ClkManager.v
  14. 59 0
      sources_1/new/ClkManager/CmdSync.v
  15. 74 0
      sources_1/new/ClkManager/MmcmClkMux.v
  16. 67 0
      sources_1/new/ClkManager/SpiClkMux.v
  17. 69 62
      sources_1/new/DataFifo/DataFifoWrapper.v
  18. 0 168
      sources_1/new/DataFifo/DataOutMux.v
  19. 247 286
      sources_1/new/DataFifo/FifoCtrl.v
  20. 32 17
      sources_1/new/DataFifo/RxFifoPtrSync.v
  21. 32 15
      sources_1/new/DataFifo/RxFifoRstSync.v
  22. 32 14
      sources_1/new/DataFifo/TxFifoPtrsync.v
  23. 0 53
      sources_1/new/MMCM/ClkCh.v
  24. 0 44
      sources_1/new/MMCM/ClkDivSync.v
  25. 0 36
      sources_1/new/MMCM/ClkGen.v
  26. 0 47
      sources_1/new/MMCM/ClkGen_tb.v
  27. 0 55
      sources_1/new/MMCM/ClkOutMMCM.v
  28. 0 158
      sources_1/new/MMCM/MmcmWrapper.v
  29. 0 177
      sources_1/new/Mux/DataMuxer.v
  30. 949 961
      sources_1/new/QuadSPI/QuadSPIm.v
  31. 144 0
      sources_1/new/QuadSPI/QuadSPImTb.v
  32. 71 3
      sources_1/new/QuadSPI/QuadSPIs.v
  33. 899 995
      sources_1/new/RegMap/RegMap.v
  34. 779 936
      sources_1/new/S5443_3Top.v
  35. 4 3
      sources_1/new/S5443_3_tb.v
  36. 176 0
      sources_1/new/SmcAnsMux/SmcAnsMux.v
  37. 186 0
      sources_1/new/SmcInDataMux/SmcInDataMux.v
  38. 528 333
      sources_1/new/SpiR/SPIm.v
  39. 48 2
      sources_1/new/SpiR/SPIs.v
  40. 58 0
      sources_1/new/SpiSubSystem/SpiLinesMuxer.v
  41. 227 0
      sources_1/new/SpiSubSystem/SpiSubSystem.v

+ 1 - 0
.gitignore

@@ -35,3 +35,4 @@ packages/
 /sources_1/new/MMCM/ClkGen_tb.v
 /sources_1/new/MMCM/ClkGen_tb.v
 /sources_1/new/S5443_3Top.v.orig
+/Docs/~$$NEW Структурная схема BY5443v новая шина вер_3.~vsd

BIN
Docs/BY5443v_новая_шина_вер_3 (2).vsd


BIN
Docs/Структурная схема BY5443v новая шина вер_3.vsd


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+ 187 - 211
constrs_1/new/S5443_3.xdc


+ 837 - 0
scripts/recreate.tcl

@@ -0,0 +1,837 @@
+#*****************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# recreate.tcl: Tcl script for re-creating project 'S5443_3_PROJ'
+#
+# Generated by Vivado on Tue Jul 16 10:47:26 +0700 2024
+# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (recreate.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    "C:/S5443_3_PROJ/S5443_3_PROJ.srcs/sources_1/ip/MMCM/MMCM.xci"
+#    "C:/S5443_3_PROJ/S5443_3_PROJ.srcs/sources_1/ip/DataFifoRx/DataFifoRx.xci"
+#    "C:/S5443_3_PROJ/S5443_3_PROJ.srcs/sources_1/ip/DataFifoTx/DataFifoTx.xci"
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "C:/S5443_V3_REPO/sources_1/new/S5443_3Top.v"
+#    "C:/S5443_V3_REPO/sources_1/new/SpiSubSystem/SpiLinesMuxer.v"
+#    "C:/S5443_V3_REPO/sources_1/new/CDC/Sync1bit.v"
+#    "C:/S5443_V3_REPO/sources_1/new/ClkManager/SpiClkMux.v"
+#    "C:/S5443_V3_REPO/sources_1/new/SpiSubSystem/SpiSubSystem.v"
+#    "C:/S5443_V3_REPO/sources_1/new/SmcAnsMux/SmcAnsMux.v"
+#    "C:/S5443_V3_REPO/sources_1/new/SpiR/SPIm.v"
+#    "C:/S5443_V3_REPO/sources_1/new/InitRst/InitRst.v"
+#    "C:/S5443_V3_REPO/sources_1/new/SpiR/SPIs.v"
+#    "C:/S5443_V3_REPO/sources_1/new/DataFifo/TxFifoPtrsync.v"
+#    "C:/S5443_V3_REPO/sources_1/new/DataFifo/FifoCtrl.v"
+#    "C:/S5443_V3_REPO/sources_1/new/CDC/Cdc.v"
+#    "C:/S5443_V3_REPO/sources_1/new/ClkManager/ClkManager.v"
+#    "C:/S5443_V3_REPO/sources_1/new/QuadSPI/QuadSPIs.v"
+#    "C:/S5443_V3_REPO/sources_1/new/ClkManager/ClkDivider.v"
+#    "C:/S5443_V3_REPO/sources_1/new/DataFifo/RxFifoPtrSync.v"
+#    "C:/S5443_V3_REPO/sources_1/new/QuadSPI/QuadSPIm.v"
+#    "C:/S5443_V3_REPO/sources_1/new/ClkManager/MmcmClkMux.v"
+#    "C:/S5443_V3_REPO/sources_1/new/DataFifo/DataFifoWrapper.v"
+#    "C:/S5443_V3_REPO/sources_1/new/ClkManager/CmdSync.v"
+#    "C:/S5443_V3_REPO/sources_1/new/RegMap/RegMap.v"
+#    "C:/S5443_V3_REPO/sources_1/new/SmcInDataMux/SmcInDataMux.v"
+#    "C:/S5443_V3_REPO/constrs_1/new/S5443_3.xdc"
+#    "C:/S5443_V3_REPO/sources_1/new/S5443_3_tb.v"
+#
+#*****************************************************************************************
+
+# Check file required for this script exists
+proc checkRequiredFiles { origin_dir} {
+  set status true
+  # set files [list \
+  #  "C:/S5443_3_PROJ/S5443_3_PROJ.srcs/sources_1/ip/MMCM/MMCM.xci" \
+  #  "C:/S5443_3_PROJ/S5443_3_PROJ.srcs/sources_1/ip/DataFifoRx/DataFifoRx.xci" \
+  #  "C:/S5443_3_PROJ/S5443_3_PROJ.srcs/sources_1/ip/DataFifoTx/DataFifoTx.xci" \
+  # ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find local file $ifile "
+      set status false
+    }
+  }
+
+  set files [list \
+   "C:/S5443_V3_REPO/sources_1/new/S5443_3Top.v" \
+   "C:/S5443_V3_REPO/sources_1/new/SpiSubSystem/SpiLinesMuxer.v" \
+   "C:/S5443_V3_REPO/sources_1/new/CDC/Sync1bit.v" \
+   "C:/S5443_V3_REPO/sources_1/new/ClkManager/SpiClkMux.v" \
+   "C:/S5443_V3_REPO/sources_1/new/SpiSubSystem/SpiSubSystem.v" \
+   "C:/S5443_V3_REPO/sources_1/new/SmcAnsMux/SmcAnsMux.v" \
+   "C:/S5443_V3_REPO/sources_1/new/SpiR/SPIm.v" \
+   "C:/S5443_V3_REPO/sources_1/new/InitRst/InitRst.v" \
+   "C:/S5443_V3_REPO/sources_1/new/SpiR/SPIs.v" \
+   "C:/S5443_V3_REPO/sources_1/new/DataFifo/TxFifoPtrsync.v" \
+   "C:/S5443_V3_REPO/sources_1/new/DataFifo/FifoCtrl.v" \
+   "C:/S5443_V3_REPO/sources_1/new/CDC/Cdc.v" \
+   "C:/S5443_V3_REPO/sources_1/new/ClkManager/ClkManager.v" \
+   "C:/S5443_V3_REPO/sources_1/new/QuadSPI/QuadSPIs.v" \
+   "C:/S5443_V3_REPO/sources_1/new/ClkManager/ClkDivider.v" \
+   "C:/S5443_V3_REPO/sources_1/new/DataFifo/RxFifoPtrSync.v" \
+   "C:/S5443_V3_REPO/sources_1/new/QuadSPI/QuadSPIm.v" \
+   "C:/S5443_V3_REPO/sources_1/new/ClkManager/MmcmClkMux.v" \
+   "C:/S5443_V3_REPO/sources_1/new/DataFifo/DataFifoWrapper.v" \
+   "C:/S5443_V3_REPO/sources_1/new/ClkManager/CmdSync.v" \
+   "C:/S5443_V3_REPO/sources_1/new/RegMap/RegMap.v" \
+   "C:/S5443_V3_REPO/sources_1/new/SmcInDataMux/SmcInDataMux.v" \
+   "C:/S5443_V3_REPO/constrs_1/new/S5443_3.xdc" \
+   "C:/S5443_V3_REPO/sources_1/new/S5443_3_tb.v" \
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find remote file $ifile "
+      set status false
+    }
+  }
+
+  return $status
+}
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "C:/"
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "S5443_3_PROJ"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "recreate.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/S5443_3_PROJ"]"
+
+# Check for paths and files needed for project creation
+set validate_required 0
+if { $validate_required } {
+  if { [checkRequiredFiles $origin_dir] } {
+    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
+  } else {
+    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
+    return
+  }
+}
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7s25csga225-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7s25csga225-2" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "source_mgmt_mode" -value "DisplayOnly" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/S5443_3Top.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/SpiSubSystem/SpiLinesMuxer.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/CDC/Sync1bit.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/ClkManager/SpiClkMux.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/SpiSubSystem/SpiSubSystem.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/SmcAnsMux/SmcAnsMux.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/SpiR/SPIm.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/InitRst/InitRst.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/SpiR/SPIs.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/DataFifo/TxFifoPtrsync.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/DataFifo/FifoCtrl.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/CDC/Cdc.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/ClkManager/ClkManager.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/QuadSPI/QuadSPIs.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/ClkManager/ClkDivider.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/DataFifo/RxFifoPtrSync.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/QuadSPI/QuadSPIm.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/ClkManager/MmcmClkMux.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/DataFifo/DataFifoWrapper.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/ClkManager/CmdSync.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/RegMap/RegMap.v"] \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/SmcInDataMux/SmcInDataMux.v"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "S5443_3Top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# # Set 'sources_1' fileset object
+# set obj [get_filesets sources_1]
+# # Import local files from the original project
+# set files [list \
+#  [file normalize "${origin_dir}/S5443_3_PROJ/S5443_3_PROJ.srcs/sources_1/ip/MMCM/MMCM.xci" ]\
+# ]
+# set imported_files [import_files -fileset sources_1 $files]
+
+# # Set 'sources_1' fileset file properties for remote files
+# # None
+
+# # Set 'sources_1' fileset file properties for local files
+# set file "MMCM/MMCM.xci"
+# set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+# set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+# set_property -name "registered_with_manager" -value "1" -objects $file_obj
+# if { ![get_property "is_locked" $file_obj] } {
+#   set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+# }
+
+
+# # Set 'sources_1' fileset object
+# set obj [get_filesets sources_1]
+# # Import local files from the original project
+# set files [list \
+#  [file normalize "${origin_dir}/S5443_3_PROJ/S5443_3_PROJ.srcs/sources_1/ip/DataFifoRx/DataFifoRx.xci" ]\
+# ]
+# set imported_files [import_files -fileset sources_1 $files]
+
+# # Set 'sources_1' fileset file properties for remote files
+# # None
+
+# # Set 'sources_1' fileset file properties for local files
+# set file "DataFifoRx/DataFifoRx.xci"
+# set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+# set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+# set_property -name "registered_with_manager" -value "1" -objects $file_obj
+# if { ![get_property "is_locked" $file_obj] } {
+#   set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+# }
+
+
+# # Set 'sources_1' fileset object
+# set obj [get_filesets sources_1]
+# # Import local files from the original project
+# set files [list \
+#  [file normalize "${origin_dir}/S5443_3_PROJ/S5443_3_PROJ.srcs/sources_1/ip/DataFifoTx/DataFifoTx.xci" ]\
+# ]
+# set imported_files [import_files -fileset sources_1 $files]
+
+# # Set 'sources_1' fileset file properties for remote files
+# # None
+
+# # Set 'sources_1' fileset file properties for local files
+# set file "DataFifoTx/DataFifoTx.xci"
+# set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+# set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+# set_property -name "registered_with_manager" -value "1" -objects $file_obj
+# if { ![get_property "is_locked" $file_obj] } {
+#   set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+# }
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/S5443_V3_REPO/constrs_1/new/S5443_3.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/S5443_V3_REPO/constrs_1/new/S5443_3.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7s25csga225-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+set files [list \
+ [file normalize "${origin_dir}/S5443_V3_REPO/sources_1/new/S5443_3_tb.v"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sim_1' fileset file properties for remote files
+# None
+
+# Set 'sim_1' fileset file properties for local files
+# None
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "top" -value "S5443_3_tb" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7s25csga225-2 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "part" -value "xc7s25csga225-2" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7s25csga225-2 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2020" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7s25csga225-2" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1
+
+##################################################################
+# CHECK VIVADO VERSION
+##################################################################
+
+set scripts_vivado_version 2020.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+  catch {common::send_msg_id "IPS_TCL-100" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_ip_tcl to create an updated script."}
+  return 1
+}
+
+##################################################################
+# START
+##################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source recreateIp.tcl
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./S5443_3_PROJ/S5443_3_PROJ.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+  create_project S5443_3_PROJ S5443_3_PROJ -part xc7s25csga225-2
+  set_property target_language Verilog [current_project]
+  set_property simulator_language Verilog [current_project]
+}
+
+##################################################################
+# CHECK IPs
+##################################################################
+
+set bCheckIPs 1
+set bCheckIPsPassed 1
+if { $bCheckIPs == 1 } {
+  set list_check_ips { xilinx.com:ip:fifo_generator:13.2 xilinx.com:ip:clk_wiz:6.0 }
+  set list_ips_missing ""
+  common::send_msg_id "IPS_TCL-1001" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+  foreach ip_vlnv $list_check_ips {
+  set ip_obj [get_ipdefs -all $ip_vlnv]
+  if { $ip_obj eq "" } {
+    lappend list_ips_missing $ip_vlnv
+    }
+  }
+
+  if { $list_ips_missing ne "" } {
+    catch {common::send_msg_id "IPS_TCL-105" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+    set bCheckIPsPassed 0
+  }
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "IPS_TCL-102" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 1
+}
+
+##################################################################
+# CREATE IP DataFifoRx
+##################################################################
+
+set DataFifoRx [create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name DataFifoRx]
+
+set_property -dict { 
+  CONFIG.Fifo_Implementation {Independent_Clocks_Builtin_FIFO}
+  CONFIG.Performance_Options {First_Word_Fall_Through}
+  CONFIG.Input_Data_Width {32}
+  CONFIG.Input_Depth {512}
+  CONFIG.Output_Data_Width {32}
+  CONFIG.Output_Depth {512}
+  CONFIG.Enable_ECC {false}
+  CONFIG.Reset_Type {Asynchronous_Reset}
+  CONFIG.Full_Flags_Reset_Value {0}
+  CONFIG.Use_Dout_Reset {false}
+  CONFIG.Data_Count_Width {9}
+  CONFIG.Write_Data_Count_Width {9}
+  CONFIG.Read_Data_Count_Width {9}
+  CONFIG.Read_Clock_Frequency {123}
+  CONFIG.Write_Clock_Frequency {100}
+  CONFIG.Full_Threshold_Assert_Value {503}
+  CONFIG.Full_Threshold_Negate_Value {502}
+  CONFIG.Empty_Threshold_Assert_Value {6}
+  CONFIG.Empty_Threshold_Negate_Value {7}
+  CONFIG.Enable_Safety_Circuit {false}
+} [get_ips DataFifoRx]
+
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $DataFifoRx
+
+##################################################################
+
+##################################################################
+# CREATE IP DataFifoTx
+##################################################################
+
+set DataFifoTx [create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name DataFifoTx]
+
+set_property -dict { 
+  CONFIG.Fifo_Implementation {Independent_Clocks_Builtin_FIFO}
+  CONFIG.Performance_Options {First_Word_Fall_Through}
+  CONFIG.Input_Data_Width {32}
+  CONFIG.Input_Depth {512}
+  CONFIG.Output_Data_Width {32}
+  CONFIG.Output_Depth {512}
+  CONFIG.Reset_Type {Asynchronous_Reset}
+  CONFIG.Use_Dout_Reset {false}
+  CONFIG.Data_Count_Width {9}
+  CONFIG.Write_Data_Count_Width {9}
+  CONFIG.Read_Data_Count_Width {9}
+  CONFIG.Read_Clock_Frequency {1}
+  CONFIG.Write_Clock_Frequency {1}
+  CONFIG.Full_Threshold_Assert_Value {505}
+  CONFIG.Full_Threshold_Negate_Value {504}
+  CONFIG.Empty_Threshold_Assert_Value {6}
+  CONFIG.Empty_Threshold_Negate_Value {7}
+} [get_ips DataFifoTx]
+
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $DataFifoTx
+
+##################################################################
+
+##################################################################
+# CREATE IP MMCM
+##################################################################
+
+set MMCM [create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name MMCM]
+
+set_property -dict { 
+  CONFIG.PRIM_IN_FREQ {123.000}
+  CONFIG.CLKIN1_JITTER_PS {81.30000000000001}
+  CONFIG.CLKOUT2_USED {true}
+  CONFIG.CLKOUT3_USED {true}
+  CONFIG.CLKOUT4_USED {true}
+  CONFIG.CLKOUT5_USED {true}
+  CONFIG.CLKOUT6_USED {true}
+  CONFIG.CLKOUT7_USED {true}
+  CONFIG.NUM_OUT_CLKS {7}
+  CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {80.000}
+  CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {70.000}
+  CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {60.000}
+  CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {50.000}
+  CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {40.000}
+  CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {30.000}
+  CONFIG.MMCM_DIVCLK_DIVIDE {1}
+  CONFIG.MMCM_CLKFBOUT_MULT_F {9.750}
+  CONFIG.MMCM_CLKIN1_PERIOD {8.130}
+  CONFIG.MMCM_CLKOUT0_DIVIDE_F {12.000}
+  CONFIG.MMCM_CLKOUT1_DIVIDE {15}
+  CONFIG.MMCM_CLKOUT2_DIVIDE {17}
+  CONFIG.MMCM_CLKOUT3_DIVIDE {20}
+  CONFIG.MMCM_CLKOUT4_DIVIDE {24}
+  CONFIG.MMCM_CLKOUT5_DIVIDE {30}
+  CONFIG.MMCM_CLKOUT6_DIVIDE {40}
+  CONFIG.CLKOUT1_JITTER {112.035}
+  CONFIG.CLKOUT1_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT2_JITTER {116.822}
+  CONFIG.CLKOUT2_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT3_JITTER {119.640}
+  CONFIG.CLKOUT3_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT4_JITTER {123.604}
+  CONFIG.CLKOUT4_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT5_JITTER {128.250}
+  CONFIG.CLKOUT5_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT6_JITTER {134.251}
+  CONFIG.CLKOUT6_PHASE_ERROR {85.478}
+  CONFIG.CLKOUT7_JITTER {142.568}
+  CONFIG.CLKOUT7_PHASE_ERROR {85.478}
+} [get_ips MMCM]
+
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $MMCM
+
+##################################################################
+

+ 0 - 0
sources_1/ip/.Xil/.DataFifoTx.xcix.lock


File diff suppressed because it is too large
+ 10 - 25
sources_1/ip/DataFifoTx/DataFifoTx.xci


+ 8 - 10
sources_1/ip/ClkDiv/ClkDiv.xci

@@ -6,7 +6,7 @@
   <spirit:version>1.0</spirit:version>
   <spirit:componentInstances>
     <spirit:componentInstance>
-      <spirit:instanceName>ClkDiv</spirit:instanceName>
+      <spirit:instanceName>MMCM</spirit:instanceName>
       <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
       <spirit:configurableElementValues>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.CAN_DEBUG">false</spirit:configurableElementValue>
@@ -148,7 +148,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">99.93750</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
@@ -222,7 +222,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">29.98125</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">30</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">30.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">1</spirit:configurableElementValue>
@@ -435,7 +435,7 @@
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1440.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MIN">600.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">ClkDiv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">MMCM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
@@ -458,7 +458,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">85.478</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
@@ -512,7 +512,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">85.478</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">30</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">30.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">true</spirit:configurableElementValue>
@@ -536,7 +536,7 @@
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ClkDiv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">MMCM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
@@ -707,7 +707,7 @@
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../S5443_3.gen/sources_1/ip/ClkDiv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../S5443_3.gen/sources_1/ip/MMCM</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
@@ -737,7 +737,6 @@
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
@@ -764,7 +763,6 @@
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_USED" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
-            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
             <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>

+ 254 - 228
sources_1/new/CDC/Cdc.v

@@ -1,101 +1,120 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		CDC
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	
+// 
+// Dependencies: 	This module synchronizes commands from RegMap to the 
+//					respective clock domain.
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 module CDC #(
-    parameter WIDTH = 32,
-    parameter STAGES = 3,
-    parameter SpiNum = 7
-
-
-
+	parameter WIDTH = 32,
+	parameter STAGES = 3,
+	parameter SPI_NUM = 7
 )
 (
-    input ClkFast_i,
-    input [SpiNum-1:0] ClkSlow_i,
-
-    input [WIDTH-1:0] Spi0Ctrl_i,
-    input [WIDTH-1:0] Spi0CsCtrl_i,
-    input [WIDTH-1:0] Spi0CsDelay_i,
-    input [WIDTH-1:0] Spi0TxFifoCtrl_i,
-    input [WIDTH-1:0] Spi0RxFifoCtrl_i,
-
-    input [WIDTH-1:0] Spi1Ctrl_i,
-    input [WIDTH-1:0] Spi1CsCtrl_i,
-    input [WIDTH-1:0] Spi1CsDelay_i,
-    input [WIDTH-1:0] Spi1TxFifoCtrl_i,
-    input [WIDTH-1:0] Spi1RxFifoCtrl_i,
-
-    input [WIDTH-1:0] Spi2Ctrl_i,
-    input [WIDTH-1:0] Spi2CsCtrl_i,
-    input [WIDTH-1:0] Spi2CsDelay_i,
-    input [WIDTH-1:0] Spi2TxFifoCtrl_i,
-    input [WIDTH-1:0] Spi2RxFifoCtrl_i,
-
-    input [WIDTH-1:0] Spi3Ctrl_i,
-    input [WIDTH-1:0] Spi3CsCtrl_i,
-    input [WIDTH-1:0] Spi3CsDelay_i,
-    input [WIDTH-1:0] Spi3TxFifoCtrl_i,
-    input [WIDTH-1:0] Spi3RxFifoCtrl_i,
-
-    input [WIDTH-1:0] Spi4Ctrl_i,
-    input [WIDTH-1:0] Spi4CsCtrl_i,
-    input [WIDTH-1:0] Spi4CsDelay_i,
-    input [WIDTH-1:0] Spi4TxFifoCtrl_i,
-    input [WIDTH-1:0] Spi4RxFifoCtrl_i,
-
-    input [WIDTH-1:0] Spi5Ctrl_i,
-    input [WIDTH-1:0] Spi5CsCtrl_i,
-    input [WIDTH-1:0] Spi5CsDelay_i,
-    input [WIDTH-1:0] Spi5TxFifoCtrl_i,
-    input [WIDTH-1:0] Spi5RxFifoCtrl_i,
-
-    input [WIDTH-1:0] Spi6Ctrl_i,
-    input [WIDTH-1:0] Spi6CsCtrl_i,
-    input [WIDTH-1:0] Spi6CsDelay_i,
-    input [WIDTH-1:0] Spi6TxFifoCtrl_i,
-    input [WIDTH-1:0] Spi6RxFifoCtrl_i,
-
-    output [WIDTH-1:0] Spi0Ctrl_o,
-    output [WIDTH-1:0] Spi0CsCtrl_o,
-    output [WIDTH-1:0] Spi0CsDelay_o,
-    output [WIDTH-1:0] Spi0TxFifoCtrl_o,
-    output [WIDTH-1:0] Spi0RxFifoCtrl_o,
-
-    output [WIDTH-1:0] Spi1Ctrl_o,
-    output [WIDTH-1:0] Spi1CsCtrl_o,
-    output [WIDTH-1:0] Spi1CsDelay_o,
-    output [WIDTH-1:0] Spi1TxFifoCtrl_o,
-    output [WIDTH-1:0] Spi1RxFifoCtrl_o,
-
-    output [WIDTH-1:0] Spi2Ctrl_o,
-    output [WIDTH-1:0] Spi2CsCtrl_o,
-    output [WIDTH-1:0] Spi2CsDelay_o,
-    output [WIDTH-1:0] Spi2TxFifoCtrl_o,
-    output [WIDTH-1:0] Spi2RxFifoCtrl_o,
-
-    output [WIDTH-1:0] Spi3Ctrl_o,
-    output [WIDTH-1:0] Spi3CsCtrl_o,
-    output [WIDTH-1:0] Spi3CsDelay_o,
-    output [WIDTH-1:0] Spi3TxFifoCtrl_o,
-    output [WIDTH-1:0] Spi3RxFifoCtrl_o,
-
-    output [WIDTH-1:0] Spi4Ctrl_o,
-    output [WIDTH-1:0] Spi4CsCtrl_o,
-    output [WIDTH-1:0] Spi4CsDelay_o,
-    output [WIDTH-1:0] Spi4TxFifoCtrl_o,
-    output [WIDTH-1:0] Spi4RxFifoCtrl_o,
-
-    output [WIDTH-1:0] Spi5Ctrl_o,
-    output [WIDTH-1:0] Spi5CsCtrl_o,
-    output [WIDTH-1:0] Spi5CsDelay_o,
-    output [WIDTH-1:0] Spi5TxFifoCtrl_o,
-    output [WIDTH-1:0] Spi5RxFifoCtrl_o,
-    
-    output [WIDTH-1:0] Spi6Ctrl_o,
-    output [WIDTH-1:0] Spi6CsCtrl_o,
-    output [WIDTH-1:0] Spi6CsDelay_o,
-    output [WIDTH-1:0] Spi6TxFifoCtrl_o,
-    output [WIDTH-1:0] Spi6RxFifoCtrl_o
-    
+	input ClkFast_i,
+	input [SPI_NUM-1:0] ClkSlow_i,
+
+	input [WIDTH-1:0] Spi0Ctrl_i,
+	input [WIDTH-1:0] Spi0CsCtrl_i,
+	input [WIDTH-1:0] Spi0CsDelay_i,
+	input [WIDTH-1:0] Spi0TxFifoCtrl_i,
+	input [WIDTH-1:0] Spi0RxFifoCtrl_i,
+
+	input [WIDTH-1:0] Spi1Ctrl_i,
+	input [WIDTH-1:0] Spi1CsCtrl_i,
+	input [WIDTH-1:0] Spi1CsDelay_i,
+	input [WIDTH-1:0] Spi1TxFifoCtrl_i,
+	input [WIDTH-1:0] Spi1RxFifoCtrl_i,
+
+	input [WIDTH-1:0] Spi2Ctrl_i,
+	input [WIDTH-1:0] Spi2CsCtrl_i,
+	input [WIDTH-1:0] Spi2CsDelay_i,
+	input [WIDTH-1:0] Spi2TxFifoCtrl_i,
+	input [WIDTH-1:0] Spi2RxFifoCtrl_i,
+
+	input [WIDTH-1:0] Spi3Ctrl_i,
+	input [WIDTH-1:0] Spi3CsCtrl_i,
+	input [WIDTH-1:0] Spi3CsDelay_i,
+	input [WIDTH-1:0] Spi3TxFifoCtrl_i,
+	input [WIDTH-1:0] Spi3RxFifoCtrl_i,
+
+	input [WIDTH-1:0] Spi4Ctrl_i,
+	input [WIDTH-1:0] Spi4CsCtrl_i,
+	input [WIDTH-1:0] Spi4CsDelay_i,
+	input [WIDTH-1:0] Spi4TxFifoCtrl_i,
+	input [WIDTH-1:0] Spi4RxFifoCtrl_i,
+
+	input [WIDTH-1:0] Spi5Ctrl_i,
+	input [WIDTH-1:0] Spi5CsCtrl_i,
+	input [WIDTH-1:0] Spi5CsDelay_i,
+	input [WIDTH-1:0] Spi5TxFifoCtrl_i,
+	input [WIDTH-1:0] Spi5RxFifoCtrl_i,
+
+	input [WIDTH-1:0] Spi6Ctrl_i,
+	input [WIDTH-1:0] Spi6CsCtrl_i,
+	input [WIDTH-1:0] Spi6CsDelay_i,
+	input [WIDTH-1:0] Spi6TxFifoCtrl_i,
+	input [WIDTH-1:0] Spi6RxFifoCtrl_i,
+
+	output [WIDTH-1:0] Spi0Ctrl_o,
+	output [WIDTH-1:0] Spi0CsCtrl_o,
+	output [WIDTH-1:0] Spi0CsDelay_o,
+	output [WIDTH-1:0] Spi0TxFifoCtrl_o,
+	output [WIDTH-1:0] Spi0RxFifoCtrl_o,
+
+	output [WIDTH-1:0] Spi1Ctrl_o,
+	output [WIDTH-1:0] Spi1CsCtrl_o,
+	output [WIDTH-1:0] Spi1CsDelay_o,
+	output [WIDTH-1:0] Spi1TxFifoCtrl_o,
+	output [WIDTH-1:0] Spi1RxFifoCtrl_o,
+
+	output [WIDTH-1:0] Spi2Ctrl_o,
+	output [WIDTH-1:0] Spi2CsCtrl_o,
+	output [WIDTH-1:0] Spi2CsDelay_o,
+	output [WIDTH-1:0] Spi2TxFifoCtrl_o,
+	output [WIDTH-1:0] Spi2RxFifoCtrl_o,
+
+	output [WIDTH-1:0] Spi3Ctrl_o,
+	output [WIDTH-1:0] Spi3CsCtrl_o,
+	output [WIDTH-1:0] Spi3CsDelay_o,
+	output [WIDTH-1:0] Spi3TxFifoCtrl_o,
+	output [WIDTH-1:0] Spi3RxFifoCtrl_o,
+
+	output [WIDTH-1:0] Spi4Ctrl_o,
+	output [WIDTH-1:0] Spi4CsCtrl_o,
+	output [WIDTH-1:0] Spi4CsDelay_o,
+	output [WIDTH-1:0] Spi4TxFifoCtrl_o,
+	output [WIDTH-1:0] Spi4RxFifoCtrl_o,
+
+	output [WIDTH-1:0] Spi5Ctrl_o,
+	output [WIDTH-1:0] Spi5CsCtrl_o,
+	output [WIDTH-1:0] Spi5CsDelay_o,
+	output [WIDTH-1:0] Spi5TxFifoCtrl_o,
+	output [WIDTH-1:0] Spi5RxFifoCtrl_o,
+	
+	output [WIDTH-1:0] Spi6Ctrl_o,
+	output [WIDTH-1:0] Spi6CsCtrl_o,
+	output [WIDTH-1:0] Spi6CsDelay_o,
+	output [WIDTH-1:0] Spi6TxFifoCtrl_o,
+	output [WIDTH-1:0] Spi6RxFifoCtrl_o
 );
 
+//================================================================================
+//  REG/WIRE
+//================================================================================
 //lauch registers 
 reg [WIDTH-1:0] spi0Ctrl;
 reg [WIDTH-1:0] spi0CsCtrl;
@@ -146,186 +165,193 @@ reg [WIDTH-1:0] spi6RxFifoCtrl;
 (* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0TxFifoCtrl_c;
 (* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0RxFifoCtrl_c;
 
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1Ctrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1CsCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1CsDelay_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1TxFifoCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1RxFifoCtrl_c;
-
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2Ctrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2CsCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2CsDelay_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2TxFifoCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2RxFifoCtrl_c;
-
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3Ctrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3CsCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3CsDelay_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3TxFifoCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3RxFifoCtrl_c;
-
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4Ctrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4CsCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4CsDelay_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4TxFifoCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4RxFifoCtrl_c;
-
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5Ctrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5CsCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5CsDelay_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5TxFifoCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5RxFifoCtrl_c;
-
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6Ctrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6CsCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6CsDelay_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6TxFifoCtrl_c;
-(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6RxFifoCtrl_c;
-
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi1Ctrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi1CsCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi1CsDelay_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi1TxFifoCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi1RxFifoCtrl_c;
+
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi2Ctrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi2CsCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi2CsDelay_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi2TxFifoCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi2RxFifoCtrl_c;
+
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi3Ctrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi3CsCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi3CsDelay_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi3TxFifoCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi3RxFifoCtrl_c;
+
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi4Ctrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi4CsCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi4CsDelay_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi4TxFifoCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi4RxFifoCtrl_c;
+
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi5Ctrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi5CsCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi5CsDelay_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi5TxFifoCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi5RxFifoCtrl_c;
+
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi6Ctrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi6CsCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi6CsDelay_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi6TxFifoCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi6RxFifoCtrl_c;
+
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
 //SPI0
-assign Spi0Ctrl_o = spi0Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi0CsDelay_o = spi0CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi0CsCtrl_o = spi0CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi0Ctrl_o 		= spi0Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi0CsDelay_o 	= spi0CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi0CsCtrl_o 	= spi0CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi0TxFifoCtrl_o = spi0TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi0RxFifoCtrl_o = spi0RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 //SPI1
-assign Spi1Ctrl_o = spi1Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi1CsDelay_o = spi1CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi1CsCtrl_o = spi1CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi1Ctrl_o 		= spi1Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi1CsDelay_o 	= spi1CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi1CsCtrl_o 	= spi1CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi1TxFifoCtrl_o = spi1TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi1RxFifoCtrl_o = spi1RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 //SPI2
-assign Spi2Ctrl_o = spi2Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi2CsDelay_o = spi2CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi2CsCtrl_o = spi2CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi2Ctrl_o 		= spi2Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi2CsDelay_o 	= spi2CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi2CsCtrl_o 	= spi2CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi2TxFifoCtrl_o = spi2TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi2RxFifoCtrl_o = spi2RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 //SPI3
-assign Spi3Ctrl_o = spi3Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi3CsDelay_o = spi3CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi3CsCtrl_o = spi3CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi3Ctrl_o 		= spi3Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi3CsDelay_o 	= spi3CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi3CsCtrl_o 	= spi3CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi3TxFifoCtrl_o = spi3TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi3RxFifoCtrl_o = spi3RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 //SPI4
-assign Spi4Ctrl_o = spi4Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi4CsDelay_o = spi4CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi4CsCtrl_o = spi4CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi4Ctrl_o 		= spi4Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi4CsDelay_o 	= spi4CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi4CsCtrl_o 	= spi4CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi4TxFifoCtrl_o = spi4TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi4RxFifoCtrl_o = spi4RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 //SPI5
-assign Spi5Ctrl_o = spi5Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi5CsDelay_o = spi5CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi5CsCtrl_o = spi5CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi5Ctrl_o 		= spi5Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi5CsDelay_o 	= spi5CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi5CsCtrl_o 	= spi5CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi5TxFifoCtrl_o = spi5TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi5RxFifoCtrl_o = spi5RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 //SPI6
-assign Spi6Ctrl_o = spi6Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi6CsDelay_o = spi6CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign Spi6CsCtrl_o = spi6CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi6Ctrl_o 		= spi6Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi6CsDelay_o 	= spi6CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi6CsCtrl_o 	= spi6CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi6TxFifoCtrl_o = spi6TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 assign Spi6RxFifoCtrl_o = spi6RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
 
+//================================================================================
+//	CODING
+//================================================================================
 always @(posedge ClkFast_i) begin
-    spi0Ctrl <= Spi0Ctrl_i;
-    spi0CsDelay <= Spi0CsDelay_i;
-    spi0CsCtrl <= Spi0CsCtrl_i;
-    spi0TxFifoCtrl <= Spi0TxFifoCtrl_i;
-    spi0RxFifoCtrl <= Spi0RxFifoCtrl_i;
-    spi1Ctrl <= Spi1Ctrl_i;
-    spi1CsDelay <= Spi1CsDelay_i;
-    spi1CsCtrl <= Spi1CsCtrl_i;
-    spi1TxFifoCtrl <= Spi1TxFifoCtrl_i;
-    spi1RxFifoCtrl <= Spi1RxFifoCtrl_i;
-    spi2Ctrl <= Spi2Ctrl_i;
-    spi2CsDelay <= Spi2CsDelay_i;
-    spi2CsCtrl <= Spi2CsCtrl_i;
-    spi2TxFifoCtrl <= Spi2TxFifoCtrl_i;
-    spi2RxFifoCtrl <= Spi2RxFifoCtrl_i;
-    spi3Ctrl <= Spi3Ctrl_i;
-    spi3CsDelay <= Spi3CsDelay_i;
-    spi3CsCtrl <= Spi3CsCtrl_i;
-    spi3TxFifoCtrl <= Spi3TxFifoCtrl_i;
-    spi3RxFifoCtrl <= Spi3RxFifoCtrl_i;
-    spi4Ctrl <= Spi4Ctrl_i;
-    spi4CsDelay <= Spi4CsDelay_i;
-    spi4CsCtrl <= Spi4CsCtrl_i;
-    spi4TxFifoCtrl <= Spi4TxFifoCtrl_i;
-    spi4RxFifoCtrl <= Spi4RxFifoCtrl_i;
-    spi5Ctrl <= Spi5Ctrl_i;
-    spi5CsDelay <= Spi5CsDelay_i;
-    spi5CsCtrl <= Spi5CsCtrl_i;
-    spi5TxFifoCtrl <= Spi5TxFifoCtrl_i;
-    spi5RxFifoCtrl <= Spi5RxFifoCtrl_i;
-    spi6Ctrl <= Spi6Ctrl_i;
-    spi6CsDelay <= Spi6CsDelay_i;
-    spi6CsCtrl <= Spi6CsCtrl_i;
-    spi6TxFifoCtrl <= Spi6TxFifoCtrl_i;
-    spi6RxFifoCtrl <= Spi6RxFifoCtrl_i;
+	spi0Ctrl 		<= Spi0Ctrl_i;
+	spi0CsDelay 	<= Spi0CsDelay_i;
+	spi0CsCtrl 		<= Spi0CsCtrl_i;
+	spi0TxFifoCtrl 	<= Spi0TxFifoCtrl_i;
+	spi0RxFifoCtrl 	<= Spi0RxFifoCtrl_i;
+
+	spi1Ctrl 		<= Spi1Ctrl_i;
+	spi1CsDelay 	<= Spi1CsDelay_i;
+	spi1CsCtrl 		<= Spi1CsCtrl_i;
+	spi1TxFifoCtrl 	<= Spi1TxFifoCtrl_i;
+	spi1RxFifoCtrl 	<= Spi1RxFifoCtrl_i;
+
+	spi2Ctrl 		<= Spi2Ctrl_i;
+	spi2CsDelay 	<= Spi2CsDelay_i;
+	spi2CsCtrl 		<= Spi2CsCtrl_i;
+	spi2TxFifoCtrl 	<= Spi2TxFifoCtrl_i;
+	spi2RxFifoCtrl 	<= Spi2RxFifoCtrl_i;
+
+	spi3Ctrl 		<= Spi3Ctrl_i;
+	spi3CsDelay 	<= Spi3CsDelay_i;
+	spi3CsCtrl 		<= Spi3CsCtrl_i;
+	spi3TxFifoCtrl 	<= Spi3TxFifoCtrl_i;
+	spi3RxFifoCtrl 	<= Spi3RxFifoCtrl_i;
+
+	spi4Ctrl 		<= Spi4Ctrl_i;
+	spi4CsDelay 	<= Spi4CsDelay_i;
+	spi4CsCtrl 		<= Spi4CsCtrl_i;
+	spi4TxFifoCtrl 	<= Spi4TxFifoCtrl_i;
+	spi4RxFifoCtrl 	<= Spi4RxFifoCtrl_i;
+
+	spi5Ctrl 		<= Spi5Ctrl_i;
+	spi5CsDelay 	<= Spi5CsDelay_i;
+	spi5CsCtrl 		<= Spi5CsCtrl_i;
+	spi5TxFifoCtrl 	<= Spi5TxFifoCtrl_i;
+	spi5RxFifoCtrl 	<= Spi5RxFifoCtrl_i;
+
+	spi6Ctrl 		<= Spi6Ctrl_i;
+	spi6CsDelay 	<= Spi6CsDelay_i;
+	spi6CsCtrl 		<= Spi6CsCtrl_i;
+	spi6TxFifoCtrl 	<= Spi6TxFifoCtrl_i;
+	spi6RxFifoCtrl 	<= Spi6RxFifoCtrl_i;
 end
 
-
-
-
-
 always @(posedge ClkSlow_i[0]) begin 
-    spi0Ctrl_c <= {spi0Ctrl_c[(STAGES-1)*WIDTH-1:0],spi0Ctrl};
-    spi0CsDelay_c <= {spi0CsDelay_c[(STAGES-1)*WIDTH-1:0],spi0CsDelay};
-    spi0CsCtrl_c <= {spi0CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi0CsCtrl};
-    spi0TxFifoCtrl_c <= {spi0TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi0TxFifoCtrl};
-    spi0RxFifoCtrl_c <= {spi0RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi0RxFifoCtrl};
+	spi0Ctrl_c 		<= {spi0Ctrl_c[(STAGES-1)*WIDTH-1:0], spi0Ctrl};
+	spi0CsDelay_c 	<= {spi0CsDelay_c[(STAGES-1)*WIDTH-1:0], spi0CsDelay};
+	spi0CsCtrl_c 	<= {spi0CsCtrl_c[(STAGES-1)*WIDTH-1:0], spi0CsCtrl};
+	spi0TxFifoCtrl_c <= {spi0TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi0TxFifoCtrl};
+	spi0RxFifoCtrl_c <= {spi0RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi0RxFifoCtrl};
 end
 
 always@(posedge ClkSlow_i[1]) begin 
-    spi1Ctrl_c <= {spi1Ctrl_c[(STAGES-1)*WIDTH-1:0],spi1Ctrl};
-    spi1CsDelay_c <= {spi1CsDelay_c[(STAGES-1)*WIDTH-1:0],spi1CsDelay};
-    spi1CsCtrl_c <= {spi1CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi1CsCtrl};
-    spi1TxFifoCtrl_c <= {spi1TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi1TxFifoCtrl};
-    spi1RxFifoCtrl_c <= {spi1RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi1RxFifoCtrl};
+	spi1Ctrl_c 		<= {spi1Ctrl_c[(STAGES-1)*WIDTH-1:0], spi1Ctrl};
+	spi1CsDelay_c 	<= {spi1CsDelay_c[(STAGES-1)*WIDTH-1:0], spi1CsDelay};
+	spi1CsCtrl_c 	<= {spi1CsCtrl_c[(STAGES-1)*WIDTH-1:0], spi1CsCtrl};
+	spi1TxFifoCtrl_c <= {spi1TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi1TxFifoCtrl};
+	spi1RxFifoCtrl_c <= {spi1RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi1RxFifoCtrl};
 end
 
 always@(posedge ClkSlow_i[2]) begin 
-    spi2Ctrl_c <= {spi2Ctrl_c[(STAGES-1)*WIDTH-1:0],spi2Ctrl};
-    spi2CsDelay_c <= {spi2CsDelay_c[(STAGES-1)*WIDTH-1:0],spi2CsDelay};
-    spi2CsCtrl_c <= {spi2CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi2CsCtrl};
-    spi2TxFifoCtrl_c <= {spi2TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi2TxFifoCtrl};
-    spi2RxFifoCtrl_c <= {spi2RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi2RxFifoCtrl};
+	spi2Ctrl_c 		<= {spi2Ctrl_c[(STAGES-1)*WIDTH-1:0], spi2Ctrl};
+	spi2CsDelay_c 	<= {spi2CsDelay_c[(STAGES-1)*WIDTH-1:0], spi2CsDelay};
+	spi2CsCtrl_c 	<= {spi2CsCtrl_c[(STAGES-1)*WIDTH-1:0], spi2CsCtrl};
+	spi2TxFifoCtrl_c <= {spi2TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi2TxFifoCtrl};
+	spi2RxFifoCtrl_c <= {spi2RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi2RxFifoCtrl};
 end
 
 always@(posedge ClkSlow_i[3]) begin 
-    spi3Ctrl_c <= {spi3Ctrl_c[(STAGES-1)*WIDTH-1:0],spi3Ctrl};
-    spi3CsDelay_c <= {spi3CsDelay_c[(STAGES-1)*WIDTH-1:0],spi3CsDelay};
-    spi3CsCtrl_c <= {spi3CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi3CsCtrl};
-    spi3TxFifoCtrl_c <= {spi3TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi3TxFifoCtrl};
-    spi3RxFifoCtrl_c <= {spi3RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi3RxFifoCtrl};
+	spi3Ctrl_c 		<= {spi3Ctrl_c[(STAGES-1)*WIDTH-1:0], spi3Ctrl};
+	spi3CsDelay_c 	<= {spi3CsDelay_c[(STAGES-1)*WIDTH-1:0], spi3CsDelay};
+	spi3CsCtrl_c 	<= {spi3CsCtrl_c[(STAGES-1)*WIDTH-1:0], spi3CsCtrl};
+	spi3TxFifoCtrl_c <= {spi3TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi3TxFifoCtrl};
+	spi3RxFifoCtrl_c <= {spi3RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi3RxFifoCtrl};
 end
 
 always@(posedge ClkSlow_i[4]) begin 
-    spi4Ctrl_c <= {spi4Ctrl_c[(STAGES-1)*WIDTH-1:0],spi4Ctrl};
-    spi4CsDelay_c <= {spi4CsDelay_c[(STAGES-1)*WIDTH-1:0],spi4CsDelay};
-    spi4CsCtrl_c <= {spi4CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi4CsCtrl};
-    spi4TxFifoCtrl_c <= {spi4TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi4TxFifoCtrl};
-    spi4RxFifoCtrl_c <= {spi4RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi4RxFifoCtrl};
+	spi4Ctrl_c 		<= {spi4Ctrl_c[(STAGES-1)*WIDTH-1:0], spi4Ctrl};
+	spi4CsDelay_c 	<= {spi4CsDelay_c[(STAGES-1)*WIDTH-1:0], spi4CsDelay};
+	spi4CsCtrl_c 	<= {spi4CsCtrl_c[(STAGES-1)*WIDTH-1:0], spi4CsCtrl};
+	spi4TxFifoCtrl_c <= {spi4TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi4TxFifoCtrl};
+	spi4RxFifoCtrl_c <= {spi4RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi4RxFifoCtrl};
 end
 
 always@(posedge ClkSlow_i[5]) begin 
-    spi5Ctrl_c <= {spi5Ctrl_c[(STAGES-1)*WIDTH-1:0],spi5Ctrl};
-    spi5CsDelay_c <= {spi5CsDelay_c[(STAGES-1)*WIDTH-1:0],spi5CsDelay};
-    spi5CsCtrl_c <= {spi5CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi5CsCtrl};
-    spi5TxFifoCtrl_c <= {spi5TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi5TxFifoCtrl};
-    spi5RxFifoCtrl_c <= {spi5RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi5RxFifoCtrl};
+	spi5Ctrl_c 		<= {spi5Ctrl_c[(STAGES-1)*WIDTH-1:0], spi5Ctrl};
+	spi5CsDelay_c 	<= {spi5CsDelay_c[(STAGES-1)*WIDTH-1:0], spi5CsDelay};
+	spi5CsCtrl_c 	<= {spi5CsCtrl_c[(STAGES-1)*WIDTH-1:0], spi5CsCtrl};
+	spi5TxFifoCtrl_c <= {spi5TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi5TxFifoCtrl};
+	spi5RxFifoCtrl_c <= {spi5RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi5RxFifoCtrl};
 end
 
 always@(posedge ClkSlow_i[6]) begin 
-    spi6Ctrl_c <= {spi6Ctrl_c[(STAGES-1)*WIDTH-1:0],spi6Ctrl};
-    spi6CsDelay_c <= {spi6CsDelay_c[(STAGES-1)*WIDTH-1:0],spi6CsDelay};
-    spi6CsCtrl_c <= {spi6CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi6CsCtrl};
-    spi6TxFifoCtrl_c <= {spi6TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi6TxFifoCtrl};
-    spi6RxFifoCtrl_c <= {spi6RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi6RxFifoCtrl};
+	spi6Ctrl_c 		<= {spi6Ctrl_c[(STAGES-1)*WIDTH-1:0], spi6Ctrl};
+	spi6CsDelay_c 	<= {spi6CsDelay_c[(STAGES-1)*WIDTH-1:0], spi6CsDelay};
+	spi6CsCtrl_c 	<= {spi6CsCtrl_c[(STAGES-1)*WIDTH-1:0], spi6CsCtrl};
+	spi6TxFifoCtrl_c <= {spi6TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi6TxFifoCtrl};
+	spi6RxFifoCtrl_c <= {spi6RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0], spi6RxFifoCtrl};
 end
 
-
-
-
-
 endmodule

+ 40 - 27
sources_1/new/CDC/Sync1bit.v

@@ -1,47 +1,60 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		Sync1bit
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	This module synchronizes Spi enable command
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 module Sync1bit #(
-    parameter WIDTH = 1,
-    parameter STAGES = 3
-
-
-
+	parameter WIDTH = 1,
+	parameter STAGES = 3
 )
 (
-    input ClkFast_i,
-    input ClkSlow_i,
-    input TxEn_i,
-    input RstReg_i,
-
-    output [WIDTH-1:0] TxEn_o,
-    output [WIDTH-1:0] RstReg_o
+	input ClkFast_i,
+	input ClkSlow_i,
+	input TxEn_i,
 
+	output [WIDTH-1:0] TxEn_o
 );
+
+//================================================================================
+//  REG/WIRE
+//================================================================================
 //lauch registers 
 reg spiTxEnReg;
-reg rstReg;
 // capture registers
 (* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] spiTxEnReg_c;
-(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rstReg_c;
 
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
 assign TxEn_o = spiTxEnReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-assign RstReg_o = rstReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
 
+//================================================================================
+//  CODING
+//================================================================================
 always @(posedge ClkFast_i) begin
-    spiTxEnReg <= TxEn_i;
-    rstReg <= RstReg_i;
+	spiTxEnReg <= TxEn_i;
 end
 
-
-
-
-
 always @(posedge ClkSlow_i) begin 
-    spiTxEnReg_c <= {spiTxEnReg_c[(STAGES-1)*WIDTH-1:0], spiTxEnReg};
-    rstReg_c <= {rstReg_c[(STAGES-1)*WIDTH-1:0], rstReg};
+	spiTxEnReg_c <= {spiTxEnReg_c[(STAGES-1)*WIDTH-1:0], spiTxEnReg};
 end
 
-
-
-
-
 endmodule

+ 62 - 0
sources_1/new/ClkManager/ClkDivider.v

@@ -0,0 +1,62 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     ClkDivider
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     This modules is clock divider that divides clock frequency based on an input divider value. 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module ClkDivider (
+  input Clk_i,
+  input [3:0] ClkDiv_i,
+  input Rst_i,
+  output Clk_o
+);
+
+//================================================================================
+//  REG/WIRE
+//================================================================================
+reg [16:0] cnt;
+
+reg clk;
+wire clk_o;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign Clk_o = (cnt < ClkDiv_i / 2) ? 1 : 0;
+
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
+
+//================================================================================
+//  CODING
+//================================================================================   
+always @(posedge Clk_i) begin 
+	if (Rst_i) begin 
+		cnt <= 0;
+	end
+	else begin 
+		if (cnt >= ClkDiv_i - 1) begin 
+			cnt <= 0;
+		end
+		else begin 
+			cnt <= cnt + 1;
+		end
+	end
+end
+
+endmodule

+ 29 - 0
sources_1/new/ClkManager/ClkGen_tb.v

@@ -0,0 +1,29 @@
+`timescale 1ns / 1ps
+module ClkGen_tb();
+
+reg Clk_i;
+reg Rst_i;
+
+reg [3:0] clkDiv_i;
+
+always #(1.667/2) Clk_i = ~Clk_i;
+
+ClkGenGowin ClkGen_inst (
+	.Clk_i(Clk_i),
+	.Rst_i(Rst_i),
+	.Clk75_o(),
+	.Clk40_o(),
+	.Clk30_o(),
+	.Clk5_o()
+);
+
+initial begin 
+	Clk_i = 0;
+	Rst_i = 1;
+	clkDiv_i = 3;
+	#1000;
+	Rst_i = 0;
+
+end
+
+endmodule

+ 167 - 0
sources_1/new/ClkManager/ClkManager.v

@@ -0,0 +1,167 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     ClkManager
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	This module is a clock distributor. Based on a setting it 
+//					multiplexing cloks that generated either from MMCM or from 
+//					a custom divider.     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module ClkManager 
+#(
+	parameter	SPI_NUM	=	7,
+	parameter	STAGES	=	3
+)
+(
+	input Clk_i,
+	input Rst_i,
+	input Rst80_i,
+	input [7:0] BaudRate0_i,
+	input [7:0] BaudRate1_i,
+	input [7:0] BaudRate2_i,
+	input [7:0] BaudRate3_i,
+	input [7:0] BaudRate4_i,
+	input [7:0] BaudRate5_i,
+	input [7:0] BaudRate6_i,
+
+	output	Clk80_o,
+	output	[SPI_NUM-1:0]	SpiClk_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire clk0out;
+	wire clk1out;
+	wire clk2out;
+	wire clk3out;
+	wire clk4out;
+	wire clk5out;
+	wire clk6out;
+	
+	wire locked;
+	
+	wire [SPI_NUM-1:0] clkOutMMCM;
+	
+	wire [SPI_NUM-1:0] clkMan;
+	
+	wire [0:2] clkNum [SPI_NUM-1:0];
+	wire [0:3] clkDiv [SPI_NUM-1:0];
+	wire [0:3] clkDivSync [SPI_NUM-1:0];
+	wire [SPI_NUM-1:0] clkCh; 
+	wire [SPI_NUM-1:0] spiClk;
+
+//================================================================================
+//	ASSIGNMENTS
+//===============================================================================
+	assign clkNum[0] = BaudRate0_i[7:5];
+	assign clkNum[1] = BaudRate1_i[7:5];
+	assign clkNum[2] = BaudRate2_i[7:5];
+	assign clkNum[3] = BaudRate3_i[7:5];
+	assign clkNum[4] = BaudRate4_i[7:5];
+	assign clkNum[5] = BaudRate5_i[7:5];
+	assign clkNum[6] = BaudRate6_i[7:5];
+
+	assign clkDiv[0] = BaudRate0_i[3:0];
+	assign clkDiv[1] = BaudRate1_i[3:0];
+	assign clkDiv[2] = BaudRate2_i[3:0];
+	assign clkDiv[3] = BaudRate3_i[3:0];
+	assign clkDiv[4] = BaudRate4_i[3:0];
+	assign clkDiv[5] = BaudRate5_i[3:0];
+	assign clkDiv[6] = BaudRate6_i[3:0];
+
+	assign clkCh[0] = BaudRate0_i[4];
+	assign clkCh[1] = BaudRate1_i[4];
+	assign clkCh[2] = BaudRate2_i[4];
+	assign clkCh[3] = BaudRate3_i[4];
+	assign clkCh[4] = BaudRate4_i[4];
+	assign clkCh[5] = BaudRate5_i[4];
+	assign clkCh[6] = BaudRate6_i[4];
+
+	assign SpiClk_o = spiClk; 
+	assign Clk100_o = clk0out;
+	assign Clk80_o = clk1out;
+
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
+
+
+//================================================================================
+//	CODING
+//================================================================================   
+	genvar i;
+
+	generate
+		for (i = 0; i < SPI_NUM; i = i + 1) begin : ClkGen
+			ClkDivider ClkDivider (
+				.Clk_i		(clk1out),
+				.ClkDiv_i	(clkDivSync[i]),
+				.Rst_i		(Rst80_i),
+				.Clk_o		(clkMan[i])
+			);
+
+			CmdSync #(
+				.WIDTH		(4),
+				.STAGES		(STAGES)
+			) CmdSync (
+				.ClkFast_i	(Clk_i),
+				.ClkSlow_i	(clk1out),
+				.ClkDiv_i	(clkDiv[i]),
+				.ClkDiv_o	(clkDivSync[i])
+			);
+
+			MmcmClkMux MmcmClkMux (
+				.Rst_i			(Rst_i),
+				.clkNum			(clkNum[i]),
+				.Clk0_i			(clk0out),
+				.Clk1_i			(clk1out),
+				.Clk2_i			(clk2out),
+				.Clk3_i			(clk3out),
+				.Clk4_i			(clk4out),
+				.Clk5_i			(clk5out),
+				.Clk6_i			(clk6out),
+				.ClkOutMMCM_o	(clkOutMMCM[i])
+			);
+	
+			SpiClkMux SpiClkMux (
+				.Rst_i		(Rst_i),
+				.clkCh		(clkCh[i]),
+				.clkOutMMCM	(clkOutMMCM[i]),
+				.clkMan		(clkMan[i]),
+				.SpiClk_o	(spiClk[i])
+			);
+		end
+	endgenerate
+	
+	MMCM MMCM
+	(
+		// Clock out ports
+		.clk_out1(clk0out),	//100 MHz
+		.clk_out2(clk1out),	// 80 MHz
+		.clk_out3(clk2out),	// 70 MHz
+		.clk_out4(clk3out),	// 60MHz
+		.clk_out5(clk4out),	// 50MHz
+		.clk_out6(clk5out),	// 40MHz
+		.clk_out7(clk6out),	// 30MHz 
+		// Status and control signals
+		.reset(Rst_i),		// input reset
+		.locked(locked),	// output locked
+		// Clock in ports
+		.clk_in1(Clk_i)		// input clk_in1
+	);
+	
+endmodule

+ 59 - 0
sources_1/new/ClkManager/CmdSync.v

@@ -0,0 +1,59 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     CmdSync
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     This module synchronize command that determines output clock 
+//					frequency to the respective clock domain 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module CmdSync #(
+	parameter WIDTH = 4,
+	parameter STAGES = 3
+)
+(
+	input ClkFast_i,
+	input ClkSlow_i,
+	input [WIDTH-1:0] ClkDiv_i,
+
+	output [WIDTH-1:0] ClkDiv_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+//lauch registers 
+reg [WIDTH-1:0] clkDivReg;
+
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] clkDivReg_c;
+
+//================================================================================
+//	ASSIGNMENTS
+//===============================================================================
+assign ClkDiv_o = clkDivReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+//================================================================================
+//	CODING
+//================================================================================ 
+always @(posedge ClkFast_i) begin
+	clkDivReg <= ClkDiv_i;
+end
+
+always @(posedge ClkSlow_i) begin
+	clkDivReg_c <= {clkDivReg_c[(STAGES-1)*WIDTH-1:0], clkDivReg};
+end
+
+endmodule

+ 74 - 0
sources_1/new/ClkManager/MmcmClkMux.v

@@ -0,0 +1,74 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     MmcmClkMux
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     This module determines which of the MMCM should be muxed based 
+//					on a input setting
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module MmcmClkMux(
+	input Rst_i,
+	input [2:0] clkNum,
+	input Clk0_i,
+	input Clk1_i,
+	input Clk2_i,
+	input Clk3_i,
+	input Clk4_i,
+	input Clk5_i,
+	input Clk6_i, 
+	
+	output ClkOutMMCM_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg clkOutMMCMReg;
+
+wire clkOutMMCM;
+
+//================================================================================
+//	ASSIGNMENTS
+//===============================================================================
+assign clkOutMMCM = clkOutMMCMReg;
+
+//================================================================================
+//	CODING
+//================================================================================ 
+always @(*) begin 
+	if (Rst_i) begin 
+		clkOutMMCMReg = 0;
+	end
+	else begin 
+		case (clkNum) 
+			0: clkOutMMCMReg = Clk0_i;
+			1: clkOutMMCMReg = Clk1_i;
+			2: clkOutMMCMReg = Clk2_i;
+			3: clkOutMMCMReg = Clk3_i;
+			4: clkOutMMCMReg = Clk4_i;
+			5: clkOutMMCMReg = Clk5_i;
+			6: clkOutMMCMReg = Clk6_i;
+			default: clkOutMMCMReg = 0;
+		endcase
+	end
+end
+
+BUFG BUFG_inst (
+	.O(ClkOutMMCM_o),	// 1-bit output: Clock output
+	.I(clkOutMMCM)		// 1-bit input: Clock input
+);
+
+endmodule

+ 67 - 0
sources_1/new/ClkManager/SpiClkMux.v

@@ -0,0 +1,67 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     SpiClkMux
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     This module muxes clock based on a clkCh signal - MMCM or 
+//					from a custom divider.
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module SpiClkMux (
+	input Rst_i,
+	input clkCh,
+	input clkOutMMCM,
+	input clkMan,
+
+	output SpiClk_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg spiClkReg;
+
+wire spiClk;
+
+//================================================================================
+//	ASSIGNMENTS
+//===============================================================================
+assign spiClk = spiClkReg;
+
+//================================================================================
+//	CODING
+//================================================================================ 
+always @(*) begin 
+	if (Rst_i) begin 
+		spiClkReg = 0;
+	end
+	else begin 
+		if (clkCh) begin 
+			spiClkReg = clkOutMMCM;
+		end
+		else begin 
+			spiClkReg = clkMan;
+		end
+	end
+end
+
+BUFG BUFG_inst (
+	.O(SpiClk_o),	// 1-bit output: Clock output
+	.I(spiClk)		// 1-bit input: Clock input
+);
+
+endmodule
+
+
+

+ 69 - 62
sources_1/new/DataFifo/DataFifoWrapper.v

@@ -1,43 +1,59 @@
-
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		SpiSubSystem
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	This is a wrapper module that contains FIFO controller and 
+//					FIFO modules 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 module DataFifoWrapper 
 #(
-    parameter	CmdRegWidth	=	32,
-    parameter	AddrRegWidth=	12,
-	parameter	STAGES		=	3,
-	
-	parameter	FifoNum	=	7
+	parameter	CMD_REG_WIDTH	=	32,
+	parameter	ADDR_REG_WIDTH	=	12,
+	parameter	STAGES			=	3,
+	parameter	FIFO_NUM		=	7
 )
 (
-    input	WrClk_i,
+	input	WrClk_i,
 	input	RdClk_i,
-    input	FifoRxRst_i,
+	input	FifoRxRst_i,
 	input	FifoTxRst_i,
 	input	FifoTxRstWrPtr_i,
 	input	FifoRxRstRdPtr_i,
-	input   SmcAre_i,
+	input	SmcAre_i,
 	input	SmcAwe_i,
-	input	[AddrRegWidth-1:0]	SmcAddr_i,
-	// input   [7:0] TxFifoWrdCnt_i,
-	// input   [7:0] RxFifoWrdCnt_i,
+	input	[ADDR_REG_WIDTH-1:0]	SmcAddr_i,
 
 	input	ToFifoVal_i,
-	input	[CmdRegWidth-1:0]	ToFifoData_i,
-	input   [CmdRegWidth-1:0]	ToFifoRxData_i,
-	input   ToFifoRxWriteVal_i,                   
+	input	[CMD_REG_WIDTH-1:0]	ToFifoData_i,
+	input	[CMD_REG_WIDTH-1:0]	ToFifoRxData_i,
+	input	ToFifoRxWriteVal_i,
 	
-	input ToFifoTxReadVal_i,
+	input	ToFifoTxReadVal_i,
 
 	output	ToSpiVal_o,
-	output EmptyFlagTx_o,
-	output [CmdRegWidth-1:0]	TxFifoCtrlReg_o,
-	output [CmdRegWidth-1:0]	RxFifoCtrlReg_o,
-	output	[CmdRegWidth-1:0]	ToSpiData_o,
-	output  [CmdRegWidth-1:0]   DataFromRxFifo_o
+	output	EmptyFlagTx_o,
+	output	[CMD_REG_WIDTH-1:0]	TxFifoCtrlReg_o,
+	output	[CMD_REG_WIDTH-1:0]	RxFifoCtrlReg_o,
+	output	[CMD_REG_WIDTH-1:0]	ToSpiData_o,
+	output	[CMD_REG_WIDTH-1:0]	DataFromRxFifo_o
 );
 //================================================================================
 //	REG/WIRE
 //================================================================================
-	wire [CmdRegWidth-1:0]	dataFromRxFifo;
+	wire [CMD_REG_WIDTH-1:0]	dataFromRxFifo;
 	wire fullFlagRx;
 	wire emptyFlagRx;
 	wire fullFlagTx;
@@ -52,19 +68,17 @@ module DataFifoWrapper
 	wire [7:0] txFifoUpDnCnt;
 
 	(* dont_touch = "true" *) wire emptyFlagTxForDsp;
-
-	//  (* dont_touch = "true" *)wire [6:0] wrDataCnt;
-	//  (* dont_touch = "true" *)wire [6:0] rdDataCnt;
 	
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
-	assign	ToSpiVal_o	=	1'b1;
+	assign ToSpiVal_o = 1'b1;
 	assign DataFromRxFifo_o = dataFromRxFifo;
 	assign EmptyFlagTx_o = emptyFlagTx;
 
-	assign TxFifoCtrlReg_o = {16'h0, txFifoUpDnCnt,5'h0,emptyFlagTxForDsp,fullFlagTx, FifoTxRst_i};
-	assign RxFifoCtrlReg_o = {16'h0, rxFifoUpDnCnt,5'h0,emptyFlagRx,fullFlagRx, FifoRxRst_i};
+	assign TxFifoCtrlReg_o = {16'h0, txFifoUpDnCnt, 5'h0, emptyFlagTxForDsp, fullFlagTx, FifoTxRst_i};
+	assign RxFifoCtrlReg_o = {16'h0, rxFifoUpDnCnt, 5'h0, emptyFlagRx, fullFlagRx, FifoRxRst_i};
+
 //================================================================================
 //	LOCALPARAMS
 //================================================================================
@@ -72,41 +86,34 @@ module DataFifoWrapper
 //================================================================================
 //	CODING
 //================================================================================
-
-	FifoCtrl FifoCtrl_inst (
-		.ToFifoTxWriteVal_i	(ToFifoVal_i),
-		.ToFifoTxReadVal_i (ToFifoTxReadVal_i),
-		.ToFifoRxWriteVal_i	(ToFifoRxWriteVal_i),
-		.ToFifoRxReadVal_i	(!SmcAre_i),
-		.SmcAddr_i			(SmcAddr_i),
-		.FifoTxFull_i		(fullFlagTx),
-		.FifoTxRst_i		(FifoTxRst_i),
-		.FifoRxRst_i		(FifoRxRst_i),
-		.FifoTxRstWrPtr_i	(FifoTxRstWrPtr_i),
-		.FifoRxRstRdPtr_i	(FifoRxRstRdPtr_i),
-		.FifoTxEmpty_i		(emptyFlagTx),
-		.FifoRxFull_i		(fullFlagRx),
-		.EmptyFlagTxForDsp_o(emptyFlagTxForDsp),
-		.FifoRxEmpty_i		(emptyFlagRx),
-		.FifoTxWrClock_i	(WrClk_i),
-		.FifoTxRdClock_i	(RdClk_i),
-		.FifoRxWrClock_i	(RdClk_i),
-		.FifoRxRdClock_i	(WrClk_i),
-		.RxFifoUpDnCnt_o	(rxFifoUpDnCnt),
-		.TxFifoUpDnCnt_o	(txFifoUpDnCnt),
-		.FifoTxWriteEn_o	(txFifoWrEn),
-		.FifoTxReadEn_o		(txFifoRdEn),
-		.FifoRxWriteEn_o	(rxFifoWrEn),
-		.FifoRxReadEn_o		(rxFifoRdEn)
-	
-	
-	
-	
-	
+	FifoCtrl FifoCtrl_inst 
+	(
+		.ToFifoTxWriteVal_i		(ToFifoVal_i),
+		.ToFifoTxReadVal_i		(ToFifoTxReadVal_i),
+		.ToFifoRxWriteVal_i		(ToFifoRxWriteVal_i),
+		.ToFifoRxReadVal_i		(!SmcAre_i),
+		.SmcAddr_i				(SmcAddr_i),
+		.FifoTxFull_i			(fullFlagTx),
+		.FifoTxRst_i			(FifoTxRst_i),
+		.FifoRxRst_i			(FifoRxRst_i),
+		.FifoTxRstWrPtr_i		(FifoTxRstWrPtr_i),
+		.FifoRxRstRdPtr_i		(FifoRxRstRdPtr_i),
+		.FifoTxEmpty_i			(emptyFlagTx),
+		.FifoRxFull_i			(fullFlagRx),
+		.EmptyFlagTxForDsp_o	(emptyFlagTxForDsp),
+		.FifoRxEmpty_i			(emptyFlagRx),
+		.FifoTxWrClock_i		(WrClk_i),
+		.FifoTxRdClock_i		(RdClk_i),
+		.FifoRxWrClock_i		(RdClk_i),
+		.FifoRxRdClock_i		(WrClk_i),
+		.RxFifoUpDnCnt_o		(rxFifoUpDnCnt),
+		.TxFifoUpDnCnt_o		(txFifoUpDnCnt),
+		.FifoTxWriteEn_o		(txFifoWrEn),
+		.FifoTxReadEn_o			(txFifoRdEn),
+		.FifoRxWriteEn_o		(rxFifoWrEn),
+		.FifoRxReadEn_o			(rxFifoRdEn)
 	);
 	
-	
-	
 	DataFifoTx	DataFifoTx
 	( 
 		.wr_clk		(WrClk_i), 
@@ -133,4 +140,4 @@ module DataFifoWrapper
 		.empty		(emptyFlagRx)
 	);
 	
-	endmodule
+endmodule

+ 0 - 168
sources_1/new/DataFifo/DataOutMux.v

@@ -1,168 +0,0 @@
-module DataOutMux#(
-    parameter	CmdRegWidth	=	32,
-    parameter	AddrRegWidth=	12
-
-
-
-) (
-    input Rst_i,
-    input FifoRxRst_i,
-    input Clk_i,
-    input SmcAre_i,
-    input [AddrRegWidth-1:0] Addr_i,
-    input [AddrRegWidth-1:0] ToRegMapAddr_i,
-    input RequestToFifo_i,
-    input ToFifoVal_i,
-    input [CmdRegWidth/2-1:0] DataFromRegMap_i,
-    input [CmdRegWidth-1:0] DataFromRxFifo1_i,
-    input [CmdRegWidth-1:0] DataFromRxFifo2_i,
-    input [CmdRegWidth-1:0] DataFromRxFifo3_i,
-    input [CmdRegWidth-1:0] DataFromRxFifo4_i,
-    input [CmdRegWidth-1:0] DataFromRxFifo5_i,
-    input [CmdRegWidth-1:0] DataFromRxFifo6_i,
-    input [CmdRegWidth-1:0] DataFromRxFifo7_i,
-
-    output [CmdRegWidth/2-1:0] AnsData_o
-
-);
-
-
-    wire [0:31] dataFromRxFifo [6:0];
-    wire [15:0] dataFromRegMap;
-    
-    reg [15:0] dataFromRxFifoR;
-    reg [1:0] readEnCnt;
-    
-    (* dont_touch = "true" *)reg [CmdRegWidth/2-1:0] dataFromRxFifoR1;
-    reg [CmdRegWidth-1:0] dataFromRxFifoR2;
-    reg [CmdRegWidth-1:0] dataFromRxFifoR3;
-    reg [CmdRegWidth-1:0] dataFromRxFifoR4;
-    reg [CmdRegWidth-1:0] dataFromRxFifoR5;
-    reg [CmdRegWidth-1:0] dataFromRxFifoR6;
-    reg [CmdRegWidth-1:0] dataFromRxFifoR7;
-    
-    
-    
-    assign dataFromRxFifo[0] = DataFromRxFifo1_i;
-    assign dataFromRxFifo[1] = DataFromRxFifo2_i;
-    assign dataFromRxFifo[2] = DataFromRxFifo3_i;
-    assign dataFromRxFifo[3] = DataFromRxFifo4_i;
-    assign dataFromRxFifo[4] = DataFromRxFifo5_i;
-    assign dataFromRxFifo[5] = DataFromRxFifo6_i;
-    assign dataFromRxFifo[6] = DataFromRxFifo7_i;
-    
-    assign dataFromRegMap = DataFromRegMap_i;
-    assign AnsData_o = (!RequestToFifo_i)?dataFromRegMap:dataFromRxFifoR;
-    
-    
-    always @(posedge Clk_i) begin 
-        if (FifoRxRst_i) begin 
-            readEnCnt <= 1'b0;
-        end
-        else begin 
-            if (!SmcAre_i) begin 
-                readEnCnt <= readEnCnt + 1'b1;
-            end
-            else begin 
-                readEnCnt <= 1'b0;
-            end
-        end
-    end
-    
-    
-    
-    always @(*) begin
-        if (Rst_i) begin
-            dataFromRxFifoR1 = 0;
-            dataFromRxFifoR2 = 0;
-            dataFromRxFifoR3 = 0;
-            dataFromRxFifoR4 = 0;
-            dataFromRxFifoR5 = 0;
-            dataFromRxFifoR6 = 0;
-            dataFromRxFifoR7 = 0;
-        end
-        else begin
-            if (!SmcAre_i && readEnCnt < 1 ) begin  
-                case(Addr_i) 
-                    12'h1c : begin
-                        dataFromRxFifoR1 = DataFromRxFifo1_i[31:16];
-                    end
-                    12'h6c : begin
-                        dataFromRxFifoR2 = DataFromRxFifo2_i;
-                    end
-                    12'h10c : begin
-                        dataFromRxFifoR3 = DataFromRxFifo3_i;
-                    end
-                    12'h15c : begin
-                        dataFromRxFifoR4 = DataFromRxFifo4_i;
-                    end
-                    12'h1ac : begin
-                        dataFromRxFifoR5 = DataFromRxFifo5_i;
-                    end
-                    12'h1fc : begin
-                        dataFromRxFifoR6 = DataFromRxFifo6_i;
-                    end
-                    12'h24c : begin
-                        dataFromRxFifoR7 = DataFromRxFifo7_i;
-                    end
-                endcase
-            end
-        end
-    end
-    
-    
-    
-    always @(*) begin 
-            case (Addr_i)  
-                12'h1c: begin 
-                    dataFromRxFifoR = DataFromRxFifo1_i[15:0];
-                end
-                12'h1e: begin
-                    dataFromRxFifoR = dataFromRxFifoR1;
-                end 
-                12'h6c: begin 
-                    dataFromRxFifoR =  DataFromRxFifo2_i[15:0];
-                end
-                12'h6e: begin 
-                    dataFromRxFifoR = dataFromRxFifoR2[31:16];
-                end
-                12'h10c: begin 
-                    dataFromRxFifoR =  DataFromRxFifo3_i[15:0];
-                end
-                12'h10e: begin 
-                    dataFromRxFifoR = dataFromRxFifoR3[31:16];
-                end
-                12'h15c: begin 
-                    dataFromRxFifoR =  DataFromRxFifo4_i[15:0];
-                end
-                12'h15e: begin 
-                    dataFromRxFifoR = dataFromRxFifoR4[31:16];
-                end
-                12'h1ac: begin 
-                    dataFromRxFifoR =  DataFromRxFifo5_i[15:0];
-                end
-                12'h1ae: begin 
-                    dataFromRxFifoR = dataFromRxFifoR5[31:16];
-                end
-                12'h1fc: begin 
-                    dataFromRxFifoR =  DataFromRxFifo6_i[15:0];
-                end
-                12'h1fe: begin 
-                    dataFromRxFifoR = dataFromRxFifoR6[31:16];
-                end
-                12'h24c: begin 
-                    dataFromRxFifoR =  DataFromRxFifo7_i[15:0];
-                end
-                12'h24e: begin 
-                    dataFromRxFifoR = dataFromRxFifoR7[31:16];
-                end
-                default: begin
-                    dataFromRxFifoR = 16'h0;
-                end
-            endcase
-        end
-    
-    
-    
-    
-    endmodule

+ 247 - 286
sources_1/new/DataFifo/FifoCtrl.v

@@ -1,302 +1,263 @@
-module FifoCtrl #(
-    parameter Fifo0ReadMsbAddr		= 12'h0+12'd28,
-	parameter Fifo1ReadMsbAddr		= 12'h50+12'd28,
-	parameter Fifo2ReadMsbAddr		= 12'hf0+12'd28,
-	parameter Fifo3ReadMsbAddr		= 12'h140+12'd28,
-	parameter Fifo4ReadMsbAddr		= 12'h190+12'd28,
-	parameter Fifo5ReadMsbAddr		= 12'h1e0+12'd28,
-	parameter Fifo6ReadMsbAddr		= 12'h230+12'd28,
-    parameter STAGES = 3
-
-
-
-
-)(
-    input ToFifoTxWriteVal_i,
-    input ToFifoTxReadVal_i,
-    input ToFifoRxWriteVal_i,
-    input ToFifoRxReadVal_i,
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     FifoCtrl
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     This module generate controll signals for FIFO's 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 
-    input FifoTxFull_i,
-    input FifoTxEmpty_i,
-    input FifoRxFull_i,
-    input FifoRxEmpty_i,
-    input [11:0] SmcAddr_i,
-
-
-    input FifoTxWrClock_i,
-    input FifoTxRdClock_i,
-    input FifoRxWrClock_i,
-    input FifoRxRdClock_i,
+module FifoCtrl #(
+	parameter FIFO_0_READ_MSB_ADDR = 12'h0+12'd28,
+	parameter FIFO_1_READ_MSB_ADDR = 12'h50+12'd28,
+	parameter FIFO_2_READ_MSB_ADDR = 12'hf0+12'd28,
+	parameter FIFO_3_READ_MSB_ADDR = 12'h140+12'd28,
+	parameter FIFO_4_READ_MSB_ADDR = 12'h190+12'd28,
+	parameter FIFO_5_READ_MSB_ADDR = 12'h1e0+12'd28,
+	parameter FIFO_6_READ_MSB_ADDR = 12'h230+12'd28,
+	parameter STAGES = 3
+)
+(
+	input ToFifoTxWriteVal_i,
+	input ToFifoTxReadVal_i,
+	input ToFifoRxWriteVal_i,
+	input ToFifoRxReadVal_i,
 
-    input FifoTxRst_i,
-    input FifoRxRst_i,
+	input FifoTxFull_i,
+	input FifoTxEmpty_i,
+	input FifoRxFull_i,
+	input FifoRxEmpty_i,
+	input [11:0] SmcAddr_i,
 
-    input FifoTxRstWrPtr_i,
-    input FifoRxRstRdPtr_i,
+	input FifoTxWrClock_i,
+	input FifoTxRdClock_i,
+	input FifoRxWrClock_i,
+	input FifoRxRdClock_i,
 
+	input FifoTxRst_i,
+	input FifoRxRst_i,
 
-    output  [7:0] RxFifoUpDnCnt_o,
-    output  [7:0] TxFifoUpDnCnt_o,
+	input FifoTxRstWrPtr_i,
+	input FifoRxRstRdPtr_i,
 
-    output EmptyFlagTxForDsp_o,
+	output [7:0] RxFifoUpDnCnt_o,
+	output [7:0] TxFifoUpDnCnt_o,
 
-    output FifoTxWriteEn_o,
-    output FifoTxReadEn_o,
-    output FifoRxWriteEn_o,
-    output FifoRxReadEn_o
+	output EmptyFlagTxForDsp_o,
 
+	output FifoTxWriteEn_o,
+	output FifoTxReadEn_o,
+	output FifoRxWriteEn_o,
+	output FifoRxReadEn_o
 );
 
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg fifoTxWriteEn;
+	reg fifoTxReadEn;
+	reg fifoRxWriteEn;
+	reg fifoRxReadEn;
+	
+	(* dont_touch = "true" *)reg [7:0] txFifoWrPtr;
+	(* dont_touch = "true" *)reg [7:0] txFifoRdPtr;
+	(* dont_touch = "true" *)reg [7:0] rxFifoWrPtr;
+	(* dont_touch = "true" *)reg [7:0] rxFifoRdPtr;
+	
+	(* dont_touch = "true" *)reg [7:0] rxFifoUpDnCnt;
+	(* dont_touch = "true" *)reg [7:0] txFifoUpDnCnt;
+	
+	reg [1:0] readEnCnt;
+	reg emptyFlagTxForDsp;    
+		
+	wire requestToFifo0	= (SmcAddr_i == FIFO_0_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo1	= (SmcAddr_i == FIFO_1_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo2	= (SmcAddr_i == FIFO_2_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo3	= (SmcAddr_i == FIFO_3_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo4	= (SmcAddr_i == FIFO_4_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo5	= (SmcAddr_i == FIFO_5_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo6	= (SmcAddr_i == FIFO_6_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	
+	wire requestToFifo	= (requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6) ? 1'b1 : 1'b0;
 
-    reg fifoTxWriteEn;
-    reg fifoTxReadEn;
-    reg fifoRxWriteEn;
-    reg fifoRxReadEn;
-    
-    (* dont_touch = "true" *)reg [7:0] txFifoWrPtr;
-    (* dont_touch = "true" *)reg [7:0] txFifoRdPtr;
-    (* dont_touch = "true" *)reg [7:0] rxFifoWrPtr;
-    (* dont_touch = "true" *)reg [7:0] rxFifoRdPtr;
-    
-    (* dont_touch = "true" *)reg [7:0] rxFifoUpDnCnt;
-    (* dont_touch = "true" *)reg [7:0] txFifoUpDnCnt;
-    
-    reg [1:0] readEnCnt;
-    reg emptyFlagTxForDsp;    
-    
-    
-    
-    wire	requestToFifo0	=(SmcAddr_i == Fifo0ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo1	=(SmcAddr_i == Fifo1ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo2	=(SmcAddr_i == Fifo2ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo3	=(SmcAddr_i == Fifo3ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo4	=(SmcAddr_i == Fifo4ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo5	=(SmcAddr_i == Fifo5ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo6	=(SmcAddr_i == Fifo6ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo   =(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6)?1'b1:1'b0;
-
-    wire [7:0] rxFifoWrPtrSync;
-    wire [7:0] txFifoWrPtrSync;
-    wire [7:0] txFifoRdPtrSync;
-
-    wire rxFifoRstSync;
-
-    
-    
-    
-    // //================================================================================
-    // //	ASSIGNMENTS
-    
-    assign FifoTxWriteEn_o = fifoTxWriteEn;
-    assign FifoTxReadEn_o = fifoTxReadEn;
-    assign FifoRxWriteEn_o = fifoRxWriteEn;
-    assign FifoRxReadEn_o = fifoRxReadEn;
-    
-    
-    assign RxFifoUpDnCnt_o = rxFifoUpDnCnt;
-    assign TxFifoUpDnCnt_o = txFifoUpDnCnt;
-    
-
-    assign EmptyFlagTxForDsp_o = emptyFlagTxForDsp;
-    
-    // //================================================================================
-    
-
-    RxFifoPtrSync #(
-        .WIDTH(8),
-        .STAGES(3)
-    )
-    rxFifoPtrSync (
-        .ClkFast_i(FifoRxWrClock_i),
-        .ClkSlow_i(FifoRxRdClock_i),
-        .RxFifoWrPtr_i(rxFifoWrPtr),
-        .RxFifoWrPtr_o(rxFifoWrPtrSync)
-    );
-
-    // TxFifoPtrSync #(
-    //     .WIDTH(8),
-    //     .STAGES(3)
-    // )
-    // txFifoPtrSync (
-    //     .ClkFast_i(FifoTxWrClock_i),
-    //     .ClkSlow_i(FifoTxRdClock_i),
-    //     .TxFifoWrPtr_i(txFifoWrPtr),
-    //     .TxFifoWrPtr_o(txFifoWrPtrSync)
-    // );
-
-    // RxFifoRstSync #(
-    //     .WIDTH(1),
-    //     .STAGES(3)
-    // )
-    // rxFifoRstSync (
-    //     .ClkFast_i(FifoRxWrClock_i),
-    //     .ClkSlow_i(FifoRxRdClock_i),
-    //     .RxFifoRst_i(FifoRxRst_i),
-    //     .RxFifoRst_o(rxFifoRstSync)
-    // );
-
-
-    TxFifoPtrSync #(
-        .WIDTH(8),
-        .STAGES(3)
-    )
-    txFifoPtrSync (
-        .ClkFast_i(FifoTxRdClock_i),
-        .ClkSlow_i(FifoTxWrClock_i),
-        .TxFifoWrPtr_i(txFifoRdPtr),
-        .TxFifoWrPtr_o(txFifoRdPtrSync)
-    );
+	wire [7:0] rxFifoWrPtrSync;
+	wire [7:0] txFifoWrPtrSync;
+	wire [7:0] txFifoRdPtrSync;
 
-    
-    always @(posedge FifoRxRdClock_i) begin 
-        if (FifoRxRstRdPtr_i) begin 
-            readEnCnt <= 1'b0;
-        end
-        else begin 
-            if (ToFifoRxReadVal_i) begin 
-                readEnCnt <= readEnCnt + 1'b1;
-            end
-            else begin 
-                readEnCnt <= 1'b0;
-            end
-        end
-    end
-    
-    
-    
-    always @(posedge FifoTxWrClock_i) begin 
-        if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
-            fifoTxWriteEn <= 1'b1;
-        end
-        else begin 
-            fifoTxWriteEn <= 1'b0;
-        end
-    end
-    
-    
-    always @(posedge FifoTxRdClock_i ) begin 
-        if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
-            fifoTxReadEn <= 1'b1;
-        end
-        else begin 
-            fifoTxReadEn <= 1'b0;
-        end
-    end
-    
-    
-    always @(posedge FifoRxWrClock_i) begin 
-        if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
-            fifoRxWriteEn <= 1'b1;
-        end
-        else begin 
-            fifoRxWriteEn <= 1'b0;
-        end
-    end
-    
-    
-    always @(posedge FifoRxRdClock_i) begin 
-        if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo && readEnCnt < 1 ) begin 
-            fifoRxReadEn <= 1'b1;
-        end
-        else begin 
-            fifoRxReadEn <= 1'b0;
-        end
-    end
-    
-    
-    always @(posedge FifoTxWrClock_i ) begin 
-        if (FifoTxRstWrPtr_i) begin 
-            txFifoWrPtr <= 8'h0;
-        end
-        else begin 
-            if (fifoTxWriteEn  ) begin 
-                txFifoWrPtr <= txFifoWrPtr + 1'b1;
-            end
-        end
-    end
-    
-    always @(posedge FifoTxRdClock_i ) begin 
-        if (FifoTxRst_i) begin 
-            txFifoRdPtr <= 8'h0;
-        end
-        else begin 
-            if (fifoTxReadEn ) begin 
-                txFifoRdPtr <= txFifoRdPtr + 1'b1;
-            end
-        end
-    end
-    
-    
-    always @(posedge FifoRxWrClock_i) begin 
-        if (FifoRxRst_i) begin 
-            rxFifoWrPtr <= 8'h0;
-        end
-        else begin
-            if (fifoRxWriteEn ) begin 
-                rxFifoWrPtr <= rxFifoWrPtr + 1'b1;
-            end
-        end
-    end
-    
-    always @(posedge FifoRxRdClock_i) begin 
-        if (FifoRxRstRdPtr_i) begin 
-            rxFifoRdPtr <= 8'h0;
-        end
-        else begin 
-            if (fifoRxReadEn ) begin 
-                rxFifoRdPtr <= rxFifoRdPtr + 1'b1;
-            end
-        end
-    end
-    
-    
-    always @(posedge FifoRxRdClock_i) begin 
-        if (FifoRxRstRdPtr_i) begin 
-            rxFifoUpDnCnt <= 8'h0;
-        end
-        else begin 
-            rxFifoUpDnCnt <= rxFifoWrPtrSync - rxFifoRdPtr;
-        end
-    end
-    
-    always @(posedge FifoTxWrClock_i) begin 
-        if (FifoTxRst_i) begin 
-            txFifoUpDnCnt <= 8'h0;
-        end
-        else begin 
-            txFifoUpDnCnt <= txFifoWrPtr - txFifoRdPtrSync;
-        end
-    end
-    
-    
-    // always @(posedge FifoTxWrClock_i) begin 
-    //     if (FifoTxRstWrPtr_i) begin 
-    //         emptyFlagTxForDsp <= 1'b1;
-    //     end
-    //     else begin 
-    //         if (txFifoWrPtr == txFifoRdPtr) begin 
-    //             emptyFlagTxForDsp <= 1'b1;
-    //         end
-    //         else begin 
-    //             emptyFlagTxForDsp <= 1'b0;
-    //         end
-    //     end
-    // end
+	wire rxFifoRstSync;
 
-    always @(*) begin
-        if (txFifoUpDnCnt == 8'h0) begin
-            emptyFlagTxForDsp <= 1'b1;
-        end
-        else begin
-            emptyFlagTxForDsp <= 1'b0;
-        end
-    end
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================	
+	assign FifoTxWriteEn_o = fifoTxWriteEn;
+	assign FifoTxReadEn_o = fifoTxReadEn;
+	assign FifoRxWriteEn_o = fifoRxWriteEn;
+	assign FifoRxReadEn_o = fifoRxReadEn;
+	
+	assign RxFifoUpDnCnt_o = rxFifoUpDnCnt;
+	assign TxFifoUpDnCnt_o = txFifoUpDnCnt;
+	
+	assign EmptyFlagTxForDsp_o = emptyFlagTxForDsp;
+	
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
 
+//================================================================================
+//	CODING
+//================================================================================
+	RxFifoPtrSync #(
+		.WIDTH	(8),
+		.STAGES	(STAGES)
+	)
+	rxFifoPtrSync (
+		.ClkFast_i		(FifoRxWrClock_i),
+		.ClkSlow_i		(FifoRxRdClock_i),
+		.RxFifoWrPtr_i	(rxFifoWrPtr),
+		.RxFifoWrPtr_o	(rxFifoWrPtrSync)
+	);
 
+	TxFifoPtrSync #(
+		.WIDTH	(8),
+		.STAGES	(STAGES)
+	)
+	txFifoPtrSync (
+		.ClkFast_i(FifoTxRdClock_i),
+		.ClkSlow_i(FifoTxWrClock_i),
+		.TxFifoWrPtr_i(txFifoRdPtr),
+		.TxFifoWrPtr_o(txFifoRdPtrSync)
+	);
+	
+	always @(posedge FifoRxRdClock_i) begin 
+		if (FifoRxRstRdPtr_i) begin 
+			readEnCnt <= 1'b0;
+		end
+		else begin 
+			if (ToFifoRxReadVal_i) begin 
+				readEnCnt <= readEnCnt + 1'b1;
+			end
+			else begin 
+				readEnCnt <= 1'b0;
+			end
+		end
+	end
+	
+	always @(posedge FifoTxWrClock_i) begin 
+		if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
+			fifoTxWriteEn <= 1'b1;
+		end
+		else begin 
+			fifoTxWriteEn <= 1'b0;
+		end
+	end
+	
+	always @(posedge FifoTxRdClock_i) begin 
+		if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
+			fifoTxReadEn <= 1'b1;
+		end
+		else begin 
+			fifoTxReadEn <= 1'b0;
+		end
+	end
+	
+	always @(posedge FifoRxWrClock_i) begin 
+		if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
+			fifoRxWriteEn <= 1'b1;
+		end
+		else begin 
+			fifoRxWriteEn <= 1'b0;
+		end
+	end
+	
+	always @(posedge FifoRxRdClock_i) begin 
+		if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo && readEnCnt < 1 ) begin 
+			fifoRxReadEn <= 1'b1;
+		end
+		else begin 
+			fifoRxReadEn <= 1'b0;
+		end
+	end
+	
+	always @(posedge FifoTxWrClock_i) begin 
+		if (FifoTxRstWrPtr_i) begin 
+			txFifoWrPtr <= 8'h0;
+		end
+		else begin 
+			if (fifoTxWriteEn  ) begin 
+				txFifoWrPtr <= txFifoWrPtr + 1'b1;
+			end
+		end
+	end
+	
+	always @(posedge FifoTxRdClock_i) begin 
+		if (FifoTxRst_i) begin 
+			txFifoRdPtr <= 8'h0;
+		end
+		else begin 
+			if (fifoTxReadEn) begin 
+				txFifoRdPtr <= txFifoRdPtr + 1'b1;
+			end
+		end
+	end
+	
+	always @(posedge FifoRxWrClock_i) begin 
+		if (FifoRxRst_i) begin 
+			rxFifoWrPtr <= 8'h0;
+		end
+		else begin
+			if (fifoRxWriteEn) begin 
+				rxFifoWrPtr <= rxFifoWrPtr + 1'b1;
+			end
+		end
+	end
+	
+	always @(posedge FifoRxRdClock_i) begin 
+		if (FifoRxRstRdPtr_i) begin 
+			rxFifoRdPtr <= 8'h0;
+		end
+		else begin 
+			if (fifoRxReadEn) begin 
+				rxFifoRdPtr <= rxFifoRdPtr + 1'b1;
+			end
+		end
+	end
+	
+	always @(posedge FifoRxRdClock_i) begin 
+		if (FifoRxRstRdPtr_i) begin 
+			rxFifoUpDnCnt <= 8'h0;
+		end
+		else begin 
+			rxFifoUpDnCnt <= rxFifoWrPtrSync - rxFifoRdPtr;
+		end
+	end
+	
+	always @(posedge FifoTxWrClock_i) begin 
+		if (FifoTxRst_i) begin 
+			txFifoUpDnCnt <= 8'h0;
+		end
+		else begin 
+			txFifoUpDnCnt <= txFifoWrPtr - txFifoRdPtrSync;
+		end
+	end
 
-    
-    
-    // //================================================================================
-    
-    endmodule
+	always @(*) begin
+		if (txFifoUpDnCnt == 8'h0) begin
+			emptyFlagTxForDsp <= 1'b1;
+		end
+		else begin
+			emptyFlagTxForDsp <= 1'b0;
+		end
+	end
+	
+endmodule

+ 32 - 17
sources_1/new/DataFifo/RxFifoPtrSync.v

@@ -1,9 +1,26 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     RxFifoPtrSync
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
 module RxFifoPtrSync #(
     parameter WIDTH = 8,
     parameter STAGES = 3
-
-
-
 )
 (
     input ClkFast_i,
@@ -13,35 +30,33 @@ module RxFifoPtrSync #(
     output [WIDTH-1:0] RxFifoWrPtr_o
 );
 
-
-
-
+//================================================================================
+//  REG/WIRE
+//================================================================================
 //lauch registers 
 reg [WIDTH-1:0] rxFifoWrPtrReg;
 
-
 // capture registers
 (* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rxFifoWrPtrReg_c;
 
-
-
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
 assign RxFifoWrPtr_o = rxFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
 
+//================================================================================
+//  CODING
+//================================================================================
 always @(posedge ClkFast_i) begin
     rxFifoWrPtrReg <= RxFifoWrPtr_i;
 end
 
-
-
-
-
 always @(posedge ClkSlow_i) begin
     rxFifoWrPtrReg_c <= {rxFifoWrPtrReg_c[(STAGES-1)*WIDTH-1:0], rxFifoWrPtrReg};
 end
 
-
-
-
-
 endmodule

+ 32 - 15
sources_1/new/DataFifo/RxFifoRstSync.v

@@ -1,9 +1,26 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     RxFifoRstSync
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
 module RxFifoRstSync #(
     parameter WIDTH = 1,
     parameter STAGES = 3
-
-
-
 )
 (
     input ClkFast_i,
@@ -13,33 +30,33 @@ module RxFifoRstSync #(
     output [WIDTH-1:0] RxFifoRst_o
 );
 
-
-
-
-
+//================================================================================
+//  REG/WIRE
+//================================================================================
 //lauch registers 
 reg [WIDTH-1:0] rxFifoRstReg;
 
-
 // capture registers
 (* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rxFifoRstReg_c;
 
-
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
 assign RxFifoWrPtr_o = rxFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
 
-
+//================================================================================
+//  CODING
+//================================================================================
 always @(posedge ClkFast_i) begin
     rxFifoRstReg <= RxFifoRst_i;
 end
 
-
 always @(posedge ClkSlow_i) begin
     rxFifoRstReg_c <= {rxFifoRstReg_c[(STAGES-1)*WIDTH-1:0], rxFifoRstReg};
 end
 
-
-
-
-
 endmodule

+ 32 - 14
sources_1/new/DataFifo/TxFifoPtrsync.v

@@ -1,9 +1,26 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     TxFifoPtrSync
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
 module TxFifoPtrSync #(
     parameter WIDTH = 8,
     parameter STAGES = 3
-
-
-
 )
 (
     input ClkFast_i,
@@ -13,32 +30,33 @@ module TxFifoPtrSync #(
     output [WIDTH-1:0] TxFifoWrPtr_o
 );
 
+//================================================================================
+//  REG/WIRE
+//================================================================================
 //lauch registers 
 reg [WIDTH-1:0] txFifoWrPtrReg;
 
-
 // capture registers
 (* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] txFifoWrPtrReg_c;
 
-
-
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
 assign TxFifoWrPtr_o = txFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
 
+//================================================================================
+//  CODING
+//================================================================================
 always @(posedge ClkFast_i) begin
     txFifoWrPtrReg <= TxFifoWrPtr_i;
 end
 
-
-
-
-
 always @(posedge ClkSlow_i) begin
     txFifoWrPtrReg_c <= {txFifoWrPtrReg_c[(STAGES-1)*WIDTH-1:0], txFifoWrPtrReg};
 end
 
-
-
-
-
 endmodule

+ 0 - 53
sources_1/new/MMCM/ClkCh.v

@@ -1,53 +0,0 @@
-module ClkCh (
-    input Rst_i,
-    input clkCh,
-    input clkOutMMCM,
-    input clkMan,
-
-    output SpiClk_o
-
-
-
-);
-
-
-reg spiClkReg;
-
-wire spiClk;
-
-assign spiClk = spiClkReg;
-
-
-
-always @(*) begin 
-    if (Rst_i) begin 
-        spiClkReg = 0;
-    end
-    else begin 
-        if (clkCh) begin 
-            spiClkReg = clkOutMMCM;
-        end
-        else begin 
-            spiClkReg = clkMan;
-        end
-    end
-end
-
-
-
-BUFG BUFG_inst (
-   .O(SpiClk_o), // 1-bit output: Clock output
-   .I(spiClk)  // 1-bit input: Clock input
-);
-
-
-
-
-
-
-
-
-endmodule
-
-
-

+ 0 - 44
sources_1/new/MMCM/ClkDivSync.v

@@ -1,44 +0,0 @@
-module ClkDivSync #(
-    parameter WIDTH = 4,
-    parameter STAGES = 3
-
-
-
-)
-(
-    input ClkFast_i,
-    input ClkSlow_i,
-    input [WIDTH-1:0] ClkDiv_i,
-
-    output [WIDTH-1:0] ClkDiv_o
-);
-
-
-//lauch registers 
-reg [WIDTH-1:0] clkDivReg;
-
-// capture registers
-(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] clkDivReg_c;
-
-
-assign ClkDiv_o = clkDivReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
-
-
-
-always @(posedge ClkFast_i) begin
-    clkDivReg <= ClkDiv_i;
-end
-
-
-
-
-
-always @(posedge ClkSlow_i) begin
-    clkDivReg_c <= {clkDivReg_c[(STAGES-1)*WIDTH-1:0], clkDivReg};
-end
-
-
-
-
-
-endmodule

+ 0 - 36
sources_1/new/MMCM/ClkGen.v

@@ -1,36 +0,0 @@
-module ClkGen (
-  input Clk_i,
-  input [3:0] ClkDiv_i,
-  input Rst_i,
-  output Clk_o
-);
-
-reg [16:0] cnt;
-
-reg clk;
-wire clk_o;
-
-
-always @(posedge Clk_i) begin 
-    if (Rst_i) begin 
-        cnt <= 0;
-    end
-    else begin 
-        if (cnt >= ClkDiv_i-1) begin 
-            cnt <= 0;
-        end
-        else begin 
-            cnt <= cnt + 1;
-        end
-    end
-end
-
-assign Clk_o = (cnt < ClkDiv_i/2) ? 1 : 0;
-
-
-
-
-
-
-
-endmodule

+ 0 - 47
sources_1/new/MMCM/ClkGen_tb.v

@@ -1,47 +0,0 @@
-`timescale 1ns / 1ps
-module ClkGen_tb();
-
-
-
-
-
-
-reg Clk_i;
-reg Rst_i;
-
-reg [3:0] clkDiv_i;
-
-
-
-
-
-
-always #(1.667/2) Clk_i = ~Clk_i;
-
-
-
-
-ClkGenGowin ClkGen_inst (
-    .Clk_i(Clk_i), 
-    .Rst_i(Rst_i), 
-    .Clk75_o(),
-    .Clk40_o(),
-    .Clk30_o(),
-    .Clk5_o()
-);
-
-
-
-initial begin 
-    Clk_i = 0;
-    Rst_i = 1;
-    clkDiv_i = 3;
-    #1000;
-    Rst_i = 0;
-
-end
-
-
-
-
-endmodule

+ 0 - 55
sources_1/new/MMCM/ClkOutMMCM.v

@@ -1,55 +0,0 @@
-module clkOutMMCM(
-input Rst_i,
-input [2:0]clkNum,
-input clk0out,
-input clk1out,
-input clk2out,
-input clk3out,
-input clk4out,
-input clk5out,
-input clk6out, 
-
-output   ClkOutMMCM_o
-
-);
-
-
-reg clkOutMMCMReg;
-
-wire clkOutMMCM;
-
-assign clkOutMMCM = clkOutMMCMReg;
-
-
-always @(*) begin 
-    if (Rst_i) begin 
-        clkOutMMCMReg = 0;
-    end
-    else begin 
-        case (clkNum) 
-            0: clkOutMMCMReg = clk0out;
-            1: clkOutMMCMReg = clk1out;
-            2: clkOutMMCMReg = clk2out;
-            3: clkOutMMCMReg = clk3out;
-            4: clkOutMMCMReg = clk4out;
-            5: clkOutMMCMReg = clk5out;
-            6: clkOutMMCMReg = clk6out;
-            default: clkOutMMCMReg = 0;
-        endcase
-    end
-end
-
-
-
-
-BUFG BUFG_inst (
-   .O(ClkOutMMCM_o), // 1-bit output: Clock output
-   .I(clkOutMMCM)  // 1-bit input: Clock input
-);
-
-
-
-
-
-
-endmodule

+ 0 - 158
sources_1/new/MMCM/MmcmWrapper.v

@@ -1,158 +0,0 @@
-
-module MmcmWrapper 
-#(
-	parameter	SpiNum	=	7,
-   parameter   STAGES   =  3
-)
-(
-   input	Clk_i,
-   input	Rst_i,
-   input Rst80_i,
-   input [7:0] BaudRate0_i,
-   input [7:0] BaudRate1_i,
-   input [7:0] BaudRate2_i,
-   input [7:0] BaudRate3_i,
-   input [7:0] BaudRate4_i,
-   input [7:0] BaudRate5_i,
-   input [7:0] BaudRate6_i,
-
-
-   output   Clk80_o,
-	output 	[SpiNum-1:0]	SpiClk_o
-   
-);
-//================================================================================
-//	REG/WIRE
-//================================================================================
-	
-wire    clk0out;
-wire    clk1out;
-wire    clk2out;
-wire    clk3out;
-wire    clk4out;
-wire    clk5out;
-wire    clk6out;
-wire    locked;
-
-wire [SpiNum-1:0] clkOutMMCM;
-
-
-wire [SpiNum-1:0] clkMan;
-
-wire [0:2] clkNum [SpiNum-1:0];
-wire [0:3] clkDiv [SpiNum-1:0];
-wire [0:3] clkDivSync [SpiNum-1:0];
-wire [SpiNum-1:0] clkCh; 
-wire [SpiNum-1:0] spiClk;
-
-
-
-//================================================================================
-//	ASSIGNMENTS
-//===============================================================================
-   assign clkNum[0] = BaudRate0_i[7:5];
-   assign clkNum[1] = BaudRate1_i[7:5];
-   assign clkNum[2] = BaudRate2_i[7:5];
-   assign clkNum[3] = BaudRate3_i[7:5];
-   assign clkNum[4] = BaudRate4_i[7:5];
-   assign clkNum[5] = BaudRate5_i[7:5];
-   assign clkNum[6] = BaudRate6_i[7:5];
-
-   assign clkDiv[0] = BaudRate0_i[3:0];
-   assign clkDiv[1] = BaudRate1_i[3:0];
-   assign clkDiv[2] = BaudRate2_i[3:0];
-   assign clkDiv[3] = BaudRate3_i[3:0];
-   assign clkDiv[4] = BaudRate4_i[3:0];
-   assign clkDiv[5] = BaudRate5_i[3:0];
-   assign clkDiv[6] = BaudRate6_i[3:0];
-
-   assign clkCh[0] = BaudRate0_i[4];
-   assign clkCh[1] = BaudRate1_i[4];
-   assign clkCh[2] = BaudRate2_i[4];
-   assign clkCh[3] = BaudRate3_i[4];
-   assign clkCh[4] = BaudRate4_i[4];
-   assign clkCh[5] = BaudRate5_i[4];
-   assign clkCh[6] = BaudRate6_i[4];
-
-   // assign SpiClk_o[0] = spiClk[0];
-   // assign SpiClk_o[1] = spiClk[1];
-   // assign SpiClk_o[2] = spiClk[2];
-   // assign SpiClk_o[3] = spiClk[3];
-   // assign SpiClk_o[4] = spiClk[4];
-   // assign SpiClk_o[5] = spiClk[5];
-   // assign SpiClk_o[6] = spiClk[6];
-
-   assign SpiClk_o = spiClk; 
-   assign Clk100_o = clk0out;
-   assign Clk80_o = clk1out;
-
-   //================================================================================
-   //	LOCALPARAMS
-   //================================================================================
-   
-   
-   //================================================================================
-   //	CODING
-   //================================================================================   
-   genvar i;
-
-   generate
-      for (i=0; i < SpiNum; i = i +1) begin : ClkGen
-         ClkGen ClkGen_inst (
-            .Clk_i(clk1out),
-            .ClkDiv_i(clkDivSync[i]),
-            .Rst_i(Rst80_i),
-            .Clk_o(clkMan[i])
-         );
-
-         ClkDivSync #(
-            .WIDTH(4),
-            .STAGES(STAGES)
-         ) ClkDiv_Inst (
-            .ClkFast_i(Clk_i),
-            .ClkSlow_i(clk1out),
-            .ClkDiv_i(clkDiv[i]),
-            .ClkDiv_o(clkDivSync[i])
-
-         );
-
-         clkOutMMCM clkOutMMCM_inst (
-            .Rst_i(Rst_i),
-            .clkNum(clkNum[i]),
-            .clk0out(clk0out),
-            .clk1out(clk1out),
-            .clk2out(clk2out),
-            .clk3out(clk3out),
-            .clk4out(clk4out),
-            .clk5out(clk5out),
-            .clk6out(clk6out),
-            .ClkOutMMCM_o(clkOutMMCM[i])
-         );
-   
-         ClkCh ClkCh_inst (
-            .Rst_i(Rst_i),
-            .clkCh(clkCh[i]),
-            .clkOutMMCM(clkOutMMCM[i]),
-            .clkMan(clkMan[i]),
-            .SpiClk_o(spiClk[i])
-         );
-      end
-   endgenerate
-   
-   ClkDiv ClkDiv_inst
-    (
-     // Clock out ports
-     .clk_out1(clk0out),     //100 MHz
-     .clk_out2(clk1out),     // 80 MHz
-     .clk_out3(clk2out),     // 70 MHz
-     .clk_out4(clk3out),     // 60MHz
-     .clk_out5(clk4out),     // 50MHz
-     .clk_out6(clk5out),     // 40MHz
-     .clk_out7(clk6out),     // 30MHz 
-     // Status and control signals
-     .reset(Rst_i), // input reset
-     .locked(locked),       // output locked
-    // Clock in ports
-     .clk_in1(Clk_i));      // input clk_in1
-   
-   endmodule

+ 0 - 177
sources_1/new/Mux/DataMuxer.v

@@ -1,177 +0,0 @@
-
-module DataMuxer 
-#(
-    parameter	CmdRegWidth	=	16,
-    parameter	AddrRegWidth=	12,
-	
-	parameter	FifoNum	=	7,
-	
-	// parameter	Fifo0WriteLsbAddr	=	12'h0+12'h24,
-	// parameter	Fifo0WriteMsbAddr	=	12'h0+12'h26,
-	// parameter	Fifo1WriteLsbAddr	=	12'h50+12'h24,
-	// parameter	Fifo2WriteMsbAddr	=	12'hF0+12'h26,
-	// parameter	Fifo3WriteLsbAddr	=	12'h140+12'h24,
-	// parameter	Fifo4WriteMsbAddr	=	12'h190+12'h26,
-	// parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
-	// parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
-	
-	parameter	Fifo0WriteLsbAddr	=	12'h0+12'd24,
-	parameter	Fifo0WriteMsbAddr	=	12'h0+12'd26,
-	parameter	Fifo1WriteLsbAddr	=	12'h50+12'd24,
-	parameter	Fifo1WriteMsbAddr	=	12'h50+12'd26,
-	parameter	Fifo2WriteLsbAddr	=	12'hf0+12'd24,
-	parameter	Fifo2WriteMsbAddr	=	12'hf0+12'd26,
-	parameter	Fifo3WriteLsbAddr	=	12'h140+12'd24,
-	parameter	Fifo3WriteMsbAddr	=	12'h140+12'd26,
-	parameter	Fifo4WriteLsbAddr	=	12'h190+12'd24,
-	parameter	Fifo4WriteMsbAddr	=	12'h190+12'd26,
-	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'd24,
-	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'd26,
-	parameter	Fifo6WriteLsbAddr	=	12'h230+12'd24,
-	parameter	Fifo6WriteMsbAddr	=	12'h230+12'd26,
-
-	parameter Fifo0ReadLsbAddr		= 12'h0+12'd28,
-	parameter Fifo0ReadMsbAddr		= 12'h0+12'd30,
-	parameter Fifo1ReadLsbAddr		= 12'h50+12'd28,
-	parameter Fifo1ReadMsbAddr		= 12'h50+12'd30,
-	parameter Fifo2ReadLsbAddr		= 12'hf0+12'd28,
-	parameter Fifo2ReadMsbAddr		= 12'hf0+12'd30,
-	parameter Fifo3ReadLsbAddr		= 12'h140+12'd28,
-	parameter Fifo3ReadMsbAddr		= 12'h140+12'd30,
-	parameter Fifo4ReadLsbAddr		= 12'h190+12'd28,
-	parameter Fifo4ReadMsbAddr		= 12'h190+12'd30,
-	parameter Fifo5ReadLsbAddr		= 12'h1e0+12'd28,
-	parameter Fifo5ReadMsbAddr		= 12'h1e0+12'd30,
-	parameter Fifo6ReadLsbAddr		= 12'h230+12'd28,
-	parameter Fifo6ReadMsbAddr		= 12'h230+12'd30
-
-
-)
-(
-    input	Clk_i,
-    input	Rst_i,
-
-	input	SmcVal_i,
-	input	[CmdRegWidth-1:0]	SmcData_i,
-    input	[AddrRegWidth-1:0]	SmcAddr_i,
-
-	output	RequestToFifo_o,
-
-	output	reg	ToRegMapVal_o,
-	output	reg	[CmdRegWidth-1:0]	ToRegMapData_o,
-    output	reg	[AddrRegWidth-1:0]	ToRegMapAddr_o,
-	
-	output	reg	[FifoNum-1:0]	ToFifoVal_o,
-	output	reg	[CmdRegWidth*2*FifoNum-1:0]	ToFifoData_o
-	
-);
-//================================================================================
-//	REG/WIRE
-//================================================================================
-	wire	requestToFifo0	=((SmcAddr_i==Fifo0WriteLsbAddr||SmcAddr_i==Fifo0WriteMsbAddr)|| (SmcAddr_i==Fifo0ReadLsbAddr||SmcAddr_i==Fifo0ReadMsbAddr));
-	wire	requestToFifo1	=((SmcAddr_i==Fifo1WriteLsbAddr||SmcAddr_i==Fifo1WriteMsbAddr)|| (SmcAddr_i==Fifo1ReadLsbAddr||SmcAddr_i==Fifo1ReadMsbAddr));
-	wire	requestToFifo2	=((SmcAddr_i==Fifo2WriteLsbAddr||SmcAddr_i==Fifo2WriteMsbAddr)|| (SmcAddr_i==Fifo2ReadLsbAddr||SmcAddr_i==Fifo2ReadMsbAddr));
-	wire	requestToFifo3	=((SmcAddr_i==Fifo3WriteLsbAddr||SmcAddr_i==Fifo3WriteMsbAddr)|| (SmcAddr_i==Fifo3ReadLsbAddr||SmcAddr_i==Fifo3ReadMsbAddr));
-	wire	requestToFifo4	=((SmcAddr_i==Fifo4WriteLsbAddr||SmcAddr_i==Fifo4WriteMsbAddr)|| (SmcAddr_i==Fifo4ReadLsbAddr||SmcAddr_i==Fifo4ReadMsbAddr));
-	wire	requestToFifo5	=((SmcAddr_i==Fifo5WriteLsbAddr||SmcAddr_i==Fifo5WriteMsbAddr)|| (SmcAddr_i==Fifo5ReadLsbAddr||SmcAddr_i==Fifo5ReadMsbAddr));
-	wire	requestToFifo6	=((SmcAddr_i==Fifo6WriteLsbAddr||SmcAddr_i==Fifo6WriteMsbAddr)|| (SmcAddr_i==Fifo6ReadLsbAddr||SmcAddr_i==Fifo6ReadMsbAddr));
-	
-	wire	requestToFifo	=	(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6);
-//================================================================================
-//	ASSIGNMENTS
-//================================================================================
-	assign	RequestToFifo_o	=	requestToFifo;
-//================================================================================
-//	LOCALPARAMS
-//================================================================================
-
-//================================================================================
-//	CODING
-//================================================================================
-
-	always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
-		if	(Rst_i)	begin
-			ToRegMapVal_o	<=	1'b0;
-			ToRegMapData_o	<=	16'h0;
-			ToRegMapAddr_o	<=	12'h0;
-			
-			ToFifoVal_o		<=	7'h0;
-			ToFifoData_o	<=	0;
-		end	else	begin
-			if	(requestToFifo)	begin	
-				case(SmcAddr_i)	
-					Fifo0WriteLsbAddr:	begin
-										ToFifoVal_o[0]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*0+:CmdRegWidth]	<=	SmcData_i;
-									end
-					Fifo0WriteMsbAddr:	begin
-										ToFifoVal_o[0]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*1+:CmdRegWidth]	<=	SmcData_i;
-									end
-									
-					Fifo1WriteLsbAddr:	begin
-										ToFifoVal_o[1]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*2+:CmdRegWidth]	<=	SmcData_i;
-									end
-					Fifo1WriteMsbAddr:	begin
-										ToFifoVal_o[1]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*3+:CmdRegWidth]	<=	SmcData_i;
-									end
-									
-					Fifo2WriteLsbAddr:	begin
-										ToFifoVal_o[2]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
-									end
-					Fifo2WriteMsbAddr:	begin
-										ToFifoVal_o[2]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*5+:CmdRegWidth]	<=	SmcData_i;
-									end
-									
-					Fifo3WriteLsbAddr:	begin
-										ToFifoVal_o[3]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*6+:CmdRegWidth]	<=	SmcData_i;
-									end
-					Fifo3WriteMsbAddr:	begin
-										ToFifoVal_o[3]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*7+:CmdRegWidth]	<=	SmcData_i;
-									end
-									
-					Fifo4WriteLsbAddr:	begin
-										ToFifoVal_o[4]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*8+:CmdRegWidth]	<=	SmcData_i;
-									end
-					Fifo4WriteMsbAddr:	begin
-										ToFifoVal_o[4]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*9+:CmdRegWidth]	<=	SmcData_i;
-									end
-									
-					Fifo5WriteLsbAddr:	begin
-										ToFifoVal_o[5]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
-									end
-					Fifo5WriteMsbAddr:	begin
-										ToFifoVal_o[5]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*11+:CmdRegWidth]	<=	SmcData_i;
-									end
-									
-					Fifo6WriteLsbAddr:	begin
-										ToFifoVal_o[6]	<=	1'b0;
-										ToFifoData_o[CmdRegWidth*12+:CmdRegWidth]	<=	SmcData_i;
-									end
-					Fifo6WriteMsbAddr:	begin
-										ToFifoVal_o[6]	<=	SmcVal_i;
-										ToFifoData_o[CmdRegWidth*13+:CmdRegWidth]	<=	SmcData_i;
-									end
-				endcase
-				ToRegMapAddr_o	<=	0;
-				ToRegMapVal_o	<=	0;
-			end	else	begin
-				ToRegMapVal_o	<=	SmcVal_i;
-				ToFifoVal_o		<=	7'h0;
-				ToRegMapData_o	<=	SmcData_i;
-				ToRegMapAddr_o	<=	SmcAddr_i;
-				ToFifoData_o	<=	0;
-			end
-		end
-	end
-	endmodule

File diff suppressed because it is too large
+ 949 - 961
sources_1/new/QuadSPI/QuadSPIm.v


+ 144 - 0
sources_1/new/QuadSPI/QuadSPImTb.v

@@ -0,0 +1,144 @@
+`timescale 1ns / 1ps
+
+module QuadSPImTb ();
+
+
+parameter CLK_PERIOD = 8.13; // Clock period in ns
+
+//================================================================================
+//  REG/WIRE
+//================================================================================
+reg rst;
+reg clk;
+
+localparam [31:0] startData = 32'h01010101;
+// localparam [31:0] startData = 32'h0A0B0C0D;
+
+reg [31:0] data;
+reg [31:0] dataS;
+
+wire [1:0] widthSel  = 2'h2;
+wire clockPol = 1'b0;
+wire clockPhase = 1'b0;
+wire endianSel = 1'b0;
+wire lag = 1'b0;
+wire lead = 1'b0;
+wire [5:0] stopDelay = 6'h1;
+wire selSt = 1'b0;
+wire val;
+wire valS;
+
+reg [31:0] tbCnt;
+
+wire start = (tbCnt>=100);
+wire fifoEmpty = (tbCnt >= 199);
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+
+
+//================================================================================
+//  CODING
+//================================================================================	
+
+always #(CLK_PERIOD/2) clk = ~clk;
+
+initial begin
+	clk = 0;
+	rst = 0;
+	#40
+	rst = 1;
+	#100
+	rst = 0;
+end
+
+always @(posedge clk) begin
+	if (rst) begin
+		tbCnt <= 0;
+	end else begin
+		tbCnt <= tbCnt+1;
+	end
+end
+
+always @(posedge clk) begin
+	if (rst) begin
+		data <= startData;
+	end else if (val) begin
+		data <= data+32'h10;
+	end
+end
+
+always @(posedge clk) begin
+	if (rst) begin
+		dataS <= 32'h0000000A;
+	end else if (valS) begin
+	// end else begin
+		case(widthSel) 
+			0:	begin
+					dataS <= dataS+32'h10;
+					// dataS <= 32'h0000000A;
+				end
+			1:	begin
+					dataS <= dataS+32'h100;
+					// dataS <= 32'h00000A0A;
+				end
+			2:	begin
+					dataS <= dataS+32'h100;
+					// dataS <= 32'h000A0A0A;
+				end
+			3:	begin
+					dataS <= dataS+32'h100;
+					// dataS <= 32'h0A0A0A0A;
+				end
+		endcase
+	end
+end
+
+QuadSPIm QuadSPIm
+(
+	.Clk_i(clk),
+	.Start_i(start),
+	.Rst_i(rst),
+	.EmptyFlag_i(fifoEmpty),
+	.SpiData_i(dataS),
+	.Sck_o(),
+	.Ss_o(),
+	.Mosi0_o(),
+	.Mosi1_o(),
+	.Mosi2_o(),
+	.Mosi3_o(),
+	.WidthSel_i(widthSel),
+	.PulsePol_i(clockPol),
+	.ClockPhase_i(clockPhase),
+	.EndianSel_i(endianSel),
+	.Lag_i(lag),
+	.Lead_i(lead),
+	.Stop_i(stopDelay),
+	.SelSt_i(selSt),
+	.Val_o(val)
+);
+
+SPIm Spi
+(
+    .Clk_i			(clk),
+    .Rst_i			(rst),
+    .Start_i		(start),
+    .EmptyFlag_i	(fifoEmpty),
+    .ClockPhase_i	(clockPhase),
+    .SpiData_i		(dataS),
+    .SelSt_i		(selSt),
+    .WidthSel_i		(widthSel),
+    .Lag_i			(lag),
+    .Lead_i			(lead),
+    .EndianSel_i	(endianSel),
+    .Stop_i			(stopDelay),
+    .PulsePol_i		(clockPol),
+
+
+    .Mosi0_o		(),
+    .Sck_o			(),
+    .Ss_o			(),
+    .Val_o			(valS)
+);			
+endmodule

+ 71 - 3
sources_1/new/QuadSPI/QuadSPIs.v

@@ -16,7 +16,8 @@ module QuadSPIs (
 
     output reg [23:0] Data_o,
     output reg [7:0] Addr_o,
-      output [31:0] DataToRxFifo_o,
+    output [31:0] DataToRxFifo_o,
+    output reg [191:0] DebugData_o,
     output reg Val_o
 );
 
@@ -42,13 +43,15 @@ reg [7:0] shiftReg1M;
 reg [7:0] shiftReg2M;
 reg [7:0] addrRegM;
 
+reg [47:0] shiftReg0Debug;
+reg [47:0] shiftReg1Debug;
+reg [47:0] shiftReg2Debug;
+reg [47:0] shiftReg3Debug;
 
 //===============================================================================
 //  ASSIGNMENTS
 
-
 assign DataToRxFifo_o = {Addr_o, Data_o};
-
 //================================================================================
 //	CODING
 //================================================================================
@@ -159,6 +162,71 @@ always @(posedge Clk_i) begin
     end
 end
 
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        DebugData_o <= 192'h0;
+    end
+    else begin 
+        DebugData_o <= {shiftReg0Debug,shiftReg1Debug, shiftReg2Debug,shiftReg3Debug};
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg0Debug <= 48'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg0Debug <= {shiftReg0Debug[46:0], Mosi0_i};
+        end
+        else begin 
+            shiftReg0Debug <= 48'h0;
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg1Debug <= 48'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg1Debug <= {shiftReg1Debug[46:0], Mosi1_i};
+        end
+        else begin 
+            shiftReg1Debug <= 48'h0;
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg2Debug <= 48'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg2Debug <= {shiftReg2Debug[46:0], Mosi2_i};
+        end
+        else begin 
+            shiftReg2Debug <= 48'h0;
+        end
+    end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg3Debug <= 48'h0;
+    end
+    else begin 
+        if (!Ss_i) begin 
+            shiftReg3Debug <= {shiftReg3Debug[46:0], Mosi3_i};
+        end
+        else begin 
+            shiftReg3Debug <= 48'h0;
+        end
+    end
+end
+
 always @(posedge Clk_i) begin 
     if (Rst_i) begin 
         Addr_o <= 8'h0;

File diff suppressed because it is too large
+ 899 - 995
sources_1/new/RegMap/RegMap.v


File diff suppressed because it is too large
+ 779 - 936
sources_1/new/S5443_3Top.v


+ 4 - 3
sources_1/new/S5443_3_tb.v

@@ -47,7 +47,7 @@ localparam ClockPhase0 = 1'b0;//
 localparam ClockPolarity0 = 1'b0;//0 for active high, 1 for active low
 localparam Assel0 = 1'b1;//0 for software control, 1 for hardware control
 localparam SelSt0 = 1'b1; //1 - assert slave select(low), 0 - deassert slave select(high)
-localparam Size0 = 2'd2; //0 - 8 bits, 1 - 16 bits, 2 - 24 bits, 3 - 32 bits
+localparam Size0 = 2'd1; //0 - 8 bits, 1 - 16 bits, 2 - 24 bits, 3 - 32 bits
 localparam Mode0 = 1'b0; // 1 - 4 Mosi, 0 - 1 Mosi
 localparam LSBF0 = 1'b0; // 1 - LSB first, 0 - MSB first
 
@@ -70,7 +70,7 @@ localparam Spi0ClkRegData = {8'h0, Mux1, Mux0, Div};
 //***********************************************
 localparam Lag0 = 1'b0; //Extended SPI clock lag control, 0 - Disable, 1 - Enable
 localparam Lead0 = 1'b0; //Extended SPI clock lead control, 0 - Disable, 1 - Enable
-localparam Stop0 = 6'd0; //Number of clock cycles to wait after CS is deasserted
+localparam Stop0 = 6'd1; //Number of clock cycles to wait after CS is deasserted
 
 localparam [15:0] Spi0CsDelayRegData = {8'h0, Stop0, Lead0, Lag0};
 
@@ -360,7 +360,8 @@ always @(posedge Clk_i) begin
             endcase
         end
         else begin 
-                SmcData_i <= $urandom_range(0, 8'hFF);
+                SmcData_i <= $urandom_range(0, 16'hFFFF);
+                // SmcData_i <= 16'hff00;
             end
     end
 end

+ 176 - 0
sources_1/new/SmcAnsMux/SmcAnsMux.v

@@ -0,0 +1,176 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		SmcAnsMux
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	This module multiplexing the data either from FIFO or a RegMap 
+//					based on an address
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+module SmcAnsMux
+#(
+	parameter	CMD_REG_WIDTH	=	32,
+	parameter	ADDR_REG_WIDTH	=	12
+)
+(
+	input Clk_i,
+	input [ADDR_REG_WIDTH-1:0] Addr_i,
+	input [ADDR_REG_WIDTH-1:0] ToRegMapAddr_i,
+	input RequestToFifo_i,
+	input FifoRxRst_i,
+	input SmcAre_i,
+
+	input [CMD_REG_WIDTH/2-1:0] DataFromRegMap_i,
+
+	input [CMD_REG_WIDTH-1:0] DataFromRxFifo1_i,
+	input [CMD_REG_WIDTH-1:0] DataFromRxFifo2_i,
+	input [CMD_REG_WIDTH-1:0] DataFromRxFifo3_i,
+	input [CMD_REG_WIDTH-1:0] DataFromRxFifo4_i,
+	input [CMD_REG_WIDTH-1:0] DataFromRxFifo5_i,
+	input [CMD_REG_WIDTH-1:0] DataFromRxFifo6_i,
+	input [CMD_REG_WIDTH-1:0] DataFromRxFifo7_i,
+
+	output [CMD_REG_WIDTH/2-1:0] AnsData_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire [0:31] dataFromRxFifo [6:0];
+	wire [15:0] dataFromRegMap;
+	
+	reg [15:0] dataFromRxFifoR;
+	reg [1:0] readEnCnt;
+	
+	(* dont_touch = "true" *)reg [CMD_REG_WIDTH/2-1:0] dataFromRxFifoR1;
+	reg [CMD_REG_WIDTH-1:0] dataFromRxFifoR2;
+	reg [CMD_REG_WIDTH-1:0] dataFromRxFifoR3;
+	reg [CMD_REG_WIDTH-1:0] dataFromRxFifoR4;
+	reg [CMD_REG_WIDTH-1:0] dataFromRxFifoR5;
+	reg [CMD_REG_WIDTH-1:0] dataFromRxFifoR6;
+	reg [CMD_REG_WIDTH-1:0] dataFromRxFifoR7;
+	
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+	assign dataFromRxFifo[0] = DataFromRxFifo1_i;
+	assign dataFromRxFifo[1] = DataFromRxFifo2_i;
+	assign dataFromRxFifo[2] = DataFromRxFifo3_i;
+	assign dataFromRxFifo[3] = DataFromRxFifo4_i;
+	assign dataFromRxFifo[4] = DataFromRxFifo5_i;
+	assign dataFromRxFifo[5] = DataFromRxFifo6_i;
+	assign dataFromRxFifo[6] = DataFromRxFifo7_i;
+	
+	assign dataFromRegMap = DataFromRegMap_i;
+	assign AnsData_o = (!RequestToFifo_i) ? dataFromRegMap : dataFromRxFifoR;
+
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
+
+//================================================================================
+//	CODING
+//================================================================================	
+	always @(posedge Clk_i) begin 
+		if (FifoRxRst_i) begin 
+			readEnCnt <= 1'b0;
+		end
+		else begin 
+			if (!SmcAre_i) begin 
+				readEnCnt <= readEnCnt + 1'b1;
+			end
+			else begin 
+				readEnCnt <= 1'b0;
+			end
+		end
+	end
+	
+	always @(*) begin
+		if (!SmcAre_i && readEnCnt < 1) begin  
+			case(Addr_i)
+				12'h1c: begin
+					dataFromRxFifoR1 = DataFromRxFifo1_i[31:16];
+				end
+				12'h6c: begin
+					dataFromRxFifoR2 = DataFromRxFifo2_i;
+				end
+				12'h10c: begin
+					dataFromRxFifoR3 = DataFromRxFifo3_i;
+				end
+				12'h15c: begin
+					dataFromRxFifoR4 = DataFromRxFifo4_i;
+				end
+				12'h1ac: begin
+					dataFromRxFifoR5 = DataFromRxFifo5_i;
+				end
+				12'h1fc: begin
+					dataFromRxFifoR6 = DataFromRxFifo6_i;
+				end
+				12'h24c: begin
+					dataFromRxFifoR7 = DataFromRxFifo7_i;
+				end
+			endcase
+		end
+	end
+	
+	always @(*) begin 
+			case (Addr_i)  
+				12'h1c: begin 
+					dataFromRxFifoR = DataFromRxFifo1_i[15:0];
+				end
+				12'h1e: begin
+					dataFromRxFifoR = dataFromRxFifoR1;
+				end 
+				12'h6c: begin 
+					dataFromRxFifoR = DataFromRxFifo2_i[15:0];
+				end
+				12'h6e: begin 
+					dataFromRxFifoR = dataFromRxFifoR2[31:16];
+				end
+				12'h10c: begin 
+					dataFromRxFifoR = DataFromRxFifo3_i[15:0];
+				end
+				12'h10e: begin 
+					dataFromRxFifoR = dataFromRxFifoR3[31:16];
+				end
+				12'h15c: begin 
+					dataFromRxFifoR = DataFromRxFifo4_i[15:0];
+				end
+				12'h15e: begin 
+					dataFromRxFifoR = dataFromRxFifoR4[31:16];
+				end
+				12'h1ac: begin 
+					dataFromRxFifoR = DataFromRxFifo5_i[15:0];
+				end
+				12'h1ae: begin 
+					dataFromRxFifoR = dataFromRxFifoR5[31:16];
+				end
+				12'h1fc: begin 
+					dataFromRxFifoR = DataFromRxFifo6_i[15:0];
+				end
+				12'h1fe: begin 
+					dataFromRxFifoR = dataFromRxFifoR6[31:16];
+				end
+				12'h24c: begin 
+					dataFromRxFifoR = DataFromRxFifo7_i[15:0];
+				end
+				12'h24e: begin 
+					dataFromRxFifoR = dataFromRxFifoR7[31:16];
+				end
+				default: begin
+					dataFromRxFifoR = 16'h0;
+				end
+			endcase
+		end
+endmodule

+ 186 - 0
sources_1/new/SmcInDataMux/SmcInDataMux.v

@@ -0,0 +1,186 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		SmcInDataMux
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	This module determines which entity is referred(FIFO or a RegMap)
+//					based on an adrress and sets a validity signal	
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+module SmcInDataMux 
+#(
+	parameter	CMD_REG_WIDTH	=	16,
+	parameter	ADDR_REG_WIDTH	=	12,
+	
+	parameter	FIFO_NUM	=	7,
+	
+	parameter	FIFO_0_WRITE_LSB_ADDR	=	12'h0+12'd24,
+	parameter	FIFO_0_WRITE_MSB_ADDR	=	12'h0+12'd26,
+	parameter	FIFO_1_WRITE_LSB_ADDR	=	12'h50+12'd24,
+	parameter	FIFO_1_WRITE_MSB_ADDR	=	12'h50+12'd26,
+	parameter	FIFO_2_WRITE_LSB_ADDR	=	12'hf0+12'd24,
+	parameter	FIFO_2_WRITE_MSB_ADDR	=	12'hf0+12'd26,
+	parameter	FIFO_3_WRITE_LSB_ADDR	=	12'h140+12'd24,
+	parameter	FIFO_3_WRITE_MSB_ADDR	=	12'h140+12'd26,
+	parameter	FIFO_4_WRITE_LSB_ADDR	=	12'h190+12'd24,
+	parameter	FIFO_4_WRITE_MSB_ADDR	=	12'h190+12'd26,
+	parameter	FIFO_5_WRITE_LSB_ADDR	=	12'h1e0+12'd24,
+	parameter	FIFO_5_WRITE_MSB_ADDR	=	12'h1e0+12'd26,
+	parameter	FIFO_6_WRITE_LSB_ADDR	=	12'h230+12'd24,
+	parameter	FIFO_6_WRITE_MSB_ADDR	=	12'h230+12'd26,
+
+	parameter	FIFO_0_READ_LSB_ADDR	=	12'h0+12'd28,
+	parameter	FIFO_0_READ_MSB_ADDR	=	12'h0+12'd30,
+	parameter	FIFO_1_READ_LSB_ADDR	=	12'h50+12'd28,
+	parameter	FIFO_1_READ_MSB_ADDR	=	12'h50+12'd30,
+	parameter	FIFO_2_READ_LSB_ADDR	=	12'hf0+12'd28,
+	parameter	FIFO_2_READ_MSB_ADDR	=	12'hf0+12'd30,
+	parameter	FIFO_3_READ_LSB_ADDR	=	12'h140+12'd28,
+	parameter	FIFO_3_READ_MSB_ADDR	=	12'h140+12'd30,
+	parameter	FIFO_4_READ_LSB_ADDR	=	12'h190+12'd28,
+	parameter	FIFO_4_READ_MSB_ADDR	=	12'h190+12'd30,
+	parameter	FIFO_5_READ_LSB_ADDR	=	12'h1e0+12'd28,
+	parameter	FIFO_5_READ_MSB_ADDR	=	12'h1e0+12'd30,
+	parameter	FIFO_6_READ_LSB_ADDR	=	12'h230+12'd28,
+	parameter	FIFO_6_READ_MSB_ADDR	=	12'h230+12'd30
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	input	SmcVal_i,
+	input	[CMD_REG_WIDTH-1:0]		SmcData_i,
+	input	[ADDR_REG_WIDTH-1:0]	SmcAddr_i,
+
+	output	RequestToFifo_o,
+
+	output	reg	ToRegMapVal_o,
+	output	reg	[CMD_REG_WIDTH-1:0]		ToRegMapData_o,
+	output	reg	[ADDR_REG_WIDTH-1:0]	ToRegMapAddr_o,
+	
+	output	reg	[FIFO_NUM-1:0]	ToFifoVal_o,
+	output	reg	[CMD_REG_WIDTH*2*FIFO_NUM-1:0]	ToFifoData_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire	requestToFifo0	=((SmcAddr_i==FIFO_0_WRITE_LSB_ADDR||SmcAddr_i==FIFO_0_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_0_READ_LSB_ADDR||SmcAddr_i==FIFO_0_READ_MSB_ADDR));
+	wire	requestToFifo1	=((SmcAddr_i==FIFO_1_WRITE_LSB_ADDR||SmcAddr_i==FIFO_1_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_1_READ_LSB_ADDR||SmcAddr_i==FIFO_1_READ_MSB_ADDR));
+	wire	requestToFifo2	=((SmcAddr_i==FIFO_2_WRITE_LSB_ADDR||SmcAddr_i==FIFO_2_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_2_READ_LSB_ADDR||SmcAddr_i==FIFO_2_READ_MSB_ADDR));
+	wire	requestToFifo3	=((SmcAddr_i==FIFO_3_WRITE_LSB_ADDR||SmcAddr_i==FIFO_3_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_3_READ_LSB_ADDR||SmcAddr_i==FIFO_3_READ_MSB_ADDR));
+	wire	requestToFifo4	=((SmcAddr_i==FIFO_4_WRITE_LSB_ADDR||SmcAddr_i==FIFO_4_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_4_READ_LSB_ADDR||SmcAddr_i==FIFO_4_READ_MSB_ADDR));
+	wire	requestToFifo5	=((SmcAddr_i==FIFO_5_WRITE_LSB_ADDR||SmcAddr_i==FIFO_5_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_5_READ_LSB_ADDR||SmcAddr_i==FIFO_5_READ_MSB_ADDR));
+	wire	requestToFifo6	=((SmcAddr_i==FIFO_6_WRITE_LSB_ADDR||SmcAddr_i==FIFO_6_WRITE_MSB_ADDR)|| (SmcAddr_i==FIFO_6_READ_LSB_ADDR||SmcAddr_i==FIFO_6_READ_MSB_ADDR));
+	
+	wire	requestToFifo	=	(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6);
+
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+	assign	RequestToFifo_o	=	requestToFifo;
+
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
+
+//================================================================================
+//	CODING
+//================================================================================
+	always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
+		if	(Rst_i)	begin
+			ToRegMapVal_o	<=	1'b0;
+			ToRegMapData_o	<=	16'h0;
+			ToRegMapAddr_o	<=	12'h0;
+			
+			ToFifoVal_o		<=	7'h0;
+			ToFifoData_o	<=	0;
+		end	else	begin
+			if	(requestToFifo)	begin	
+				case(SmcAddr_i)	
+					FIFO_0_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[0]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*0+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_0_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[0]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*1+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_1_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[1]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*2+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_1_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[1]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*3+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_2_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[2]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*4+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_2_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[2]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*5+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_3_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[3]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*6+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_3_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[3]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*7+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_4_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[4]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*8+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_4_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[4]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*9+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_5_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[5]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*10+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_5_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[5]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*11+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+									
+					FIFO_6_WRITE_LSB_ADDR:	begin
+										ToFifoVal_o[6]	<=	1'b0;
+										ToFifoData_o[CMD_REG_WIDTH*12+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+					FIFO_6_WRITE_MSB_ADDR:	begin
+										ToFifoVal_o[6]	<=	SmcVal_i;
+										ToFifoData_o[CMD_REG_WIDTH*13+:CMD_REG_WIDTH]	<=	SmcData_i;
+									end
+				endcase
+				ToRegMapAddr_o	<=	0;
+				ToRegMapVal_o	<=	0;
+			end	else	begin
+				ToRegMapVal_o	<=	SmcVal_i;
+				ToFifoVal_o		<=	7'h0;
+				ToRegMapData_o	<=	SmcData_i;
+				ToRegMapAddr_o	<=	SmcAddr_i;
+				ToFifoData_o	<=	0;
+			end
+		end
+	end
+endmodule

File diff suppressed because it is too large
+ 528 - 333
sources_1/new/SpiR/SPIm.v


+ 48 - 2
sources_1/new/SpiR/SPIs.v

@@ -1,3 +1,22 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		SPIs
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	This is module implements an Spi Slave protocol.
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 module SPIs (
     input Clk_i,
     input Rst_i,
@@ -13,6 +32,7 @@ module SPIs (
     output reg [23:0] Data_o,
     output reg [7:0] Addr_o,
     output [31:0] DataToRxFifo_o,
+    output reg [191:0] DebugData_o,
     output reg Val_o
 );
 
@@ -23,8 +43,9 @@ module SPIs (
     reg ssReg;
     reg ssRegR;  
     reg [31:0] shiftReg;
-    
-    reg [31:0] shiftRegM; 
+    reg [31:0] shiftRegM;
+
+    reg [255:0] shiftRegDebug; 
  
 
 //===============================================================================
@@ -100,6 +121,31 @@ module SPIs (
         end
     end
 
+    always @(posedge Sck_i or posedge Rst_i) begin 
+        if (Rst_i) begin 
+            shiftRegDebug <= 0;
+        end
+        else begin
+            if (!Ss_i) begin  
+                shiftRegDebug <= {shiftRegDebug[190:0],Mosi0_i};
+                // shiftRegDebug <= {Mosi0_i, shiftRegDebug[191:1]};
+            end
+            else begin
+                shiftRegDebug <= 192'h0;
+            end
+        end
+    end
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            DebugData_o <= 192'h0;
+        end
+        else begin 
+            if (ssReg && !ssRegR) begin 
+                DebugData_o <= shiftRegDebug;
+            end
+        end
+    end
+
     always @(posedge Sck_i) begin 
         if (Rst_i) begin 
             shiftReg<= 32'h0;

+ 58 - 0
sources_1/new/SpiSubSystem/SpiLinesMuxer.v

@@ -0,0 +1,58 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     SpiLinesMuxer
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     This module multiplexing Spi output signals based on an settings.
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////////
+
+module SpiLinesMuxer (
+    input SsR_i,
+    input SsQ_i,
+    input SckR_i,
+    input SckQ_i,
+    input Mosi0R_i,
+    input Mosi0Q_i,
+
+    input ChipSelFpga_i,
+    input ChipSelFlash_i,
+    input Assel_i,
+    input SpiMode_i,
+
+    output Ss_o,
+    output SsFlash_o,
+    output Sck_o,
+    output Mosi0_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+wire ssMuxed;
+wire sckMuxed;
+wire mosi0Muxed;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign sckMuxed = (SpiMode_i) ? SckQ_i : SckR_i;
+assign ssMuxed = (SpiMode_i) ? SsQ_i : SsR_i;
+assign mosi0Muxed = (SpiMode_i) ? Mosi0Q_i : Mosi0R_i;
+
+assign Ss_o = (Assel_i) ? (ChipSelFpga_i ? ssMuxed : 1'b1) : ChipSelFpga_i;
+assign SsFlash_o = (Assel_i) ? (ChipSelFlash_i ? ssMuxed:1'b1) : ChipSelFlash_i;
+assign Sck_o = sckMuxed;
+assign Mosi0_o = mosi0Muxed;
+
+endmodule

+ 227 - 0
sources_1/new/SpiSubSystem/SpiSubSystem.v

@@ -0,0 +1,227 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		SpiSubSystem
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	This is wrapper that encapsulates FIFO's, Spi modules and 
+//					modules that multiplex Spi output lines 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module SpiSubSystem #(
+	parameter STAGES = 3,
+	parameter CMD_REG_WIDTH = 32,
+	parameter ADDR_REG_WIDTH = 12,
+	parameter WIDTH  = 1,
+    parameter FIFO_NUM = 7
+) 
+(
+	input Clk123_i,
+	input SpiClk_i,
+
+	input TxEn_i,
+
+	input FifoRxRst_i,
+	input FifoTxRst_i,
+	input FifoRxRstRdPtr_i,
+	input FifoTxRstWrPtr_i,
+	input SmcAre_i,
+	input SmcAwe_i,
+	input [ADDR_REG_WIDTH-1:0] SmcAddr_i,
+	input ToFifoVal_i,
+	input [CMD_REG_WIDTH-1:0] ToFifoData_i,
+
+	input [1:0] WidthSel_i,
+	input PulsePol_i,
+	input ClockPhase_i,
+	input EndianSel_i,
+	input Lag_i,
+	input Lead_i,
+	input SelSt_i,
+	input [5:0] Stop_i,
+	input Assel_i,
+
+	input ChipSelFpga_i,
+	input ChipSelFlash_i,
+
+	input SpiMode_i,
+	input SpiEn_i,
+
+	output [CMD_REG_WIDTH-1:0] TxFifoCtrlReg_o,
+	output [CMD_REG_WIDTH-1:0] RxFifoCtrlReg_o,
+	output [CMD_REG_WIDTH-1:0] DataFromRxFifo_o,
+
+	output Sck_o,
+	output Ss_o,
+	output SsFlash_o,
+	output Mosi0_o,
+	inout Mosi1_io,
+	output Mosi2_o,
+	output Mosi3_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+wire [CMD_REG_WIDTH-1:0] toSpiData;
+wire emptyFlagTx;
+wire initRst;
+
+wire sckR;
+wire ssR;
+wire mosi0R;
+wire valToTxR;
+wire valToRxR;
+
+wire sckQ;
+wire ssQ;
+wire mosi0Q;
+wire valToTxQ;
+
+wire valToTxFifoRead;
+wire valToRxFifoWrite;
+wire [CMD_REG_WIDTH-1:0] dataToRxFifo;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign valToTxFifoRead  = (SpiMode_i) ? valToTxQ : valToTxR;
+
+assign Mosi1_io = (SpiMode_i) ? mosi1_o : 1'bz;
+
+//================================================================================
+//	CODING
+//================================================================================
+InitRst InitRst_inst
+(
+	.clk_i		(SpiClk_i),
+	.signal_o	(initRst)
+);
+
+Sync1bit #(
+	.WIDTH		(1),
+	.STAGES		(STAGES)
+) Sync1bit_inst 
+(
+	.ClkFast_i	(Clk123_i),
+	.ClkSlow_i	(SpiClk_i),
+	.TxEn_i		(TxEn_i),
+	.TxEn_o		(spiTxEnSync)
+);
+
+DataFifoWrapper #(
+	.CMD_REG_WIDTH		(CMD_REG_WIDTH),
+	.ADDR_REG_WIDTH		(ADDR_REG_WIDTH),
+	.STAGES				(STAGES),
+	.FIFO_NUM			(FIFO_NUM)
+) DataFifoWrapper
+(
+	.WrClk_i			(Clk123_i),
+	.RdClk_i			(SpiClk_i),
+
+	.FifoRxRst_i		(FifoRxRst_i),
+	.FifoTxRst_i		(FifoTxRst_i),
+	.FifoRxRstRdPtr_i	(FifoRxRstRdPtr_i),
+	.FifoTxRstWrPtr_i	(FifoTxRstWrPtr_i),
+
+	.SmcAre_i			(SmcAre_i),
+	.SmcAwe_i			(SmcAwe_i),
+	.SmcAddr_i			(SmcAddr_i),
+	.ToFifoVal_i		(ToFifoVal_i),
+	.ToFifoRxData_i		(dataToRxFifo),
+	.ToFifoRxWriteVal_i	(valToRxR),
+	.ToFifoTxReadVal_i	(valToTxFifoRead),
+	.ToFifoData_i		(ToFifoData_i),
+
+	.TxFifoCtrlReg_o	(TxFifoCtrlReg_o),
+	.RxFifoCtrlReg_o	(RxFifoCtrlReg_o),
+	.EmptyFlagTx_o		(emptyFlagTx),
+	.DataFromRxFifo_o	(DataFromRxFifo_o),
+	.ToSpiData_o		(toSpiData)
+);
+
+SPIm SPIm_inst (
+	.Clk_i			(SpiClk_i),
+	.Start_i		(spiTxEnSync),
+	.Rst_i			(initRst | SpiMode_i | !SpiEn_i),
+	.EmptyFlag_i	(emptyFlagTx),
+	.SpiData_i		(toSpiData),
+	.WidthSel_i		(WidthSel_i),
+	.PulsePol_i		(PulsePol_i),
+	.ClockPhase_i	(ClockPhase_i),
+	.EndianSel_i	(EndianSel_i),
+	.Lag_i			(Lag_i),
+	.Lead_i			(Lead_i),
+	.Stop_i			(Stop_i),
+	.SelSt_i		(SelSt_i),
+	.Sck_o			(sckR),
+	.Ss_o			(ssR),
+	.Mosi0_o		(mosi0R),
+	.Val_o			(valToTxR)
+);
+
+SPIs SPIs_inst (
+	.Clk_i			(SpiClk_i),
+	.Rst_i			(initRst | SpiMode_i),
+	.Sck_i			(sckR),
+	.Ss_i			(ssR),
+	.Mosi0_i		(Mosi1_io),
+	.WidthSel_i		(WidthSel_i),
+	.EndianSel_i	(EndianSel_i),
+	.SelSt_i		(SelSt_i),
+	.DataToRxFifo_o	(dataToRxFifo),
+	.Val_o			(valToRxR)
+);
+
+QuadSPIm QuadSPIm_inst (
+	.Clk_i			(SpiClk_i),
+	.Start_i		(spiTxEnSync),
+	.Rst_i			(initRst | !SpiMode_i | !SpiEn_i),
+	.EmptyFlag_i	(emptyFlagTx),
+	.SpiData_i		(toSpiData),
+	.WidthSel_i		(WidthSel_i),
+	.PulsePol_i		(PulsePol_i),
+	.ClockPhase_i	(ClockPhase_i),
+	.EndianSel_i	(EndianSel_i),
+	.Lag_i			(Lag_i),
+	.Lead_i			(Lead_i),
+	.Stop_i			(Stop_i),
+	.SelSt_i		(SelSt_i),
+	.Sck_o			(sckQ),
+	.Ss_o			(ssQ),
+	.Mosi0_o		(mosi0Q),
+	.Mosi1_o		(mosi1_o),
+	.Mosi2_o		(Mosi2_o),
+	.Mosi3_o		(Mosi3_o),
+	.Val_o			(valToTxQ)
+);
+
+SpiLinesMuxer SpiLinesMuxer (
+	.SsR_i			(ssR),
+	.SsQ_i			(ssQ),
+	.SckR_i			(sckR),
+	.SckQ_i			(sckQ),
+	.Mosi0R_i		(mosi0R),
+	.Mosi0Q_i		(mosi0Q),
+	.ChipSelFpga_i	(ChipSelFpga_i),
+	.ChipSelFlash_i	(ChipSelFlash_i),
+	.Assel_i		(Assel_i),
+	.SpiMode_i		(SpiMode_i),
+	.Ss_o			(Ss_o),
+	.SsFlash_o		(SsFlash_o),
+	.Sck_o			(Sck_o),
+	.Mosi0_o		(Mosi0_o)
+);
+
+endmodule