Добавлен QuadSpi модуль и тестбенч для него. Исправлены назначения пинов. Доработан топ модуль в части добаления линий QuadSpi.

S5444_M/src/constrs/S5443Top.xdc

@@ -17,7 +17,7 @@ set_property PACKAGE_PIN A11 [get_ports Adc2DataDb1P_i]
 set_property PACKAGE_PIN H3 [get_ports ClkP_i]
 set_property IOSTANDARD LVDS_25 [get_ports ClkP_i]
 set_property IOSTANDARD LVDS_25 [get_ports ClkN_i]
-create_clock -period 20.000 [get_ports Clk_i]
+create_clock -period 20.000 [get_ports ClkP_i]
 
 #==========================================================================
 #	ADC1
@@ -154,8 +154,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports StartMeas_i]
 set_property PACKAGE_PIN N9 [get_ports EndMeas_o]
 set_property IOSTANDARD LVCMOS33 [get_ports EndMeas_o]
 
-set_property PACKAGE_PIN R3 [get_ports StartMeasEvent_o]
-set_property IOSTANDARD LVCMOS33 [get_ports StartMeasEvent_o]
+#set_property PACKAGE_PIN R3 [get_ports StartMeasEvent_o]
+#set_property IOSTANDARD LVCMOS25 [get_ports StartMeasEvent_o]
 
 set_property PACKAGE_PIN P7 [get_ports TimersClk_o]
 set_property IOSTANDARD LVCMOS33 [get_ports TimersClk_o]
@@ -187,13 +187,13 @@ set_property PACKAGE_PIN B10 [get_ports {PortSel_o[7]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {PortSel_o[7]}]
 
 set_property PACKAGE_PIN C5 [get_ports DspReadyForRxToFpgaS_o]
-set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRxToFpgaS_o]
+set_property IOSTANDARD LVCMOS25 [get_ports DspReadyForRxToFpgaS_o]
 
 set_property PACKAGE_PIN H14 [get_ports DspReadyForRx_i]
 set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRx_i]
 
-set_property PACKAGE_PIN P7 [get_ports StartMeasDsp_o]
-set_property IOSTANDARD LVCMOS33 [get_ports StartMeasDsp_o]
+set_property PACKAGE_PIN R3 [get_ports StartMeasDsp_o]
+set_property IOSTANDARD LVCMOS25 [get_ports StartMeasDsp_o]
 
 set_property PACKAGE_PIN A6 [get_ports {FastMod_o[0]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {FastMod_o[0]}]

S5444_M/src/src/ExtDspInterface/DspInterface.v

@@ -39,9 +39,13 @@ module	DspInterface
 	input	DspReadyForRx_i,
 	input	[31:0]	MeasNum_i,
 	
-	input	Mosi_i,
+	input	Mosi0_i,
+	input	Mosi1_i,
+	inout	Miso0_Mosi2_io,
+	inout	Miso1_Mosi3_io,
 	input	Sck_i,
 	input	Ss_i,
+	input	SpiRst_i,
 	
 	input	Mode_i,
 	input	[CmdWidth-2:0]		PortSel_i,
@@ -181,36 +185,64 @@ always	@(posedge	Clk_i)	begin
 end
 
 
-SlaveSpi
-#(	
-	.CmdRegWidth	(CmdRegWidth),
-	.DataCntWidth	(DataCntWidth),
-	.HeaderWidth	(HeaderWidth)
-)
-DspSlaveSpi
-(
-	.Clk_i		(Clk_i),
-	.Rst_i		(Rst_i),
+// SlaveSpi
+// #(	
+	// .CmdRegWidth	(CmdRegWidth),
+	// .DataCntWidth	(DataCntWidth),
+	// .HeaderWidth	(HeaderWidth)
+// )
+// DspSlaveSpi
+// (
+	// .Clk_i		(Clk_i),
+	// .Rst_i		(Rst_i),
 
-	.Data_o		(CmdDataReg_o),
-	.Val_o		(CmdDataVal_o),
+	// .Data_o		(CmdDataReg_o),
+	// .Val_o		(CmdDataVal_o),
 	
-	.Mosi_i		(Mosi_i),
-	.Sck_i		(Sck_i),
-	.Ss_i		(Ss_i),
+	// .Mosi_i		(Mosi_i),
+	// .Sck_i		(Sck_i),
+	// .Ss_i		(Ss_i),
 	
-	.Mosi_o		(Mosi_o),
-	.Sck_o		(Sck_o),
-	.Ss0_o		(Ss0_o),
-	.Ss1_o		(Ss1_o),
+	// .Mosi_o		(Mosi_o),
+	// .Sck_o		(Sck_o),
+	// .Ss0_o		(Ss0_o),
+	// .Ss1_o		(Ss1_o),
 	
-	.AnsAddr_o	(AnsAddr_o),
-	.AnsReg_i	(AnsReg_i),
+	// .AnsAddr_o	(AnsAddr_o),
+	// .AnsReg_i	(AnsReg_i),
 	
-	.Miso_i		(Miso_i),
-	.Miso_o		(Miso_o)
+	// .Miso_i		(Miso_i),
+	// .Miso_o		(Miso_o)
+// );
+
+QuadSlaveSpi SlaveSpi
+(
+	.Clk_i				(Clk_i),
+	.Rst_i				(Rst_i),
+
+	.Data_o				(CmdDataReg_o),
+	.Val_o				(CmdDataVal_o),
+	
+	.SpiRst_i			(SpiRst_i),
+	.Mosi0_i			(Mosi0_i),
+	.Mosi1_i			(Mosi1_i),
+	.Miso0_Mosi2_io		(Miso0_Mosi2_io),
+	.Miso1_Mosi3_io		(Miso1_Mosi3_io),
+	.Sck_i				(Sck_i),
+	.Ss_i				(Ss_i),
+
+	.Mosi_o				(Mosi_o),
+	.Sck_o				(Sck_o),
+	.Ss0_o				(Ss0_o),
+	.Ss1_o				(Ss1_o),
+	
+	.AnsAddr_o			(AnsAddr_o),
+	.AnsReg_i			(AnsReg_i),
+	
+	.Miso_o				(Miso_o)
 );
 
+
 MeasDataFifoWrapper		
 #(	
 	.DataWidth	(ResultWidth),

S5444_M/src/src/ExtDspInterface/QuadSlaveSpi.v

@@ -0,0 +1,257 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 17.09.2020 14:18:14
+// Design Name: 
+// Module Name: SlaveSpi
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module	QuadSlaveSpi
+#(	
+	parameter	CmdRegWidth			=	32,
+	parameter	DataCntWidth		=	5,
+	parameter	HeaderWidth			=	7,
+	parameter	CmdDataRegWith		=	24,
+	parameter	Adc0DirAccessAddr	=	7'h13,
+	parameter	Adc1DirAccessAddr	=	7'h14
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	output	reg	[CmdRegWidth-1:0]	Data_o,
+	output	reg	Val_o,
+	
+	input	SpiRst_i,
+	input	Mosi0_i,
+	input	Mosi1_i,
+	inout	Miso0_Mosi2_io,
+	inout	Miso1_Mosi3_io,
+	input	Sck_i,
+	input	Ss_i,
+
+	output	Mosi_o,
+	output	Sck_o,
+	output	Ss0_o,
+	output	Ss1_o,
+	
+	output	[HeaderWidth-1:0]		AnsAddr_o,
+	input	[CmdDataRegWith-1:0]	AnsReg_i,
+	
+	output	Miso_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+	localparam QuadSpiRegWidth = CmdRegWidth/4;
+	
+	reg	[CmdRegWidth-1:0] singleCaptReg;
+	
+	reg [QuadSpiRegWidth-1:0] quadCaptReg0;
+	reg [QuadSpiRegWidth-1:0] quadCaptReg1;
+	reg [QuadSpiRegWidth-1:0] quadCaptReg2;
+	reg [QuadSpiRegWidth-1:0] quadCaptReg3;
+	
+	reg	[DataCntWidth-1:0] dataCnt;
+	reg	[HeaderWidth-1:0] ansAddr;
+	reg	spiMode;
+	wire directTransit	=	(ansAddr	==	Adc0DirAccessAddr)|(ansAddr	==	Adc1DirAccessAddr);
+
+	
+	reg	txWind;
+	reg	[4:0]	txCnt;
+
+	reg	ssReg;
+	reg	ssRegR;
+	reg	ssPos;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+	assign	Mosi_o		=	(!spiMode&directTransit)?	Mosi0_i:1'b1;
+	assign	Sck_o		=	(directTransit)?	Sck_i:1'b0;
+	assign	Ss0_o		=	(ansAddr	==	Adc0DirAccessAddr)?	Ss_i:1'b1;
+	assign	Ss1_o		=	(ansAddr	==	Adc1DirAccessAddr)?	Ss_i:1'b1;
+	
+	assign	AnsAddr_o	=	ansAddr;
+	assign	Miso_o		=	txWind?	AnsReg_i[txCnt]:1'b0;
+//================================================================================
+//	CODING
+//================================================================================
+	
+	always @(posedge Sck_i) begin
+		if (Rst_i) begin
+			singleCaptReg <= 0;
+			quadCaptReg0 <= 0;
+			quadCaptReg1 <= 0;
+			quadCaptReg2 <= 0;
+			quadCaptReg3 <= 0;
+		end else begin
+			if (!Ss_i) begin
+				if (SpiRst_i) begin
+					singleCaptReg <= {singleCaptReg[CmdRegWidth-2:0],Mosi0_i};
+					quadCaptReg0 <= 0;
+					quadCaptReg1 <= 0;
+					quadCaptReg2 <= 0;
+					quadCaptReg3 <= 0;
+				end else begin
+					singleCaptReg <= 0;
+					quadCaptReg0 <= {quadCaptReg0[QuadSpiRegWidth-2:0],Mosi0_i};
+					quadCaptReg1 <= {quadCaptReg1[QuadSpiRegWidth-2:0],Mosi1_i};
+					quadCaptReg2 <= {quadCaptReg2[QuadSpiRegWidth-2:0],Miso0_Mosi2_io};
+					quadCaptReg3 <= {quadCaptReg3[QuadSpiRegWidth-2:0],Miso1_Mosi3_io};
+				end
+			end
+		end 
+	end
+	
+	always @(posedge Sck_i)	begin
+		if	(Rst_i)	begin
+			dataCnt	<=	0;
+		end else begin
+			if	(~Ss_i)	begin
+				dataCnt	<=	dataCnt	+	5'd1;
+			end
+		end
+	end
+
+	always @(posedge Sck_i)	begin
+		if	(Rst_i)	begin
+			spiMode	<=	1'b0;
+		end else begin
+			if	(dataCnt	==	5'd1)	begin
+				if (SpiRst_i) begin
+					if	(singleCaptReg[CmdRegWidth-CmdRegWidth])	begin
+						spiMode	<=	1'b1;
+					end	else	begin
+						spiMode	<=	1'b0;
+					end
+				end else begin
+					if	(quadCaptReg3[QuadSpiRegWidth-QuadSpiRegWidth])	begin
+						spiMode	<=	1'b1;
+					end	else	begin
+						spiMode	<=	1'b0;
+					end
+				end
+			end
+		end
+	end
+
+	always @(negedge Sck_i)	begin
+		if	(Rst_i)	begin
+			ansAddr	<=	7'h7F;	
+		end else begin
+			if	(~Ss_i)	begin
+				if	(dataCnt	==	5'd8)	begin
+					if (SpiRst_i) begin
+						ansAddr	<=	singleCaptReg[QuadSpiRegWidth-1:0];
+					end	else	begin
+						ansAddr	<=	quadCaptReg3[QuadSpiRegWidth-1:0];
+					end 
+				end
+			end	else	begin
+				ansAddr	<=	7'h7F;	
+			end
+		end
+	end
+
+//================================================================================
+//	Generating output signals
+//================================================================================
+
+	always @(posedge Clk_i)	begin
+		ssReg	<=	Ss_i;
+		ssRegR	<=	ssReg;
+	end
+
+	always @(posedge Clk_i)	begin
+		ssPos <= ssReg&!ssRegR;
+	end
+
+	always @(posedge Clk_i)	begin
+		if	(!directTransit&!spiMode)	begin
+			if	(ssReg&!ssRegR)	begin
+				Val_o <= 1'b1;
+			end	else	begin
+				Val_o <= 0;
+			end
+		end
+	end
+
+	always @(posedge Clk_i)	begin
+		if (Rst_i) 	begin
+			Data_o <= 0;
+		end else begin
+			if	(ssReg&!ssRegR)	begin
+				if (SpiRst_i) begin
+					Data_o <= singleCaptReg;
+				end else begin
+					Data_o <= {quadCaptReg3,quadCaptReg2,quadCaptReg1,quadCaptReg0};
+				end
+			end
+		end
+	end
+
+	always	@(*)	begin
+		if	(spiMode	&	!Ss_i)	begin
+			if	(dataCnt	>=5'd8|dataCnt	==	0)	begin
+				txWind	=	1'b1;
+			end	else	begin
+				txWind	=	1'b0;
+			end
+		end	else	begin
+			txWind	=	1'b0;
+		end
+	end
+
+	always	@(negedge	Sck_i)	begin
+		if	(txWind)	begin
+			if	(~Ss_i	&	txWind	&	txCnt!=	0)	begin
+				txCnt	<=	txCnt	-	5'd1;
+			end	else	begin
+				txCnt	<=	5'd24;
+			end
+		end	else	begin
+			txCnt	<=	5'd24;
+		end
+	end
+
+endmodule
+
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S5444_M/src/src/ExtDspInterface/QuadSlaveSpiTb.v

@@ -0,0 +1,293 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 17.09.2020 14:18:14
+// Design Name: 
+// Module Name: SlaveSpi
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module	QuadSlaveSpiTb();
+
+
+
+parameter	CmdRegWidth			=	32;
+parameter	DataCntWidth		=	6;
+parameter	HeaderWidth			=	7;
+parameter	CmdDataRegWith		=	24;
+parameter	Adc0DirAccessAddr	=	7'h13;
+parameter	Adc1DirAccessAddr	=	7'h14;
+
+parameter	[31:0]	MeasCmd =	{8'h11,8'h3e,8'h72,8'h0};
+
+//==========================================================================================
+//clocks gen
+	wire spiRst = 1'b0;
+	
+	reg mosi0;
+	reg mosi1;
+	wire miso0_mosi2;
+	wire miso1_mosi3;
+	
+	reg mosi2;
+	reg mosi3;
+	
+	reg ss;
+
+	reg rst;
+	reg Clk41;
+	reg Clk50;
+	reg	[31:0]	cmdCnt;
+	reg	[31:0]	DspSpiData;
+	
+	always	#10 Clk50	=	~Clk50;
+	always	#(24.390243902439/2)	Clk41	=	~Clk41;
+		
+	reg	[31:0]	tb_cnt;
+	
+	assign miso0_mosi2 = (spiRst)? 1'bz:mosi2;
+	assign miso1_mosi3 = (spiRst)? 1'bz:mosi3;
+	
+//==========================================================================================
+
+initial begin
+	Clk50	=	1'b1;
+	Clk41	=	1'b1;
+	rst = 1'b1;
+#100;
+	rst		=	1'b0;
+end
+
+always	@(negedge	Clk41)	begin
+	if	(!rst)		begin
+		tb_cnt	<=	tb_cnt+1;
+	end	else	begin
+		tb_cnt	<=	0;
+	end
+end
+
+parameter	IDLE	=	3'h0;
+parameter	CMD		=	3'h1;
+parameter	STX		=	3'h2;
+parameter	QTX		=	3'h3;
+parameter	PAUSE	=	3'h4;
+
+reg	[2:0]	txCurrState;
+reg	[2:0]	txNextState;
+
+wire	txWork	=	tb_cnt	>=	23;
+wire	txStop	=	(cmdCnt	>=	251);
+
+
+reg	[6:0]	txCnt;
+reg	[3:0]	pauseCnt;
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	STX || txCurrState	==	QTX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			DspSpiData		<=	MeasCmd;
+		end	else begin
+			DspSpiData	<=	32'hfffffff;
+		end
+	end	else	if	(txCurrState	==	STX||txCurrState	==	QTX)	begin
+		DspSpiData	<=	DspSpiData<<1;
+	end
+end
+
+always	@(posedge Clk41)	begin
+	if	(txCurrState	==	STX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			mosi0	<=	DspSpiData[31];
+		end	else	begin
+			mosi0	<=	1'b1;
+		end
+	end else if (txCurrState == QTX) begin
+		if	(txCnt	>=	7'd0)	begin
+			mosi0	<=	DspSpiData[7];
+			mosi1	<=	DspSpiData[15];
+			mosi2	<=	DspSpiData[23];
+			mosi3	<=	DspSpiData[31];
+		end	else	begin
+			mosi0	<=	1'b1;
+			mosi1	<=	1'b1;
+			mosi2	<=	1'b1;
+			mosi3	<=	1'b1;
+		end
+	end else begin
+		mosi0	<=	1'b1;
+		mosi1	<=	1'b1;
+		mosi2	<=	1'b1;
+		mosi3	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	STX || txCurrState	==	QTX)	begin
+		ss	<=	1'b0;
+	end	else	begin
+		ss	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(rst)	begin
+		txCurrState	<=	IDLE;
+	end	else	begin
+		txCurrState	<=	txNextState;
+	end
+end
+
+
+always @(*) begin
+	txNextState	=	IDLE;
+	case(txCurrState)
+	IDLE	:	begin
+					if (txWork)	begin
+						txNextState = CMD;
+					end else begin
+						txNextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						if (spiRst) begin
+							txNextState = STX;
+						end	else begin
+							txNextState = QTX;
+						end
+					end else begin
+						txNextState = IDLE;
+					end
+				end
+
+	STX		:	begin
+					if (txCnt==6'd31) begin
+						txNextState  = PAUSE;
+					end	else begin
+						txNextState  = STX;
+					end
+				end
+	
+	QTX		:	begin
+					if (txCnt==6'd7) begin
+						txNextState  = PAUSE;
+					end	else begin
+						txNextState  = QTX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd10) begin
+						txNextState  = CMD;
+					end	else begin
+						txNextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+QuadSlaveSpi uut
+(
+	.Clk_i				(Clk50),
+	.Rst_i				(rst),
+
+	.Data_o				(),
+	.Val_o				(),
+	
+	.SpiRst_i			(spiRst),
+	.Mosi0_i			(mosi0),
+	.Mosi1_i			(mosi1),
+	.Miso0_Mosi2_io		(miso0_mosi2),
+	.Miso1_Mosi3_io		(miso1_mosi3),
+	.Sck_i				(Clk41),
+	.Ss_i				(ss),
+
+	.Mosi_o				(),
+	.Sck_o				(),
+	.Ss0_o				(),
+	.Ss1_o				(),
+	
+	.AnsAddr_o			(),
+	.AnsReg_i			(24'h1),
+	
+	.Miso_o				()
+);
+
+
+
+endmodule
+
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S5444_M/src/src/Sim/S5443TopPulseProfileTb.v

@@ -163,20 +163,38 @@ module S5443TopPulseProfileTb;
 	parameter	[31:0]	MuxCtrl3RegCmd	=	{8'h1e,4'h0,GATINGMUXCMD,EXTTRIGMUXCMD,EP2MUXCMD,EP1MUXCMD};
 	parameter	[31:0]	MuxCtrl4RegCmd	=	{8'h1f,4'h0,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD};
 	
+	
+	parameter	[31:0]	DirectAdc1Access	=	{8'h13,24'hA};
+	parameter	[31:0]	DirectAdc2Access	=	{8'h14,24'hA};
+	
 	//=================================================================================================================================================================================================================
 	
+	wire spiRst = 1'b1;
+	// wire spiRst = 1'b0;
+	
 	reg		Clk41;
 	reg		Clk50;
 	reg		Clk70;
 	
 	reg	[31:0]	tb_cnt=4'd0;
 	reg	rst;
-	reg	mosi_i	=	1'b0;
+	
+	reg mosi0;
+	reg mosi1;
+	
+	wire miso0_mosi2;
+	wire miso1_mosi3;
+	
+	reg mosi2;
+	reg mosi3;
+	
+	assign miso0_mosi2 = (spiRst)? 1'bz:mosi2;
+	assign miso1_mosi3 = (spiRst)? 1'bz:mosi3;
+	
 	reg	Miso_i	=	1'b0;
-	reg	ss_i;
+	reg	ss;
 	reg	clk_i	=	1'b0;
 	
-	
 	reg	[31:0]	DspSpiData;
 	reg		startCalcCmdReg;
 						
@@ -201,6 +219,8 @@ module S5443TopPulseProfileTb;
 	assign	trig0R	=	trig0;
     assign	trig1R	=	trig1;
 	
+	
+	
 //==========================================================================================
 //clocks gen
 	always	#10 Clk50	=	~Clk50;
@@ -209,6 +229,7 @@ module S5443TopPulseProfileTb;
 	always	#(24.390243902439/2)	Clk41	=	~Clk41;
 	
 	wire	sck_i;	
+	
 //==========================================================================================
 initial begin
 	Clk50	=	1'b1;
@@ -279,7 +300,8 @@ ncoInst
 
 S5443Top MasterFpga 
 (
-	.Clk_i				(Clk50),
+	.ClkP_i				(Clk50),
+	.ClkN_i				(~Clk50),
 	.Led_o				(),
 //------------------------------------------	
     .Adc1FclkP_i		(),		
@@ -313,11 +335,18 @@ S5443Top MasterFpga
 	.Adc1InitCs_o		(),
 	.Adc2InitCs_o		(),
 	.AdcInitRst_o		(),
+	
+	.DitherCtrlCh1_o	(),
+	.DitherCtrlCh2_o	(),
 //------------------------------------------	
 	
-	.Mosi_i				(mosi_i),
-	.Sck_i				(~sck_i),
-	.Ss_i				(ss_i),
+	.Mosi0_i			(mosi0),
+	.Mosi1_i			(mosi1),
+	.Miso0_Mosi2_io		(miso0_mosi2),
+	.Miso1_Mosi3_io		(miso1_mosi3),
+	.SpiRst_i			(spiRst),
+	.Sck_i				(Clk41),
+	.Ss_i				(ss),
 
 	.LpOutClk_o			(),
 	.LpOutFs_o			(),			
@@ -339,11 +368,12 @@ S5443Top MasterFpga
 	.Overload_o			(),
 	
 	.PortSel_o			(),
-	.PortSelDir_o		(),
+	// .PortSelDir_o		(),
 	
 	//mod out line
 	
-	.Mod_o				(),	
+	.FastMod_o				(),	
+	.StartMeasDsp_o			(),	
 	
 	//gain lines
 	.DspReadyForRx_i		(1'b0),
@@ -353,13 +383,14 @@ S5443Top MasterFpga
 	// .AdcData_i			(Data_i)
 );
 
-parameter	IDLE	=	2'h0;
-parameter	CMD		=	2'h1;
-parameter	TX		=	2'h2;
-parameter	PAUSE	=	2'h3;
+parameter	IDLE	=	3'h0;
+parameter	CMD		=	3'h1;
+parameter	STX		=	3'h2;
+parameter	QTX		=	3'h3;
+parameter	PAUSE	=	3'h4;
 
-reg	[1:0]	txCurrState;
-reg	[1:0]	txNextState;
+reg	[2:0]	txCurrState;
+reg	[2:0]	txNextState;
 
 wire	txWork	=	tb_cnt	>=	23;
 // wire	txStop	=	(cmdCnt	>=	90)	&	(cmdCnt	>=	70)	&	(cmdCnt	>=	71);
@@ -383,7 +414,7 @@ end
 
 always	@(posedge	Clk41)	begin
 	if	(!rst)	begin
-		if	(txCurrState	==	TX)	begin
+		if	(txCurrState	==	STX || txCurrState	==	QTX)	begin
 			txCnt	<=	txCnt+1;
 		end	else	begin
 			txCnt	<=	0;
@@ -409,9 +440,9 @@ end
 always	@(posedge	Clk41)	begin
 	if	(txCurrState	==	CMD)	begin
 		if	(cmdCnt	==	0)	begin
-			DspSpiData		<=	MeasCmd;
+			DspSpiData		<=	DirectAdc1Access;
 		end	else	if	(cmdCnt	==	1)	begin
-			DspSpiData		<=	IfFtwH;
+			DspSpiData		<=	DirectAdc2Access;
 		end	else	if	(cmdCnt	==	2)	begin
 			DspSpiData		<=	IfFtwL;
 		end	else	if	(cmdCnt	==	3)	begin
@@ -553,33 +584,46 @@ always	@(posedge	Clk41)	begin
 		end else	begin
 			DspSpiData	<=	32'hfffffff;
 		end
-	end	else	if	(txCurrState	==	TX)	begin
+	end	else	if	(txCurrState	==	STX||txCurrState	==	QTX)	begin
 		DspSpiData	<=	DspSpiData<<1;
 	end
 end
 
 always	@(posedge Clk41)	begin
-	if	(txCurrState	==	TX)	begin
+	if	(txCurrState	==	STX)	begin
 		if	(txCnt	>=	7'd0)	begin
-			mosi_i	<=	DspSpiData[31];
+			mosi0	<=	DspSpiData[31];
 		end	else	begin
-			mosi_i	<=	1'b1;
+			mosi0	<=	1'b1;
 		end
-	end	else	begin
-		mosi_i	<=	1'b1;
+	end else if (txCurrState == QTX) begin
+		if	(txCnt	>=	7'd0)	begin
+			mosi0	<=	DspSpiData[7];
+			mosi1	<=	DspSpiData[15];
+			mosi2	<=	DspSpiData[23];
+			mosi3	<=	DspSpiData[31];
+		end	else	begin
+			mosi0	<=	1'b1;
+			mosi1	<=	1'b1;
+			mosi2	<=	1'b1;
+			mosi3	<=	1'b1;
+		end
+	end else begin
+		mosi0	<=	1'b1;
+		mosi1	<=	1'b1;
+		mosi2	<=	1'b1;
+		mosi3	<=	1'b1;
 	end
 end
 
 always	@(posedge	Clk41)	begin
-	if	(txCurrState	==	TX)	begin
-		ss_i	<=	1'b0;
+	if	(txCurrState	==	STX || txCurrState	==	QTX)	begin
+		ss	<=	1'b0;
 	end	else	begin
-		ss_i	<=	1'b1;
+		ss	<=	1'b1;
 	end
 end
 
-assign	sck_i	=	Clk41;
-
 always	@(posedge	Clk41)	begin
 	if	(rst)	begin
 		txCurrState	<=	IDLE;
@@ -595,24 +639,36 @@ always @(*) begin
 	IDLE	:	begin
 					if (txWork)	begin
 						txNextState = CMD;
-					end	else begin
+					end else begin
 						txNextState = IDLE;
 					end
 				end
 				
 	CMD	:		begin
 					if (!txStop)	begin
-						txNextState = TX;
-					end	else begin
+						if (spiRst) begin
+							txNextState = STX;
+						end	else begin
+							txNextState = QTX;
+						end
+					end else begin
 						txNextState = IDLE;
 					end
 				end
 
-	TX		:	begin
+	STX		:	begin
 					if (txCnt==6'd31) begin
 						txNextState  = PAUSE;
 					end	else begin
-						txNextState  = TX;
+						txNextState  = STX;
+					end
+				end
+	
+	QTX		:	begin
+					if (txCnt==6'd7) begin
+						txNextState  = PAUSE;
+					end	else begin
+						txNextState  = QTX;
 					end
 				end
         

S5444_M/src/src/Top/S5443Top.v

@@ -175,8 +175,8 @@ module	S5443Top
 	wire	adcInitRst;
 	wire	adcInitMosi;
 	wire	adcInitSck;
-	wire	adc0InitCs;
 	wire	adc1InitCs;
+	wire	adc2InitCs;
 
 	wire	[ResultWidth-1:0]	adc1ImT1;
 	wire	[ResultWidth-1:0]	adc1ReT1;
@@ -542,8 +542,8 @@ module	S5443Top
 	
 	assign	AdcInitMosi_o	=	adcInitMosi;
 	assign	AdcInitClk_o	=	adcInitSck;			
-	assign	Adc1InitCs_o	=	adc0InitCs;
-	assign	Adc2InitCs_o	=	adc1InitCs;
+	assign	Adc1InitCs_o	=	adc1InitCs;
+	assign	Adc2InitCs_o	=	adc2InitCs;
 	assign	AdcInitRst_o	=	adcCtrl[0];
 
 	assign	Led_o	=	ledReg	|(|ampEnNewStates);
@@ -728,9 +728,13 @@ ExternalDspInterface
 	.DspReadyForRx_i	(dspReadyForRxRegRR),
 	.MeasNum_i			({measNum2[7:0],measNum1}),
 	
-	.Mosi_i				(Mosi_i),
+	.Mosi0_i			(Mosi0_i),
+	.Mosi1_i			(Mosi1_i),
+	.Miso0_Mosi2_io		(Miso0_Mosi2_io),
+	.Miso1_Mosi3_io		(Miso1_Mosi3_io),
 	.Sck_i				(Sck_i),
 	.Ss_i				(Ss_i),
+	.SpiRst_i			(SpiRst_i),
 
 	.Mode_i				(measCtrl[0]),
 	.PortSel_i			(measCtrl[23:22]),
@@ -747,10 +751,10 @@ ExternalDspInterface
 	
 	.Mosi_o				(adcInitMosi),
 	.Sck_o				(adcInitSck),
-	.Ss0_o				(adc0InitCs),
-	.Ss1_o				(adc1InitCs),
-	.Miso_i				(Miso_i),
-	.Miso_o				(Miso_o),
+	.Ss0_o				(adc1InitCs),
+	.Ss1_o				(adc2InitCs),
+	.Miso_i				(),
+	.Miso_o				(),
 	
 	.CmdDataReg_o		(cmdDataReg),
 	.CmdDataVal_o		(cmdDataVal),
@@ -805,15 +809,15 @@ InternalDsp
 	.NcoRst_i				(ncoRst),
 	.OscWind_o				(oscWind),
 
-	// .Adc1ChT1Data_i			(adc1ChT1Data),	//T1
-	// .Adc1ChR1Data_i			(adc1ChR1Data),	//R1
-	// .Adc2ChR2Data_i			(adc2ChR2Data),	//R2
-	// .Adc2ChT2Data_i			(adc2ChT2Data),	//T2
+	.Adc1ChT1Data_i			(adc1ChT1Data),	//T1
+	.Adc1ChR1Data_i			(adc1ChR1Data),	//R1
+	.Adc2ChR2Data_i			(adc2ChR2Data),	//R2
+	.Adc2ChT2Data_i			(adc2ChT2Data),	//T2
 
-	.Adc1ChT1Data_i			(AdcData_i),	//T1
-	.Adc1ChR1Data_i			(AdcData_i),	//R1
-	.Adc2ChR2Data_i			(AdcData_i),	//R2
-	.Adc2ChT2Data_i			(AdcData_i),	//T2
+	// .Adc1ChT1Data_i			(AdcData_i),	//T1
+	// .Adc1ChR1Data_i			(AdcData_i),	//R1
+	// .Adc2ChR2Data_i			(AdcData_i),	//R2
+	// .Adc2ChT2Data_i			(AdcData_i),	//T2
 
 	.GatingPulse_i			(gatingPulse),