|
|
@@ -380,7 +380,7 @@ module S5443Top
|
|
|
wire pGenRstDone;
|
|
|
wire [CmdRegWidth-28:0] pgMuxCtrlArray [PGenNum-1:0];
|
|
|
wire [CmdRegWidth-28:0] extTrigMuxCtrlArray [TrigPortsNum-1:0];
|
|
|
- wire [TrigPortsNum-1:0] extTrigDirCmd = measCtrl[21:16];
|
|
|
+ wire [TrigPortsNum-1:0] extTrigDirCmd = measCtrl[23:18];
|
|
|
|
|
|
wire [CmdRegWidth-1:0] pgP1DelArray [PGenNum-1:0];
|
|
|
wire [CmdRegWidth-1:0] pgP2DelArray [PGenNum-1:0];
|
|
|
@@ -578,19 +578,19 @@ module S5443Top
|
|
|
|
|
|
// assign PortSelDir_o = 4'd15;
|
|
|
|
|
|
- assign Trig6to1Dir_o [0] = !measCtrl[16];
|
|
|
- assign Trig6to1Dir_o [1] = !measCtrl[17];
|
|
|
- assign Trig6to1Dir_o [2] = !measCtrl[18];
|
|
|
- assign Trig6to1Dir_o [3] = !measCtrl[19];
|
|
|
- assign Trig6to1Dir_o [4] = !measCtrl[20];
|
|
|
- assign Trig6to1Dir_o [5] = !measCtrl[21];
|
|
|
+ assign Trig6to1Dir_o [0] = !measCtrl[18];
|
|
|
+ assign Trig6to1Dir_o [1] = !measCtrl[19];
|
|
|
+ assign Trig6to1Dir_o [2] = !measCtrl[20];
|
|
|
+ assign Trig6to1Dir_o [3] = !measCtrl[21];
|
|
|
+ assign Trig6to1Dir_o [4] = !measCtrl[22];
|
|
|
+ assign Trig6to1Dir_o [5] = !measCtrl[23];
|
|
|
|
|
|
- assign Trig6to1_io [0] = (measCtrl[16]) ? 1'bz:extPortsMuxedOut[0]; //1 - in, 0 - out
|
|
|
- assign Trig6to1_io [1] = (measCtrl[17]) ? 1'bz:extPortsMuxedOut[1]; //1 - in, 0 - out
|
|
|
- assign Trig6to1_io [2] = (measCtrl[18]) ? 1'bz:extPortsMuxedOut[2]; //1 - in, 0 - out
|
|
|
- assign Trig6to1_io [3] = (measCtrl[19]) ? 1'bz:extPortsMuxedOut[3]; //1 - in, 0 - out
|
|
|
- assign Trig6to1_io [4] = (measCtrl[20]) ? 1'bz:extPortsMuxedOut[4]; //1 - in, 0 - out
|
|
|
- assign Trig6to1_io [5] = (measCtrl[21]) ? 1'bz:extPortsMuxedOut[5]; //1 - in, 0 - out
|
|
|
+ assign Trig6to1_io [0] = (measCtrl[18]) ? 1'bz:extPortsMuxedOut[0]; //1 - in, 0 - out
|
|
|
+ assign Trig6to1_io [1] = (measCtrl[19]) ? 1'bz:extPortsMuxedOut[1]; //1 - in, 0 - out
|
|
|
+ assign Trig6to1_io [2] = (measCtrl[20]) ? 1'bz:extPortsMuxedOut[2]; //1 - in, 0 - out
|
|
|
+ assign Trig6to1_io [3] = (measCtrl[21]) ? 1'bz:extPortsMuxedOut[3]; //1 - in, 0 - out
|
|
|
+ assign Trig6to1_io [4] = (measCtrl[22]) ? 1'bz:extPortsMuxedOut[4]; //1 - in, 0 - out
|
|
|
+ assign Trig6to1_io [5] = (measCtrl[23]) ? 1'bz:extPortsMuxedOut[5]; //1 - in, 0 - out
|
|
|
|
|
|
assign DspReadyForRxToFpgaS_o = dspReadyForRxRegR;
|
|
|
assign StartMeasDsp_o = startMeasSyncR;
|
|
|
@@ -628,15 +628,13 @@ end
|
|
|
//--------------------------------------------------------------------------------
|
|
|
IBUFDS
|
|
|
#(
|
|
|
- .DIFF_TERM("TRUE"),
|
|
|
- .IBUF_LOW_PWR("FALSE"),
|
|
|
- .IOSTANDARD("DEFAULT")
|
|
|
-)
|
|
|
-ClkBuf
|
|
|
-(
|
|
|
- .O (gclk),
|
|
|
- .I (ClkN_i),
|
|
|
- .IB (ClkP_i)
|
|
|
+ .DIFF_TERM ("FALSE")
|
|
|
+)
|
|
|
+Clk50Buf
|
|
|
+(
|
|
|
+ .I (ClkN_i),
|
|
|
+ .IB (ClkP_i),
|
|
|
+ .O (gclk)
|
|
|
);
|
|
|
|
|
|
Clk200Gen ClocksGenerator
|
|
|
@@ -729,9 +727,8 @@ ExternalDspInterface
|
|
|
.Ss_i (Ss_i),
|
|
|
.SpiRst_i (SpiRst_i),
|
|
|
|
|
|
- .Mode_i (measCtrl[0]),
|
|
|
- .PortSel_i (measCtrl[23:22]),
|
|
|
- .DecimFactor_i (measCtrl[3:1]),
|
|
|
+ .PortSel_i (measCtrl[9:6]),
|
|
|
+ .DecimFactor_i (measCtrl[5:2]),
|
|
|
.IfFtwL_i (ifFtw1L),
|
|
|
.IfFtwH_i (ifFtw1H),
|
|
|
|