Поправлены назначения пинов. Актуализирован проект для Slave Fpga.

S5444_M/src/constrs/S5443Top.xdc

@@ -2,8 +2,10 @@ set_property PACKAGE_PIN D2 [get_ports Adc1DataDa0P_i]
 set_property PACKAGE_PIN E2 [get_ports Adc1DataDa1P_i]
 set_property PACKAGE_PIN K1 [get_ports Adc1DataDb0P_i]
 set_property PACKAGE_PIN M1 [get_ports Adc1DataDb1P_i]
-set_property PACKAGE_PIN F15 [get_ports Adc2DataDa0N_i] 
-set_property PACKAGE_PIN D15 [get_ports Adc2DataDa1N_i] 
+set_property PACKAGE_PIN F15 [get_ports Adc2DataDa0P_i] 
+set_property PACKAGE_PIN G15 [get_ports Adc2DataDa0N_i] 
+set_property PACKAGE_PIN D15 [get_ports Adc2DataDa1P_i] 
+set_property PACKAGE_PIN E14 [get_ports Adc2DataDa1N_i] 
 set_property PACKAGE_PIN A13 [get_ports Adc2DataDb0P_i]
 set_property PACKAGE_PIN A11 [get_ports Adc2DataDb1P_i]
 
@@ -15,9 +17,10 @@ set_property PACKAGE_PIN A11 [get_ports Adc2DataDb1P_i]
 
 #==========================================================================
 #	INPUT CLOCKS
-set_property PACKAGE_PIN H3 [get_ports ClkN_i]       
-set_property IOSTANDARD LVDS_25 [get_ports ClkN_i]
+set_property PACKAGE_PIN H3 [get_ports ClkP_i]       
+set_property PACKAGE_PIN H4 [get_ports ClkN_i]       
 set_property IOSTANDARD LVDS_25 [get_ports ClkP_i]
+set_property IOSTANDARD LVDS_25 [get_ports ClkN_i]
 create_clock -period 20.000 [get_ports ClkN_i]
 
 #==========================================================================
@@ -42,7 +45,8 @@ set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1N_i]
 #==========================================================================
 #	ADC2
 
-set_property PACKAGE_PIN B15 [get_ports Adc2FclkN_i]     
+set_property PACKAGE_PIN C15 [get_ports Adc2FclkN_i]     
+set_property PACKAGE_PIN B15 [get_ports Adc2FclkP_i]     
 set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkP_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkN_i]
 
@@ -152,11 +156,14 @@ set_property IOSTANDARD LVCMOS33 [get_ports OverloadS_i]
 set_property PACKAGE_PIN R6 [get_ports StartMeas_i]
 set_property IOSTANDARD LVCMOS33 [get_ports StartMeas_i]
 
+set_property PACKAGE_PIN A10 [get_ports StartMeasDsp_o]
+set_property IOSTANDARD LVCMOS25 [get_ports StartMeasDsp_o]
+
 set_property PACKAGE_PIN N9 [get_ports EndMeas_o]
 set_property IOSTANDARD LVCMOS33 [get_ports EndMeas_o]
 
-#set_property PACKAGE_PIN R3 [get_ports StartMeasEvent_o]
-#set_property IOSTANDARD LVCMOS25 [get_ports StartMeasEvent_o]
+set_property PACKAGE_PIN R3 [get_ports StartMeasEvent_o]
+set_property IOSTANDARD LVCMOS25 [get_ports StartMeasEvent_o]
 
 set_property PACKAGE_PIN P7 [get_ports TimersClk_o]
 set_property IOSTANDARD LVCMOS33 [get_ports TimersClk_o]
@@ -193,9 +200,6 @@ set_property IOSTANDARD LVCMOS25 [get_ports DspReadyForRxToFpgaS_o]
 set_property PACKAGE_PIN H14 [get_ports DspReadyForRx_i]
 set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRx_i]
 
-set_property PACKAGE_PIN R3 [get_ports StartMeasDsp_o]
-set_property IOSTANDARD LVCMOS25 [get_ports StartMeasDsp_o]
-
 set_property PACKAGE_PIN A6 [get_ports {FastMod_o[0]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {FastMod_o[0]}]
 set_property PACKAGE_PIN B5 [get_ports {FastMod_o[1]}]
@@ -242,7 +246,8 @@ set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh1_o]
 set_property PACKAGE_PIN G14 [get_ports DitherCtrlCh2_o]
 set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh2_o]
 
-#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Sck_i_IBUF]
 
 #set_false_path -from [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]]
 

S5444_M/src/src/Sim/S5443TopPulseProfileTb.v

@@ -167,6 +167,9 @@ module S5443TopPulseProfileTb;
 	parameter	[31:0]	DirectAdc1Access	=	{8'h13,24'hA};
 	parameter	[31:0]	DirectAdc2Access	=	{8'h14,24'hA};
 	
+	parameter	[31:0]	PortSelRegCmd	=	{8'h19,8'h0,4'h3,4'h3,4'h3,4'h3};
+	parameter	[31:0]	MuxCtrl6RegCmd	=	{8'h1a,4'h0,5'd17,5'd17,5'd17,5'd17};
+	parameter	[31:0]	MuxCtrl7RegCmd	=	{8'h5a,4'h0,5'd17,5'd17,5'd17,5'd17};
 	//=================================================================================================================================================================================================================
 	
 	wire spiRst = 1'b1;
@@ -197,6 +200,9 @@ module S5443TopPulseProfileTb;
 	
 	reg	[31:0]	DspSpiData;
 	reg		startCalcCmdReg;
+	wire	startCalcSlaveFpga;
+	wire	startMeasS;
+	wire	dspReadySlaveFpga;
 						
 	wire	[17:0]	cos_value;	
 	wire	[17:0]	sin_value;				
@@ -373,16 +379,80 @@ S5443Top MasterFpga
 	//mod out line
 	
 	.FastMod_o				(),	
-	.StartMeasDsp_o			(),	
+	.StartMeasDsp_o			(startCalcSlaveFpga),	
 	
 	//gain lines
 	.DspReadyForRx_i		(1'b0),
-	.DspReadyForRxToFpgaS_o	(),
+	.DspReadyForRxToFpgaS_o	(dspReadySlaveFpga),
 	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
 	.AdcData_i				(sin_value[17-:14])
 	// .AdcData_i			(Data_i)
 );
 
+S5443TopS SlaveFpga 
+(
+	.ClkP_i				(Clk50),
+	.ClkN_i				(~Clk50),
+//------------------------------------------	
+    .Adc1FclkP_i		(),		
+    .Adc1FclkN_i		(),		
+
+    .Adc1DataDa0P_i		(),
+	.Adc1DataDa0N_i		(),		
+    .Adc1DataDa1P_i		(),
+    .Adc1DataDa1N_i		(),
+
+	.Adc1DataDb0P_i		(),
+    .Adc1DataDb0N_i		(),		
+    .Adc1DataDb1P_i		(),
+    .Adc1DataDb1N_i		(),
+//------------------------------------------	
+    .Adc2FclkP_i		(),		
+    .Adc2FclkN_i		(),		
+
+    .Adc2DataDa0P_i		(),
+    .Adc2DataDa0N_i		(),		
+    .Adc2DataDa1P_i		(),
+    .Adc2DataDa1N_i		(),
+  
+	.Adc2DataDb0P_i		(),
+    .Adc2DataDb0N_i		(),		
+    .Adc2DataDb1P_i		(),
+    .Adc2DataDb1N_i		(),
+//------------------------------------------
+	.AdcInitMosi_o		(),
+	.AdcInitClk_o		(),			
+	.Adc1InitCs_o		(),
+	.Adc2InitCs_o		(),
+	.AdcInitRst_o		(),
+	
+	.DitherCtrlCh1_o	(),
+	.DitherCtrlCh2_o	(),
+//------------------------------------------	
+	
+	.Mosi0_i			(mosi0),
+	.Mosi1_i			(mosi1),
+	.Miso0_Mosi2_io		(miso0_mosi2),
+	.Miso1_Mosi3_io		(miso1_mosi3),
+	.SpiRst_i			(spiRst),
+	.Sck_i				(Clk41),
+	.Ss_i				(ss),
+
+	.LpOutClk_o			(),
+	.LpOutFs_o			(),			
+	.LpOutData_o		(),
+	
+	//fpga-dsp signals
+	.StartMeasDsp_i		(startCalcSlaveFpga),
+	.StartMeasEvent_i	(startMeasS),
+	
+	.Overload_o			(),
+
+	//gain lines
+	.DspReadyForRx_i		(dspReadySlaveFpga),
+	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
+	.AdcData_i				(sin_value[17-:14])
+);
 parameter	IDLE	=	3'h0;
 parameter	CMD		=	3'h1;
 parameter	STX		=	3'h2;
@@ -560,7 +630,7 @@ always	@(posedge	Clk41)	begin
 		end	else	if	(cmdCnt	==	59)	begin
 			DspSpiData		<=	PG7P3WidthRegCmd;
 		end	else	if	(cmdCnt	==	60)	begin
-			DspSpiData		<=	DitherCmd;
+			DspSpiData		<=	PortSelRegCmd;
 		end	else	if	(cmdCnt	==	61)	begin
 			DspSpiData		<=	MeasNum0RegCmd;
 		end else	if	(cmdCnt	==	62)	begin
@@ -578,9 +648,9 @@ always	@(posedge	Clk41)	begin
 		end	else	if	(cmdCnt	==	68)	begin
 			DspSpiData		<=	AdcCtrl;
 		end	else	if	(cmdCnt	==	99)	begin
-			DspSpiData		<=	{8'h58,24'd100};
+			DspSpiData		<=	MuxCtrl6RegCmd;
 		end	else	if	(cmdCnt	==	100)	begin
-			DspSpiData		<=	MeasCmdFft;
+			DspSpiData		<=	MuxCtrl7RegCmd;
 		end else	begin
 			DspSpiData	<=	32'hfffffff;
 		end

S5444_M/src/src/Top/S5443Top.v

@@ -425,7 +425,7 @@ module	S5443Top
 	assign	fastModCtrl [ChNum-3] = muxCtrl5[9:5]; 
 	assign	fastModCtrl [ChNum-4] = muxCtrl5[4:0];
 	
-	assign	slowModCtrl [ChNum-1] = muxCtrl6[18:15]; 
+	assign	slowModCtrl [ChNum-1] = muxCtrl6[19:15]; 
 	assign	slowModCtrl [ChNum-2] = muxCtrl6[14:10]; 
 	assign	slowModCtrl [ChNum-3] = muxCtrl6[9:5]; 
 	assign	slowModCtrl [ChNum-4] = muxCtrl6[4:0];
@@ -626,13 +626,6 @@ end
 //--------------------------------------------------------------------------------
 //	Data Receiving Interface
 //--------------------------------------------------------------------------------
-
-// IBUF iob_50m_in
-// (
-	// .I    			(Clk_i),
-	// .O         		(gclk)
-// );
-	
 IBUFDS 
 #(
 	.DIFF_TERM("TRUE"),       
@@ -642,8 +635,8 @@ IBUFDS
 ClkBuf 
 (
 	.O	(gclk),  
-	.I	(~ClkP_i),  
-	.IB	(~ClkN_i) 
+	.I	(ClkN_i),  
+	.IB	(ClkP_i) 
 );
    
 Clk200Gen	ClocksGenerator 
@@ -685,13 +678,13 @@ AdcDataInterface
 	.Adc1DataDb1P_i	(Adc1DataDb1P_i),
 	.Adc1DataDb1N_i	(Adc1DataDb1N_i),
 	
-	.Adc2FclkP_i	(~Adc2FclkP_i),		
-	.Adc2FclkN_i	(~Adc2FclkN_i),	
+	.Adc2FclkP_i	(Adc2FclkN_i),		
+	.Adc2FclkN_i	(Adc2FclkP_i),	
 	
-	.Adc2DataDa0P_i	(~Adc2DataDa0P_i),
-	.Adc2DataDa0N_i	(~Adc2DataDa0N_i),
-	.Adc2DataDa1P_i	(~Adc2DataDa1P_i),
-	.Adc2DataDa1N_i	(~Adc2DataDa1N_i),
+	.Adc2DataDa0P_i	(Adc2DataDa0N_i),
+	.Adc2DataDa0N_i	(Adc2DataDa0P_i),
+	.Adc2DataDa1P_i	(Adc2DataDa1N_i),
+	.Adc2DataDa1N_i	(Adc2DataDa1P_i),
 	
 	.Adc2DataDb0P_i	(Adc2DataDb0P_i),	
 	.Adc2DataDb0N_i	(Adc2DataDb0N_i),

S5444_S/src/constrs/S5443Top.xdc

@@ -4,162 +4,178 @@
 
 #==========================================================================
 #	INPUT CLOCKS
-set_property PACKAGE_PIN C15 [get_ports Clk_i]
-set_property IOSTANDARD LVCMOS25 [get_ports Clk_i]
-create_clock -period 20.000 [get_ports Clk_i]
+set_property PACKAGE_PIN B13 [get_ports ClkP_i]       
+set_property PACKAGE_PIN B14 [get_ports ClkN_i]       
+set_property IOSTANDARD LVDS_25 [get_ports ClkP_i]
+set_property IOSTANDARD LVDS_25 [get_ports ClkN_i]
+create_clock -period 20.000 [get_ports ClkN_i]
 
 #==========================================================================
 #	ADC1
 
 set_property PACKAGE_PIN H1 [get_ports Adc1FclkP_i]
+set_property PACKAGE_PIN G1 [get_ports Adc1FclkN_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc1FclkP_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc1FclkN_i]
 
-set_property PACKAGE_PIN C1 [get_ports Adc1DataDa0P_i]
+set_property PACKAGE_PIN D2 [get_ports Adc1DataDa0P_i]
+set_property PACKAGE_PIN D1 [get_ports Adc1DataDa0N_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa0P_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa0N_i]
 
-set_property PACKAGE_PIN D2 [get_ports Adc1DataDa1P_i]
+set_property PACKAGE_PIN E2 [get_ports Adc1DataDa1P_i]
+set_property PACKAGE_PIN E1 [get_ports Adc1DataDa1N_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa1P_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDa1N_i]
 
-set_property PACKAGE_PIN E2 [get_ports Adc1DataDb0P_i]
+set_property PACKAGE_PIN K1 [get_ports Adc1DataDb0P_i]
+set_property PACKAGE_PIN J1 [get_ports Adc1DataDb0N_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb0P_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb0N_i]
 
-set_property PACKAGE_PIN F2 [get_ports Adc1DataDb1P_i]
+set_property PACKAGE_PIN M1 [get_ports Adc1DataDb1P_i]
+set_property PACKAGE_PIN L1 [get_ports Adc1DataDb1N_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1P_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1N_i]
 
 #==========================================================================
 #	ADC2
 
-set_property PACKAGE_PIN A11 [get_ports Adc2FclkP_i]
+set_property PACKAGE_PIN B15 [get_ports Adc2FclkP_i]
+set_property PACKAGE_PIN C15 [get_ports Adc2FclkN_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkP_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkN_i]
 
-set_property PACKAGE_PIN B9 [get_ports Adc2DataDa0P_i]
+set_property PACKAGE_PIN F15 [get_ports Adc2DataDa0P_i]
+set_property PACKAGE_PIN G15 [get_ports Adc2DataDa0N_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa0P_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa0N_i]
 
-set_property PACKAGE_PIN A8 [get_ports Adc2DataDa1P_i]
+set_property PACKAGE_PIN D15 [get_ports Adc2DataDa1P_i]
+set_property PACKAGE_PIN E14 [get_ports Adc2DataDa1N_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa1P_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDa1N_i]
 
-set_property PACKAGE_PIN B6 [get_ports Adc2DataDb0P_i]
+set_property PACKAGE_PIN A13 [get_ports Adc2DataDb0P_i]
+set_property PACKAGE_PIN A14 [get_ports Adc2DataDb0N_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb0P_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb0N_i]
 
-set_property PACKAGE_PIN A5 [get_ports Adc2DataDb1P_i]
+set_property PACKAGE_PIN A11 [get_ports Adc2DataDb1P_i]
+set_property PACKAGE_PIN A12 [get_ports Adc2DataDb1N_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb1P_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2DataDb1N_i]
 
 #==========================================================================
 # DSP interface
 
-set_property PACKAGE_PIN H14 [get_ports Miso_o]
-set_property IOSTANDARD LVCMOS33 [get_ports Miso_o]
+set_property PACKAGE_PIN K15 [get_ports Mosi0_i]
+set_property IOSTANDARD LVCMOS33 [get_ports Mosi0_i]
+set_property PACKAGE_PIN M14 [get_ports Mosi1_i]
+set_property IOSTANDARD LVCMOS33 [get_ports Mosi1_i]
 
-set_property PACKAGE_PIN H15 [get_ports Mosi_i]
-set_property IOSTANDARD LVCMOS33 [get_ports Mosi_i]
+set_property PACKAGE_PIN J15 [get_ports Miso0_Mosi2_io]
+set_property IOSTANDARD LVCMOS33 [get_ports Miso0_Mosi2_io]
+set_property PACKAGE_PIN M15 [get_ports Miso1_Mosi3_io]
+set_property IOSTANDARD LVCMOS33 [get_ports Miso1_Mosi3_io]
 
-set_property PACKAGE_PIN J12 [get_ports Ss_i]
+set_property PACKAGE_PIN L14 [get_ports Ss_i]
 set_property IOSTANDARD LVCMOS33 [get_ports Ss_i]
 
-set_property PACKAGE_PIN M9 [get_ports Sck_i]
+set_property PACKAGE_PIN N15 [get_ports SpiRst_i]
+set_property IOSTANDARD LVCMOS33 [get_ports SpiRst_i]
+
+set_property PACKAGE_PIN L15 [get_ports Sck_i]
 set_property IOSTANDARD LVCMOS33 [get_ports Sck_i]
 create_clock -period 16.000 [get_ports Sck_i]
 
-set_property PACKAGE_PIN P14 [get_ports LpOutClk_o]
+set_property PACKAGE_PIN R13 [get_ports LpOutClk_o]
 set_property IOSTANDARD LVCMOS33 [get_ports LpOutClk_o]
 
-set_property PACKAGE_PIN R14 [get_ports LpOutFs_o]
+set_property PACKAGE_PIN N14 [get_ports LpOutFs_o]
 set_property IOSTANDARD LVCMOS33 [get_ports LpOutFs_o]
 
-set_property PACKAGE_PIN R5 [get_ports {LpOutData_o[0]}]
+set_property PACKAGE_PIN P15 [get_ports {LpOutData_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[0]}]
-set_property PACKAGE_PIN P6 [get_ports {LpOutData_o[1]}]
+set_property PACKAGE_PIN P14 [get_ports {LpOutData_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[1]}]
-set_property PACKAGE_PIN R6 [get_ports {LpOutData_o[2]}]
+set_property PACKAGE_PIN R14 [get_ports {LpOutData_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[2]}]
-set_property PACKAGE_PIN P7 [get_ports {LpOutData_o[3]}]
+set_property PACKAGE_PIN P12 [get_ports {LpOutData_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[3]}]
-set_property PACKAGE_PIN R7 [get_ports {LpOutData_o[4]}]
+set_property PACKAGE_PIN R12 [get_ports {LpOutData_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[4]}]
-set_property PACKAGE_PIN R8 [get_ports {LpOutData_o[5]}]
+set_property PACKAGE_PIN P11 [get_ports {LpOutData_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[5]}]
-set_property PACKAGE_PIN N9 [get_ports {LpOutData_o[6]}]
+set_property PACKAGE_PIN R11 [get_ports {LpOutData_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[6]}]
-set_property PACKAGE_PIN R9 [get_ports {LpOutData_o[7]}]
+set_property PACKAGE_PIN P10 [get_ports {LpOutData_o[7]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[7]}]
-set_property PACKAGE_PIN P10 [get_ports {LpOutData_o[8]}]
+set_property PACKAGE_PIN R10 [get_ports {LpOutData_o[8]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[8]}]
-set_property PACKAGE_PIN R10 [get_ports {LpOutData_o[9]}]
+set_property PACKAGE_PIN R8 [get_ports {LpOutData_o[9]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[9]}]
-set_property PACKAGE_PIN P11 [get_ports {LpOutData_o[10]}]
+set_property PACKAGE_PIN R9 [get_ports {LpOutData_o[10]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[10]}]
-set_property PACKAGE_PIN R11 [get_ports {LpOutData_o[11]}]
+set_property PACKAGE_PIN P7 [get_ports {LpOutData_o[11]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[11]}]
-set_property PACKAGE_PIN P12 [get_ports {LpOutData_o[12]}]
+set_property PACKAGE_PIN R7 [get_ports {LpOutData_o[12]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[12]}]
-set_property PACKAGE_PIN R12 [get_ports {LpOutData_o[13]}]
+set_property PACKAGE_PIN P6 [get_ports {LpOutData_o[13]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[13]}]
-set_property PACKAGE_PIN R13 [get_ports {LpOutData_o[14]}]
+set_property PACKAGE_PIN R6 [get_ports {LpOutData_o[14]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[14]}]
-set_property PACKAGE_PIN N13 [get_ports {LpOutData_o[15]}]
+set_property PACKAGE_PIN R5 [get_ports {LpOutData_o[15]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {LpOutData_o[15]}]
 
 #==========================================================================
 #  ADC SPI
 
-set_property PACKAGE_PIN F14 [get_ports AdcInitMosi_o]
+set_property PACKAGE_PIN M2 [get_ports AdcInitMosi_o]
 set_property IOSTANDARD LVCMOS25 [get_ports AdcInitMosi_o]
-set_property PACKAGE_PIN E15 [get_ports AdcInitClk_o]
+set_property PACKAGE_PIN N1 [get_ports AdcInitClk_o]
 set_property IOSTANDARD LVCMOS25 [get_ports AdcInitClk_o]
-set_property PACKAGE_PIN F15 [get_ports Adc2InitCs_o]
+set_property PACKAGE_PIN P2 [get_ports Adc2InitCs_o]
 set_property IOSTANDARD LVCMOS25 [get_ports Adc2InitCs_o]
-set_property PACKAGE_PIN E14 [get_ports Adc1InitCs_o]
+set_property PACKAGE_PIN N2 [get_ports Adc1InitCs_o]
 set_property IOSTANDARD LVCMOS25 [get_ports Adc1InitCs_o]
-set_property PACKAGE_PIN D15 [get_ports AdcInitRst_o]
+set_property PACKAGE_PIN P1 [get_ports AdcInitRst_o]
 set_property IOSTANDARD LVCMOS25 [get_ports AdcInitRst_o]
 
 #==========================================================================
 #  OTHER
 
-set_property PACKAGE_PIN M14 [get_ports Overload_o]
+set_property PACKAGE_PIN N13 [get_ports Overload_o]
 set_property IOSTANDARD LVCMOS33 [get_ports Overload_o]
 
-set_property PACKAGE_PIN M15 [get_ports StartMeasEvent_i]
-set_property IOSTANDARD LVCMOS33 [get_ports StartMeasEvent_i]
+set_property PACKAGE_PIN R3 [get_ports StartMeasEvent_i]
+set_property IOSTANDARD LVCMOS25 [get_ports StartMeasEvent_i]
 
 #set_property PACKAGE_PIN M8 [get_ports EndMeas_o]
 #set_property IOSTANDARD LVCMOS33 [get_ports EndMeas_o]
 
-set_property PACKAGE_PIN A14 [get_ports {AmpEn_o[0]}]
+set_property PACKAGE_PIN A6 [get_ports {AmpEn_o[0]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[0]}]
-set_property PACKAGE_PIN A13 [get_ports {AmpEn_o[1]}]
+set_property PACKAGE_PIN B6 [get_ports {AmpEn_o[1]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[1]}]
-set_property PACKAGE_PIN B14 [get_ports {AmpEn_o[2]}]
+set_property PACKAGE_PIN A8 [get_ports {AmpEn_o[2]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[2]}]
-set_property PACKAGE_PIN B15 [get_ports {AmpEn_o[3]}]
+set_property PACKAGE_PIN A7 [get_ports {AmpEn_o[3]}]
 set_property IOSTANDARD LVCMOS25 [get_ports {AmpEn_o[3]}]
 
-set_property PACKAGE_PIN N15 [get_ports DspReadyForRx_i]
-set_property IOSTANDARD LVCMOS33 [get_ports DspReadyForRx_i]
-
-set_property PACKAGE_PIN L15 [get_ports StartMeasDsp_i]
-set_property IOSTANDARD LVCMOS33 [get_ports StartMeasDsp_i]
+set_property PACKAGE_PIN A4 [get_ports DspReadyForRx_i]
+set_property IOSTANDARD LVCMOS25 [get_ports DspReadyForRx_i]
 
-##set_property PACKAGE_PIN E14	[get_ports Mod_o];
-##set_property IOSTANDARD LVCMOS25 [get_ports Mod_o];
+set_property PACKAGE_PIN B2 [get_ports StartMeasDsp_i]
+set_property IOSTANDARD LVCMOS25 [get_ports StartMeasDsp_i]
 
 set_property PACKAGE_PIN R2 [get_ports DitherCtrlCh1_o]
 set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh1_o]
 
-set_property PACKAGE_PIN P2 [get_ports DitherCtrlCh2_o]
+set_property PACKAGE_PIN A5 [get_ports DitherCtrlCh2_o]
 set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh2_o]
 
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Sck_i_IBUF]
 
 
 

S5444_S/src/src/ClkGen/Clk200Gen.v

@@ -24,7 +24,7 @@ PLLE2_ADV #(
       	.CLKOUT1_DIVIDE		(120),
       	.CLKOUT1_DUTY_CYCLE	(0.5),
       	.CLKOUT1_PHASE		(0.0),
-      	.CLKOUT2_DIVIDE		(6),
+      	.CLKOUT2_DIVIDE		(12),
       	.CLKOUT2_DUTY_CYCLE	(0.5),
       	.CLKOUT2_PHASE		(0.0),
       	.CLKOUT3_DIVIDE		(120),
@@ -43,7 +43,7 @@ CommonPll (
       	.CLKFBOUT		(ClkFb),
       	.CLKOUT0		(rx_mmcmout_200),
       	.CLKOUT1		(rx_mmcmout_10),
-      	.CLKOUT2		(rx_mmcmout_150),
+      	.CLKOUT2		(rx_mmcmout_100),
       	.CLKOUT3		(),
       	.CLKOUT4		(),
       	.CLKOUT5		(),
@@ -68,7 +68,7 @@ BUFG	bufg_mmcm_Fb (.I(ClkFb), .O(rxFb)) ;
 
 BUFG	ctrlClk200 (.I(rx_mmcmout_200), .O(Clk200_o)) ;
 BUFG	ctrlClk10 (.I(rx_mmcmout_10), .O(Clk10Timers_o)) ;
-BUFG	ctrlClk150 (.I(rx_mmcmout_150), .O(Clk150_o)) ;
+BUFG	ctrlClk100 (.I(rx_mmcmout_100), .O(Clk150_o)) ;
 
 endmodule
 

S5444_S/src/src/DitherGen/DitherGenv2.v

@@ -71,7 +71,7 @@ module DitherGenv2
 	
 	wire	[3:0]	ncoSignalT2R2	=	ncoArray[currStateT2R2[FrAmpWordWidth-1-:4]];
 	wire	[3:0]	ncoSignalT1R1	=	ncoArray[currStateT1R1[FrAmpWordWidth-1-:4]];
-	
+
 	wire	dithGenT2R2	=	((ncoSignalT2R2>>ditherAmpT2R2)>sawCnt)	?	1'b1:1'b0;
 	wire	dithGenT1R1	=	((ncoSignalT1R1>>ditherAmpT1R1)>sawCnt)	?	1'b1:1'b0;
 //================================================================================

S5444_S/src/src/ExtDspInterface/DspInterface.v

@@ -39,9 +39,13 @@ module	DspInterface
 	input	DspReadyForRx_i,
 	input	[31:0]	MeasNum_i,
 	
-	input	Mosi_i,
+	input	Mosi0_i,
+	input	Mosi1_i,
+	inout	Miso0_Mosi2_io,
+	inout	Miso1_Mosi3_io,
 	input	Sck_i,
 	input	Ss_i,
+	input	SpiRst_i,
 	
 	input	Mode_i,
 	input	[CmdWidth-2:0]		PortSel_i,
@@ -181,36 +185,64 @@ always	@(posedge	Clk_i)	begin
 end
 
 
-SlaveSpi
-#(	
-	.CmdRegWidth	(CmdRegWidth),
-	.DataCntWidth	(DataCntWidth),
-	.HeaderWidth	(HeaderWidth)
-)
-DspSlaveSpi
-(
-	.Clk_i		(Clk_i),
-	.Rst_i		(Rst_i),
+// SlaveSpi
+// #(	
+	// .CmdRegWidth	(CmdRegWidth),
+	// .DataCntWidth	(DataCntWidth),
+	// .HeaderWidth	(HeaderWidth)
+// )
+// DspSlaveSpi
+// (
+	// .Clk_i		(Clk_i),
+	// .Rst_i		(Rst_i),
 
-	.Data_o		(CmdDataReg_o),
-	.Val_o		(CmdDataVal_o),
+	// .Data_o		(CmdDataReg_o),
+	// .Val_o		(CmdDataVal_o),
 	
-	.Mosi_i		(Mosi_i),
-	.Sck_i		(Sck_i),
-	.Ss_i		(Ss_i),
+	// .Mosi_i		(Mosi_i),
+	// .Sck_i		(Sck_i),
+	// .Ss_i		(Ss_i),
 	
-	.Mosi_o		(Mosi_o),
-	.Sck_o		(Sck_o),
-	.Ss0_o		(Ss0_o),
-	.Ss1_o		(Ss1_o),
+	// .Mosi_o		(Mosi_o),
+	// .Sck_o		(Sck_o),
+	// .Ss0_o		(Ss0_o),
+	// .Ss1_o		(Ss1_o),
 	
-	.AnsAddr_o	(AnsAddr_o),
-	.AnsReg_i	(AnsReg_i),
+	// .AnsAddr_o	(AnsAddr_o),
+	// .AnsReg_i	(AnsReg_i),
 	
-	.Miso_i		(Miso_i),
-	.Miso_o		(Miso_o)
+	// .Miso_i		(Miso_i),
+	// .Miso_o		(Miso_o)
+// );
+
+QuadSlaveSpi SlaveSpi
+(
+	.Clk_i				(Clk_i),
+	.Rst_i				(Rst_i),
+
+	.Data_o				(CmdDataReg_o),
+	.Val_o				(CmdDataVal_o),
+	
+	.SpiRst_i			(SpiRst_i),
+	.Mosi0_i			(Mosi0_i),
+	.Mosi1_i			(Mosi1_i),
+	.Miso0_Mosi2_io		(Miso0_Mosi2_io),
+	.Miso1_Mosi3_io		(Miso1_Mosi3_io),
+	.Sck_i				(Sck_i),
+	.Ss_i				(Ss_i),
+
+	.Mosi_o				(Mosi_o),
+	.Sck_o				(Sck_o),
+	.Ss0_o				(Ss0_o),
+	.Ss1_o				(Ss1_o),
+	
+	.AnsAddr_o			(AnsAddr_o),
+	.AnsReg_i			(AnsReg_i),
+	
+	.Miso_o				(Miso_o)
 );
 
+
 MeasDataFifoWrapper		
 #(	
 	.DataWidth	(ResultWidth),
@@ -223,6 +255,7 @@ MeasDataFifoInst
 	.PpiBusy_i		(ppiBusy),	
 	.MeasNum_i		(MeasNum_i),	
 	.StartMeasDsp_i	(StartMeasDsp_i),	
+	.DspReadyForRx_i(DspReadyForRx_i),	
 	.MeasDataBus_i	(measDataBus),
 	.MeasDataVal_i	(LpOutStart_i),	
 	

S5444_S/src/src/ExtDspInterface/DspPpiOut.v

@@ -141,20 +141,35 @@ end
 //================================================================================
 //  INSTANTIATIONS
 //================================================================================		
-ODDR2
-#(
-	.DDR_ALIGNMENT("NONE"),
-	.INIT	(1'b0),
-	.SRTYPE	("SYNC")
-) clk_i10OutInst (
-	.Q		(LpOutClk_o),
-	.C0		(Clk_i),
-	.C1		(~Clk_i),
-	.CE		(1'b1),
-	.D0		(1'b1),
-	.D1		(1'b0),
-	.R		(1'b0),
-	.S		(1'b0)
-);		
+// ODDR2
+// #(
+	// .DDR_ALIGNMENT("NONE"),
+	// .INIT	(1'b0),
+	// .SRTYPE	("SYNC")
+// ) clk_i10OutInst (
+	// .Q		(LpOutClk_o),
+	// .C0		(Clk_i),
+	// .C1		(~Clk_i),
+	// .CE		(1'b1),
+	// .D0		(1'b1),
+	// .D1		(1'b0),
+	// .R		(1'b0),
+	// .S		(1'b0)
+// );		
 
+ODDR 
+#(
+	.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
+	.INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
+	.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
+) ODDR_inst (
+	.Q(LpOutClk_o),   // 1-bit DDR output
+	.C(Clk_i),   // 1-bit clock input
+	.CE(1'b1), // 1-bit clock enable input
+	.D1(1'b1), // 1-bit data input (positive edge)
+	.D2(1'b0), // 1-bit data input (negative edge)
+	.R(1'b0),   // 1-bit reset
+	.S(1'b0)    // 1-bit set
+);
+   
 endmodule

S5444_S/src/src/ExtDspInterface/QuadSlaveSpi.v

@@ -0,0 +1,257 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 17.09.2020 14:18:14
+// Design Name: 
+// Module Name: SlaveSpi
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module	QuadSlaveSpi
+#(	
+	parameter	CmdRegWidth			=	32,
+	parameter	DataCntWidth		=	5,
+	parameter	HeaderWidth			=	7,
+	parameter	CmdDataRegWith		=	24,
+	parameter	Adc0DirAccessAddr	=	7'h13,
+	parameter	Adc1DirAccessAddr	=	7'h14
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	output	reg	[CmdRegWidth-1:0]	Data_o,
+	output	reg	Val_o,
+	
+	input	SpiRst_i,
+	input	Mosi0_i,
+	input	Mosi1_i,
+	inout	Miso0_Mosi2_io,
+	inout	Miso1_Mosi3_io,
+	input	Sck_i,
+	input	Ss_i,
+
+	output	Mosi_o,
+	output	Sck_o,
+	output	Ss0_o,
+	output	Ss1_o,
+	
+	output	[HeaderWidth-1:0]		AnsAddr_o,
+	input	[CmdDataRegWith-1:0]	AnsReg_i,
+	
+	output	Miso_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+	localparam QuadSpiRegWidth = CmdRegWidth/4;
+	
+	reg	[CmdRegWidth-1:0] singleCaptReg;
+	
+	reg [QuadSpiRegWidth-1:0] quadCaptReg0;
+	reg [QuadSpiRegWidth-1:0] quadCaptReg1;
+	reg [QuadSpiRegWidth-1:0] quadCaptReg2;
+	reg [QuadSpiRegWidth-1:0] quadCaptReg3;
+	
+	reg	[DataCntWidth-1:0] dataCnt;
+	reg	[HeaderWidth-1:0] ansAddr;
+	reg	spiMode;
+	wire directTransit	=	(ansAddr	==	Adc0DirAccessAddr)|(ansAddr	==	Adc1DirAccessAddr);
+
+	
+	reg	txWind;
+	reg	[4:0]	txCnt;
+
+	reg	ssReg;
+	reg	ssRegR;
+	reg	ssPos;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+	assign	Mosi_o		=	(!spiMode&directTransit)?	Mosi0_i:1'b1;
+	assign	Sck_o		=	(directTransit)?	Sck_i:1'b0;
+	assign	Ss0_o		=	(ansAddr	==	Adc0DirAccessAddr)?	Ss_i:1'b1;
+	assign	Ss1_o		=	(ansAddr	==	Adc1DirAccessAddr)?	Ss_i:1'b1;
+	
+	assign	AnsAddr_o	=	ansAddr;
+	assign	Miso_o		=	txWind?	AnsReg_i[txCnt]:1'b0;
+//================================================================================
+//	CODING
+//================================================================================
+	
+	always @(posedge Sck_i) begin
+		if (Rst_i) begin
+			singleCaptReg <= 0;
+			quadCaptReg0 <= 0;
+			quadCaptReg1 <= 0;
+			quadCaptReg2 <= 0;
+			quadCaptReg3 <= 0;
+		end else begin
+			if (!Ss_i) begin
+				if (SpiRst_i) begin
+					singleCaptReg <= {singleCaptReg[CmdRegWidth-2:0],Mosi0_i};
+					quadCaptReg0 <= 0;
+					quadCaptReg1 <= 0;
+					quadCaptReg2 <= 0;
+					quadCaptReg3 <= 0;
+				end else begin
+					singleCaptReg <= 0;
+					quadCaptReg0 <= {quadCaptReg0[QuadSpiRegWidth-2:0],Mosi0_i};
+					quadCaptReg1 <= {quadCaptReg1[QuadSpiRegWidth-2:0],Mosi1_i};
+					quadCaptReg2 <= {quadCaptReg2[QuadSpiRegWidth-2:0],Miso0_Mosi2_io};
+					quadCaptReg3 <= {quadCaptReg3[QuadSpiRegWidth-2:0],Miso1_Mosi3_io};
+				end
+			end
+		end 
+	end
+	
+	always @(posedge Sck_i)	begin
+		if	(Rst_i)	begin
+			dataCnt	<=	0;
+		end else begin
+			if	(~Ss_i)	begin
+				dataCnt	<=	dataCnt	+	5'd1;
+			end
+		end
+	end
+
+	always @(posedge Sck_i)	begin
+		if	(Rst_i)	begin
+			spiMode	<=	1'b0;
+		end else begin
+			if	(dataCnt	==	5'd1)	begin
+				if (SpiRst_i) begin
+					if	(singleCaptReg[CmdRegWidth-CmdRegWidth])	begin
+						spiMode	<=	1'b1;
+					end	else	begin
+						spiMode	<=	1'b0;
+					end
+				end else begin
+					if	(quadCaptReg3[QuadSpiRegWidth-QuadSpiRegWidth])	begin
+						spiMode	<=	1'b1;
+					end	else	begin
+						spiMode	<=	1'b0;
+					end
+				end
+			end
+		end
+	end
+
+	always @(negedge Sck_i)	begin
+		if	(Rst_i)	begin
+			ansAddr	<=	7'h7F;	
+		end else begin
+			if	(~Ss_i)	begin
+				if	(dataCnt	==	5'd8)	begin
+					if (SpiRst_i) begin
+						ansAddr	<=	singleCaptReg[QuadSpiRegWidth-1:0];
+					end	else	begin
+						ansAddr	<=	quadCaptReg3[QuadSpiRegWidth-1:0];
+					end 
+				end
+			end	else	begin
+				ansAddr	<=	7'h7F;	
+			end
+		end
+	end
+
+//================================================================================
+//	Generating output signals
+//================================================================================
+
+	always @(posedge Clk_i)	begin
+		ssReg	<=	Ss_i;
+		ssRegR	<=	ssReg;
+	end
+
+	always @(posedge Clk_i)	begin
+		ssPos <= ssReg&!ssRegR;
+	end
+
+	always @(posedge Clk_i)	begin
+		if	(!directTransit&!spiMode)	begin
+			if	(ssReg&!ssRegR)	begin
+				Val_o <= 1'b1;
+			end	else	begin
+				Val_o <= 0;
+			end
+		end
+	end
+
+	always @(posedge Clk_i)	begin
+		if (Rst_i) 	begin
+			Data_o <= 0;
+		end else begin
+			if	(ssReg&!ssRegR)	begin
+				if (SpiRst_i) begin
+					Data_o <= singleCaptReg;
+				end else begin
+					Data_o <= {quadCaptReg3,quadCaptReg2,quadCaptReg1,quadCaptReg0};
+				end
+			end
+		end
+	end
+
+	always	@(*)	begin
+		if	(spiMode	&	!Ss_i)	begin
+			if	(dataCnt	>=5'd8|dataCnt	==	0)	begin
+				txWind	=	1'b1;
+			end	else	begin
+				txWind	=	1'b0;
+			end
+		end	else	begin
+			txWind	=	1'b0;
+		end
+	end
+
+	always	@(negedge	Sck_i)	begin
+		if	(txWind)	begin
+			if	(~Ss_i	&	txWind	&	txCnt!=	0)	begin
+				txCnt	<=	txCnt	-	5'd1;
+			end	else	begin
+				txCnt	<=	5'd24;
+			end
+		end	else	begin
+			txCnt	<=	5'd24;
+		end
+	end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5444_S/src/src/ExtDspInterface/QuadSlaveSpiTb.v

@@ -0,0 +1,293 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 17.09.2020 14:18:14
+// Design Name: 
+// Module Name: SlaveSpi
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module	QuadSlaveSpiTb();
+
+
+
+parameter	CmdRegWidth			=	32;
+parameter	DataCntWidth		=	6;
+parameter	HeaderWidth			=	7;
+parameter	CmdDataRegWith		=	24;
+parameter	Adc0DirAccessAddr	=	7'h13;
+parameter	Adc1DirAccessAddr	=	7'h14;
+
+parameter	[31:0]	MeasCmd =	{8'h11,8'h3e,8'h72,8'h0};
+
+//==========================================================================================
+//clocks gen
+	wire spiRst = 1'b0;
+	
+	reg mosi0;
+	reg mosi1;
+	wire miso0_mosi2;
+	wire miso1_mosi3;
+	
+	reg mosi2;
+	reg mosi3;
+	
+	reg ss;
+
+	reg rst;
+	reg Clk41;
+	reg Clk50;
+	reg	[31:0]	cmdCnt;
+	reg	[31:0]	DspSpiData;
+	
+	always	#10 Clk50	=	~Clk50;
+	always	#(24.390243902439/2)	Clk41	=	~Clk41;
+		
+	reg	[31:0]	tb_cnt;
+	
+	assign miso0_mosi2 = (spiRst)? 1'bz:mosi2;
+	assign miso1_mosi3 = (spiRst)? 1'bz:mosi3;
+	
+//==========================================================================================
+
+initial begin
+	Clk50	=	1'b1;
+	Clk41	=	1'b1;
+	rst = 1'b1;
+#100;
+	rst		=	1'b0;
+end
+
+always	@(negedge	Clk41)	begin
+	if	(!rst)		begin
+		tb_cnt	<=	tb_cnt+1;
+	end	else	begin
+		tb_cnt	<=	0;
+	end
+end
+
+parameter	IDLE	=	3'h0;
+parameter	CMD		=	3'h1;
+parameter	STX		=	3'h2;
+parameter	QTX		=	3'h3;
+parameter	PAUSE	=	3'h4;
+
+reg	[2:0]	txCurrState;
+reg	[2:0]	txNextState;
+
+wire	txWork	=	tb_cnt	>=	23;
+wire	txStop	=	(cmdCnt	>=	251);
+
+
+reg	[6:0]	txCnt;
+reg	[3:0]	pauseCnt;
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	STX || txCurrState	==	QTX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			DspSpiData		<=	MeasCmd;
+		end	else begin
+			DspSpiData	<=	32'hfffffff;
+		end
+	end	else	if	(txCurrState	==	STX||txCurrState	==	QTX)	begin
+		DspSpiData	<=	DspSpiData<<1;
+	end
+end
+
+always	@(posedge Clk41)	begin
+	if	(txCurrState	==	STX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			mosi0	<=	DspSpiData[31];
+		end	else	begin
+			mosi0	<=	1'b1;
+		end
+	end else if (txCurrState == QTX) begin
+		if	(txCnt	>=	7'd0)	begin
+			mosi0	<=	DspSpiData[7];
+			mosi1	<=	DspSpiData[15];
+			mosi2	<=	DspSpiData[23];
+			mosi3	<=	DspSpiData[31];
+		end	else	begin
+			mosi0	<=	1'b1;
+			mosi1	<=	1'b1;
+			mosi2	<=	1'b1;
+			mosi3	<=	1'b1;
+		end
+	end else begin
+		mosi0	<=	1'b1;
+		mosi1	<=	1'b1;
+		mosi2	<=	1'b1;
+		mosi3	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	STX || txCurrState	==	QTX)	begin
+		ss	<=	1'b0;
+	end	else	begin
+		ss	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(rst)	begin
+		txCurrState	<=	IDLE;
+	end	else	begin
+		txCurrState	<=	txNextState;
+	end
+end
+
+
+always @(*) begin
+	txNextState	=	IDLE;
+	case(txCurrState)
+	IDLE	:	begin
+					if (txWork)	begin
+						txNextState = CMD;
+					end else begin
+						txNextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						if (spiRst) begin
+							txNextState = STX;
+						end	else begin
+							txNextState = QTX;
+						end
+					end else begin
+						txNextState = IDLE;
+					end
+				end
+
+	STX		:	begin
+					if (txCnt==6'd31) begin
+						txNextState  = PAUSE;
+					end	else begin
+						txNextState  = STX;
+					end
+				end
+	
+	QTX		:	begin
+					if (txCnt==6'd7) begin
+						txNextState  = PAUSE;
+					end	else begin
+						txNextState  = QTX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd10) begin
+						txNextState  = CMD;
+					end	else begin
+						txNextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+QuadSlaveSpi uut
+(
+	.Clk_i				(Clk50),
+	.Rst_i				(rst),
+
+	.Data_o				(),
+	.Val_o				(),
+	
+	.SpiRst_i			(spiRst),
+	.Mosi0_i			(mosi0),
+	.Mosi1_i			(mosi1),
+	.Miso0_Mosi2_io		(miso0_mosi2),
+	.Miso1_Mosi3_io		(miso1_mosi3),
+	.Sck_i				(Clk41),
+	.Ss_i				(ss),
+
+	.Mosi_o				(),
+	.Sck_o				(),
+	.Ss0_o				(),
+	.Ss1_o				(),
+	
+	.AnsAddr_o			(),
+	.AnsReg_i			(24'h1),
+	
+	.Miso_o				()
+);
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

S5444_S/src/src/InternalDsp/InternalDsp.v

@@ -318,7 +318,7 @@ CordicNco
 	.IterNum	(13),
 	.EnSinN		(0)
 )
-ncoInstFirstTone
+ncoFirstTone
 (
 	.Clk_i		(Clk_i),
 	.Rst_i		(Rst_i|NcoRst_i),
@@ -339,7 +339,7 @@ CordicNco
 	.IterNum	(13),
 	.EnSinN		(0)
 )
-ncoInstSecondTone
+ncoSecondTone
 (
 	.Clk_i		(Clk_i),
 	.Rst_i		(Rst_i|NcoRst_i),

S5444_S/src/src/PulseMeas/MeasStartEventGen.v

@@ -1,4 +1,5 @@
 `timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)	
 //////////////////////////////////////////////////////////////////////////////////
 // Company: 
 // Engineer: 
@@ -44,6 +45,7 @@ module	MeasStartEventGen
 //  LOCALPARAM
 
 //================================================================================
+	reg		startMeasEventVal;
 	reg		startMeasEvent;
 	reg		initTrig;
 	
@@ -59,30 +61,46 @@ module	MeasStartEventGen
 
 	always	@(posedge	Clk_i)	begin
 		if	(!Rst_i)	begin
-			measTrigReg	<=	MeasTrig_i;
+			measTrigReg	 <=	MeasTrig_i;
 		end	else	begin
-			measTrigReg	=	0;
+			measTrigReg	 <=	0;
 		end
 	end
 	
-	always	@(posedge	Clk_i)	begin
+	always	@(posedge Clk_i)	begin
 		if	(!Rst_i)	begin
 			if	(StartMeasDsp_i)	begin
 				if	(measTrigPos)	begin
-					startMeasEvent	<=	1'b1;
+					startMeasEventVal	<=	1'b1;
+				end 
+			end	else	begin
+				startMeasEventVal	<=	0;
+			end
+		end	else	begin
+			startMeasEventVal	<=	0;
+		end
+	end
+	
+	always	@(*)	begin
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(startMeasEventVal)	begin
+					startMeasEvent	=	measTrigReg;
+				end else begin
+					startMeasEvent	=	0;
 				end
 			end	else	begin
-				startMeasEvent	<=	0;
+				startMeasEvent	=	0;
 			end
 		end	else	begin
-			startMeasEvent	<=	0;
+			startMeasEvent	=	0;
 		end
 	end
 	
 	always	@(*)	begin
 		if	(!Rst_i)	begin
 			if	(StartMeasDsp_i)	begin
-				if	(measTrigPos)	begin
+				if	(MeasTrig_i)	begin
 					initTrig	=	1'b1;
 				end	else	begin
 					initTrig	=	1'b0;
@@ -94,7 +112,6 @@ module	MeasStartEventGen
 			initTrig	=	0;
 		end
 	end
-
 endmodule
 
 

S5444_S/src/src/PulseMeas/Mux.v

@@ -35,6 +35,8 @@ module	Mux
 	input	IntTrig2_i,
 	input	[PGenNum-1:0]		PulseBus_i,
 	input	[TrigPortsNum-1:0]	ExtPortsBus_i,
+	input	SlowMod_i,
+	input	FastMod_i,
 	
 	output	MuxOut_o
 );	
@@ -45,7 +47,7 @@ module	Mux
 //================================================================================
 //	REG/WIRE
 	reg		muxOut;
-	wire	[PGenNum+TrigPortsNum+5:0]	inputBus	=	{IntTrig2_i,1'b1,1'b0,DspStartCmd_i,DspTrigOut_i,IntTrig_i,ExtPortsBus_i,PulseBus_i};
+	wire	[PGenNum+TrigPortsNum+7:0]	inputBus	=	{FastMod_i,SlowMod_i,IntTrig2_i,1'b1,1'b0,DspStartCmd_i,DspTrigOut_i,IntTrig_i,ExtPortsBus_i,PulseBus_i};
 //================================================================================
 //  ASSIGNMENTS
 	assign	MuxOut_o	=	muxOut;

S5444_S/src/src/RegMap/RegMap.v

@@ -59,8 +59,7 @@ module	RegMap
 	output	[CmdDataRegWith-1:0]	IfFtw2RegH_o,
 	output	[CmdDataRegWith-1:0]	FilterCorrCoefRegL_o,
 	output	[CmdDataRegWith-1:0]	FilterCorrCoefRegH_o,
-	output	[CmdDataRegWith-1:0]	DspTrigInReg_o,		
-	output	[CmdDataRegWith-1:0]	DspTrigOutReg_o,
+	output	[CmdDataRegWith-1:0]	ActivePortSel_o,		
 	output	[CmdDataRegWith-1:0]	DspTrigIn1Reg_o,		
 	output	[CmdDataRegWith-1:0]	DspTrigIn2Reg_o,
 	output	[CmdDataRegWith-1:0]	DspTrigOut1Reg_o,		
@@ -144,7 +143,9 @@ module	RegMap
 	output	[CmdDataRegWith-1:0]	MuxCtrl1Reg_o,
 	output	[CmdDataRegWith-1:0]	MuxCtrl2Reg_o,
 	output	[CmdDataRegWith-1:0]	MuxCtrl3Reg_o,
-	output	[CmdDataRegWith-1:0]	MuxCtrl4Reg_o
+	output	[CmdDataRegWith-1:0]	MuxCtrl4Reg_o,
+	output	[CmdDataRegWith-1:0]	MuxCtrl5Reg_o,
+	output	[CmdDataRegWith-1:0]	MuxCtrl6Reg_o
 );
 //================================================================================
 //	LOCALPARAMS
@@ -167,12 +168,11 @@ module	RegMap
 	localparam	AdcDirectRd1RegAddr		=	7'h14;
 	localparam	IfFtw1RegHAddr			=	7'h15;
 	localparam	IfFtw1RegLAddr			=	7'h16;
-	localparam	IfFtw2RegHAddr			=	7'h19;
-	localparam	IfFtw2RegLAddr			=	7'h1a;
+	localparam	IfFtw2RegHAddr			=	7'hc;
+	localparam	IfFtw2RegLAddr			=	7'hd;
 	localparam	FilterCorrCoefHAddr		=	7'h17;
 	localparam	FilterCorrCoefLAddr		=	7'h18;
-	localparam	DspTrigInAddr			=	7'h19;	
-	localparam	DspTrigOutAddr			=	7'h1a;	
+	localparam	ActivePortSelAddr		=	7'h19;	
 	localparam	DspTrigIn1Addr			=	7'h5a;	
 	localparam	DspTrigIn2Addr			=	7'h5b;	
 	localparam	DspTrigOut1Addr			=	7'h5c;	
@@ -259,6 +259,8 @@ module	RegMap
 	localparam	MuxCtrl2RegAddr			=	7'h1d;
 	localparam	MuxCtrl3RegAddr			=	7'h1e;
 	localparam	MuxCtrl4RegAddr			=	7'h1f;
+	localparam	MuxCtrl5RegAddr			=	7'h1a;	
+	localparam	MuxCtrl6RegAddr			=	7'h5a;
 
 //================================================================================
 //	REG/WIRE
@@ -286,12 +288,12 @@ module	RegMap
 	reg	[CmdDataRegWith-1:0]	ifFtw2RegH;
 	reg	[CmdDataRegWith-1:0]	filterCorrCoefRegL;
 	reg	[CmdDataRegWith-1:0]	filterCorrCoefRegH;
-	reg	[CmdDataRegWith-1:0]	dspTrigInReg;
-	reg	[CmdDataRegWith-1:0]	dspTrigOutReg;
+	reg	[CmdDataRegWith-1:0]	activePortSelReg;
 	reg	[CmdDataRegWith-1:0]	dspTrigIn1Reg;
 	reg	[CmdDataRegWith-1:0]	dspTrigIn2Reg;
 	reg	[CmdDataRegWith-1:0]	dspTrigOut1Reg;
 	reg	[CmdDataRegWith-1:0]	dspTrigOut2Reg;
+	
 	//pulse meas regs
 	reg	[CmdDataRegWith-1:0]	pGMode0Reg;
 	reg	[CmdDataRegWith-1:0]	pGMode1Reg;
@@ -301,6 +303,8 @@ module	RegMap
 	reg	[CmdDataRegWith-1:0]	muxCtrl2Reg;
 	reg	[CmdDataRegWith-1:0]	muxCtrl3Reg;
 	reg	[CmdDataRegWith-1:0]	muxCtrl4Reg;
+	reg	[CmdDataRegWith-1:0]	muxCtrl5Reg;
+	reg	[CmdDataRegWith-1:0]	muxCtrl6Reg;
 	
 	//PG1 Regs
 	reg	[CmdDataRegWith-1:0]	pG1P1DelayReg;
@@ -398,8 +402,7 @@ module	RegMap
 	assign	IfFtw2RegH_o			=	ifFtw2RegH;
 	assign	FilterCorrCoefRegL_o	=	filterCorrCoefRegL;
 	assign	FilterCorrCoefRegH_o	=	filterCorrCoefRegH;	
-	assign	DspTrigInReg_o			=	dspTrigInReg;		
-	assign	DspTrigOutReg_o			=	dspTrigOutReg;
+	assign	ActivePortSel_o			=	activePortSelReg;		
 	assign	DspTrigIn1Reg_o			=	dspTrigIn1Reg;		
 	assign	DspTrigIn2Reg_o			=	dspTrigIn2Reg;
 	assign	DspTrigOut1Reg_o		=	dspTrigOut1Reg;		
@@ -485,6 +488,8 @@ module	RegMap
 	assign	MuxCtrl2Reg_o		=	muxCtrl2Reg;
 	assign	MuxCtrl3Reg_o		=	muxCtrl3Reg;
 	assign	MuxCtrl4Reg_o		=	muxCtrl4Reg;
+	assign	MuxCtrl5Reg_o		=	muxCtrl5Reg;
+	assign	MuxCtrl6Reg_o		=	muxCtrl6Reg;
 	
 	assign	AnsDataReg_o		=	ansReg;
 //================================================================================
@@ -548,17 +553,15 @@ module	RegMap
 					IfFtw2RegHAddr:			begin
 												ifFtw2RegH	<=	Data_i	[CmdDataRegWith-1:0];
 											end
+											
 					FilterCorrCoefLAddr:	begin
 												filterCorrCoefRegL	<=	Data_i	[CmdDataRegWith-1:0];
 											end
 					FilterCorrCoefHAddr:	begin
 												filterCorrCoefRegH	<=	Data_i	[CmdDataRegWith-1:0];
 											end
-					DspTrigInAddr:			begin
-												dspTrigInReg	<=	Data_i	[CmdDataRegWith-1:0];
-											end
-					DspTrigOutAddr:			begin
-												dspTrigOutReg	<=	Data_i	[CmdDataRegWith-1:0];
+					ActivePortSelAddr:		begin
+												activePortSelReg	<=	Data_i	[CmdDataRegWith-1:0];
 											end
 					PG1P1DelayRegAddr:		begin
 												pG1P1DelayReg	<=	Data_i	[CmdDataRegWith-1:0];
@@ -752,6 +755,12 @@ module	RegMap
 					MuxCtrl4RegAddr:		begin
 												muxCtrl4Reg	<=	Data_i	[CmdDataRegWith-1:0];
 											end
+					MuxCtrl5RegAddr:		begin
+												muxCtrl5Reg	<=	Data_i	[CmdDataRegWith-1:0];
+											end
+					MuxCtrl6RegAddr:		begin
+												muxCtrl6Reg	<=	Data_i	[CmdDataRegWith-1:0];
+											end
 					DspTrigIn1Addr:			begin
 												dspTrigIn1Reg	<=	Data_i	[CmdDataRegWith-1:0];
 											end
@@ -783,10 +792,11 @@ module	RegMap
 			adcDirectRd1Reg		<=	{CmdDataRegWith{1'b0}};
 			ifFtw1RegL			<=	{CmdDataRegWith{1'b0}};
 			ifFtw1RegH			<=	{CmdDataRegWith{1'b0}};
+			ifFtw2RegL			<=	{CmdDataRegWith{1'b0}};
+			ifFtw2RegH			<=	{CmdDataRegWith{1'b0}};
 			filterCorrCoefRegL	<=	{CmdDataRegWith{1'b0}};
 			filterCorrCoefRegH	<=	{CmdDataRegWith{1'b0}};
-			dspTrigInReg		<=	{CmdDataRegWith{1'b0}};
-			dspTrigOutReg		<=	{CmdDataRegWith{1'b0}};
+			activePortSelReg	<=	{CmdDataRegWith{1'b0}};
 			dspTrigIn1Reg		<=	{CmdDataRegWith{1'b0}};
 			dspTrigIn2Reg		<=	{CmdDataRegWith{1'b0}};
 			dspTrigOut1Reg		<=	{CmdDataRegWith{1'b0}};
@@ -862,7 +872,9 @@ module	RegMap
 			muxCtrl1Reg			<=	{CmdDataRegWith{1'b0}};	
 			muxCtrl2Reg			<=	{CmdDataRegWith{1'b0}};	
 			muxCtrl3Reg			<=	{CmdDataRegWith{1'b0}};	
-			muxCtrl4Reg			<=	{CmdDataRegWith{1'b0}};	
+			muxCtrl4Reg			<=	{CmdDataRegWith{1'b0}};
+			muxCtrl6Reg			<=	{CmdDataRegWith{1'b0}};
+			muxCtrl5Reg			<=	{CmdDataRegWith{1'b0}};			
 		end
 	end
 	
@@ -968,11 +980,11 @@ module	RegMap
 					FilterCorrCoefHAddr:	begin
 												ansReg	=	filterCorrCoefRegH;
 											end
-					DspTrigInAddr:			begin
-												ansReg	=	dspTrigInReg;
+					ActivePortSelAddr:		begin
+												ansReg	=	activePortSelReg;
 											end
-					DspTrigOutAddr:			begin
-												ansReg	=	dspTrigOutReg;
+					MuxCtrl5RegAddr:		begin
+												ansReg	=	muxCtrl5Reg;
 											end
 					DspTrigIn1Addr:			begin
 												ansReg	=	dspTrigIn1Reg;

S5444_S/src/src/Top/S5443Top.v

@@ -53,7 +53,8 @@ module	S5443Top
 )
 (
 	//common ports
-	input	Clk_i,
+	input	ClkP_i,
+	input	ClkN_i,
 	
 	//fpga-adc1 data interface
     input	Adc1FclkP_i,
@@ -95,11 +96,13 @@ module	S5443Top
 	output	DitherCtrlCh2_o,
 	
 	//fpga-dsp cmd interface
-	input	Mosi_i,
+	input	Mosi0_i,
+	input	Mosi1_i,
+	inout	Miso0_Mosi2_io,
+	inout	Miso1_Mosi3_io,
+	input	SpiRst_i,
 	input	Sck_i,
 	input	Ss_i,
-	// input	Miso_i,
-	output	Miso_o,
 	
 	//fpga-dsp data interface
 	output	LpOutClk_o,
@@ -130,8 +133,6 @@ module	S5443Top
 	
 	reg		startMeasSync;
 	wire	intTrig1;
-	reg		startMeasEventReg;
-	wire	startMeasEventPos	=	(!startMeasEventReg&StartMeasEvent_i);
 	
 	wire	intTrig;
 	wire	trigForIntTrig2;
@@ -196,14 +197,13 @@ module	S5443Top
 	wire	[CmdDataRegWith-1:0]	adcCtrl;
 	wire	[CmdDataRegWith-1:0]	adcDirectRd0;
 	wire	[CmdDataRegWith-1:0]	adcDirectRd1;
-	wire	[CmdDataRegWith-1:0]	ifF1twL;
-	wire	[CmdDataRegWith-1:0]	ifF1twH;
-	wire	[CmdDataRegWith-1:0]	ifF2twL;
-	wire	[CmdDataRegWith-1:0]	ifF2twH;
+	wire	[CmdDataRegWith-1:0]	ifFtw1L;
+	wire	[CmdDataRegWith-1:0]	ifFtw1H;	
+	wire	[CmdDataRegWith-1:0]	ifFtw2L;
+	wire	[CmdDataRegWith-1:0]	ifFtw2H;
 	wire	[CmdDataRegWith-1:0]	measCtrl;
 	wire	[CmdDataRegWith-1:0]	amplitudeMod;
-	wire	[CmdDataRegWith-1:0]	dspTrigIn;
-	wire	[CmdDataRegWith-1:0]	dspTrigOut;
+	wire	[CmdDataRegWith-1:0]	activePortSel;
 	wire	[CmdDataRegWith-1:0]	dspTrigIn1;
 	wire	[CmdDataRegWith-1:0]	dspTrigIn2;
 	wire	[CmdDataRegWith-1:0]	dspTrigOut1;
@@ -337,6 +337,8 @@ module	S5443Top
 	wire	[CmdDataRegWith-1:0]	muxCtrl2;
 	wire	[CmdDataRegWith-1:0]	muxCtrl3;
 	wire	[CmdDataRegWith-1:0]	muxCtrl4;
+	wire	[CmdDataRegWith-1:0]	muxCtrl5;
+	wire	[CmdDataRegWith-1:0]	muxCtrl6;
 
 	wire	[CmdRegWidth-29:0]	pgModeArray		[PGenNum-1:0];
 	wire	pgPulsePolArray		[PGenNum-1:0];
@@ -534,12 +536,19 @@ end
 //	Data Receiving Interface
 //--------------------------------------------------------------------------------
 
-IBUF iob_50m_in
+IBUFDS 
+#(
+	.DIFF_TERM("TRUE"),       
+	.IBUF_LOW_PWR("FALSE"),     
+	.IOSTANDARD("DEFAULT")    
+) 
+ClkBuf 
 (
-	.I    			(Clk_i),
-	.O         		(gclk)
+	.O	(gclk),  
+	.I	(ClkP_i),  
+	.IB	(ClkN_i) 
 );
-	
+
 Clk200Gen	ClocksGenerator 
 (
     .Clk_i			(gclk),
@@ -565,7 +574,9 @@ AdcDataInterface
 	.Rst_i			(initRst),
 	
 	.Adc1FclkP_i	(Adc1FclkP_i),		
-	.Adc1FclkN_i	(Adc1FclkN_i),	
+	.Adc1FclkN_i	(Adc1FclkN_i),
+	
+	.testAdc		(AdcData_i),		
 	
 	.Adc1DataDa0P_i	(Adc1DataDa0P_i),
 	.Adc1DataDa0N_i	(Adc1DataDa0N_i),
@@ -577,13 +588,13 @@ AdcDataInterface
 	.Adc1DataDb1P_i	(Adc1DataDb1P_i),
 	.Adc1DataDb1N_i	(Adc1DataDb1N_i),
 	
-	.Adc2FclkP_i	(Adc2FclkP_i),		
-	.Adc2FclkN_i	(Adc2FclkN_i),	
+	.Adc2FclkP_i	(Adc2FclkN_i),		
+	.Adc2FclkN_i	(Adc2FclkP_i),	
 	
-	.Adc2DataDa0P_i	(Adc2DataDa0P_i),
-	.Adc2DataDa0N_i	(Adc2DataDa0N_i),
-	.Adc2DataDa1P_i	(Adc2DataDa1P_i),
-	.Adc2DataDa1N_i	(Adc2DataDa1N_i),
+	.Adc2DataDa0P_i	(Adc2DataDa0N_i),
+	.Adc2DataDa0N_i	(Adc2DataDa0P_i),
+	.Adc2DataDa1P_i	(Adc2DataDa1N_i),
+	.Adc2DataDa1N_i	(Adc2DataDa1P_i),
 	
 	.Adc2DataDb0P_i	(Adc2DataDb0P_i),	
 	.Adc2DataDb0N_i	(Adc2DataDb0N_i),
@@ -595,7 +606,7 @@ AdcDataInterface
 	
 	.Adc2ChR2Data_o	(adc2ChR2Data),
 	.Adc2ChT2Data_o	(adc2ChT2Data)
-);  
+);   
  
 //--------------------------------------------------------------------------------
 //	External DSP Interface
@@ -620,29 +631,33 @@ ExternalDspInterface
 	.DspReadyForRx_i	(dspReadyForRxReg),
 	.MeasNum_i			({measNum2[7:0],measNum1}),
 	
-	.Mosi_i				(Mosi_i),
+	.Mosi0_i			(Mosi0_i),
+	.Mosi1_i			(Mosi1_i),
+	.Miso0_Mosi2_io		(Miso0_Mosi2_io),
+	.Miso1_Mosi3_io		(Miso1_Mosi3_io),
 	.Sck_i				(Sck_i),
 	.Ss_i				(Ss_i),
+	.SpiRst_i			(SpiRst_i),
 
 	.Mode_i				(measCtrl[0]),
 	.PortSel_i			(measCtrl[23:22]),
 	.DecimFactor_i		(measCtrl[3:1]),
-	.IfFtwL_i			(ifF1twL),
-	.IfFtwH_i			(ifF1twH),
+	.IfFtwL_i			(ifFtw1L),
+	.IfFtwH_i			(ifFtw1H),
 	
 	.OscDataRdFlag_o	(oscDataRdFlag),
 	
 	.Adc1ChT1Data_i		(adc1ChT1Data),	
 	.Adc1ChR1Data_i		(adc1ChR1Data),	
-	.Adc2ChR2Data_i		(adc2ChT2Data),	
-	.Adc2ChT2Data_i		(adc2ChR2Data),	
+	.Adc2ChR2Data_i		(adc2ChR2Data),	
+	.Adc2ChT2Data_i		(adc2ChT2Data),		
 	
 	.Mosi_o				(adcInitMosi),
 	.Sck_o				(adcInitSck),
-	.Ss0_o				(adc0InitCs),
-	.Ss1_o				(adc1InitCs),
-	.Miso_i				(Miso_i),
-	.Miso_o				(Miso_o),
+	.Ss0_o				(adc1InitCs),
+	.Ss1_o				(adc2InitCs),
+	.Miso_i				(),
+	.Miso_o				(),
 	
 	.CmdDataReg_o		(cmdDataReg),
 	.CmdDataVal_o		(cmdDataVal),
@@ -679,19 +694,11 @@ always	@(posedge	gclk)	begin
 	end
 end
 
-always	@(posedge	gclk)	begin
-	if	(!initRst)	begin
-		startMeasEventReg	<=	StartMeasEvent_i;
-	end	else	begin
-		startMeasEventReg	<=	0;
-	end
-end
-
 NcoRstGen	NcoRstGenInst
 (
 	.Clk_i				(gclk),
 	.Rst_i				(initRst),
-	.NcoPhInc_i			({ifF1twH[0+:PhIncWidth-CmdDataRegWith],ifF1twL}),
+	.NcoPhInc_i			({ifFtw1H[0+:PhIncWidth-CmdDataRegWith],ifFtw1L}),
 	.StartMeasEvent_i	(StartMeasEvent_i),
 	
 	.NcoRst_o			(ncoRst),
@@ -759,7 +766,7 @@ InternalDsp
 	.GatingPulse_i			(gatingPulse),
 
 	.StartMeas_i			(measStart),
-	.StartMeasDsp_i			(startMeasSyncRR),
+	.StartMeasDsp_i			(startMeasSync),
 	.OscDataRdFlag_i		(oscDataRdFlag),
 
 	.MeasNum_i				({measNum2[7:0],measNum1}),
@@ -771,11 +778,10 @@ InternalDsp
 	.CalModeEn_i			(adcCtrl[1]),
 	.CalModeDone_o			(calDone),
 
-	.IfFtw1L_i				(ifF1twL),
-	.IfFtw1H_i				(ifF1twH),
-	
-	.IfFtw2L_i				(ifF2twL),
-	.IfFtw2H_i				(ifF2twH),
+	.IfFtw1L_i				(ifFtw1L),
+	.IfFtw1H_i				(ifFtw1H),
+	.IfFtw2L_i				(ifFtw2L),
+	.IfFtw2H_i				(ifFtw2H),
 	
 	.NcoSin_o				(ncoSin),
 	.NcoCos_o				(ncoCos),
@@ -835,14 +841,13 @@ RegMapInst
 	.AdcCtrlReg_o			(adcCtrl),
 	.AdcDirectRd0Reg_o		(adcDirectRd0),
 	.AdcDirectRd1Reg_o		(adcDirectRd1),
-	.IfFtw1RegL_o			(ifF1twL),
-	.IfFtw1RegH_o			(ifF1twH),
-	.IfFtw2RegL_o			(ifF2twL),
-	.IfFtw2RegH_o			(ifF2twH),
+	.IfFtw1RegL_o			(ifFtw1L),
+	.IfFtw1RegH_o			(ifFtw1H),
+	.IfFtw2RegL_o			(ifFtw2L),
+	.IfFtw2RegH_o			(ifFtw2H),
 	.FilterCorrCoefRegL_o	(filterCorrCoefL),
 	.FilterCorrCoefRegH_o	(filterCorrCoefH),
-	.DspTrigInReg_o			(dspTrigIn),		
-	.DspTrigOutReg_o		(dspTrigOut),
+	.ActivePortSel_o		(activePortSel),
 	.DspTrigIn1Reg_o		(dspTrigIn1),
 	.DspTrigIn2Reg_o		(dspTrigIn2),
 	.DspTrigOut1Reg_o		(dspTrigOut1),	
@@ -926,7 +931,9 @@ RegMapInst
 	.MuxCtrl1Reg_o			(muxCtrl1),
 	.MuxCtrl2Reg_o			(muxCtrl2),
 	.MuxCtrl3Reg_o			(muxCtrl3),
-	.MuxCtrl4Reg_o			(muxCtrl4)
+	.MuxCtrl4Reg_o			(muxCtrl4),
+	.MuxCtrl5Reg_o			(muxCtrl5),
+	.MuxCtrl6Reg_o			(muxCtrl6)
 );
 
 //--------------------------------------------------------------------------------
@@ -1063,7 +1070,9 @@ PulseGenMux
 	.IntTrig_i		(intTrig1),
 	.IntTrig2_i		(intTrig2),
 	.PulseBus_i		(pulseBus),
-	.ExtPortsBus_i	(Trig6to1_io),
+	.ExtPortsBus_i	(),
+	.SlowMod_i		(1'b0),
+	.FastMod_i		(1'b0),
 	
 	.MuxOut_o		(pgMuxedOut[j])
 );	
@@ -1139,6 +1148,8 @@ GatingMux
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(pulseBus),
 	.ExtPortsBus_i	(),
+	.SlowMod_i		(1'b0),
+	.FastMod_i		(1'b0),
 	
 	.MuxOut_o		(gatingPulse)
 );
@@ -1164,6 +1175,8 @@ SampleStrobeMux
 	.IntTrig2_i		(1'b0),
 	.PulseBus_i		(pulseBus),
 	.ExtPortsBus_i	(),
+	.SlowMod_i		(1'b0),
+	.FastMod_i		(1'b0),
 	
 	.MuxOut_o		(sampleStrobe)
 );