Добавлена схема синхронизации для сигнала валидности одуля QuadSlaveSpi. Актуализированы проект для FPGA_S.

S5444_M/src/src/ExtDspInterface/QuadSlaveSpi.v

@@ -74,9 +74,6 @@ module	QuadSlaveSpi
 	reg	txWind;
 	reg	[4:0]	txCnt;
 
-	reg	ssReg;
-	reg	ssRegR;
-	reg	ssPos;
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
@@ -171,22 +168,47 @@ module	QuadSlaveSpi
 //	Generating output signals
 //================================================================================
 
-	always @(posedge Clk_i)	begin
-		ssReg	<=	Ss_i;
-		ssRegR	<=	ssReg;
+	localparam SyncLenght = 2;
+
+	reg	[SyncLenght-1:0] syncReg;
+
+	always	@(posedge Rst_i or posedge	Clk_i)	begin
+		if (Rst_i) begin
+			syncReg	<=	0;
+		end else begin
+			syncReg	<=	{syncReg[SyncLenght-2 : 0], Ss_i};
+		end
 	end
 
-	always @(posedge Clk_i)	begin
-		ssPos <= ssReg&!ssRegR;
+	wire ssSync;
+
+	assign ssSync = syncReg[SyncLenght-1];
+
+	reg ssSyncReg;
+
+	always	@(posedge Rst_i or posedge	Clk_i)	begin
+		if (Rst_i) begin
+			ssSyncReg <= 0;
+		end else begin
+			ssSyncReg <= ssSync;
+		end
 	end
 
-	always @(posedge Clk_i)	begin
+	reg	ssPos;
+
+	always	@(posedge Rst_i or posedge	Clk_i)	begin
+		if (Rst_i) begin
+			ssPos <= 0;
+		end else begin
+			ssPos <= ssSync&!ssSyncReg;
+		end
+	end
+
+	always	@(posedge	Clk_i)	begin
 		if	(!directTransit&!spiMode)	begin
-			if	(ssReg&!ssRegR)	begin
-				Val_o <= 1'b1;
-			end	else	begin
-				Val_o <= 0;
-			end
+			Val_o	<=	ssPos;
+		end	else	begin
+			Val_o	<=	0;
 		end
 	end
 
@@ -194,12 +216,10 @@ module	QuadSlaveSpi
 		if (Rst_i) 	begin
 			Data_o <= 0;
 		end else begin
-			if	(ssReg&!ssRegR)	begin
-				if (SpiRst_i) begin
-					Data_o <= singleCaptReg;
-				end else begin
-					Data_o <= {quadCaptReg3,quadCaptReg2,quadCaptReg1,quadCaptReg0};
-				end
+			if (SpiRst_i) begin
+				Data_o <= singleCaptReg;
+			end else begin
+				Data_o <= {quadCaptReg3,quadCaptReg2,quadCaptReg1,quadCaptReg0};
 			end
 		end
 	end

S5444_S/src/src/ExtDspInterface/QuadSlaveSpi.v

@@ -74,9 +74,6 @@ module	QuadSlaveSpi
 	reg	txWind;
 	reg	[4:0]	txCnt;
 
-	reg	ssReg;
-	reg	ssRegR;
-	reg	ssPos;
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
@@ -171,22 +168,47 @@ module	QuadSlaveSpi
 //	Generating output signals
 //================================================================================
 
-	always @(posedge Clk_i)	begin
-		ssReg	<=	Ss_i;
-		ssRegR	<=	ssReg;
+	localparam SyncLenght = 2;
+
+	reg	[SyncLenght-1:0] syncReg;
+
+	always	@(posedge Rst_i or posedge	Clk_i)	begin
+		if (Rst_i) begin
+			syncReg	<=	0;
+		end else begin
+			syncReg	<=	{syncReg[SyncLenght-2 : 0], Ss_i};
+		end
 	end
 
-	always @(posedge Clk_i)	begin
-		ssPos <= ssReg&!ssRegR;
+	wire ssSync;
+
+	assign ssSync = syncReg[SyncLenght-1];
+
+	reg ssSyncReg;
+
+	always	@(posedge Rst_i or posedge	Clk_i)	begin
+		if (Rst_i) begin
+			ssSyncReg <= 0;
+		end else begin
+			ssSyncReg <= ssSync;
+		end
 	end
 
-	always @(posedge Clk_i)	begin
+	reg	ssPos;
+
+	always	@(posedge Rst_i or posedge	Clk_i)	begin
+		if (Rst_i) begin
+			ssPos <= 0;
+		end else begin
+			ssPos <= ssSync&!ssSyncReg;
+		end
+	end
+
+	always	@(posedge	Clk_i)	begin
 		if	(!directTransit&!spiMode)	begin
-			if	(ssReg&!ssRegR)	begin
-				Val_o <= 1'b1;
-			end	else	begin
-				Val_o <= 0;
-			end
+			Val_o	<=	ssPos;
+		end	else	begin
+			Val_o	<=	0;
 		end
 	end
 
@@ -194,12 +216,10 @@ module	QuadSlaveSpi
 		if (Rst_i) 	begin
 			Data_o <= 0;
 		end else begin
-			if	(ssReg&!ssRegR)	begin
-				if (SpiRst_i) begin
-					Data_o <= singleCaptReg;
-				end else begin
-					Data_o <= {quadCaptReg3,quadCaptReg2,quadCaptReg1,quadCaptReg0};
-				end
+			if (SpiRst_i) begin
+				Data_o <= singleCaptReg;
+			end else begin
+				Data_o <= {quadCaptReg3,quadCaptReg2,quadCaptReg1,quadCaptReg0};
 			end
 		end
 	end