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@@ -269,8 +269,8 @@ module S5443Top
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wire [AdcDataWidth-1:0] adcDataBus [ChNum-1:0];
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wire overCtrlR = |overCtrlChannels[ChNum-1:0];
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- localparam TESTCNTPARAM = 32'd100000000;
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- reg [31:0] testCnt;
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+ localparam LEDCNTTHRESH = 32'd100000000;
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+ reg [31:0] ledCnt;
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wire refClk;
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wire windClk150;
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@@ -575,9 +575,7 @@ module S5443Top
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assign PortSel_o [5:4] = slowModOut[ChNum-2] ? activePortSel[9:8]:2'b0;
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assign PortSel_o [3:2] = slowModOut[ChNum-3] ? activePortSel[5:4]:2'b0;
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assign PortSel_o [1:0] = slowModOut[ChNum-4] ? activePortSel[1:0]:2'b0;
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-
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- // assign PortSelDir_o = 4'd15;
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-
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+
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assign Trig6to1Dir_o [0] = !measCtrl[18];
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assign Trig6to1Dir_o [1] = !measCtrl[19];
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assign Trig6to1Dir_o [2] = !measCtrl[20];
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@@ -626,6 +624,7 @@ end
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//--------------------------------------------------------------------------------
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// Data Receiving Interface
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//--------------------------------------------------------------------------------
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+
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IBUFDS
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#(
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.DIFF_TERM ("FALSE")
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@@ -743,8 +742,6 @@ ExternalDspInterface
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.Sck_o (adcInitSck),
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.Ss0_o (adc1InitCs),
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.Ss1_o (adc2InitCs),
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- .Miso_i (),
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- .Miso_o (),
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.CmdDataReg_o (cmdDataReg),
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.CmdDataVal_o (cmdDataVal),
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@@ -773,6 +770,7 @@ ExternalDspInterface
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//--------------------------------------------------------------------------------
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// Internal DSP calculation module
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//--------------------------------------------------------------------------------
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+
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NcoRstGen NcoRstGenInst
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(
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.Clk_i (gclk),
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@@ -852,6 +850,7 @@ InternalDsp
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//--------------------------------------------------------------------------------
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// Reg Map With Config Registers
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//--------------------------------------------------------------------------------
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+
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RegMap
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#(
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.CmdRegWidth (CmdRegWidth),
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@@ -985,6 +984,7 @@ RegMapInst
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//--------------------------------------------------------------------------------
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// Global FPGA reset generator
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//--------------------------------------------------------------------------------
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+
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InitRst FpgaInitRst
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(
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.clk_i (gclk),
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@@ -994,6 +994,7 @@ InitRst FpgaInitRst
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//--------------------------------------------------------------------------------
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// ADC overload detection
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//--------------------------------------------------------------------------------
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+
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genvar i;
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generate
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for (i=0; i<ChNum; i=i+1) begin :OverControl
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@@ -1017,6 +1018,7 @@ endgenerate
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//--------------------------------------------------------------------------------
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// Gain Control module
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//--------------------------------------------------------------------------------
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+
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genvar g;
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generate
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for (g=0; g<ChNum; g=g+1) begin :GainControl
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@@ -1063,6 +1065,7 @@ StartAfterGainSelInst
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.MeasStart_o (measStart)
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);
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+
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//--------------------------------------------------------------------------------
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// Trig TO/FROM DSP
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//--------------------------------------------------------------------------------
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@@ -1507,18 +1510,18 @@ SampleStrobeGenRstDemux
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//--------------------------------------------------------------------------------
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always @(posedge gclk) begin
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if (initRst) begin
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- testCnt <= 32'b0;
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- end else if (testCnt != TESTCNTPARAM) begin
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- testCnt <= testCnt+1;
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+ ledCnt <= 32'b0;
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+ end else if (ledCnt != LEDCNTTHRESH) begin
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+ ledCnt <= ledCnt+1;
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end else begin
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- testCnt <= 32'd0;
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+ ledCnt <= 32'd0;
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end
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end
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always @(posedge gclk) begin
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if (initRst) begin
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ledReg <= 1'b0;
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- end else if ((testCnt == TESTCNTPARAM-1)) begin
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+ end else if ((ledCnt == LEDCNTTHRESH-1)) begin
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ledReg <= ~ledReg;
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end
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end
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