Поправлены пины.

S5444_M/src/constrs/S5443Top.xdc

@@ -2,8 +2,8 @@ set_property PACKAGE_PIN D2 [get_ports Adc1DataDa0P_i]
 set_property PACKAGE_PIN E2 [get_ports Adc1DataDa1P_i]
 set_property PACKAGE_PIN K1 [get_ports Adc1DataDb0P_i]
 set_property PACKAGE_PIN M1 [get_ports Adc1DataDb1P_i]
-set_property PACKAGE_PIN F15 [get_ports Adc2DataDa0P_i]
-set_property PACKAGE_PIN D15 [get_ports Adc2DataDa1P_i]
+set_property PACKAGE_PIN F15 [get_ports Adc2DataDa0N_i] 
+set_property PACKAGE_PIN D15 [get_ports Adc2DataDa1N_i] 
 set_property PACKAGE_PIN A13 [get_ports Adc2DataDb0P_i]
 set_property PACKAGE_PIN A11 [get_ports Adc2DataDb1P_i]
 
@@ -12,12 +12,13 @@ set_property PACKAGE_PIN A11 [get_ports Adc2DataDb1P_i]
 #   TIMING CONSTRAINTS
 
 
+
 #==========================================================================
 #	INPUT CLOCKS
-set_property PACKAGE_PIN H3 [get_ports ClkP_i]
-set_property IOSTANDARD LVDS_25 [get_ports ClkP_i]
+set_property PACKAGE_PIN H3 [get_ports ClkN_i]       
 set_property IOSTANDARD LVDS_25 [get_ports ClkN_i]
-create_clock -period 20.000 [get_ports ClkP_i]
+set_property IOSTANDARD LVDS_25 [get_ports ClkP_i]
+create_clock -period 20.000 [get_ports ClkN_i]
 
 #==========================================================================
 #	ADC1
@@ -41,7 +42,7 @@ set_property IOSTANDARD LVDS_25 [get_ports Adc1DataDb1N_i]
 #==========================================================================
 #	ADC2
 
-set_property PACKAGE_PIN B15 [get_ports Adc2FclkP_i]
+set_property PACKAGE_PIN B15 [get_ports Adc2FclkN_i]     
 set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkP_i]
 set_property IOSTANDARD LVDS_25 [get_ports Adc2FclkN_i]
 
@@ -241,11 +242,8 @@ set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh1_o]
 set_property PACKAGE_PIN G14 [get_ports DitherCtrlCh2_o]
 set_property IOSTANDARD LVCMOS25 [get_ports DitherCtrlCh2_o]
 
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Ss_i_IBUF]
 
 #set_false_path -from [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins Clk200Gen/rx_plle2_adv_inst/CLKOUT0]]
 
 
-connect_debug_port u_ila_0/clk [get_nets [list gclk_BUFG]]
-connect_debug_port dbg_hub/clk [get_nets gclk_BUFG]
-

S5444_M/src/src/ExtDspInterface/DspInterface.v

@@ -255,6 +255,7 @@ MeasDataFifoInst
 	.PpiBusy_i		(ppiBusy),	
 	.MeasNum_i		(MeasNum_i),	
 	.StartMeasDsp_i	(StartMeasDsp_i),	
+	.DspReadyForRx_i(DspReadyForRx_i),	
 	.MeasDataBus_i	(measDataBus),
 	.MeasDataVal_i	(LpOutStart_i),	
 	

S5444_M/src/src/ExtDspInterface/DspPpiOut.v

@@ -141,20 +141,35 @@ end
 //================================================================================
 //  INSTANTIATIONS
 //================================================================================		
-ODDR2
-#(
-	.DDR_ALIGNMENT("NONE"),
-	.INIT	(1'b0),
-	.SRTYPE	("SYNC")
-) clk_i10OutInst (
-	.Q		(LpOutClk_o),
-	.C0		(Clk_i),
-	.C1		(~Clk_i),
-	.CE		(1'b1),
-	.D0		(1'b1),
-	.D1		(1'b0),
-	.R		(1'b0),
-	.S		(1'b0)
-);		
+// ODDR2
+// #(
+	// .DDR_ALIGNMENT("NONE"),
+	// .INIT	(1'b0),
+	// .SRTYPE	("SYNC")
+// ) clk_i10OutInst (
+	// .Q		(LpOutClk_o),
+	// .C0		(Clk_i),
+	// .C1		(~Clk_i),
+	// .CE		(1'b1),
+	// .D0		(1'b1),
+	// .D1		(1'b0),
+	// .R		(1'b0),
+	// .S		(1'b0)
+// );		
 
+ODDR 
+#(
+	.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
+	.INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
+	.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
+) ODDR_inst (
+	.Q(LpOutClk_o),   // 1-bit DDR output
+	.C(Clk_i),   // 1-bit clock input
+	.CE(1'b1), // 1-bit clock enable input
+	.D1(1'b1), // 1-bit data input (positive edge)
+	.D2(1'b0), // 1-bit data input (negative edge)
+	.R(1'b0),   // 1-bit reset
+	.S(1'b0)    // 1-bit set
+);
+   
 endmodule

S5444_M/src/src/PulseMeas/MeasStartEventGen.v

@@ -1,4 +1,5 @@
 `timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)	
 //////////////////////////////////////////////////////////////////////////////////
 // Company: 
 // Engineer: 
@@ -44,6 +45,7 @@ module	MeasStartEventGen
 //  LOCALPARAM
 
 //================================================================================
+	reg		startMeasEventVal;
 	reg		startMeasEvent;
 	reg		initTrig;
 	
@@ -59,30 +61,46 @@ module	MeasStartEventGen
 
 	always	@(posedge	Clk_i)	begin
 		if	(!Rst_i)	begin
-			measTrigReg	<=	MeasTrig_i;
+			measTrigReg	 <=	MeasTrig_i;
 		end	else	begin
-			measTrigReg	=	0;
+			measTrigReg	 <=	0;
 		end
 	end
 	
-	always	@(posedge	Clk_i)	begin
+	always	@(posedge Clk_i)	begin
 		if	(!Rst_i)	begin
 			if	(StartMeasDsp_i)	begin
 				if	(measTrigPos)	begin
-					startMeasEvent	<=	1'b1;
+					startMeasEventVal	<=	1'b1;
+				end 
+			end	else	begin
+				startMeasEventVal	<=	0;
+			end
+		end	else	begin
+			startMeasEventVal	<=	0;
+		end
+	end
+	
+	always	@(*)	begin
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(startMeasEventVal)	begin
+					startMeasEvent	=	measTrigReg;
+				end else begin
+					startMeasEvent	=	0;
 				end
 			end	else	begin
-				startMeasEvent	<=	0;
+				startMeasEvent	=	0;
 			end
 		end	else	begin
-			startMeasEvent	<=	0;
+			startMeasEvent	=	0;
 		end
 	end
 	
 	always	@(*)	begin
 		if	(!Rst_i)	begin
 			if	(StartMeasDsp_i)	begin
-				if	(measTrigPos)	begin
+				if	(MeasTrig_i)	begin
 					initTrig	=	1'b1;
 				end	else	begin
 					initTrig	=	1'b0;
@@ -94,7 +112,6 @@ module	MeasStartEventGen
 			initTrig	=	0;
 		end
 	end
-
 endmodule
 
 

S5444_M/src/src/Sim/S5443TopPulseProfileTb.v

@@ -440,9 +440,9 @@ end
 always	@(posedge	Clk41)	begin
 	if	(txCurrState	==	CMD)	begin
 		if	(cmdCnt	==	0)	begin
-			DspSpiData		<=	DirectAdc1Access;
+			DspSpiData		<=	MeasCmd;
 		end	else	if	(cmdCnt	==	1)	begin
-			DspSpiData		<=	DirectAdc2Access;
+			DspSpiData		<=	IfFtwH;
 		end	else	if	(cmdCnt	==	2)	begin
 			DspSpiData		<=	IfFtwL;
 		end	else	if	(cmdCnt	==	3)	begin

S5444_M/src/src/Top/S5443Top.v

@@ -642,8 +642,8 @@ IBUFDS
 ClkBuf 
 (
 	.O	(gclk),  
-	.I	(ClkP_i),  
-	.IB	(ClkN_i) 
+	.I	(~ClkP_i),  
+	.IB	(~ClkN_i) 
 );
    
 Clk200Gen	ClocksGenerator 
@@ -685,13 +685,13 @@ AdcDataInterface
 	.Adc1DataDb1P_i	(Adc1DataDb1P_i),
 	.Adc1DataDb1N_i	(Adc1DataDb1N_i),
 	
-	.Adc2FclkP_i	(Adc2FclkP_i),		
-	.Adc2FclkN_i	(Adc2FclkN_i),	
+	.Adc2FclkP_i	(~Adc2FclkP_i),		
+	.Adc2FclkN_i	(~Adc2FclkN_i),	
 	
-	.Adc2DataDa0P_i	(Adc2DataDa0P_i),
-	.Adc2DataDa0N_i	(Adc2DataDa0N_i),
-	.Adc2DataDa1P_i	(Adc2DataDa1P_i),
-	.Adc2DataDa1N_i	(Adc2DataDa1N_i),
+	.Adc2DataDa0P_i	(~Adc2DataDa0P_i),
+	.Adc2DataDa0N_i	(~Adc2DataDa0N_i),
+	.Adc2DataDa1P_i	(~Adc2DataDa1P_i),
+	.Adc2DataDa1N_i	(~Adc2DataDa1N_i),
 	
 	.Adc2DataDb0P_i	(Adc2DataDb0P_i),	
 	.Adc2DataDb0N_i	(Adc2DataDb0N_i),