Убрал части кода, добавленные при дебаге проблем с АЦП.

S5444_M/src/src/ExtDspInterface/DspInterface.v

@@ -129,15 +129,6 @@ module	DspInterface
 	assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	Adc2R2ImResult_i;
 	assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	Adc2R2ReResult_i;
 	
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-7))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChT1Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-6))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChR1Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-5))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChR2Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-4))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChT2Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-3))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChT1Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-2))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChR1Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChR2Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChT2Data_i};
-	
 	assign	OscDataRdFlag_o	=	measDataValTx;
 	
 //================================================================================

S5444_M/src/src/InternalDsp/InternalDsp.v

@@ -158,11 +158,6 @@ module InternalDsp
 	reg	[AdcDataWidth-1:0]	adc2ChT2DataR;
 //================================================================================
 //  ASSIGNMENTS
-
-	// assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
-	// assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
-	// assign	adcDataBus	[ChNum-3]	=	{{2{Adc1ChR1Data_i[AdcDataWidth-1]}},Adc1ChR1Data_i,4'b0};
-	// assign	adcDataBus	[ChNum-4]	=	{{2{Adc1ChT1Data_i[AdcDataWidth-1]}},Adc1ChT1Data_i,4'b0};	
 	
 	assign	adcDataBus	[ChNum-1]	=	{{2{adc2ChT2DataR[AdcDataWidth-1]}},adc2ChT2DataR,4'b0};
 	assign	adcDataBus	[ChNum-2]	=	{{2{adc2ChR2DataR[AdcDataWidth-1]}},adc2ChR2DataR,4'b0};
@@ -187,18 +182,7 @@ module InternalDsp
 	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-2];
 	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-2];
 	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-1];
-	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-1];
-	
-	// assign	Adc1ImT1Data_o	=	32'h3f800000;
-	// assign	Adc1ReT1Data_o	=	32'h3f800000;
-	// assign	Adc1ImR1Data_o	=	32'h3f800000;
-	// assign	Adc1ReR1Data_o	=	32'h3f800000;
-                
-	// assign	Adc2ImR2Data_o	=	32'h3f800000;
-	// assign	Adc2ReR2Data_o	=	32'h3f800000;
-	// assign	Adc2ImT2Data_o	=	32'h3f800000;
-	// assign	Adc2ReT2Data_o	=	32'h3f800000;
-	
+	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-1];	
 	
 	assign	MeasDataRdy_o	=	&resultValBus;
 	assign	EndMeas_o		=	stopMeas;

S5444_S/src/constrs/S5443Top.xdc

@@ -198,25 +198,4 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Sck_i_IBUF]
 
 
 
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list gclk_BUFG]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-set_property port_width 14 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {adc1ChR1Data[0]} {adc1ChR1Data[1]} {adc1ChR1Data[2]} {adc1ChR1Data[3]} {adc1ChR1Data[4]} {adc1ChR1Data[5]} {adc1ChR1Data[6]} {adc1ChR1Data[7]} {adc1ChR1Data[8]} {adc1ChR1Data[9]} {adc1ChR1Data[10]} {adc1ChR1Data[11]} {adc1ChR1Data[12]} {adc1ChR1Data[13]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-set_property port_width 14 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {adc1ChT1Data[0]} {adc1ChT1Data[1]} {adc1ChT1Data[2]} {adc1ChT1Data[3]} {adc1ChT1Data[4]} {adc1ChT1Data[5]} {adc1ChT1Data[6]} {adc1ChT1Data[7]} {adc1ChT1Data[8]} {adc1ChT1Data[9]} {adc1ChT1Data[10]} {adc1ChT1Data[11]} {adc1ChT1Data[12]} {adc1ChT1Data[13]}]]
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets gclk_BUFG]
+

S5444_S/src/src/ExtDspInterface/DspInterface.v

@@ -129,19 +129,6 @@ module	DspInterface
 	assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	Adc2R2ImResult_i;
 	assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	Adc2R2ReResult_i;
 	
-	// wire [13:0] testR1 = 14'd16318;
-	// wire [13:0] testR2 = 14'd12468;
-	
-	
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-7))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChT1Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-6))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChR1Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-5))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChR2Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-4))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChT2Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-3))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChT1Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-2))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChR1Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChR2Data_i};
-	// assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChT2Data_i};
-	
 	assign	OscDataRdFlag_o	=	measDataValTx;
 	
 //================================================================================

S5444_S/src/src/InternalDsp/InternalDsp.v

@@ -1,5 +1,5 @@
 `timescale 1ns / 1ps
-// (* keep_hierarchy = "yes" *)
+(* keep_hierarchy = "yes" *)
 //////////////////////////////////////////////////////////////////////////////////
 // Company: 
 // Engineer: 
@@ -163,11 +163,6 @@ module InternalDsp
 	assign	adcDataBus	[ChNum-2]	=	{{2{adc2ChR2DataR[AdcDataWidth-1]}},adc2ChR2DataR,4'b0};
 	assign	adcDataBus	[ChNum-3]	=	{{2{adc1ChR1DataR[AdcDataWidth-1]}},adc1ChR1DataR,4'b0};
 	assign	adcDataBus	[ChNum-4]	=	{{2{adc1ChT1DataR[AdcDataWidth-1]}},adc1ChT1DataR,4'b0};
-
-	// assign	adcDataBus	[ChNum-1]	=	{{2{ncoSinFirstTone[NcoWidth-1]}},ncoSinFirstTone[NcoWidth-1-:14],4'b0};
-	// assign	adcDataBus	[ChNum-2]	=	{{2{ncoSinFirstTone[NcoWidth-1]}},ncoSinFirstTone[NcoWidth-1-:14],4'b0};
-	// assign	adcDataBus	[ChNum-3]	=	{{2{ncoSinFirstTone[NcoWidth-1]}},ncoSinFirstTone[NcoWidth-1-:14],4'b0};
-	// assign	adcDataBus	[ChNum-4]	=	{{2{ncoSinFirstTone[NcoWidth-1]}},ncoSinFirstTone[NcoWidth-1-:14],4'b0};	
 	
 	assign	adcDataBusExt	[ChNum-1]	=	calAdcData	[ChNum-1]+prngDataBus[ChNum-1];
 	assign	adcDataBusExt	[ChNum-2]	=	calAdcData	[ChNum-2]+prngDataBus[ChNum-2];
@@ -183,11 +178,11 @@ module InternalDsp
 	assign	Adc1ReT1Data_o	=	resultReBus	[ChNum-4];
 	assign	Adc1ImR1Data_o	=	resultImBus	[ChNum-3];
 	assign	Adc1ReR1Data_o	=	resultReBus	[ChNum-3];
-              
+               
 	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-2];
 	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-2];
 	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-1];
-	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-1];
+	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-1];	
 	
 	assign	MeasDataRdy_o	=	&resultValBus;
 	assign	EndMeas_o		=	stopMeas;
@@ -447,6 +442,7 @@ generate
 			// .FilterCorrCoef_i	(32'h3f800000),
 			.AverageNoizeLvl_i	(averageNoizeLvl),
 			.AdcData_i			(gatedAdcDataBus[g]),
+			// .AdcData_i			({{2{ncoCosFirstTone[17]}},ncoCosFirstTone}),
 			.Wind_i				(wind),
 			// .NcoSin_i			(ncoSinFirstTone),
 			// .NcoCos_i			(ncoCosFirstTone),
@@ -454,6 +450,8 @@ generate
 			.NcoSin_i			(currNcoSinTone[g]),
 			.NcoCos_i			(currNcoCosTone[g]),	
 			.NormCoef_i			(windNormCoef),
+			// .NormCoef_i			(32'h3f800000),
+			// .NormCoef_i			(32'h3f03993a),
 
 			.CorrResultIm_o		(resultImBus[g]),
 			.CorrResultRe_o		(resultReBus[g]),