Исправлена ошибка с выводом сигнала Cs при инициализации АЦП.

S5444_M/src/constrs/S5443Top.xdc

@@ -277,6 +277,7 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Sck_i_IBUF]
 
 
 
+
 
 create_debug_core u_ila_0 ila
 set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
@@ -289,9 +290,25 @@ set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
 set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
 set_property port_width 1 [get_debug_ports u_ila_0/clk]
 connect_debug_port u_ila_0/clk [get_nets [list gclk_BUFG]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-set_property port_width 1 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list OverloadS_i_IBUF]]
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
+set_property port_width 14 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {adc1ChR1Data[0]} {adc1ChR1Data[1]} {adc1ChR1Data[2]} {adc1ChR1Data[3]} {adc1ChR1Data[4]} {adc1ChR1Data[5]} {adc1ChR1Data[6]} {adc1ChR1Data[7]} {adc1ChR1Data[8]} {adc1ChR1Data[9]} {adc1ChR1Data[10]} {adc1ChR1Data[11]} {adc1ChR1Data[12]} {adc1ChR1Data[13]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
+set_property port_width 14 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {adc1ChT1Data[0]} {adc1ChT1Data[1]} {adc1ChT1Data[2]} {adc1ChT1Data[3]} {adc1ChT1Data[4]} {adc1ChT1Data[5]} {adc1ChT1Data[6]} {adc1ChT1Data[7]} {adc1ChT1Data[8]} {adc1ChT1Data[9]} {adc1ChT1Data[10]} {adc1ChT1Data[11]} {adc1ChT1Data[12]} {adc1ChT1Data[13]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
+set_property port_width 14 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {adc2ChR2Data[0]} {adc2ChR2Data[1]} {adc2ChR2Data[2]} {adc2ChR2Data[3]} {adc2ChR2Data[4]} {adc2ChR2Data[5]} {adc2ChR2Data[6]} {adc2ChR2Data[7]} {adc2ChR2Data[8]} {adc2ChR2Data[9]} {adc2ChR2Data[10]} {adc2ChR2Data[11]} {adc2ChR2Data[12]} {adc2ChR2Data[13]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
+set_property port_width 14 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {adc2ChT2Data[0]} {adc2ChT2Data[1]} {adc2ChT2Data[2]} {adc2ChT2Data[3]} {adc2ChT2Data[4]} {adc2ChT2Data[5]} {adc2ChT2Data[6]} {adc2ChT2Data[7]} {adc2ChT2Data[8]} {adc2ChT2Data[9]} {adc2ChT2Data[10]} {adc2ChT2Data[11]} {adc2ChT2Data[12]} {adc2ChT2Data[13]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list startMeasSyncRR]]
 set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
 set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
 set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]

S5444_M/src/src/ExtDspInterface/DspInterface.v

@@ -129,6 +129,15 @@ module	DspInterface
 	assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	Adc2R2ImResult_i;
 	assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	Adc2R2ReResult_i;
 	
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-7))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChT1Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-6))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChR1Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-5))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChR2Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-4))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChT2Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-3))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChT1Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-2))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChR1Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChR2Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChT2Data_i};
+	
 	assign	OscDataRdFlag_o	=	measDataValTx;
 	
 //================================================================================

S5444_S/src/src/AdcDataRx/AdcDataInterface.v

@@ -105,7 +105,7 @@ module	AdcDataInterface
 	assign	Adc1ChT1Data_o	=	adc1ChT1DataSync;
 	assign	Adc1ChR1Data_o	=	adc1ChR1DataSync;
 	assign	Adc2ChR2Data_o	=	adc2ChR2DataSync;
-	assign	Adc2ChT2Data_o	=	adc2ChT2DataSync;
+	assign	Adc2ChT2Data_o	=	~adc2ChT2DataSync;
 	
 	wire	idly_reset_int;
 	wire	rx_reset;

S5444_S/src/src/AdcDataRx/Description.txt

@@ -0,0 +1,3 @@
+1. Модуль AdcDataInterface просто обертка для модулей приёма данных с двух АЦП.
+2. Модуль TopRx реализовывает приём данных с АЦП в соответствии с XAPP585.
+3. Модуль AdcSync служит для синхронизации данных между клоковых доменов внутри FPGA. Модуль по сути простая синхро цепь из двух последовательных регистров.

S5444_S/src/src/ExtDspInterface/DspInterface.v

@@ -129,6 +129,19 @@ module	DspInterface
 	assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	Adc2R2ImResult_i;
 	assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	Adc2R2ReResult_i;
 	
+	// wire [13:0] testR1 = 14'd16318;
+	// wire [13:0] testR2 = 14'd12468;
+	
+	
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-7))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChT1Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-6))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChR1Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-5))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChR2Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-4))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChT2Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-3))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChT1Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-2))-1-:ResultWidth]	=	{{18{1'b0}},Adc1ChR1Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChR2Data_i};
+	// assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	{{18{1'b0}},Adc2ChT2Data_i};
+	
 	assign	OscDataRdFlag_o	=	measDataValTx;
 	
 //================================================================================

S5444_S/src/src/Top/S5443Top.v

@@ -150,8 +150,8 @@ module	S5443Top
 	wire	adcInitRst;
 	wire	adcInitMosi;
 	wire	adcInitSck;
-	wire	adc0InitCs;
 	wire	adc1InitCs;
+	wire	adc2InitCs;
 
 	wire	[ResultWidth-1:0]	adc1ImT1;
 	wire	[ResultWidth-1:0]	adc1ReT1;
@@ -482,6 +482,11 @@ module	S5443Top
 	assign	adcDataBus	[ChNum-2]	=	adc2ChR2Data;
 	assign	adcDataBus	[ChNum-1]	=	adc2ChT2Data;
 	
+	// assign	adcDataBus	[ChNum-4]	=	AdcData_i;
+	// assign	adcDataBus	[ChNum-3]	=	AdcData_i;
+	// assign	adcDataBus	[ChNum-2]	=	AdcData_i;
+	// assign	adcDataBus	[ChNum-1]	=	AdcData_i;
+	
 	assign	gainManual	[ChNum-4]	=	gainCtrl[5];
 	assign	gainManual	[ChNum-3]	=	gainCtrl[4];
 	assign	gainManual	[ChNum-2]	=	gainCtrl[6];
@@ -494,8 +499,8 @@ module	S5443Top
 	
 	assign	AdcInitMosi_o	=	adcInitMosi;
 	assign	AdcInitClk_o	=	adcInitSck;			
-	assign	Adc1InitCs_o	=	adc0InitCs;
-	assign	Adc2InitCs_o	=	adc1InitCs;
+	assign	Adc1InitCs_o	=	adc1InitCs;
+	assign	Adc2InitCs_o	=	adc2InitCs;
 	assign	AdcInitRst_o	=	adcCtrl[0];
 	
 	// assign	Led_o	=	ledReg	&(adc1ImT1|adc1ReT1|adc1ImR1|adc1ReR1|adc2ImT2|adc2ReT2|adc2ImR2|adc2ReR2);
@@ -512,19 +517,12 @@ module	S5443Top
 	assign	gainHighThresholdBus	[ChNum-2]	=	gainHighThreshR2;
 	assign	gainHighThresholdBus	[ChNum-1]	=	gainHighThreshT2;
 	
-	
-	// assign	testAdc = (adc1ChT1Data == 14'h3fff);
-	assign	testAdc = (adc1ChR1Data == 14'h3fff);
-	// assign	testAdc = (adc2ChR2Data == 14'h3fff);
-	// assign	testAdc = (adc2ChT2Data == 14'h3fff);
-	
 	assign	AmpEn_o	[3]	=	~ampEnNewStates[3];		
 	assign	AmpEn_o	[2]	=	~ampEnNewStates[2];	
 	assign	AmpEn_o	[1]	=	~ampEnNewStates[0];	
 	assign	AmpEn_o	[0]	=	~ampEnNewStates[1];	
 	
-	// assign	Overload_o	=	overCtrlR;
-	assign	Overload_o	=	testAdc;
+	assign	Overload_o	=	overCtrlR;
 //================================================================================
 //  CODING
 //================================================================================