Добавил врапперы для устройств

src/src/ClkGen/ClkGen.v

@@ -16,6 +16,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////
 module ClkGen (
 	output Clk60Mhz_o,
+	output Clk40Mhz_o,
 	output Clk25Mhz_o
 );
 
@@ -24,9 +25,9 @@ module ClkGen (
 //==========================================
 wire clk25Mhz;
 wire clk210Mhz;
-wire clk60Mhz;
 
 wire lockFirstPll;
+wire lockSecondPll;
 
 //==========================================
 // Assignments
@@ -47,6 +48,12 @@ GowinPllFirst GowinPllFirst
 	.clkout(clk210Mhz)
 );
 
+GowinPllSecond GowinPllSecond
+(
+	.clkin(clk25Mhz),
+	.clkout(Clk40Mhz_o)
+);
+
 GowinClkDiv3dot5 GowinClkDiv210MhzTo60Mhz
 (
 	.hclkin(clk210Mhz),

src/src/ClkGen/GowinPllSecond/GowinPllSecond.ipc

@@ -0,0 +1,24 @@
+[General]
+ipc_version=4
+file=GowinPllSecond
+module=GowinPllSecond
+target_device=gw1n9-022
+type=clock_rpll
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=0
+CLKIN_FREQ=25
+CLKOUTD=false
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=40
+CLKOUT_TOLERANCE=0
+DYNAMIC=true
+LANG=0
+LOCK_EN=true
+MODE_GENERAL=true
+PLL_PWD=false
+RESET_PLL=false

src/src/ClkGen/GowinPllSecond/GowinPllSecond.mod

@@ -0,0 +1,33 @@
+-series GW1N
+-device GW1N-9
+-device_version 
+-package QFN88
+-part_number GW1N-UV9QN88C6/I5
+
+
+-mod_name GowinPllSecond
+-file_name GowinPllSecond
+-path C:/Gowin/Projects/BOCHv3_FPGA/src/src/ClkGen/GowinPllSecond/
+-type PLL
+-rPll true
+-file_type vlg
+-dev_type GW1N-9
+-dyn_idiv_sel false
+-idiv_sel 5
+-dyn_fbdiv_sel false
+-fbdiv_sel 8
+-dyn_odiv_sel false
+-odiv_sel 16
+-dyn_da_en true
+-rst_sig false
+-rst_sig_p false
+-fclkin 25
+-clkfb_sel 0
+-en_lock true
+-clkout_bypass false
+-clkout_ft_dir 1
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd false
+-clkoutd_bypass false
+-en_clkoutd3 false

src/src/ClkGen/GowinPllSecond/GowinPllSecond.v

@@ -0,0 +1,63 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Mon Nov 25 12:18:21 2024
+
+module GowinPllSecond (clkout, lock, clkin);
+
+output clkout;
+output lock;
+input clkin;
+
+wire clkoutp_o;
+wire clkoutd_o;
+wire clkoutd3_o;
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+rPLL rpll_inst (
+    .CLKOUT(clkout),
+    .LOCK(lock),
+    .CLKOUTP(clkoutp_o),
+    .CLKOUTD(clkoutd_o),
+    .CLKOUTD3(clkoutd3_o),
+    .RESET(gw_gnd),
+    .RESET_P(gw_gnd),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd})
+);
+
+defparam rpll_inst.FCLKIN = "25";
+defparam rpll_inst.DYN_IDIV_SEL = "false";
+defparam rpll_inst.IDIV_SEL = 4;
+defparam rpll_inst.DYN_FBDIV_SEL = "false";
+defparam rpll_inst.FBDIV_SEL = 7;
+defparam rpll_inst.DYN_ODIV_SEL = "false";
+defparam rpll_inst.ODIV_SEL = 16;
+defparam rpll_inst.PSDA_SEL = "0000";
+defparam rpll_inst.DYN_DA_EN = "true";
+defparam rpll_inst.DUTYDA_SEL = "1000";
+defparam rpll_inst.CLKOUT_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUT_DLY_STEP = 0;
+defparam rpll_inst.CLKOUTP_DLY_STEP = 0;
+defparam rpll_inst.CLKFB_SEL = "internal";
+defparam rpll_inst.CLKOUT_BYPASS = "false";
+defparam rpll_inst.CLKOUTP_BYPASS = "false";
+defparam rpll_inst.CLKOUTD_BYPASS = "false";
+defparam rpll_inst.DYN_SDIV_SEL = 2;
+defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
+defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
+defparam rpll_inst.DEVICE = "GW1N-9";
+
+endmodule //GowinPllSecond

src/src/ClkGen/GowinPllSecond/GowinPllSecond_tmp.v

@@ -0,0 +1,18 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.03 (64-bit)
+//Part Number: GW1N-UV9QN88C6/I5
+//Device: GW1N-9
+//Created Time: Mon Nov 25 12:18:21 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinPllSecond your_instance_name(
+        .clkout(clkout), //output clkout
+        .lock(lock), //output lock
+        .clkin(clkin) //input clkin
+    );
+
+//--------Copy end-------------------

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -106,13 +106,14 @@ module InterfaceArbiter
 	reg plsToggleSyncSignalR;
 
 	/*Flash signals*/
-	reg plsToggleFlash;
+	reg 	plsToggleFlash;
+	wire 	plsToggleMux;
 
 //================================================================================
 //  ASSIGNMENTS
 	assign ssPos = ssRegR & !ssRegRR;
 
-	
+	assign plsToggleMux = (DirectFlagFlash_i) ? plsToggleFlash:plsToggle;
 	assign DataVal_o = plsToggleSyncSignalR;
 	assign Data_o = (spiMode)? dataRegQSpi:dataRegSSpi;
 
@@ -235,15 +236,6 @@ module InterfaceArbiter
 		end
 	end
 
-	always @(*) begin
-		if (currState == IDLE && (Data_o[11]& Data_o[8])) begin
-			TestTrig_o = 1'b1;
-		end
-		else begin
-			TestTrig_o = 1'b0;
-		end
-	end
-
 	always @(posedge Sck_i or posedge Rst_i) begin 
 		if (Rst_i) begin 
 			ssCnt <= 0;
@@ -299,35 +291,13 @@ module InterfaceArbiter
 		end
 	end
 
-	always @(posedge Sck_i or posedge Rst_i) begin 
-		if (Rst_i) begin 
-			qSpiDirectMode <= 1'b0;
-		end
-		else begin 
-			if (currState == IDLE) begin 
-				if (ssCnt == 2) begin 
-					if (captRegSspi[1:0] == 2'b11) begin 
-						qSpiDirectMode <= 1'b1; 
-					end 
-					else begin 
-						qSpiDirectMode <= 1'b0; 
-					end
-				end
-			end
-		end
-	end
-
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (currState == IDLE) begin
 				if (!spiMode) begin
-					wordsNum <= dataRegSSpi[16:1];
+					wordsNum <= dataRegSSpi[17:1];
 				end else begin
-					if (!qSpiDirectMode) begin
-						wordsNum <= dataRegQSpi[21:19]+dataRegQSpi[17:16]+dataRegQSpi[15:12]+dataRegQSpi[10:9]+dataRegQSpi[7:6]+dataRegQSpi[4:3]+dataRegQSpi[2]+dataRegQSpi[1];
-					end else begin
-						wordsNum <= dataRegQSpi[16:1];
-					end
+					wordsNum <= dataRegQSpi[21:18]+dataRegQSpi[17]+dataRegQSpi[16:15]+dataRegQSpi[14:13]+dataRegQSpi[12:11];
 				end 
 			end
 		end else begin

src/src/PacketAnalyzer4Mosi/PacketAnalyzer4Mosi.v

@@ -65,7 +65,7 @@ wire [4:0] selector;
 //==========================================
 localparam [22:0] DECREMENT_CTRL_COLD_PART 	= 23'h40000;	//23'b000 0100 0000 0000 0000 0000
 localparam [22:0] DECREMENT_TFE_2_BYTES 	= 23'h20000;	//23'b000 0010 0000 0000 0000 0000
-localparam [22:0] DECREMENT_TFE_4_BYTES 	= 23'h10000;	//23'b000 0001 0000 0000 0000 0000
+localparam [22:0] DECREMENT_TFE_4_BYTES 	= 23'h8000;		//23'b000 0001 0000 0000 0000 0000
 localparam [22:0] DECREMENT_TFE_7_BYTES 	= 23'h2000;		//23'b000 0000 0010 0000 0000 0000
 localparam [22:0] DECREMENT_TFE_6_BYTES 	= 23'h800 ;		//23'b000 0000 0000 1000 0000 0000
 

src/src/Top/TopBochV3.v

@@ -3,7 +3,6 @@ module TopBochv3 #(
     parameter SSPIWORDWIDTH = 24
 )
 (
-input Clk_i,
 input Rst_i,
 
 input Sck_i,
@@ -61,9 +60,53 @@ wire valTfe6BytesDataToFifo;
 /* ClkGen wires */
 wire clk60;
 wire clk25;
+wire clk40;
 /* InitRst */
 wire initRst;
 
+/* Busy wires */
+wire busyMosi1;
+wire busyMosi4;
+/* Tfe Wrapper Spi lines */
+wire tfe2BytesCs;
+wire tfe2BytesSck;
+wire tfe2BytesMosi;
+/* 4 Bytes */
+wire tfe4BytesCs;
+wire tfe4BytesSck;
+wire tfe4BytesMosi;
+/* 6 Bytes */
+wire tfe6BytesCs;
+wire tfe6BytesSck;
+wire tfe6BytesMosi;
+/* 7 Bytes */
+wire tfe7BytesCs;
+wire tfe7BytesSck;
+wire tfe7BytesMosi;
+
+/* Busy SpiM devices */
+wire tfe2BytesSpiBusy;
+wire tfe4BytesSpiBusy;
+wire tfe6BytesSpiBusy;
+wire tfe7BytesSpiBusy;
+/* BusyForTfeDevs */
+wire busyForTfe2Bytes;
+wire busyForTfe4Bytes;
+wire busyForTfe6Bytes;
+wire busyForTfe7Bytes;
+
+/* Tfe6BytesFifoEmpty */
+wire tfe6BytesFifoEmpty;
+//***********************************************
+//	                ASSIGNMENTS
+//***********************************************
+assign CtrlCp2444v1Rst_o = Rst_i;
+
+assign busyForTfe2Bytes = tfe4BytesSpiBusy | tfe6BytesSpiBusy | tfe7BytesSpiBusy;
+assign busyForTfe4Bytes = tfe2BytesSpiBusy | tfe6BytesSpiBusy | tfe7BytesSpiBusy;
+assign busyForTfe6Bytes = tfe2BytesSpiBusy | tfe4BytesSpiBusy | tfe7BytesSpiBusy ;
+assign busyForTfe7Bytes = tfe2BytesSpiBusy | tfe4BytesSpiBusy | tfe6BytesSpiBusy | (!tfe6BytesFifoEmpty);
+
 //***********************************************
 //	                CODING
 //***********************************************
@@ -96,9 +139,31 @@ always @(*) begin
         TfeCs_o = Ss_i;
     end
     else begin 
-        TfeClk_o = 1'b0;
-        TfeMosi_o = 24'b0;
-        TfeCs_o = 1'b1;
+        if (!busyForTfe2Bytes) begin // Tfe2Bytes
+            TfeClk_o = tfe2BytesSck;
+            TfeMosi_o = tfe2BytesMosi;
+            TfeCs_o = tfe2BytesCs;
+        end
+        else if (!busyForTfe4Bytes) begin // Tfe4Bytes
+            TfeClk_o = tfe4BytesSck;
+            TfeMosi_o = tfe4BytesMosi;
+            TfeCs_o = tfe4BytesCs;
+        end
+        else if (!busyForTfe6Bytes) begin // Tfe6Bytes
+            TfeClk_o = tfe6BytesSck;
+            TfeMosi_o = tfe6BytesMosi;
+            TfeCs_o = tfe6BytesCs;
+        end
+        else if (!busyForTfe7Bytes) begin // Tfe7Bytes
+            TfeClk_o = tfe7BytesSck;
+            TfeMosi_o = tfe7BytesMosi;
+            TfeCs_o = tfe7BytesCs;
+        end
+        else begin 
+            TfeClk_o = 1'b0;
+            TfeMosi_o = 24'b0;
+            TfeCs_o = 1'b1;
+        end
     end
     if (flagDirectFlash) begin // Flash
         CtrlCp2444v1CsFlash_o = SsFlash_i;
@@ -111,6 +176,7 @@ end
 ClkGen ClkGen
 (
     .Clk60Mhz_o(clk60),
+    .Clk40Mhz_o(clk40),
     .Clk25Mhz_o(clk25)
 );
 
@@ -128,10 +194,11 @@ InterfaceArbiter#
 SpiSlaveArbiter
 (
     .Rst_i(Rst_i),
-    .Clk_i(Clk_i),
+    .Clk_i(clk60),
     .Sck_i(Sck_i),
     .Ss_i(Ss_i),
     .SsFlash_i(SsFlash_i),
+    .DirectFlagFlash_i(flagDirectFlash),
     .Mosi0_i(Mosi0_i),
     .Mosi1_i(Mosi1_io),
     .Mosi2_i(Mosi2_i),
@@ -178,16 +245,16 @@ PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 );
 
 CtrlCp2444Wrapper #(
-    .IN_WIDTH(WORDWIDTH),
+    .IN_WIDTH(24),
     .WR_NUM(1),
-    .OUT_WIDTH(WORDWIDTH)
+    .OUT_WIDTH(24)
 ) CtrlCp2444Wrapper
 (
     .WrClk_i                        (clk60),
     .RdClk_i                        (clk60),
     .Rst_i                          (initRst),
     .Data_i                         (spiData),
-    .Val_i                          (spiDataVal),
+    .Val_i                          (valCtrlColdPartDataToFifo),
     .Ss_o                           (CtrlCp2444v1Cs_o),
     .Sck_o                          (CtrlCp2444v1Sck_o),
     .Mosi0_o                        (CtrlCp2444v1Mosi0_o),
@@ -197,5 +264,81 @@ CtrlCp2444Wrapper #(
 
 );
 
+Tfe2BytesWrapper #(
+    .IN_WIDTH(24),
+    .WR_NUM(1),
+    .OUT_WIDTH(24),
+    .DATA_WIDTH(24)
+) Tfe2BytesWrapper
+(
+    .WrClk_i                        (clk60),
+    .RdClk_i                        (clk40),
+    .Rst_i                          (initRst),
+    .Data_i                         (spiData),
+    .Val_i                          (valTfe2BytesDataToFifo),
+    .SpiBusy_i                      (busyForTfe2Bytes),
+    .Tfe2BytesSpiBusy_o             (tfe2BytesSpiBusy),
+    .Ss_o                           (tfe2BytesCs),
+    .Sck_o                          (tfe2BytesSck),
+    .Mosi_o                         (tfe2BytesMosi)
+);
+
+Tfe4BytesWrapper #(
+    .IN_WIDTH(24),
+    .WR_NUM(2),
+    .OUT_WIDTH(32),
+    .DATA_WIDTH(32)
+) Tfe4BytesWrapper
+(
+    .WrClk_i                        (clk60),
+    .RdClk_i                        (clk40),
+    .Rst_i                          (initRst),
+    .Data_i                         (spiData),
+    .Val_i                          (valTfe4BytesDataToFifo),
+    .SpiBusy_i                      (busyForTfe4Bytes),
+    .Tfe4BytesSpiBusy_o             (tfe4BytesSpiBusy),
+    .Ss_o                           (tfe4BytesCs),
+    .Sck_o                          (tfe4BytesSck),
+    .Mosi_o                         (tfe4BytesMosi)
+);
+
+Tfe6BytesWrapper #(
+    .IN_WIDTH(24),
+    .WR_NUM(2),
+    .OUT_WIDTH(48),
+    .DATA_WIDTH(48)
+) Tfe6BytesWrapper
+(
+    .WrClk_i                        (clk60),
+    .RdClk_i                        (clk40),
+    .Rst_i                          (initRst),
+    .Data_i                         (spiData),
+    .Val_i                          (valTfe6BytesDataToFifo),
+    .SpiBusy_i                      (busyForTfe6Bytes),
+    .Tfe6BytesSpiBusy_o             (tfe6BytesSpiBusy),
+    .Tfe6BytesFifoEmpty_o           (tfe6BytesFifoEmpty),
+    .Ss_o                           (tfe6BytesCs),
+    .Sck_o                          (tfe6BytesSck),
+    .Mosi_o                         (tfe6BytesMosi)
+);
+
+Tfe7BytesWrapper #(
+    .IN_WIDTH(24),
+    .WR_NUM(3),
+    .OUT_WIDTH(56),
+    .DATA_WIDTH(56)
+) Tfe7BytesWrapper
+(
+    .WrClk_i                        (clk60),
+    .RdClk_i                        (clk40),
+    .Rst_i                          (initRst),
+    .Data_i                         (spiData),
+    .Val_i                          (valTfe7BytesDataToFifo),
+    .SpiBusy_i                      (busyForTfe7Bytes),
+    .Tfe7BytesSpiBusy_o             (tfe7BytesSpiBusy),
+    .Ss_o                           (tfe7BytesCs),
+    .Sck_o                          (tfe7BytesSck),
+    .Mosi_o                         (tfe7BytesMosi)
+);
 
 endmodule

src/src/Top/TopBochV3Tb.sv

@@ -2,7 +2,7 @@
 
 module TopBochV3Tb;
 
-
+parameter CLK_PERIOD = 8.13; // Clock period in ns
 //***********************************************
 //	            INPUTS
 //***********************************************
@@ -19,7 +19,7 @@ module TopBochV3Tb;
     logic Rst_i;
     logic Start_i;
     logic CPHA_i;
-    logic [31:0] SPIdata;
+    logic [23:0] SPIdata;
 	logic SpiDataVal_i;
     logic SELST_i;
     logic [1:0] WidthSel_i;
@@ -39,6 +39,7 @@ module TopBochV3Tb;
     wire Mosi3_o;
     wire Sck_o;
     wire Ss_o;
+    wire SsFlash_o;
     wire Val_o;
     wire anyFlag;
 
@@ -92,15 +93,6 @@ class Packet;
 endclass
 
 Packet pkt;
-
-//***********************************************
-//	            FUNCTIONS
-//***********************************************
-task automatic Packet::randomize();
-    data = $urandom_range(0, 2**24-1);
-    data32 = $urandom_range(0, 2**32-1);
-endtask
-
 //***********************************************
 //	      HEADERS FOR DEVICES - SB_TMSG
 //***********************************************
@@ -199,9 +191,9 @@ localparam [23:0] InitFlashHeader = {1'h0, DeviceIdFlash, FlashInitWordNum, 1'h1
 /* Word Numbers 4-MOSI */
 localparam [3:0] CtrlColdPartWordNum = 4'd7;
 localparam [0:0]     Tfe2bWordNum = 1'd1;
-localparam [0:0]      Tfe4bWordNum= 2'd2;
-localparam [0:0]      Tfe7bWordNum= 2'd3;
-localparam [0:0]      Tfe6bWordNum= 2'd2;
+localparam [1:0]      Tfe4bWordNum= 2'd2;
+localparam [1:0]      Tfe7bWordNum= 2'd3;
+localparam [1:0]      Tfe6bWordNum= 2'd2;
 /* Headers 4-MOSI */
 localparam [23:0] CtrlColdPartHeader = {1'h1, 1'h0, CtrlColdPartWordNum, 1'h0, 2'h0, 2'h0, 2'h0, 10'h0, 1'h1};
 localparam [23:0] Tfe2bHeader = {1'h1, 1'h0, 4'h0, Tfe2bWordNum, 2'h0, 2'h0, 2'h0, 10'h0, 1'h1};
@@ -234,20 +226,20 @@ localparam [23:0] AttCtrlP3Header = {1'h0, DeviceIdAttCtrlP3, AttCtrlP3WordNum,
 localparam [23:0] AttCtrlP4Header = {1'h0, DeviceIdAttCtrlP4, AttCtrlP4WordNum, 1'h1};
 localparam [23:0] CtrlCp2444v1GpioHeader = {1'h0, DeviceIdCtrlCp2444v1Gpio, CtrlCp2444v1GpioWordNum, 1'h1};
 /* Word Numbers */
-localparam [3:0] SwCtrlP1WordNum = 1'd1;
-localparam [3:0] AttCtrlP1WordNum = 1'd1;
-localparam [3:0] AttCtrlP2WordNum = 1'd1;
-localparam [3:0] AttCtrlP3WordNum = 1'd1;
-localparam [3:0] AttCtrlP4WordNum = 1'd1;
-localparam [3:0] CtrlCp2444v1GpioWordNum = 1'd1;
+localparam        SwCtrlP1QSpiWordNum = 1'd1;
+localparam        AttCtrlP1QSpiWordNum = 1'd1;
+localparam        AttCtrlP2QSpiWordNum = 1'd1;
+localparam        AttCtrlP3QSpiWordNum = 1'd1;
+localparam        AttCtrlP4QSpiWordNum = 1'd1;
+localparam        CtrlCp2444v1GpioQSpiWordNum = 1'd1;
 /* QSpi Headers */
-localparam [23:0] CtrlCp2444v1GpioHeader = {1'h1, CtrlCp2444v1GpioWordNum, 1'h0,1'h0,1'h0,1'h0,1'h0, 15'h0, 1'h1};
-localparam [23:0] SwCtrlP1Header = {1'h1, 1'h0, SwCtrlP1WordNum, 1'h0, 1'h0, 1'h0, 1'h0, 15'h0, 1'h1};
-localparam [23:0] AttCtrlP1Header = {1'h1, 1'h0, 1'h0, AttCtrlP1WordNum, 1'h0, 1'h0, 1'h0, 15'h0, 1'h1};
-localparam [23:0] AttCtrlP2Header = {1'h1, 1'h0, 1'h0, 1'h0, AttCtrlP2WordNum, 1'h0, 1'h0, 15'h0, 1'h1};
-localparam [23:0] AttCtrlP3Header = {1'h1, 1'h0, 1'h0, 1'h0, 1'h0, AttCtrlP3WordNum, 1'h0, 15'h0, 1'h1};
-localparam [23:0] AttCtrlP4Header = {1'h1, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, AttCtrlP4WordNum, 15'h0, 1'h1};
-localparam [23:0] AllDevCtrlCp2444v1QSpiHeader = {1'h1,CtrlCp2444v1GpioWordNum, SwCtrlP1WordNum, AttCtrlP1WordNum, AttCtrlP2WordNum, AttCtrlP3WordNum, AttCtrlP4WordNum, 15'h0, 1'h1};
+localparam [23:0] CtrlCp2444v1GpioQSpiHeader = {1'h1, CtrlCp2444v1GpioQSpiWordNum, 1'h0,1'h0,1'h0,1'h0,1'h0, 15'h0, 1'h1};
+localparam [23:0] SwCtrlP1QSpiHeader = {1'h1, 1'h0, SwCtrlP1QSpiWordNum, 1'h0, 1'h0, 1'h0, 1'h0, 15'h0, 1'h1};
+localparam [23:0] AttCtrlP1QSpiHeader = {1'h1, 1'h0, 1'h0, AttCtrlP1QSpiWordNum, 1'h0, 1'h0, 1'h0, 15'h0, 1'h1};
+localparam [23:0] AttCtrlP2QSpiHeader = {1'h1, 1'h0, 1'h0, 1'h0, AttCtrlP2QSpiWordNum, 1'h0, 1'h0, 15'h0, 1'h1};
+localparam [23:0] AttCtrlP3QSpiHeader = {1'h1, 1'h0, 1'h0, 1'h0, 1'h0, AttCtrlP3QSpiWordNum, 1'h0, 15'h0, 1'h1};
+localparam [23:0] AttCtrlP4QSpiHeader = {1'h1, 1'h0, 1'h0, 1'h0, 1'h0, 1'h0, AttCtrlP4QSpiWordNum, 15'h0, 1'h1};
+localparam [23:0] AllDevCtrlCp2444v1QSpiHeader = {1'h1,CtrlCp2444v1GpioQSpiWordNum, SwCtrlP1QSpiWordNum, AttCtrlP1QSpiWordNum, AttCtrlP2QSpiWordNum, AttCtrlP3QSpiWordNum, AttCtrlP4QSpiWordNum, 16'h0, 1'h1};
 
 
 //***********************************************
@@ -255,12 +247,15 @@ localparam [23:0] AllDevCtrlCp2444v1QSpiHeader = {1'h1,CtrlCp2444v1GpioWordNum,
 //***********************************************
 assign Val_o = (modeSel) ? valQ : valR;
 assign Sck_o = (modeSel) ? SckQ : SckR;
-assign Ss_o = (modeSel) ? SsQ : SsR;
+/* If the counter is 261 then the SsFlash should be active instead of Ss_o */
+assign Ss_o = (trCnt == 261) ? 1'b1 : (modeSel) ? SsQ : SsR;
+/* SsFlash_o should be active instead of Ss_o during the Flash transaction */
+assign SsFlash_o = (trCnt  == 261 ) ? 1'b0 : 1'b1;
 assign Mosi0_o = (modeSel) ? mosi0Q : mosi0R;
 assign Mosi1_io = (anyFlag) ? 1'bz : Mosi1_o;
 assign MisoLdLmx_i = 1'b1;
 
-assign emptyFlagTx = (trCnt > 260+QSpiBochv3TotalWordNum) ? 1'b1 : 1'b0;
+assign emptyFlagTx = (trCnt > 262 + QSpiBochv3TotalWordNum) ? 1'b1 : 1'b0;
 assign QSPITotalWordNum = LMXWordNum + DDSWordNum + POTWordNum + DACWordNum + ATTWordNum + ShRegWordNum + MaxWordNum + GPIOWordNum; 
 assign QSpiBochv3TotalWordNum = CtrlColdPartWordNum + Tfe2bWordNum + Tfe4bWordNum + Tfe7bWordNum + Tfe6bWordNum;
 assign QSpiCtrlCp2444v1TotalWordNum = CtrlCp2444v1GpioWordNum + SwCtrlP1WordNum + AttCtrlP1WordNum + AttCtrlP2WordNum + AttCtrlP3WordNum + AttCtrlP4WordNum;
@@ -313,16 +308,16 @@ initial begin
       #(700000-60) rstForFPGA = 1;
       #(CLK_PERIOD*74) rstForFPGA = 0;
       #(165000) Start_i = 1; // Start SPI transaction
-       wait (trCnt == 45) begin 
+       wait (trCnt == 262) begin 
             Start_i = 0;
         end
         #(CLK_PERIOD*100) 
         Start_i = 1; // Start SPI transaction
-      wait (trCnt == 70) begin 
-            Start_i = 0;
-        end
-        #(CLK_PERIOD*1000) 
-        Start_i = 1; // Start SPI transaction
+    //   wait (trCnt == 70) begin 
+    //         Start_i = 0;
+    //     end
+    //     #(CLK_PERIOD*1000) 
+    //     Start_i = 1; // Start SPI transaction
   end
 //***********************************************
 always_ff @(posedge currClk) begin
@@ -370,7 +365,7 @@ always_comb begin
         modeSel = 0;
     end
     else begin 
-        if (trCnt == 260) begin 
+        if (trCnt == 262) begin 
             modeSel = 1;
         end
     end
@@ -413,7 +408,7 @@ always_comb begin
         end
         /* Then the data for LMK_A */
         else if (trCnt > 0 && trCnt < 130) begin 
-            SPIdata = randData;
+            SPIdata = 24'haaaaaa;
         end
         /* Then the header for LMK_B */
         else if (trCnt == 130) begin 
@@ -421,15 +416,15 @@ always_comb begin
         end
         /* Then the data for LMK_B */
         else if (trCnt > 130 && trCnt < 260) begin 
-            SPIdata = randData;
+            SPIdata = 24'haaaaaa;
         end
         /* Then the header for the Flash */
         else if (trCnt == 260) begin 
             SPIdata = InitFlashHeader;
         end
         /* Then the data for the Flash but the SsFlash should be active instead of Ss_o */
-        else if (trCnt > 260 && trCnt < 261) begin 
-            SPIdata = randData;
+        else if (trCnt == 261) begin 
+            SPIdata = 24'haaaaaa;
         end
         /* Then the header for QSpi header */
         else if (trCnt == 262) begin 
@@ -440,14 +435,16 @@ always_comb begin
             SPIdata = AllDevCtrlCp2444v1QSpiHeader;
         end
         /* Then the data for QSpi */
-        else if (trCnt > 263 && trCnt < 260+QSpiBochv3TotalWordNum) begin
-            SPIdata = randData;
+        else if (trCnt > 263 && trCnt < 263+QSpiBochv3TotalWordNum) begin
+            SPIdata = 24'haaaaaa;
         end
     end
 end
 //***********************************************
 //	           DUT INSTANTIATION
 //***********************************************
+GSR GSR(.GSRI(1'b1));
+
 ExtSpiMEmul ExtSpiMEmul_inst (
         .Clk_i(currClk), 
         .Rst_i(Rst_i || modeSel), 
@@ -468,28 +465,67 @@ ExtSpiMEmul ExtSpiMEmul_inst (
         .Val_o(valR)
     );
 
-    ExtQspiMEmul ExtQspiMEmul_inst (
-        .Clk_i(currClk),
-        .Rst_i(Rst_i || !modeSel),
-        .Start_i(Start_i),
-        .ClockPhase_i(CPHA_i),
-        .EmptyFlag_i(emptyFlagTx),
-        .SpiData_i(SPIdata),
-        .SelSt_i(SELST_i),
-        .WidthSel_i(WidthSel_i),
-        .Lag_i(LAG_i),
-        .Lead_i(LEAD_i),
-        .EndianSel_i(EndianSel_i),
-        .Stop_i(6'h0),
-        .PulsePol_i(PulsePol_i),
-        .Mosi0_o(mosi0Q),
-        .Mosi1_o(Mosi1_o),
-        .Mosi2_o(Mosi2_o),
-        .Mosi3_o(Mosi3_o),
-        .Sck_o(SckQ),
-        .Ss_o(SsQ),
-        .Val_o(valQ)
-    );
+ExtQspiMEmul ExtQspiMEmul_inst (
+    .Clk_i(currClk),
+    .Rst_i(Rst_i || !modeSel),
+    .Start_i(Start_i),
+    .ClockPhase_i(CPHA_i),
+    .EmptyFlag_i(emptyFlagTx),
+    .SpiData_i(SPIdata),
+    .SelSt_i(SELST_i),
+    .WidthSel_i(WidthSel_i),
+    .Lag_i(LAG_i),
+    .Lead_i(LEAD_i),
+    .EndianSel_i(EndianSel_i),
+    .Stop_i(6'h0),
+    .PulsePol_i(PulsePol_i),
+    .Mosi0_o(mosi0Q),
+    .Mosi1_o(Mosi1_o),
+    .Mosi2_o(Mosi2_o),
+    .Mosi3_o(Mosi3_o),
+    .Sck_o(SckQ),
+    .Ss_o(SsQ),
+    .Val_o(valQ)
+);
+
+TopBochv3 TopBochV3_inst (
+    .Rst_i(rstForFPGA),
+    .Sck_i(Sck_o),
+    .Ss_i(Ss_o),
+    .SsFlash_i(SsFlash_o),
+    .Mosi0_i(Mosi0_o),
+    .Mosi1_io(Mosi1_o),
+    .Mosi2_i(Mosi2_o),
+    .Mosi3_i(Mosi3_o),
+
+    /* LMK_A */
+    .LmkAMosi_o(),
+    .LmkACs_o(),
+    .LmkASck_o(),
+    .LmkAMiso_i(),
+    /* LMK_B */
+    .LmkBMosi_o(),
+    .LmkBCs_o(),
+    .LmkBSck_o(),
+    .LmkBMiso_i(),
+    /* CtrlCp2444v1 */
+    .CtrlCp2444v1Mosi0_o(),
+    .CtrlCp2444v1Mosi1_o(),
+    .CtrlCp2444v1Mosi2_o(),
+    .CtrlCp2444v1Mosi3_o(),
+    .CtrlCp2444v1Sck_o(),
+    .CtrlCp2444v1Cs_o(),
+    .CtrlCp2444v1Rst_o(),
+    .CtrlCp2444v1Ld_i(),
+    /* HUB-1854 */
+    .TfeClk_o(),
+    .TfeCs_o(),
+    .TfeMosi_o(),
+    .TfeMiso_i()
+
+
+);
+
 
 
 

src/src/WrapFifoChain/FifoTfe6Bytes/FifoTfe6Bytes.v

@@ -0,0 +1,201 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Mon Nov 25 11:45:23 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7136)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+pkr25MEyl+V31OQ=
+`pragma protect end_protected
+module FifoTfe6Bytes (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [47:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [47:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoTfe6Bytes  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[47:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[47:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoTfe6Bytes */

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/FifoTfe6Bytes.vo

@@ -2,7 +2,7 @@
 //All rights reserved.
 //File Title: Post-PnR Simulation Model file
 //Tool Version: V1.9.9.03 (64-bit)
-//Created Time: Fri Nov 22 16:07:51 2024
+//Created Time: Mon Nov 25 11:45:24 2024
 
 `timescale 100 ps/100 ps
 module FifoTfe6Bytes(

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/FifoTfe6Bytes_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-UV9QN88C6/I5
 //Device: GW1N-9
-//Created Time: Fri Nov 22 16:07:51 2024
+//Created Time: Mon Nov 25 11:45:23 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/FifoTfe6Bytes.v

@@ -1,201 +0,0 @@
-//
-//Written by GowinSynthesis
-//Tool Version "V1.9.9.03 (64-bit)"
-//Fri Nov 22 16:07:51 2024
-
-//Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
-`timescale 100 ps/100 ps
-`pragma protect begin_protected
-`pragma protect version="2.3"
-`pragma protect author="default"
-`pragma protect author_info="default"
-`pragma protect encrypt_agent="GOWIN"
-`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
-
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
-`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
-`pragma protect key_block
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-
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=7136)
-`pragma protect data_keyowner="default-ip-vendor"
-`pragma protect data_keyname="default-ip-key"
-`pragma protect data_method="aes128-cfb"
-`pragma protect data_block
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-std/lcv1FqX4Wk4=
-`pragma protect end_protected
-module FifoTfe6Bytes (
-  Data,
-  Reset,
-  WrClk,
-  RdClk,
-  WrEn,
-  RdEn,
-  Q,
-  Empty,
-  Full
-)
-;
-input [47:0] Data;
-input Reset;
-input WrClk;
-input RdClk;
-input WrEn;
-input RdEn;
-output [47:0] Q;
-output Empty;
-output Full;
-wire VCC;
-wire GND;
-  \~fifo.FifoTfe6Bytes  fifo_inst (
-    .Reset(Reset),
-    .RdClk(RdClk),
-    .WrClk(WrClk),
-    .WrEn(WrEn),
-    .RdEn(RdEn),
-    .Data(Data[47:0]),
-    .Empty(Empty),
-    .Full(Full),
-    .Q(Q[47:0])
-);
-  VCC VCC_cZ (
-    .V(VCC)
-);
-  GND GND_cZ (
-    .G(GND)
-);
-  GSR GSR (
-    .GSRI(VCC) 
-);
-endmodule /* FifoTfe6Bytes */

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/FifoTfe6Bytes.vg

@@ -1,201 +0,0 @@
-//
-//Written by GowinSynthesis
-//Tool Version "V1.9.9.03 (64-bit)"
-//Fri Nov 22 16:07:51 2024
-
-//Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
-`timescale 100 ps/100 ps
-`pragma protect begin_protected
-`pragma protect version="2.3"
-`pragma protect author="default"
-`pragma protect author_info="default"
-`pragma protect encrypt_agent="GOWIN"
-`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
-
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
-`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
-`pragma protect key_block
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-
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=7136)
-`pragma protect data_keyowner="default-ip-vendor"
-`pragma protect data_keyname="default-ip-key"
-`pragma protect data_method="aes128-cfb"
-`pragma protect data_block
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-std/lcv1FqX4Wk4=
-`pragma protect end_protected
-module FifoTfe6Bytes (
-  Data,
-  Reset,
-  WrClk,
-  RdClk,
-  WrEn,
-  RdEn,
-  Q,
-  Empty,
-  Full
-)
-;
-input [47:0] Data;
-input Reset;
-input WrClk;
-input RdClk;
-input WrEn;
-input RdEn;
-output [47:0] Q;
-output Empty;
-output Full;
-wire VCC;
-wire GND;
-  \~fifo.FifoTfe6Bytes  fifo_inst (
-    .Reset(Reset),
-    .RdClk(RdClk),
-    .WrClk(WrClk),
-    .WrEn(WrEn),
-    .RdEn(RdEn),
-    .Data(Data[47:0]),
-    .Empty(Empty),
-    .Full(Full),
-    .Q(Q[47:0])
-);
-  VCC VCC_cZ (
-    .V(VCC)
-);
-  GND GND_cZ (
-    .G(GND)
-);
-  GSR GSR (
-    .GSRI(VCC) 
-);
-endmodule /* FifoTfe6Bytes */

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/FIFOHS.prj

@@ -10,7 +10,7 @@
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
         <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Gowin/Projects/BOCHv3_FPGA/src/src/WrapFifoChain/FifoTfe6Bytes/temp/FIFOHS"/>
         <Option type="output_file" value="FifoTfe6Bytes.vg"/>
         <Option type="output_template" value="FifoTfe6Bytes_tmp.v"/>
         <Option type="ram_balance" value="1"/>

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/FifoTfe6Bytes.log

@@ -39,7 +39,7 @@ WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe6Bytes\fifo_hs\temp\FIFOHS\FifoTfe6Bytes.vg" completed
-Generate template file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe6Bytes\fifo_hs\temp\FIFOHS\FifoTfe6Bytes_tmp.v" completed
-[100%] Generate report file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe6Bytes\fifo_hs\temp\FIFOHS\FifoTfe6Bytes_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe6Bytes\temp\FIFOHS\FifoTfe6Bytes.vg" completed
+Generate template file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe6Bytes\temp\FIFOHS\FifoTfe6Bytes_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\BOCHv3_FPGA\src\src\WrapFifoChain\FifoTfe6Bytes\temp\FIFOHS\FifoTfe6Bytes_syn.rpt.html" completed
 GowinSynthesis finish

src/src/WrapFifoChain/FifoTfe6Bytes/temp/FIFOHS/FifoTfe6Bytes.vg

@@ -0,0 +1,201 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 (64-bit)"
+//Mon Nov 25 11:45:23 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7136)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+pkr25MEyl+V31OQ=
+`pragma protect end_protected
+module FifoTfe6Bytes (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [47:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [47:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoTfe6Bytes  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[47:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[47:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoTfe6Bytes */

src/src/WrapFifoChain/FifoTfe6Bytes/fifo_hs/temp/FIFOHS/FifoTfe6Bytes_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-UV9QN88C6/I5
 //Device: GW1N-9
-//Created Time: Fri Nov 22 16:07:51 2024
+//Created Time: Mon Nov 25 11:45:23 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/WrapFifoChain/FifoTfe7Bytes/FifoTfe7Bytes.ipc

@@ -1,7 +1,7 @@
 [General]
 ipc_version=4
 file=FifoTfe7Bytes
-module=FifoTfe2Bytes
+module=FifoTfe7Bytes
 target_device=gw1n9-022
 type=fifo_hs
 version=1.0
@@ -10,7 +10,7 @@ version=1.0
 AlmostEmptyFlag=false
 AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
 AlmostFullFlag=false
-AlmostFullFlagItem=Full_Dual Threshold Constant Parameter
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
 BSRAM=true
 ControlledByRdEn=false
 ECCSelected=false

src/src/WrapFifoChain/FifoTfe7Bytes/FifoTfe7Bytes.v

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.03 (64-bit)"
-//Fri Nov 22 16:10:39 2024
+//Mon Nov 25 11:42:49 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,144 +17,144 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+ByxOM+vj5gLABIgxBUkfu2HIgQPc/ABFQK6Ong==
 
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=7104)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+16SQofIJi4J7tY2rlyVbiYdIzb5SF4bLwQwSAbZ0teUXhPV1
 `pragma protect end_protected
-module FifoTfe2Bytes (
+module FifoTfe7Bytes (
   Data,
   Reset,
   WrClk,
@@ -177,7 +177,7 @@ output Empty;
 output Full;
 wire VCC;
 wire GND;
-  \~fifo.FifoTfe2Bytes  fifo_inst (
+  \~fifo.FifoTfe7Bytes  fifo_inst (
     .Reset(Reset),
     .RdClk(RdClk),
     .WrClk(WrClk),
@@ -197,4 +197,4 @@ wire GND;
   GSR GSR (
     .GSRI(VCC) 
 );
-endmodule /* FifoTfe2Bytes */
+endmodule /* FifoTfe7Bytes */

src/src/WrapFifoChain/FifoTfe7Bytes/FifoTfe7Bytes.vo

@@ -2,10 +2,10 @@
 //All rights reserved.
 //File Title: Post-PnR Simulation Model file
 //Tool Version: V1.9.9.03 (64-bit)
-//Created Time: Fri Nov 22 16:10:39 2024
+//Created Time: Mon Nov 25 11:42:49 2024
 
 `timescale 100 ps/100 ps
-module FifoTfe2Bytes(
+module FifoTfe7Bytes(
 	Data,
 	Reset,
 	WrClk,

src/src/WrapFifoChain/FifoTfe7Bytes/FifoTfe7Bytes_tmp.v

@@ -4,12 +4,12 @@
 //Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-UV9QN88C6/I5
 //Device: GW1N-9
-//Created Time: Fri Nov 22 16:10:39 2024
+//Created Time: Mon Nov 25 11:42:49 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
-	FifoTfe2Bytes your_instance_name(
+	FifoTfe7Bytes your_instance_name(
 		.Data(Data), //input [55:0] Data
 		.Reset(Reset), //input Reset
 		.WrClk(WrClk), //input WrClk

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/FifoTfe7Bytes.log

@@ -11,10 +11,10 @@ Analyzing included file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\st
 Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
 Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
 Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'FifoTfe2Bytes'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module 'FifoTfe7Bytes'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
 Compiling module '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-NOTE  (EX0101) : Current top module is "FifoTfe2Bytes"
+NOTE  (EX0101) : Current top module is "FifoTfe7Bytes"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
 [10%] Optimizing Phase 0 completed

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/FifoTfe7Bytes.vg

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.03 (64-bit)"
-//Fri Nov 22 16:10:39 2024
+//Mon Nov 25 11:42:49 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,144 +17,144 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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 `pragma protect encoding=(enctype="base64", line_length=76, bytes=7104)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
-module FifoTfe2Bytes (
+module FifoTfe7Bytes (
   Data,
   Reset,
   WrClk,
@@ -177,7 +177,7 @@ output Empty;
 output Full;
 wire VCC;
 wire GND;
-  \~fifo.FifoTfe2Bytes  fifo_inst (
+  \~fifo.FifoTfe7Bytes  fifo_inst (
     .Reset(Reset),
     .RdClk(RdClk),
     .WrClk(WrClk),
@@ -197,4 +197,4 @@ wire GND;
   GSR GSR (
     .GSRI(VCC) 
 );
-endmodule /* FifoTfe2Bytes */
+endmodule /* FifoTfe7Bytes */

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/FifoTfe7Bytes_syn_resource.html

@@ -30,7 +30,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">FifoTfe2Bytes (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td class="label">FifoTfe7Bytes (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
 <td align = "center">19</td>
 <td align = "center">-</td>
 <td align = "center">18</td>

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/FifoTfe7Bytes_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoTfe2Bytes" Register="19" Lut="18" Bsram="2" T_Register="19(19)" T_Lut="18(18)" T_Bsram="2(2)"/>
+<Module name="FifoTfe7Bytes" Register="19" Lut="18" Bsram="2" T_Register="19(19)" T_Lut="18(18)" T_Bsram="2(2)"/>

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/FifoTfe7Bytes_tmp.v

@@ -4,12 +4,12 @@
 //Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-UV9QN88C6/I5
 //Device: GW1N-9
-//Created Time: Fri Nov 22 16:10:39 2024
+//Created Time: Mon Nov 25 11:42:49 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
-	FifoTfe2Bytes your_instance_name(
+	FifoTfe7Bytes your_instance_name(
 		.Data(Data), //input [55:0] Data
 		.Reset(Reset), //input Reset
 		.WrClk(WrClk), //input WrClk

src/src/WrapFifoChain/FifoTfe7Bytes/temp/FIFOHS/fifo_define.v

@@ -1,4 +1,4 @@
-`define module_name FifoTfe2Bytes
+`define module_name FifoTfe7Bytes
 `define EBR_BASED
 `define FWFT
 `define En_Reset

src/src/WrapFifoChain/Tfe2BytesWrapper.v

@@ -0,0 +1,83 @@
+module Tfe2BytesWrapper #(
+   	parameter 	IN_WIDTH = 24,
+	parameter 	WR_NUM = 1,
+    parameter	OUT_WIDTH = 24,
+    parameter	DATA_WIDTH = 24
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+	input 	SpiBusy_i,
+	output 	Tfe2BytesSpiBusy_o,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================  
+wire [OUT_WIDTH-1:0] dataFromFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromFifo;
+wire readEn;
+wire writeEn;
+wire valRdData;
+wire busySpiM;
+wire fifoFull;
+wire fifoEmpty;
+//==========================================================================//
+//									ASSIGNMENTS								//
+//==========================================================================//
+assign Tfe2BytesSpiBusy_o = busySpiM;
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(IN_WIDTH),
+	.WR_NUM			(WR_NUM),
+	.OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrlTfe2Bytes
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiM | SpiBusy_i ),
+	.FifoFull_i		(fifoFull),
+	.FifoEmpty_i	(fifoEmpty),
+	.Data_o			(dataFromFifoCtrl),
+	.ReadEn_o		(readEn),
+	.WriteEn_o		(writeEn),
+	.ValRdData_o	(valRdData)
+);
+
+FifoTfe2Bytes FifoTfe2Bytes (
+	.Data	(dataFromFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEn),
+	.RdEn	(readEn),
+	.Full	(fifoFull),
+	.Empty	(fifoEmpty),
+	.Q		(dataFromFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(DATA_WIDTH)
+)SpiMTfe2Bytes(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdData),
+	.SpiData_i	(dataFromFifo),
+	.Busy_o	    (busySpiM),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/WrapFifoChain/Tfe4BytesWrapper.v

@@ -0,0 +1,83 @@
+module Tfe4BytesWrapper #(
+   	parameter	IN_WIDTH = 24,
+    parameter 	WR_NUM = 	2,
+    parameter	OUT_WIDTH = 32,
+    parameter	DATA_WIDTH = 32
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+	input 	SpiBusy_i,
+	output 	Tfe4BytesSpiBusy_o,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================  
+wire [OUT_WIDTH-1:0] dataFromFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromFifo;
+wire readEn;
+wire writeEn;
+wire valRdData;
+wire busySpiM;
+wire fifoFull;
+wire fifoEmpty;
+//==========================================================================//
+//									ASSIGNMENTS								//
+//==========================================================================//
+assign Tfe4BytesSpiBusy_o = busySpiM;
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(IN_WIDTH),
+	.WR_NUM			(WR_NUM),
+	.OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrlTfe4Bytes
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiM | SpiBusy_i),
+	.FifoFull_i		(fifoFull),
+	.FifoEmpty_i	(fifoEmpty),
+	.Data_o			(dataFromFifoCtrl),
+	.ReadEn_o		(readEn),
+	.WriteEn_o		(writeEn),
+	.ValRdData_o	(valRdData)
+);
+
+FifoTfe4Bytes FifoTfe4Bytes (
+	.Data	(dataFromFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEn),
+	.RdEn	(readEn),
+	.Full	(fifoFull),
+	.Empty	(fifoEmpty),
+	.Q		(dataFromFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(DATA_WIDTH)
+)SpiMTfe4Bytes(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdData),
+	.SpiData_i	(dataFromFifo),
+	.Busy_o	    (busySpiM),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/WrapFifoChain/Tfe6BytesWrapper.v

@@ -0,0 +1,85 @@
+module Tfe6BytesWrapper #(
+   	parameter	IN_WIDTH = 24,
+    parameter	WR_NUM = 2,
+    parameter	OUT_WIDTH = 48,
+    parameter	DATA_WIDTH = 48
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+	input	SpiBusy_i,
+	output 	Tfe6BytesSpiBusy_o,
+	output	Tfe6BytesFifoEmpty_o,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================  
+wire [OUT_WIDTH-1:0] dataFromFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromFifo;
+wire readEn;
+wire writeEn;
+wire valRdData;
+wire busySpiM;
+wire fifoFull;
+wire fifoEmpty;
+//==========================================================================//
+//									ASSIGNMENTS								//
+//==========================================================================//
+assign Tfe6BytesSpiBusy_o = busySpiM;
+assign Tfe6BytesFifoEmpty_o = fifoEmpty;
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(IN_WIDTH),
+	.WR_NUM			(WR_NUM),
+	.OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrlTfe6Bytes
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiM | SpiBusy_i ),
+	.FifoFull_i		(fifoFull),
+	.FifoEmpty_i	(fifoEmpty),
+	.Data_o			(dataFromFifoCtrl),
+	.ReadEn_o		(readEn),
+	.WriteEn_o		(writeEn),
+	.ValRdData_o	(valRdData)
+);
+
+FifoTfe6Bytes FifoTfe6Bytes (
+	.Data	(dataFromFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEn),
+	.RdEn	(readEn),
+	.Full	(fifoFull),
+	.Empty	(fifoEmpty),
+	.Q		(dataFromFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(DATA_WIDTH)
+)SpiMTfe6Bytes(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdData),
+	.SpiData_i	(dataFromFifo),
+	.Busy_o	    (busySpiM),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/WrapFifoChain/Tfe7BytesWrapper.v

@@ -0,0 +1,83 @@
+module Tfe7BytesWrapper #(
+   	parameter	IN_WIDTH = 24,
+    parameter	WR_NUM = 3,
+    parameter	OUT_WIDTH = 56,
+    parameter	DATA_WIDTH = 56
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+	input	SpiBusy_i,
+	output 	Tfe7BytesSpiBusy_o,
+	
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================  
+wire [OUT_WIDTH-1:0] dataFromFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromFifo;
+wire readEn;
+wire writeEn;
+wire valRdData;
+wire busySpiM;
+wire fifoFull;
+wire fifoEmpty;
+//==========================================================================//
+//									ASSIGNMENTS								//
+//==========================================================================//
+assign Tfe7BytesSpiBusy_o = busySpiM;
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(IN_WIDTH),
+	.WR_NUM			(WR_NUM),
+	.OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrlTfe7Bytes
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiM | SpiBusy_i ),
+	.FifoFull_i		(fifoFull),
+	.FifoEmpty_i	(fifoEmpty),
+	.Data_o			(dataFromFifoCtrl),
+	.ReadEn_o		(readEn),
+	.WriteEn_o		(writeEn),
+	.ValRdData_o	(valRdData)
+);
+
+FifoTfe7Bytes FifoTfe7Bytes (
+	.Data	(dataFromFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEn),
+	.RdEn	(readEn),
+	.Full	(fifoFull),
+	.Empty	(fifoEmpty),
+	.Q		(dataFromFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(DATA_WIDTH)
+)SpiMTfe7Bytes(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdData),
+	.SpiData_i	(dataFromFifo),
+	.Busy_o	    (busySpiM),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule