Создание репозитория

script/recreate_vna_pcie.tcl

@@ -0,0 +1,860 @@
+#*****************************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# recreate_vna_pcie.tcl: Tcl script for re-creating project 'VNA_PCIE_PROJ'
+#
+# Generated by Vivado on Tue Oct 08 17:41:06 +0700 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (recreate_vna_pcie.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    "c:/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/pcie1234/pcie1234.xci"
+#    "c:/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"
+#    "C:/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp"
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/ActivePortSelector.v"
+#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/AdcCalibration.v"
+#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/ComplPrng.v"
+#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/CordicNco.v"
+#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/CordicRotation.v"
+#    "C:/VNA_PCIE_REPO/src/src/DitherGen/DitherGenv2.v"
+#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/DspPipeline.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/EP_MEM.v"
+#    "C:/VNA_PCIE_REPO/src/src/Math/FpCustomMultiplier.v"
+#    "C:/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControl.v"
+#    "C:/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControlWrapper.v"
+#    "C:/VNA_PCIE_REPO/src/src/InitRst/InitRst.v"
+#    "C:/VNA_PCIE_REPO/src/src/Top/IntermediateLogic.v"
+#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/InternalDsp.v"
+#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/MeasCtrlModule.v"
+#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/MeasStartEventGen.v"
+#    "C:/VNA_PCIE_REPO/src/src/Math/MultModule.v"
+#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/Mux.v"
+#    "C:/VNA_PCIE_REPO/src/src/Math/MyIntToFp.v"
+#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/NcoRstGen.v"
+#    "C:/VNA_PCIE_REPO/src/src/GainOverloadControl/OverloadDetect.v"
+#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/PGenRstGenerator.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP_MEM_ACCESS.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO_RX_ENGINE.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TO_CTRL.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TX_ENGINE.v"
+#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/PulseGen.v"
+#    "C:/VNA_PCIE_REPO/src/src/RegMap/RegMap.v"
+#    "C:/VNA_PCIE_REPO/src/src/Top/S5443Top.v"
+#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/SampleStrobeGenRstDemux.v"
+#    "C:/VNA_PCIE_REPO/src/src/Math/SimpleMult.v"
+#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/StartAfterGainSel.v"
+#    "C:/VNA_PCIE_REPO/src/src/Math/SumAcc.v"
+#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/TrigInt2Mux.v"
+#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/WinParameters.v"
+#    "C:/VNA_PCIE_REPO/src/src/InternalDsp/Win_calc.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_pipe_clock.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_support.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie_app_7x.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_ep_7x.v"
+#    "C:/VNA_PCIE_REPO/src/src/Top/PciVnaEmulTop.v"
+#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/AdcSync.v"
+#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/delay_controller_wrap.v"
+#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"
+#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"
+#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"
+#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/top5x2_7to1_sdr_rx.v"
+#    "C:/VNA_PCIE_REPO/src/src/AdcDataRx/AdcDataInterface.v"
+#    "C:/VNA_PCIE_REPO/src/src/ClkGen/Clk200Gen.v"
+#    "C:/VNA_PCIE_REPO/src/src/ExtDspInterface/DspInterface.v"
+#    "C:/VNA_PCIE_REPO/src/src/ExtDspInterface/DspPpiOut.v"
+#    "C:/VNA_PCIE_REPO/src/src/MeasDataFifo/FifoController.v"
+#    "C:/VNA_PCIE_REPO/src/src/Top/IntermediateLogicTb.v"
+#    "C:/VNA_PCIE_REPO/src/src/MeasDataFifo/MeasDataFifoWrapper.v"
+#    "C:/VNA_PCIE_REPO/src/src/PulseMeas/PulseGenNew.v"
+#    "C:/VNA_PCIE_REPO/src/src/Sim/S5443TopPulseProfileTb.v"
+#    "C:/VNA_PCIE_REPO/src/src/Sim/S5443TopSimpleMeasTb.v"
+#    "C:/VNA_PCIE_REPO/src/src/ExtDspInterface/SlaveSpi.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/board_common.vh"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pipe_interconnect.vh"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/board.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_cfg.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_com.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_pl.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_rx.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/tests.vh"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/sample_tests1.vh"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_tx.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_gt_top_pipe_mode.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie_2_1_rport_7x.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/pcie_axi_trn_bridge.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen_ds.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/xil_sig2pipe.v"
+#    "C:/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_rport_7x.v"
+#    "C:/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"
+#
+#*****************************************************************************************
+
+# Check file required for this script exists
+proc checkRequiredFiles { origin_dir} {
+  set status true
+  set files [list \
+ "[file normalize "$origin_dir/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/pcie1234/pcie1234.xci"]"\
+ "[file normalize "$origin_dir/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci"]"\
+ "[file normalize "$origin_dir/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp"]"\
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find local file $ifile "
+      set status false
+    }
+  }
+
+  set files [list \
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/ActivePortSelector.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/AdcCalibration.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/ComplPrng.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/CordicNco.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/CordicRotation.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/DitherGen/DitherGenv2.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/DspPipeline.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/EP_MEM.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Math/FpCustomMultiplier.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControl.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControlWrapper.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InitRst/InitRst.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Top/IntermediateLogic.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/InternalDsp.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/MeasCtrlModule.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/MeasStartEventGen.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Math/MultModule.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/Mux.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Math/MyIntToFp.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/NcoRstGen.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/GainOverloadControl/OverloadDetect.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/PGenRstGenerator.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP_MEM_ACCESS.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO_RX_ENGINE.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TO_CTRL.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TX_ENGINE.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/PulseGen.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/RegMap/RegMap.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Top/S5443Top.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/SampleStrobeGenRstDemux.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Math/SimpleMult.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/StartAfterGainSel.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Math/SumAcc.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/TrigInt2Mux.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/WinParameters.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/InternalDsp/Win_calc.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_pipe_clock.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_support.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie_app_7x.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_ep_7x.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Top/PciVnaEmulTop.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/AdcSync.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/delay_controller_wrap.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/top5x2_7to1_sdr_rx.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/AdcDataRx/AdcDataInterface.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/ClkGen/Clk200Gen.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/ExtDspInterface/DspInterface.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/ExtDspInterface/DspPpiOut.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/MeasDataFifo/FifoController.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Top/IntermediateLogicTb.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/MeasDataFifo/MeasDataFifoWrapper.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PulseMeas/PulseGenNew.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Sim/S5443TopPulseProfileTb.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/Sim/S5443TopSimpleMeasTb.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/ExtDspInterface/SlaveSpi.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/board_common.vh"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pipe_interconnect.vh"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/board.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_cfg.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_com.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_pl.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_rx.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/tests.vh"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/sample_tests1.vh"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_tx.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_gt_top_pipe_mode.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie_2_1_rport_7x.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pcie_axi_trn_bridge.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen_ds.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/xil_sig2pipe.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_rport_7x.v"]"\
+ "[file normalize "$origin_dir/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"]"\
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find remote file $ifile "
+      set status false
+    }
+  }
+
+  return $status
+}
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "C:/"
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "VNA_PCIE_PROJ"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "recreate_vna_pcie.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/Projects/VNA_PCIE_PROJ"]"
+
+# Check for paths and files needed for project creation
+set validate_required 0
+if { $validate_required } {
+  if { [checkRequiredFiles $origin_dir] } {
+    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
+  } else {
+    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
+    return
+  }
+}
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a100tfgg484-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Reconstruct message rules
+# None
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_resource_estimation" -value "0" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "revised_directory_structure" -value "1" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "sim_compile_state" -value "1" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/ActivePortSelector.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/AdcCalibration.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/ComplPrng.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/CordicNco.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/CordicRotation.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/DitherGen/DitherGenv2.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/DspPipeline.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/EP_MEM.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Math/FpCustomMultiplier.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControl.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/GainOverloadControl/GainControlWrapper.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InitRst/InitRst.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Top/IntermediateLogic.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/InternalDsp.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/MeasCtrlModule.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/MeasStartEventGen.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Math/MultModule.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/Mux.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Math/MyIntToFp.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/NcoRstGen.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/GainOverloadControl/OverloadDetect.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/PGenRstGenerator.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO_EP_MEM_ACCESS.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO_RX_ENGINE.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TO_CTRL.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/PIO_TX_ENGINE.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/PulseGen.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/RegMap/RegMap.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Top/S5443Top.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/SampleStrobeGenRstDemux.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Math/SimpleMult.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/StartAfterGainSel.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Math/SumAcc.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/TrigInt2Mux.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/WinParameters.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/InternalDsp/Win_calc.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_pipe_clock.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_support.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie_app_7x.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_ep_7x.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Top/PciVnaEmulTop.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/AdcSync.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/delay_controller_wrap.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/top5x2_7to1_sdr_rx.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/AdcDataRx/AdcDataInterface.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/ClkGen/Clk200Gen.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/ExtDspInterface/DspInterface.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/ExtDspInterface/DspPpiOut.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/MeasDataFifo/FifoController.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Top/IntermediateLogicTb.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/MeasDataFifo/MeasDataFifoWrapper.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PulseMeas/PulseGenNew.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Sim/S5443TopPulseProfileTb.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/Sim/S5443TopSimpleMeasTb.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/ExtDspInterface/SlaveSpi.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/board_common.vh"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pipe_interconnect.vh"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/board.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_cfg.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_com.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_pl.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_rx.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/tests.vh"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/sample_tests1.vh"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_usrapp_tx.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie1234_gt_top_pipe_mode.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie_2_1_rport_7x.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/pcie_axi_trn_bridge.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/sys_clk_gen_ds.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/xil_sig2pipe.v"] \
+ [file normalize "${origin_dir}/VNA_PCIE_REPO/src/src/PCIeImports/xilinx_pcie_2_1_rport_7x.v"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sources_1' fileset file properties for remote files
+set file "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/board_common.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pipe_interconnect.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/pci_exp_expect_tasks.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/tests.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "$origin_dir/VNA_PCIE_REPO/src/src/PCIeImports/sample_tests1.vh"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
+set_property -name "top" -value "PciVnaEmulTop" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/pcie1234/pcie1234.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "pcie1234/pcie1234.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/sources_1/ip/ClkPllSysTo125/ClkPllSysTo125.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "ClkPllSysTo125/ClkPllSysTo125.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/VNA_PCIE_REPO/src/consrtrs/xilinx_pcie_7x_ep_x1g1.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7a100tfgg484-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "top" -value "AdcDataInterface" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/Projects/VNA_PCIE_PROJ/VNA_PCIE_PROJ.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp" ]\
+]
+set imported_files ""
+foreach f $files {
+  lappend imported_files [import_files -fileset utils_1 $f]
+}
+
+# Set 'utils_1' fileset file properties for remote files
+# None
+
+# Set 'utils_1' fileset file properties for local files
+set file "synth_1/PciVnaEmulTop.dcp"
+set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
+set_property -name "netlist_only" -value "0" -objects $file_obj
+
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+set idrFlowPropertiesConstraints ""
+catch {
+ set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints]
+ set_param runs.disableIDRFlowPropertyConstraints 1
+}
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a100tfgg484-2 -flow {Vivado Synthesis 2024} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2024" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "incremental_checkpoint" -value "$proj_dir/${_xil_proj_name_}.srcs/utils_1/imports/synth_1/PciVnaEmulTop.dcp" -objects $obj
+set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+set_property -name "steps.synth_design.args.flatten_hierarchy" -value "none" -objects $obj
+set_property -name "steps.synth_design.args.gated_clock_conversion" -value "auto" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a100tfgg484-2 -flow {Vivado Implementation 2024} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2024" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+catch {
+ if { $idrFlowPropertiesConstraints != {} } {
+   set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints
+ }
+}
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

src/src/AdcDataRx/AdcDataInterface.v

@@ -0,0 +1,208 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    11:47:44 07/11/2019 
+// design name: 
+// module name:    adc_data_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	AdcDataInterface	
+#(	
+	parameter	AdcDataWidth	=	14,
+	parameter	ChNum			=	4,
+	parameter	Ratio			=	8
+)
+(
+	input	Clk_i,
+	input	RefClk_i,
+	input	Locked_i,
+	input	Rst_i,
+	
+	input	[AdcDataWidth-1:0]	testAdc,
+		
+	input	Adc1FclkP_i,		
+    input	Adc1FclkN_i,		
+	
+    input	Adc1DataDa0P_i,
+	input	Adc1DataDa0N_i,
+    input	Adc1DataDa1P_i,
+    input	Adc1DataDa1N_i,
+	
+	input	Adc1DataDb0P_i,
+    input	Adc1DataDb0N_i,
+    input	Adc1DataDb1P_i,
+    input	Adc1DataDb1N_i,
+		
+	input	Adc2FclkP_i,		
+    input	Adc2FclkN_i,		
+	
+	input	Adc2DataDa0P_i,
+    input	Adc2DataDa0N_i,
+    input	Adc2DataDa1P_i,
+    input	Adc2DataDa1N_i,
+	
+	input	Adc2DataDb0P_i,
+    input	Adc2DataDb0N_i,
+    input	Adc2DataDb1P_i,
+    input	Adc2DataDb1N_i,
+	
+	output	[AdcDataWidth-1:0]	Adc1ChT1Data_o,
+	output	[AdcDataWidth-1:0]	Adc1ChR1Data_o,
+	output	[AdcDataWidth-1:0]	Adc2ChR2Data_o,
+	output	[AdcDataWidth-1:0]	Adc2ChT2Data_o
+);
+//================================================================================
+//  reg/wire
+//================================================================================	
+	wire    [ChNum-1:0]    	adc1P;
+    wire    [ChNum-1:0]    	adc1N;
+    wire    [ChNum-1:0]    	adc2P;
+    wire    [ChNum-1:0]    	adc2N;
+	
+	reg	[AdcDataWidth*2-1:0]	adc1DataSyncPipe	[2:0];
+	reg	[AdcDataWidth*2-1:0]	adc2DataSyncPipe	[2:0];
+
+	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc1Dout;
+	wire	[(ChNum-2)*AdcDataWidth-1:0]	adc2Dout;
+	
+	wire	[AdcDataWidth-1:0]	adc1ChAData;
+	wire	[AdcDataWidth-1:0]	adc1ChBData;
+	wire	[AdcDataWidth-1:0]	adc2ChAData;
+	wire	[AdcDataWidth-1:0]	adc2ChBData;	
+	
+	reg		[AdcDataWidth-1:0]	adc1ChT1DataSyncR;	
+	reg		[AdcDataWidth-1:0]	adc1ChR1DataSyncR;
+	reg		[AdcDataWidth-1:0]	adc2ChT2DataSyncR;
+	reg		[AdcDataWidth-1:0]	adc2ChR2DataSyncR;
+	
+	wire	[AdcDataWidth-1:0]	adc1ChT1DataSync;	
+	wire	[AdcDataWidth-1:0]	adc1ChR1DataSync;
+	wire	[AdcDataWidth-1:0]	adc2ChT2DataSync;
+	wire	[AdcDataWidth-1:0]	adc2ChR2DataSync;
+	
+	assign  adc1P	= {Adc1DataDb1P_i, Adc1DataDb0P_i, Adc1DataDa1P_i, Adc1DataDa0P_i};
+	assign  adc1N	= {Adc1DataDb1N_i, Adc1DataDb0N_i, Adc1DataDa1N_i, Adc1DataDa0N_i};
+	
+	assign  adc2P	= {Adc2DataDb1P_i, Adc2DataDb0P_i, Adc2DataDa1P_i, Adc2DataDa0P_i};
+	assign  adc2N	= {Adc2DataDb1N_i, Adc2DataDb0N_i, Adc2DataDa1N_i, Adc2DataDa0N_i};
+	
+	// assign	Adc1ChT1Data_o	=	adc1DataSyncPipe[2][AdcDataWidth*2-1-:14];
+	// assign	Adc1ChR1Data_o	=	adc1DataSyncPipe[2][AdcDataWidth-1-:14];
+	// assign	Adc2ChR2Data_o	=	adc2DataSyncPipe[2][AdcDataWidth*2-1-:14];
+	// assign	Adc2ChT2Data_o	=	adc2DataSyncPipe[2][AdcDataWidth-1-:14];
+	
+	assign	Adc1ChT1Data_o	=	adc1ChT1DataSync;
+	assign	Adc1ChR1Data_o	=	adc1ChR1DataSync;
+	assign	Adc2ChR2Data_o	=	adc2ChR2DataSync;
+	assign	Adc2ChT2Data_o	=	adc2ChT2DataSync;
+	
+	wire	idly_reset_int;
+	wire	rx_reset;
+	wire	rx2_cmt_locked;
+	wire	Adc1RxClk;
+	wire	Adc2RxClk;
+	
+//================================================================================
+//  instantiations
+//================================================================================
+
+top5x2_7to1_sdr_rx	Adc1Rx
+(                  
+	.reset		(Rst_i),
+	.refclkin	(RefClk_i),
+	.Locked_i	(Locked_i),
+	.clkin1_p	(Adc1FclkP_i),
+	.clkin1_n	(Adc1FclkN_i),	
+	.datain1_p	(adc1P),	
+	.datain1_n	(adc1N),	
+	.clkin2_p	(),	
+	.clkin2_n	(),	
+	.datain2_p	(),	
+	.datain2_n	(),	
+	.dummy		(),
+	.dout		(adc1Dout),
+	.DivClk_o	(Adc1RxClk)
+);
+
+top5x2_7to1_sdr_rx	Adc2Rx
+(                  
+	.reset		(Rst_i),
+	.refclkin	(RefClk_i),
+	.Locked_i	(Locked_i),
+	.clkin1_p	(Adc2FclkP_i),
+	.clkin1_n	(Adc2FclkN_i),	
+	.datain1_p	(adc2P),	
+	.datain1_n	(adc2N),	
+	.clkin2_p	(),	
+	.clkin2_n	(),	
+	.datain2_p	(),	
+	.datain2_n	(),	
+	.dummy		(),
+	.dout		(adc2Dout),
+	.DivClk_o	(Adc2RxClk)
+);
+
+
+AdcSync Adc1Sync
+(
+    .Clk_i	(Clk_i),
+	.Rst_i	(Rst_i),
+	
+    .Data_i	(adc1Dout),
+	
+	.Data_o	({adc1ChT1DataSync, adc1ChR1DataSync})
+);
+
+AdcSync Adc2Sync
+(
+    .Clk_i	(Clk_i),
+	.Rst_i	(Rst_i),
+	
+    .Data_i	(adc2Dout),
+	
+	.Data_o	({adc2ChR2DataSync, adc2ChT2DataSync})
+);
+
+// AdcSyncFifo	adc1SyncFifo	(
+	// .rst		(Rst_i),
+	// .wr_clk		(Adc1RxClk),	
+	// .rd_clk		(Clk_i),
+	// .din		(adc1Dout),
+	// .din		({testAdc,testAdc}),
+	// .wr_en		(1'b1),
+	// .rd_en		(1'b1),
+	// .dout		({adc1ChT1DataSync, adc1ChR1DataSync}),
+	// .full		(),
+	// .empty		()
+// );
+
+// AdcSyncFifo	adc2SyncFifo	(
+	// .rst		(Rst_i),
+	// .wr_clk		(Adc2RxClk),	
+	// .rd_clk		(Clk_i),
+	// .din		(adc2Dout),
+	// .wr_en		(1'b1),
+	// .rd_en		(1'b1),
+	// .dout		({adc2ChR2DataSync, adc2ChT2DataSync}),
+	// .full		(),
+	// .empty		()
+// );
+endmodule
+
+
+
+
+
+

src/src/AdcDataRx/AdcSync.v

@@ -0,0 +1,41 @@
+module AdcSync 
+#(	
+	parameter	AdcDataWidth	=	14
+)
+(
+    input	Clk_i,
+	input	Rst_i,
+	
+    input	[AdcDataWidth*2-1:0]	Data_i,
+	
+	output	[AdcDataWidth*2-1:0]	Data_o
+);
+
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+	reg	[AdcDataWidth*2-1:0]	adcDataSyncPipe	[2:0];
+	integer i;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	Data_o	=	adcDataSyncPipe[2];
+//================================================================================
+//  CODING
+//================================================================================
+
+
+always @(posedge Clk_i) begin
+	if	(!Rst_i)	begin
+		adcDataSyncPipe[0]  <= Data_i;
+		for(i=1; i<3; i=i+1) begin
+			adcDataSyncPipe	[i]<=adcDataSyncPipe[i-1];
+		end
+	end	else	begin
+		adcDataSyncPipe	[i]	<=	0;
+	end
+end
+
+endmodule

src/src/AdcDataRx/delay_controller_wrap.v

@@ -0,0 +1,410 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: delay_controller_wrap.v
+//  /   /        Date Last Modified: 21JAN2015
+// /___/   /\    Date Created: 8JAN2013
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7 Series
+//Purpose:  	Controls delays on a per-bit basis
+//		Number of bits from each seres set via an attribute
+//
+//Reference:	XAPP585
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.2 - Updated format (brandond)
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module delay_controller_wrap (m_datain, s_datain, enable_phase_detector, enable_monitor, reset, clk, c_delay_in, m_delay_out, s_delay_out, data_out, bt_val, results, m_delay_1hot, del_mech) ;
+
+parameter integer 	S = 4 ;   			// Set the number of bits
+
+input		[S-1:0]	m_datain ;			// Inputs from master serdes
+input		[S-1:0]	s_datain ;			// Inputs from slave serdes
+input			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the eye monitoring logic when high
+input			reset ;				// Reset line synchronous to clk 
+input			clk ;				// Global/Regional clock 
+input		[4:0]	c_delay_in ;			// delay value found on clock line
+output		[4:0]	m_delay_out ;			// Master delay control value
+output		[4:0]	s_delay_out ;			// Master delay control value
+output	reg	[S-1:0]	data_out ;			// Output data
+input		[4:0]	bt_val ;			// Calculated bit time value for slave devices
+output	reg	[31:0]	results ;			// eye monitor result data	
+output	reg	[31:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector	
+input			del_mech ;			// changes delay mechanism slightly at higher bit rates
+
+reg	[S-1:0]		mdataouta ;		
+reg			mdataoutb ;		
+reg	[S-1:0]		mdataoutc ;		
+reg	[S-1:0]		sdataouta ;		
+reg			sdataoutb ;		
+reg	[S-1:0]		sdataoutc ;		
+reg			s_ovflw ; 		
+reg	[1:0]		m_delay_mux ;				
+reg	[1:0]		s_delay_mux ;				
+reg			data_mux ;		
+reg			dec_run ;			
+reg			inc_run ;			
+reg			eye_run ;			
+reg	[4:0]		s_state ;					
+reg	[5:0]		pdcount ;					
+reg	[4:0]		m_delay_val_int ;	
+reg	[4:0]		s_delay_val_int ;	
+reg	[4:0]		s_delay_val_eye ;	
+reg			meq_max	;		
+reg			meq_min	;		
+reg			pd_max	;		
+reg			pd_min	;		
+reg			delay_change ;		
+wire	[S-1:0]		all_high ;		
+wire	[S-1:0]		all_low	;		
+wire	[7:0]		msxoria	;		
+wire	[7:0]		msxorda	;		
+reg	[1:0]		action	;		
+reg	[1:0]		msxor_cti ;
+reg	[1:0]		msxor_ctd ;
+reg	[1:0]		msxor_ctix ;
+reg	[1:0]		msxor_ctdx ;
+wire	[2:0]		msxor_ctiy ;
+wire	[2:0]		msxor_ctdy ;
+reg	[7:0]		match ;	
+reg	[31:0]		shifter ;	
+reg	[7:0]		pd_hold ;	
+	
+assign m_delay_out = m_delay_val_int ;
+assign s_delay_out = s_delay_val_int ;
+genvar i ;
+
+generate
+
+for (i = 0 ; i <= S-2 ; i = i+1) begin : loop0
+
+assign msxoria[i+1] = ((~s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] & ~sdataouta[i])   | (~mdataouta[i] & mdataouta[i+1] &  sdataouta[i]))) | 
+	               ( s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] & ~sdataouta[i+1]) | (~mdataouta[i] & mdataouta[i+1] &  sdataouta[i+1])))) ; // early bits                   
+assign msxorda[i+1] = ((~s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] &  sdataouta[i])   | (~mdataouta[i] & mdataouta[i+1] & ~sdataouta[i])))) | 
+	               ( s_ovflw & ((mdataouta[i] & ~mdataouta[i+1] &  sdataouta[i+1]) | (~mdataouta[i] & mdataouta[i+1] & ~sdataouta[i+1]))) ;	// late bits
+end 
+endgenerate
+
+assign msxoria[0] = ((~s_ovflw & ((mdataoutb & ~mdataouta[0] & ~sdataoutb)    | (~mdataoutb & mdataouta[0] &  sdataoutb))) | 			// first early bit
+	             ( s_ovflw & ((mdataoutb & ~mdataouta[0] & ~sdataouta[0]) | (~mdataoutb & mdataouta[0] &  sdataouta[0])))) ;
+assign msxorda[0] = ((~s_ovflw & ((mdataoutb & ~mdataouta[0] &  sdataoutb)    | (~mdataoutb & mdataouta[0] & ~sdataoutb)))) | 			// first late bit
+	             ( s_ovflw & ((mdataoutb & ~mdataouta[0] &  sdataouta[0]) | (~mdataoutb & mdataouta[0] & ~sdataouta[0]))) ;
+
+always @ (posedge clk) begin				// generate number of incs or decs for low 4 bits
+	case (msxoria[3:0])
+		4'h0    : msxor_cti <= 2'h0 ;
+		4'h1    : msxor_cti <= 2'h1 ;
+		4'h2    : msxor_cti <= 2'h1 ;
+		4'h3    : msxor_cti <= 2'h2 ;
+		4'h4    : msxor_cti <= 2'h1 ;
+		4'h5    : msxor_cti <= 2'h2 ;
+		4'h6    : msxor_cti <= 2'h2 ;
+		4'h8    : msxor_cti <= 2'h1 ;
+		4'h9    : msxor_cti <= 2'h2 ;
+		4'hA    : msxor_cti <= 2'h2 ;
+		4'hC    : msxor_cti <= 2'h2 ;
+		default : msxor_cti <= 2'h3 ;
+	endcase
+	case (msxorda[3:0])
+		4'h0    : msxor_ctd <= 2'h0 ;
+		4'h1    : msxor_ctd <= 2'h1 ;
+		4'h2    : msxor_ctd <= 2'h1 ;
+		4'h3    : msxor_ctd <= 2'h2 ;
+		4'h4    : msxor_ctd <= 2'h1 ;
+		4'h5    : msxor_ctd <= 2'h2 ;
+		4'h6    : msxor_ctd <= 2'h2 ;
+		4'h8    : msxor_ctd <= 2'h1 ;
+		4'h9    : msxor_ctd <= 2'h2 ;
+		4'hA    : msxor_ctd <= 2'h2 ;
+		4'hC    : msxor_ctd <= 2'h2 ;
+		default : msxor_ctd <= 2'h3 ;
+	endcase
+	case (msxoria[7:4])				// generate number of incs or decs for high n bits, max 4
+		4'h0    : msxor_ctix <= 2'h0 ;
+		4'h1    : msxor_ctix <= 2'h1 ;
+		4'h2    : msxor_ctix <= 2'h1 ;
+		4'h3    : msxor_ctix <= 2'h2 ;
+		4'h4    : msxor_ctix <= 2'h1 ;
+		4'h5    : msxor_ctix <= 2'h2 ;
+		4'h6    : msxor_ctix <= 2'h2 ;
+		4'h8    : msxor_ctix <= 2'h1 ;
+		4'h9    : msxor_ctix <= 2'h2 ;
+		4'hA    : msxor_ctix <= 2'h2 ;
+		4'hC    : msxor_ctix <= 2'h2 ;
+		default : msxor_ctix <= 2'h3 ;
+	endcase
+	case (msxorda[7:4])
+		4'h0    : msxor_ctdx <= 2'h0 ;
+		4'h1    : msxor_ctdx <= 2'h1 ;
+		4'h2    : msxor_ctdx <= 2'h1 ;
+		4'h3    : msxor_ctdx <= 2'h2 ;
+		4'h4    : msxor_ctdx <= 2'h1 ;
+		4'h5    : msxor_ctdx <= 2'h2 ;
+		4'h6    : msxor_ctdx <= 2'h2 ;
+		4'h8    : msxor_ctdx <= 2'h1 ;
+		4'h9    : msxor_ctdx <= 2'h2 ;
+		4'hA    : msxor_ctdx <= 2'h2 ;
+		4'hC    : msxor_ctdx <= 2'h2 ;
+		default : msxor_ctdx <= 2'h3 ;
+	endcase
+end
+
+assign msxor_ctiy = {1'b0, msxor_cti} + {1'b0, msxor_ctix} ;
+assign msxor_ctdy = {1'b0, msxor_ctd} + {1'b0, msxor_ctdx} ;
+
+always @ (posedge clk) begin
+	if (msxor_ctiy == msxor_ctdy) begin
+		action <= 2'h0 ;
+	end
+	else if (msxor_ctiy > msxor_ctdy) begin
+		action <= 2'h1 ;
+	end 
+	else begin
+		action <= 2'h2 ;
+	end
+end
+		       	       
+generate
+for (i = 0 ; i <= S-1 ; i = i+1) begin : loop1
+assign all_high[i] = 1'b1 ;
+assign all_low[i] = 1'b0 ;
+end 
+endgenerate
+
+always @ (posedge clk) begin
+	mdataouta <= m_datain ;
+	mdataoutb <= mdataouta[S-1] ;
+	sdataouta <= s_datain ;
+	sdataoutb <= sdataouta[S-1] ;
+end
+	
+always @ (posedge clk) begin
+	if (reset == 1'b1) begin
+		s_ovflw <= 1'b0 ;
+		pdcount <= 6'b100000 ;
+		m_delay_val_int <= c_delay_in ; 			// initial master delay
+		s_delay_val_int <= c_delay_in ; 			// initial slave delay
+		data_mux <= 1'b0 ;
+		m_delay_mux <= 2'b01 ;
+		s_delay_mux <= 2'b01 ;
+		s_state <= 5'b00000 ;
+		inc_run <= 1'b0 ;
+		dec_run <= 1'b0 ;
+		eye_run <= 1'b0 ;
+		s_delay_val_eye <= 5'h00 ;
+		shifter <= 32'h00000001 ;
+		delay_change <= 1'b0 ;
+		results <= 32'h00000000 ;
+		pd_hold <= 8'h00 ;
+	end
+	else begin
+		case (m_delay_mux)
+			2'b00   : mdataoutc <= {mdataouta[S-2:0], mdataoutb} ;
+			2'b10   : mdataoutc <= {m_datain[0],      mdataouta[S-1:1]} ;
+			default : mdataoutc <= mdataouta ;
+		endcase 
+		case (s_delay_mux)  
+			2'b00   : sdataoutc <= {sdataouta[S-2:0], sdataoutb} ;
+			2'b10   : sdataoutc <= {s_datain[0],      sdataouta[S-1:1]} ;
+			default : sdataoutc <= sdataouta ;
+		endcase
+		if (m_delay_val_int == bt_val) begin
+			meq_max <= 1'b1 ;
+		end else begin 
+			meq_max <= 1'b0 ;
+		end 
+		if (m_delay_val_int == 5'h00) begin
+			meq_min <= 1'b1 ;
+		end else begin 
+			meq_min <= 1'b0 ;
+		end 
+		if (pdcount == 6'h3F && pd_max == 1'b0 && delay_change == 1'b0) begin
+			pd_max <= 1'b1 ;
+		end else begin 
+			pd_max <= 1'b0 ;
+		end 
+		if (pdcount == 6'h00 && pd_min == 1'b0 && delay_change == 1'b0) begin
+			pd_min <= 1'b1 ;
+		end else begin 
+			pd_min <= 1'b0 ;
+		end
+		if (delay_change == 1'b1 || inc_run == 1'b1 || dec_run == 1'b1 || eye_run == 1'b1) begin
+			pd_hold <= 8'hFF ;
+			pdcount <= 6'b100000 ; 
+		end													// increment filter count
+		else if (pd_hold[7] == 1'b1) begin
+			pdcount <= 6'b100000 ; 
+			pd_hold <= {pd_hold[6:0], 1'b0} ;
+		end
+		else if (action[0] == 1'b1 && pdcount != 6'b111111) begin 
+			pdcount <= pdcount + 6'h01 ; 
+		end													// decrement filter count
+		else if (action[1] == 1'b1 && pdcount != 6'b000000) begin 
+			pdcount <= pdcount - 6'h01 ; 
+		end
+		if ((enable_phase_detector == 1'b1 && pd_max == 1'b1 && delay_change == 1'b0) || inc_run == 1'b1) begin					// increment delays, check for master delay = max
+			delay_change <= 1'b1 ;
+			if (meq_max == 1'b0 && inc_run == 1'b0) begin
+				m_delay_val_int <= m_delay_val_int + 5'h01 ;
+			end 
+			else begin											// master is max
+				s_state[3:0] <= s_state[3:0] + 4'h1 ;
+				case (s_state[3:0]) 
+				4'b0000 : begin inc_run <= 1'b1 ; s_delay_val_int <= bt_val ; end			// indicate state machine running and set slave delay to bit time 
+				4'b0110 : begin data_mux <= 1'b1 ; m_delay_val_int <= 5'b00000 ; end			// change data mux over to forward slave data and set master delay to zero
+				4'b1001 : begin m_delay_mux <= m_delay_mux - 2'h1 ; end 				// change delay mux over to forward with a 1-bit less advance
+				4'b1110 : begin data_mux <= 1'b0 ; end 							// change data mux over to forward master data
+				4'b1111 : begin s_delay_mux <= m_delay_mux ; inc_run <= 1'b0 ; end			// change delay mux over to forward with a 1-bit less advance
+				default : begin inc_run <= 1'b1 ; end
+				endcase 
+			end
+		end
+		else if ((enable_phase_detector == 1'b1 && pd_min == 1'b1 && delay_change == 1'b0) || dec_run == 1'b1) begin				// decrement delays, check for master delay = 0
+			delay_change <= 1'b1 ;
+			if (meq_min == 1'b0 && dec_run == 1'b0) begin
+				m_delay_val_int <= m_delay_val_int - 5'h01 ;
+			end
+			else begin 											// master is zero
+				s_state[3:0] <= s_state[3:0] + 4'h1 ;
+				case (s_state[3:0]) 
+				4'b0000 : begin dec_run <= 1'b1 ; s_delay_val_int <= 5'b00000 ; end			// indicate state machine running and set slave delay to zero 
+				4'b0110 : begin data_mux <= 1'b1 ;  m_delay_val_int <= bt_val ;	end			// change data mux over to forward slave data and set master delay to bit time 
+				4'b1001 : begin m_delay_mux <= m_delay_mux + 2'h1 ; end  				// change delay mux over to forward with a 1-bit more advance
+				4'b1110 : begin data_mux <= 1'b0 ; end 							// change data mux over to forward master data
+				4'b1111 : begin s_delay_mux <= m_delay_mux ; dec_run <= 1'b0 ; end			// change delay mux over to forward with a 1-bit less advance
+				default : begin dec_run <= 1'b1 ; end
+				endcase 
+			end
+		end
+		else if (enable_monitor == 1'b1 && (eye_run == 1'b1 || delay_change == 1'b1)) begin
+			delay_change <= 1'b0 ;
+			s_state <= s_state + 5'h01 ;
+			case (s_state) 
+				5'b00000 : begin eye_run <= 1'b1 ; s_delay_val_int <= s_delay_val_eye ; end						// indicate state machine running and set slave delay to monitor value 
+				5'b10110 : begin 
+				           if (match == 8'hFF) begin results <= results | shifter ; end			//. set or clear result bit
+				           else begin results <= results & ~shifter ; end 							 
+				           if (s_delay_val_eye == bt_val) begin 					// only monitor active taps, ie as far as btval
+				          	shifter <= 32'h00000001 ; s_delay_val_eye <= 5'h00 ; end
+				           else begin shifter <= {shifter[30:0], shifter[31]} ; 
+				          	s_delay_val_eye <= s_delay_val_eye + 5'h01 ; end			// 
+				          	eye_run <= 1'b0 ; s_state <= 5'h00 ; end
+				default :  begin eye_run <= 1'b1 ; end
+			endcase 
+		end
+		else begin
+			delay_change <= 1'b0 ;
+			if (m_delay_val_int >= {1'b0, bt_val[4:1]} &&  del_mech == 1'b0) begin 						// set slave delay to 1/2 bit period beyond or behind the master delay
+				s_delay_val_int <= m_delay_val_int - {1'b0, bt_val[4:1]} ;
+				s_ovflw <= 1'b0 ;
+			end
+			else begin
+				s_delay_val_int <= m_delay_val_int + {1'b0, bt_val[4:1]} ;
+				s_ovflw <= 1'b1 ;
+			end 
+		end 
+		if (enable_phase_detector == 1'b0 && delay_change == 1'b0) begin
+			delay_change <= 1'b1 ;
+		end
+	end
+	if (enable_phase_detector == 1'b1) begin
+		if (data_mux == 1'b0) begin
+			data_out <= mdataoutc ;
+		end else begin 
+			data_out <= sdataoutc ;
+		end
+	end
+	else begin
+		data_out <= m_datain ;	
+	end
+end
+
+always @ (posedge clk) begin
+	if ((mdataouta == sdataouta)) begin
+		match <= {match[6:0], 1'b1} ;
+	end else begin
+		match <= {match[6:0], 1'b0} ;
+	end
+end
+
+always @ (m_delay_val_int) begin
+	case (m_delay_val_int)
+	    	5'b00000	: m_delay_1hot <= 32'h00000001 ;
+	    	5'b00001	: m_delay_1hot <= 32'h00000002 ;
+	    	5'b00010	: m_delay_1hot <= 32'h00000004 ;
+	    	5'b00011	: m_delay_1hot <= 32'h00000008 ;
+	    	5'b00100	: m_delay_1hot <= 32'h00000010 ;
+	    	5'b00101	: m_delay_1hot <= 32'h00000020 ;
+	    	5'b00110	: m_delay_1hot <= 32'h00000040 ;
+	    	5'b00111	: m_delay_1hot <= 32'h00000080 ;
+	    	5'b01000	: m_delay_1hot <= 32'h00000100 ;
+	    	5'b01001	: m_delay_1hot <= 32'h00000200 ;
+	    	5'b01010	: m_delay_1hot <= 32'h00000400 ;
+	    	5'b01011	: m_delay_1hot <= 32'h00000800 ;
+	    	5'b01100	: m_delay_1hot <= 32'h00001000 ;
+	    	5'b01101	: m_delay_1hot <= 32'h00002000 ;
+	    	5'b01110	: m_delay_1hot <= 32'h00004000 ;
+	    	5'b01111	: m_delay_1hot <= 32'h00008000 ;
+            	5'b10000	: m_delay_1hot <= 32'h00010000 ;
+            	5'b10001	: m_delay_1hot <= 32'h00020000 ;
+            	5'b10010	: m_delay_1hot <= 32'h00040000 ;
+            	5'b10011	: m_delay_1hot <= 32'h00080000 ;
+            	5'b10100	: m_delay_1hot <= 32'h00100000 ;
+            	5'b10101	: m_delay_1hot <= 32'h00200000 ;
+            	5'b10110	: m_delay_1hot <= 32'h00400000 ;
+            	5'b10111	: m_delay_1hot <= 32'h00800000 ;
+            	5'b11000	: m_delay_1hot <= 32'h01000000 ;
+            	5'b11001	: m_delay_1hot <= 32'h02000000 ;
+            	5'b11010	: m_delay_1hot <= 32'h04000000 ;
+            	5'b11011	: m_delay_1hot <= 32'h08000000 ;
+            	5'b11100	: m_delay_1hot <= 32'h10000000 ;
+            	5'b11101	: m_delay_1hot <= 32'h20000000 ;
+            	5'b11110	: m_delay_1hot <= 32'h40000000 ;
+            	default		: m_delay_1hot <= 32'h80000000 ; 
+         endcase
+end
+   	
+endmodule

src/src/AdcDataRx/n_x_serdes_1_to_7_mmcm_idelay_sdr.v

@@ -0,0 +1,169 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: n_x_serdes_1_to_7_mmcm_idelay_sdr.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 5MAR2010
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7 Series
+//Purpose:  	Wrapper for multiple 1 to 7 SDR clock and data receiver using one PLL/MMCM for clock multiplication
+//
+//Reference:	XAPP585
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - Generate loop changed to correct problem when only one channel
+//    Rev 1.2 - Eye monitoring added, upated format
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module n_x_serdes_1_to_7_mmcm_idelay_sdr (clkin_p, clkin_n, datain_p, datain_n, enable_phase_detector, enable_monitor, rxclk, idelay_rdy, reset, rxclk_div, 
+                                          rx_mmcm_lckdps, rx_mmcm_lckd, rx_mmcm_lckdpsbs, clk_data, rx_data, status, debug, bit_rate_value, bit_time_value, eye_info, m_delay_1hot) ;
+
+parameter integer 	N = 8 ;				// Set the number of channels
+parameter integer 	D = 6 ;   			// Parameter to set the number of data lines per channel
+parameter integer      	MMCM_MODE = 1 ;   		// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
+parameter real 	  	CLKIN_PERIOD = 6.000 ;		// clock period (ns) of input clock on clkin_p
+parameter 		HIGH_PERFORMANCE_MODE = "FALSE";// Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
+parameter         	DIFF_TERM = "FALSE" ; 		// Parameter to enable internal differential termination
+parameter         	SAMPL_CLOCK = "BUFIO" ;   	// Parameter to set sampling clock buffer type, BUFIO, BUF_H, BUF_G
+parameter         	PIXEL_CLOCK = "BUF_R" ;       	// Parameter to set pixel clock buffer type, BUF_R, BUF_H, BUF_G
+parameter         	USE_PLL = "FALSE" ;          	// Parameter to enable PLL use rather than MMCM use, overides SAMPL_CLOCK and INTER_CLOCK to be both BUFH
+parameter         	DATA_FORMAT = "PER_CLOCK" ;     // Parameter Used to determine method for mapping input parallel word to output serial words
+                                     	
+input 	[N-1:0]		clkin_p ;			// Input from LVDS clock receiver pin
+input 	[N-1:0]		clkin_n ;			// Input from LVDS clock receiver pin
+input 	[N*D-1:0]	datain_p ;			// Input from LVDS clock data pins
+input 	[N*D-1:0]	datain_n ;			// Input from LVDS clock data pins
+input 			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the monitor logic when high, note time-shared with phase detector function
+input 			reset ;				// Reset line
+input			idelay_rdy ;			// input delays are ready
+output 			rxclk ;				// Global/BUFIO rx clock network
+output 			rxclk_div ;			// Global/Regional clock output
+output 			rx_mmcm_lckd ; 			// MMCM locked, synchronous to rxclk_d4
+output 			rx_mmcm_lckdps ; 		// MMCM locked and phase shifting finished, synchronous to rxclk_d4
+output 	[N-1:0]		rx_mmcm_lckdpsbs ; 		// MMCM locked and phase shifting finished and bitslipping finished, synchronous to rxclk_div
+output 	[N*7-1:0]	clk_data ;	 		// Clock Data
+output 	[N*D*7-1:0]	rx_data ;	 		// Received Data
+output 	[(10*D+6)*N-1:0]debug ;	 			// debug info
+output 	[6:0]		status ;	 		// clock status
+input 	[15:0]		bit_rate_value ;	 	// Bit rate in Mbps, for example 16'h0585
+output	[4:0]		bit_time_value ;		// Calculated bit time value for slave devices
+output	[32*D*N-1:0]	eye_info ;			// Eye info
+output	[32*D*N-1:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector
+
+wire			rxclk_d4 ;
+wire			pd ;
+
+serdes_1_to_7_mmcm_idelay_sdr #(
+	.SAMPL_CLOCK		(SAMPL_CLOCK),
+	.PIXEL_CLOCK		(PIXEL_CLOCK),
+	.USE_PLL		(USE_PLL),
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.D			(D),				// Number of data lines
+      	.CLKIN_PERIOD		(CLKIN_PERIOD),			// Set input clock period
+      	.MMCM_MODE		(MMCM_MODE),			// Set mmcm vco, either 1 or 2
+	.DIFF_TERM		(DIFF_TERM),
+	.DATA_FORMAT		(DATA_FORMAT))
+rx0 (
+	.clkin_p   		(clkin_p[0]),
+	.clkin_n   		(clkin_n[0]),
+	.datain_p     		(datain_p[D-1:0]),
+	.datain_n     		(datain_n[D-1:0]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.rxclk    		(rxclk),
+	.idelay_rdy		(idelay_rdy),
+	.rxclk_div		(rxclk_div),
+	.reset     		(reset),
+	.rx_mmcm_lckd		(rx_mmcm_lckd),
+	.rx_mmcm_lckdps		(rx_mmcm_lckdps),
+	.rx_mmcm_lckdpsbs	(rx_mmcm_lckdpsbs[0]),
+	.clk_data  		(clk_data[6:0]),
+	.rx_data		(rx_data[7*D-1:0]),
+	.bit_rate_value		(bit_rate_value),
+	.bit_time_value		(bit_time_value),
+	.status			(status),
+	.eye_info		(eye_info[32*D-1:0]),
+	.rst_iserdes		(rst_iserdes),
+	.m_delay_1hot		(m_delay_1hot[32*D-1:0]),
+	.debug			(debug[10*D+5:0])
+	);
+
+genvar i ;
+genvar j ;
+
+generate
+if (N > 1) begin
+for (i = 1 ; i <= (N-1) ; i = i+1)
+begin : loop0
+
+serdes_1_to_7_slave_idelay_sdr #(
+      	.D			(D),				// Number of data lines
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+	.DIFF_TERM		(DIFF_TERM),
+	.DATA_FORMAT		(DATA_FORMAT))
+rxn (
+	.clkin_p   		(clkin_p[i]),
+	.clkin_n   		(clkin_n[i]),
+	.datain_p     		(datain_p[D*(i+1)-1:D*i]),
+	.datain_n     		(datain_n[D*(i+1)-1:D*i]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.rxclk    		(rxclk),
+	.idelay_rdy		(idelay_rdy),
+	.rxclk_div		(),
+	.reset     		(~rx_mmcm_lckdps),
+	.bitslip_finished	(rx_mmcm_lckdpsbs[i]),
+	.clk_data  		(clk_data[7*i+6:7*i]),
+	.rx_data		(rx_data[(D*(i+1)*7)-1:D*i*7]),
+	.bit_time_value		(bit_time_value),
+	.eye_info		(eye_info[32*D*(i+1)-1:32*D*i]),
+	.m_delay_1hot		(m_delay_1hot[(32*D)*(i+1)-1:(32*D)*i]),
+	.rst_iserdes		(rst_iserdes),
+	.debug			(debug[(10*D+6)*(i+1)-1:(10*D+6)*i]));
+
+end
+end
+endgenerate
+endmodule

src/src/AdcDataRx/serdes_1_to_7_mmcm_idelay_sdr.v

@@ -0,0 +1,718 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: serdes_1_to_7_mmcm_idelay_sdr.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 5MAR2010
+// \   \  /  \
+//  \___\/\___\
+//
+//Device: 	7 Series
+//Purpose:  	1 to 7 SDR receiver clock and data receiver using an MMCM for clock multiplication
+//		Data formatting is set by the DATA_FORMAT parameter.
+//		PER_CLOCK (default) format receives bits for 0, 1, 2 .. on the same sample edge
+//		PER_CHANL format receives bits for 0, 7, 14 ..  on the same sample edge
+//
+//Reference:	XAPP585
+//
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - PER_CLOCK and PER_CHANL descriptions swapped
+//    Rev 1.2 - Eye monitoring added, updated format
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer:
+//
+//		This disclaimer is not a license and does not grant any rights to the materials
+//              distributed herewith. Except as otherwise provided in a valid license issued to you
+//              by Xilinx, and to the maximum extent permitted by applicable law:
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage
+//              of any kind or nature related to, arising under or in connection with these materials,
+//              including for any direct, or any indirect, special, incidental, or consequential loss
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
+//              as a result of any action brought by a third party) even if such damage or loss was
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application
+//		requiring fail-safe performance, such as life-support or safety devices or systems,
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module serdes_1_to_7_mmcm_idelay_sdr (clkin_p, clkin_n, datain_p, datain_n, enable_phase_detector, enable_monitor, rxclk, idelay_rdy, reset, rxclk_div,
+                                      rx_mmcm_lckdps, rx_mmcm_lckd, rx_mmcm_lckdpsbs, clk_data, rx_data, status, debug, bit_rate_value, bit_time_value, m_delay_1hot, rst_iserdes, eye_info) ;
+
+parameter integer 	D = 8 ;   			// Parameter to set the number of data lines
+parameter integer      	MMCM_MODE = 1 ;   		// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
+parameter 		HIGH_PERFORMANCE_MODE = "FALSE";// Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
+parameter real 	  	CLKIN_PERIOD = 6.000 ;		// clock period (ns) of input clock on clkin_p
+parameter         	DIFF_TERM = "FALSE" ; 		// Parameter to enable internal differential termination
+parameter         	SAMPL_CLOCK = "BUFIO" ;   	// Parameter to set sampling clock buffer type, BUFIO, BUF_H, BUF_G
+parameter         	PIXEL_CLOCK = "BUF_R" ;       	// Parameter to set final pixel buffer type, BUF_R, BUF_H, BUF_G
+parameter         	USE_PLL = "FALSE" ;          	// Parameter to enable PLL use rather than MMCM use, note, PLL does not support BUFIO and BUFR
+parameter         	DATA_FORMAT = "PER_CLOCK" ;     // Parameter Used to determine method for mapping input parallel word to output serial words
+
+input 			clkin_p ;			// Input from LVDS clock receiver pin
+input 			clkin_n ;			// Input from LVDS clock receiver pin
+input 	[D-1:0]		datain_p ;			// Input from LVDS clock data pins
+input 	[D-1:0]		datain_n ;			// Input from LVDS clock data pins
+input 			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the monitor logic when high, note time-shared with phase detector function
+input 			reset ;				// Reset line
+input			idelay_rdy ;			// input delays are ready
+output 			rxclk ;				// Global/BUFIO rx clock network
+output 			rxclk_div ;			// Global/Regional clock output
+output 			rx_mmcm_lckd ; 			// MMCM locked, synchronous to rxclk_div
+output 			rx_mmcm_lckdps ; 		// MMCM locked and phase shifting finished, synchronous to rxclk_div
+output 			rx_mmcm_lckdpsbs ; 		// MMCM locked and phase shifting finished and bitslipping finished, synchronous to rxclk_div
+output 	[6:0]		clk_data ;	 		// Clock Data
+output 	[D*7-1:0]	rx_data ;	 		// Received Data
+output 	[10*D+5:0]	debug ;	 			// debug info
+output 	[6:0]		status ;	 		// clock status info
+input 	[15:0]		bit_rate_value ;	 	// Bit rate in Mbps, eg 16'h0585
+output	[4:0]		bit_time_value ;		// Calculated bit time value for slave devices
+output	reg		rst_iserdes ;			// serdes reset signal
+output	[32*D-1:0]	eye_info ;			// Eye info
+output	[32*D-1:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector
+
+wire	[D*5-1:0]	m_delay_val_in ;
+wire	[D*5-1:0]	s_delay_val_in ;
+reg	[1:0]		bsstate ;
+reg 			bslip ;
+reg	[3:0]		bcount ;
+wire 	[6:0] 		clk_iserdes_data ;
+reg 	[6:0] 		clk_iserdes_data_d ;
+reg 			enable ;
+reg 			flag1 ;
+reg 			flag2 ;
+reg 	[2:0] 		state2 ;
+reg 	[4:0] 		state2_count ;
+reg 	[5:0] 		scount ;
+reg 			locked_out ;
+reg			chfound ;
+reg			chfoundc ;
+reg			not_rx_mmcm_lckd_int ;
+reg	[4:0]		c_delay_in ;
+reg	[4:0]		c_delay_in_target ;
+reg			c_delay_in_ud ;
+wire 	[D-1:0]		rx_data_in_p ;
+wire 	[D-1:0]		rx_data_in_n ;
+wire 	[D-1:0]		rx_data_in_m ;
+wire 	[D-1:0]		rx_data_in_s ;
+wire 	[D-1:0]		rx_data_in_md ;
+wire 	[D-1:0]		rx_data_in_sd ;
+wire	[(7*D)-1:0] 	mdataout ;
+wire	[(7*D)-1:0] 	mdataoutd ;
+wire	[(7*D)-1:0] 	sdataout ;
+reg			data_different ;
+reg			bs_finished ;
+reg			not_bs_finished ;
+reg	[4:0]		bt_val ;
+wire			mmcm_locked ;
+wire			rx_mmcmout_x1 ;
+wire			rx_mmcmout_xs ;
+reg			rstcserdes ;
+reg	[1:0]		c_loop_cnt ;
+
+parameter [D-1:0] 	RX_SWAP_MASK = 16'h0000 ;	// pinswap mask for input data bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
+
+assign clk_data = clk_iserdes_data ;
+assign debug = {s_delay_val_in, m_delay_val_in, bslip, c_delay_in} ;
+assign rx_mmcm_lckdpsbs = bs_finished & mmcm_locked ;
+assign rx_mmcm_lckd = ~not_rx_mmcm_lckd_int & mmcm_locked ;
+assign rx_mmcm_lckdps = ~not_rx_mmcm_lckd_int & locked_out & mmcm_locked ;
+assign bit_time_value = bt_val ;
+
+always @ (bit_rate_value) begin			// Generate tap number to be used for input bit rate
+	if      (bit_rate_value > 16'h1068) begin bt_val <= 5'h0C ; end
+	else if (bit_rate_value > 16'h0986) begin bt_val <= 5'h0D ; end
+	else if (bit_rate_value > 16'h0916) begin bt_val <= 5'h0E ; end
+	else if (bit_rate_value > 16'h0855) begin bt_val <= 5'h0F ; end
+	else if (bit_rate_value > 16'h0801) begin bt_val <= 5'h10 ; end
+	else if (bit_rate_value > 16'h0754) begin bt_val <= 5'h11 ; end
+	else if (bit_rate_value > 16'h0712) begin bt_val <= 5'h12 ; end
+	else if (bit_rate_value > 16'h0675) begin bt_val <= 5'h13 ; end
+	else if (bit_rate_value > 16'h0641) begin bt_val <= 5'h14 ; end
+	else if (bit_rate_value > 16'h0611) begin bt_val <= 5'h15 ; end
+	else if (bit_rate_value > 16'h0583) begin bt_val <= 5'h16 ; end
+	else if (bit_rate_value > 16'h0557) begin bt_val <= 5'h17 ; end
+	else if (bit_rate_value > 16'h0534) begin bt_val <= 5'h18 ; end
+	else if (bit_rate_value > 16'h0513) begin bt_val <= 5'h19 ; end
+	else if (bit_rate_value > 16'h0493) begin bt_val <= 5'h1A ; end
+	else if (bit_rate_value > 16'h0475) begin bt_val <= 5'h1B ; end
+	else if (bit_rate_value > 16'h0458) begin bt_val <= 5'h1C ; end
+	else if (bit_rate_value > 16'h0442) begin bt_val <= 5'h1D ; end
+	else if (bit_rate_value > 16'h0427) begin bt_val <= 5'h1E ; end
+	else                                begin bt_val <= 5'h1F ; end
+end
+
+// Bitslip state machine
+
+always @ (posedge rxclk_div)
+begin
+if (locked_out == 1'b0) begin
+	bslip <= 1'b0 ;
+	bsstate <= 1 ;
+	enable <= 1'b0 ;
+	bcount <= 4'h0 ;
+	bs_finished <= 1'b0 ;
+	not_bs_finished <= 1'b1 ;
+end
+else begin
+	enable <= 1'b1 ;
+   	if (enable == 1'b1) begin
+   		if (clk_iserdes_data != 7'b1111111) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end
+   		if (clk_iserdes_data != 7'b0000000) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+     		if (bsstate == 0) begin
+   			if (flag1 == 1'b1 && flag2 == 1'b1) begin
+     		   		bslip <= 1'b1 ;						// bitslip needed
+     		   		bsstate <= 1 ;
+     		   	end
+     		   	else begin
+     		   		bs_finished <= 1'b1 ;					// bitslip done
+     		   		not_bs_finished <= 1'b0 ;				// bitslip done
+     		   	end
+		end
+   		else if (bsstate == 1) begin
+     		   	bslip <= 1'b0 ;
+     		   	bcount <= bcount + 4'h1 ;
+   			if (bcount == 4'hF) begin
+     		   		bsstate <= 0 ;
+     		   	end
+   		end
+   	end
+end
+end
+
+// Clock input
+
+IBUFGDS_DIFF_OUT #(
+	.DIFF_TERM 		(DIFF_TERM),
+	.IBUF_LOW_PWR		("FALSE"))
+iob_clk_in (
+	.I    			(clkin_p),
+	.IB       		(clkin_n),
+	.O         		(rx_clk_in_p),
+	.OB         		(rx_clk_in_n));
+
+genvar i ;
+genvar j ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE 	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(1),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_cm(
+	.DATAOUT		(rx_clkin_p_d),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_clk_in_p),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(c_delay_in),
+	.CNTVALUEOUT		());
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE 	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(1),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_cs(
+	.DATAOUT		(rx_clk_in_n_d),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(~rx_clk_in_n),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		({1'b0, bt_val[4:1]}),
+	.CNTVALUEOUT		());
+
+ISERDESE2 #(
+	.DATA_WIDTH     	(7),
+	.DATA_RATE      	("SDR"),
+//	.SERDES_MODE    	("MASTER"),
+	.IOBDELAY	    	("IFD"),
+	.INTERFACE_TYPE 	("NETWORKING"))
+iserdes_cm (
+	.D       		(1'b0),
+	.DDLY     		(rx_clk_in_n_d),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK    		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rstcserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8 			(),
+	.Q7 			(clk_iserdes_data[0]),
+	.Q6 			(clk_iserdes_data[1]),
+	.Q5 			(clk_iserdes_data[2]),
+	.Q4 			(clk_iserdes_data[3]),
+	.Q3 			(clk_iserdes_data[4]),
+	.Q2 			(clk_iserdes_data[5]),
+	.Q1 			(clk_iserdes_data[6]),
+	.OFB 			(),
+	.SHIFTOUT1 		(),
+	.SHIFTOUT2 		());
+
+generate
+if (USE_PLL == "FALSE") begin : loop8					// use an MMCM
+assign status[6] = 1'b1 ;
+
+MMCME2_ADV #(
+      	.BANDWIDTH		("OPTIMIZED"),  		
+      	.CLKFBOUT_MULT_F	(7*MMCM_MODE),
+      	.CLKFBOUT_PHASE		(0.0),
+      	.CLKIN1_PERIOD		(CLKIN_PERIOD),
+      	.CLKIN2_PERIOD		(CLKIN_PERIOD),
+      	.CLKOUT0_DIVIDE_F	(1*MMCM_MODE),
+      	.CLKOUT0_DUTY_CYCLE	(0.5),
+      	.CLKOUT0_PHASE		(0.0),
+	.CLKOUT0_USE_FINE_PS	("FALSE"),
+      	.CLKOUT1_DIVIDE		(6*MMCM_MODE),
+      	.CLKOUT1_DUTY_CYCLE	(0.5),
+      	.CLKOUT1_PHASE		(22.5),
+	.CLKOUT1_USE_FINE_PS	("FALSE"),
+      	.CLKOUT2_DIVIDE		(7*MMCM_MODE),
+      	.CLKOUT2_DUTY_CYCLE	(0.5),
+      	.CLKOUT2_PHASE		(0.0),
+	.CLKOUT2_USE_FINE_PS	("FALSE"),
+      	.CLKOUT3_DIVIDE		(7),
+      	.CLKOUT3_DUTY_CYCLE	(0.5),
+      	.CLKOUT3_PHASE		(0.0),
+      	.CLKOUT4_DIVIDE		(7),
+      	.CLKOUT4_DUTY_CYCLE	(0.5),
+      	.CLKOUT4_PHASE		(0.0),
+      	.CLKOUT5_DIVIDE		(7),
+      	.CLKOUT5_DUTY_CYCLE	(0.5),
+      	.CLKOUT5_PHASE		(0.0),
+      	.COMPENSATION		("ZHOLD"),
+      	.DIVCLK_DIVIDE		(1),
+      	.REF_JITTER1		(0.100))
+rx_mmcm_adv_inst (
+      	.CLKFBOUT		(rx_mmcmout_x1),
+      	.CLKFBOUTB		(),
+      	.CLKFBSTOPPED		(),
+      	.CLKINSTOPPED		(),
+      	.CLKOUT0		(rx_mmcmout_xs),
+      	.CLKOUT0B		(),
+      	.CLKOUT1		(),
+      	.CLKOUT1B		(),
+      	.CLKOUT2		(),
+      	.CLKOUT2B		(),
+      	.CLKOUT3		(),
+      	.CLKOUT3B		(),
+      	.CLKOUT4		(),
+      	.CLKOUT5		(),
+      	.CLKOUT6		(),
+      	.DO			(),
+      	.DRDY			(),
+      	.PSDONE			(),
+      	.PSCLK			(1'b0),
+      	.PSEN			(1'b0),
+      	.PSINCDEC		(1'b0),
+      	.PWRDWN			(1'b0),
+      	.LOCKED			(mmcm_locked),
+      	.CLKFBIN		(rxclk_div),
+      	.CLKIN1			(rx_clkin_p_d),
+      	.CLKIN2			(1'b0),
+      	.CLKINSEL		(1'b1),
+      	.DADDR			(7'h00),
+      	.DCLK			(1'b0),
+      	.DEN			(1'b0),
+      	.DI			(16'h0000),
+      	.DWE			(1'b0),
+      	.RST			(reset)) ;
+
+   assign status[3:2] = 2'b00 ;
+
+   if (PIXEL_CLOCK == "BUF_G") begin 						// Final clock selection
+      BUFG	bufg_mmcm_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+      assign status[1:0] = 2'b00 ;
+   end
+   else if (PIXEL_CLOCK == "BUF_R") begin
+      BUFR #(.BUFR_DIVIDE("1"),.SIM_DEVICE("7SERIES"))bufr_mmcm_x1 (.I(rx_mmcmout_x1),.CE(1'b1),.O(rxclk_div),.CLR(1'b0)) ;
+      assign status[1:0] = 2'b01 ;
+   end
+   else begin
+      BUFH	bufh_mmcm_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+      assign status[1:0] = 2'b10 ;
+   end
+
+   if (SAMPL_CLOCK == "BUF_G") begin						// Sample clock selection
+      BUFG	bufg_mmcm_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b00 ;
+   end
+   else if (SAMPL_CLOCK == "BUFIO") begin
+      BUFIO  	bufio_mmcm_xn (.I (rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b11 ;
+   end
+   else begin
+      BUFH	bufh_mmcm_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b10 ;
+   end
+
+end
+else begin
+assign status[6] = 1'b0 ;
+
+PLLE2_ADV #(
+      	.BANDWIDTH		("OPTIMIZED"),
+      	.CLKFBOUT_MULT		(42),
+      	.CLKFBOUT_PHASE		(0.0),
+      	.CLKIN1_PERIOD		(CLKIN_PERIOD),
+      	.CLKIN2_PERIOD		(CLKIN_PERIOD),
+      	.CLKOUT0_DIVIDE		(3),
+      	.CLKOUT0_DUTY_CYCLE	(0.5),
+      	.CLKOUT0_PHASE		(0.0),
+      	.CLKOUT1_DIVIDE		(21),
+      	.CLKOUT1_DUTY_CYCLE	(0.5),
+      	.CLKOUT1_PHASE		(0),
+      	.CLKOUT2_DIVIDE		(7*MMCM_MODE),
+      	.CLKOUT2_DUTY_CYCLE	(0.5),
+      	.CLKOUT2_PHASE		(0.0),
+      	.CLKOUT3_DIVIDE		(7),
+      	.CLKOUT3_DUTY_CYCLE	(0.5),
+      	.CLKOUT3_PHASE		(0.0),
+      	.CLKOUT4_DIVIDE		(7),
+      	.CLKOUT4_DUTY_CYCLE	(0.5),
+      	.CLKOUT4_PHASE		(0.0),
+      	.CLKOUT5_DIVIDE		(7),
+      	.CLKOUT5_DUTY_CYCLE	(0.5),
+      	.CLKOUT5_PHASE		(0.0),
+      	.COMPENSATION		("ZHOLD"),
+      	.DIVCLK_DIVIDE		(1),
+      	.REF_JITTER1		(0.100))
+rx_plle2_adv_inst (
+      	.CLKFBOUT		(rx_mmcmFb),
+      	.CLKOUT0		(rx_mmcmout_xs),
+      	.CLKOUT1		(rx_mmcmout_x1),
+      	.CLKOUT2		(),
+      	.CLKOUT3		(),
+      	.CLKOUT4		(),
+      	.CLKOUT5		(),
+      	.DO			(),
+      	.DRDY			(),
+      	.PWRDWN			(1'b0),
+      	.LOCKED			(mmcm_locked),
+      	.CLKFBIN		(ClkFb),
+      	.CLKIN1			(rx_clkin_p_d),
+      	.CLKIN2			(1'b0),
+      	.CLKINSEL		(1'b1),
+      	.DADDR			(7'h00),
+      	.DCLK			(1'b0),
+      	.DEN			(1'b0),
+      	.DI			(16'h0000),
+      	.DWE			(1'b0),
+      	.RST			(reset)) ;
+
+   assign status[3:2] = 2'b00 ;
+
+   if (PIXEL_CLOCK == "BUF_G") begin 						// Final clock selection
+      BUFG	bufg_pll_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+	  BUFG	bufg_pll_fb (.I(rx_mmcmFb), .O(ClkFb)) ;
+      assign status[1:0] = 2'b00 ;
+   end
+   else if (PIXEL_CLOCK == "BUF_R") begin
+      BUFR #(.BUFR_DIVIDE("1"),.SIM_DEVICE("7SERIES"))bufr_pll_x1 (.I(rx_mmcmout_x1),.CE(1'b1),.O(rxclk_div),.CLR(1'b0)) ;
+      assign status[1:0] = 2'b01 ;
+   end
+   else begin
+      BUFH	bufh_pll_x1 (.I(rx_mmcmout_x1), .O(rxclk_div)) ;
+      assign status[1:0] = 2'b10 ;
+   end
+
+   if (SAMPL_CLOCK == "BUF_G") begin						// Sample clock selection
+      BUFG	bufg_pll_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b00 ;
+   end
+   else if (SAMPL_CLOCK == "BUFIO") begin
+      BUFIO  	bufio_pll_xn (.I (rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b11 ;
+   end
+   else begin
+      BUFH	bufh_pll_xn (.I(rx_mmcmout_xs), .O(rxclk)) ;
+      assign status[5:4] = 2'b10 ;
+   end
+
+end
+endgenerate
+
+always @ (posedge rxclk_div) begin				//
+	clk_iserdes_data_d <= clk_iserdes_data ;
+	if ((clk_iserdes_data != clk_iserdes_data_d) && (clk_iserdes_data != 7'h00) && (clk_iserdes_data != 7'h7F)) begin
+		data_different <= 1'b1 ;
+	end
+	else begin
+		data_different <= 1'b0 ;
+	end
+end
+
+always @ (posedge rxclk_div) begin						// clock delay shift state machine
+	not_rx_mmcm_lckd_int <= ~(mmcm_locked & idelay_rdy) ;
+	rstcserdes <= not_rx_mmcm_lckd_int | rst_iserdes ;
+	if (not_rx_mmcm_lckd_int == 1'b1) begin
+		scount <= 6'h00 ;
+		state2 <= 0 ;
+		state2_count <= 5'h00 ;
+		locked_out <= 1'b0 ;
+		chfoundc <= 1'b1 ;
+		c_delay_in <= bt_val ;							// Start the delay line at the current bit period
+		rst_iserdes <= 1'b0 ;
+		c_loop_cnt <= 2'b00 ;
+	end
+	else begin
+		if (scount[5] == 1'b0) begin
+			scount <= scount + 6'h01 ;
+		end
+		state2_count <= state2_count + 5'h01 ;
+		if (chfoundc == 1'b1) begin
+			chfound <= 1'b0 ;
+		end
+		else if (chfound == 1'b0 && data_different == 1'b1) begin
+			chfound <= 1'b1 ;
+		end
+		if ((state2_count == 5'h1F && scount[5] == 1'b1)) begin
+			case(state2)
+			0	: begin							// decrement delay and look for a change
+				  if (chfound == 1'b1 || (c_loop_cnt == 2'b11 && c_delay_in == 5'h00)) begin  // quit loop if we've been around a few times
+					chfoundc <= 1'b1 ;
+					state2 <= 1 ;
+				  end
+				  else begin
+					chfoundc <= 1'b0 ;
+					if (c_delay_in != 5'h00) begin			// check for underflow
+						c_delay_in <= c_delay_in - 5'h01 ;
+					end
+					else begin
+						c_delay_in <= bt_val ;
+						c_loop_cnt <= c_loop_cnt + 2'b01 ;
+					end
+				  end
+				  end
+			1	: begin							// add half a bit period using input information
+				  state2 <= 2 ;
+				  if (c_delay_in < {1'b0, bt_val[4:1]}) begin		// choose the lowest delay value to minimise jitter
+				   	c_delay_in_target <= c_delay_in + {1'b0, bt_val[4:1]} ;
+				  end
+				  else begin
+				   	c_delay_in_target <= c_delay_in - {1'b0, bt_val[4:1]} ;
+				  end
+				  end
+			2 	: begin
+				  if (c_delay_in == c_delay_in_target) begin
+				   	state2 <= 3 ;
+				  end
+				  else begin
+				   	if (c_delay_in_ud == 1'b1) begin		// move gently to end position to stop MMCM unlocking
+						c_delay_in <= c_delay_in + 5'h01 ;
+				   		c_delay_in_ud <= 1'b1 ;
+				   	end
+				   	else begin
+						c_delay_in <= c_delay_in - 5'h01 ;
+				   		c_delay_in_ud <= 1'b0 ;
+				   	end
+				  end
+				  end
+			3 	: begin rst_iserdes <= 1'b1 ; state2 <= 4 ; end		// remove serdes reset
+			default	: begin							// issue locked out signal
+				  rst_iserdes <= 1'b0 ;  locked_out <= 1'b1 ;
+			 	  end
+			endcase
+		end
+	end
+end
+
+generate
+for (i = 0 ; i <= D-1 ; i = i+1)
+begin : loop3
+
+delay_controller_wrap # (
+	.S 			(7))
+dc_inst (
+	.m_datain		(mdataout[7*i+6:7*i]),
+	.s_datain		(sdataout[7*i+6:7*i]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.reset			(not_bs_finished),
+	.clk			(rxclk_div),
+	.c_delay_in		({1'b0, bt_val[4:1]}),
+	.m_delay_out		(m_delay_val_in[5*i+4:5*i]),
+	.s_delay_out		(s_delay_val_in[5*i+4:5*i]),
+	.data_out		(mdataoutd[7*i+6:7*i]),
+	.bt_val			(bt_val),
+	.del_mech		(1'b0),
+	.m_delay_1hot		(m_delay_1hot[32*i+31:32*i]),
+	.results		(eye_info[32*i+31:32*i])) ;
+
+// Data bit Receivers
+
+IBUFDS_DIFF_OUT #(
+	.DIFF_TERM 		(DIFF_TERM))
+data_in (
+	.I    			(datain_p[i]),
+	.IB       		(datain_n[i]),
+	.O         		(rx_data_in_p[i]),
+	.OB         		(rx_data_in_n[i]));
+
+assign rx_data_in_m[i] = rx_data_in_p[i]  ^ RX_SWAP_MASK[i] ;
+assign rx_data_in_s[i] = ~rx_data_in_n[i] ^ RX_SWAP_MASK[i] ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_m(
+	.DATAOUT		(rx_data_in_md[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_m[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(m_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+
+ISERDESE2 #(
+	.DATA_WIDTH     	(7),
+	.DATA_RATE      	("SDR"),
+	.SERDES_MODE    	("MASTER"),
+	.IOBDELAY	    	("IFD"),
+	.INTERFACE_TYPE 	("NETWORKING"))
+iserdes_m (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_md[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(mdataout[7*i+0]),
+	.Q6  			(mdataout[7*i+1]),
+	.Q5  			(mdataout[7*i+2]),
+	.Q4  			(mdataout[7*i+3]),
+	.Q3  			(mdataout[7*i+4]),
+	.Q2  			(mdataout[7*i+5]),
+	.Q1  			(mdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_s(
+	.DATAOUT		(rx_data_in_sd[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_s[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(s_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+
+ISERDESE2 #(
+	.DATA_WIDTH     	(7),
+	.DATA_RATE      	("SDR"),
+//	.SERDES_MODE    	("SLAVE"),
+	.IOBDELAY	    	("IFD"),
+	.INTERFACE_TYPE 	("NETWORKING"))
+iserdes_s (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_sd[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(sdataout[7*i+0]),
+	.Q6  			(sdataout[7*i+1]),
+	.Q5  			(sdataout[7*i+2]),
+	.Q4  			(sdataout[7*i+3]),
+	.Q3  			(sdataout[7*i+4]),
+	.Q2  			(sdataout[7*i+5]),
+	.Q1  			(sdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+for (j = 0 ; j <= 6 ; j = j+1) begin : loop1			// Assign data bits to correct serdes according to required format
+	if (DATA_FORMAT == "PER_CLOCK") begin
+		assign rx_data[D*j+i] = mdataoutd[7*i+j] ;
+	end
+	else begin
+		assign rx_data[7*i+j] = mdataoutd[7*i+j] ;
+	end
+end
+end
+endgenerate
+endmodule

src/src/AdcDataRx/serdes_1_to_7_slave_idelay_sdr.v

@@ -0,0 +1,495 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: serdes_1_to_7_slave_idelay_sdr.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 5MAR2010
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7 Series
+//Purpose:  	1 to 7 SDR receiver slave data receiver
+//		Data formatting is set by the DATA_FORMAT parameter. 
+//		PER_CLOCK (default) format receives bits for 0, 1, 2 .. on the same sample edge
+//		PER_CHANL format receives bits for 0, 7, 14 ..  on the same sample edge
+//
+//Reference:	XAPP585
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - PER_CLOCK and PER_CHANL descriptions swapped
+//    Rev 1.2 - Eye monitoring added, updated format
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module serdes_1_to_7_slave_idelay_sdr (clkin_p, clkin_n, datain_p, datain_n, enable_phase_detector, enable_monitor, idelay_rdy, rxclk, reset, rxclk_div, 
+                                       bitslip_finished, clk_data, rx_data, debug, bit_time_value, m_delay_1hot, rst_iserdes, eye_info) ;
+
+parameter integer 	D = 8 ;   			// Parameter to set the number of data lines
+parameter 		HIGH_PERFORMANCE_MODE = "FALSE";// Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
+parameter         	DIFF_TERM = "FALSE" ; 		// Parameter to enable internal differential termination
+parameter         	DATA_FORMAT = "PER_CLOCK" ;     // Parameter Used to determine method for mapping input parallel word to output serial words
+                                     	
+input 			clkin_p ;			// Input from LVDS clock receiver pin
+input 			clkin_n ;			// Input from LVDS clock receiver pin
+input 	[D-1:0]		datain_p ;			// Input from LVDS clock data pins
+input 	[D-1:0]		datain_n ;			// Input from LVDS clock data pins
+input 			enable_phase_detector ;		// Enables the phase detector logic when high
+input			enable_monitor ;		// Enables the monitor logic when high, note time-shared with phase detector function
+input			idelay_rdy ;			// input delays are ready
+input 			reset ;				// Reset line
+input 			rxclk ;				// Global/BUFIO rx clock network
+input 			rxclk_div ;			// Global/Regional clock input
+output 			bitslip_finished ;	 	// bitslipping finished
+output 	[6:0]		clk_data ;	 		// Clock Data
+output 	[D*7-1:0]	rx_data ;	 		// Received Data
+output 	[10*D+5:0]	debug ;	 			// debug info
+input	[4:0]		bit_time_value ;		// Calculated bit time value from 'master'
+input			rst_iserdes ;			// reset serdes input
+output	[32*D-1:0]	eye_info ;			// Eye info
+output	[32*D-1:0]	m_delay_1hot ;			// Master delay control value as a one-hot vector
+
+wire	[D*5-1:0]	m_delay_val_in ;
+wire	[D*5-1:0]	s_delay_val_in ;
+wire			rx_clk_in ;			
+reg	[1:0]		bsstate ;                 	
+reg 			bslip ;                 	
+reg 			bslipreq ;                 	
+reg 			bslipr ;                 	
+reg	[3:0]		bcount ;                 	
+wire 	[6:0] 		clk_iserdes_data ;      	
+reg 	[6:0] 		clk_iserdes_data_d ;    	
+reg 			enable ;                	
+reg 			flag1 ;                 	
+reg 			flag2 ;                 	
+reg 	[2:0] 		state2 ;			
+reg 	[3:0] 		state2_count ;			
+reg 	[5:0] 		scount ;			
+reg 			locked_out ;	
+reg 			locked_out_rt ;	
+reg			chfound ;	
+reg			chfoundc ;
+reg	[4:0]		c_delay_in ;
+reg	[4:0]		old_c_delay_in ;
+reg			local_reset ;
+wire 	[D-1:0]		rx_data_in_p ;			
+wire 	[D-1:0]		rx_data_in_n ;			
+wire 	[D-1:0]		rx_data_in_m ;			
+wire 	[D-1:0]		rx_data_in_s ;		
+wire 	[D-1:0]		rx_data_in_md ;			
+wire 	[D-1:0]		rx_data_in_sd ;	
+wire	[(7*D)-1:0] 	mdataout ;						
+wire	[(7*D)-1:0] 	mdataoutd ;			
+wire	[(7*D)-1:0] 	sdataout ;						
+reg			bslip_ackr ;		
+reg			bslip_ack ;		
+reg	[1:0]		bstate ;
+reg			data_different ;		
+reg			bs_finished ;
+reg			not_bs_finished ;
+wire	[4:0]		bt_val ;
+reg	[D*4-1:0]	s_state ;                 			
+reg			retry ;
+reg			no_clock ;
+reg	[1:0]		c_loop_cnt ;  
+
+parameter [D-1:0] 	RX_SWAP_MASK = 16'h0000 ;	// pinswap mask for input data bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
+
+assign clk_data = clk_iserdes_data ;
+assign debug = {s_delay_val_in, m_delay_val_in, bslip, c_delay_in} ;
+assign bitslip_finished = bs_finished & ~reset ;
+assign bt_val = bit_time_value ;
+
+always @ (posedge rxclk_div or posedge reset) begin	// generate local sync (rxclk_div) reset
+if (reset == 1'b1 || retry == 1'b1) begin
+	local_reset <= 1'b1 ;
+end
+else begin
+	if (idelay_rdy == 1'b0) begin
+		local_reset <= 1'b1 ;
+	end
+	else begin
+		local_reset <= 1'b0 ;
+	end
+end
+end
+
+// Bitslip state machine
+
+always @ (posedge rxclk_div)
+begin
+if (locked_out == 1'b0) begin
+	bslip <= 1'b0 ;
+	bsstate <= 1 ;
+	enable <= 1'b0 ;
+	bcount <= 4'h0 ;
+	bs_finished <= 1'b0 ;
+	not_bs_finished <= 1'b1 ;
+	retry <= 1'b0 ;
+end
+else begin
+	enable <= 1'b1 ;
+   	if (enable == 1'b1) begin
+   		if (clk_iserdes_data != 7'b1100001) begin flag1 <= 1'b1 ; end else begin flag1 <= 1'b0 ; end
+   		if (clk_iserdes_data != 7'b1100011) begin flag2 <= 1'b1 ; end else begin flag2 <= 1'b0 ; end
+     		if (bsstate == 0) begin
+   			if (flag1 == 1'b1 && flag2 == 1'b1) begin
+     		   		bslip <= 1'b1 ;						// bitslip needed
+     		   		bsstate <= 1 ;
+     		   	end
+     		   	else begin
+     		   		bs_finished <= 1'b1 ;					// bitslip done
+     		   		not_bs_finished <= 1'b0 ;				// bitslip done
+     		   	end
+		end
+   		else if (bsstate == 1) begin				
+     		   	bslip <= 1'b0 ; 
+     		   	bcount <= bcount + 4'h1 ;
+   			if (bcount == 4'hF) begin
+     		   		bsstate <= 0 ;
+     		   	end
+   		end
+   	end
+end
+end
+
+// Clock input 
+
+IBUFGDS #(
+	.DIFF_TERM 		(DIFF_TERM)) 
+iob_clk_in (
+	.I    			(clkin_p),
+	.IB       		(clkin_n),
+	.O         		(rx_clk_in));
+
+genvar i ;
+genvar j ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(1),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_cm(               	
+	.DATAOUT		(rx_clk_in_d),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_clk_in),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(c_delay_in),
+	.CNTVALUEOUT		());
+	
+ISERDESE2 #(
+	.DATA_WIDTH     	(7), 				
+	.DATA_RATE      	("SDR"), 			
+	.SERDES_MODE    	("MASTER"), 			
+	.IOBDELAY	    	("IFD"), 			
+	.INTERFACE_TYPE 	("NETWORKING")) 		
+iserdes_cm (
+	.D       		(1'b0),
+	.DDLY     		(rx_clk_in_d),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK    		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(local_reset),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8 			(),
+	.Q7 			(clk_iserdes_data[0]),
+	.Q6 			(clk_iserdes_data[1]),
+	.Q5 			(clk_iserdes_data[2]),
+	.Q4 			(clk_iserdes_data[3]),
+	.Q3 			(clk_iserdes_data[4]),
+	.Q2 			(clk_iserdes_data[5]),
+	.Q1 			(clk_iserdes_data[6]),
+	.OFB 			(),
+	.SHIFTOUT1 		(),
+	.SHIFTOUT2 		());	
+
+always @ (posedge rxclk_div) begin				// 
+	clk_iserdes_data_d <= clk_iserdes_data ;
+	if ((clk_iserdes_data != clk_iserdes_data_d) && (clk_iserdes_data != 7'h00) && (clk_iserdes_data != 7'h7F)) begin
+		data_different <= 1'b1 ;
+	end
+	else begin
+		data_different <= 1'b0 ;
+	end
+	if ((clk_iserdes_data == 7'h00) || (clk_iserdes_data == 7'h7F)) begin
+		no_clock <= 1'b1 ;
+	end
+	else begin
+		no_clock <= 1'b0 ;
+	end
+end
+	
+always @ (posedge rxclk_div) begin					// clock delay shift state machine
+	if (local_reset == 1'b1) begin
+		scount <= 6'h00 ;
+		state2 <= 0 ;
+		state2_count <= 4'h0 ;
+		locked_out <= 1'b0 ;
+		chfoundc <= 1'b1 ;
+		chfound <= 1'b0 ;
+		c_delay_in <= bt_val ;						// Start the delay line at the current bit period
+		c_loop_cnt <= 2'b00 ;	
+	end
+	else begin
+		if (scount[5] == 1'b0) begin
+			if (no_clock == 1'b0) begin
+				scount <= scount + 6'h01 ;
+			end
+			else begin
+				scount <= 6'h00 ;
+			end
+		end
+		state2_count <= state2_count + 4'h1 ;
+		if (chfoundc == 1'b1) begin
+			chfound <= 1'b0 ;
+		end
+		else if (chfound == 1'b0 && data_different == 1'b1) begin
+			chfound <= 1'b1 ;
+		end
+		if ((state2_count == 4'hF && scount[5] == 1'b1)) begin
+			case(state2) 					
+			0	: begin							// decrement delay and look for a change
+				  if (chfound == 1'b1 || (c_loop_cnt == 2'b11 && c_delay_in == 5'h00)) begin  // quit loop if we've been around a few times
+					chfoundc <= 1'b1 ;				// change found
+					state2 <= 1 ;
+					c_delay_in <= old_c_delay_in ;
+				  end
+				  else begin
+					chfoundc <= 1'b0 ;
+					old_c_delay_in <= c_delay_in ;
+					if (c_delay_in != 5'h00) begin			// check for underflow
+						c_delay_in <= c_delay_in - 5'h01 ;
+					end
+					else begin
+						c_delay_in <= bt_val ;
+						c_loop_cnt <= c_loop_cnt + 2'b01 ;
+					end
+				  end
+				  end
+			1	: begin							// add half a bit period using input information
+				  state2 <= 2 ;
+				  if (c_delay_in < {1'b0, bt_val[4:1]}) begin		// choose the lowest delay value to minimise jitter
+				   	c_delay_in <= c_delay_in + {1'b0, bt_val[4:1]} ;
+				  end
+				  else begin
+				   	c_delay_in <= c_delay_in - {1'b0, bt_val[4:1]} ;
+				  end
+				  end
+			default	: begin							// issue locked out signal
+				  locked_out <= 1'b1 ;
+			 	  end
+			endcase
+		end
+	end
+end
+			
+generate
+for (i = 0 ; i <= D-1 ; i = i+1)
+begin : loop3
+
+delay_controller_wrap # (
+	.S 			(7))
+dc_inst (                       
+	.m_datain		(mdataout[7*i+6:7*i]),
+	.s_datain		(sdataout[7*i+6:7*i]),
+	.enable_phase_detector	(enable_phase_detector),
+	.enable_monitor		(enable_monitor),
+	.reset			(not_bs_finished),
+	.clk			(rxclk_div),
+	.c_delay_in		(c_delay_in),
+	.m_delay_out		(m_delay_val_in[5*i+4:5*i]),
+	.s_delay_out		(s_delay_val_in[5*i+4:5*i]),
+	.data_out		(mdataoutd[7*i+6:7*i]),
+	.bt_val			(bt_val),
+	.del_mech		(1'b0),
+	.m_delay_1hot		(m_delay_1hot[32*i+31:32*i]),
+	.results		(eye_info[32*i+31:32*i])) ;
+
+// Data bit Receivers 
+
+IBUFDS_DIFF_OUT #(
+	.DIFF_TERM 		(DIFF_TERM)) 
+data_in (
+	.I    			(datain_p[i]),
+	.IB       		(datain_n[i]),
+	.O         		(rx_data_in_p[i]),
+	.OB         		(rx_data_in_n[i]));
+
+assign rx_data_in_m[i] = rx_data_in_p[i]  ^ RX_SWAP_MASK[i] ;
+assign rx_data_in_s[i] = ~rx_data_in_n[i] ^ RX_SWAP_MASK[i] ;
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_m(               	
+	.DATAOUT		(rx_data_in_md[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_m[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(m_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+		
+ISERDESE2 #(
+	.DATA_WIDTH     	(7), 			
+	.DATA_RATE      	("SDR"), 		
+	.SERDES_MODE    	("MASTER"), 		
+	.IOBDELAY	    	("IFD"), 		
+	.INTERFACE_TYPE 	("NETWORKING")) 	
+iserdes_m (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_md[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(mdataout[7*i+0]),
+	.Q6  			(mdataout[7*i+1]),
+	.Q5  			(mdataout[7*i+2]),
+	.Q4  			(mdataout[7*i+3]),
+	.Q3  			(mdataout[7*i+4]),
+	.Q2  			(mdataout[7*i+5]),
+	.Q1  			(mdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+IDELAYE2 #(
+	.HIGH_PERFORMANCE_MODE	(HIGH_PERFORMANCE_MODE),
+      	.IDELAY_VALUE		(0),
+      	.DELAY_SRC		("IDATAIN"),
+      	.IDELAY_TYPE		("VAR_LOAD"))
+idelay_s(               	
+	.DATAOUT		(rx_data_in_sd[i]),
+	.C			(rxclk_div),
+	.CE			(1'b0),
+	.INC			(1'b0),
+	.DATAIN			(1'b0),
+	.IDATAIN		(rx_data_in_s[i]),
+	.LD			(1'b1),
+	.LDPIPEEN		(1'b0),
+	.REGRST			(1'b0),
+	.CINVCTRL		(1'b0),
+	.CNTVALUEIN		(s_delay_val_in[5*i+4:5*i]),
+	.CNTVALUEOUT		());
+	
+ISERDESE2 #(
+	.DATA_WIDTH     	(7), 			
+	.DATA_RATE      	("SDR"), 		
+//	.SERDES_MODE    	("SLAVE"), 		
+	.IOBDELAY	    	("IFD"), 		
+	.INTERFACE_TYPE 	("NETWORKING")) 	
+iserdes_s (
+	.D       		(1'b0),
+	.DDLY     		(rx_data_in_sd[i]),
+	.CE1     		(1'b1),
+	.CE2     		(1'b1),
+	.CLK	   		(rxclk),
+	.CLKB    		(~rxclk),
+	.RST     		(rst_iserdes),
+	.CLKDIV  		(rxclk_div),
+	.CLKDIVP  		(1'b0),
+	.OCLK    		(1'b0),
+	.OCLKB    		(1'b0),
+	.DYNCLKSEL    		(1'b0),
+	.DYNCLKDIVSEL  		(1'b0),
+	.SHIFTIN1 		(1'b0),
+	.SHIFTIN2 		(1'b0),
+	.BITSLIP 		(bslip),
+	.O	 		(),
+	.Q8  			(),
+	.Q7  			(sdataout[7*i+0]),
+	.Q6  			(sdataout[7*i+1]),
+	.Q5  			(sdataout[7*i+2]),
+	.Q4  			(sdataout[7*i+3]),
+	.Q3  			(sdataout[7*i+4]),
+	.Q2  			(sdataout[7*i+5]),
+	.Q1  			(sdataout[7*i+6]),
+	.OFB 			(),
+	.SHIFTOUT1		(),
+	.SHIFTOUT2 		());
+
+for (j = 0 ; j <= 6 ; j = j+1) begin : loop1			// Assign data bits to correct serdes according to required format
+	if (DATA_FORMAT == "PER_CLOCK") begin
+		assign rx_data[D*j+i] = mdataoutd[7*i+j] ;
+	end 
+	else begin
+		assign rx_data[7*i+j] = mdataoutd[7*i+j] ;
+	end
+end
+end
+endgenerate
+endmodule

src/src/AdcDataRx/top5x2_7to1_sdr_rx.v

@@ -0,0 +1,149 @@
+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2012-2015 Xilinx, Inc.
+// This design is confidential and proprietary of Xilinx, All Rights Reserved.
+//////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor: Xilinx
+// \   \   \/    Version: 1.2
+//  \   \        Filename: top5x2_7to1_sdr_rx.v
+//  /   /        Date Last Modified:  21JAN2015
+// /___/   /\    Date Created: 2SEP2011
+// \   \  /  \
+//  \___\/\___\
+// 
+//Device: 	7-Series
+//Purpose:  	SDR top level receiver example - 2 channels of 5-bits each
+//
+//Reference:	XAPP585.pdf
+//    
+//Revision History:
+//    Rev 1.0 - First created (nicks)
+//    Rev 1.1 - BUFG added to IDELAY reference clock
+//    Rev 1.2 - Updated format (brandond)
+//
+//////////////////////////////////////////////////////////////////////////////
+//
+//  Disclaimer: 
+//
+//		This disclaimer is not a license and does not grant any rights to the materials 
+//              distributed herewith. Except as otherwise provided in a valid license issued to you 
+//              by Xilinx, and to the maximum extent permitted by applicable law: 
+//              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+//              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+//              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+//              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+//              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+//              of any kind or nature related to, arising under or in connection with these materials, 
+//              including for any direct, or any indirect, special, incidental, or consequential loss 
+//              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+//              as a result of any action brought by a third party) even if such damage or loss was 
+//              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+//  Critical Applications:
+//
+//		Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+//		requiring fail-safe performance, such as life-support or safety devices or systems, 
+//		Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+//		or any other applications that could lead to death, personal injury, or severe property or 
+//		environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+//		the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+//		to applicable laws and regulations governing limitations on product liability.
+//
+//  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ps/1ps
+
+module top5x2_7to1_sdr_rx 
+#(
+	parameter	integer	D	=	4,		// Set the number of outputs per channel to be 5 in this example
+	parameter	integer	N	=	1,       // Set the number of channels to be 2 in this example
+	parameter	DataWidth	=	14
+)
+(
+	input	reset,					// reset (active high)
+	input	refclkin,				// Reference clock for input delay control
+	input	Locked_i,				// Reference clock for input delay control
+	input	clkin1_p,	
+	input	clkin1_n,			// lvds channel 1 clock input
+	input	[D-1:0]	datain1_p,
+	input	[D-1:0]	datain1_n,			// lvds channel 1 data inputs
+	input	clkin2_p,	
+	input	clkin2_n,			// lvds channel 2 clock input
+	input	[D-1:0]	datain2_p,	
+	input	[D-1:0]	datain2_n,			// lvds channel 2 data inputs
+	output	reg	dummy,
+	output	[27:0]	dout,
+	output	DivClk_o
+	// output	[DataWidth-1:0]	dout
+);// Dummy output for test
+			
+		
+wire	refclkint; 		
+wire	rx_mmcm_lckdps;		
+wire	[1:0]	rx_mmcm_lckdpsbs;	
+wire	rxclk_div;		
+wire	clkin_p;			
+wire	clkin_n;			
+wire	[D*N-1:0]	datain_p;		
+wire	[D*N-1:0]	datain_n;		
+// wire	[N*DataWidth-1:0]	rxdall;			
+wire	[27:0]	rxdall;			
+wire	delay_ready;		
+wire	rx_mmcm_lckd;	
+
+IDELAYCTRL	icontrol 
+(              			// Instantiate input delay control block
+	.REFCLK	(refclkin),
+	.RST	(~Locked_i),
+	.RDY	(delay_ready)
+);
+
+// Input clock and data for 2 channels
+assign	clkin_p		=	clkin1_p;
+assign	clkin_n		=	clkin1_n;
+assign	datain_p	=	datain1_p;
+assign	datain_n	=	datain1_n;
+
+assign	dout		=	rxdall;
+assign	DivClk_o	=	rxclk_div;
+
+n_x_serdes_1_to_7_mmcm_idelay_sdr 
+#(
+	.N	(N),
+	.SAMPL_CLOCK	("BUF_G"),
+	.PIXEL_CLOCK	("BUF_G"),
+	.USE_PLL		("TRUE"),
+	.HIGH_PERFORMANCE_MODE	("FALSE"),
+	.D	(D),				// Number of data lines
+	.CLKIN_PERIOD	(40.000),			// Set input clock period
+	.MMCM_MODE		(4),				// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
+	.DIFF_TERM		("TRUE"),
+	// .DATA_FORMAT	("PER_CLOCK")
+	.DATA_FORMAT	("PER_CHANL")
+) 			// PER_CLOCK or PER_CHANL data formatting
+ReceiverModule	
+(                          
+	.clkin_p	(clkin_p),
+	.clkin_n	(clkin_n),
+	.datain_p	(datain_p),
+	.datain_n	(datain_n),
+	.enable_phase_detector	(1'b0),
+	.rxclk		(),
+	.idelay_rdy	(delay_ready),
+	.rxclk_div	(rxclk_div),
+	.reset		(reset),
+	.rx_mmcm_lckd		(rx_mmcm_lckd),
+	.rx_mmcm_lckdps		(rx_mmcm_lckdps),
+	.rx_mmcm_lckdpsbs	(rx_mmcm_lckdpsbs),
+	.clk_data	(),
+	.rx_data	(rxdall),
+	.bit_rate_value		(16'h0350),			// required bit rate value
+	.bit_time_value		(),
+	.status		(),
+	.debug		()
+);
+      	
+endmodule

src/src/ClkGen/Clk200Gen.v

@@ -0,0 +1,86 @@
+module Clk200Gen 
+(
+    input	Clk_i,
+    input	Rst_i,
+	output	Clk200_o,
+	output	Clk10Timers_o,
+	output	Clk150_o,
+	
+	output	Locked_o
+);
+
+wire	ClkFb;
+wire	rxFb;
+
+PLLE2_ADV #(
+      	.BANDWIDTH		("OPTIMIZED"),
+      	.CLKFBOUT_MULT		(8),
+      	.CLKFBOUT_PHASE		(0.0),
+      	.CLKIN1_PERIOD		(8),
+      	.CLKIN2_PERIOD		(),
+      	.CLKOUT0_DIVIDE		(20),
+      	.CLKOUT0_DUTY_CYCLE	(0.5),
+      	.CLKOUT0_PHASE		(0.0),
+      	.CLKOUT1_DIVIDE		(120),
+      	.CLKOUT1_DUTY_CYCLE	(0.5),
+      	.CLKOUT1_PHASE		(0.0),
+      	.CLKOUT2_DIVIDE		(12),
+      	.CLKOUT2_DUTY_CYCLE	(0.5),
+      	.CLKOUT2_PHASE		(0.0),
+      	.CLKOUT3_DIVIDE		(120),
+      	.CLKOUT3_DUTY_CYCLE	(0.5),
+      	.CLKOUT3_PHASE		(0.0),
+      	.CLKOUT4_DIVIDE		(7),
+      	.CLKOUT4_DUTY_CYCLE	(0.5),
+      	.CLKOUT4_PHASE		(0.0),
+      	.CLKOUT5_DIVIDE		(7),
+      	.CLKOUT5_DUTY_CYCLE	(0.5),
+      	.CLKOUT5_PHASE		(0.0),
+      	.COMPENSATION		("BUF_IN"),
+      	.DIVCLK_DIVIDE		(1),
+      	.REF_JITTER1		(0.100))
+CommonPll (
+      	.CLKFBOUT		(ClkFb),
+      	.CLKOUT0		(rx_mmcmout_200),
+      	.CLKOUT1		(rx_mmcmout_10),
+      	.CLKOUT2		(rx_mmcmout_100),
+      	.CLKOUT3		(),
+      	.CLKOUT4		(),
+      	.CLKOUT5		(),
+      	.DO				(),
+      	.DRDY			(),
+      	.PWRDWN			(1'b0),
+      	.LOCKED			(Locked_o),
+      	.CLKFBIN		(rxFb),
+      	.CLKIN1			(Clk_i),
+      	.CLKIN2			(1'b0),
+      	.CLKINSEL		(1'b1),
+      	.DADDR			(7'h00),
+      	.DCLK			(1'b0),
+      	.DEN			(1'b0),
+      	.DI				(16'h0000),
+      	.DWE			(1'b0),
+      	.RST			(1'b0)
+) ;
+
+
+BUFG	bufg_mmcm_Fb (.I(ClkFb), .O(rxFb)) ;
+
+BUFG	ctrlClk200 (.I(rx_mmcmout_200), .O(Clk200_o)) ;
+BUFG	ctrlClk10 (.I(rx_mmcmout_10), .O(Clk10Timers_o)) ;
+BUFG	ctrlClk100 (.I(rx_mmcmout_100), .O(Clk150_o)) ;
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/DitherGen/DitherGenv2.v

@@ -0,0 +1,131 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:		Churbanov S.
+// 
+// Create Date:    10:00:14 13/08/2019 
+// Design Name: 
+// Module Name:    DspPpiOut 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DitherGenv2
+#(	
+	parameter	CmdDataRegWith		=	24,
+	parameter	FrAmpWordWidth		=	8,
+	parameter	RefFreqDiv			=	5
+)
+(
+	input	Rst_i,
+	input	Clk_i,	
+	
+	input	[CmdDataRegWith-1:0]	DitherCmd_i,
+	output	DitherCtrlT2R2_o,
+	output	DitherCtrlT1R1_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	
+	wire	[FrAmpWordWidth-1:0]	ditherFreq	=	DitherCmd_i[CmdDataRegWith-1-:FrAmpWordWidth];
+	
+	wire	[4-1:0]	ditherAmpT2R2	=	DitherCmd_i[15:12];
+	wire	[4-1:0]	ditherAmpT1R1	=	DitherCmd_i[11:8];
+	wire	[4-1:0]	rampLimit		=	DitherCmd_i[7:4];
+	
+	wire	ditherEnT2R2	=	DitherCmd_i[1];
+	wire	ditherEnT1R1	=	DitherCmd_i[0];
+	
+	wire	[3:0]	ncoArray	[15:0];
+	
+	assign	ncoArray	[0]		=	0;
+	assign	ncoArray	[1]		=	1;
+	assign	ncoArray	[2]		=	2;
+	assign	ncoArray	[3]		=	3;
+	assign	ncoArray	[4]		=	4;
+	assign	ncoArray	[5]		=	5;
+	assign	ncoArray	[6]		=	6;
+	assign	ncoArray	[7]		=	7;
+	assign	ncoArray	[8]		=	8;
+	assign	ncoArray	[9]		=	7;
+	assign	ncoArray	[10]	=	6;
+	assign	ncoArray	[11]	=	5;
+	assign	ncoArray	[12]	=	4;
+	assign	ncoArray	[13]	=	3;
+	assign	ncoArray	[14]	=	2;
+	assign	ncoArray	[15]	=	1;
+	
+	reg	[3:0]	sawCnt;
+	
+	reg	[FrAmpWordWidth-1:0]	currStateT2R2;
+	reg	[FrAmpWordWidth-1:0]	currStateT1R1;
+	
+	wire	[3:0]	ncoSignalT2R2	=	ncoArray[currStateT2R2[FrAmpWordWidth-1-:4]];
+	wire	[3:0]	ncoSignalT1R1	=	ncoArray[currStateT1R1[FrAmpWordWidth-1-:4]];
+
+	wire	dithGenT2R2	=	((ncoSignalT2R2>>ditherAmpT2R2)>sawCnt)	?	1'b1:1'b0;
+	wire	dithGenT1R1	=	((ncoSignalT1R1>>ditherAmpT1R1)>sawCnt)	?	1'b1:1'b0;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	DitherCtrlT2R2_o	=	(ditherEnT2R2)	?	dithGenT2R2:1'b0;
+	assign	DitherCtrlT1R1_o	=	(ditherEnT1R1)	?	dithGenT1R1:1'b0;
+//================================================================================
+//  CODING
+//================================================================================	
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(sawCnt	!=	rampLimit)	begin
+			sawCnt	<=	sawCnt	+1;
+		end	else	begin
+			sawCnt	<=	0;
+		end
+	end	else	begin
+		sawCnt	<=	0;
+	end
+end
+
+wire	Clk5=(sawCnt<=10/2-1)?	1'b1:1'b0;
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(sawCnt	==rampLimit)	begin
+			currStateT2R2	<=	currStateT2R2+ditherFreq;
+			currStateT1R1	<=	currStateT1R1+ditherFreq;
+		end
+	end	else	begin
+		currStateT2R2	<=0;
+		currStateT1R1	<=0;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/ExtDspInterface/DspInterface.v

@@ -0,0 +1,263 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    16:37:06 07/11/2019 
+// design name: 
+// module name:    dsp_linkport_interface 
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 					
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	DspInterface
+#(	
+	parameter	AdcDataWidth	=	14,	
+	parameter	ExtAdcDataWidth	=	16,	
+	parameter	ODataWidth		=	16,	
+	parameter	ResultWidth		=	40,
+	parameter	ChNum			=	16,
+	parameter	CmdRegWidth		=	32,
+	parameter	CmdDataRegWith	=	24,
+	parameter	HeaderWidth		=	7,
+	parameter	DataCntWidth	=	5,
+	parameter	CmdWidth		=	3
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+	input	OscWind_i,
+	input	StartMeasDsp_i,
+	input	DspReadyForRx_i,
+	input	[31:0]	MeasNum_i,
+	
+	input	Mosi_i,
+	input	Sck_i,
+	input	Ss_i,
+	
+	input	Mode_i,
+	input	[CmdWidth-2:0]		PortSel_i,
+	input	[CmdWidth-1:0]		DecimFactor_i,
+	
+	input	[CmdRegWidth-9:0]	IfFtwL_i,
+	input	[CmdRegWidth-9:0]   IfFtwH_i,
+	
+	output	OscDataRdFlag_o,
+	input	[AdcDataWidth-1:0]	Adc1ChT1Data_i,	
+	input	[AdcDataWidth-1:0]	Adc1ChR1Data_i,	
+	input	[AdcDataWidth-1:0]	Adc2ChR2Data_i,	
+	input	[AdcDataWidth-1:0]	Adc2ChT2Data_i,	
+	
+	output	Mosi_o,
+	output	Sck_o,
+	output	Ss0_o,
+	output	Ss1_o,
+	input	Miso_i,
+	output	Miso_o,
+
+	
+	output	[CmdRegWidth-1:0]	CmdDataReg_o,
+	output	CmdDataVal_o,
+	
+	input	[CmdDataRegWith-1:0]	AnsReg_i,
+	output	[HeaderWidth-1:0]		AnsAddr_o,	
+
+	output	LpOutFs_o,
+	output	LpOutClk_o,
+	output	[ODataWidth-1:0]	LpOutData_o,
+	
+	input	[ResultWidth-1:0]	Adc1T1ImResult_i,
+	input	[ResultWidth-1:0]	Adc1T1ReResult_i,
+	input	[ResultWidth-1:0]	Adc1R1ImResult_i,
+	input	[ResultWidth-1:0]	Adc1R1ReResult_i,	
+	
+	input	[ResultWidth-1:0]	Adc2R2ImResult_i,
+	input	[ResultWidth-1:0]	Adc2R2ReResult_i,
+	input	[ResultWidth-1:0]	Adc2T2ImResult_i,
+	input	[ResultWidth-1:0]	Adc2T2ReResult_i,
+	input	[ChNum-1:0]			ServiseRegData_i,
+
+	input	LpOutStart_i
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire	[ResultWidth*(ChNum*2)-1:0]	measDataBus;
+	wire	[ResultWidth*(ChNum*2)-1:0]	fftDataBus;
+	wire	[ResultWidth*(ChNum*2)-1:0]	bypassDataBus;
+	
+	reg		[ResultWidth*(ChNum*2)-1:0]	dataForFifo;
+	reg		dataForFifoVal;
+	
+	wire	fftDataBusVal;
+	wire	bypassDataBusVal;
+	
+	wire	[ResultWidth*(ChNum*2)-1:0]	measDataBusTx;
+	wire	measDataValTx;
+	
+	wire	ppiBusy;
+	
+	reg	signed	[15:0]	adc1ChT1DataExt;	
+	reg	signed	[15:0]	adc1ChR1DataExt;	
+	reg	signed	[15:0]	adc2ChR2DataExt;	
+	reg	signed	[15:0]	adc2ChT2DataExt;
+	
+	reg		signed	[AdcDataWidth-1:0]	currDataChannel;
+	wire	signed	[AdcDataWidth-1:0]	testData;
+	
+	wire	signed	[15:0]	filteredDecimDataI;
+	wire	signed	[15:0]	filteredDecimDataQ;
+	wire	filteredDecimDataVal;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+
+	assign	measDataBus	[(ResultWidth*(ChNum*2-7))-1-:ResultWidth]	=	Adc1T1ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-6))-1-:ResultWidth]	=	Adc1T1ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-5))-1-:ResultWidth]	=	Adc1R1ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-4))-1-:ResultWidth]	=	Adc1R1ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-3))-1-:ResultWidth]	=	Adc2T2ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-2))-1-:ResultWidth]	=	Adc2T2ReResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-1))-1-:ResultWidth]	=	Adc2R2ImResult_i;
+	assign	measDataBus	[(ResultWidth*(ChNum*2-0))-1-:ResultWidth]	=	Adc2R2ReResult_i;
+	
+	assign	OscDataRdFlag_o	=	measDataValTx;
+	
+//================================================================================
+//	CODING
+//================================================================================
+
+reg	oscWindR;
+reg	[15:0]	testPatternData;
+
+wire	oscWindNeg	=	(!OscWind_i&oscWindR);
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		oscWindR	<=	OscWind_i;
+	end	else	begin
+		oscWindR	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(oscWindNeg)	begin
+			testPatternData	<=	~testPatternData;
+		end
+	end	else	begin
+		testPatternData	<=	16'h1fff;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case(PortSel_i)
+			0:	begin
+					// currDataChannel	<=	testPatternData;
+					currDataChannel	<=	Adc1ChT1Data_i;
+				end
+			1:	begin
+					currDataChannel	<=	Adc1ChR1Data_i;
+				end
+			2:	begin
+					currDataChannel	<=	Adc2ChT2Data_i;
+				end
+			3:	begin
+					currDataChannel	<=	Adc2ChR2Data_i;
+				end
+		endcase
+	end	else	begin
+		currDataChannel	<=	0;
+	end
+end
+
+
+SlaveSpi
+#(	
+	.CmdRegWidth	(CmdRegWidth),
+	.DataCntWidth	(DataCntWidth),
+	.HeaderWidth	(HeaderWidth)
+)
+DspSlaveSpi
+(
+	.Clk_i		(Clk_i),
+	.Rst_i		(Rst_i),
+
+	.Data_o		(CmdDataReg_o),
+	.Val_o		(CmdDataVal_o),
+	
+	.Mosi_i		(Mosi_i),
+	.Sck_i		(Sck_i),
+	.Ss_i		(Ss_i),
+	
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o),
+	.Ss0_o		(Ss0_o),
+	.Ss1_o		(Ss1_o),
+	
+	.AnsAddr_o	(AnsAddr_o),
+	.AnsReg_i	(AnsReg_i),
+	
+	.Miso_i		(Miso_i),
+	.Miso_o		(Miso_o)
+);
+
+MeasDataFifoWrapper		
+#(	
+	.DataWidth	(ResultWidth),
+	.ChNum		(ChNum)
+)
+MeasDataFifoInst
+(
+	.Clk_i			(Clk_i), 
+	.Rst_i			(Rst_i),	
+	.PpiBusy_i		(ppiBusy),	
+	.MeasNum_i		(MeasNum_i),	
+	.StartMeasDsp_i	(StartMeasDsp_i),	
+	.DspReadyForRx_i(DspReadyForRx_i),	
+	.MeasDataBus_i	(measDataBus),
+	.MeasDataVal_i	(LpOutStart_i),	
+	
+	.MeasDataBus_o	(measDataBusTx),
+	.MeasDataVal_o	(measDataValTx)
+);
+
+DspPpiOut	
+#(	
+	.ODataWidth		(ODataWidth),	
+	.ResultWidth	(ResultWidth), 
+	.ChNum			(ChNum)
+)
+MeasDataPpiOut
+(
+	.Rst_i				(Rst_i),	
+	.Clk_i				(Clk_i),		
+	
+	.MeasDataBus_i		(measDataBusTx),
+	.ServiseRegData_i	(ServiseRegData_i),
+	
+	.PpiBusy_o			(ppiBusy),
+	.LpOutStart_i		(measDataValTx),
+	
+	.LpOutClk_o			(LpOutClk_o),
+	.LpOutFs_o			(LpOutFs_o),
+	.LpOutData_o		(LpOutData_o)
+);
+
+endmodule
+
+
+
+
+
+
+

src/src/ExtDspInterface/DspPpiOut.v

@@ -0,0 +1,160 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:		Churbanov S.
+// 
+// Create Date:    10:00:14 13/08/2019 
+// Design Name: 
+// Module Name:    DspPpiOut 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DspPpiOut
+#(	
+	parameter	ODataWidth		=	16,	
+	parameter	ResultWidth		=	40, 
+	parameter	ChNum			=	8,
+	localparam	DataBusWidth	=	((ChNum*2)+1)*ResultWidth,
+	localparam	ServisePattern	=	32'hABCD
+)
+(
+	input	Rst_i,
+	input	Clk_i,	
+	
+	input	[ChNum-1:0]	ServiseRegData_i,
+	input	[ResultWidth*(ChNum*2)-1:0]	MeasDataBus_i,
+	
+	input	LpOutStart_i,
+	output	PpiBusy_o,
+	
+	output	LpOutClk_o,
+	output	LpOutFs_o,
+	output	[ODataWidth-1:0]	LpOutData_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	lpDataRst;
+	reg	[5:0]	txCnt	=	6'd0;	
+	reg	[DataBusWidth-1:0]	lpDataBuf;
+	reg	dataShEn;
+	reg	dataValid;
+	
+	reg	lpOutFs;
+	reg	ppiBusy;
+	
+	wire	oddrCe = (txCnt	<=	6'd19 && dataValid)	?	1'b1:1'b0;
+	
+	wire	[7:0]	ampEnT1	=	{{7{1'b0}},ServiseRegData_i[0]};
+	wire	[7:0]	ampEnR1	=	{{7{1'b0}},ServiseRegData_i[1]};
+	wire	[7:0]	ampEnR2	=	{{7{1'b0}},ServiseRegData_i[2]};
+	wire	[7:0]	ampEnT2	=	{{7{1'b0}},ServiseRegData_i[3]};
+	
+	wire	[31:0]	serviceData	=	{ampEnR2,ampEnT2,ampEnR1,ampEnT1};
+	
+	wire	outDataVal	=	(txCnt	<=	18	&&	txCnt	!=	0);
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	LpOutData_o	=	lpDataBuf[ODataWidth-1:0];
+	assign	LpOutFs_o	=	lpOutFs;
+	assign	PpiBusy_o	=	ppiBusy;
+//================================================================================
+//  CODING
+//================================================================================	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(LpOutStart_i)	begin
+			ppiBusy	<=	1'b1;
+		end	else	if	(!dataValid)	begin
+			ppiBusy	<=	1'b0;
+		end
+	end	else	begin
+		ppiBusy	<=	1'b0;
+	end
+end
+
+always	@(posedge Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(LpOutStart_i)	begin	
+			txCnt	<=	6'd19;
+		end	else	if	(dataValid)	begin
+			txCnt	<=	txCnt	-	6'd1;
+		end
+	end	else	begin
+		txCnt	<=	6'd0;
+	end
+end
+
+always	@(*)	begin
+	case (txCnt)
+		6'd19:	begin
+					dataShEn	=	1'b0;
+					dataValid	=	1'b1;
+					lpOutFs		=	1'b0;
+				end
+		6'd18:	begin 
+					dataShEn	=	1'b1;
+					dataValid	=	1'b1;
+					lpOutFs		=	1'b1;
+				end
+		6'd17:	begin 
+					dataShEn	=	1'b1;
+					dataValid	=	1'b1;
+					lpOutFs		=	1'b0;
+				end
+		6'd0:	begin	
+					dataShEn	=	1'b0;
+					dataValid	=	1'b0;
+					lpOutFs		=	1'b0;
+				end	
+		default: 
+			begin
+				dataShEn	=	1'b1;
+				dataValid	=	1'b1;
+				lpOutFs		=	1'b0;
+			end
+	endcase
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(txCnt	==	6'd19)	begin
+			lpDataBuf	<=	{serviceData,MeasDataBus_i};
+		end	else	if	(dataShEn)	begin
+			lpDataBuf	<=	{{ODataWidth{1'b0}},lpDataBuf[DataBusWidth-1:ODataWidth]};
+		end
+	end	else	begin
+		lpDataBuf	<=	{DataBusWidth{1'b0}};
+	end
+end
+//================================================================================
+//  INSTANTIATIONS
+//================================================================================		
+ODDR2
+#(
+	.DDR_ALIGNMENT("NONE"),
+	.INIT	(1'b0),
+	.SRTYPE	("SYNC")
+) clk_i10OutInst (
+	.Q		(LpOutClk_o),
+	.C0		(Clk_i),
+	.C1		(~Clk_i),
+	.CE		(1'b1),
+	.D0		(1'b1),
+	.D1		(1'b0),
+	.R		(1'b0),
+	.S		(1'b0)
+);		
+
+endmodule

src/src/ExtDspInterface/SlaveSpi.v

@@ -0,0 +1,213 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 17.09.2020 14:18:14
+// Design Name: 
+// Module Name: SlaveSpi
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module	SlaveSpi
+#(	
+	parameter	CmdRegWidth			=	32,
+	parameter	DataCntWidth		=	6,
+	parameter	HeaderWidth			=	7,
+	parameter	CmdDataRegWith		=	24,
+	parameter	Adc0DirAccessAddr	=	7'h13,
+	parameter	Adc1DirAccessAddr	=	7'h14
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	output	reg	[CmdRegWidth-1:0]	Data_o,
+	output	reg	Val_o,
+	
+	//-----------------------------------
+	//input Spi lines from ext. Dsp
+	input	Mosi_i,
+	input	Sck_i,
+	input	Ss_i,
+	//-----------------------------------
+	
+	//-----------------------------------
+	output	Mosi_o,
+	output	Sck_o,
+	output	Ss0_o,
+	output	Ss1_o,
+	//-----------------------------------
+	
+	output	[HeaderWidth-1:0]		AnsAddr_o,
+	input	[CmdDataRegWith-1:0]	AnsReg_i,
+	
+	input	Miso_i,
+	output	Miso_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	reg	[CmdRegWidth-1:0]		dataCaptReg;
+	reg	[DataCntWidth-1:0]		dataCnt;
+	reg	[HeaderWidth-1:0]		ansAddr;
+	reg	spiMode;
+	wire	directTransit	=	(ansAddr	==	Adc0DirAccessAddr)|(ansAddr	==	Adc1DirAccessAddr);
+	reg	txWind;
+	reg	[4:0]	txCnt;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+	assign	Mosi_o		=	(!spiMode&directTransit)?	Mosi_i:1'b1;
+	assign	Sck_o		=	(directTransit)?	Sck_i:1'b0;
+	assign	Ss0_o		=	(directTransit&&(ansAddr==Adc0DirAccessAddr))?	Ss_i:1'b1;
+	assign	Ss1_o		=	(directTransit&&(ansAddr==Adc1DirAccessAddr))?	Ss_i:1'b1;
+	assign	AnsAddr_o	=	ansAddr;
+	assign	Miso_o		=	txWind?	AnsReg_i[txCnt]:1'b0;
+//================================================================================
+//	CODING
+//================================================================================
+always	@(posedge	Sck_i)	begin
+	if	(~Ss_i)	begin
+		dataCaptReg	<=	{dataCaptReg[CmdRegWidth-2:0],Mosi_i};
+	end	else	begin
+		dataCaptReg	<=	dataCaptReg;
+	end
+end
+
+always	@(posedge	Sck_i)	begin
+	if	(~Rst_i)	begin
+		if	(~Ss_i)	begin
+			dataCnt	<=	dataCnt	+	5'd1;
+		end
+	end	else	begin
+		dataCnt	<=	0;
+	end
+end
+
+always	@(posedge	Sck_i)	begin
+	if	(~Rst_i)	begin
+		if	(dataCnt	==	5'd1)	begin
+			if	(dataCaptReg[CmdRegWidth-CmdRegWidth])	begin
+				spiMode	<=	1'b1;
+			end	else	begin
+				spiMode	<=	1'b0;
+			end
+		end
+	end	else	begin
+		spiMode	<=	1'b0;
+	end
+end
+
+always	@(negedge Sck_i)	begin
+	if	(~Rst_i)	begin
+		if	(~Ss_i)	begin
+			if	(dataCnt	==	5'd8)	begin
+				ansAddr	<=	dataCaptReg[CmdRegWidth-26-:HeaderWidth];
+			end	else	if	(dataCnt	==	5'd0)	begin
+				ansAddr	<=	7'h7F;
+			end
+		end	else	begin
+			ansAddr	<=	7'h7F;	
+		end
+	end	else	begin
+		ansAddr	<=	7'h7F;	
+	end
+end
+
+//================================================================================
+//	Generating output signals
+//================================================================================
+reg	ssReg;
+reg	ssRegR;
+
+always	@(posedge	Clk_i)	begin
+	ssReg	<=	Ss_i;
+	ssRegR	<=	ssReg;
+end
+
+reg	ssPos;
+
+always	@(posedge	Clk_i)	begin
+	ssPos	<=	ssReg&!ssRegR;
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!directTransit&!spiMode)	begin
+		if	(ssReg&!ssRegR)	begin
+			Val_o	<=	1'b1;
+		end	else	begin
+			Val_o	<=	0;
+		end
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(((ansAddr	!=	Adc0DirAccessAddr)|(ansAddr	!=	Adc1DirAccessAddr))&!spiMode)	begin
+		if	(ssReg&!ssRegR)	begin
+			Data_o	<=	dataCaptReg;
+		end	
+	end
+end
+
+always	@(*)	begin
+	if	(spiMode	&	!Ss_i)	begin
+		if	(dataCnt	>=5'd8|dataCnt	==	0)	begin
+			txWind	=	1'b1;
+		end	else	begin
+			txWind	=	1'b0;
+		end
+	end	else	begin
+		txWind	=	1'b0;
+	end
+end
+
+always	@(negedge	Sck_i)	begin
+	if	(txWind)	begin
+		if	(~Ss_i	&	txWind	&	txCnt!=	0)	begin
+			txCnt	<=	txCnt	-	5'd1;
+		end	else	begin
+			txCnt	<=	5'd24;
+		end
+	end	else	begin
+		txCnt	<=	5'd24;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/GainOverloadControl/GainControl.v

@@ -0,0 +1,172 @@
+`timescale 1ns / 1ps
+(* KEEP = "TRUE" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:    gain_master 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module GainControl
+#(	
+	parameter	AdcNcoMultWidth	=	35,
+	parameter	ThresholdWidth	=	24,
+	parameter	AdcDataWidth	=	14,
+	parameter	MeasPeriod		=	32
+)	
+(
+	input	Rst_i,
+	input	Clk_i,	
+	input	StartMeas_i,
+	input	GainAutoEn_i,
+	
+	input	signed	[AdcNcoMultWidth-1:0]	AdcCos_i,
+	input	signed	[AdcNcoMultWidth-1:0]	AdcSin_i,
+	
+	input	[ThresholdWidth-1:0]	GainLowThreshold_i,
+	input	[ThresholdWidth-1:0]	GainHighThreshold_i,
+	
+	output	GainNewState_o,
+	output	SensEn_o,
+	output	MeasStart_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+	localparam	CntWidth		=	32;
+	localparam	Delay			=	100;
+	localparam	AverageDelay	=	MeasPeriod+Delay-1;
+	localparam	SumWidth		=	AdcNcoMultWidth+6-1;
+//================================================================================
+//  REG/WIRE
+	reg		[CntWidth-1:0]	measCnt;
+	
+	reg		signed	[SumWidth-1:0]	adcSinSum;			
+	reg		signed	[SumWidth-1:0]	adcCosSum;	
+	
+	reg		measWind;
+	wire	measEnd	=	(measCnt==AverageDelay-1)&measWind;
+	
+	reg	gainNewStateR;
+	reg		gainNewState;
+	wire	sensEn	=	((gainNewStateR& (!gainNewState))|(!gainNewStateR&gainNewState));
+	
+	reg		signed	[SumWidth-1:0]	sinShifted;
+	reg		signed	[SumWidth-1:0]	cosShifted;
+	
+	wire	signed	[ThresholdWidth-5:0]		sinShiftedCut	=	sinShifted	[(SumWidth-1)-:20];		//width is 20
+	wire	signed	[ThresholdWidth-5:0]		cosShiftedCut	=	cosShifted	[(SumWidth-1)-:20];		//width is 20
+	
+	wire	signed	[(ThresholdWidth*2)-9:0]	sinSumSquared	=	(sinShiftedCut*sinShiftedCut);	// width is 40
+	wire	signed	[(ThresholdWidth*2)-9:0]	cosSumSquared	=	(cosShiftedCut*cosShiftedCut);	// width is 40
+	
+	wire	signed	[(ThresholdWidth*2)-9:0]	sumSquared	=	(cosSumSquared+sinSumSquared);	//width is 40	
+	
+	wire	[(ThresholdWidth*2)-9:0]	lowThresholdCompl	=	{10'b0,GainLowThreshold_i,6'b0};
+	wire	[(ThresholdWidth*2)-9:0]	highThresholdCompl	=	{10'b0,GainHighThreshold_i,6'b0};
+	
+	wire	accWind	=	(measCnt>0	&	measCnt	<=MeasPeriod-2);
+//================================================================================
+//  ASSIGNMENTS
+	assign	GainNewState_o	=	gainNewState;
+	assign	SensEn_o		=	sensEn;
+	assign	MeasStart_o		=	GainAutoEn_i?	measEnd:StartMeas_i;
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(GainAutoEn_i)	begin
+			if	(StartMeas_i)	begin
+				measWind	<=	1'b1;
+			end	else	if	(measEnd)	begin
+				measWind	<=	1'b0;
+			end
+		end	else	begin
+			measWind	<=	1'b0;
+		end
+	end	else	begin
+		measWind	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(measWind)	begin
+		if	(measCnt	==	MeasPeriod-2)	begin
+			sinShifted	<=	adcSinSum>>>2;
+			cosShifted	<=	adcCosSum>>>2;
+		end
+	end	
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(measWind)	begin
+			if	(measCnt	!= AverageDelay-1)	begin
+				measCnt	<=	measCnt	+	3'd1;	
+			end
+		end	else	begin
+			measCnt	<=	3'd0;
+		end
+	end	else	begin
+		measCnt	<=	3'd0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!accWind)	begin
+			adcSinSum	<=	AdcSin_i;
+			adcCosSum	<=	AdcCos_i;
+		end	else	begin
+			adcSinSum	<=	adcSinSum	+	AdcSin_i;
+			adcCosSum	<=	adcCosSum	+	AdcCos_i;
+		end
+	end	else	begin
+		adcSinSum	<=	0;	
+		adcCosSum	<=	0;
+	end
+end
+
+
+always	@(posedge	Clk_i)	begin	
+	if	(!Rst_i)	begin
+		if	(GainAutoEn_i)	begin
+			if	(measCnt	==	MeasPeriod-1)	begin
+				if	(gainNewState)	begin
+					if	(sumSquared	>	highThresholdCompl)	begin
+						gainNewState	<=	1'b0;
+					end	else	begin
+						gainNewState	<=	gainNewState;
+					end
+				end	else	begin
+					if	(sumSquared	<	lowThresholdCompl)	begin
+						gainNewState	<=	1'b1;
+					end	else	begin
+						gainNewState	<=	gainNewState;
+					end
+				end
+			end
+		end	else	begin
+			gainNewState	<=	1'b0;
+		end
+	end	else	begin
+		gainNewState	<=	1'b0;
+	end
+	
+	gainNewStateR	<=	gainNewState;
+end
+
+endmodule

src/src/GainOverloadControl/GainControlWrapper.v

@@ -0,0 +1,105 @@
+`timescale 1ns / 1ps
+// (* use_dsp48	=	"yes"*)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:    gain_master 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module GainControlWrapper
+#(	
+	parameter	AdcDataWidth		=	14,
+	parameter	ThresholdWidth		=	24,
+	parameter	PhIncWidth			=	32,
+	parameter	IfNcoOutWidth		=	18,
+	parameter	MeasPeriod			=	32
+)	
+(
+	input	Rst_i,
+	input	Clk_i,	
+	input	StartMeas_i,
+	
+	input	[IfNcoOutWidth-1:0]	NcoSin_i,
+	input	[IfNcoOutWidth-1:0]	NcoCos_i,
+	
+	input	[AdcDataWidth-1:0]		AdcData_i,
+	
+	input	[ThresholdWidth-1:0]	GainLowThreshold_i,
+	input	[ThresholdWidth-1:0]	GainHighThreshold_i,
+	input	GainAutoEn_i,
+	input	GainManualState_i,
+	
+	output	AmpEnNewState_o,
+	output	SensEn_o,
+	output	MeasStart_o
+);
+
+//================================================================================
+//  LOCALPARAM
+	localparam	MultDataWidth	=	36;
+	
+//================================================================================
+	wire	[MultDataWidth-1:0]	adcSin;
+	wire	[MultDataWidth-1:0]	adcCos;
+
+	wire	[MultDataWidth-1:0]	adcSinCut	=	adcSin	[MultDataWidth-1:0];
+	wire	[MultDataWidth-1:0]	adcCosCut	=	adcCos	[MultDataWidth-1:0];
+	wire	gainNewState;
+//================================================================================
+//  ASSIGNMENTS
+	assign	AmpEnNewState_o	=	(GainAutoEn_i)?	gainNewState:GainManualState_i;
+//================================================================================
+//  CODING
+
+MultModule		
+#(	
+	.AdcDataWidth	(AdcDataWidth),
+	.IfNcoOutWidth	(IfNcoOutWidth)
+)	
+Adc1Mult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.AdcData_i	(AdcData_i),
+	.Sin_i		(NcoSin_i),
+	.Cos_i		(NcoCos_i),
+	.AdcSin_o	(adcSin),
+	.AdcCos_o	(adcCos)
+);
+
+
+GainControl		
+#(	
+	.AdcNcoMultWidth	(MultDataWidth),
+	.ThresholdWidth		(ThresholdWidth),
+	.AdcDataWidth		(AdcDataWidth),
+	.MeasPeriod			(MeasPeriod)
+)
+GainMaster
+(
+	.Rst_i					(Rst_i),
+	.StartMeas_i			(StartMeas_i),
+	.GainAutoEn_i			(GainAutoEn_i),
+	.Clk_i					(Clk_i),
+	.AdcCos_i				(adcSin),
+	.AdcSin_i				(adcCos),
+	.GainLowThreshold_i		(GainLowThreshold_i),
+	.GainHighThreshold_i	(GainHighThreshold_i),
+	.GainNewState_o			(gainNewState),
+	.SensEn_o				(SensEn_o),
+	.MeasStart_o			(MeasStart_o)
+); 
+endmodule

src/src/GainOverloadControl/OverloadDetect.v

@@ -0,0 +1,101 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:  
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module OverloadDetect
+#(	
+	parameter	ThresholdWidth	=	24,
+	parameter	AdcDataWidth	=	14,
+	parameter	MeasPeriod		=	32
+)	
+(
+	input	Rst_i,
+	input	Clk_i,	
+	input	[AdcDataWidth-1:0]		AdcData_i,
+	input	[ThresholdWidth-1:0]	OverThreshold_i,
+	output	Overload_o
+);
+
+//================================================================================
+//  LOG2 FUNCTION
+	function integer Log2;
+	input integer value;
+		begin
+			Log2 = 0;
+			while (value > 1) begin
+				value   = value >> 1;
+				Log2    = Log2 + 1;
+			end
+			
+			if	((2**Log2)<MeasPeriod)	begin
+				Log2	=	Log2+1;
+			end	
+		end
+	endfunction
+//================================================================================
+//  LOCALPARAMS
+	localparam CntWidth	=	Log2(MeasPeriod);
+	localparam SumWidth	=	AdcDataWidth+CntWidth;
+//================================================================================
+//  REG/WIRE
+	reg		overloadReg;
+	reg		[CntWidth-1:0]	measCnt;		
+	
+	reg		[SumWidth-1:0]	adcSum;	
+	
+	wire	[AdcDataWidth-1:0]	absAdc	=	(AdcData_i[AdcDataWidth-1])?	(~AdcData_i + 1):AdcData_i;
+//================================================================================
+//  ASSIGNMENTS
+	assign	Overload_o	=	overloadReg;
+//================================================================================
+//  CODING
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(measCnt	!= MeasPeriod-1)	begin
+			measCnt	<=	measCnt	+	{{{CntWidth-1{1'b0}},1'b1}};	
+		end	else	begin
+			measCnt	<=	{CntWidth{1'b0}};
+		end
+	end	else	begin
+		measCnt	<=	{CntWidth{1'b0}};
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(measCnt==MeasPeriod-1)	begin
+			adcSum	<=	absAdc;	
+		end	else	begin
+			adcSum	<=	adcSum	+	absAdc;
+		end
+	end	else	begin
+		adcSum	<=	0;
+	end
+end
+	
+always	@(posedge	Clk_i)	begin
+	if	(measCnt	==	MeasPeriod-1)	begin
+		if	((adcSum>>CntWidth)	>	OverThreshold_i)	begin
+			overloadReg	<=	1'b1;
+		end	else	begin
+			overloadReg	<=	1'b0;
+		end
+	end
+end
+endmodule

src/src/InitRst/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 20;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

src/src/InternalDsp/AdcCalibration.v

@@ -0,0 +1,131 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:12:30 06/03/2020 
+// Design Name: 
+// Module Name:    WinParameters 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: kek
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//18.01.2022	AdcData_I is 1.0.13 now changing to 1.2.17 for further calculation. The integer part added to avoid the overflow of the corrected data.
+//////////////////////////////////////////////////////////////////////////////////
+
+module AdcCalibration 
+#(	
+	parameter	AccNum			=	128,
+	parameter	AdcDataWidth	=	14
+)
+(	
+	input		Clk_i,
+	input		Rst_i,
+	input		CalModeEn_i,
+	input		[AdcDataWidth-1:0]	AdcData_i,
+	
+	output		CalDone_o,
+	output		[AdcDataWidth-1:0]	CalibratedAdcData_o
+);
+
+//================================================================================
+//  Func
+//================================================================================
+	function integer Log2;
+	input integer value;
+		begin
+			Log2 = 0;
+			while (value > 1) begin
+				value   = value >> 1;
+				Log2    = Log2 + 1;
+			end
+		end
+	endfunction
+	
+	localparam ShiftValue	= Log2(AccNum);
+	localparam AccWidth		= AdcDataWidth+ShiftValue;
+	
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg signed	[AccWidth:0]	adcAcc;
+	reg signed	[AdcDataWidth-1:0]	calValue;
+	reg signed	[AdcDataWidth-1:0]	calValueR;
+	reg [ShiftValue-1:0]	accCnt;
+	reg calDone;
+	
+	wire	[AccWidth:0]	adcDataCompl	=	{{ShiftValue+1{AdcData_i[AdcDataWidth-1]}},AdcData_i};
+	
+	wire	signed	[AdcDataWidth-1:0]	calibratedData	=	AdcData_i-calValue;
+	
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	CalDone_o	=	calDone;
+	assign	CalibratedAdcData_o	=	calibratedData;
+//================================================================================
+//  CODING
+//================================================================================	
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(CalModeEn_i)	begin
+			if	(!calDone)	begin
+				accCnt	<=	accCnt+1;
+			end	else	begin
+				accCnt	<=	0;
+			end
+		end	else	begin
+			accCnt	<=	0;
+		end
+	end	else	begin
+		accCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(accCnt	==	AccNum-1)	begin
+			calDone	<=	1'b1;
+		end	else	begin
+			calDone	<=	1'b0;
+		end
+	end	else	begin
+		calDone	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(CalModeEn_i)	begin
+			if	(!calDone)	begin
+				adcAcc	<=	adcAcc+adcDataCompl;
+			end	else	begin
+				adcAcc	<=	adcDataCompl;
+			end
+		end	else	begin
+			adcAcc	<=	adcDataCompl;
+		end
+	end	
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(calDone)	begin
+			calValue	<=	adcAcc>>ShiftValue;
+		end	
+	end	else	begin
+		calValue	<=	14'h0;
+	end
+end
+
+endmodule
+

src/src/InternalDsp/ComplPrng.v

@@ -0,0 +1,95 @@
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: NPK TAIR
+// Engineer: Mikhail Zaytsev
+// 
+// Create Date: 21.02.2023
+// Design Name: 
+// Module Name: ComplPrng
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: Pseudorandom number generator (PRNG) based on 
+//				Linear Feedback Shift Register (LFSR). Taus88
+//
+// Dependencies: None
+// 
+//////////////////////////////////////////////////////////////////////////////////
+module ComplPrng
+#(
+	parameter DataPrngWidth = 4,
+	parameter InDataWidth = 14,
+	parameter OutDataWidth = 20
+)
+(
+	// input [InDataWidth-1:0] Data_i,
+	input Clk_i,
+	input Rst_i,
+
+	// output signed	[OutDataWidth-1:0] DataAndPrng_o
+	output signed	[OutDataWidth-1:0] PrngData_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg [31:0] s1;
+reg [31:0] s2;
+reg [31:0] s3;
+reg signed	[31:0] dataPrng;
+
+wire	signed	[OutDataWidth-1:0]	adcDataExtended;
+
+wire	signed	[DataPrngWidth-1:0]	dataPrngCut;
+// wire	signed	[OutDataWidth-1:0]	dataPrngCutExtended;
+reg		signed	[OutDataWidth-1:0]	dataPrngCutExtended;
+
+reg	signed	[OutDataWidth-1:0]	dataAndPrngReg;
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================
+// assign	adcDataExtended		=	{Data_i[InDataWidth-1], Data_i[InDataWidth-1], Data_i, 4'b0};
+assign	dataPrngCut			=	dataPrng[31-:DataPrngWidth];
+// assign	dataPrngCutExtended	=	{{OutDataWidth-DataPrngWidth{dataPrngCut[DataPrngWidth-1]}}, dataPrngCut};
+// assign	DataAndPrng_o		=	adcDataExtended+dataPrngCutExtended;
+// assign	DataAndPrng_o		=	dataAndPrngReg;
+assign	PrngData_o			=	dataPrngCutExtended;
+//================================================================================
+//	CODING
+//================================================================================
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		s1 <= 32'd12345;
+		s2 <= 32'd12345;
+		s3 <= 32'd12345;
+	end else begin
+		s1 <= (((s1 & 32'd4294967294) << 12) ^ (((s1 << 13) ^ s1) >> 19));
+		s2 <= (((s2 & 32'd4294967288) << 4) ^ (((s2 << 2) ^ s2) >> 25));
+		s3 <= (((s3 & 32'd4294967280) << 17) ^ (((s3 << 3) ^ s3) >> 11));
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		dataPrng <= 32'b0;
+	end else begin
+		dataPrng <= s1 ^ s2 ^ s3;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		dataPrngCutExtended	<=	0;
+	end else begin
+		dataPrngCutExtended	<=	{{OutDataWidth-DataPrngWidth{dataPrngCut[DataPrngWidth-1]}}, dataPrngCut};
+	end
+end
+
+// always @(posedge Clk_i) begin
+	// if (Rst_i) begin
+		// dataAndPrngReg	<=	0;
+	// end else begin
+		// dataAndPrngReg	<=	Data_i+dataPrngCutExtended;
+	// end
+// end
+
+endmodule

src/src/InternalDsp/CordicNco.v

@@ -0,0 +1,246 @@
+/*
+    NCO module.
+    The module implements CORDIC algorithm
+*/
+
+module CordicNco 
+#(	parameter                   ODatWidth	= 18,
+	parameter                   PhIncWidth	= 32,
+	parameter                   IterNum		= 10,
+	parameter                   EnSinN		= 0,
+	parameter                   WinTypeW	= 0
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+    input	Val_i,
+    input	[PhIncWidth-1:0]	PhaseInc_i,
+	input	[WinTypeW-1:0]	WinType_i,
+	input	WindVal_i,
+	output	[ODatWidth-1:0]	Wind_o,
+	output	[ODatWidth-1:0]	Sin_o,
+	output	[ODatWidth-1:0]	Cos_o,
+    output	reg	Val_o
+);
+
+//================================================================================
+//  FUNCTIONS
+//================================================================================
+    function integer log2;
+        input integer value;
+        begin
+            log2 = 0;
+            while (value > 1) begin
+                value   = value >> 1;
+                log2    = log2 + 1;
+            end
+        end
+    endfunction
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
+	localparam  [PhIncWidth-1:0]	angle270	= 3<<(PhIncWidth-2);
+	localparam  [PhIncWidth-1:0]	angle180	= 1<<(PhIncWidth-1);
+	localparam  [PhIncWidth-1:0]	angle90		= 1<<(PhIncWidth-2);
+	
+	localparam [17:0] initValue = 18'd78498;
+//================================================================================
+//  REG/WIRE DECLARATIONS
+//================================================================================
+	
+    wire	[PhIncWidth-1:0]	precompAngle[ODatWidth-1:0];   
+    wire	[ODatWidth-1:0]		xPipe[IterNum:0];
+    wire	[ODatWidth-1:0]		yPipe[IterNum:0];
+    wire	[IterNum:0]			valPipe;
+    reg		[PhIncWidth-1:0]	phaseDiffPipe[IterNum-1:0];
+    reg		[2:0]				scwSignPipe[IterNum-1:0];
+
+    reg		[PhIncWidth-1:0]	phaseAcc;
+    reg     [PhIncWidth-1:0]	currPhase;
+    reg		[2:0]				scwSignPrev;
+    reg		[2:0]				scwSign;
+    reg		[2:0]				valSr;
+
+	reg		[ODatWidth-1:0]		sin_o;
+	reg		[ODatWidth-1:0]		cos_o;
+	reg		[ODatWidth-1:0]		wind_o;
+    genvar	g;
+    integer	i;
+	
+	reg		valR;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+    assign	xPipe[0]	=	(Val_i)	?	initValue:xPipe[0];
+    assign	yPipe[0]	=	(Val_i)	?	initValue:yPipe[0];
+    assign	valPipe[0]	=	valSr[2];
+	assign	Wind_o		=	(WindVal_i&&WinType_i==0)	?	wind_o:14'b0;
+
+	assign precompAngle[0] = 32'd536870912;
+	assign precompAngle[1] = 32'd316933406;
+	assign precompAngle[2] = 32'd167458907;
+	assign precompAngle[3] = 32'd85004756;
+	assign precompAngle[4] = 32'd42667331;
+	assign precompAngle[5] = 32'd21354465;
+	assign precompAngle[6] = 32'd10679838;
+	assign precompAngle[7] = 32'd5340245;
+	assign precompAngle[8] = 32'd2670163;
+	assign precompAngle[9] = 32'd1335087;
+	assign precompAngle[10] = 32'd667544;
+	assign precompAngle[11] = 32'd333772;
+	assign precompAngle[12] = 32'd166886;
+	assign precompAngle[13] = 32'd83443;
+	// assign precompAngle[14] = 32'd41722;
+	// assign precompAngle[15] = 32'd20861;
+	// assign precompAngle[16] = 32'd10430;
+	// assign precompAngle[17] = 32'd5215;
+	//assign precompAngle[18] = 32'd2608;
+
+	assign	Sin_o	=	WindVal_i	?	sin_o	:	14'h0;
+	assign	Cos_o	=	WindVal_i	?	cos_o	:	14'h0;
+//================================================================================
+//  CODING
+//================================================================================
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        valR	<=	1'b0;
+    end else begin
+		valR	<=	Val_i;
+	end
+end
+
+//  Phase handle logic
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        phaseAcc   <= {PhIncWidth{1'b0}};
+    end else if (Val_i) begin
+        phaseAcc   <= phaseAcc + PhaseInc_i;
+    end	else	begin
+		phaseAcc   <= {PhIncWidth{1'b0}};
+	end
+end
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        currPhase   <= {PhIncWidth{1'b0}};
+        scwSign         <= 3'b0;
+    end else begin
+        if (phaseAcc > angle270) begin
+            currPhase   <= {PhIncWidth{1'b0}} - phaseAcc;
+            scwSign         <= 3'b010;
+        end else if (phaseAcc > angle180) begin
+            currPhase   <= phaseAcc - angle180;
+            scwSign         <= 3'b011;
+        end else if (phaseAcc > angle90) begin
+            currPhase   <= angle180 - phaseAcc;
+            scwSign         <= 3'b001;
+        end else begin
+            currPhase   <= phaseAcc;
+            scwSign         <= 3'b000;
+        end
+    end
+end
+
+//--------------------------------------------------------------------------------
+//  CORDIC pipe
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        valSr <= 3'b0;
+    end else if	(Val_i)	begin
+        valSr <= {valSr[1:0], Val_i};
+    end	else	begin
+		valSr <= 3'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+    phaseDiffPipe[0]  <= currPhase - precompAngle[0];
+    scwSignPipe[0]     <= scwSign;
+    for(i=1; i<IterNum; i=i+1) begin
+        scwSignPipe[i] <= scwSignPipe[i-1];
+        if (phaseDiffPipe[i-1][PhIncWidth-1]) begin
+            phaseDiffPipe[i] <= phaseDiffPipe[i-1] + precompAngle[i];
+        end else begin
+            phaseDiffPipe[i] <= phaseDiffPipe[i-1] - precompAngle[i];
+        end
+    end
+end
+
+generate
+    for (g = 0; g < IterNum; g = g + 1) begin : cordic_pipe
+        cordic_rotation #(
+            .ODatWidth	(ODatWidth),
+            .Shift      (g+1)
+        ) cordic_rotation_inst (
+            .Clk_i      (Clk_i),
+            .Rst_i      (Rst_i),
+			.X_i        (xPipe[g]),
+			.Y_i        (yPipe[g]),
+			.Val_i      (valPipe[g]),
+			.Sign_i     (phaseDiffPipe[g][PhIncWidth-1]),
+			.X_o        (xPipe[g+1]),
+			.Y_o        (yPipe[g+1]),
+			.Val_o      (valPipe[g+1])
+		);
+    end
+endgenerate
+
+//--------------------------------------------------------------------------------
+//  Output logic
+
+generate 
+    if (EnSinN) begin
+        always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                sin_o       <= {ODatWidth{1'b0}};
+            end else begin
+                if (scwSignPrev[1]) begin
+                    sin_o   <=  yPipe[IterNum];
+                end else begin
+                    sin_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+                end
+            end
+        end
+    end else begin
+        always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                sin_o       <= {ODatWidth{1'b0}};
+            end else begin
+				if (scwSignPrev[1]) begin
+					sin_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+				end else begin
+					sin_o   <=  yPipe[IterNum];
+				end
+            end
+        end
+		always @(posedge Clk_i) begin
+            if (Rst_i) begin
+                wind_o       <= {ODatWidth{1'b0}};
+            end else begin
+				if (scwSignPrev[2]) begin
+					wind_o   <= ~yPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+				end else begin
+					wind_o   <=  yPipe[IterNum];
+				end
+            end
+        end
+    end
+endgenerate
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        cos_o		<= {ODatWidth{1'b0}};
+        scwSignPrev	<= 3'b0;
+        Val_o		<= 1'b0;
+    end else begin
+        if (scwSignPrev[0]) begin
+            cos_o	<= ~xPipe[IterNum] + {{(ODatWidth-1){1'b0}}, 1'b1};
+        end else begin
+            cos_o	<= xPipe[IterNum];
+        end
+		scwSignPrev	<= scwSignPipe[IterNum-1];
+		Val_o		<= valPipe[0];
+    end	
+end
+endmodule

src/src/InternalDsp/CordicRotation.v

@@ -0,0 +1,74 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:32:49 05/13/2020 
+// Design Name: 
+// Module Name:    cordic_rotation 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module cordic_rotation 
+#(	parameter   ODatWidth	= 16,
+	parameter   Shift		= 1)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	input	signed  [ODatWidth-1:0]	X_i,
+	input	signed  [ODatWidth-1:0]	Y_i,
+	input	Val_i,
+	input	Sign_i,
+	output	reg	signed	[ODatWidth-1:0]	X_o,
+	output	reg	signed	[ODatWidth-1:0]	Y_o,
+	output	reg	Val_o
+);
+//================================================================================
+//  REG/WIRE DECLARATIONS
+//================================================================================
+    wire    [ODatWidth-1:0]    shiftedInX;
+    wire    [ODatWidth-1:0]    shiftedInY;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+    assign  shiftedInX    =   X_i >>> Shift;
+    assign  shiftedInY    =   Y_i >>> Shift;
+//================================================================================
+//  CODING
+//================================================================================
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        Val_o	<= 1'b0;
+    end else if	(Val_i)	begin
+        Val_o	<= Val_i;
+    end	else	begin
+		Val_o	<=	1'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+    if (Rst_i) begin
+        X_o   <= {ODatWidth{1'b0}};
+        Y_o   <= {ODatWidth{1'b0}};
+    end else if (Val_i) begin
+        if (Sign_i) begin
+            X_o   <= X_i + shiftedInY;
+            Y_o   <= Y_i - shiftedInX; 
+        end else begin
+            X_o   <= X_i - shiftedInY;
+            Y_o   <= Y_i + shiftedInX;
+        end
+    end
+end
+
+endmodule

src/src/InternalDsp/DspPipeline.v

@@ -0,0 +1,296 @@
+
+(* keep_hierarchy = "yes" *)	
+module DspPipeline 
+#(	
+	parameter	AdcDataWidth		=	14,
+	parameter	AccWidth			=	48,
+	parameter	WindWidth			=	14,
+	parameter	AdcCorrData			=	20,
+	parameter	NcoWidth			=	14,
+	parameter	ResultWidth			=	32,
+	parameter	WindNormCoefWidth	=	32,
+	parameter	WindCorrCoefWidth	=	32,
+	parameter	IntermediateWidth	=	14,
+	// parameter	FracWidth			=	51
+	parameter	FracWidth			=	32
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+    input	Val_i,
+    input	MeasWindEnd_i,
+    input	StartFpConv_i,
+	
+	input	[WindCorrCoefWidth-1:0]	FilterCorrCoef_i,
+	input	[WindCorrCoefWidth-1:0]	AverageNoizeLvl_i,
+	input	[AdcCorrData-1:0]	AdcData_i,
+	input	[WindWidth-1:0]		Wind_i,
+	input	[NcoWidth-1:0]		NcoSin_i,
+	input	[NcoWidth-1:0]		NcoCos_i,
+	input	[WindNormCoefWidth-1:0]	NormCoef_i,
+	
+	output	[ResultWidth-1:0]	CorrResultIm_o,
+	output	[ResultWidth-1:0]	CorrResultRe_o,
+    output	CorrResultVal_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+	localparam	NormResultWidth	=	AccWidth+WindNormCoefWidth;
+	localparam	AdcWindWidth	=	18;
+//================================================================================
+//  REG/WIRE 
+	wire	[AdcWindWidth-1:0]	adcWindResult;
+	wire	adcWindResultVal;
+	
+	wire	[54:0]	adcWindSinResult;
+	wire	adcWindSinResultVal;
+	wire	[54:0]	adcWindCosResult;
+	wire	adcWindCosResultVal;
+	
+	wire	[AccWidth-1:0]	AccResultI;
+	wire	resultIVal;
+	wire	[AccWidth-1:0]	AccResultQ;
+	wire	resultQVal;
+	
+	wire	[ResultWidth-1:0]	NormResultI;
+	wire	NormResultIVal;
+	wire	[ResultWidth-1:0]	NormResultQ;
+	wire	NormResultQVal;
+	
+	wire	[ResultWidth-1:0]	iFp32Result;
+	wire	iFp32ResultVal;
+	wire	[ResultWidth-1:0]	qFp32Result;
+	wire	qFp32ResultVal;
+	
+	wire	CorrResultReVal;
+	wire	CorrResultImVal;
+	
+	reg		valReg;
+	reg		valRegReg;
+//================================================================================
+//  ASSIGNMENTS
+	assign	CorrResultVal_o	=	CorrResultReVal&CorrResultImVal;
+	
+//================================================================================
+//  CODING
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			valReg		<=	Val_i;
+			valRegReg	<=	valReg;
+		end	else	begin
+			valReg		<=	0;
+			valRegReg	<=	0;	
+		end
+	end
+	
+//===============================Adc*Wind=========================================
+SimpleMult	
+#(	
+	.FactorAWidth	(AdcCorrData),
+	.FactorBWidth	(WindWidth),
+	.OutputWidth	(AdcWindWidth)
+)
+AdcWindMult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.Val_i		(Val_i),
+	.FactorA_i	(AdcData_i),
+	.FactorB_i	(Wind_i),
+	.Result_o	(adcWindResult),
+	.ResultVal_o(adcWindResultVal)
+);
+//===============================AdcWind*NcoSinCos================================
+SimpleMult	
+#(	
+	.FactorAWidth	(AdcWindWidth),
+	.FactorBWidth	(NcoWidth),
+	.OutputWidth	(NcoWidth+AdcWindWidth)
+)
+AdcNcoSinMult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.Val_i		(adcWindResultVal),
+	.FactorA_i	(adcWindResult),
+	.FactorB_i	(NcoSin_i),	
+	.Result_o	(adcWindSinResult),
+	.ResultVal_o(adcWindSinResultVal)
+);
+
+SimpleMult	
+#(	
+	.FactorAWidth	(AdcWindWidth),
+	.FactorBWidth	(NcoWidth),
+	.OutputWidth	(NcoWidth+AdcWindWidth)
+)
+AdcNcoCosMult	
+(
+	.Rst_i		(Rst_i),
+	.Clk_i		(Clk_i),
+	.Val_i		(adcWindResultVal),
+	.FactorA_i	(adcWindResult),
+	.FactorB_i	(NcoCos_i),
+	.Result_o	(adcWindCosResult),
+	.ResultVal_o(adcWindCosResultVal)
+);
+
+//===============================SumAcc===========================================
+SumAcc
+#(	
+	.IDataWidth	(NcoWidth+AdcWindWidth-1),
+	.ODataWidth	(AccWidth)
+)
+SummAccQ
+(
+    .Clk_i		(Clk_i),
+    .Rst_i		(Rst_i),
+	.AccZeroing_i		(MeasWindEnd_i),
+    .Val_i		(adcWindSinResultVal),
+	
+	.Data_i		(adcWindSinResult[53:0]),
+	.Result_o	(AccResultQ),
+	.ResultVal_o	(resultQVal)
+);
+
+SumAcc
+#(	
+	.IDataWidth	(NcoWidth+AdcWindWidth-1),
+	.ODataWidth	(AccWidth)
+)
+SummAccI
+(
+    .Clk_i		(Clk_i),
+    .Rst_i		(Rst_i),
+    .AccZeroing_i		(MeasWindEnd_i),
+    .Val_i		(adcWindCosResultVal),
+	
+	.Data_i		(adcWindCosResult[53:0]),
+	.Result_o	(AccResultI),
+	.ResultVal_o	(resultIVal)
+);
+
+//===============================InToFpConv=======================================
+MyIntToFp
+#(	
+	.InWidth	(AccWidth),
+	.ExpWidth	(8),
+	.ManWidth	(23),
+	.FracWidth	(FracWidth)
+)
+QToFp32
+(	
+	.Clk_i				(Clk_i),
+	.Rst_i				(Rst_i),
+	.InData_i			(AccResultQ),
+	.AverageNoizeLvl_i	(AverageNoizeLvl_i),
+	.InDataVal_i		(resultQVal),
+	.OutData_o			(qFp32Result),
+	.OutDataVal_o		(qFp32ResultVal)
+);
+
+MyIntToFp
+#(	
+	.InWidth	(AccWidth),
+	.ExpWidth	(8),
+	.ManWidth	(23),
+	.FracWidth	(FracWidth)
+)
+IToFp32
+(	
+	.Clk_i				(Clk_i),
+	.Rst_i				(Rst_i),
+	.InData_i			(AccResultI),
+	.AverageNoizeLvl_i	(AverageNoizeLvl_i),
+	.InDataVal_i		(resultIVal),
+	.OutData_o			(iFp32Result),
+	.OutDataVal_o		(iFp32ResultVal)
+);
+
+//===============================Result*NormCoeff=================================
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultQNorm
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(qFp32Result),
+	.B_i			(NormCoef_i),
+	.Nd_i			(qFp32ResultVal),
+	.Result_o		(NormResultQ),
+	.ResultValid_o	(NormResultQVal)
+);
+
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultINorm
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(iFp32Result),
+	.B_i			(NormCoef_i),
+	.Nd_i			(iFp32ResultVal),
+	.Result_o		(NormResultI),
+	.ResultValid_o	(NormResultIVal)
+);
+
+//===============================NormResult*CorrCoeff========================
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultReCorr
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(NormResultQ),
+	.B_i			(FilterCorrCoef_i),
+	.Nd_i			(NormResultQVal),
+	.Result_o		(CorrResultRe_o),
+	.ResultValid_o	(CorrResultReVal)
+);
+
+FpCustomMultiplier 
+# (
+	.ManWidth	(23),
+	.ExpWidth	(8)
+)
+ResultImCorr
+(
+	.Rst_i			(Rst_i),
+	.Clk_i			(Clk_i),
+	.A_i			(NormResultI),
+	.B_i			(FilterCorrCoef_i),
+	.Nd_i			(NormResultIVal),
+	.Result_o		(CorrResultIm_o),
+	.ResultValid_o	(CorrResultImVal)
+);
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/InternalDsp/InternalDsp.v

@@ -0,0 +1,409 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    18:00:25 07/10/2019 
+// Design Name: 
+// Module Name:    internal_dsp 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module InternalDsp	
+#(	
+	parameter	AdcDataWidth		=	14,	
+	parameter	WindWidth			=	18,
+	parameter	WindNcoPhIncWidth	=	32,
+	parameter	NcoWidth			=	18,
+	parameter	ChNum				=	4,
+	parameter	ResultWidth			=	32,
+	parameter	WinTypeWidth		=	3,
+	parameter	BandCmdWidth		=	8,
+	parameter	WindPNumWidth		=	32,
+	parameter	WindNormCoefWidth	=	32,
+	parameter	WindCorrCoefWidth	=	32,
+	parameter	CmdDataRegWith		=	24,
+	parameter	IntermediateWidth	=	18,
+	parameter	CorrAdcDataWidth	=	20,
+	parameter	AccWidth			=	61
+)
+(
+	input	wire	Clk_i,
+	input	wire	WindCalcClk_i,
+	input	wire	Rst_i,
+	input	wire	NcoRst_i,
+	output	wire	OscWind_o,
+	
+	input	wire	[AdcDataWidth-1:0]	Adc1ChT1Data_i,	//A
+	input	wire	[AdcDataWidth-1:0]	Adc1ChR1Data_i,	//R1
+	input	wire	[AdcDataWidth-1:0]	Adc2ChR2Data_i,	//R2
+	input	wire	[AdcDataWidth-1:0]	Adc2ChT2Data_i,	//B	
+	
+	input	wire	GatingPulse_i,
+	
+	input	wire	StartMeas_i,
+	input	wire	StartMeasDsp_i,
+	input	wire	OscDataRdFlag_i,
+	
+	input	wire	[32-1:0]	MeasNum_i,
+	
+	input	wire	[CmdDataRegWith-1:0]	MeasCtrl_i,
+	input	wire	[CmdDataRegWith-1:0]	FilterCorrCoefL_i,
+	input	wire	[CmdDataRegWith-1:0]	FilterCorrCoefH_i,
+	
+	output	wire	EndMeas_o,
+	
+	input	wire	CalModeEn_i,
+	output	wire	CalModeDone_o,
+
+	input	wire	[CmdDataRegWith-1:0]	IfFtwL_i,
+	input	wire	[CmdDataRegWith-1:0]	IfFtwH_i,
+	
+	output	wire	[ResultWidth-1:0]	Adc1ImT1Data_o,
+	output	wire	[ResultWidth-1:0]	Adc1ReT1Data_o,
+	output	wire	[ResultWidth-1:0]	Adc1ImR1Data_o,
+	output	wire	[ResultWidth-1:0]	Adc1ReR1Data_o,
+	//adc2                 
+	output	wire	[ResultWidth-1:0]	Adc2ImR2Data_o,
+	output	wire	[ResultWidth-1:0]	Adc2ReR2Data_o,
+	output	wire	[ResultWidth-1:0]	Adc2ImT2Data_o,
+	output	wire	[ResultWidth-1:0]	Adc2ReT2Data_o,
+	
+	output	wire	[NcoWidth-1:0]	NcoSin_o,
+	output	wire	[NcoWidth-1:0]	NcoCos_o,
+	
+	output	wire	MeasDataRdy_o,
+	output	wire	MeasWind_o,
+	output	wire	MeasEnd_o,
+	output	wire	SampleStrobeGenRst_o
+);
+
+//================================================================================
+//  REG/WIRE
+	wire	[WindNormCoefWidth-1:0]	windNormCoef;
+	wire	[WindPNumWidth-1:0]		windPointsNum;
+	wire	[WindPNumWidth-1:0]		averageNoizeLvl;
+	wire	[WindNcoPhIncWidth-1:0]	windPhInc;
+	wire	[WindNcoPhIncWidth-1:0]	winPhIncStart;
+	
+	wire	[WindWidth-1:0]	wind;			
+
+	wire	[NcoWidth-1:0]	ncoCos;
+	wire	[NcoWidth-1:0]	ncoSin;
+	
+	wire	[CorrAdcDataWidth-1:0]	adcDataBus	[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	adcDataBusExt	[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	gatedAdcDataBus	[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	calAdcData		[ChNum-1:0];
+	wire	[CorrAdcDataWidth-1:0]	prngData;
+	reg		[CorrAdcDataWidth-1:0]	prngDataBus		[ChNum-1:0];
+	wire	[ChNum-1:0]	calDone;
+	
+	genvar g;
+	integer i;
+	
+	wire	[ResultWidth-1:0]	resultImBus		[ChNum-1:0];
+	wire	[ResultWidth-1:0]	resultReBus		[ChNum-1:0];
+	wire	[ChNum-1:0]	resultValBus;
+	
+	wire	measWind;
+	wire	measWindEnd;
+	wire	stopMeas;
+	wire	[1:0]	tukeyCtrl;
+	
+	reg		[CmdDataRegWith-1:0]	measCtrlReg;
+	reg		[32-1:0]	windPointsNumReg;
+	reg		[32-1:0]	measNumReg;
+	reg		[WindCorrCoefWidth-1:0]	filterCorrCoeffReg;
+	reg		[CmdDataRegWith-1:0]	ifFtwLReg;
+	reg		[CmdDataRegWith-1:0]	ifFtwHReg;
+	reg		[CmdDataRegWith-1:0]	filterCorrCoefLReg;
+	reg		[CmdDataRegWith-1:0]	filterCorrCoefHReg;
+	
+	wire	[31:0]	windArg;
+	
+	wire	[CorrAdcDataWidth-1:0]	adc1ChT1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-4]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc1ChR1DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-3]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc2ChR2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-2]:{CorrAdcDataWidth{1'b0}};
+	wire	[CorrAdcDataWidth-1:0]	adc2ChT2DataGated	=	(GatingPulse_i)?	adcDataBusExt[ChNum-1]:{CorrAdcDataWidth{1'b0}};	
+	
+	wire	[WindNcoPhIncWidth-1:0]	ncoPhInc = {ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg};
+	
+//================================================================================
+//  ASSIGNMENTS
+
+	assign	adcDataBus	[ChNum-1]	=	{{2{Adc2ChT2Data_i[AdcDataWidth-1]}},Adc2ChT2Data_i,4'b0};
+	assign	adcDataBus	[ChNum-2]	=	{{2{Adc2ChR2Data_i[AdcDataWidth-1]}},Adc2ChR2Data_i,4'b0};
+	assign	adcDataBus	[ChNum-3]	=	{{2{Adc1ChR1Data_i[AdcDataWidth-1]}},Adc1ChR1Data_i,4'b0};
+	assign	adcDataBus	[ChNum-4]	=	{{2{Adc1ChT1Data_i[AdcDataWidth-1]}},Adc1ChT1Data_i,4'b0};
+	
+	assign	adcDataBusExt	[ChNum-1]	=	calAdcData	[ChNum-1]+prngDataBus[ChNum-1];
+	assign	adcDataBusExt	[ChNum-2]	=	calAdcData	[ChNum-2]+prngDataBus[ChNum-2];
+	assign	adcDataBusExt	[ChNum-3]	=	calAdcData	[ChNum-3]+prngDataBus[ChNum-3];
+	assign	adcDataBusExt	[ChNum-4]	=	calAdcData	[ChNum-4]+prngDataBus[ChNum-4];
+	
+	assign	gatedAdcDataBus	[ChNum-1]	=	adc2ChT2DataGated;
+	assign	gatedAdcDataBus	[ChNum-2]	=	adc2ChR2DataGated;
+	assign	gatedAdcDataBus	[ChNum-3]	=	adc1ChR1DataGated;
+	assign	gatedAdcDataBus	[ChNum-4]	=	adc1ChT1DataGated;
+	
+	assign	Adc1ImT1Data_o	=	resultImBus	[ChNum-4];
+	assign	Adc1ReT1Data_o	=	resultReBus	[ChNum-4];
+	assign	Adc1ImR1Data_o	=	resultImBus	[ChNum-3];
+	assign	Adc1ReR1Data_o	=	resultReBus	[ChNum-3];
+	//adc2                 
+	assign	Adc2ImR2Data_o	=	resultImBus	[ChNum-2];
+	assign	Adc2ReR2Data_o	=	resultReBus	[ChNum-2];
+	assign	Adc2ImT2Data_o	=	resultImBus	[ChNum-1];
+	assign	Adc2ReT2Data_o	=	resultReBus	[ChNum-1];
+	
+	
+	assign	MeasDataRdy_o	=	&resultValBus;
+	assign	EndMeas_o		=	stopMeas;
+	
+	assign	NcoCos_o	=	ncoCos;
+	assign	NcoSin_o	=	ncoSin;
+	assign	MeasWind_o	=	measWind;
+	
+	assign	CalModeDone_o	=	&calDone;
+	
+//================================================================================
+//  INSTANTIATIONS
+
+//----------------------------------------------
+//Module generates event signals for measurement
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!StartMeas_i)	begin
+			measCtrlReg			<=	MeasCtrl_i;
+			ifFtwLReg			<=	IfFtwL_i;
+			ifFtwHReg			<=	IfFtwH_i;
+			filterCorrCoefLReg	<=	FilterCorrCoefL_i;
+			filterCorrCoefHReg	<=	FilterCorrCoefH_i;
+			measNumReg			<=	MeasNum_i;
+			windPointsNumReg	<=	windPointsNum;
+		end 
+	end	else	begin
+		measCtrlReg			<=	0;
+		ifFtwLReg			<=	0;
+		ifFtwHReg			<=	0;
+		filterCorrCoefLReg	<=	0;
+		filterCorrCoefHReg	<=	0;
+		measNumReg			<=	0;
+		windPointsNumReg	<=	0;
+	end 
+end
+
+MeasCtrlModule	
+#(	
+	.WindPNumWidth	(WindPNumWidth)
+)
+MeasCtrlModule	
+(
+	.Clk_i					(Clk_i),
+	.Rst_i					(Rst_i),
+	.OscWind_o				(OscWind_o),
+	.FilterCmd_i			(measCtrlReg[15-:8]),
+		
+	.MeasNum_i				(measNumReg),
+	.StartMeas_i			(StartMeas_i),
+	.StartMeasDsp_i			(StartMeasDsp_i),
+	.Mode_i					(measCtrlReg[0]),
+	.OscDataRdFlag_i		(OscDataRdFlag_i),
+		
+	.WindPointsNum_i		(windPointsNumReg),
+		
+	.WindPhInc_i			(windPhInc),
+	.WindPhIncStart_i		(winPhIncStart),
+	.WindArg_o				(windArg),
+		
+	.StartFpConv_o			(),
+	.MeasWind_o				(measWind),
+	.MeasWindEnd_o			(measWindEnd),
+	.StopMeas_o				(stopMeas),
+	.MeasEnd_o				(MeasEnd_o),
+	.WinCtrl_o				(winCtrl),
+	.TukeyCtrl_o			(tukeyCtrl),
+	.SampleStrobeGenRst_o	(SampleStrobeGenRst_o)
+);	
+
+//----------------------------------------------
+//Module selects settings for current window
+WinParameters 
+#(	
+	.WindPhIncWidth		(WindNcoPhIncWidth),
+	.WindNormCoefWidth	(WindNormCoefWidth),
+	.WindPNumWidth		(WindPNumWidth),
+	.BandCmdWidth		(BandCmdWidth)
+)
+WinParameters
+(	
+	.Clk_i				(Clk_i),
+	.Rst_i				(Rst_i),
+	.FilterCmd_i		(measCtrlReg[15-:8]),
+	.WinPhInc_o			(windPhInc),
+	.WinPhIncStart_o	(winPhIncStart),
+	.WinNormCoef_o		(windNormCoef),
+	.WinPointsNum_o		(windPointsNum),
+	.AverageNoiseLvl_o	(averageNoizeLvl)
+);
+
+//----------------------------------------------
+//Module generates win samples
+Win_calc	WinCalcInst
+(
+	.clk_i			(Clk_i),
+	.filterCmd_i	(measCtrlReg[15-:8]),
+	.reset_i		(Rst_i),
+	.WinCtrl_i		(winCtrl),
+	.TukeyCtrl_i	(tukeyCtrl),
+	.MeasWind_i		(measWind),
+	.win_value_i	(windArg),
+	.win_type_i		(measCtrlReg[2:0]),
+	.win_o			(wind)
+);
+
+// Approximation3 WindCalc2
+// (
+    // .Clk_i			(Clk_i), 
+    // .Rst_i			(Rst_i),
+    // .Clk100_i		(WindCalcClk_i),
+    // .WinCtrl_i		(winCtrl),
+    // .Win_value_i	(windArg),
+    // .filterCmd_i	(measCtrlReg[15-:8]), 
+	// .Win_o			(wind)
+// );
+
+
+//----------------------------------------------
+//Module generates Sin and Cos for measurement
+
+CordicNco		
+#(	
+	.ODatWidth	(NcoWidth),
+	.PhIncWidth	(WindNcoPhIncWidth),
+	.IterNum	(13),
+	.EnSinN		(0)
+)
+ncoInst
+(
+	.Clk_i		(Clk_i),
+	.Rst_i		(Rst_i|NcoRst_i),
+	.Val_i		(1'b1),
+	.PhaseInc_i	({ifFtwHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],ifFtwLReg}),
+	.WindVal_i	(1'b1),
+	.WinType_i	(),
+	.Wind_o		(),
+	.Sin_o		(ncoSin),
+	.Cos_o		(ncoCos),	
+	.Val_o		()
+);
+
+ComplPrng
+#(
+	.DataPrngWidth	(8),
+	.InDataWidth 	(CorrAdcDataWidth),
+	.OutDataWidth	(CorrAdcDataWidth)
+)
+ComplPrngAdderInst
+(
+	.Clk_i	(Clk_i),
+	.Rst_i	(Rst_i),
+
+	.PrngData_o		(prngData)
+);
+
+always @(posedge Clk_i) begin
+	prngDataBus[0]  <= prngData;
+	for(i=1; i<4; i=i+1) begin
+		prngDataBus	[i]<=prngDataBus[i-1];
+	end
+end
+//------------------------------------------------
+//Generating needed amount of calculating channels
+generate
+	for	(g=0;	g<ChNum;	g=g+1)	begin	:DspChannel
+	
+		AdcCalibration 
+		#(	
+			.AccNum			(2097152),
+			.AdcDataWidth	(CorrAdcDataWidth)
+		)
+		AdcCalibrationInst
+		(	
+			.Clk_i					(Clk_i),
+			.Rst_i					(Rst_i),
+			.CalModeEn_i			(CalModeEn_i),
+			.AdcData_i				(adcDataBus[g]),
+			
+			.CalDone_o				(calDone[g]),
+			.CalibratedAdcData_o	(calAdcData[g])
+		);
+		
+		DspPipeline	
+		#(	
+			.AdcDataWidth		(AdcDataWidth),
+			.AccWidth			(AccWidth),
+			.WindWidth			(WindWidth),
+			.NcoWidth			(NcoWidth),
+			.ResultWidth		(ResultWidth),
+			.WindCorrCoefWidth	(WindCorrCoefWidth),
+			.WindNormCoefWidth	(WindNormCoefWidth),
+			.IntermediateWidth	(IntermediateWidth)
+		)
+		DspPipelineInst
+		(
+			.Clk_i				(Clk_i),
+			.Rst_i				(Rst_i),
+			.Val_i				(measWind),
+			.MeasWindEnd_i		(measWindEnd),
+			.StartFpConv_i		(measWindEnd),
+			
+			.FilterCorrCoef_i	({filterCorrCoefHReg[0+:WindNcoPhIncWidth-CmdDataRegWith],filterCorrCoefLReg}),
+			// .FilterCorrCoef_i	(32'h3f800000),
+			.AverageNoizeLvl_i	(averageNoizeLvl),
+			.AdcData_i			(gatedAdcDataBus[g]),
+			// .AdcData_i			({{2{ncoCos[17]}},ncoCos}),
+			.Wind_i				(wind),
+			.NcoSin_i			(ncoSin),
+			.NcoCos_i			(ncoCos),	
+			.NormCoef_i			(windNormCoef),
+			// .NormCoef_i			(32'h3f800000),
+			// .NormCoef_i			(32'h3f03993a),
+
+			.CorrResultIm_o		(resultImBus[g]),
+			.CorrResultRe_o		(resultReBus[g]),
+			.CorrResultVal_o	(resultValBus[g])
+		);
+	end
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/InternalDsp/MeasCtrlModule.v

@@ -0,0 +1,351 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:22:41 09/18/2019 
+// Design Name: 
+// Module Name:    MeasCtrlModule 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module MeasCtrlModule
+#(	
+	parameter	WindPNumWidth	=	48,
+	localparam	TukeyWinAlpha	=	4
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+	output	OscWind_o,
+	
+	input	StartMeas_i,
+	input	StartMeasDsp_i,
+	input	[7:0]	FilterCmd_i,
+	input	Mode_i,
+	input	OscDataRdFlag_i,
+	
+	input	[32-1:0]	MeasNum_i,
+
+	input	[WindPNumWidth-1:0]	WindPointsNum_i,
+	
+	input	[32-1:0]	WindPhInc_i,
+	input	[32-1:0]	WindPhIncStart_i,
+	output	[32-1:0]	WindArg_o,
+	
+	output	StartFpConv_o,
+	output	MeasWind_o,
+	output	MeasWindEnd_o,
+	output	StopMeas_o,
+	output	MeasEnd_o,
+	output	WinCtrl_o,
+	output	SampleStrobeGenRst_o,
+	output	[1:0]	TukeyCtrl_o
+);
+
+
+//================================================================================
+//  REG/WIRE
+	reg	startFpConv;
+
+	reg	[1:0]	startFpConvPipe	[3:0];
+	integer i;
+
+	reg		measWind;
+	reg		measWindR;
+	
+	reg		startMeasReg;										
+	reg		startMeasDspReg;										
+	wire	startMeasCmd	=	(StartMeas_i		&	!startMeasReg);	//esli prihodit bol'she chem 1 sigtal zapuska na 1 izmerenie, to ostal'nie ignoriruutsya
+	wire	stopMeasCmd		=	(!StartMeasDsp_i	&	startMeasDspReg);
+	wire	startMeasDspPos	=	(StartMeasDsp_i		&	!startMeasDspReg);
+	
+	reg		[31:0]	measCnt;
+	
+	reg		[WindPNumWidth-1:0]	pNumCnt;
+
+	reg		measWindEnd;
+	reg		pMeasEnd;
+	wire	pNumCntRes		=	!measWind;
+	wire	measCntRes		=	pMeasEnd|!StartMeasDsp_i;
+	
+	wire	stopCalc		=	(stopMeasCmd|measWindEnd);
+
+	reg		[32-1:0]	windArg;
+	
+	wire	oscMode	=	(Mode_i	==	1'b1);
+	
+	reg		oscWind;
+	
+	wire	[31:0]	tukeyCosPNum = WindPointsNum_i/TukeyWinAlpha;
+	
+	wire	[31:0]	tukeyCosPNumDiv2			=	tukeyCosPNum/2;
+	wire	[31:0]	tukeyFirstCosValues			=	tukeyCosPNum/2;
+	wire	[31:0]	tukeyFirstCosValuesDiv2		=	tukeyFirstCosValues/2;
+	wire	[31:0]	tukeySecondCosValuesDiv2	=	(WindPointsNum_i-tukeyFirstCosValuesDiv2);
+	wire	[31:0]	tukeySecondCosValues		=	(WindPointsNum_i-tukeyCosPNum/2);
+
+	reg		[1:0]	tukeyCtrl;
+	reg		[1:0]	tukeyCtrlR;
+	reg		[1:0]	tukeyCtrlRR;
+
+	
+	wire	incPhase	=	(pNumCnt	<=	tukeyFirstCosValues);
+	wire	decrPhase	=	(pNumCnt	>=	tukeySecondCosValues-1	&	pNumCnt	<=	WindPointsNum_i-1);
+	
+	wire	wideFilterFlag	=	(FilterCmd_i>=8'h54	&	FilterCmd_i!=8'h70);
+	
+	reg		sampleStrobeGenRst;
+	
+	wire	measWindOr	=	(measWind|measWindR);
+//================================================================================
+//  ASSIGNMENTS
+	assign	StartFpConv_o			=	startFpConvPipe	[2];
+	// assign	MeasWind_o				=	measWind;
+	assign	MeasWind_o				=	measWindOr;
+	assign	MeasWindEnd_o			=	measWindEnd;
+	assign	StopMeas_o				=	pMeasEnd;
+	assign	MeasEnd_o				=	stopMeasCmd;
+	assign	WindArg_o				=	windArg;
+	assign	OscWind_o				=	oscWind;
+	assign	TukeyCtrl_o				=	tukeyCtrl;
+	assign	WinCtrl_o				=	(pNumCnt<=tukeyFirstCosValuesDiv2+1|pNumCnt>tukeySecondCosValuesDiv2);
+	assign	SampleStrobeGenRst_o	=	sampleStrobeGenRst;
+//================================================================================
+//  CODING
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(measCnt	==	MeasNum_i-1	&	measWind)	begin
+				sampleStrobeGenRst	<=	1'b1;
+			end	else	begin
+				sampleStrobeGenRst	<=	1'b0;
+			end
+		end	else	begin
+			sampleStrobeGenRst	<=	1'b0;
+		end
+	end
+	
+	always	@(*)	begin
+		if	(!Rst_i)	begin
+			if	(measWind)	begin
+				if	(pNumCnt	!=	0)	begin
+					if	(pNumCnt	<=	tukeyFirstCosValues-1	|	pNumCnt	>	tukeySecondCosValues)	begin
+						tukeyCtrl	=	2'd2;
+					end	else	begin
+						tukeyCtrl	=	2'd1;
+					end
+				end	else	begin
+					tukeyCtrl	=	2'd0;
+				end
+			end	else	begin
+				tukeyCtrl	=	2'd0;
+			end
+		end	else	begin
+			tukeyCtrl	=	2'd0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			measWindR	<=	measWind;
+		end	else	begin
+			measWindR	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			tukeyCtrlR	<=	tukeyCtrl;
+			tukeyCtrlRR	<=	tukeyCtrlR;
+		end	else	begin
+			tukeyCtrlR	<=	1'b0;
+			tukeyCtrlRR	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(measWindR)	begin
+				if	(pNumCnt	==	WindPointsNum_i-2)	begin
+					measWindEnd	<=	1'b1;
+				end	else	begin
+					measWindEnd	<=	1'b0;
+				end
+			end	else	begin
+				measWindEnd	<=	1'b0;
+			end
+		end	else	begin
+			measWindEnd	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(!oscMode)	begin
+				if	(measCnt	==	MeasNum_i-1)	begin
+					if	(measWindEnd)	begin
+						pMeasEnd	<=	1'b1;
+					end	else	begin
+						pMeasEnd	<=	1'b0;
+					end
+				end	else	begin
+					pMeasEnd	<=	1'b0;
+				end
+			end	else	begin
+				if	(measCnt	==	MeasNum_i-1)	begin
+					if	(OscDataRdFlag_i)	begin
+						pMeasEnd	<=	1'b1;
+					end	else	begin
+						pMeasEnd	<=	1'b0;
+					end
+				end	else	begin
+					pMeasEnd	<=	1'b0;
+				end
+			end
+		end	else	begin
+			pMeasEnd	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(wideFilterFlag)	begin
+				if	(measWind)	begin
+					windArg	<=	windArg+WindPhInc_i;
+				end	else	begin
+					windArg	<=	WindPhInc_i>>1;
+				end
+			end	else	begin
+				if	(measWind)	begin
+					if	(incPhase)	begin
+						windArg	<=	windArg+WindPhInc_i;
+					end	
+					if	(decrPhase)	begin
+						windArg	<=	windArg-WindPhInc_i;
+					end
+				end	else	begin
+					windArg	<=	WindPhIncStart_i;
+				end
+			end
+		end	else	begin
+			windArg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(!measCntRes)	begin
+				if	(!oscMode)	begin
+					if	(measCnt	!=	MeasNum_i-1)	begin
+						if	(measWindEnd)	begin
+							measCnt	<=	measCnt+1;
+						end
+					end
+				end	else	begin
+					if	(measCnt	!=	MeasNum_i-1)	begin
+						if	(OscDataRdFlag_i)	begin
+							measCnt	<=	measCnt+1;
+						end
+					end
+				end
+			end	else	begin
+				measCnt	<=	0;
+			end
+		end	else	begin
+			measCnt	<=	0;
+		end	
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(oscMode)	begin
+				if	(startMeasDspPos)	begin
+					oscWind	<=	1'b1;
+				end	
+				if	(pMeasEnd)	begin
+					oscWind	<=	1'b0;
+				end
+			end	else	begin
+				oscWind	<=	1'b0;
+			end
+		end	else	begin
+			oscWind	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i) begin
+		if	(!Rst_i)	begin
+			if	(measWindEnd)	begin
+				startFpConv	<=	1'b1;
+			end	else	begin
+				startFpConv	<=	1'b0;
+			end
+		end	else	begin
+			startFpConv	<=	1'b0;
+		end
+	end
+
+	always @(posedge Clk_i) begin
+		startFpConvPipe[0]  <= startFpConv;
+		for(i=1; i<4; i=i+1) begin
+			startFpConvPipe	[i]<=startFpConvPipe[i-1];
+		end
+	end
+	
+	always 	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(pNumCntRes)	begin
+				pNumCnt	<=	{WindPNumWidth{1'b0}};
+			end	else	begin
+				pNumCnt	<=	pNumCnt	+	{{WindPNumWidth-1{1'b0}},1'b1};
+			end
+		end	else	begin
+			pNumCnt	<=	{WindPNumWidth{1'b0}};
+		end
+	end
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			startMeasReg	<=	StartMeas_i;
+		end	else	begin
+			startMeasReg	<=	1'b0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			startMeasDspReg	<=	StartMeasDsp_i;
+		end	else	begin
+			startMeasDspReg	<=	1'b0;
+		end
+	end
+	
+	always	@(*)	begin	
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(!measWind)	begin
+					if	(startMeasCmd)	begin
+						measWind	=	1'b1;
+					end	
+				end	else	if	(stopCalc)	begin	
+					measWind	=	1'b0;
+				end
+			end	else	begin
+				measWind	=	1'b0;
+			end
+		end	else	begin
+			measWind	=	1'b0;
+		end
+	end
+
+endmodule

src/src/InternalDsp/NcoRstGen.v

@@ -0,0 +1,115 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:		15:22:20 12/08/2019 
+// Design Name: 
+// Module Name:		Win_parameters
+// Project Name:	Compact_main
+// Target Devices: 
+// Tool versions: 
+// Description: 	
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module NcoRstGen	
+(
+	input	Clk_i,
+	input	Rst_i,
+	input	[31:0]	NcoPhInc_i,
+	input	StartMeasEvent_i,
+	
+	output	NcoRst_o,
+	output	StartMeasEvent_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	[15:0]	startMeasEventReg;
+	reg	[31:0]	ncoPhIncReg;
+	reg	[31:0]	ncoPhIncRegR;
+	
+	wire	ncoPhIncUpdateFlag	=	(ncoPhIncRegR!=ncoPhIncReg);
+	wire	delFlag	=	(startMeasEventReg[15]);
+	
+	reg	[1:0]	currState;
+	
+	reg	rst;
+//================================================================================
+//  PARAMETERS
+//================================================================================
+	parameter	[1:0]	IDLE	=	2'd0;
+	parameter	[1:0]	RST		=	2'd1;
+	parameter	[1:0]	DEL		=	2'd2;
+//================================================================================
+//  ASSIGNMENTS
+// ================================================================================	
+	assign	NcoRst_o	=	rst;
+	assign	StartMeasEvent_o	=	(currState	==	IDLE)?	StartMeasEvent_i:startMeasEventReg[15];
+//================================================================================
+//  CODING
+//================================================================================	
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			ncoPhIncReg		<=	NcoPhInc_i;
+			ncoPhIncRegR	<=	ncoPhIncReg;
+		end	else	begin
+			ncoPhIncReg		<=	0;
+			ncoPhIncRegR	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			startMeasEventReg	<=	{startMeasEventReg[15:0],StartMeasEvent_i};
+		end	else	begin
+			startMeasEventReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			case(currState)
+			IDLE	:	begin
+							if (ncoPhIncUpdateFlag)	begin
+								currState	<= RST;
+								rst	<=	1'b1;
+							end	else begin
+								currState	<= IDLE;
+								rst	<=	1'b0;
+							end
+						end
+						
+			RST		:	begin
+							if	(rst	&	StartMeasEvent_i)	begin
+								currState	<= DEL;
+								rst	<=	1'b0;
+							end	else begin
+								currState	<= RST;
+								rst	<=	1'b1;
+							end
+						end
+		
+			DEL		:	begin
+							if	(delFlag)	begin
+								currState  <= IDLE;
+								rst	<=	1'b0;
+							end	else begin
+								currState  <= DEL;
+								rst	<=	1'b0;
+							end
+						end
+			endcase
+		end	else	begin
+			currState	<=	2'd0;
+		end
+	end
+
+endmodule

src/src/InternalDsp/WinParameters.v

@@ -0,0 +1,406 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:12:30 06/03/2020 
+// Design Name: 
+// Module Name:    WinParameters 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: kek
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module WinParameters 
+#(	
+	parameter	WindPhIncWidth		=	48,
+	parameter	WindNormCoefWidth	=	14,
+	parameter	WindPNumWidth		=	32,
+	parameter	BandCmdWidth		=	16
+)
+(	
+	input		Clk_i,
+	input		Rst_i,
+	input		[BandCmdWidth-1:0]		FilterCmd_i,
+	output		[WindPhIncWidth-1:0]	WinPhInc_o,
+	output		[WindPhIncWidth-1:0]	WinPhIncStart_o,
+	output		[WindNormCoefWidth-1:0]	WinNormCoef_o,
+	output		[WindPNumWidth-1:0]		WinPointsNum_o,
+	output		[WindPNumWidth-1:0]		AverageNoiseLvl_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg [WindPhIncWidth-1:0]	windPhInc;
+	reg	[WindNormCoefWidth-1:0]	winNormCoef;
+	reg	[WindPNumWidth-1:0]		winPointsNum;
+	reg	[WindPNumWidth-1:0]		averageNoiseLvl;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================	
+	assign	WinPhInc_o 			=	windPhInc;
+	assign	WinPhIncStart_o		 =	32'h80000000;
+	assign	WinNormCoef_o		=	winNormCoef;
+	assign	WinPointsNum_o		=	winPointsNum;
+	assign	AverageNoiseLvl_o	=	averageNoiseLvl;
+//================================================================================
+//  CODING
+//================================================================================	
+always	@	(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case (FilterCmd_i)			
+			8'h0 : begin	//	1	Hz
+						windPhInc		<=	32'h2a8;
+						// winNormCoef		<=	32'h334269d2;
+						winNormCoef		<=	32'h3395e8ca;
+						winPointsNum	<=	32'h30291a0;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h1 : begin//	1.5	Hz
+						windPhInc		<=	32'h3fc;
+						// winNormCoef		<=	32'h3391cf5e;
+						winNormCoef		<=	32'h3395e8ca;
+						winPointsNum	<=	32'h201b66a;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h2 : begin//	2	Hz
+						windPhInc		<=	32'h550;
+						// winNormCoef		<=	32'h33c269d2;
+						winNormCoef		<=	32'h33c7e10e;
+						winPointsNum	<=	32'h18148d0;
+						averageNoiseLvl	<=	32'h0;
+					 end
+			8'h3 : begin//	3	Hz
+						windPhInc		<=	32'h7f9;
+						// winNormCoef		<=	32'h3411ccc1;
+						winNormCoef		<=	32'h3415e61b;
+						winPointsNum	<=	32'h100db35;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h4 : begin//	5	Hz
+						windPhInc		<=	32'hd49;
+						// winNormCoef		<=	32'h347301aa;
+						winNormCoef		<=	32'h3479d6a3;
+						winPointsNum	<=	32'h9a1d20;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h5 : begin//	7	Hz
+						windPhInc		<=	32'h129a;
+						// winNormCoef		<=	32'h34aa19fd;
+						winNormCoef		<=	32'h34aee23e;
+						winPointsNum	<=	32'h6e14cd;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h10 : begin//	10	Hz
+						windPhInc		<=	32'h1a93;
+						// winNormCoef		<=	32'h34f3005d;
+						winNormCoef		<=	32'h34f9d54a;
+						winPointsNum	<=	32'h4d0e90;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h11 : begin//	15	Hz
+						windPhInc		<=	32'h27dd;
+						// winNormCoef		<=	32'h35363ff7;
+						winNormCoef		<=	32'h353b5fa5;
+						winPointsNum	<=	32'h335f0a;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h12 : begin//	20	Hz
+						windPhInc		<=	32'h3527;
+						// winNormCoef		<=	32'h3572ffba;
+						winNormCoef		<=	32'h3579d49f;
+						winPointsNum	<=	32'h268748;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h13 : begin//	30	Hz
+						windPhInc		<=	32'h4fbb;
+						// winNormCoef		<=	32'h35b63fa7;
+						winNormCoef		<=	32'h35bb5f4e;
+						winPointsNum	<=	32'h19af85;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h14 : begin//	50	Hz
+						windPhInc		<=	32'h84e3;
+						// winNormCoef		<=	32'h3617df9c;
+						winNormCoef		<=	32'h361c24a2;
+						winPointsNum	<=	32'hf6950;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h15 : begin//	70	Hz
+						windPhInc		<=	32'hba0b;
+						// winNormCoef		<=	32'h36549f77;
+						winNormCoef		<=	32'h365a99ac;
+						winPointsNum	<=	32'hb0214;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h20 : begin//	100	Hz
+						windPhInc		<=	32'h109c7;
+						// winNormCoef		<=	32'h3697df93;
+						winNormCoef		<=	32'h369c248d;
+						winPointsNum	<=	32'h7b4a8;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h21 : begin//	150	Hz
+						windPhInc		<=	32'h18eab;
+						// winNormCoef		<=	32'h36e3cf84;
+						winNormCoef		<=	32'h36ea36ec;
+						winPointsNum	<=	32'h5231a;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h22 : begin//	200	Hz
+						windPhInc		<=	32'h21390;
+						// winNormCoef		<=	32'h3717df94;
+						winNormCoef		<=	32'h371c2478;
+						winPointsNum	<=	32'h3da54;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h23 : begin//	300	Hz 
+						windPhInc		<=	32'h31d5b;
+						// winNormCoef		<=	32'h3763cf83;
+						winNormCoef		<=	32'h376a36b6;
+						winPointsNum	<=	32'h2918d;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h24 : begin//	500	Hz
+						windPhInc		<=	32'h530e3;
+						// winNormCoef		<=	32'h37bdd7e8;
+						winNormCoef		<=	32'h37c32db2;
+						winPointsNum	<=	32'h18a88;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h25 : begin//	700	Hz
+						windPhInc		<=	32'h7449e;
+						// winNormCoef		<=	32'h3804e417;
+						winNormCoef		<=	32'h38089ffd;
+						winPointsNum	<=	32'h119ce;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h30 : begin//	1	kHz
+						windPhInc		<=	32'ha61fc;
+						// winNormCoef		<=	32'h383dd7e8;
+						winNormCoef		<=	32'h38432d23;
+						winPointsNum	<=	32'hc544;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h31 : begin//	1.5	kHz
+						windPhInc		<=	32'hf92fb;
+						// winNormCoef		<=	32'h388e6329;
+						winNormCoef		<=	32'h389262af;
+						winPointsNum	<=	32'h8382;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h32 : begin//	2	kHz
+						windPhInc		<=	32'h14c3f9;
+						// winNormCoef		<=	32'h38bdd900;
+						winNormCoef		<=	32'h38c32d23;
+						winPointsNum	<=	32'h62a2;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h33 : begin//	3	kHz
+						windPhInc		<=	32'h1f25f6;
+						// winNormCoef		<=	32'h390e6466;
+						winNormCoef		<=	32'h391262b5;
+						winPointsNum	<=	32'h41c1;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h34 : begin//	5	kHz
+						windPhInc		<=	32'h33ee26;
+						// winNormCoef		<=	32'h396d509f;
+						winNormCoef		<=	32'h3973f593;
+						winPointsNum	<=	32'h2774;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h35 : begin//	7	kHz
+						windPhInc		<=	32'h48bca9;
+						// winNormCoef		<=	32'h39a61fcc;
+						winNormCoef		<=	32'h39aac491;
+						winPointsNum	<=	32'h1c2e;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h40 : begin//	10	kHz
+						windPhInc		<=	32'h67dc4c;
+						// winNormCoef		<=	32'h39ed577f;
+						winNormCoef		<=	32'h39f3f593;
+						winPointsNum	<=	32'h13ba;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h41 : begin//	15	kHz
+						windPhInc		<=	32'h9c09c0;
+						// winNormCoef		<=	32'h3a3206c8;
+						winNormCoef		<=	32'h3a36f82e;
+						winPointsNum	<=	32'hd26;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h42 : begin//	20	kHz
+						windPhInc 		<=	32'hd00d00;
+						// winNormCoef		<=	32'h3a6d577f;
+						winNormCoef		<=	32'h3a73e7a1;
+						winPointsNum	<=	32'h9dd;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h43 : begin//	30	kHz
+						windPhInc		<=	32'h1381381;
+						// winNormCoef		<=	32'h3ab21643;
+						winNormCoef		<=	32'h3ab6f82e;
+						winPointsNum	<=	32'h693;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h44 : begin//	50	kHz
+						windPhInc		<=	32'h2082082;
+						// winNormCoef		<=	32'h3b14707d;
+						winNormCoef		<=	32'h3b1870f3;
+						winPointsNum	<=	32'h3f2;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h45 : begin//	70	KHz
+						windPhInc		<=	32'h2d82d82;
+						// winNormCoef		<=	32'h3b500d01;
+						winNormCoef		<=	32'h3b559010;
+						winPointsNum	<=	32'h2d1;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h50 : begin//	100	KHz
+						windPhInc		<=	32'h4104104;
+						// winNormCoef		<=	32'h3b949b93;
+						winNormCoef		<=	32'h3b98700b;
+						winPointsNum	<=	32'h1f9;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h51 : begin//	150	KHz
+						windPhInc 		<=	32'h6186186;
+						// winNormCoef		<=	32'h3bdfac1f;
+						winNormCoef		<=	32'h3be52dcd;
+						winPointsNum	<=	32'h150;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h52 : begin//	200	KHz
+						windPhInc		<=	32'h8421084;
+						// winNormCoef		<=	32'h3c14f209;
+						winNormCoef		<=	32'h3c18700b;
+						winPointsNum	<=	32'hfc;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h53 : begin//	300	KHz
+						windPhInc 		<=	32'hc30c30c;
+						// winNormCoef		<=	32'h3c607038;
+						winNormCoef		<=	32'h3c652dcd;
+						winPointsNum	<=	32'ha8;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h54 : begin//	500	KHz
+						windPhInc 		<=	32'h1c71c71;
+						// winNormCoef		<=	32'h3ce38e38;
+						winNormCoef		<=	32'h3ce98ccd;
+						winPointsNum	<=	32'h90;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h55 : begin//	700	KHz
+						windPhInc		<=	32'h2828282;
+						// winNormCoef		<=	32'h3d20a0a0;
+						winNormCoef		<=	32'h3d24cd6d;
+						winPointsNum	<=	32'h66;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h60 : begin//	1	MHz
+						windPhInc 		<=	32'h38e38e3;
+						// winNormCoef		<=	32'h3d638e39;
+						winNormCoef		<=	32'h3d698ccd;
+						winPointsNum	<=	32'h48;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h61 : begin//	1.5	MHz
+						windPhInc 		<=	32'h5555555;
+						// winNormCoef		<=	32'h3daaaaab;
+						winNormCoef		<=	32'h3daf299a;
+						winPointsNum	<=	32'h30;
+						averageNoiseLvl	<=	32'h0;
+					end
+			8'h62 : begin//	2	MHz
+						windPhInc 		<=	32'h71c71c7;
+						// winNormCoef		<=	32'h3de38e39;
+						winNormCoef		<=	32'h3de98759;
+						winPointsNum	<=	32'h24;
+						averageNoiseLvl	<=	32'h0;
+					end	
+			8'h63 : begin
+						windPhInc 		<=	32'h0;
+						// winNormCoef		<=	32'h3e124925;
+						winNormCoef		<=	32'h3e1665f8;
+						winPointsNum	<=	32'he;
+						averageNoiseLvl	<=	32'h3b83126f;
+					end	
+			// 8'h64 : begin//	5	MHz
+						// windPhInc 		<=	32'h12492492;
+						// winNormCoef		<=	32'h3e924925;
+						// winPointsNum	<=	32'he;
+					// end	
+			// 8'h64 : begin//	2,46	MHz
+						// windPhInc 		<=	32'h9d89d89;
+						// winNormCoef		<=	32'h3df76c57;
+						// winPointsNum	<=	32'h1a;
+					// end	
+			// 8'h70 : begin
+						// параметры для калибровки - прямоугольное окно 65536 отсчетов	2^16
+						// windPhInc 		<=	32'h1FFFFFFF;
+						// winNormCoef		<=	32'h6D13892;
+						// winPointsNum	<=	32'h10000;
+					// end	
+			// 8'h71 : begin
+						// 7.5MHZ
+						// windPhInc 		<=	32'h1c71c71c;
+						// winNormCoef		<=	32'h3ee38e39;
+						// winPointsNum	<=	32'h9;
+					// end	
+			// 8'h72 : begin
+						// 10MHZ
+						// windPhInc 		<=	32'h24924924;
+						// winNormCoef		<=	32'h3f124925;
+						// winPointsNum	<=	32'h7;
+					// end	
+			8'h64 : begin
+						windPhInc 		<=	32'h0;
+						// winNormCoef		<=	32'h3e800000;
+						winNormCoef		<=	32'h3e839930;
+						winPointsNum	<=	32'h8;
+						averageNoiseLvl	<=	32'h3bc49ba6;
+					end	
+			8'h70 : begin
+						// параметры для калибровки - прямоугольное окно 65536 отсчетов	2^16
+						windPhInc 		<=	32'h1FFFFFFF;
+						winNormCoef		<=	32'h6D13892;
+						winPointsNum	<=	32'h10000;
+						averageNoiseLvl	<=	32'h0;
+					end	
+			8'h71 : begin							
+						windPhInc 		<=	32'h0;
+						// winNormCoef		<=	32'h3eaaaaab;
+						winNormCoef		<=	32'h3eaf76cd;
+						winPointsNum	<=	32'h6;
+						averageNoiseLvl	<=	32'h3c03126f;
+					end	
+			8'h72 : begin	
+						windPhInc 		<=	32'h0;
+						// winNormCoef		<=	32'h3f000000;
+						winNormCoef		<=	32'h3f039939;
+						winPointsNum	<=	32'h4;
+						averageNoiseLvl	<=	32'h3a83126f;
+					end
+					
+			default: begin	
+						windPhInc 		<=	32'h15555555;
+						winNormCoef		<=	32'h3e86cfea;
+						winPointsNum	<=	32'hc;
+						averageNoiseLvl	<=	32'h0;
+					 end					 
+		endcase
+	end	
+end
+endmodule
+

src/src/InternalDsp/Win_calc.v

@@ -0,0 +1,195 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)	
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:		15:22:20 12/08/2019 
+// Design Name: 
+// Module Name:		Win_parameters
+// Project Name:	Compact_main
+// Target Devices: 
+// Tool versions: 
+// Description: 	
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Win_calc	(
+	input			clk_i,
+	input	[7:0]	filterCmd_i,
+	input			reset_i,
+	input			WinCtrl_i,
+	input			MeasWind_i,
+	input	[1:0]	TukeyCtrl_i,
+	input	[31:0]	win_value_i,
+	input	[2:0]	win_type_i,	
+	output	signed [17:0]	win_o,
+	output	reg	signed [17:0]	sinWin_o
+);
+
+//================================================================================
+//  PARAMETERS
+//================================================================================
+	localparam	signed	A3_1	=	18'h15584;
+// ????????? ??? ?????????? SIN
+	localparam signed	[17:0]	A1	=	18'h12400;			// a-1
+	localparam signed	[17:0]	A2	=	18'h002C0;			// b
+	localparam signed	[17:0]	A3	=	~A3_1	+	1'b1;	// c
+	localparam signed	[17:0]	A4	=	18'h0126C;			// d
+	localparam signed	[17:0]	A5	=	18'h01C5C;			// e
+	
+	localparam	CalcWidth			=	10;
+	localparam	CalcWidthR			=	18;
+	localparam	b2Width				=	CalcWidth*2;
+	localparam	b3Width				=	CalcWidth*3;
+	localparam	b4Width				=	CalcWidth*4;
+	localparam	b5Width				=	CalcWidth*5;
+	
+	localparam [31:0]	testArg	=	32'h12492492;
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg			signed	[17:0]	sinWind;
+	reg			signed	[17:0]	tukeyWind;	
+		
+	reg	[1:0]	tukeyCtrlR;
+	reg	[1:0]	tukeyCtrlRR;
+	
+	reg	[35:0]	sinWindPow2;
+	
+	wire	sinFilterFlag	=	(filterCmd_i>=8'h54	&	filterCmd_i<=8'h62);
+	wire	rectFilterFlag	=	(filterCmd_i>=8'h63	&	filterCmd_i!=8'h70);
+	
+	wire	[CalcWidth-1:0]	bCurr	=	win_value_i[31]	?	10'h3FF	-	win_value_i[31-:CalcWidth]	:	win_value_i	[31-:CalcWidth];
+	
+	wire	[CalcWidthR-1:0]	bNew	=	win_value_i[31]	?	18'h3FFFF	-	win_value_i[31:14]	:	win_value_i	[31:14];
+	
+	wire	signed	[17:0]	constOne	=	18'b011111111111111111;
+	
+	reg		signed	[18:0]	tukeyCorr;
+	
+	reg		[17:0]	tukeyWindOut;
+	
+	wire	signed [17:0]	windMux1;
+	wire	signed [17:0]	windMux2;
+	
+	wire	signed	[b2Width-1:0]	b2	=	bCurr**2;
+	wire	signed	[b3Width-1:0]	b3	=	bCurr**3;
+	wire	signed	[b4Width-1:0]	b4	=	bCurr**4;
+	wire	signed	[b5Width-1:0]	b5	=	bCurr**5;
+	
+	wire	signed	[CalcWidthR-1:0]	b2Cut	=	b2[b2Width-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b3Cut	=	b3[b3Width-3-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b4Cut	=	b4[b4Width-4-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	b5Cut	=	b5[b5Width-5-:CalcWidthR];
+	
+	reg		signed	[CalcWidthR*2-1:0]	a1b;
+	reg		signed	[CalcWidthR*2-1:0]	a2b2;
+	reg		signed	[CalcWidthR*2-1:0]	a3b3;
+	reg		signed	[CalcWidthR*2-1:0]	a4b4;
+	reg		signed	[CalcWidthR*2-1:0]	a5b5;
+	
+	wire	signed	[CalcWidthR-1:0]	a1bCut	=	a1b	[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a2b2Cut	=	a2b2[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a3b3Cut	=	a3b3[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a4b4Cut	=	a4b4[CalcWidthR*2-2-:CalcWidthR];
+	wire	signed	[CalcWidthR-1:0]	a5b5Cut	=	a5b5[CalcWidthR*2-2-:CalcWidthR];
+	
+	reg		signed	[CalcWidthR-1:0]	bPrevSh;
+		
+	wire	signed	[CalcWidthR-1:0]	approxSin	=	a5b5Cut+a4b4Cut+a3b3Cut+a2b2Cut+a1bCut+bPrevSh;	
+	
+	wire	signed	[CalcWidthR-1:0]	resultSin	=	approxSin[17]?	18'h1ffff:approxSin;
+//================================================================================
+//  ASSIGNMENTS
+// ================================================================================	
+	
+	assign	windMux1	=	(sinFilterFlag)	?	sinWindPow2[34-:18]:tukeyWindOut;
+	assign	windMux2	=	(rectFilterFlag)?	18'h1ffff:windMux1;
+
+	assign	win_o		=	windMux2;
+// ================================================================================
+//  CODING
+//================================================================================	
+
+always	@(posedge	clk_i)	begin
+	if	(!reset_i)	begin
+		a5b5	<=	A5*b5Cut;
+		a4b4	<=	A4*b4Cut;
+		a3b3	<=	A3*b3Cut;
+		a2b2	<=	A2*b2Cut;
+		a1b		<=	A1*bNew;
+		bPrevSh	<=	bNew;
+	end	else	begin
+		a5b5	<=	0;
+		a4b4	<=	0;
+		a3b3	<=	0;
+		a2b2	<=	0;
+		a1b		<=	0;
+		bPrevSh	<=	0;
+	end
+end
+
+always	@(posedge	clk_i)	begin
+	if	(!reset_i)	begin
+		tukeyCtrlR	<=	TukeyCtrl_i;
+		tukeyCtrlRR	<=	tukeyCtrlR;
+	end	else	begin
+		tukeyCtrlR	<=	0;
+		tukeyCtrlRR	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!reset_i)	begin
+		tukeyCorr	=	(tukeyWind+constOne);
+		sinWindPow2	=	resultSin**2;
+	end	else	begin
+		tukeyCorr	=	18'h0;
+		sinWindPow2	=	18'h0;
+	end
+end
+
+always	@(*)	begin
+	if	(!reset_i)	begin
+		case(tukeyCtrlR)
+			2'h0:		begin
+							tukeyWindOut	=	0;
+						end
+			2'h1:		begin
+							tukeyWindOut	=	18'h1ffff;
+						end
+			2'h2:		begin
+							tukeyWindOut	=	tukeyCorr[18-:18];
+						end
+			default:	begin
+							tukeyWindOut	=	0;
+						end
+		endcase
+	end	else	begin
+		tukeyWindOut	=	18'h0;
+	end
+end
+
+
+always	@(*)	begin
+	if	(!reset_i)	begin
+		if	(!win_type_i)	begin 
+			if	(!WinCtrl_i)	begin
+				tukeyWind	=	resultSin;
+			end	else	begin
+				tukeyWind	=	0-resultSin;
+			end
+		end	else	begin
+			tukeyWind	=	18'h0;
+		end
+	end	else	begin
+		tukeyWind	=	18'h0;
+	end
+end
+endmodule

src/src/Math/FpCustomMultiplier.v

@@ -0,0 +1,125 @@
+module FpCustomMultiplier 
+# (
+	parameter	ManWidth	=	16,
+	parameter	ExpWidth	=	6
+)
+(
+	Rst_i,
+	Clk_i,
+	A_i,
+	B_i,
+	Nd_i,
+	Result_o,
+	ResultValid_o
+);	
+
+	localparam	InOutWidth	=	1+ExpWidth+ManWidth;
+	
+	input	Rst_i;
+	input	Clk_i;
+	
+	input	[InOutWidth-1:0]	A_i;
+	input	[InOutWidth-1:0]	B_i;
+	input	Nd_i;
+	output	[InOutWidth-1:0]	Result_o;
+	output	ResultValid_o;
+	
+	localparam	ExtManWidth			=	2+ManWidth;
+	localparam	MultResultWidth		=	(ExtManWidth*2)-2;
+	localparam	ExpConst			=	(2**(ExpWidth-1))-1;
+	
+	reg	expA_or;
+	reg	expB_or;
+	
+	reg	signed	[ExtManWidth-1:0]	manAReg;
+	reg	signed	[ExtManWidth-1:0]	manBReg;
+	
+	reg	[ExpWidth-1:0]	expAReg;
+	reg	[ExpWidth-1:0]	expBReg;
+	
+	always	@(posedge	Clk_i)	begin
+		expA_or	<=	|A_i[InOutWidth-2 -:ExpWidth];	//looking for zero exponents for mult operation
+		expB_or	<=	|B_i[InOutWidth-2 -:ExpWidth];
+		
+		manAReg	<=	{2'b01,A_i[ManWidth-1 -:ManWidth]};	//add 0-sign and implied 1 to mantissa.
+		manBReg	<=	{2'b01,B_i[ManWidth-1 -:ManWidth]};
+		
+		expAReg	<=	A_i[InOutWidth-2 -:ExpWidth];	//exp highlight
+		expBReg	<=	B_i[InOutWidth-2 -:ExpWidth];
+	end
+	
+	reg	[ExpWidth:0]	expAddProd;
+	reg	expZero;
+	reg	signed	[MultResultWidth-1:0]	manMultProd;
+	
+	always	@(posedge	Clk_i)	begin
+		manMultProd	<=	manAReg*manBReg;	//man(C)=man(A)*man(B)
+		
+		expAddProd	<=	expAReg+expBReg-ExpConst;	//exp(C)=exp(A)+exp(B)-ExpConst. ExpConst = 2^ExpWidth-1;
+		
+		expZero	<=	~(expA_or&expB_or);	//setting exp(C) = 0 when either A or B is zero or denormalized.
+	end
+	
+	reg	[ExpWidth-1:0]	expCReg;
+	reg	expResultNegative;
+	reg	[ManWidth-1:0]	manCReg;
+	
+	always	@(posedge	Clk_i)	begin
+		expResultNegative	<=	expAddProd[ExpWidth]; //if exponents are too small then their result will be negative
+		
+		if	(Rst_i)	begin
+			expCReg	<=	{ExpWidth{1'b0}};
+		end	else	if	(expAddProd[ExpWidth]||expZero)	begin
+			expCReg	<=	{ExpWidth{1'b0}};
+		end	else	begin
+			expCReg	<=	expAddProd[ExpWidth-1:0]+manMultProd[MultResultWidth-1];
+		end
+		
+		if	(Rst_i)	begin
+			manCReg	<=	{ManWidth{1'b0}};
+		end	else	if	(expAddProd[ExpWidth]||expZero)	begin
+			manCReg	<=	{ManWidth{1'b0}};
+		end	else	if	(!manMultProd[MultResultWidth-1])	begin	//normalize man(C) in accordance to MSB value
+			manCReg	<=	manMultProd[MultResultWidth-3 -:ManWidth];	
+		end	else	begin
+			manCReg	<=	manMultProd[MultResultWidth-2 -:ManWidth];
+		end
+	end
+		
+	reg	[4:0]	signCShReg;
+	always	@(posedge	Clk_i)	begin
+		signCShReg	<=	{signCShReg[3:0], A_i[InOutWidth-1] ^ B_i[InOutWidth-1]};
+	end
+	
+	reg	[5:0]	resValidShReg;
+	always	@(posedge	Clk_i)	begin
+		resValidShReg	<=	{resValidShReg[4:0],	Nd_i};
+	end
+	
+	assign Result_o = {signCShReg[2], expCReg,manCReg};
+	assign ResultValid_o = resValidShReg[2];
+	
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/Math/MultModule.v

@@ -0,0 +1,76 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	MultModule	
+#(	
+	parameter	AdcDataWidth	=	14,
+	parameter	IfNcoOutWidth	=	18,
+	parameter	MultDataWidth	=	36
+)	
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	signed	[AdcDataWidth-1:0]	AdcData_i,
+	input	signed	[IfNcoOutWidth-1:0]	Sin_i,
+	input	signed	[IfNcoOutWidth-1:0]	Cos_i,
+	output	signed	[MultDataWidth-1:0]	AdcSin_o,
+	output	signed	[MultDataWidth-1:0]	AdcCos_o
+);
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+//  REG/WIRE
+	reg	signed	[IfNcoOutWidth-1:0]	adcDataCompl;
+	reg	signed	[IfNcoOutWidth-1:0]	sinReg;
+	reg	signed	[IfNcoOutWidth-1:0]	cosReg;
+	
+	reg	signed	[MultDataWidth-1:0]	AdcSinReg;
+	reg	signed	[MultDataWidth-1:0]	AdcCosReg;
+//================================================================================
+//  ASSIGNMENTS
+	assign	AdcSin_o	=	AdcSinReg;
+	assign	AdcCos_o	=	AdcCosReg;
+//================================================================================
+//  CODING
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			adcDataCompl	<=	{AdcData_i,4'b0};
+			sinReg	<=	Sin_i;
+			cosReg	<=	Cos_i;
+		end	else	begin
+			adcDataCompl	<=	0;
+			sinReg	<=	0;
+			cosReg	<=	0;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			AdcSinReg	<=	adcDataCompl*sinReg;
+			AdcCosReg	<=	adcDataCompl*cosReg;
+		end	else	begin
+			AdcSinReg	<=	{MultDataWidth{1'b0}};
+			AdcCosReg	<=	{MultDataWidth{1'b0}};
+		end
+	end
+	
+endmodule

src/src/Math/MyIntToFp.v

@@ -0,0 +1,153 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:14:34 01/28/2021 
+// Design Name: 
+// Module Name:    FpConvTop 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	MyIntToFp	
+#(	
+	parameter	InWidth		=	32,
+	parameter	ExpWidth	=	8,
+	parameter	ManWidth	=	23,
+	parameter	FracWidth	=	17
+)
+(Clk_i,Rst_i,InData_i,AverageNoizeLvl_i,InDataVal_i,OutData_o,OutDataVal_o);
+
+	input	Clk_i;
+	input	Rst_i;
+	input	[InWidth-1:0]	InData_i;
+	input	InDataVal_i;
+	
+	localparam	OutWidth	=	1+ExpWidth+ManWidth;	//sign+ExpWidth+ManWidth
+	localparam	ExpConst	=	(2**(ExpWidth-1))-1;
+	
+	input		[OutWidth-1:0]	AverageNoizeLvl_i;
+	output	reg	[OutWidth-1:0]	OutData_o;
+	output	reg	OutDataVal_o;
+	
+//================================================================================
+//  Func
+	function integer Log2;
+	input integer value;
+		begin
+			Log2 = 0;
+			while (value > 1) begin
+				value   = value >> 1;
+				Log2    = Log2 + 1;
+			end
+			
+			if	((2**Log2)<InWidth)	begin
+				Log2	=	Log2+1;
+			end	
+		end
+	endfunction
+	
+	localparam Stages = Log2(InWidth);
+	
+//================================================================================
+//  Coding
+	reg		[InWidth-1:0]	inDataR;
+	reg		signR;
+	reg		outValR;
+	wire	[OutWidth-1:0]	fpOut;
+	wire	[Stages-1:0]	distance;
+	genvar  i;
+	wire	[ExpWidth-1:0]	fpExp;
+	
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		inDataR	<=	{InWidth{1'b0}};
+		signR	<=	1'b0;
+		outValR	<=	1'b0;
+	end	else	begin
+		if	(InData_i	[InWidth-1])	begin
+			inDataR	<=	~InData_i+1'b1;
+		end	else	begin
+			inDataR	<=	InData_i;
+		end
+		signR	<=	InData_i[InWidth-1];
+		outValR	<=	InDataVal_i;
+	end
+end
+
+wire	[(Stages+1)*InWidth-1:0]	dataArray;
+
+assign  dataArray [InWidth-1:0] = inDataR;			
+	
+generate	
+	for (i=0; i<Stages; i=i+1)	begin: searchMSB
+		wire [InWidth-1:0] dataIn;	
+        wire [InWidth-1:0] shiftedDataOut;
+        wire [InWidth-1:0] dataOut;
+		
+        assign  dataIn = dataArray[(i+1)*InWidth-1:i*InWidth];
+
+        wire    shiftDesired = ~|(dataIn[InWidth-1:InWidth-(1 << (Stages-1-i))]);
+        assign  distance[(Stages-1-i)] = shiftDesired;		
+        assign  shiftedDataOut = dataIn << (1 << (Stages-1-i));	
+        assign  dataOut = shiftDesired ? shiftedDataOut : dataIn;	
+        assign  dataArray[(i+2)*InWidth-1:(i+1)*InWidth] = dataOut;	
+	end
+endgenerate
+
+wire	[InWidth-1:0]	scaledData	=	dataArray[(Stages+1)*InWidth-1:Stages*InWidth];
+wire	[ManWidth-1:0]	mantisa		=	scaledData[InWidth-2 -:ManWidth];
+
+assign	fpExp		=	(ExpConst+(InWidth-1-FracWidth))-distance;
+assign	fpOut		=	&distance ? {signR, 31'h0}:	{signR, fpExp,	mantisa};
+
+always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
+	if	(Rst_i)	begin
+		OutData_o		<=	{OutWidth{1'b0}};
+		OutDataVal_o	<=	1'b0;
+	end	else	begin
+		if	(outValR)	begin
+			if	(fpOut!=0)	begin
+				OutData_o	<=	fpOut;
+			end	else	begin
+				// OutData_o	<=	32'h3a83126f;
+				OutData_o	<=	AverageNoizeLvl_i;
+			end
+		end
+		OutDataVal_o	<=	outValR;
+	end
+end
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/Math/SimpleMult.v

@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    SimpleMult 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	SimpleMult	
+#(	
+	parameter	FactorAWidth	=	14,
+	parameter	FactorBWidth	=	14,
+	parameter	OutputWidth		=	18
+)	
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	Val_i,
+	input	signed	[FactorAWidth-1:0]	FactorA_i,
+	input	signed	[FactorBWidth-1:0]	FactorB_i,
+	
+	
+	output	signed	[OutputWidth-1:0]	Result_o,
+	output	ResultVal_o
+);
+
+//================================================================================
+//  LOCALPARAM
+	localparam	ResultWidth	=	FactorAWidth+FactorBWidth;
+//================================================================================
+//  REG/WIRE
+	reg	[ResultWidth-1:0]	resultReg;
+	reg	resultValReg;
+//================================================================================
+//  ASSIGNMENTS
+	assign	Result_o	=	(ResultWidth==OutputWidth)?	resultReg:resultReg[ResultWidth-2-:OutputWidth];
+	assign	ResultVal_o	=	resultValReg;
+//================================================================================
+//  CODING
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(Val_i)	begin
+				resultReg		<=	FactorA_i*FactorB_i;
+				resultValReg	<=	Val_i;
+			end	else	begin
+				resultReg		<=	{ResultWidth{1'b0}};
+				resultValReg	<=	1'b0;
+			end
+		end	else	begin
+			resultReg		<=	{ResultWidth{1'b0}};
+			resultValReg	<=	1'b0;
+		end
+	end
+endmodule

src/src/Math/SumAcc.v

@@ -0,0 +1,64 @@
+module SumAcc 
+#(	
+	parameter	IDataWidth	=	14,
+	parameter	ODataWidth	=	48
+)
+(
+    input	Clk_i,
+    input	Rst_i,
+    input	Val_i,
+    input	AccZeroing_i,
+	input	[IDataWidth-1:0]	Data_i,
+	
+	output	[ODataWidth-1:0]	Result_o,
+	output	ResultVal_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+
+//================================================================================
+//  REG/WIRE
+	reg		[ODataWidth-1:0]	dataAcc;
+	reg		resultVal;
+	wire	[ODataWidth-1:0]	extData	=	{{(ODataWidth - IDataWidth){Data_i[IDataWidth-1]}}, Data_i};	//sign extension
+	
+	reg		accZeroing;
+	reg		accZeroingR;
+	reg		accZeroingRR;
+//================================================================================
+//  ASSIGNMENTS
+	assign	Result_o	=	dataAcc;
+	assign	ResultVal_o	=	resultVal;
+//================================================================================
+//  CODING
+
+	always	@(posedge	Clk_i)	begin
+		if	(Rst_i)	begin
+			accZeroing		<=	0;
+			accZeroingR		<=	0;
+			accZeroingRR		<=	0;
+		end	else	begin
+			accZeroing		<=	AccZeroing_i;
+			accZeroingR		<=	accZeroing;
+			accZeroingRR	<=	accZeroingR;
+		end
+	end
+	
+	always	@(posedge	Clk_i)	begin
+		if	(Rst_i)	begin
+			dataAcc		<=	{ODataWidth{1'b0}};
+		end	else	if	(Val_i)	begin
+			if	(!accZeroingRR)	begin
+				dataAcc		<=	dataAcc+extData;
+			end	else	begin
+				dataAcc		<=	0+extData;
+			end
+		resultVal	<=	accZeroingR;
+		end	else	begin
+			dataAcc		<=	0;
+			resultVal	<=	0;
+		end
+	end
+
+endmodule

src/src/MeasDataFifo/FifoController.v

@@ -0,0 +1,110 @@
+`timescale 1ns / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:12:30 06/03/2020 
+// Design Name: 
+// Module Name:    WinParameters 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: kek
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
+	
+module FifoController	
+#(
+	parameter	TxInPack		=	200,		
+	parameter	WorkTimeCycles	=	404000
+	// parameter	WorkTimeCycles	=	20000
+)
+(
+	input	Clk_i, 
+	input	Rst_i,	
+	input	PpiBusy_i,	
+	input	DspReadyForRx_i,
+	input	MeasDataVal_i,
+	input	[32-1:0]	MeasNum_i,
+	input	FullFlag_i,
+	input	EmptyFlag_i,
+	
+	output	MeasDataVal_o,
+	
+	output	reg	WrEn_o,
+	output	RdEn_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	rdEn;
+	reg	[13:0]	wrCnt;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	MeasDataVal_o	=	rdEn&(!PpiBusy_i);
+	assign	RdEn_o			=	rdEn&(!PpiBusy_i);
+	
+//================================================================================
+//  CODING
+//================================================================================		
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(WrEn_o)	begin
+			wrCnt	<=	wrCnt+14'd1;
+		end	
+	end	else	begin
+		wrCnt	<=	14'd0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!FullFlag_i)	begin
+			if	(MeasDataVal_i)	begin
+				if	(wrCnt!=MeasNum_i)	begin
+					WrEn_o	<=	1'b1;
+				end	else	begin
+					WrEn_o	<=	1'b0;
+				end
+			end	else	begin
+				WrEn_o	<=	1'b0;
+			end
+		end	else	begin
+			WrEn_o	<=	1'b0;
+		end
+	end	else	begin
+		WrEn_o	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(!DspReadyForRx_i)	begin
+			if	(!PpiBusy_i)	begin
+				if	(!EmptyFlag_i)	begin
+					rdEn	<=	1'b1;
+				end	else	begin
+					rdEn	<=	1'b0;
+				end
+			end	else	begin
+				rdEn	<=	1'b0;
+			end
+		end	else	begin
+			rdEn	<=	1'b0;
+		end
+	end	else	begin
+		rdEn	<=	1'b0;
+	end
+end
+
+endmodule

src/src/MeasDataFifo/MeasDataFifoWrapper.v

@@ -0,0 +1,103 @@
+`timescale 1ns / 1ns
+	
+module MeasDataFifoWrapper	
+#(	
+	parameter	DataWidth	=	32,
+	parameter	ChNum		=	4
+)
+(
+	input	Clk_i, 
+	input	Rst_i,	
+	input	PpiBusy_i,	
+	input	StartMeasDsp_i,
+	input	DspReadyForRx_i,
+	input	[DataWidth-1:0]	MeasNum_i,
+	
+	input	[DataWidth*(ChNum*2)-1:0]	MeasDataBus_i,
+	input	MeasDataVal_i,
+	
+	output	[DataWidth*(ChNum*2)-1:0]	MeasDataBus_o,
+	output	MeasDataVal_o
+);
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+	wire	fullFlag;
+	wire	emptyFlag;
+	wire	wrEn;
+	wire	rdEn;
+
+	reg		startMeasDspReg;
+	wire	startMeasDspNeg;
+	wire	startMeasDspPos;
+	
+	reg		ppiBusyReg;
+	
+	reg		rstFromDsp;
+	wire	trueRstFromDsp;
+	
+	integer	i;
+	reg	[0:0]	rstFromDspPipe	[49:0];
+	
+	reg		[13:0]	rdCnt;
+	wire	rstOr;
+	
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	rstOr	=	Rst_i|startMeasDspPos;
+	assign	MeasDataVal_o		=	rdEn;
+	assign	startMeasDspPos		=	(StartMeasDsp_i&(!startMeasDspReg));
+//================================================================================
+//  CODING
+//================================================================================		
+
+always	@(posedge	Clk_i)	begin
+	if	(!rstOr)	begin
+		if	(rdEn)	begin
+			rdCnt	<=	rdCnt+14'd1;
+		end	
+	end	else	begin
+		rdCnt	<=	14'd0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		startMeasDspReg	<=	StartMeasDsp_i;
+	end	else	begin
+		startMeasDspReg	<=	1'b0;
+	end
+end
+
+MeasDataFifo	MeasDataFifoInst
+(
+	.clk	(Clk_i),
+	.srst	(Rst_i|startMeasDspPos),
+	.din	(MeasDataBus_i),
+	.wr_en	(wrEn),
+	.rd_en	(rdEn),
+	.dout	(MeasDataBus_o),
+	.full	(fullFlag),
+	.empty	(emptyFlag)
+);
+
+  
+FifoController	FifoControllerInst
+(
+	.Clk_i				(Clk_i), 
+	.Rst_i				(Rst_i|startMeasDspPos),	
+	.DspReadyForRx_i	(DspReadyForRx_i),	
+	.PpiBusy_i			(PpiBusy_i),	
+	.MeasNum_i			(MeasNum_i),	
+	.MeasDataVal_i		(MeasDataVal_i),
+	.FullFlag_i			(fullFlag),
+	.EmptyFlag_i		(emptyFlag),
+	
+	.MeasDataVal_o		(),
+	.WrEn_o				(wrEn),
+	.RdEn_o				(rdEn)
+);
+
+endmodule

src/src/PCIeImports/EP_MEM.v

@@ -0,0 +1,995 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : EP_MEM.v
+// Version    : 3.3
+//--
+//-- Description: Endpoint Memory: 8KB organized as 4 x (512 DW) BlockRAM banks.
+//--              Block RAM Port A: Read Port
+//--              Block RAM Port B: Write Port
+//--
+//--------------------------------------------------------------------------------
+
+
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module EP_MEM (
+
+                      clk_i,
+
+  a_rd_a_i_0,  // [8:0]   Port A Read Address Bank 0
+  a_rd_d_o_0,  // [31:0]  Port A Read Data Bank 0
+  a_rd_en_i_0, //         Port A Read Enable Bank 0
+
+  b_wr_a_i_0,  // [8:0]   Port B Write Address Bank 0
+  b_wr_d_i_0,  // [31:0]  Port B Write Data Bank 0
+  b_wr_en_i_0, //         Port B Write Enable Bank 0
+  b_rd_d_o_0,  // [31:0]  Port B Read Data Bank 0
+  b_rd_en_i_0, //         Port B Read Enable Bank 0
+
+  a_rd_a_i_1,  // [8:0]   Port A Read Address Bank 1
+  a_rd_d_o_1,  // [31:0]  Port A Read Data Bank 1
+  a_rd_en_i_1,
+
+  b_wr_a_i_1,  // [8:0]   Port B Write Address Bank 1
+  b_wr_d_i_1,  // [31:0]  Port B Write Data Bank 1
+  b_wr_en_i_1, //         Port B Write Enable Bank 1
+  b_rd_d_o_1,  // [31:0]  Port B Read Data Bank 1
+  b_rd_en_i_1, //         Port B Read Enable Bank 1
+
+  a_rd_a_i_2,  // [8:0]   Port A Read Address Bank 2
+  a_rd_d_o_2,  // [31:0]  Port A Read Data Bank 2
+  a_rd_en_i_2,
+
+  b_wr_a_i_2,  // [8:0]   Port B Write Address Bank 2
+  b_wr_d_i_2,  // [31:0]  Port B Write Data Bank 2
+  b_wr_en_i_2, //         Port B Write Enable Bank 2
+  b_rd_d_o_2,  // [31:0]  Port B Read Data Bank 2
+  b_rd_en_i_2, //         Port B Read Enable Bank 2
+
+  a_rd_a_i_3,  // [8:0]   Port A Read Address Bank 3
+  a_rd_d_o_3,  // [31:0]  Port A Read Data Bank 3
+  a_rd_en_i_3,
+
+  b_wr_a_i_3,  // [8:0]   Port B Write Address Bank 3
+  b_wr_d_i_3,  // [31:0]  Port B Write Data Bank 3
+  b_wr_en_i_3, //         Port B Write Enable Bank 3
+  b_rd_d_o_3,  // [31:0]  Port B Read Data Bank 3
+  b_rd_en_i_3  //         Port B Read Enable Bank 3
+
+                      );
+
+    input             clk_i;
+
+    input  [08:00]    a_rd_a_i_0;
+    output [31:00]    a_rd_d_o_0;
+    input             a_rd_en_i_0;
+
+    input  [08:00]    b_wr_a_i_0;
+    input  [31:00]    b_wr_d_i_0;
+    input             b_wr_en_i_0;
+    output [31:00]    b_rd_d_o_0;
+    input             b_rd_en_i_0;
+
+    input  [08:00]    a_rd_a_i_1;
+    output [31:00]    a_rd_d_o_1;
+    input             a_rd_en_i_1;
+
+    input  [08:00]    b_wr_a_i_1;
+    input  [31:00]    b_wr_d_i_1;
+    input             b_wr_en_i_1;
+    output [31:00]    b_rd_d_o_1;
+    input             b_rd_en_i_1;
+
+    input  [08:00]    a_rd_a_i_2;
+    output [31:00]    a_rd_d_o_2;
+    input             a_rd_en_i_2;
+
+    input  [08:00]    b_wr_a_i_2;
+    input  [31:00]    b_wr_d_i_2;
+    input             b_wr_en_i_2;
+    output [31:00]    b_rd_d_o_2;
+    input             b_rd_en_i_2;
+
+    input  [08:00]    a_rd_a_i_3;
+    output [31:00]    a_rd_d_o_3;
+    input             a_rd_en_i_3;
+
+    input  [08:00]    b_wr_a_i_3;
+    input  [31:00]    b_wr_d_i_3;
+    input             b_wr_en_i_3;
+    output [31:00]    b_rd_d_o_3;
+    input             b_rd_en_i_3;
+
+  //----------------------------------------------------------------
+  //
+  //  4 x 512 DWs Buffer Banks (512 x 32 bits + 512 x 4 bits)
+  //    1 each for IO, Mem32, Mem64 and EROM
+  //----------------------------------------------------------------
+
+   RAMB36E1 #(
+      .SIM_DEVICE("7SERIES"),
+      .RDADDR_COLLISION_HWCONFIG( "DELAYED_WRITE" ),
+      .DOA_REG(1),  // Optional output registers on A port (0 or 1)
+      .DOB_REG(1),  // Optional output registers on B port (0 or 1)
+      .INIT_A(36'h000000000),  // Initial values on A output port
+      .INIT_B(36'h000000000),  // Initial values on B output port
+      .EN_ECC_READ( "FALSE" ),
+      .EN_ECC_WRITE( "FALSE" ),
+      .RAM_EXTENSION_A("NONE"),  // "UPPER", "LOWER" or "NONE" when cascaded
+      .RAM_EXTENSION_B("NONE"),  // "UPPER", "LOWER" or "NONE" when cascaded
+      .RAM_MODE( "TDP" ),
+      .READ_WIDTH_A(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .READ_WIDTH_B(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .RSTREG_PRIORITY_A( "REGCE" ),
+      .RSTREG_PRIORITY_B( "REGCE" ),
+      .SIM_COLLISION_CHECK("ALL"),  // Collision check enable "ALL", "WARNING_ONLY",
+                                    //   "GENERATE_X_ONLY" or "NONE
+      .SRVAL_A(36'h000000000), // Set/Reset value for A port output
+      .SRVAL_B(36'h000000000),  // Set/Reset value for B port output
+      .WRITE_MODE_A("WRITE_FIRST"),  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
+      .WRITE_MODE_B("WRITE_FIRST"),  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
+      .WRITE_WIDTH_A(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .WRITE_WIDTH_B(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+
+      // The following INIT_xx declarations specify the initial contents of the RAM
+      .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+
+      // The next set of INITP_xx are for the parity bits
+      .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
+   ) ep_io_mem (
+
+      
+      .DOADO(a_rd_d_o_0[31:0]),      // 32-bit A port data output
+      .DOBDO(b_rd_d_o_0[31:0]),      // 32-bit B port data output
+      .DOPADOP(),    // 4-bit A port parity data output
+      .DOPBDOP(),    // 4-bit B port parity data output
+      .ADDRARDADDR({1'b0,a_rd_a_i_0[8:0],6'b0}),  // 16-bit A port address input
+      .ADDRBWRADDR ({1'b0,b_wr_a_i_0[8:0],6'b0}),  // 16-bit B port address input
+      .CLKARDCLK(clk_i),     // 1-bit A port clock input
+      .CLKBWRCLK(clk_i),     // 1-bit B port clock input
+      .DIADI(32'b0),       // 32-bit A port data input
+      .DIBDI(b_wr_d_i_0[31:0]),       // 32-bit B port data input
+      .DIPADIP(4'b0000),     // 4-bit A port parity data input
+      .DIPBDIP(4'b0),     // 4-bit B port parity data input
+      .ENARDEN(a_rd_en_i_0),       // 1-bit A port enable input
+      .ENBWREN(b_rd_en_i_0),       // 1-bit B port enable input
+      .REGCEAREGCE (1'b1), // 1-bit A port register enable input
+      .REGCEB(1'b1), // 1-bit B port register enable input
+      .WEA(4'b0),       // 4-bit A port write enable input
+      .WEBWE({4'b0,b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0}), // 4-bit B port write enable input
+      .DBITERR(),
+      .INJECTDBITERR(1'b0),
+      .INJECTSBITERR(1'b0),
+      .RSTRAMARSTRAM(1'b0),
+      .RSTRAMB(1'b0),
+      .RSTREGARSTREG(1'b0),
+      .RSTREGB(1'b0),
+      .SBITERR(),
+      .ECCPARITY(),
+      .RDADDRECC(),
+      .CASCADEINA(),
+      .CASCADEINB(),
+      .CASCADEOUTA(),
+      .CASCADEOUTB()
+
+   );
+
+
+   RAMB36E1 #(
+      .SIM_DEVICE("7SERIES"),
+      .RDADDR_COLLISION_HWCONFIG( "DELAYED_WRITE" ),
+      .DOA_REG(1),  // Optional output registers on A port (0 or 1)
+      .DOB_REG(1),  // Optional output registers on B port (0 or 1)
+      .INIT_A(36'h000000000),  // Initial values on A output port
+      .INIT_B(36'h000000000),  // Initial values on B output port
+      .EN_ECC_READ( "FALSE" ),
+      .EN_ECC_WRITE( "FALSE" ),
+      .RAM_EXTENSION_A("NONE"),  // "UPPER", "LOWER" or "NONE" when cascaded
+      .RAM_EXTENSION_B("NONE"),  // "UPPER", "LOWER" or "NONE" when cascaded
+      .RAM_MODE( "TDP" ),
+      .READ_WIDTH_A(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .READ_WIDTH_B(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .RSTREG_PRIORITY_A( "REGCE" ),
+      .RSTREG_PRIORITY_B( "REGCE" ),
+      .SIM_COLLISION_CHECK("ALL"),  // Collision check enable "ALL", "WARNING_ONLY",
+                                    //   "GENERATE_X_ONLY" or "NONE
+      .SRVAL_A(36'h000000000), // Set/Reset value for A port output
+      .SRVAL_B(36'h000000000),  // Set/Reset value for B port output
+      .WRITE_MODE_A("WRITE_FIRST"),  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
+      .WRITE_MODE_B("WRITE_FIRST"),  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
+      .WRITE_WIDTH_A(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .WRITE_WIDTH_B(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+
+      // The following INIT_xx declarations specify the initial contents of the RAM
+      .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+
+      // The next set of INITP_xx are for the parity bits
+      .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
+   ) ep_mem32 (
+      .DOADO(a_rd_d_o_1[31:0]),      // 32-bit A port data output
+      .DOBDO(b_rd_d_o_1[31:0]),      // 32-bit B port data output
+      .DOPADOP(),    // 4-bit A port parity data output
+      .DOPBDOP(),    // 4-bit B port parity data output
+      .ADDRARDADDR({1'b0,a_rd_a_i_1[8:0],6'b0}),  // 16-bit A port address input
+      .ADDRBWRADDR({1'b0,b_wr_a_i_1[8:0],6'b0}),  // 16-bit B port address input
+      .CLKARDCLK(clk_i),     // 1-bit A port clock input
+      .CLKBWRCLK(clk_i),     // 1-bit B port clock input
+      .DIADI(32'b0),       // 32-bit A port data input
+      .DIBDI(b_wr_d_i_1[31:0]),       // 32-bit B port data input
+      .DIPADIP(4'b0000),     // 4-bit A port parity data input
+      .DIPBDIP(4'b0),     // 4-bit B port parity data input
+      .ENARDEN(a_rd_en_i_1),       // 1-bit A port enable input
+      .ENBWREN(b_rd_en_i_1),       // 1-bit B port enable input
+      .REGCEAREGCE(1'b1), // 1-bit A port register enable input
+      .REGCEB(1'b1), // 1-bit B port register enable inputt
+      .WEA(4'b0),       // 4-bit A port write enable input
+      .WEBWE({4'b0,b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1}), // 4-bit B port write enable input
+      .DBITERR(),
+      .INJECTDBITERR(1'b0),
+      .INJECTSBITERR(1'b0),
+      .RSTRAMARSTRAM(1'b0),
+      .RSTRAMB(1'b0),
+      .RSTREGARSTREG(1'b0),
+      .RSTREGB(1'b0),
+      .SBITERR(),
+      .ECCPARITY(),
+      .RDADDRECC(),
+      .CASCADEINA(),
+      .CASCADEINB(),
+      .CASCADEOUTA(),
+      .CASCADEOUTB()
+   );
+
+   RAMB36E1 #(
+      .SIM_DEVICE("7SERIES"),
+      .RDADDR_COLLISION_HWCONFIG( "DELAYED_WRITE" ),
+      .DOA_REG(1),  // Optional output registers on A port (0 or 1)
+      .DOB_REG(1),  // Optional output registers on B port (0 or 1)
+      .INIT_A(36'h000000000),  // Initial values on A output port
+      .INIT_B(36'h000000000),  // Initial values on B output port
+      .EN_ECC_READ( "FALSE" ),
+      .EN_ECC_WRITE( "FALSE" ),
+      .RAM_EXTENSION_A("NONE"),  // "UPPER", "LOWER" or "NONE" when cascaded
+      .RAM_EXTENSION_B("NONE"),  // "UPPER", "LOWER" or "NONE" when cascaded
+      .RAM_MODE( "TDP" ),
+      .READ_WIDTH_A(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .READ_WIDTH_B(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .RSTREG_PRIORITY_A( "REGCE" ),
+      .RSTREG_PRIORITY_B( "REGCE" ),
+      .SIM_COLLISION_CHECK("ALL"),  // Collision check enable "ALL", "WARNING_ONLY",
+                                    //   "GENERATE_X_ONLY" or "NONE
+      .SRVAL_A(36'h000000000), // Set/Reset value for A port output
+      .SRVAL_B(36'h000000000),  // Set/Reset value for B port output
+      .WRITE_MODE_A("WRITE_FIRST"),  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
+      .WRITE_MODE_B("WRITE_FIRST"),  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
+      .WRITE_WIDTH_A(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .WRITE_WIDTH_B(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+
+      // The following INIT_xx declarations specify the initial contents of the RAM
+      .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+
+      // The next set of INITP_xx are for the parity bits
+      .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
+   ) ep_mem64 (
+      .DOADO(a_rd_d_o_2[31:0]),      // 32-bit A port data output
+      .DOBDO(b_rd_d_o_2[31:0]),      // 32-bit B port data output
+      .DOPADOP(),    // 4-bit A port parity data output
+      .DOPBDOP(),    // 4-bit B port parity data output
+      .ADDRARDADDR({1'b0,a_rd_a_i_2[8:0],6'b0}),  // 16-bit A port address input
+      .ADDRBWRADDR({1'b0,b_wr_a_i_2[8:0],6'b0}),  // 16-bit B port address input
+      .CLKARDCLK(clk_i),     // 1-bit A port clock input
+      .CLKBWRCLK(clk_i),     // 1-bit B port clock input
+      .DIADI(32'b0),       // 32-bit A port data input
+      .DIBDI(b_wr_d_i_2[31:0]),       // 32-bit B port data input
+      .DIPADIP(4'b0000),     // 4-bit A port parity data input
+      .DIPBDIP(4'b0),     // 4-bit B port parity data input
+      .ENARDEN(a_rd_en_i_2),       // 1-bit A port enable input
+      .ENBWREN(b_rd_en_i_2),       // 1-bit B port enable input
+      .REGCEAREGCE(1'b1), // 1-bit A port register enable input
+      .REGCEB(1'b1), // 1-bit B port register enable input
+      .WEA(4'b0),       // 4-bit A port write enable input
+      .WEBWE({4'b0,b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2}),  // 4-bit B port write enable input
+      .DBITERR(),
+      .INJECTDBITERR(1'b0),
+      .INJECTSBITERR(1'b0),
+      .RSTRAMARSTRAM(1'b0),
+      .RSTRAMB(1'b0),
+      .RSTREGARSTREG(1'b0),
+      .RSTREGB(1'b0),
+      .SBITERR(),
+      .ECCPARITY(),
+      .RDADDRECC(),
+      .CASCADEINA(),
+      .CASCADEINB(),
+      .CASCADEOUTA(),
+      .CASCADEOUTB()
+   );
+
+
+
+   RAMB36E1 #(
+      .SIM_DEVICE("7SERIES"),
+      .RDADDR_COLLISION_HWCONFIG( "DELAYED_WRITE" ),
+      .DOA_REG(1),  // Optional output registers on A port (0 or 1)
+      .DOB_REG(1),  // Optional output registers on B port (0 or 1)
+      .INIT_A(36'h000000000),  // Initial values on A output port
+      .INIT_B(36'h000000000),  // Initial values on B output port
+      .EN_ECC_READ( "FALSE" ),
+      .EN_ECC_WRITE( "FALSE" ),
+      .RAM_EXTENSION_A("NONE"),  // "UPPER", "LOWER" or "NONE" when cascaded
+      .RAM_EXTENSION_B("NONE"),  // "UPPER", "LOWER" or "NONE" when cascaded
+      .RAM_MODE( "TDP" ),
+      .READ_WIDTH_A(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .READ_WIDTH_B(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .RSTREG_PRIORITY_A( "REGCE" ),
+      .RSTREG_PRIORITY_B( "REGCE" ),
+      .SIM_COLLISION_CHECK("ALL"),  // Collision check enable "ALL", "WARNING_ONLY",
+                                    //   "GENERATE_X_ONLY" or "NONE
+      .SRVAL_A(36'h000000000), // Set/Reset value for A port output
+      .SRVAL_B(36'h000000000),  // Set/Reset value for B port output
+      .WRITE_MODE_A("WRITE_FIRST"),  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
+      .WRITE_MODE_B("WRITE_FIRST"),  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
+      .WRITE_WIDTH_A(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+      .WRITE_WIDTH_B(36),  // Valid values are 1, 2, 4, 9, 18, or 36
+
+      // The following INIT_xx declarations specify the initial contents of the RAM
+      .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+
+      // The next set of INITP_xx are for the parity bits
+      .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+      .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
+   ) ep_mem_erom (
+      .DOADO(a_rd_d_o_3[31:0]),      // 32-bit A port data output
+      .DOBDO(b_rd_d_o_3[31:0]),      // 32-bit B port data output
+      .DOPADOP(),    // 4-bit A port parity data output
+      .DOPBDOP(),    // 4-bit B port parity data output
+      .ADDRARDADDR({1'b0,a_rd_a_i_3[8:0],6'b0}),  // 16-bit A port address input
+      .ADDRBWRADDR({1'b0,b_wr_a_i_3[8:0],6'b0}),  // 16-bit B port address input
+      .CLKARDCLK(clk_i),     // 1-bit A port clock input
+      .CLKBWRCLK(clk_i),     // 1-bit B port clock input
+      .DIADI(32'b0),       // 32-bit A port data input
+      .DIBDI(b_wr_d_i_3[31:0]),       // 32-bit B port data input
+      .DIPADIP(4'b0000),     // 4-bit A port parity data input
+      .DIPBDIP(4'b0),     // 4-bit B port parity data input
+      .ENARDEN(a_rd_en_i_3),       // 1-bit A port enable input
+      .ENBWREN(b_rd_en_i_3),       // 1-bit B port enable input
+      .REGCEAREGCE(1'b1), // 1-bit A port register enable input
+      .REGCEB(1'b1), // 1-bit B port register enable input
+      .WEA(4'b0),       // 4-bit A port write enable input
+      .WEBWE({4'b0,b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3}),  // 4-bit B port write enable input
+      .DBITERR(),
+      .INJECTDBITERR(1'b0),
+      .INJECTSBITERR(1'b0),
+      .RSTRAMARSTRAM(1'b0),
+      .RSTRAMB(1'b0),
+      .RSTREGARSTREG(1'b0),
+      .RSTREGB(1'b0),
+      .SBITERR(),
+      .ECCPARITY(),
+      .RDADDRECC(),
+      .CASCADEINA(),
+      .CASCADEINB(),
+      .CASCADEOUTA(),
+      .CASCADEOUTB()
+   );
+
+
+endmodule
+

src/src/PCIeImports/PIO.v

@@ -0,0 +1,179 @@
+
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : PIO.v
+// Version    : 3.3
+//
+// Description:  Programmed I/O module. Design implements 8 KBytes of programmable
+//--              memory space. Host processor can access this memory space using
+//--              Memory Read 32 and Memory Write 32 TLPs. Design accepts
+//--              1 Double Word (DW) payload length on Memory Write 32 TLP and
+//--              responds to 1 DW length Memory Read 32 TLPs with a Completion
+//--              with Data TLP (1DW payload).
+//--
+//--------------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module PIO #(
+  parameter C_DATA_WIDTH = 64,            // RX/TX interface data width
+
+  // Do not override parameters below this line
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8,              // TSTRB width
+  parameter TCQ        = 1
+)(
+  input                         user_clk,
+  input                         user_reset,
+  input                         user_lnk_up,
+
+  // AXIS
+  input                         s_axis_tx_tready,
+  output  [C_DATA_WIDTH-1:0]    s_axis_tx_tdata,
+  output  [KEEP_WIDTH-1:0]      s_axis_tx_tkeep,
+  output                        s_axis_tx_tlast,
+  output                        s_axis_tx_tvalid,
+  output                        tx_src_dsc,
+
+
+  input  [C_DATA_WIDTH-1:0]     m_axis_rx_tdata,
+  input  [KEEP_WIDTH-1:0]       m_axis_rx_tkeep,
+  input                         m_axis_rx_tlast,
+  input                         m_axis_rx_tvalid,
+  output                        m_axis_rx_tready,
+  input    [21:0]               m_axis_rx_tuser,
+
+
+  input                         cfg_to_turnoff,
+  output                        cfg_turnoff_ok,
+
+  input [15:0]                  cfg_completer_id,
+
+  input   [63:0] MeasData_i,
+  input   MeasEnd_i,
+
+  output  StartMeasCmd_o
+
+); // synthesis syn_hier = "hard"
+
+
+  // Local wires
+
+  wire          req_compl;
+  wire          compl_done;
+  reg           pio_reset_n;
+
+  always @(posedge user_clk) begin
+    if (user_reset)
+        pio_reset_n <= #TCQ 1'b0;
+    else
+        pio_reset_n <= #TCQ user_lnk_up;
+  end
+
+  //
+  // PIO instance
+  //
+
+  PIO_EP  #(
+    .C_DATA_WIDTH( C_DATA_WIDTH ),
+    .KEEP_WIDTH( KEEP_WIDTH ),
+    .TCQ( TCQ )
+  ) PIO_EP_inst (
+
+    .clk( user_clk ),                             // I
+    .rst_n( pio_reset_n ),                        // I
+
+    .s_axis_tx_tready( s_axis_tx_tready ),        // I
+    .s_axis_tx_tdata( s_axis_tx_tdata ),          // O
+    .s_axis_tx_tkeep( s_axis_tx_tkeep ),          // O
+    .s_axis_tx_tlast( s_axis_tx_tlast ),          // O
+    .s_axis_tx_tvalid( s_axis_tx_tvalid ),        // O
+    .tx_src_dsc( tx_src_dsc ),                    // O
+
+    .m_axis_rx_tdata( m_axis_rx_tdata ),          // I
+    .m_axis_rx_tkeep( m_axis_rx_tkeep ),          // I
+    .m_axis_rx_tlast( m_axis_rx_tlast ),          // I
+    .m_axis_rx_tvalid( m_axis_rx_tvalid ),        // I
+    .m_axis_rx_tready( m_axis_rx_tready ),        // O
+    .m_axis_rx_tuser ( m_axis_rx_tuser ),         // I
+
+    .req_compl(req_compl),                        // O
+    .compl_done(compl_done),                      // O
+
+    .cfg_completer_id ( cfg_completer_id ),        // I [15:0]
+
+    .MeasData_i(MeasData_i),
+    .MeasEnd_i(MeasEnd_i),
+
+    .StartMeasCmd_o(StartMeasCmd_o)
+  );
+
+
+  //
+  // Turn-Off controller
+  //
+
+  PIO_TO_CTRL #(
+    .TCQ( TCQ )
+  ) PIO_TO_inst  (
+    .clk( user_clk ),                       // I
+    .rst_n( pio_reset_n ),                  // I
+
+    .req_compl( req_compl ),                // I
+    .compl_done( compl_done ),              // I
+
+    .cfg_to_turnoff( cfg_to_turnoff ),      // I
+    .cfg_turnoff_ok( cfg_turnoff_ok )       // O
+  );
+
+
+endmodule // PIO
+

src/src/PCIeImports/PIO_EP.v

@@ -0,0 +1,273 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : PIO_EP.v
+// Version    : 3.3
+//
+// Description: Endpoint Programmed I/O module.
+//              Consists of Receive and Transmit modules and a Memory Aperture
+//
+//------------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module PIO_EP #(
+  parameter C_DATA_WIDTH = 64,            // RX/TX interface data width
+
+  // Do not override parameters below this line
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8,              // TSTRB width
+  parameter TCQ        = 1
+) (
+
+  input                         clk,
+  input                         rst_n,
+
+  // AXIS TX
+  input                         s_axis_tx_tready,
+  output  [C_DATA_WIDTH-1:0]    s_axis_tx_tdata,
+  output  [KEEP_WIDTH-1:0]      s_axis_tx_tkeep,
+  output                        s_axis_tx_tlast,
+  output                        s_axis_tx_tvalid,
+  output                        tx_src_dsc,
+
+  //AXIS RX
+  input   [C_DATA_WIDTH-1:0]    m_axis_rx_tdata,
+  input   [KEEP_WIDTH-1:0]      m_axis_rx_tkeep,
+  input                         m_axis_rx_tlast,
+  input                         m_axis_rx_tvalid,
+  output                        m_axis_rx_tready,
+  input   [21:0]                m_axis_rx_tuser,
+
+  output                        req_compl,
+  output                        compl_done,
+
+  input   [15:0]                cfg_completer_id,
+
+  input   [63:0] MeasData_i,
+  input   MeasEnd_i,
+
+  output  StartMeasCmd_o
+);
+
+    // Local wires
+
+    wire  [10:0]      rd_addr;
+    wire  [3:0]       rd_be;
+    wire  [31:0]      rd_data;
+
+    wire  [10:0]      wr_addr;
+    wire  [7:0]       wr_be;
+    (* DONT_TOUCH = "yes" *) wire  [31:0]      wr_data;
+    wire              wr_en;
+    wire              wr_busy;
+
+    wire              req_compl_int;
+    wire              req_compl_wd;
+    wire              compl_done_int;
+
+    wire  [2:0]       req_tc;
+    wire              req_td;
+    wire              req_ep;
+    wire  [1:0]       req_attr;
+    wire  [9:0]       req_len;
+    wire  [15:0]      req_rid;
+    wire  [7:0]       req_tag;
+    wire  [7:0]       req_be;
+    wire  [12:0]      req_addr;
+    
+    wire valToCfgReg;
+    wire valToMeasData;
+
+    //
+    // ENDPOINT MEMORY : 8KB memory aperture implemented in FPGA BlockRAM(*)
+    //
+
+    PIO_EP_MEM_ACCESS  #(
+       .TCQ( TCQ )
+       ) EP_MEM_inst (
+      
+      .clk(clk),               // I
+      .rst_n(rst_n),           // I
+      
+      // Read Port
+      
+      .rd_addr(rd_addr),     // I [10:0]
+      .rd_be(rd_be),         // I [3:0]
+      .rd_data(),     // O [31:0]
+      
+      // Write Port
+      
+      .wr_addr(wr_addr),     // I [10:0]
+      .wr_be(wr_be),         // I [7:0]
+      .wr_data(wr_data),     // I [31:0]
+      .wr_en(wr_en),         // I
+      .wr_busy(wr_busy)      // O
+      );
+
+    //
+    // Local-Link Receive Controller
+    //
+
+  PIO_RX_ENGINE #(
+    .C_DATA_WIDTH( C_DATA_WIDTH ),
+    .KEEP_WIDTH( KEEP_WIDTH ),
+    .TCQ( TCQ )
+
+  ) EP_RX_inst (
+
+    .clk(clk),                              // I
+    .rst_n(rst_n),                          // I
+
+    // AXIS RX
+    .m_axis_rx_tdata( m_axis_rx_tdata ),    // I
+    .m_axis_rx_tkeep( m_axis_rx_tkeep ),    // I
+    .m_axis_rx_tlast( m_axis_rx_tlast ),    // I
+    .m_axis_rx_tvalid( m_axis_rx_tvalid ),  // I
+    .m_axis_rx_tready( m_axis_rx_tready ),  // O
+    .m_axis_rx_tuser ( m_axis_rx_tuser ),   // I
+
+    // Handshake with Tx engine
+    .req_compl(req_compl_int),              // O
+    .req_compl_wd(req_compl_wd),            // O
+    .compl_done(compl_done_int),            // I
+
+    .req_tc(req_tc),                        // O [2:0]
+    .req_td(req_td),                        // O
+    .req_ep(req_ep),                        // O
+    .req_attr(req_attr),                    // O [1:0]
+    .req_len(req_len),                      // O [9:0]
+    .req_rid(req_rid),                      // O [15:0]
+    .req_tag(req_tag),                      // O [7:0]
+    .req_be(req_be),                        // O [7:0]
+    .req_addr(req_addr),                    // O [12:0]
+                                            
+    // Memory Write Port                    
+    .wr_addr(wr_addr),                      // O [10:0]
+    .wr_be(wr_be),
+    .wr_data_msb(wr_data),                  // O [31:0]
+    .wr_en(wr_en),                          // O
+    .wr_busy(wr_busy),                       // I
+    
+    .ValToCfgReg_o    (valToCfgReg),                                   
+    .ValToMeasData_o  (valToMeasData)                                   
+  );
+
+
+  IntermediateLogic IntermediateLogic 
+  (
+  .Clk_i(clk),
+  .Rst_i(~rst_n),
+
+  .MeasEnd_i(MeasEnd_i),
+
+  .ReadReq_i(req_compl_int),
+
+  .ValToCfgReg_i(valToCfgReg),
+  .CfgData_i(wr_data),
+ 
+  .ValToMeasData_i(valToMeasData),
+  .MeasData_i(MeasData_i),
+  
+  .StartMeasCmd_o(StartMeasCmd_o),
+  .Data_o(rd_data)
+  );
+
+    //
+    // Local-Link Transmit Controller
+    //
+
+  PIO_TX_ENGINE #(
+    .C_DATA_WIDTH( C_DATA_WIDTH ),
+    .KEEP_WIDTH( KEEP_WIDTH ),
+    .TCQ( TCQ )
+  )EP_TX_inst(
+
+    .clk(clk),                                  // I
+    .rst_n(rst_n),                              // I
+
+    // AXIS Tx
+    .s_axis_tx_tready( s_axis_tx_tready ),      // I
+    .s_axis_tx_tdata( s_axis_tx_tdata ),        // O
+    .s_axis_tx_tkeep( s_axis_tx_tkeep ),        // O
+    .s_axis_tx_tlast( s_axis_tx_tlast ),        // O
+    .s_axis_tx_tvalid( s_axis_tx_tvalid ),      // O
+    .tx_src_dsc( tx_src_dsc ),                  // O
+
+    // Handshake with Rx engine
+    .req_compl(req_compl_int),                // I
+    .req_compl_wd(req_compl_wd),              // I
+    .compl_done(compl_done_int),                // 0
+
+    .req_tc(req_tc),                          // I [2:0]
+    .req_td(req_td),                          // I
+    .req_ep(req_ep),                          // I
+    .req_attr(req_attr),                      // I [1:0]
+    .req_len(req_len),                        // I [9:0]
+    .req_rid(req_rid),                        // I [15:0]
+    .req_tag(req_tag),                        // I [7:0]
+    .req_be(req_be),                          // I [7:0]
+    .req_addr(req_addr),                      // I [12:0]
+
+    // Read Port
+
+    .rd_addr(rd_addr),                        // O [10:0]
+    .rd_be(rd_be),                            // O [3:0]
+    .rd_data(rd_data),                        // I [31:0]
+
+    .completer_id(cfg_completer_id)           // I [15:0]
+
+    );
+
+  assign req_compl  = req_compl_int;
+  assign compl_done = compl_done_int;
+
+endmodule // PIO_EP
+

src/src/PCIeImports/PIO_EP_MEM_ACCESS.v

@@ -0,0 +1,344 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : PIO_EP_MEM_ACCESS.v
+// Version    : 3.3
+//--
+//-- Description: Endpoint Memory Access Unit. This module provides access functions
+//--              to the Endpoint memory aperture.
+//--
+//--              Read Access: Module returns data for the specifed address and
+//--              byte enables selected.
+//--
+//--              Write Access: Module accepts data, byte enables and updates
+//--              data when write enable is asserted. Modules signals write busy
+//--              when data write is in progress.
+//--
+//--------------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module PIO_EP_MEM_ACCESS  #(
+  parameter TCQ = 1
+) (
+
+  clk,
+  rst_n,
+
+  // Read Access
+
+  rd_addr,     // I [10:0]  Read Address
+  rd_be,       // I [3:0]   Read Byte Enable
+  rd_data,     // O [31:0]  Read Data
+
+  // Write Access
+
+  wr_addr,     // I [10:0]  Write Address
+  wr_be,       // I [7:0]   Write Byte Enable
+  wr_data,     // I [31:0]  Write Data
+  wr_en,       // I         Write Enable
+  wr_busy      // O         Write Controller Busy
+
+);
+
+  input            clk;
+  input            rst_n;
+
+  //  Read Port
+
+  input  [10:0]    rd_addr;
+  input  [3:0]     rd_be;
+  output [31:0]    rd_data;
+
+  //  Write Port
+
+  input  [10:0]    wr_addr;
+  input  [7:0]     wr_be;
+  input  [31:0]    wr_data;
+  input            wr_en;
+  output           wr_busy;
+
+  localparam PIO_MEM_ACCESS_WR_RST   = 3'b000;
+  localparam PIO_MEM_ACCESS_WR_WAIT  = 3'b001;
+  localparam PIO_MEM_ACCESS_WR_READ  = 3'b010;
+  localparam PIO_MEM_ACCESS_WR_WRITE = 3'b100;
+
+  wire   [31:0]     rd_data;
+
+  reg   [31:0]      rd_data_raw_o;
+
+  wire  [31:0]     rd_data0_o, rd_data1_o, rd_data2_o, rd_data3_o;
+
+  wire             rd_data0_en, rd_data1_en, rd_data2_en, rd_data3_en;
+
+  wire             wr_busy;
+  reg              write_en;
+  reg   [31:0]     post_wr_data;
+  reg   [31:0]     w_pre_wr_data;
+
+  reg   [2:0]      wr_mem_state;
+
+  reg   [31:0]     pre_wr_data;
+  wire  [31:0]     w_pre_wr_data0;
+  wire  [31:0]     w_pre_wr_data1;
+  wire  [31:0]     w_pre_wr_data2;
+  wire  [31:0]     w_pre_wr_data3;
+
+  wire  [7:0]      w_pre_wr_data_b0;
+  wire  [7:0]      w_pre_wr_data_b1;
+  wire  [7:0]      w_pre_wr_data_b2;
+  wire  [7:0]      w_pre_wr_data_b3;
+
+  wire  [7:0]      w_wr_data_b0;
+  wire  [7:0]      w_wr_data_b1;
+  wire  [7:0]      w_wr_data_b2;
+  wire  [7:0]      w_wr_data_b3;
+
+
+  // Memory Write Process
+
+  //  Extract current data bytes. These need to be swizzled
+  //  BRAM storage format :
+  //    data[31:0] = { byte[3], byte[2], byte[1], byte[0] (lowest addr) }
+
+  assign w_pre_wr_data_b3 = pre_wr_data[31:24];
+  assign w_pre_wr_data_b2 = pre_wr_data[23:16];
+  assign w_pre_wr_data_b1 = pre_wr_data[15:08];
+  assign w_pre_wr_data_b0 = pre_wr_data[07:00];
+
+  //  Extract new data bytes from payload
+  //  TLP Payload format :
+  //    data[31:0] = { byte[0] (lowest addr), byte[2], byte[1], byte[3] }
+
+  assign w_wr_data_b3 = wr_data[07:00];
+  assign w_wr_data_b2 = wr_data[15:08];
+  assign w_wr_data_b1 = wr_data[23:16];
+  assign w_wr_data_b0 = wr_data[31:24];
+
+  always @(posedge clk) begin
+
+    if ( !rst_n )
+    begin
+
+      pre_wr_data <= #TCQ 32'b0;
+      post_wr_data <= #TCQ 32'b0;
+      pre_wr_data <= #TCQ 32'b0;
+      write_en   <= #TCQ 1'b0;
+
+      wr_mem_state <= #TCQ PIO_MEM_ACCESS_WR_RST;
+
+    end // if !rst_n
+    else
+    begin
+
+      case ( wr_mem_state )
+
+        PIO_MEM_ACCESS_WR_RST : begin
+
+          if (wr_en)
+          begin // read state
+            wr_mem_state <= #TCQ PIO_MEM_ACCESS_WR_WAIT; //Pipelining happens in RAM's internal output reg.
+          end
+          else
+          begin
+            write_en <= #TCQ 1'b0;
+            wr_mem_state <= #TCQ PIO_MEM_ACCESS_WR_RST;
+          end
+        end // PIO_MEM_ACCESS_WR_RST
+
+        PIO_MEM_ACCESS_WR_WAIT : begin
+
+          write_en <= #TCQ 1'b0;
+          wr_mem_state <= #TCQ PIO_MEM_ACCESS_WR_READ ;
+
+        end // PIO_MEM_ACCESS_WR_WAIT
+
+        PIO_MEM_ACCESS_WR_READ : begin
+
+            // Now save the selected BRAM B port data out
+
+            pre_wr_data <= #TCQ w_pre_wr_data;
+            write_en <= #TCQ 1'b0;
+            wr_mem_state <= #TCQ PIO_MEM_ACCESS_WR_WRITE;
+
+        end // PIO_MEM_ACCESS_WR_READ
+
+        PIO_MEM_ACCESS_WR_WRITE : begin
+
+          //Merge new enabled data and write target BlockRAM location
+
+          post_wr_data <= #TCQ {{wr_be[3] ? w_wr_data_b3 : w_pre_wr_data_b3},
+                               {wr_be[2] ? w_wr_data_b2 : w_pre_wr_data_b2},
+                               {wr_be[1] ? w_wr_data_b1 : w_pre_wr_data_b1},
+                               {wr_be[0] ? w_wr_data_b0 : w_pre_wr_data_b0}};
+          write_en     <= #TCQ 1'b1;
+          wr_mem_state <= #TCQ PIO_MEM_ACCESS_WR_RST;
+
+        end // PIO_MEM_ACCESS_WR_WRITE
+
+        default : begin
+          // default case stmt
+          wr_mem_state <= #TCQ PIO_MEM_ACCESS_WR_RST;
+        end // default
+
+      endcase // case (wr_mem_state)
+    end // if rst_n
+  end
+
+  // Write controller busy
+
+  assign wr_busy = wr_en | (wr_mem_state != PIO_MEM_ACCESS_WR_RST);
+
+  //  Select BlockRAM output based on higher 2 address bits
+
+  always @* 
+  begin
+    case ({wr_addr[10:9]}) // synthesis parallel_case full_case
+
+      2'b00 : w_pre_wr_data = w_pre_wr_data0;
+      2'b01 : w_pre_wr_data = w_pre_wr_data1;
+      2'b10 : w_pre_wr_data = w_pre_wr_data2;
+      2'b11 : w_pre_wr_data = w_pre_wr_data3;
+
+    endcase
+  end
+
+  //  Memory Read Controller
+
+  assign rd_data0_en = {rd_addr[10:9]  == 2'b00};
+  assign rd_data1_en = {rd_addr[10:9]  == 2'b01};
+  assign rd_data2_en = {rd_addr[10:9]  == 2'b10};
+  assign rd_data3_en = {rd_addr[10:9]  == 2'b11};
+
+  always @(rd_addr or rd_data0_o or rd_data1_o or rd_data2_o or rd_data3_o)
+  begin
+
+    case ({rd_addr[10:9]}) // synthesis parallel_case full_case
+
+      2'b00 : rd_data_raw_o = rd_data0_o;
+      2'b01 : rd_data_raw_o = rd_data1_o;
+      2'b10 : rd_data_raw_o = rd_data2_o;
+      2'b11 : rd_data_raw_o = rd_data3_o;
+
+    endcase
+
+  end
+
+  // Handle Read byte enables
+
+  assign rd_data = {{rd_be[0] ? rd_data_raw_o[07:00] : 8'h0},
+                      {rd_be[1] ? rd_data_raw_o[15:08] : 8'h0},
+                      {rd_be[2] ? rd_data_raw_o[23:16] : 8'h0},
+                      {rd_be[3] ? rd_data_raw_o[31:24] : 8'h0}};
+
+  EP_MEM EP_MEM_inst (
+
+     .clk_i(clk),
+
+     .a_rd_a_i_0(rd_addr[8:0]),                              // I [8:0]
+     .a_rd_en_i_0(rd_data0_en),                                // I [1:0]
+     .a_rd_d_o_0(rd_data0_o),                                  // O [31:0]
+
+     .b_wr_a_i_0(wr_addr[8:0]),                              // I [8:0]
+     .b_wr_d_i_0(post_wr_data),                                // I [31:0]
+     .b_wr_en_i_0({write_en & (wr_addr[10:9] == 2'b00)}),    // I
+     .b_rd_d_o_0(w_pre_wr_data0[31:0]),                        // O [31:0]
+     .b_rd_en_i_0({wr_addr[10:9] == 2'b00}),                 // I
+
+     .a_rd_a_i_1(rd_addr[8:0]),                              // I [8:0]
+     .a_rd_en_i_1(rd_data1_en),                                // I [1:0]
+     .a_rd_d_o_1(rd_data1_o),                                  // O [31:0]
+
+     .b_wr_a_i_1(wr_addr[8:0]),                              // [8:0]
+     .b_wr_d_i_1(post_wr_data),                                // [31:0]
+     .b_wr_en_i_1({write_en & (wr_addr[10:9] == 2'b01)}),    // I
+     .b_rd_d_o_1(w_pre_wr_data1[31:0]),                        // [31:0]
+     .b_rd_en_i_1({wr_addr[10:9] == 2'b01}),                 // I
+
+     .a_rd_a_i_2(rd_addr[8:0]),                              // I [8:0]
+     .a_rd_en_i_2(rd_data2_en),                                // I [1:0]
+     .a_rd_d_o_2(rd_data2_o),                                  // O [31:0]
+
+     .b_wr_a_i_2(wr_addr[8:0]),                              // I [8:0]
+     .b_wr_d_i_2(post_wr_data),                                // I [31:0]
+     .b_wr_en_i_2({write_en & (wr_addr[10:9] == 2'b10)}),    // I
+     .b_rd_d_o_2(w_pre_wr_data2[31:0]),                        // I [31:0]
+     .b_rd_en_i_2({wr_addr[10:9] == 2'b10}),                 // I
+
+     .a_rd_a_i_3(rd_addr[8:0]),                              // [8:0]
+     .a_rd_en_i_3(rd_data3_en),                                // [1:0]
+     .a_rd_d_o_3(rd_data3_o),                                  // O [31:0]
+
+     .b_wr_a_i_3(wr_addr[8:0]),                              // I [8:0]
+     .b_wr_d_i_3(post_wr_data),                                // I [31:0]
+     .b_wr_en_i_3({write_en & (wr_addr[10:9] == 2'b11)}),    // I
+     .b_rd_d_o_3(w_pre_wr_data3[31:0]),                        // I [31:0]
+     .b_rd_en_i_3({wr_addr[10:9] == 2'b11})                  // I
+
+  );
+
+  // synthesis translate_off
+  reg  [8*20:1] state_ascii;
+  always @(wr_mem_state)
+  begin
+    case (wr_mem_state)
+      PIO_MEM_ACCESS_WR_RST    : state_ascii <= #TCQ "PIO_MEM_WR_RST";
+      PIO_MEM_ACCESS_WR_WAIT   : state_ascii <= #TCQ "PIO_MEM_WR_WAIT";
+      PIO_MEM_ACCESS_WR_READ   : state_ascii <= #TCQ "PIO_MEM_WR_READ";
+      PIO_MEM_ACCESS_WR_WRITE  : state_ascii <= #TCQ "PIO_MEM_WR_WRITE";
+      default                  : state_ascii <= #TCQ "PIO MEM STATE ERR";
+    endcase
+  end
+  // synthesis translate_on
+
+
+endmodule
+

src/src/PCIeImports/PIO_TO_CTRL.v

@@ -0,0 +1,130 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : PIO_TO_CTRL.v
+// Version    : 3.3
+//--
+//-- Description: Turn-off Control Unit.
+//--
+//--------------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module PIO_TO_CTRL #(
+  parameter TCQ = 1
+) (
+  input               clk,
+  input               rst_n,
+
+  input               req_compl,
+  input               compl_done,
+
+  input               cfg_to_turnoff,
+  output  reg         cfg_turnoff_ok
+  );
+
+  reg                 trn_pending;
+
+
+
+  //  Check if completion is pending
+
+
+  always @ ( posedge clk ) begin
+
+    if (!rst_n )
+    begin
+
+      trn_pending <= #TCQ 0;
+
+    end
+    else
+    begin
+
+      if (!trn_pending && req_compl)
+
+        trn_pending <= #TCQ 1'b1;
+
+      else if (compl_done)
+
+        trn_pending <= #TCQ 1'b0;
+
+    end
+
+  end
+
+
+  //  Turn-off OK if requested and no transaction is pending
+
+
+  always @ ( posedge clk ) begin
+
+    if (!rst_n )
+    begin
+
+      cfg_turnoff_ok <= #TCQ 1'b0;
+
+    end
+    else
+    begin
+
+      if ( cfg_to_turnoff  && !trn_pending)
+        cfg_turnoff_ok <= #TCQ 1'b1;
+      else
+        cfg_turnoff_ok <= #TCQ 1'b0;
+
+    end
+
+  end
+
+
+endmodule // PIO_TO_CTRL
+

src/src/PCIeImports/PIO_TX_ENGINE.v

@@ -0,0 +1,412 @@
+
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : PIO_TX_ENGINE.v
+// Version    : 3.3
+
+`timescale 1ps/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module PIO_TX_ENGINE    #(
+  // RX/TX interface data width
+  parameter C_DATA_WIDTH = 64,
+  parameter TCQ = 1,
+
+  // TSTRB width
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8
+)(
+
+  input             clk,
+  input             rst_n,
+
+  // AXIS
+  input                           s_axis_tx_tready,
+  output  reg [C_DATA_WIDTH-1:0]  s_axis_tx_tdata,
+  output  reg [KEEP_WIDTH-1:0]    s_axis_tx_tkeep,
+  output  reg                     s_axis_tx_tlast,
+  output  reg                     s_axis_tx_tvalid,
+  output                          tx_src_dsc,
+
+  input                           req_compl,
+  input                           req_compl_wd,
+  output reg                      compl_done,
+
+  input [2:0]                     req_tc,
+  input                           req_td,
+  input                           req_ep,
+  input [1:0]                     req_attr,
+  input [9:0]                     req_len,
+  input [15:0]                    req_rid,
+  input [7:0]                     req_tag,
+  input [7:0]                     req_be,
+  input [12:0]                    req_addr,
+
+  output [10:0]                   rd_addr,
+  output reg [3:0]                rd_be,
+  input  [31:0]                   rd_data,
+  input [15:0]                    completer_id
+
+);
+
+localparam PIO_CPLD_FMT_TYPE      = 7'b10_01010;
+localparam PIO_CPL_FMT_TYPE       = 7'b00_01010;
+localparam PIO_TX_RST_STATE       = 2'b00;
+localparam PIO_TX_CPLD_QW1_FIRST  = 2'b01;
+localparam PIO_TX_CPLD_QW1_TEMP   = 2'b10;
+localparam PIO_TX_CPLD_QW1        = 2'b11;
+
+  // Local registers
+
+  reg [11:0]              byte_count;
+  reg [6:0]               lower_addr;
+
+  reg                     req_compl_q;
+  reg                     req_compl_wd_q;
+
+  reg                     compl_busy_i;
+ 
+  // Local wires
+
+  wire                    compl_wd;
+
+  // Unused discontinue
+  assign tx_src_dsc = 1'b0;
+
+  // Present address and byte enable to memory module
+
+  assign rd_addr = req_addr[12:2];
+ 
+  always @(posedge clk) begin
+    if (!rst_n)
+    begin
+     rd_be <= #TCQ 0;
+    end else begin
+     rd_be <= #TCQ req_be[3:0];
+    end
+  end
+
+  // Calculate byte count based on byte enable
+
+  always @ (rd_be) begin
+    casex (rd_be[3:0])
+      4'b1xx1 : byte_count = 12'h004;
+      4'b01x1 : byte_count = 12'h003;
+      4'b1x10 : byte_count = 12'h003;
+      4'b0011 : byte_count = 12'h002;
+      4'b0110 : byte_count = 12'h002;
+      4'b1100 : byte_count = 12'h002;
+      4'b0001 : byte_count = 12'h001;
+      4'b0010 : byte_count = 12'h001;
+      4'b0100 : byte_count = 12'h001;
+      4'b1000 : byte_count = 12'h001;
+      4'b0000 : byte_count = 12'h001;
+    endcase
+  end
+
+  always @ ( posedge clk ) begin
+    if (!rst_n ) 
+    begin
+      req_compl_q      <= #TCQ 1'b0;
+      req_compl_wd_q   <= #TCQ 1'b1;
+    end // if !rst_n
+    else
+    begin
+      req_compl_q      <= #TCQ req_compl;
+      req_compl_wd_q   <= #TCQ req_compl_wd;
+    end // if rst_n
+  end
+
+    always @ (rd_be or req_addr or compl_wd) begin
+    casex ({compl_wd, rd_be[3:0]})
+       5'b1_0000 : lower_addr = {req_addr[6:2], 2'b00};
+       5'b1_xxx1 : lower_addr = {req_addr[6:2], 2'b00};
+       5'b1_xx10 : lower_addr = {req_addr[6:2], 2'b01};
+       5'b1_x100 : lower_addr = {req_addr[6:2], 2'b10};
+       5'b1_1000 : lower_addr = {req_addr[6:2], 2'b11};
+       5'b0_xxxx : lower_addr = 8'h0;
+    endcase // casex ({compl_wd, rd_be[3:0]})
+    end
+
+  //  Generate Completion with 1 DW Payload
+    
+  generate
+    if (C_DATA_WIDTH == 64) begin : gen_cpl_64
+      reg         [1:0]            state;
+
+      assign compl_wd = req_compl_wd_q;
+
+      always @ ( posedge clk ) begin
+
+        if (!rst_n ) 
+        begin
+          s_axis_tx_tlast   <= #TCQ 1'b0;
+          s_axis_tx_tvalid  <= #TCQ 1'b0;
+          s_axis_tx_tdata   <= #TCQ {C_DATA_WIDTH{1'b0}};
+          s_axis_tx_tkeep   <= #TCQ {KEEP_WIDTH{1'b0}};
+         
+          compl_done        <= #TCQ 1'b0;
+          compl_busy_i      <= #TCQ 1'b0;
+          state             <= #TCQ PIO_TX_RST_STATE;
+        end // if (!rst_n ) 
+        else
+        begin
+          compl_done        <= #TCQ 1'b0;
+          // -- Generate compl_busy signal...
+          if (req_compl_q ) 
+            compl_busy_i <= 1'b1;
+          case ( state )
+            PIO_TX_RST_STATE : begin
+
+              if (compl_busy_i) 
+              begin
+                
+                s_axis_tx_tdata   <= #TCQ {C_DATA_WIDTH{1'b0}};
+                s_axis_tx_tkeep   <= #TCQ 8'hFF;
+                s_axis_tx_tlast   <= #TCQ 1'b0;
+                s_axis_tx_tvalid  <= #TCQ 1'b0;
+                  if (s_axis_tx_tready)
+                    state             <= #TCQ PIO_TX_CPLD_QW1_FIRST;
+                  else
+                  state             <= #TCQ PIO_TX_RST_STATE;
+               end
+              else
+              begin
+
+                s_axis_tx_tlast   <= #TCQ 1'b0;
+                s_axis_tx_tvalid  <= #TCQ 1'b0;
+                s_axis_tx_tdata   <= #TCQ 64'b0;
+                s_axis_tx_tkeep   <= #TCQ 8'hFF;
+                compl_done        <= #TCQ 1'b0;
+                state             <= #TCQ PIO_TX_RST_STATE;
+
+              end // if !(compl_busy) 
+              end // PIO_TX_RST_STATE
+
+            PIO_TX_CPLD_QW1_FIRST : begin
+              if (s_axis_tx_tready) begin
+
+                s_axis_tx_tlast  <= #TCQ 1'b0;
+                s_axis_tx_tdata  <= #TCQ {                      // Bits
+                                      completer_id,             // 16
+                                      {3'b0},                   // 3
+                                      {1'b0},                   // 1
+                                      byte_count,               // 12
+                                      {1'b0},                   // 1
+                                      (req_compl_wd_q ?
+                                      PIO_CPLD_FMT_TYPE :
+                                      PIO_CPL_FMT_TYPE),        // 7
+                                      {1'b0},                   // 1
+                                      req_tc,                   // 3
+                                      {4'b0},                   // 4
+                                      req_td,                   // 1
+                                      req_ep,                   // 1
+                                      req_attr,                 // 2
+                                      {2'b0},                   // 2
+                                      req_len                   // 10
+                                      };
+                s_axis_tx_tkeep   <= #TCQ 8'hFF;
+
+                state             <= #TCQ PIO_TX_CPLD_QW1_TEMP;
+                end
+            else
+                state             <= #TCQ PIO_TX_RST_STATE;
+
+               end //PIO_TX_CPLD_QW1_FIRST
+
+
+            PIO_TX_CPLD_QW1_TEMP : begin   
+                s_axis_tx_tvalid <= #TCQ 1'b1;
+                state             <= #TCQ PIO_TX_CPLD_QW1;
+            end
+
+
+            PIO_TX_CPLD_QW1 : begin
+
+              if (s_axis_tx_tready)
+              begin
+
+                s_axis_tx_tlast  <= #TCQ 1'b1;
+                s_axis_tx_tvalid <= #TCQ 1'b1;
+                // Swap DWORDS for AXI
+                s_axis_tx_tdata  <= #TCQ {        // Bits
+                                      rd_data,    // 32
+                                      req_rid,    // 16
+                                      req_tag,    //  8
+                                      {1'b0},     //  1
+                                      lower_addr  //  7
+                                      };
+
+                // Here we select if the packet has data or
+                // not.  The strobe signal will mask data
+                // when it is not needed.  No reason to change
+                // the data bus.
+                if (req_compl_wd_q)
+                  s_axis_tx_tkeep <= #TCQ 8'hFF;
+                else
+                  s_axis_tx_tkeep <= #TCQ 8'h0F;
+
+
+                compl_done        <= #TCQ 1'b1;
+                compl_busy_i      <= #TCQ 1'b0;
+                state             <= #TCQ PIO_TX_RST_STATE;
+
+              end // if (s_axis_tx_tready)
+              else
+                state             <= #TCQ PIO_TX_CPLD_QW1;
+
+            end // PIO_TX_CPLD_QW1
+
+            default : begin
+              // case default stmt
+              state             <= #TCQ PIO_TX_RST_STATE;
+            end
+
+          endcase
+        end // if rst_n
+      end
+    end
+    else if (C_DATA_WIDTH == 128) begin : gen_cpl_128
+      reg                     hold_state;
+      reg                     req_compl_q2;
+      reg                     req_compl_wd_q2;
+
+      assign compl_wd = req_compl_wd_q2;
+
+      always @ ( posedge clk ) begin
+        if (!rst_n ) 
+        begin
+          req_compl_q2      <= #TCQ 1'b0;
+          req_compl_wd_q2   <= #TCQ 1'b0;
+        end // if (!rst_n ) 
+        else
+        begin
+          req_compl_q2      <= #TCQ req_compl_q;
+          req_compl_wd_q2   <= #TCQ req_compl_wd_q;
+        end // if (rst_n ) 
+      end
+
+      always @ ( posedge clk ) begin
+        if (!rst_n ) 
+        begin
+          s_axis_tx_tlast   <= #TCQ 1'b0;
+          s_axis_tx_tvalid  <= #TCQ 1'b0;
+          s_axis_tx_tdata   <= #TCQ {C_DATA_WIDTH{1'b0}};
+          s_axis_tx_tkeep   <= #TCQ {KEEP_WIDTH{1'b0}};
+          compl_done        <= #TCQ 1'b0;
+          hold_state        <= #TCQ 1'b0;
+        end // if !rst_n
+        else
+        begin
+  
+          if (req_compl_q2 | hold_state)
+          begin
+            if (s_axis_tx_tready) 
+            begin
+  
+              s_axis_tx_tlast   <= #TCQ 1'b1;
+              s_axis_tx_tvalid  <= #TCQ 1'b1;
+              s_axis_tx_tdata   <= #TCQ {                   // Bits
+                                  rd_data,                  // 32
+                                  req_rid,                  // 16
+                                  req_tag,                  //  8
+                                  {1'b0},                   //  1
+                                  lower_addr,               //  7
+                                  completer_id,             // 16
+                                  {3'b0},                   //  3
+                                  {1'b0},                   //  1
+                                  byte_count,               // 12
+                                  {1'b0},                   //  1
+                                  (req_compl_wd_q2 ?
+                                  PIO_CPLD_FMT_TYPE :
+                                  PIO_CPL_FMT_TYPE),        //  7
+                                  {1'b0},                   //  1
+                                  req_tc,                   //  3
+                                  {4'b0},                   //  4
+                                  req_td,                   //  1
+                                  req_ep,                   //  1
+                                  req_attr,                 //  2
+                                  {2'b0},                   //  2
+                                  req_len                   // 10
+                                  };
+  
+              // Here we select if the packet has data or
+              // not.  The strobe signal will mask data
+              // when it is not needed.  No reason to change
+              // the data bus.
+              if (req_compl_wd_q2)
+                s_axis_tx_tkeep   <= #TCQ 16'hFFFF;
+              else
+                s_axis_tx_tkeep   <= #TCQ 16'h0FFF;
+  
+              compl_done        <= #TCQ 1'b1;
+              hold_state        <= #TCQ 1'b0;
+  
+            end // if (s_axis_tx_tready) 
+            else
+              hold_state        <= #TCQ 1'b1;
+  
+          end // if (req_compl_q2 | hold_state)
+          else
+          begin
+  
+            s_axis_tx_tlast   <= #TCQ 1'b0;
+            s_axis_tx_tvalid  <= #TCQ 1'b0;
+            s_axis_tx_tdata   <= #TCQ {C_DATA_WIDTH{1'b0}};
+            s_axis_tx_tkeep   <= #TCQ {KEEP_WIDTH{1'b1}};
+            compl_done        <= #TCQ 1'b0;
+  
+          end // if !(req_compl_q2 | hold_state) 
+        end // if rst_n
+      end
+    end
+  endgenerate
+
+endmodule // PIO_TX_ENGINE

src/src/PCIeImports/board.v

@@ -0,0 +1,246 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : board.v
+// Version    : 3.3
+// Description:  Top level testbench
+//
+//------------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+
+`include "board_common.vh"
+
+`define SIMULATION
+
+module board;
+
+parameter          REF_CLK_FREQ       = 0;      // 0 - 100 MHz, 1 - 125 MHz,  2 - 250 MHz
+
+localparam         REF_CLK_HALF_CYCLE = (REF_CLK_FREQ == 0) ? 5000 :
+                                        (REF_CLK_FREQ == 1) ? 4000 :
+                                        (REF_CLK_FREQ == 2) ? 2000 : 0;
+integer            i;
+
+// System-level clock and reset
+reg                sys_rst_n;
+
+wire               ep_sys_clk_p;
+wire               ep_sys_clk_n;
+wire               ep_sys_clk;
+wire               rp_sys_clk;
+
+`ifdef ENABLE_GT
+parameter PIPE_SIM = "FALSE";
+defparam board.EP.pcie1234_support_i.pcie1234_i.inst.inst.PIPE_SIM_MODE = "FALSE";
+defparam board.RP.rport.PIPE_SIM_MODE = "FALSE";
+`else
+parameter PIPE_SIM = "TRUE";
+defparam board.EP.pcie1234_support.pcie1234_i.inst.inst.PIPE_SIM_MODE = "TRUE";
+defparam board.RP.rport.PIPE_SIM_MODE = "TRUE";
+`endif
+
+localparam EXT_PIPE_SIM = "FALSE";
+
+
+//
+// PCI-Express Serial Interconnect
+//
+
+wire  [0:0]  ep_pci_exp_txn;
+wire  [0:0]  ep_pci_exp_txp;
+wire  [0:0]  rp_pci_exp_txn;
+wire  [0:0]  rp_pci_exp_txp;
+//
+// PCI-Express Endpoint Instance
+//
+
+xilinx_pcie_2_1_ep_7x 
+  
+
+EP (
+
+
+  // SYS Inteface
+  .sys_clk_n(ep_sys_clk_n),
+  .sys_clk_p(ep_sys_clk_p),
+  .sys_rst_n(sys_rst_n),
+
+
+
+  // PCI-Express Interface
+  .pci_exp_txn(ep_pci_exp_txn),
+  .pci_exp_txp(ep_pci_exp_txp),
+  .pci_exp_rxn(rp_pci_exp_txn),
+  .pci_exp_rxp(rp_pci_exp_txp)
+);
+
+//
+// PCI-Express Model Root Port Instance
+//
+
+xilinx_pcie_2_1_rport_7x # (
+
+  .REF_CLK_FREQ(0),
+  .PL_FAST_TRAIN("TRUE"),
+  .ALLOW_X8_GEN2("FALSE"),
+  .C_DATA_WIDTH(64),
+  .LINK_CAP_MAX_LINK_WIDTH(6'h1),
+  .DEVICE_ID(16'h7100),
+  .LINK_CAP_MAX_LINK_SPEED(4'h1),
+  .LINK_CTRL2_TARGET_LINK_SPEED(4'h1),
+  .DEV_CAP_MAX_PAYLOAD_SUPPORTED(2),
+  .TRN_DW("FALSE"),
+  .VC0_TX_LASTPACKET(29),
+  .VC0_RX_RAM_LIMIT(13'h7FF),
+  .VC0_CPL_INFINITE("TRUE"),
+  .VC0_TOTAL_CREDITS_PD(437),
+  .VC0_TOTAL_CREDITS_CD(461),
+  .USER_CLK_FREQ(2),
+  .USER_CLK2_DIV2("FALSE")
+)
+RP (
+
+  // SYS Inteface
+  .sys_clk(rp_sys_clk),
+  .sys_rst_n(sys_rst_n),
+
+  // PCI-Express Interface
+  .pci_exp_txn(rp_pci_exp_txn),
+  .pci_exp_txp(rp_pci_exp_txp),
+  .pci_exp_rxn(ep_pci_exp_txn),
+  .pci_exp_rxp(ep_pci_exp_txp)
+);
+
+
+sys_clk_gen  # (
+
+  .halfcycle(REF_CLK_HALF_CYCLE),
+  .offset(0)
+
+)
+CLK_GEN_RP (
+
+  .sys_clk(rp_sys_clk)
+
+);
+
+
+sys_clk_gen_ds # (
+
+  .halfcycle(REF_CLK_HALF_CYCLE),
+  .offset(0)
+
+)
+CLK_GEN_EP (
+
+  .sys_clk_p(ep_sys_clk_p),
+  .sys_clk_n(ep_sys_clk_n)
+
+);
+
+
+
+`include "pipe_interconnect.vh"
+
+
+initial begin
+  $display("[%t] : System Reset Asserted...", $realtime);
+
+  sys_rst_n = 1'b0;
+
+  for (i = 0; i < 500; i = i + 1) begin
+
+    @(posedge ep_sys_clk_p);
+
+  end
+
+  $display("[%t] : System Reset De-asserted...", $realtime);
+
+  sys_rst_n = 1'b1;
+
+end
+
+
+
+initial begin
+
+  if ($test$plusargs ("dump_all")) begin
+
+`ifdef NCV // Cadence TRN dump
+
+    $recordsetup("design=board",
+                 "compress",
+                 "wrapsize=100M",
+                 "version=1",
+                 "run=1");
+    $recordvars();
+
+`elsif VCS //Synopsys VPD dump
+
+    $vcdplusfile("board.vpd");
+    $vcdpluson;
+    $vcdplusglitchon;
+    $vcdplusflush;
+
+`else
+
+    // Verilog VC dump
+    $dumpfile("board.vcd");
+    $dumpvars(0, board);
+
+`endif
+
+  end
+
+end
+
+
+endmodule // BOARD

src/src/PCIeImports/board_common.vh

@@ -0,0 +1,86 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : board_common.vh
+// Version    : 3.3
+//--
+//--------------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+
+`define IO_TRUE                      1
+`define IO_FALSE                     0
+
+`define TX_TASKS                     board.RP.tx_usrapp
+
+// Endpoint Sys clock clock frequency 100 MHz -> half clock -> 5000 pS
+`define SYS_CLK_COR_HALF_CLK_PERIOD         5000
+
+// Downstrean Port Sys clock clock frequency 250 MHz -> half clock -> 2000 pS
+`define SYS_CLK_DSPORT_HALF_CLK_PERIOD      2000
+
+`define RX_LOG                       0
+`define TX_LOG                       1
+
+// PCI Express TLP Types constants
+`define  PCI_EXP_MEM_READ32          7'b0000000
+`define  PCI_EXP_IO_READ             7'b0000010
+`define  PCI_EXP_CFG_READ0           7'b0000100
+`define  PCI_EXP_COMPLETION_WO_DATA  7'b0001010
+`define  PCI_EXP_MEM_READ64          7'b0100000
+`define  PCI_EXP_MSG_NODATA          7'b0110xxx
+`define  PCI_EXP_MEM_WRITE32         7'b1000000
+`define  PCI_EXP_IO_WRITE            7'b1000010
+`define  PCI_EXP_CFG_WRITE0          7'b1000100
+`define  PCI_EXP_COMPLETION_DATA     7'b1001010
+`define  PCI_EXP_MEM_WRITE64         7'b1100000
+`define  PCI_EXP_MSG_DATA            7'b1110xxx
+
+`define  TRN_RX_TIMEOUT              5000

src/src/PCIeImports/hierarchy.txt

@@ -0,0 +1,74 @@
+ xilinx_pcie_2_1_ep_7x
+ |
+ |--pcie1234_support
+ |  |--pcie1234_pipe_clock                                      
+ |  |--pcie1234 (Core Top level module Generated by Vivado in synth directory)
+ |     |--pcie_7x_v3_3_14_top (Static Top level file) 
+ |        |--pcie_7x_v3_3_14_core_top
+ |           |
+ |           |--pcie1234_pcie_top
+ |           |  |
+ |           |  |--pcie1234_axi_basic_top
+ |           |  |  |
+ |           |  |  |--pcie1234_axi_basic_rx
+ |           |  |  |  |
+ |           |  |  |  |--pcie1234_axi_basic_rx_pipeline
+ |           |  |  |  |--pcie1234_axi_basic_rx_null_gen
+ |           |  |  |
+ |           |  |  |--pcie1234_axi_basic_tx
+ |           |  |     |
+ |           |  |     |--pcie1234_axi_basic_tx_pipeline
+ |           |  |     |--pcie1234_axi_basic_tx_thrtl_ctl
+ |           |  |
+ |           |  |--pcie1234_pcie_7x
+ |           |  |  |
+ |           |  |  |--pcie1234_pcie_bram_top_7x
+ |           |  |  |  |
+ |           |  |  |  |--pcie1234_pcie_brams_7x (an instance each for Rx & Tx)
+ |           |  |  |     |
+ |           |  |  |     |--pcie1234_pcie_bram_7x
+ |           |  |  |
+ |           |  |  |--PCIE_2_1 (Integrated Block Instance)
+ |           |  |
+ |           |  |--pcie1234_pcie_pipe_pipeline
+ |           |     |
+ |           |     |--pcie1234_pcie_pipe_misc
+ |           |     |--pcie1234_pcie_pipe_lane (per lane)
+ |           |
+ |           |--pcie1234_gt_top
+ |              |
+ |              |--pcie1234_gt_rx_valid_filter
+ |              |
+ |              |--pcie1234_pipe_wrapper
+ |              |  |
+ |              |  |--pcie1234_pipe_reset
+ |              |  |--pcie1234_qpll_reset
+ |              |  |--pcie1234_pipe_user
+ |              |  |--pcie1234_pipe_rate
+ |              |  |--pcie1234_pipe_sync
+ |              |  |--pcie1234_pipe_drp
+ |              |  |--pcie1234_pipe_eq
+ |              |  |  |--pcie1234_rxeq_scan
+ |              |  |  |
+ |              |  |--pcie1234_gt_common
+ |              |  |  |--pcie1234_qpll_drp
+ |              |  |  |--pcie1234_qpll_wrapper
+ |              |  |
+ |              |  |--pcie1234_gt_wrapper
+ |
+ |--pcie_app_7x (PIO design, in example_design directory)
+    |
+    |--PIO
+       |
+       |--PIO_EP
+       |  |
+       |  |--PIO_EP_MEM_ACCESS
+       |  |  |
+       |  |  |--EP_MEM
+       |  |     |
+       |  |     |--RAMB36
+       |  |
+       |  |--PIO_RX_ENGINE
+       |  |--PIO_TX_ENGINE
+       |
+       |--PIO_TO_CTRL

src/src/PCIeImports/pci_exp_usrapp_cfg.v

@@ -0,0 +1,276 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : pci_exp_usrapp_cfg.v
+// Version    : 3.3
+//--
+//--------------------------------------------------------------------------------
+
+`include "board_common.vh"
+
+module pci_exp_usrapp_cfg (
+
+                          cfg_do,
+                          cfg_di,
+                          cfg_byte_en_n,
+                          cfg_dwaddr,
+                          cfg_wr_en_n,
+                          cfg_rd_en_n,
+                          cfg_rd_wr_done_n,
+                    
+                          cfg_err_cor_n,
+                          cfg_err_ur_n,      
+                          cfg_err_ecrc_n,
+                          cfg_err_cpl_timeout_n,
+                          cfg_err_cpl_abort_n,
+                          cfg_err_cpl_unexpect_n,
+                          cfg_err_posted_n,
+                          cfg_err_tlp_cpl_header,
+                          cfg_interrupt_n,
+                          cfg_interrupt_rdy_n,
+                          cfg_turnoff_ok_n,
+                          cfg_to_turnoff_n,
+                          cfg_bus_number,
+                          cfg_device_number,
+                          cfg_function_number,
+                           cfg_status,
+                          cfg_command,
+                          cfg_dstatus,
+                          cfg_dcommand,
+                          cfg_lstatus,
+                          cfg_lcommand,
+
+                          cfg_pcie_link_state_n,
+                          cfg_trn_pending_n,
+                          cfg_pm_wake_n,
+                    
+                          trn_clk,
+                          trn_reset_n
+                    
+                          );
+
+
+
+input   [(32 - 1):0]     cfg_do;
+output  [(32 - 1):0]     cfg_di;
+output  [(32/8 - 1):0]   cfg_byte_en_n;
+output  [(10 - 1):0]     cfg_dwaddr;
+output                                        cfg_wr_en_n;
+output                                        cfg_rd_en_n;
+input                                         cfg_rd_wr_done_n;
+
+output                                        cfg_err_cor_n;
+output                                        cfg_err_ur_n;
+output                                        cfg_err_ecrc_n;
+output                                        cfg_err_cpl_timeout_n;
+output                                        cfg_err_cpl_abort_n;
+output                                        cfg_err_cpl_unexpect_n;
+output                                        cfg_err_posted_n;
+output  [(48 - 1):0]   cfg_err_tlp_cpl_header;
+output                                        cfg_interrupt_n;
+input                                         cfg_interrupt_rdy_n;
+output                                        cfg_turnoff_ok_n;
+input                                         cfg_to_turnoff_n;
+output                                        cfg_pm_wake_n;
+input    [(8 - 1):0]  cfg_bus_number;
+input    [(5 - 1):0]  cfg_device_number;
+input    [(3 - 1):0]  cfg_function_number;
+input   [(16 - 1):0]      cfg_status;
+input   [(16- 1):0]      cfg_command;
+input   [(16- 1):0]      cfg_dstatus;
+input   [(16 - 1):0]      cfg_dcommand;
+input   [(16 - 1):0]      cfg_lstatus;
+input   [(16 - 1):0]      cfg_lcommand;
+
+input  [(3 - 1):0]     cfg_pcie_link_state_n;
+output                                        cfg_trn_pending_n;
+
+input                                         trn_clk;
+input                                         trn_reset_n;
+
+parameter                                     Tcq = 1;
+
+reg  [(32 - 1):0]        cfg_di;
+reg  [(32/8 - 1):0]      cfg_byte_en_n;
+reg  [(10 - 1):0]        cfg_dwaddr;
+reg                                           cfg_wr_en_n;
+reg                                           cfg_rd_en_n;
+
+reg                                           cfg_err_cor_n;
+reg                                           cfg_err_ecrc_n;
+reg                                           cfg_err_ur_n;
+reg                                           cfg_err_cpl_timeout_n;
+reg                                           cfg_err_cpl_abort_n;
+reg                                           cfg_err_cpl_unexpect_n;
+reg                                           cfg_err_posted_n;  
+reg  [(48 - 1):0]      cfg_err_tlp_cpl_header;
+reg                                           cfg_interrupt_n;
+reg                                           cfg_turnoff_ok_n;
+reg                                           cfg_pm_wake_n;
+reg                                           cfg_trn_pending_n;
+
+initial begin
+
+  cfg_err_cor_n <= 1'b1;
+  cfg_err_ur_n <= 1'b1;
+  cfg_err_ecrc_n <= 1'b1;
+  cfg_err_cpl_timeout_n <= 1'b1;
+  cfg_err_cpl_abort_n <= 1'b1;
+  cfg_err_cpl_unexpect_n <= 1'b1;
+  cfg_err_posted_n <= 1'b0;
+  cfg_interrupt_n <= 1'b1;
+  cfg_turnoff_ok_n <= 1'b1;
+
+  cfg_dwaddr <= 0;
+  cfg_err_tlp_cpl_header <= 0;
+
+  cfg_di <= 0;
+  cfg_byte_en_n <= 4'hf;
+  cfg_wr_en_n <= 1;
+  cfg_rd_en_n <= 1;
+
+  cfg_pm_wake_n <= 1;
+  cfg_trn_pending_n <= 1'b0;
+
+end
+
+/************************************************************
+Task : TSK_READ_CFG_DW                
+Description : Read Configuration Space DW
+*************************************************************/
+
+task TSK_READ_CFG_DW;
+
+input   [31:0]   addr_;
+
+begin           
+
+  if (!trn_reset_n) begin
+  
+    $display("[%t] : trn_reset_n is asserted", $realtime);
+    $finish(1); 
+  
+  end
+
+  wait ( cfg_rd_wr_done_n == 1'b1)
+
+  @(posedge trn_clk);
+  cfg_dwaddr <= #(Tcq) addr_;
+  cfg_wr_en_n <= #(Tcq) 1'b1;
+  cfg_rd_en_n <= #(Tcq) 1'b0;
+
+  $display("[%t] : Reading Cfg Addr [0x%h]", $realtime, addr_);
+  $fdisplay(board.RP.com_usrapp.tx_file_ptr,
+            "\n[%t] : Local Configuration Read Access :", 
+            $realtime);
+                 
+  @(posedge trn_clk); 
+  #(Tcq);
+  wait ( cfg_rd_wr_done_n == 1'b0)
+  #(Tcq);
+
+  $fdisplay(board.RP.com_usrapp.tx_file_ptr,
+            "\t\t\tCfg Addr [0x%h] -> Data [0x%h]\n", 
+            {addr_,2'b00}, cfg_do);
+  cfg_rd_en_n <= #(Tcq) 1'b1;
+         
+end
+
+endtask // TSK_READ_CFG_DW;
+
+
+/************************************************************
+Task : TSK_WRITE_CFG_DW
+Description : Write Configuration Space DW
+*************************************************************/
+
+task TSK_WRITE_CFG_DW;
+
+input   [31:0]   addr_;
+input   [31:0]   data_;
+input   [3:0]    ben_;
+
+begin
+
+  if (!trn_reset_n) begin
+
+    $display("[%t] : trn_reset_n is asserted", $realtime);
+    $finish(1);
+
+  end
+
+  wait ( cfg_rd_wr_done_n == 1'b1)
+
+  @(posedge trn_clk);
+  cfg_dwaddr <= #(Tcq) addr_;
+  cfg_di      <= #(Tcq) data_;
+  cfg_byte_en_n <= #(Tcq) ben_;
+  cfg_wr_en_n <= #(Tcq) 1'b0;
+  cfg_rd_en_n <= #(Tcq) 1'b1;
+
+  $display("[%t] : Writing Cfg Addr [0x%h]", $realtime, addr_);
+  $fdisplay(board.RP.com_usrapp.tx_file_ptr,
+            "\n[%t] : Local Configuration Write Access :",
+            $realtime);
+
+  @(posedge trn_clk);
+  #(Tcq);
+  wait ( cfg_rd_wr_done_n == 1'b0)
+  #(Tcq);
+
+  cfg_wr_en_n <= #(Tcq) 1'b1;
+
+end
+
+endtask // TSK_WRITE_CFG_DW;
+
+
+endmodule // pci_exp_usrapp_cfg
+

src/src/PCIeImports/pci_exp_usrapp_com.v

@@ -0,0 +1,643 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : pci_exp_usrapp_com.v
+// Version    : 3.3
+//--
+//--------------------------------------------------------------------------------
+
+`include "board_common.vh"
+
+module pci_exp_usrapp_com ();
+
+
+/* Local variables */
+
+reg   [31:0]           rx_file_ptr;
+reg   [7:0]            frame_store_rx[5119:0];
+integer                frame_store_rx_idx;
+reg   [31:0]           tx_file_ptr;
+reg   [7:0]            frame_store_tx[5119:0];
+integer                frame_store_tx_idx;
+
+reg   [31:0]           log_file_ptr;
+integer                _frame_store_idx;
+
+event                  rcvd_cpld, rcvd_memrd, rcvd_memwr;
+event                  rcvd_cpl, rcvd_memrd64, rcvd_memwr64;
+event                  rcvd_msg, rcvd_msgd, rcvd_cfgrd0;
+event                  rcvd_cfgwr0, rcvd_cfgrd1, rcvd_cfgwr1;
+event                  rcvd_iord, rcvd_iowr;
+
+initial begin
+
+  frame_store_rx_idx = 0;
+  frame_store_tx_idx = 0;
+
+  rx_file_ptr = $fopen("rx.dat");
+
+  if (!rx_file_ptr) begin
+
+    $write("ERROR: Could not open rx.dat.\n");
+    $finish;
+
+  end
+
+  tx_file_ptr = $fopen("tx.dat");
+
+  if (!tx_file_ptr) begin
+
+    $write("ERROR: Could not open tx.dat.\n");
+    $finish;
+  end
+end
+
+  /************************************************************
+  Task : TSK_PARSE_FRAME
+  Inputs : None
+  Outputs : None
+  Description : Parse frame data
+  *************************************************************/
+
+  task TSK_PARSE_FRAME;
+  input    log_file;
+
+  reg   [1:0]   fmt;
+  reg   [4:0]   f_type;
+  reg   [2:0]   traffic_class;
+  reg     td;
+  reg      ep;
+  reg  [1:0]   attr;
+  reg  [9:0]   length;
+  reg     payload;
+  reg  [15:0]   requester_id;
+  reg  [15:0]   completer_id;
+  reg  [7:0]   tag;
+  reg  [7:0]   byte_enables;
+  reg  [7:0]  message_code;
+  reg  [31:0]   address_low;
+  reg  [31:0]   address_high;
+  reg  [9:0]   register_address;
+  reg   [2:0]   completion_status;
+  reg  [31:0]  _log_file_ptr;
+  integer    _frame_store_idx;
+
+  begin
+
+  if (log_file == `RX_LOG)
+    _log_file_ptr = rx_file_ptr;
+  else
+    _log_file_ptr = tx_file_ptr;
+
+  if (log_file == `RX_LOG) begin
+
+    _frame_store_idx = frame_store_rx_idx;
+    frame_store_rx_idx = 0;
+
+  end else begin
+
+    _frame_store_idx = frame_store_tx_idx;
+    frame_store_tx_idx = 0;
+
+  end
+
+  if (log_file == `RX_LOG) begin
+
+    $display("[%t] : TSK_PARSE_FRAME on Receive", $realtime);
+
+    end
+  else begin
+
+    $display("[%t] : TSK_PARSE_FRAME on Transmit", $realtime);
+
+    end          
+
+  TSK_DECIPHER_FRAME (fmt, f_type, traffic_class, td, ep, attr, length, log_file);  
+
+  // decode the packets received based on fmt and f_type
+
+  casex({fmt, f_type})
+
+    `PCI_EXP_MEM_READ32 : begin
+
+      $fdisplay(_log_file_ptr, "[%t] : Memory Read-32 Frame \n", $time);
+      payload = 0;
+      TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
+      
+      if (log_file == `RX_LOG)
+        -> rcvd_memrd;
+    end
+
+    `PCI_EXP_IO_READ : begin
+
+      $fdisplay(_log_file_ptr, "[%t] : IO Read Frame \n", $time);
+      payload = 0;
+      TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
+
+      if (log_file == `RX_LOG)
+        -> rcvd_iord;
+    end
+
+    `PCI_EXP_CFG_READ0 : begin
+
+      $fdisplay(_log_file_ptr, "[%t] : Config Read Type 0 Frame \n", $time);
+      payload = 0;
+      TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
+
+      if (log_file == `RX_LOG) 
+        -> rcvd_cfgrd0;
+    end
+
+    `PCI_EXP_COMPLETION_WO_DATA: begin
+
+      $fdisplay(_log_file_ptr, "[%t] : Completion Without Data Frame \n", $time);
+      payload = 0;
+      TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
+
+      if (log_file == `RX_LOG) 
+        -> rcvd_cpl;
+    end
+
+    `PCI_EXP_MEM_READ64: begin
+
+      $fdisplay(_log_file_ptr, "[%t] : Memory Read-64 Frame \n", $time);
+      payload = 0;
+      TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload,  _frame_store_idx, _log_file_ptr, log_file);
+
+      if (log_file == `RX_LOG) 
+        -> rcvd_memrd64;
+    end
+
+    `PCI_EXP_MSG_NODATA: begin
+
+      $fdisplay(_log_file_ptr, "[%t] : Message With No Data Frame \n", $time);
+      payload = 0;
+      TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload,  _frame_store_idx, _log_file_ptr, log_file);
+
+      if (log_file == `RX_LOG) 
+        -> rcvd_msg;
+    end
+
+    `PCI_EXP_MEM_WRITE32: begin
+
+      $fdisplay(_log_file_ptr, "[%t] : Memory Write-32 Frame \n", $time);
+      payload = 1;
+      TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
+      $fdisplay(_log_file_ptr, "\n");
+
+      if (log_file == `RX_LOG) 
+        -> rcvd_memwr;
+    end
+
+    `PCI_EXP_IO_WRITE: begin
+
+      $fdisplay(_log_file_ptr, "[%t] : IO Write Frame \n", $time);
+      payload = 1;
+      TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
+      $fdisplay(_log_file_ptr, "\n");
+
+      if (log_file == `RX_LOG) 
+        -> rcvd_iowr;
+    end
+
+    `PCI_EXP_CFG_WRITE0: begin
+
+      $fdisplay(_log_file_ptr, "[%t] : Config Write Type 0 Frame \n", $time);
+      payload = 1;
+      TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
+      $fdisplay(_log_file_ptr, "\n");
+
+      if (log_file == `RX_LOG) 
+        -> rcvd_cfgwr0;
+    end
+
+    `PCI_EXP_COMPLETION_DATA: begin
+
+      $fdisplay(_log_file_ptr, "[%t] : Completion With Data Frame \n", $time);
+      payload = 1;
+      TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
+      $fdisplay(_log_file_ptr, "\n");
+
+      if (log_file == `RX_LOG) 
+        -> rcvd_cpld;
+    end
+
+    `PCI_EXP_MEM_WRITE64: begin
+
+      $fdisplay(_log_file_ptr, "[%t] : Memory Write-64 Frame \n", $time);
+      payload = 1;
+      TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload,  _frame_store_idx, _log_file_ptr, log_file);
+      $fdisplay(_log_file_ptr, "\n");
+
+      if (log_file == `RX_LOG) 
+        -> rcvd_memwr64;
+    end
+
+    `PCI_EXP_MSG_DATA: begin
+
+      $fdisplay(_log_file_ptr, "[%t] : Message With Data Frame \n", $time);
+      payload = 1;
+      TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload,  _frame_store_idx, _log_file_ptr, log_file);
+      $fdisplay(_log_file_ptr, "\n");
+
+      if (log_file == `RX_LOG) 
+        -> rcvd_msgd;
+    end
+
+    default: begin
+      $fdisplay(_log_file_ptr, "[%t] : Not a valid frame \n", $time);
+      $display(_log_file_ptr, "[%t] : Received an invalid frame \n", $time);
+      $finish(2);
+    end
+
+  endcase
+  end
+  endtask // TSK_PARSE_FRAME
+
+  /************************************************************
+  Task : TSK_DECIPHER_FRAME
+  Inputs : None
+  Outputs : fmt, f_type, traffic_class, td, ep, attr, length
+  Description : Deciphers frame
+  *************************************************************/
+
+  task TSK_DECIPHER_FRAME;
+  output [1:0]   fmt;
+  output [4:0]   f_type;
+  output [2:0]   traffic_class;
+  output     td;
+  output     ep;
+  output [1:0]   attr;
+  output [9:0]   length;
+  input    txrx;
+
+  begin
+
+    fmt = (txrx ? frame_store_tx[0] : frame_store_rx[0]) >> 5;
+    f_type = txrx ? frame_store_tx[0] : frame_store_rx[0];
+    traffic_class = (txrx ? frame_store_tx[1] : frame_store_rx[1]) >> 4;
+    td = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 7;
+    ep = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 6;
+    attr = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 4;
+    length = (txrx ? frame_store_tx[2] : frame_store_rx[2]);
+    length = (length << 8) | (txrx ? frame_store_tx[3] : frame_store_rx[3]);
+
+  end
+
+  endtask // TSK_DECIPHER_FRAME
+
+
+  /************************************************************
+  Task : TSK_3DW
+  Inputs : fmt, f_type, traffic_class, td, ep, attr, length, 
+  payload, _frame_store_idx
+  Outputs : None
+  Description : Gets variables and prints frame 
+  *************************************************************/
+
+  task TSK_3DW;
+  input   [1:0]   fmt;
+  input   [4:0]   f_type;
+  input   [2:0]   traffic_class;
+  input     td;
+  input     ep;
+  input   [1:0]   attr;
+  input   [9:0]   length;
+  input      payload;
+  input  [31:0]  _frame_store_idx;
+  input  [31:0]  _log_file_ptr;
+  input     txrx;
+
+  reg [15:0] requester_id;
+  reg [7:0] tag;
+  reg [7:0] byte_enables;
+  reg [31:0] address_low;
+  reg [15:0] completer_id;
+  reg [9:0] register_address;
+  reg [2:0] completion_status;
+  reg [31:0] dword_data; // this will be used to recontruct bytes of data and sent to tx_app
+ 
+  integer    _i;
+
+  begin
+    $fdisplay(_log_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
+    $fdisplay(_log_file_ptr, "\t TD: %h", td);
+    $fdisplay(_log_file_ptr, "\t EP: %h", ep);
+    $fdisplay(_log_file_ptr, "\t Attributes: 0x%h", attr);
+    $fdisplay(_log_file_ptr, "\t Length: 0x%h", length);
+
+    casex({fmt, f_type})
+
+    `PCI_EXP_CFG_READ0, 
+    `PCI_EXP_CFG_WRITE0: begin
+
+      requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
+      tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
+      byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
+      completer_id = {txrx ? frame_store_tx[8] : frame_store_rx[8], txrx ? frame_store_tx[9] : frame_store_rx[9]};
+      register_address = txrx ? frame_store_tx[10] : frame_store_rx[10];
+      register_address = (register_address << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
+
+      $fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
+      $fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
+      $fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
+      $fdisplay(_log_file_ptr, "\t Completer Id: 0x%h", completer_id);
+      $fdisplay(_log_file_ptr, "\t Register Address: 0x%h \n", register_address);
+
+      if (payload == 1) begin
+
+        for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
+
+          $fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
+
+        end
+      end
+    end
+
+    `PCI_EXP_COMPLETION_WO_DATA,
+    `PCI_EXP_COMPLETION_DATA: begin
+
+      completer_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
+      completion_status = txrx ? (frame_store_tx[6] >> 5) : (frame_store_rx[6] >> 5);
+      requester_id = txrx ? {frame_store_tx[8], frame_store_tx[9]} : {frame_store_rx[8], frame_store_rx[9]};
+      tag = txrx ? frame_store_tx[10] : frame_store_rx[10];
+      $fdisplay(_log_file_ptr, "\t Completer Id: 0x%h", completer_id);
+      $fdisplay(_log_file_ptr, "\t Completion Status: 0x%h", completion_status);
+      $fdisplay(_log_file_ptr, "\t Requester Id: 0x%h ", requester_id);
+      $fdisplay(_log_file_ptr, "\t Tag: 0x%h \n", tag);
+
+      if (payload == 1) begin      
+                                
+         dword_data = 32'h0000_0000;
+				
+	 for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
+				    				    
+		$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
+		if (!txrx) begin // if we are called from rx
+				       
+			dword_data = dword_data >> 8; // build a dword to send to tx app
+			dword_data = dword_data | {frame_store_rx[_i], 24'h00_0000}; 
+		end  
+	end
+	`TX_TASKS.TSK_SET_READ_DATA(4'hf,dword_data); // send the data to the tx_app
+      end
+    
+    
+    end
+
+    // memory reads, io reads, memory writes and io writes
+    default: begin
+
+      requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
+      tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
+      byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
+      address_low = txrx ? frame_store_tx[8] : frame_store_rx[8];
+      address_low = (address_low << 8) | (txrx ? frame_store_tx[9] : frame_store_rx[9]);
+      address_low = (address_low << 8) | (txrx ? frame_store_tx[10] : frame_store_rx[10]);
+      address_low = (address_low << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
+      $fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
+      $fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
+      $fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
+      $fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
+      if (payload == 1) begin
+
+        for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
+  
+          $fdisplay(_log_file_ptr, "\t 0x%h", (txrx ? frame_store_tx[_i] : frame_store_rx[_i]));
+        end
+
+      end
+      
+    end
+  endcase 
+  end
+  endtask // TSK_3DW
+
+
+  /************************************************************
+  Task : TSK_4DW
+  Inputs : fmt, f_type, traffic_class, td, ep, attr, length
+  payload, _frame_store_idx
+  Outputs : None
+  Description : Gets variables and prints frame 
+  *************************************************************/
+  
+  task TSK_4DW;
+  input [1:0]   fmt;
+  input [4:0]   f_type;
+  input [2:0]   traffic_class;
+  input         td;
+  input     ep;
+  input [1:0]   attr;
+  input [9:0]   length;
+  input      payload;
+  input  [31:0]  _frame_store_idx;
+  input  [31:0]  _log_file_ptr;
+  input    txrx;
+  
+  reg [15:0]   requester_id;
+  reg [7:0]   tag;
+  reg [7:0]   byte_enables;
+  reg [7:0]   message_code;
+  reg [31:0]   address_high;
+  reg [31:0]   address_low;
+  reg [2:0]   msg_type;
+  
+  integer    _i;
+  
+  begin
+
+    $fdisplay(_log_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
+    $fdisplay(_log_file_ptr, "\t TD: %h", td);
+    $fdisplay(_log_file_ptr, "\t EP: %h", ep);
+    $fdisplay(_log_file_ptr, "\t Attributes: 0x%h", attr);
+    $fdisplay(_log_file_ptr, "\t Length: 0x%h", length);
+  
+    requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
+    tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
+    byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
+    message_code = txrx ? frame_store_tx[7] : frame_store_rx[7];
+    address_high = txrx ? frame_store_tx[8] : frame_store_rx[8];
+    address_high = (address_high << 8) | (txrx ? frame_store_tx[9] : frame_store_rx[9]);
+    address_high = (address_high << 8) | (txrx ? frame_store_tx[10] : frame_store_rx[10]);
+    address_high = (address_high << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
+    address_low = txrx ? frame_store_tx[12] : frame_store_rx[12];
+    address_low = (address_low << 8) | (txrx ? frame_store_tx[13] : frame_store_rx[13]);
+    address_low = (address_low << 8) | (txrx ? frame_store_tx[14] : frame_store_rx[14]);
+    address_low = (address_low << 8) | (txrx ? frame_store_tx[15] : frame_store_rx[15]);
+    
+    $fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
+    $fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
+    
+    casex({fmt, f_type})
+  
+      `PCI_EXP_MEM_READ64,
+      `PCI_EXP_MEM_WRITE64: begin
+  
+        $fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
+        $fdisplay(_log_file_ptr, "\t Address High: 0x%h", address_high);
+        $fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
+        if (payload == 1) begin
+  
+          for (_i = 16; _i < _frame_store_idx; _i = _i + 1) begin
+  
+            $fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
+  
+          end
+        end
+      end
+    
+      `PCI_EXP_MSG_NODATA,
+      `PCI_EXP_MSG_DATA: begin
+  
+        msg_type = f_type;
+        $fdisplay(_log_file_ptr, "\t Message Type: 0x%h", msg_type);
+        $fdisplay(_log_file_ptr, "\t Message Code: 0x%h", message_code);
+        $fdisplay(_log_file_ptr, "\t Address High: 0x%h", address_high);
+        $fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
+  
+        if (payload == 1) begin
+  
+          for (_i = 16; _i < _frame_store_idx; _i = _i + 1) begin
+  
+            $fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
+          end
+        end
+      end
+    endcase
+    end
+  endtask // TSK_4DW
+
+  
+   /************************************************************
+        Task : TSK_READ_DATA
+        Inputs : None
+        Outputs : None
+        Description : Consume clocks.
+   *************************************************************/
+
+  task TSK_READ_DATA;
+    input    last;
+    input    txrx;
+    input  [63:0]  trn_d;
+    input  [3:0]  trn_rem;
+    integer   _i;
+    reg  [7:0]  _byte;
+    reg  [63:0]  _msk;
+    reg  [3:0]  _rem;
+                begin
+
+      _msk = 64'hff00000000000000;
+      _rem = last ? ((trn_rem == 8'h0F) ? 4 : 8) : 8;
+      for (_i = 0; _i < _rem; _i = _i + 1) begin
+
+        _byte = (trn_d & (_msk >> (_i * 8))) >> (((7) - _i) * 8);
+
+        if (txrx) begin
+
+          board.RP.com_usrapp.frame_store_tx[board.RP.com_usrapp.frame_store_tx_idx] = _byte;
+          board.RP.com_usrapp.frame_store_tx_idx = board.RP.com_usrapp.frame_store_tx_idx + 1;
+
+        end else begin
+
+          board.RP.com_usrapp.frame_store_rx[board.RP.com_usrapp.frame_store_rx_idx] = _byte;
+          board.RP.com_usrapp.frame_store_rx_idx = board.RP.com_usrapp.frame_store_rx_idx + 1;
+        end
+
+      end 
+                end
+   endtask // TSK_READ_DATA
+
+   /************************************************************
+        Task : TSK_READ_DATA_128
+        Inputs : None
+        Outputs : None
+        Description : Consume clocks.
+   *************************************************************/
+
+  task TSK_READ_DATA_128;
+    input    first;
+    input    last;
+    input    txrx;
+    input  [127:0]  trn_d;
+    input  [1:0]  trn_rem;
+    integer   _i;
+    reg  [7:0]  _byte;
+    reg  [127:0]  _msk;
+    reg  [4:0]  _rem;
+    reg  [3:0]  _strt_pos;
+                begin
+
+      _msk = (first && trn_rem[1]) ? 128'h0000000000000000ff00000000000000 : 128'hff000000000000000000000000000000;
+      _rem = first ? (last ? ((trn_rem == 2'b01) ? 12 : 16) : 8) : (last ? (trn_rem[1] ? (trn_rem[0] ? 4 : 8) : (trn_rem[0] ? 12 : 16)) : 16);
+      _strt_pos = (first && trn_rem[1]) ? 4'd7 : 4'd15;
+
+      for (_i = 0; _i < _rem; _i = _i + 1) begin
+
+        _byte = (trn_d & (_msk >> (_i * 8))) >> (((_strt_pos) - _i) * 8);
+
+        if (txrx) begin
+
+          board.RP.com_usrapp.frame_store_tx[board.RP.com_usrapp.frame_store_tx_idx] = _byte;
+          board.RP.com_usrapp.frame_store_tx_idx = board.RP.com_usrapp.frame_store_tx_idx + 1;
+
+        end else begin
+
+          board.RP.com_usrapp.frame_store_rx[board.RP.com_usrapp.frame_store_rx_idx] = _byte;
+          board.RP.com_usrapp.frame_store_rx_idx = board.RP.com_usrapp.frame_store_rx_idx + 1;
+        end
+
+      end 
+                end
+   endtask // TSK_READ_DATA_128
+
+`include "pci_exp_expect_tasks.vh"
+
+endmodule // pci_exp_usrapp_com

src/src/PCIeImports/pci_exp_usrapp_pl.v

@@ -0,0 +1,138 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : pci_exp_usrapp_pl.v
+// Version    : 3.3
+//--
+//--------------------------------------------------------------------------------
+`timescale 1ns/1ns
+module pci_exp_usrapp_pl (
+
+                          pl_initial_link_width,
+                          pl_lane_reversal_mode,
+                          pl_link_gen2_capable,
+                          pl_link_partner_gen2_supported,
+                          pl_link_upcfg_capable,
+                          pl_ltssm_state,
+                          pl_received_hot_rst,
+                          pl_sel_link_rate,
+                          pl_sel_link_width,
+                          pl_directed_link_auton,
+                          pl_directed_link_change,
+                          pl_directed_link_speed,
+                          pl_directed_link_width,
+                          pl_upstream_prefer_deemph,
+                          speed_change_done_n,
+
+                          trn_lnk_up_n,
+                          trn_clk,
+                          trn_reset_n
+                    
+                          );
+
+
+input [2:0]              pl_initial_link_width;
+input [1:0]              pl_lane_reversal_mode;
+input                    pl_link_gen2_capable;
+input                    pl_link_partner_gen2_supported;
+input                    pl_link_upcfg_capable;
+input [5:0]              pl_ltssm_state;
+input                    pl_received_hot_rst;
+input                    pl_sel_link_rate;
+input [1:0]              pl_sel_link_width;
+output                   pl_directed_link_auton;
+output [1:0]             pl_directed_link_change;
+output                   pl_directed_link_speed;
+output [1:0]             pl_directed_link_width;
+output                   pl_upstream_prefer_deemph;
+output                   speed_change_done_n;
+
+
+input                    trn_lnk_up_n;
+input                    trn_clk;
+input                    trn_reset_n;
+
+parameter                Tcq = 1;
+parameter                LINK_CAP_MAX_LINK_SPEED = 4'h1;
+
+reg                      pl_directed_link_auton;
+reg [1:0]                pl_directed_link_change;
+reg                      pl_directed_link_speed;
+reg [1:0]                pl_directed_link_width;
+reg                      pl_upstream_prefer_deemph;
+reg                      speed_change_done_n;
+
+initial begin
+
+   pl_directed_link_auton <= 1'b0;
+   pl_directed_link_change <= 2'b0;
+   pl_directed_link_speed <= 1'b0;
+   pl_directed_link_width <= 2'b0;
+   pl_upstream_prefer_deemph <= 1'b0;
+   speed_change_done_n <= 1'b1;
+
+   if (LINK_CAP_MAX_LINK_SPEED == 4'h2) begin
+
+     wait (trn_lnk_up_n == 1'b0);
+
+     if (pl_link_gen2_capable && pl_link_partner_gen2_supported) begin
+
+       wait (pl_sel_link_rate == 1'h1);
+       wait (pl_ltssm_state == 6'h16);
+
+       speed_change_done_n <= 1'b0; 
+
+     end
+   end
+
+end
+
+endmodule // pci_exp_usrapp_pl
+

src/src/PCIeImports/pci_exp_usrapp_rx.v

@@ -0,0 +1,475 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : pci_exp_usrapp_rx.v
+// Version    : 3.3
+//--
+//--------------------------------------------------------------------------------
+
+`include "board_common.vh"
+
+`define EXPECT_FINISH_CHECK board.RP.tx_usrapp.expect_finish_check
+module pci_exp_usrapp_rx #(
+parameter                                  C_DATA_WIDTH = 64,
+parameter                                  REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1
+)
+(
+                     
+                                           trn_rdst_rdy_n,
+                                           trn_rnp_ok_n,
+              
+                                           trn_rd,
+                                           trn_rrem_n,
+                                           trn_rsof_n,
+                                           trn_reof_n,
+                                           trn_rsrc_rdy_n,
+                                           trn_rsrc_dsc_n,
+                                           trn_rerrfwd_n,
+                                           trn_rbar_hit_n,
+              
+                                           trn_clk,
+                                           trn_reset_n,
+                                           trn_lnk_up_n
+              
+                                           );
+
+output                                     trn_rdst_rdy_n;
+output                                     trn_rnp_ok_n;
+
+input  [C_DATA_WIDTH-1:0]                  trn_rd;
+input  [REM_WIDTH-1:0]                     trn_rrem_n;
+input                                      trn_rsof_n;
+input                                      trn_reof_n;
+input                                      trn_rsrc_rdy_n;
+input                                      trn_rsrc_dsc_n;
+input                                      trn_rerrfwd_n;
+input  [(7 - 1):0]                         trn_rbar_hit_n;
+
+input                                      trn_clk;
+input                                      trn_reset_n;
+input                                      trn_lnk_up_n;
+
+parameter                                   Tcq = 1;
+
+/* Output variables */
+
+reg               trn_rdst_rdy_n, next_trn_rdst_rdy_n;
+reg               trn_rnp_ok_n, next_trn_rnp_ok_n;
+
+/* Local variables */
+
+reg     [4:0]     trn_rx_state, next_trn_rx_state;
+reg               trn_rx_in_frame, next_trn_rx_in_frame;
+reg               trn_rx_in_channel, next_trn_rx_in_channel;
+
+reg     [31:0]    next_trn_rx_timeout;
+
+/* State variables */
+
+`define           TRN_RX_RESET    5'b00001
+`define           TRN_RX_DOWN     5'b00010
+`define           TRN_RX_IDLE     5'b00100
+`define           TRN_RX_ACTIVE   5'b01000
+`define           TRN_RX_SRC_DSC  5'b10000
+
+
+/* Transaction Receive User Interface State Machine */
+
+generate
+if (C_DATA_WIDTH == 64) begin : trn_rx_sm_64
+always @(posedge trn_clk or negedge trn_reset_n) begin
+
+  if (trn_reset_n == 1'b0) begin
+
+    trn_rx_state     <= #(Tcq)  `TRN_RX_RESET;
+
+  end else begin
+
+  case (trn_rx_state)
+
+    `TRN_RX_RESET :  begin
+      
+      if (trn_reset_n == 1'b0)
+        
+        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
+
+      else
+
+        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
+    end
+
+    `TRN_RX_DOWN : begin
+
+      if (trn_lnk_up_n == 1'b1)
+
+        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
+
+      else begin
+        
+        trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
+      end
+
+    end
+
+    `TRN_RX_IDLE : begin
+
+      if (trn_reset_n == 1'b0)
+        
+        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
+
+      else if (trn_lnk_up_n == 1'b1)
+
+        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
+
+      else begin
+
+        if (  (trn_rsof_n == 1'b0) &&
+              (trn_rsrc_rdy_n == 1'b0) &&
+               (trn_rdst_rdy_n == 1'b0)  ) begin
+
+          board.RP.com_usrapp.TSK_READ_DATA(0, `RX_LOG, trn_rd, trn_rrem_n);
+
+          trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
+
+        end else begin
+
+          trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
+
+        end
+      end
+
+    end
+
+    `TRN_RX_ACTIVE : begin
+
+      if (trn_reset_n == 1'b0)
+        
+        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
+
+      else if (trn_lnk_up_n == 1'b1)
+
+        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
+
+      else if (  (trn_rsrc_rdy_n == 1'b0) && 
+                (trn_reof_n == 1'b0) &&
+                 (trn_rdst_rdy_n == 1'b0)  ) begin
+
+        board.RP.com_usrapp.TSK_READ_DATA(1, `RX_LOG, trn_rd, trn_rrem_n);
+        board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
+
+        trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
+
+      end else if (  (trn_rsrc_rdy_n == 1'b0) &&
+                     (trn_rdst_rdy_n == 1'b0)  ) begin
+
+        board.RP.com_usrapp.TSK_READ_DATA(0, `RX_LOG, trn_rd, trn_rrem_n);
+
+        trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
+
+      end else if (  (trn_rsrc_rdy_n == 1'b0) &&
+          (trn_reof_n == 1'b0) &&
+          (trn_rsrc_dsc_n == 1'b0)  ) begin
+
+        board.RP.com_usrapp.TSK_READ_DATA(1, `RX_LOG, trn_rd, trn_rrem_n);
+        board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
+
+        trn_rx_state <= #(Tcq) `TRN_RX_SRC_DSC;
+
+      end else begin
+
+        trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
+      end
+
+    end
+
+    `TRN_RX_SRC_DSC : begin
+
+      if (trn_reset_n == 1'b0)
+
+        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
+
+      else if (trn_lnk_up_n == 1'b1)
+
+        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
+
+      else begin
+
+        trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
+
+      end
+    end
+
+  endcase
+
+   end
+
+end
+end 
+else if (C_DATA_WIDTH == 128) begin : trn_rx_sm_128
+always @(posedge trn_clk or negedge trn_reset_n) begin
+
+  if (trn_reset_n == 1'b0) begin
+
+    trn_rx_state     <= #(Tcq)  `TRN_RX_RESET;
+
+  end else begin
+
+  case (trn_rx_state)
+
+    `TRN_RX_RESET :  begin
+      
+      if (trn_reset_n == 1'b0)
+        
+        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
+
+      else
+
+        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
+    end
+
+    `TRN_RX_DOWN : begin
+
+      if (trn_lnk_up_n == 1'b1)
+
+        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
+
+      else begin
+        
+        trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
+      end
+
+    end
+
+    `TRN_RX_IDLE : begin
+
+      if (trn_reset_n == 1'b0)
+        
+        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
+
+      else if (trn_lnk_up_n == 1'b1)
+
+        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
+
+      else begin
+
+      // single TLP in a Data Beat Case
+
+        if (  (trn_rsof_n == 1'b0) &&
+              (trn_rsrc_rdy_n == 1'b0) &&
+               (trn_rdst_rdy_n == 1'b0)  ) begin
+
+          board.RP.com_usrapp.TSK_READ_DATA_128(~trn_rsof_n, ~trn_reof_n, `RX_LOG, trn_rd, trn_rrem_n);
+          if ( (trn_rsof_n == 1'b0) && (trn_reof_n == 1'b0)) begin
+
+            board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
+            trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
+
+          end else begin
+
+            trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
+
+          end
+        end else begin
+
+          trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
+
+        end
+      end
+
+    end
+
+    `TRN_RX_ACTIVE : begin
+
+      if (trn_reset_n == 1'b0)
+        
+        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
+
+      else if (trn_lnk_up_n == 1'b1)
+
+        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
+
+      else if (  (trn_rsrc_rdy_n == 1'b0) && 
+                 (trn_rdst_rdy_n == 1'b0)  ) begin
+
+        case ({trn_rsof_n, trn_reof_n})
+                  // Data Stream - both sof & eof de-asserted
+          2'b11 : begin
+                    board.RP.com_usrapp.TSK_READ_DATA_128(0, 0, `RX_LOG, trn_rd, trn_rrem_n);
+                    trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
+                  end
+                  // EOF scenario. Not a straddle case
+          2'b10 : begin
+                    board.RP.com_usrapp.TSK_READ_DATA_128(0, 1, `RX_LOG, trn_rd, trn_rrem_n);
+                    board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
+                    trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
+                  end
+          2'b00 : begin
+                    board.RP.com_usrapp.TSK_READ_DATA_128(0, 1, `RX_LOG, trn_rd, trn_rrem_n);
+                    board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
+                    board.RP.com_usrapp.TSK_READ_DATA_128(1, 0, `RX_LOG, trn_rd, trn_rrem_n);
+                    trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
+                  end
+            //2'b01 is not a valid option as the TRN_RX_ACTIVE case is only entered when we have seen an SOF but not an EOF, in the TRN_RX_IDLE state
+          endcase
+
+      end else if (  (trn_rsrc_rdy_n == 1'b0) &&
+          (trn_reof_n == 1'b0) &&
+          (trn_rsrc_dsc_n == 1'b0)  ) begin
+
+             board.RP.com_usrapp.TSK_READ_DATA_128(0, 1, `RX_LOG, trn_rd, trn_rrem_n);
+             board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
+
+             trn_rx_state <= #(Tcq) `TRN_RX_SRC_DSC;
+
+      end else begin
+
+        trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
+      end
+
+    end
+
+    `TRN_RX_SRC_DSC : begin
+
+      if (trn_reset_n == 1'b0)
+
+        trn_rx_state <= #(Tcq) `TRN_RX_RESET;
+
+      else if (trn_lnk_up_n == 1'b1)
+
+        trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
+
+      else begin
+
+        trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
+
+      end
+    end
+
+  endcase
+
+   end
+
+end
+end
+endgenerate
+
+
+reg [1:0]   trn_rdst_rdy_toggle_count;
+reg [8:0]   trn_rnp_ok_toggle_count;
+
+always @(posedge trn_clk or negedge trn_reset_n) begin
+
+   if (trn_reset_n == 1'b0) begin
+
+    trn_rnp_ok_n        <= #(Tcq)   1'b0;
+    trn_rdst_rdy_n      <= #(Tcq)       1'b0;
+    trn_rdst_rdy_toggle_count <= #(Tcq) $random;
+    trn_rnp_ok_toggle_count <=  #(Tcq)     $random;
+
+   end else begin
+
+    if (trn_rnp_ok_toggle_count == 0) begin
+
+        trn_rnp_ok_n        <= #(Tcq)   !trn_rnp_ok_n;
+        trn_rnp_ok_toggle_count <=  #(Tcq)     $random;
+
+    end else begin
+
+        //trn_rnp_ok_toggle_count   <=  #(Tcq)     trn_rnp_ok_toggle_count - 1;
+                
+    end         
+
+    if (trn_rdst_rdy_toggle_count == 0) begin
+
+        //trn_rdst_rdy_n      <= #(Tcq)       !trn_rdst_rdy_n;
+        trn_rdst_rdy_toggle_count <= #(Tcq) $random;
+                
+    end else begin
+
+        //trn_rdst_rdy_toggle_count <= trn_rdst_rdy_toggle_count - 1;
+    end
+        
+   end
+            
+end
+                
+reg [31:0] sim_timeout;
+initial
+begin
+  sim_timeout = `TRN_RX_TIMEOUT;
+end
+
+/* Transaction Receive Timeout */
+            
+always @(trn_clk or trn_rsof_n or trn_rsrc_rdy_n) begin
+                
+    if (next_trn_rx_timeout == 0) begin
+        if(!`EXPECT_FINISH_CHECK)
+          $display("[%t] : TEST FAILED --- Haven't Received All Expected TLPs", $realtime);
+
+        $finish(2);
+    end
+                
+    if ((trn_rsof_n == 1'b0) && (trn_rsrc_rdy_n == 1'b0)) begin
+            
+        next_trn_rx_timeout = sim_timeout;
+
+    end else begin
+
+        if (trn_lnk_up_n == 1'b0)
+
+            next_trn_rx_timeout = next_trn_rx_timeout - 1'b1;
+
+    end
+
+end
+
+endmodule // pci_exp_usrapp_rx
+

src/src/PCIeImports/pcie1234_gt_top_pipe_mode.v

@@ -0,0 +1,372 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : pcie1234_gt_top_pipe_mode.v
+// Version    : 3.3
+//-- Description: GTX module for 7-series Integrated PCIe Block
+//--
+//--
+//--
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module pcie1234_gt_top_pipe_mode #
+(
+   parameter               LINK_CAP_MAX_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
+   parameter               REF_CLK_FREQ = 0,            // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
+   parameter               USER_CLK2_DIV2 = "FALSE",    // "FALSE" => user_clk2 = user_clk
+                                                        // "TRUE" => user_clk2 = user_clk/2, where user_clk = 500 or 250 MHz.
+   parameter  integer      USER_CLK_FREQ = 3,           // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
+   parameter               PL_FAST_TRAIN = "FALSE",     // Simulation Speedup
+   parameter               PCIE_EXT_CLK = "FALSE",      // Use External Clocking
+   parameter               PCIE_USE_MODE = "1.0",       // 1.0 = K325T IES, 1.1 = VX485T IES, 3.0 = K325T GES
+   parameter               PCIE_GT_DEVICE = "GTX",      // Select the GT to use (GTP for Artix-7, GTX for K7/V7)
+   parameter               PCIE_PLL_SEL   = "CPLL",     // Select the PLL (CPLL or QPLL)
+   parameter               PCIE_ASYNC_EN  = "FALSE",    // Asynchronous Clocking Enable
+   parameter               PCIE_TXBUF_EN  = "FALSE",    // Use the Tansmit Buffer
+   parameter               PCIE_CHAN_BOND = 0
+)
+(
+   // pl ltssm
+   input   wire [5:0]                pl_ltssm_state         ,
+   // Pipe Per-Link Signals
+   input   wire                      pipe_tx_rcvr_det       ,
+   input   wire                      pipe_tx_reset          ,
+   input   wire                      pipe_tx_rate           ,
+   input   wire                      pipe_tx_deemph         ,
+   input   wire [2:0]                pipe_tx_margin         ,
+   input   wire                      pipe_tx_swing          ,
+
+   // Clock Inputs                                                                                                    //
+
+   input                                      PIPE_PCLK_IN,
+   input                                      PIPE_RXUSRCLK_IN,
+   input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0]  PIPE_RXOUTCLK_IN,
+   input                                      PIPE_DCLK_IN,
+   input                                      PIPE_USERCLK1_IN,
+   input                                      PIPE_USERCLK2_IN,
+   input                                      PIPE_OOBCLK_IN,
+   input                                      PIPE_MMCM_LOCK_IN,
+
+   output                                     PIPE_TXOUTCLK_OUT,
+   output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_OUT,
+   output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_PCLK_SEL_OUT,
+   output                                     PIPE_GEN3_OUT,
+
+   // Pipe Per-Lane Signals - Lane 0
+   output  wire [ 1:0]               pipe_rx0_char_is_k     ,
+   output  wire [15:0]               pipe_rx0_data          ,
+   output  wire                      pipe_rx0_valid         ,
+   output  wire                      pipe_rx0_chanisaligned ,
+   output  wire [ 2:0]               pipe_rx0_status        ,
+   output  wire                      pipe_rx0_phy_status    ,
+   output  wire                      pipe_rx0_elec_idle     ,
+   input   wire                      pipe_rx0_polarity      ,
+   input   wire                      pipe_tx0_compliance    ,
+   input   wire [ 1:0]               pipe_tx0_char_is_k     ,
+   input   wire [15:0]               pipe_tx0_data          ,
+   input   wire                      pipe_tx0_elec_idle     ,
+   input   wire [ 1:0]               pipe_tx0_powerdown     ,
+
+   // Pipe Per-Lane Signals - Lane 1
+   output  wire [ 1:0]               pipe_rx1_char_is_k     ,
+   output  wire [15:0]               pipe_rx1_data          ,
+   output  wire                      pipe_rx1_valid         ,
+   output  wire                      pipe_rx1_chanisaligned ,
+   output  wire [ 2:0]               pipe_rx1_status        ,
+   output  wire                      pipe_rx1_phy_status    ,
+   output  wire                      pipe_rx1_elec_idle     ,
+   input   wire                      pipe_rx1_polarity      ,
+   input   wire                      pipe_tx1_compliance    ,
+   input   wire [ 1:0]               pipe_tx1_char_is_k     ,
+   input   wire [15:0]               pipe_tx1_data          ,
+   input   wire                      pipe_tx1_elec_idle     ,
+   input   wire [ 1:0]               pipe_tx1_powerdown     ,
+
+   // Pipe Per-Lane Signals - Lane 2
+   output  wire [ 1:0]               pipe_rx2_char_is_k     ,
+   output  wire [15:0]               pipe_rx2_data          ,
+   output  wire                      pipe_rx2_valid         ,
+   output  wire                      pipe_rx2_chanisaligned ,
+   output  wire [ 2:0]               pipe_rx2_status        ,
+   output  wire                      pipe_rx2_phy_status    ,
+   output  wire                      pipe_rx2_elec_idle     ,
+   input   wire                      pipe_rx2_polarity      ,
+   input   wire                      pipe_tx2_compliance    ,
+   input   wire [ 1:0]               pipe_tx2_char_is_k     ,
+   input   wire [15:0]               pipe_tx2_data          ,
+   input   wire                      pipe_tx2_elec_idle     ,
+   input   wire [ 1:0]               pipe_tx2_powerdown     ,
+
+   // Pipe Per-Lane Signals - Lane 3
+   output  wire [ 1:0]               pipe_rx3_char_is_k     ,
+   output  wire [15:0]               pipe_rx3_data          ,
+   output  wire                      pipe_rx3_valid         ,
+   output  wire                      pipe_rx3_chanisaligned ,
+   output  wire [ 2:0]               pipe_rx3_status        ,
+   output  wire                      pipe_rx3_phy_status    ,
+   output  wire                      pipe_rx3_elec_idle     ,
+   input   wire                      pipe_rx3_polarity      ,
+   input   wire                      pipe_tx3_compliance    ,
+   input   wire [ 1:0]               pipe_tx3_char_is_k     ,
+   input   wire [15:0]               pipe_tx3_data          ,
+   input   wire                      pipe_tx3_elec_idle     ,
+   input   wire [ 1:0]               pipe_tx3_powerdown     ,
+
+   // Pipe Per-Lane Signals - Lane 4
+   output  wire [ 1:0]               pipe_rx4_char_is_k     ,
+   output  wire [15:0]               pipe_rx4_data          ,
+   output  wire                      pipe_rx4_valid         ,
+   output  wire                      pipe_rx4_chanisaligned ,
+   output  wire [ 2:0]               pipe_rx4_status        ,
+   output  wire                      pipe_rx4_phy_status    ,
+   output  wire                      pipe_rx4_elec_idle     ,
+   input   wire                      pipe_rx4_polarity      ,
+   input   wire                      pipe_tx4_compliance    ,
+   input   wire [ 1:0]               pipe_tx4_char_is_k     ,
+   input   wire [15:0]               pipe_tx4_data          ,
+   input   wire                      pipe_tx4_elec_idle     ,
+   input   wire [ 1:0]               pipe_tx4_powerdown     ,
+
+   // Pipe Per-Lane Signals - Lane 5
+   output  wire [ 1:0]               pipe_rx5_char_is_k     ,
+   output  wire [15:0]               pipe_rx5_data          ,
+   output  wire                      pipe_rx5_valid         ,
+   output  wire                      pipe_rx5_chanisaligned ,
+   output  wire [ 2:0]               pipe_rx5_status        ,
+   output  wire                      pipe_rx5_phy_status    ,
+   output  wire                      pipe_rx5_elec_idle     ,
+   input   wire                      pipe_rx5_polarity      ,
+   input   wire                      pipe_tx5_compliance    ,
+   input   wire [ 1:0]               pipe_tx5_char_is_k     ,
+   input   wire [15:0]               pipe_tx5_data          ,
+   input   wire                      pipe_tx5_elec_idle     ,
+   input   wire [ 1:0]               pipe_tx5_powerdown     ,
+
+   // Pipe Per-Lane Signals - Lane 6
+   output  wire [ 1:0]               pipe_rx6_char_is_k     ,
+   output  wire [15:0]               pipe_rx6_data          ,
+   output  wire                      pipe_rx6_valid         ,
+   output  wire                      pipe_rx6_chanisaligned ,
+   output  wire [ 2:0]               pipe_rx6_status        ,
+   output  wire                      pipe_rx6_phy_status    ,
+   output  wire                      pipe_rx6_elec_idle     ,
+   input   wire                      pipe_rx6_polarity      ,
+   input   wire                      pipe_tx6_compliance    ,
+   input   wire [ 1:0]               pipe_tx6_char_is_k     ,
+   input   wire [15:0]               pipe_tx6_data          ,
+   input   wire                      pipe_tx6_elec_idle     ,
+   input   wire [ 1:0]               pipe_tx6_powerdown     ,
+
+   // Pipe Per-Lane Signals - Lane 7
+   output  wire [ 1:0]               pipe_rx7_char_is_k     ,
+   output  wire [15:0]               pipe_rx7_data          ,
+   output  wire                      pipe_rx7_valid         ,
+   output  wire                      pipe_rx7_chanisaligned ,
+   output  wire [ 2:0]               pipe_rx7_status        ,
+   output  wire                      pipe_rx7_phy_status    ,
+   output  wire                      pipe_rx7_elec_idle     ,
+   input   wire                      pipe_rx7_polarity      ,
+   input   wire                      pipe_tx7_compliance    ,
+   input   wire [ 1:0]               pipe_tx7_char_is_k     ,
+   input   wire [15:0]               pipe_tx7_data          ,
+   input   wire                      pipe_tx7_elec_idle     ,
+   input   wire [ 1:0]               pipe_tx7_powerdown     ,
+
+   // PCI Express signals
+   output  wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txn            ,
+   output  wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txp            ,
+   input   wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxn            ,
+   input   wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxp            ,
+
+   // Non PIPE signals
+   input   wire                      sys_clk                ,
+   input   wire                      sys_rst_n              ,
+   input   wire                      PIPE_MMCM_RST_N        ,        // Async      | Async
+
+   output  wire                      pipe_clk               ,
+   output  wire                      user_clk               ,
+   output  wire                      user_clk2              ,
+
+   output  wire                      phy_rdy_n
+);
+
+  localparam                          TCQ  = 100;      // clock to out delay model
+  localparam      LINK_CAP_MAX_LINK_SPEED = (PL_FAST_TRAIN == "TRUE") ? 2 : 3;
+  localparam      USERCLK2_FREQ   =  (USER_CLK2_DIV2 == "FALSE") ? USER_CLK_FREQ :
+                                                        (USER_CLK_FREQ == 4) ? 3 :
+                                                        (USER_CLK_FREQ == 3) ? 2 :
+                                                       USER_CLK_FREQ;
+   wire pcl_sel_sim;
+   reg [11:0] pipe_cnt1 = 0;
+   reg phy_rdy_ni = 0;
+
+
+pcie1234_pipe_clock #
+        (
+            .PCIE_ASYNC_EN                  (PCIE_ASYNC_EN),        // PCIe async enable
+            .PCIE_TXBUF_EN                  (PCIE_TXBUF_EN),        // PCIe TX buffer enable for Gen1/Gen2 only
+            .PCIE_LANE                      (LINK_CAP_MAX_LINK_WIDTH),            // PCIe number of lanes
+            .PCIE_LINK_SPEED                (LINK_CAP_MAX_LINK_SPEED),      // PCIe link speed
+            .PCIE_REFCLK_FREQ               (REF_CLK_FREQ),     // PCIe reference clock frequency
+            .PCIE_USERCLK1_FREQ             (USER_CLK_FREQ + 1),   // PCIe user clock 1 frequency
+            .PCIE_USERCLK2_FREQ             (USERCLK2_FREQ + 1),   // PCIe user clock 2 frequency
+            .PCIE_DEBUG_MODE                (1'b0)       // PCIe debug mode
+        )
+        pipe_clock_i
+        (
+            //---------- Input -------------------------------------
+            .CLK_CLK                        (sys_clk),
+            .CLK_TXOUTCLK                   (sys_clk),       // Reference clock from lane 0
+            .CLK_RXOUTCLK_IN                ({LINK_CAP_MAX_LINK_WIDTH {1'b0}}),
+            .CLK_RST_N                      (1'b1),
+            .CLK_PCLK_SEL                   ({LINK_CAP_MAX_LINK_WIDTH {pcl_sel_sim}}),
+            .CLK_GEN3                       (1'b0),
+
+            //---------- Output ------------------------------------
+            .CLK_PCLK                       (pipe_clk),
+            .CLK_RXUSRCLK                   ( ),
+            .CLK_RXOUTCLK_OUT               (PIPE_RXOUTCLK_OUT),
+            .CLK_DCLK                       ( ),
+            .CLK_USERCLK1                   (user_clk),
+            .CLK_USERCLK2                   (user_clk2),
+            .CLK_MMCM_LOCK                  ( )
+        );
+   //--------------------------------------------------------------------//  
+   // Free running counter begins once the pipe_tx_rcvr_det is seen high and continues till it gets saturation.
+   always @(posedge pipe_clk)
+   begin
+       if (sys_rst_n == 0) begin
+           pipe_cnt1 <= #TCQ 0;
+       end else begin
+          if (pipe_cnt1 == 2047)
+              pipe_cnt1 <= #TCQ 0;
+          else begin
+             if (pipe_tx_rcvr_det || pipe_cnt1 >= 1) 
+                 pipe_cnt1 <= #TCQ pipe_cnt1 + 1;
+             else
+                 pipe_cnt1 <= #TCQ 0;
+          end
+       end
+   end 
+   //--------------------------------------------------------------------//  
+   // phy status signal need to asserted once when pipe_tx_rcvr_det is hight and again after it gets low. And also on every rate change.
+   assign pipe_rx0_phy_status    =  (((pipe_tx_rate == 1) && (pipe_cnt1 == 1750) && (pl_ltssm_state == 6'b011111)) ? 1 : 
+                                    ((pipe_cnt1 == 1) ? 1 : ((pipe_cnt1 == 10) ? 1 : 0))); 
+   assign pipe_rx1_phy_status    =  pipe_rx0_phy_status; 
+   assign pipe_rx2_phy_status    =  pipe_rx0_phy_status; 
+   assign pipe_rx3_phy_status    =  pipe_rx0_phy_status; 
+   assign pipe_rx4_phy_status    =  pipe_rx0_phy_status; 
+   assign pipe_rx5_phy_status    =  pipe_rx0_phy_status; 
+   assign pipe_rx6_phy_status    =  pipe_rx0_phy_status; 
+   assign pipe_rx7_phy_status    =  pipe_rx0_phy_status; 
+   //--------------------------------------------------------------------// 
+   // Alignement has to be asserted based on the link speed and LTSSM state, counter 1700/1750 meant for change in rate from gen1 to gen2 
+   assign pipe_rx0_chanisaligned =  (((sys_rst_n == 1 && pipe_tx_rate == 0 ) ? 1 : (sys_rst_n == 0 && pipe_tx_rate == 0) ? 0 : 
+                                    ((pipe_tx_rate == 1) && (pipe_cnt1 == 1700) && (pl_ltssm_state == 6'b011111)) ? 0 : 
+                                    ((pipe_tx_rate == 1) && (pipe_cnt1 == 1750)  ? 1 : pipe_rx0_chanisaligned ))) ;
+   assign pipe_rx1_chanisaligned = pipe_rx0_chanisaligned; 
+   assign pipe_rx2_chanisaligned = pipe_rx0_chanisaligned; 
+   assign pipe_rx3_chanisaligned = pipe_rx0_chanisaligned; 
+   assign pipe_rx4_chanisaligned = pipe_rx0_chanisaligned; 
+   assign pipe_rx5_chanisaligned = pipe_rx0_chanisaligned; 
+   assign pipe_rx6_chanisaligned = pipe_rx0_chanisaligned; 
+   assign pipe_rx7_chanisaligned = pipe_rx0_chanisaligned; 
+
+   //--------------------------------------------------------------------//  
+   // status gets values based on the link speed and LTSSM state as below. counter 1700/1701 meant for change in rate from gen1 to gen2
+   assign pipe_rx0_status        =  ((sys_rst_n == 0) ? 0 :  
+                                    ((pipe_tx_rate == 1) && (pipe_cnt1 == 1750) && (pl_ltssm_state == 6'b011111)) ? 4 : 
+                                    ((pipe_tx_rate == 1) && (pipe_cnt1 == 1751) && (pl_ltssm_state == 6'b011111)) ? 0 : 
+                                    ((pipe_cnt1 == 1) ? 3 : (pipe_cnt1 == 2) ? 0 : pipe_rx0_status));  
+   assign pipe_rx1_status        =  pipe_rx0_status;  
+   assign pipe_rx2_status        =  pipe_rx0_status;  
+   assign pipe_rx3_status        =  pipe_rx0_status;  
+   assign pipe_rx4_status        =  pipe_rx0_status;  
+   assign pipe_rx5_status        =  pipe_rx0_status;  
+   assign pipe_rx6_status        =  pipe_rx0_status;  
+   assign pipe_rx7_status        =  pipe_rx0_status;  
+   //--------------------------------------------------------------------//  
+   // aligning with chanisaligned
+   assign pipe_rx0_valid         =  pipe_rx0_chanisaligned;
+   assign pipe_rx1_valid         =  pipe_rx0_valid;
+   assign pipe_rx2_valid         =  pipe_rx0_valid;
+   assign pipe_rx3_valid         =  pipe_rx0_valid;
+   assign pipe_rx4_valid         =  pipe_rx0_valid;
+   assign pipe_rx5_valid         =  pipe_rx0_valid;
+   assign pipe_rx6_valid         =  pipe_rx0_valid;
+   assign pipe_rx7_valid         =  pipe_rx0_valid;
+   //--------------------------------------------------------------------//  
+   // can be connected to other end tx0 electrical idles
+   assign pipe_rx0_elec_idle     =  0;
+   assign pipe_rx1_elec_idle     =  0;
+   assign pipe_rx2_elec_idle     =  0;
+   assign pipe_rx3_elec_idle     =  0;
+   assign pipe_rx4_elec_idle     =  0;
+   assign pipe_rx5_elec_idle     =  0;
+   assign pipe_rx6_elec_idle     =  0;
+   assign pipe_rx7_elec_idle     =  0;
+   //--------------------------------------------------------------------//  
+   assign phy_rdy_n = phy_rdy_ni;
+
+   // BUFG_MUX selection should  be '1' when the link speed changes to GEN2 (5.0 Gbps)
+
+   assign pcl_sel_sim            =  ((sys_rst_n == 0 && pipe_tx_rate == 0) ? 0 : (pipe_tx_rate == 1) ? 1 : pcl_sel_sim);
+   //--------------------------------------------------------------------// 
+   initial begin
+   phy_rdy_ni =  1'b1;
+   #2000000; 
+   phy_rdy_ni =  1'b0;
+   end
+   //--------------------------------------------------------------------// 
+
+endmodule
+

src/src/PCIeImports/pcie1234_pipe_clock.v

@@ -0,0 +1,620 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : pcie1234_pipe_clock.v
+// Version    : 3.3
+//------------------------------------------------------------------------------
+//  Filename     :  pipe_clock.v
+//  Description  :  PIPE Clock Module for 7 Series Transceiver
+//  Version      :  15.3
+//------------------------------------------------------------------------------
+
+
+
+`timescale 1ns / 1ps
+
+
+
+//---------- PIPE Clock Module -------------------------------------------------
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pcie1234_pipe_clock #
+(
+
+	parameter PCIE_ASYNC_EN      = "FALSE",                 // PCIe async enable
+	parameter PCIE_TXBUF_EN      = "FALSE",                 // PCIe TX buffer enable for Gen1/Gen2 only
+	parameter PCIE_CLK_SHARING_EN= "FALSE",                 // Enable Clock Sharing
+	parameter PCIE_LANE          = 1,                       // PCIe number of lanes
+	parameter PCIE_LINK_SPEED    = 3,                       // PCIe link speed 
+	parameter PCIE_REFCLK_FREQ   = 0,                       // PCIe reference clock frequency
+	parameter PCIE_USERCLK1_FREQ = 2,                       // PCIe user clock 1 frequency
+	parameter PCIE_USERCLK2_FREQ = 2,                       // PCIe user clock 2 frequency
+	parameter PCIE_OOBCLK_MODE   = 1,                       // PCIe oob clock mode
+	parameter PCIE_DEBUG_MODE    = 0                        // PCIe Debug mode
+	
+)
+
+(
+
+	//---------- Input -------------------------------------
+	input                       CLK_CLK,
+	input                       CLK_TXOUTCLK,
+	input       [PCIE_LANE-1:0] CLK_RXOUTCLK_IN,
+	input                       CLK_RST_N,
+	input       [PCIE_LANE-1:0] CLK_PCLK_SEL,
+	input       [PCIE_LANE-1:0] CLK_PCLK_SEL_SLAVE,
+	input                       CLK_GEN3,
+	
+	//---------- Output ------------------------------------
+	output                      CLK_PCLK,
+	output                      CLK_PCLK_SLAVE,
+	output                      CLK_RXUSRCLK,
+	output      [PCIE_LANE-1:0] CLK_RXOUTCLK_OUT,
+	output                      CLK_DCLK,
+	output                      CLK_OOBCLK,
+	output                      CLK_USERCLK1,
+	output                      CLK_USERCLK2,
+	output                      CLK_MMCM_LOCK
+
+	/*output						ClkUser3_o*/
+	
+);
+	
+	//---------- Select Clock Divider ----------------------
+	localparam          DIVCLK_DIVIDE    = (PCIE_REFCLK_FREQ == 2) ? 1 :
+										   (PCIE_REFCLK_FREQ == 1) ? 1 : 1;
+											   
+	localparam          CLKFBOUT_MULT_F  = (PCIE_REFCLK_FREQ == 2) ? 4 :
+										   (PCIE_REFCLK_FREQ == 1) ? 8 : 10;
+			   
+	localparam          CLKIN1_PERIOD    = (PCIE_REFCLK_FREQ == 2) ? 4 :
+										   (PCIE_REFCLK_FREQ == 1) ? 8 : 10;
+											   
+	localparam          CLKOUT0_DIVIDE_F = 8;
+	
+	localparam          CLKOUT1_DIVIDE   = 4;
+	
+	localparam          CLKOUT2_DIVIDE   = (PCIE_USERCLK1_FREQ == 5) ?  2 : 
+										   (PCIE_USERCLK1_FREQ == 4) ?  4 :
+										   (PCIE_USERCLK1_FREQ == 3) ?  8 :
+										   (PCIE_USERCLK1_FREQ == 1) ? 32 : 16;
+											   
+	localparam          CLKOUT3_DIVIDE   = (PCIE_USERCLK2_FREQ == 5) ?  2 : 
+										   (PCIE_USERCLK2_FREQ == 4) ?  4 :
+										   (PCIE_USERCLK2_FREQ == 3) ?  8 :
+										   (PCIE_USERCLK2_FREQ == 1) ? 32 : 16;
+										   
+	localparam          CLKOUT4_DIVIDE   = 20;
+	localparam          CLKOUT5_DIVIDE   = 20;
+
+	localparam          PCIE_GEN1_MODE    = 1'b1;             // PCIe link speed is GEN1 only
+									
+	   
+	//---------- Input Registers ---------------------------
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0] pclk_sel_slave_reg1 = {PCIE_LANE{1'd0}};
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                         gen3_reg1     = 1'd0;
+	
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg         [PCIE_LANE-1:0] pclk_sel_slave_reg2 = {PCIE_LANE{1'd0}};
+(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)    reg                         gen3_reg2     = 1'd0;   
+	   
+	//---------- Internal Signals -------------------------- 
+	wire                            refclk;
+	wire                            mmcm_fb;
+	wire                            clk_125mhz;
+	wire                            clk_125mhz_buf;
+	wire                            clk_250mhz;
+	wire                            userclk1;
+	wire                            userclk2;
+	wire                            oobclk;
+	(* dont_touch = "true" *)reg    pclk_sel = 1'd0;
+	reg                             pclk_sel_slave = 1'd0;
+
+	//---------- Output Registers --------------------------
+	wire                        pclk_1;
+	wire                        pclk;
+	wire                        userclk1_1;
+	wire                        userclk2_1;
+	wire                        mmcm_lock;
+	
+	//---------- Generate Per-Lane Signals -----------------
+	genvar              i;                                  // Index for per-lane signals
+
+
+
+//---------- Input FF ----------------------------------------------------------
+always @ (posedge pclk)
+begin
+
+	if (!CLK_RST_N)
+		begin
+		//---------- 1st Stage FF --------------------------
+		pclk_sel_reg1 <= {PCIE_LANE{1'd0}};
+		pclk_sel_slave_reg1 <= {PCIE_LANE{1'd0}};
+		gen3_reg1     <= 1'd0;
+		//---------- 2nd Stage FF --------------------------
+		pclk_sel_reg2 <= {PCIE_LANE{1'd0}};
+		pclk_sel_slave_reg2 <= {PCIE_LANE{1'd0}};
+		gen3_reg2     <= 1'd0;
+		end
+	else
+		begin  
+		//---------- 1st Stage FF --------------------------
+		pclk_sel_reg1 <= CLK_PCLK_SEL;
+		pclk_sel_slave_reg1 <= CLK_PCLK_SEL_SLAVE;
+		gen3_reg1     <= CLK_GEN3;
+		//---------- 2nd Stage FF --------------------------
+		pclk_sel_reg2 <= pclk_sel_reg1;
+		pclk_sel_slave_reg2 <= pclk_sel_slave_reg1;
+		gen3_reg2     <= gen3_reg1;
+		end
+		
+end
+
+
+   
+//---------- Select Reference clock or TXOUTCLK --------------------------------   
+generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3))
+
+	begin : refclk_i
+
+	//---------- Select Reference Clock ----------------------------------------
+	BUFG refclk_i
+	(
+	
+		//---------- Input -------------------------------------
+		.I                          (CLK_CLK),
+		//---------- Output ------------------------------------
+		.O                          (refclk)
+	   
+	);
+	  
+	end
+
+else
+
+	begin : txoutclk_i
+	
+	//---------- Select TXOUTCLK -----------------------------------------------
+	BUFG txoutclk_i
+	(
+	
+		//---------- Input -------------------------------------
+		.I                          (CLK_TXOUTCLK),
+		//---------- Output ------------------------------------
+		.O                          (refclk)
+	   
+	);
+   
+	end
+
+endgenerate
+
+
+
+//---------- MMCM --------------------------------------------------------------
+MMCME2_ADV #
+(
+
+	.BANDWIDTH                  ("OPTIMIZED"),
+	.CLKOUT4_CASCADE            ("FALSE"),
+	.COMPENSATION               ("ZHOLD"),
+	.STARTUP_WAIT               ("FALSE"),
+	.DIVCLK_DIVIDE              (DIVCLK_DIVIDE),
+	.CLKFBOUT_MULT_F            (CLKFBOUT_MULT_F),  
+	.CLKFBOUT_PHASE             (0.000),
+	.CLKFBOUT_USE_FINE_PS       ("FALSE"),
+	.CLKOUT0_DIVIDE_F           (CLKOUT0_DIVIDE_F),                    
+	.CLKOUT0_PHASE              (0.000),
+	.CLKOUT0_DUTY_CYCLE         (0.500),
+	.CLKOUT0_USE_FINE_PS        ("FALSE"),
+	.CLKOUT1_DIVIDE             (CLKOUT1_DIVIDE),                    
+	.CLKOUT1_PHASE              (0.000),
+	.CLKOUT1_DUTY_CYCLE         (0.500),
+	.CLKOUT1_USE_FINE_PS        ("FALSE"),
+	.CLKOUT2_DIVIDE             (CLKOUT2_DIVIDE),                  
+	.CLKOUT2_PHASE              (0.000),
+	.CLKOUT2_DUTY_CYCLE         (0.500),
+	.CLKOUT2_USE_FINE_PS        ("FALSE"),
+	.CLKOUT3_DIVIDE             (CLKOUT3_DIVIDE),                  
+	.CLKOUT3_PHASE              (0.000),
+	.CLKOUT3_DUTY_CYCLE         (0.500),
+	.CLKOUT3_USE_FINE_PS        ("FALSE"),
+	.CLKOUT4_DIVIDE             (CLKOUT4_DIVIDE),                  
+	.CLKOUT4_PHASE              (0.000),
+	.CLKOUT4_DUTY_CYCLE         (0.500),
+	.CLKOUT4_USE_FINE_PS        ("FALSE"),
+/*	.CLKOUT5_DIVIDE             (20),                  
+	.CLKOUT5_PHASE              (0.000),
+	.CLKOUT5_DUTY_CYCLE         (0.500),
+	.CLKOUT5_USE_FINE_PS        ("FALSE"),*/
+	.CLKIN1_PERIOD              (CLKIN1_PERIOD),                   
+	.REF_JITTER1                (0.010)
+	
+)
+mmcm_i
+(
+
+	 //---------- Input ------------------------------------
+	.CLKIN1                     (refclk),
+	.CLKIN2                     (1'd0),                     // not used, comment out CLKIN2 if it cause implementation issues
+  //.CLKIN2                     (refclk),                   // not used, comment out CLKIN2 if it cause implementation issues
+	.CLKINSEL                   (1'd1),
+	.CLKFBIN                    (mmcm_fb),
+	.RST                        (!CLK_RST_N),
+	.PWRDWN                     (1'd0), 
+	
+	//---------- Output ------------------------------------
+	.CLKFBOUT                   (mmcm_fb),
+	.CLKFBOUTB                  (),
+	.CLKOUT0                    (clk_125mhz),
+	.CLKOUT0B                   (),
+	.CLKOUT1                    (clk_250mhz),
+	.CLKOUT1B                   (),
+	.CLKOUT2                    (userclk1),
+	.CLKOUT2B                   (),
+	.CLKOUT3                    (userclk2),
+	.CLKOUT3B                   (),
+	.CLKOUT4                    (oobclk),
+	.CLKOUT5                    (/*ClkUser3_o*/),
+	.CLKOUT6                    (),
+	.LOCKED                     (mmcm_lock),
+	
+	//---------- Dynamic Reconfiguration -------------------
+	.DCLK                       ( 1'd0),
+	.DADDR                      ( 7'd0),
+	.DEN                        ( 1'd0),
+	.DWE                        ( 1'd0),
+	.DI                         (16'd0),
+	.DO                         (),
+	.DRDY                       (),
+	
+	//---------- Dynamic Phase Shift -----------------------
+	.PSCLK                      (1'd0),
+	.PSEN                       (1'd0),
+	.PSINCDEC                   (1'd0),
+	.PSDONE                     (),
+	
+	//---------- Status ------------------------------------
+	.CLKINSTOPPED               (),
+	.CLKFBSTOPPED               ()  
+
+); 
+  
+
+
+//---------- Select PCLK MUX ---------------------------------------------------
+generate if (PCIE_LINK_SPEED != 1) 
+
+	begin : pclk_i1_bufgctrl
+	//---------- PCLK Mux ----------------------------------
+	BUFGCTRL pclk_i1
+	(
+		//---------- Input ---------------------------------
+		.CE0                        (1'd1),         
+		.CE1                        (1'd1),        
+		.I0                         (clk_125mhz),   
+		.I1                         (clk_250mhz),   
+		.IGNORE0                    (1'd0),        
+		.IGNORE1                    (1'd0),        
+		.S0                         (~pclk_sel),    
+		.S1                         ( pclk_sel),    
+		//---------- Output --------------------------------
+		.O                          (pclk_1)
+	);
+	end
+
+else 
+
+	//---------- Select PCLK Buffer ------------------------
+	begin : pclk_i1_bufg
+	//---------- PCLK Buffer -------------------------------
+	BUFG pclk_i1
+	(
+		//---------- Input ---------------------------------
+		.I                          (clk_125mhz), 
+		//---------- Output --------------------------------
+		.O                          (clk_125mhz_buf)
+	);
+	assign pclk_1 = clk_125mhz_buf;
+	end 
+
+endgenerate
+
+//---------- Select PCLK MUX for Slave---------------------------------------------------
+generate  if(PCIE_CLK_SHARING_EN == "FALSE")
+   //---------- PCLK MUX for Slave------------------// 
+	begin : pclk_slave_disable
+	assign CLK_PCLK_SLAVE = 1'b0;
+	end  
+
+else if (PCIE_LINK_SPEED != 1) 
+
+	begin : pclk_slave_bufgctrl
+	//---------- PCLK Mux ----------------------------------
+	BUFGCTRL pclk_slave
+	(
+		//---------- Input ---------------------------------
+		.CE0                        (1'd1),         
+		.CE1                        (1'd1),        
+		.I0                         (clk_125mhz),   
+		.I1                         (clk_250mhz),   
+		.IGNORE0                    (1'd0),        
+		.IGNORE1                    (1'd0),        
+		.S0                         (~pclk_sel_slave),    
+		.S1                         ( pclk_sel_slave),    
+		//---------- Output --------------------------------
+		.O                          (CLK_PCLK_SLAVE)
+	);
+	end
+
+else 
+
+	//---------- Select PCLK Buffer ------------------------
+	begin : pclk_slave_bufg
+	//---------- PCLK Buffer -------------------------------
+	BUFG pclk_slave
+	(
+		//---------- Input ---------------------------------
+		.I                          (clk_125mhz), 
+		//---------- Output --------------------------------
+		.O                          (CLK_PCLK_SLAVE)
+	);
+	end 
+
+endgenerate
+
+
+
+//---------- Generate RXOUTCLK Buffer for Debug --------------------------------
+generate if ((PCIE_DEBUG_MODE == 1) || (PCIE_ASYNC_EN == "TRUE"))
+		
+	begin : rxoutclk_per_lane
+	//---------- Generate per Lane -------------------------
+	for (i=0; i<PCIE_LANE; i=i+1) 
+	
+		begin : rxoutclk_i
+		//---------- RXOUTCLK Buffer -----------------------
+		BUFG rxoutclk_i
+		(
+			//---------- Input -----------------------------
+			.I                          (CLK_RXOUTCLK_IN[i]), 
+			//---------- Output ----------------------------
+			.O                          (CLK_RXOUTCLK_OUT[i])
+		);
+		end
+
+	end 
+		
+else
+
+	//---------- Disable RXOUTCLK Buffer for Normal Operation 
+	begin : rxoutclk_i_disable
+	assign CLK_RXOUTCLK_OUT = {PCIE_LANE{1'd0}};
+	end       
+			
+endgenerate 
+
+
+//---------- Generate DCLK Buffer ----------------------------------------------
+//generate if (PCIE_USERCLK2_FREQ <= 3)
+//---------- Disable DCLK Buffer -----------------------
+//    begin : dclk_i
+//    assign CLK_DCLK = userclk2_1;                       // always less than 125Mhz
+//   end
+//else
+//    begin : dclk_i_bufg
+//---------- DCLK Buffer -------------------------------
+//    BUFG dclk_i
+//    (
+//---------- Input ---------------------------------
+//        .I                          (clk_125mhz), 
+//---------- Output --------------------------------
+//        .O                          (CLK_DCLK)
+//    );
+//    end 
+//endgenerate
+
+generate if (PCIE_LINK_SPEED != 1)
+
+	begin : dclk_i_bufg
+	//---------- DCLK Buffer -------------------------------
+	BUFG dclk_i
+	(
+		//---------- Input ---------------------------------
+		.I                          (clk_125mhz),
+		//---------- Output --------------------------------
+		.O                          (CLK_DCLK)
+	);
+	end
+
+else
+
+	//---------- Disable DCLK Buffer -----------------------
+	begin : dclk_i
+	assign CLK_DCLK = clk_125mhz_buf;                       // always 125 MHz in Gen1
+	end
+
+endgenerate
+
+
+
+
+//---------- Generate USERCLK1 Buffer ------------------------------------------
+generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK1_FREQ == 3) 
+	//---------- USERCLK1 same as PCLK -------------------
+	begin :userclk1_i1_no_bufg
+	assign userclk1_1 = pclk_1;
+	end 
+else
+	begin : userclk1_i1
+	//---------- USERCLK1 Buffer ---------------------------
+	BUFG usrclk1_i1
+	(
+		//---------- Input ---------------------------------
+		.I                          (userclk1),
+		//---------- Output --------------------------------
+		.O                          (userclk1_1)
+	);
+	end 
+endgenerate 
+
+
+
+//---------- Generate USERCLK2 Buffer ------------------------------------------
+
+generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK2_FREQ == 3 ) 
+//---------- USERCLK2 same as PCLK -------------------
+	begin : userclk2_i1_no_bufg0
+	assign userclk2_1 = pclk_1;
+	end 
+else if (PCIE_USERCLK2_FREQ == PCIE_USERCLK1_FREQ ) 
+//---------- USERCLK2 same as USERCLK1 -------------------
+	begin : userclk2_i1_no_bufg1
+	assign userclk2_1 = userclk1_1;
+	end  
+else    
+	begin : userclk2_i1
+	//---------- USERCLK2 Buffer ---------------------------
+	BUFG usrclk2_i1
+	(
+		//---------- Input ---------------------------------
+		.I                          (userclk2),
+		//---------- Output --------------------------------
+		.O                          (userclk2_1)
+	);
+	end
+endgenerate 
+
+
+
+//---------- Generate OOBCLK Buffer --------------------------------------------
+generate if (PCIE_OOBCLK_MODE == 2) 
+
+	begin : oobclk_i1
+	//---------- OOBCLK Buffer -----------------------------
+	BUFG oobclk_i1
+	(
+		//---------- Input ---------------------------------
+		.I                          (oobclk),
+		//---------- Output --------------------------------
+		.O                          (CLK_OOBCLK)
+	);
+	end
+
+else 
+		
+	//---------- Disable OOBCLK Buffer ---------------------
+	begin : oobclk_i1_disable
+	assign CLK_OOBCLK = pclk;
+	end  
+
+endgenerate 
+
+
+// Disabled Second Stage Buffers
+	assign pclk         = pclk_1;
+	assign CLK_RXUSRCLK = pclk_1;
+	assign CLK_USERCLK1 = userclk1_1;
+	assign CLK_USERCLK2 = userclk2_1;
+ 
+
+
+
+//---------- Select PCLK -------------------------------------------------------
+always @ (posedge pclk)
+begin
+
+	if (!CLK_RST_N)
+		pclk_sel <= 1'd0;
+	else
+		begin 
+		//---------- Select 250 MHz ------------------------
+		if (&pclk_sel_reg2)
+			pclk_sel <= 1'd1;
+		//---------- Select 125 MHz ------------------------  
+		else if (&(~pclk_sel_reg2))
+			pclk_sel <= 1'd0;  
+		//---------- Hold PCLK -----------------------------
+		else
+			pclk_sel <= pclk_sel;
+		end
+
+end        
+
+always @ (posedge pclk)
+begin
+
+	if (!CLK_RST_N)
+		pclk_sel_slave<= 1'd0;
+	else
+		begin 
+		//---------- Select 250 MHz ------------------------
+		if (&pclk_sel_slave_reg2)
+			pclk_sel_slave <= 1'd1;
+		//---------- Select 125 MHz ------------------------  
+		else if (&(~pclk_sel_slave_reg2))
+			pclk_sel_slave <= 1'd0;  
+		//---------- Hold PCLK -----------------------------
+		else
+			pclk_sel_slave <= pclk_sel_slave;
+		end
+
+end     
+
+
+
+//---------- PIPE Clock Output -------------------------------------------------
+assign CLK_PCLK      = pclk;
+assign CLK_MMCM_LOCK = mmcm_lock;
+
+
+
+endmodule

src/src/PCIeImports/pcie1234_support.v

@@ -0,0 +1,602 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : pcie1234_support.v
+// Version    : 3.3
+//--
+//-- Description:  PCI Express Endpoint Shared Logic Wrapper
+//--
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module pcie1234_support # (
+	parameter LINK_CAP_MAX_LINK_WIDTH = 8,                       // PCIe Lane Width
+	parameter CLK_SHARING_EN          = "FALSE",                 // Enable Clock Sharing
+	parameter C_DATA_WIDTH            = 256,                     // AXI interface data width
+	parameter KEEP_WIDTH              = C_DATA_WIDTH / 8,        // TSTRB width
+	parameter PCIE_REFCLK_FREQ        = 0,                       // PCIe reference clock frequency
+	parameter PCIE_USERCLK1_FREQ      = 2,                       // PCIe user clock 1 frequency
+	parameter PCIE_USERCLK2_FREQ      = 2,                       // PCIe user clock 2 frequency
+	parameter PCIE_GT_DEVICE          = "GTX",                   // PCIe GT device
+	parameter PCIE_USE_MODE           = "2.1"                    // PCIe use mode
+)
+(
+
+	//----------------------------------------------------------------------------------------------------------------//
+	// PCI Express (pci_exp) Interface                                                                                //
+	//----------------------------------------------------------------------------------------------------------------//
+
+	// Tx
+	output  [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn,
+	output  [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp,
+
+	// Rx
+	input   [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn,
+	input   [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp,
+
+	//----------------------------------------------------------------------------------------------------------------//
+	// Clocking Sharing Interface                                                                                     //
+	//----------------------------------------------------------------------------------------------------------------//
+	output                                     pipe_pclk_out_slave,
+	output                                     pipe_rxusrclk_out,
+	output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_out,
+	output                                     pipe_dclk_out,
+	output                                     pipe_userclk1_out,
+	output                                     pipe_userclk2_out,
+	output                                     pipe_oobclk_out,
+	output                                     pipe_mmcm_lock_out,
+	input  [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_pclk_sel_slave,
+	input                                      pipe_mmcm_rst_n,
+
+	//----------------------------------------------------------------------------------------------------------------//
+	// AXI-S Interface                                                                                                //
+	//----------------------------------------------------------------------------------------------------------------//
+
+	// Common
+	output                                     user_clk_out,
+	output                                     user_reset_out,
+	output                                     user_lnk_up,
+	output                                     user_app_rdy,
+
+	input                                      tx_cfg_gnt,
+	input                                      rx_np_ok,
+	input                                      rx_np_req,
+	input                                      cfg_turnoff_ok,
+	input                                      cfg_trn_pending,
+	input                                      cfg_pm_halt_aspm_l0s,
+	input                                      cfg_pm_halt_aspm_l1,
+	input                                      cfg_pm_force_state_en,
+	input    [1:0]                             cfg_pm_force_state,
+	input    [63:0]                            cfg_dsn,
+	input                                      cfg_pm_send_pme_to,
+	input    [7:0]                             cfg_ds_bus_number,
+	input    [4:0]                             cfg_ds_device_number,
+	input    [2:0]                             cfg_ds_function_number,
+	input                                      cfg_pm_wake,
+
+	// AXI TX
+	//-----------
+	input   [C_DATA_WIDTH-1:0]                 s_axis_tx_tdata,
+	input                                      s_axis_tx_tvalid,
+	output                                     s_axis_tx_tready,
+	input   [KEEP_WIDTH-1:0]                   s_axis_tx_tkeep,
+	input                                      s_axis_tx_tlast,
+	input   [3:0]                              s_axis_tx_tuser,
+
+	// AXI RX
+	//-----------
+	output  [C_DATA_WIDTH-1:0]                 m_axis_rx_tdata,
+	output                                     m_axis_rx_tvalid,
+	input                                      m_axis_rx_tready,
+	output  [KEEP_WIDTH-1:0]                   m_axis_rx_tkeep,
+	output                                     m_axis_rx_tlast,
+	output  [21:0]                             m_axis_rx_tuser,
+
+	// Flow Control
+	output  [11:0]                             fc_cpld,
+	output  [7:0]                              fc_cplh,
+	output  [11:0]                             fc_npd,
+	output  [7:0]                              fc_nph,
+	output  [11:0]                             fc_pd,
+	output  [7:0]                              fc_ph,
+	input   [2:0]                              fc_sel,
+
+	//----------------------------------------------------------------------------------------------------------------//
+	// Configuration (CFG) Interface                                                                                  //
+	//----------------------------------------------------------------------------------------------------------------//
+	//------------------------------------------------//
+	// EP and RP                                      //
+	//------------------------------------------------//
+	output                                     tx_err_drop,
+	output                                     tx_cfg_req,
+	output  [5:0]                              tx_buf_av,
+	output   [15:0]                            cfg_status,
+	output   [15:0]                            cfg_command,
+	output   [15:0]                            cfg_dstatus,
+	output   [15:0]                            cfg_dcommand,
+	output   [15:0]                            cfg_lstatus,
+	output   [15:0]                            cfg_lcommand,
+	output   [15:0]                            cfg_dcommand2,
+	output   [2:0]                             cfg_pcie_link_state,
+	output                                     cfg_to_turnoff,
+	output   [7:0]                             cfg_bus_number,
+	output   [4:0]                             cfg_device_number,
+	output   [2:0]                             cfg_function_number,
+
+	output                                     cfg_pmcsr_pme_en,
+	output   [1:0]                             cfg_pmcsr_powerstate,
+	output                                     cfg_pmcsr_pme_status,
+	output                                     cfg_received_func_lvl_rst,
+
+	//------------------------------------------------//
+	// RP Only                                        //
+	//------------------------------------------------//
+	output                                     cfg_bridge_serr_en,
+	output                                     cfg_slot_control_electromech_il_ctl_pulse,
+	output                                     cfg_root_control_syserr_corr_err_en,
+	output                                     cfg_root_control_syserr_non_fatal_err_en,
+	output                                     cfg_root_control_syserr_fatal_err_en,
+	output                                     cfg_root_control_pme_int_en,
+	output                                     cfg_aer_rooterr_corr_err_reporting_en,
+	output                                     cfg_aer_rooterr_non_fatal_err_reporting_en,
+	output                                     cfg_aer_rooterr_fatal_err_reporting_en,
+	output                                     cfg_aer_rooterr_corr_err_received,
+	output                                     cfg_aer_rooterr_non_fatal_err_received,
+	output                                     cfg_aer_rooterr_fatal_err_received,
+	//----------------------------------------------------------------------------------------------------------------//
+	// VC interface                                                                                                   //
+	//----------------------------------------------------------------------------------------------------------------//
+
+	output   [6:0]                              cfg_vc_tcvc_map,
+
+	// Management Interface
+	output   [31:0]                             cfg_mgmt_do,
+	output                                      cfg_mgmt_rd_wr_done,
+	input    [31:0]                             cfg_mgmt_di,
+	input    [3:0]                              cfg_mgmt_byte_en,
+	input    [9:0]                              cfg_mgmt_dwaddr,
+	input                                       cfg_mgmt_wr_en,
+	input                                       cfg_mgmt_rd_en,
+	input                                       cfg_mgmt_wr_readonly,
+	input                                       cfg_mgmt_wr_rw1c_as_rw,
+
+	// Error Reporting Interface
+	input                                       cfg_err_ecrc,
+	input                                       cfg_err_ur,
+	input                                       cfg_err_cpl_timeout,
+	input                                       cfg_err_cpl_unexpect,
+	input                                       cfg_err_cpl_abort,
+	input                                       cfg_err_posted,
+	input                                       cfg_err_cor,
+	input                                       cfg_err_atomic_egress_blocked,
+	input                                       cfg_err_internal_cor,
+	input                                       cfg_err_malformed,
+	input                                       cfg_err_mc_blocked,
+	input                                       cfg_err_poisoned,
+	input                                       cfg_err_norecovery,
+	input   [47:0]                              cfg_err_tlp_cpl_header,
+	output                                      cfg_err_cpl_rdy,
+	input                                       cfg_err_locked,
+	input                                       cfg_err_acs,
+	input                                       cfg_err_internal_uncor,
+	//----------------------------------------------------------------------------------------------------------------//
+	// AER interface                                                                                                  //
+	//----------------------------------------------------------------------------------------------------------------//
+	input   [127:0]                             cfg_err_aer_headerlog,
+	input   [4:0]                               cfg_aer_interrupt_msgnum,
+	output                                      cfg_err_aer_headerlog_set,
+	output                                      cfg_aer_ecrc_check_en,
+	output                                      cfg_aer_ecrc_gen_en,
+
+	output                                      cfg_msg_received,
+	output   [15:0]                             cfg_msg_data,
+	output                                      cfg_msg_received_pm_as_nak,
+	output                                      cfg_msg_received_setslotpowerlimit,
+	output                                      cfg_msg_received_err_cor,
+	output                                      cfg_msg_received_err_non_fatal,
+	output                                      cfg_msg_received_err_fatal,
+	output                                      cfg_msg_received_pm_pme,
+	output                                      cfg_msg_received_pme_to_ack,
+	output                                      cfg_msg_received_assert_int_a,
+	output                                      cfg_msg_received_assert_int_b,
+	output                                      cfg_msg_received_assert_int_c,
+	output                                      cfg_msg_received_assert_int_d,
+	output                                      cfg_msg_received_deassert_int_a,
+	output                                      cfg_msg_received_deassert_int_b,
+	output                                      cfg_msg_received_deassert_int_c,
+	output                                      cfg_msg_received_deassert_int_d,
+
+	//------------------------------------------------//
+	// EP Only                                        //
+	//------------------------------------------------//
+	// Interrupt Interface Signals
+	input                                       cfg_interrupt,
+	output                                      cfg_interrupt_rdy,
+	input                                       cfg_interrupt_assert,
+	input    [7:0]                              cfg_interrupt_di,
+	output   [7:0]                              cfg_interrupt_do,
+	output   [2:0]                              cfg_interrupt_mmenable,
+	output                                      cfg_interrupt_msienable,
+	output                                      cfg_interrupt_msixenable,
+	output                                      cfg_interrupt_msixfm,
+	input                                       cfg_interrupt_stat,
+	input    [4:0]                              cfg_pciecap_interrupt_msgnum,
+
+	//----------------------------------------------------------------------------------------------------------------//
+	// Physical Layer Control and Status (PL) Interface                                                               //
+	//----------------------------------------------------------------------------------------------------------------//
+	//------------------------------------------------//
+	// EP and RP                                      //
+	//------------------------------------------------//
+	input    [1:0]                              pl_directed_link_change,
+	input    [1:0]                              pl_directed_link_width,
+	input                                       pl_directed_link_speed,
+	input                                       pl_directed_link_auton,
+	input                                       pl_upstream_prefer_deemph,
+ 
+	output                                      pl_sel_lnk_rate,
+	output   [1:0]                              pl_sel_lnk_width,
+	output   [5:0]                              pl_ltssm_state,
+	output   [1:0]                              pl_lane_reversal_mode,
+	output                                      pl_phy_lnk_up,
+	output   [2:0]                              pl_tx_pm_state,
+	output   [1:0]                              pl_rx_pm_state,
+	output                                      pl_link_upcfg_cap,
+	output                                      pl_link_gen2_cap,
+	output                                      pl_link_partner_gen2_supported,
+	output   [2:0]                              pl_initial_link_width,
+	output                                      pl_directed_change_done,
+
+	//------------------------------------------------//
+	// EP Only                                        //
+	//------------------------------------------------//
+	output                                      pl_received_hot_rst,
+
+	//------------------------------------------------//
+	// RP Only                                        //
+	//------------------------------------------------//
+	input                                       pl_transmit_hot_rst,
+	input                                       pl_downstream_deemph_source,
+
+	//----------------------------------------------------------------------------------------------------------------//
+	// PCIe DRP (PCIe DRP) Interface                                                                                  //
+	//----------------------------------------------------------------------------------------------------------------//
+	input                                       pcie_drp_clk,
+	input                                       pcie_drp_en,
+	input                                       pcie_drp_we,
+	input    [8:0]                              pcie_drp_addr,
+	input    [15:0]                             pcie_drp_di,
+	output                                      pcie_drp_rdy,
+	output   [15:0]                             pcie_drp_do,
+
+	input                                       sys_clk,
+	input                                       sys_rst_n,
+
+	output ClkUser3_o
+
+);
+	// Wires used for external clocking connectivity
+	wire                                        pipe_pclk_out;
+	wire                                        pipe_txoutclk_in;
+	wire [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0]    pipe_rxoutclk_in;
+	wire [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0]    pipe_pclk_sel_in;
+	wire                                        pipe_gen3_in;
+
+
+	// Wires used for external GT COMMON connectivity
+	wire [11:0]                                 qpll_drp_crscode;
+	wire [17:0]                                 qpll_drp_fsm;
+	wire [1:0]                                  qpll_drp_done;
+	wire [1:0]                                  qpll_drp_reset;
+	wire                                        qpll_qplld;
+	wire [1:0]                                  qpll_qpllreset;
+	wire                                        qpll_drp_clk;
+	wire                                        qpll_drp_rst_n;
+	wire                                        qpll_drp_ovrd;
+	wire                                        qpll_drp_gen3;
+	wire                                        qpll_drp_start;
+
+	wire clkUser3;
+	wire sysClkBufG;
+
+	BUFG BUFG_inst
+(
+	.I	(sys_clk),
+	.O	(sysClkBufG)
+);
+
+
+			//---------- PIPE Clock Shared Mode ------------------------------//
+
+pcie1234_pipe_clock #
+			(
+					.PCIE_ASYNC_EN                  ( "FALSE" ),                 // PCIe async enable
+					.PCIE_TXBUF_EN                  ( "FALSE" ),                 // PCIe TX buffer enable for Gen1/Gen2 only
+					.PCIE_LANE                      ( LINK_CAP_MAX_LINK_WIDTH ), // PCIe number of lanes
+					// synthesis translate_off
+					.PCIE_LINK_SPEED                ( 2 ),
+					// synthesis translate_on
+					.PCIE_REFCLK_FREQ               ( PCIE_REFCLK_FREQ ),        // PCIe reference clock frequency
+					.PCIE_USERCLK1_FREQ             ( PCIE_USERCLK1_FREQ ),      // PCIe user clock 1 frequency
+					.PCIE_USERCLK2_FREQ             ( PCIE_USERCLK2_FREQ ),      // PCIe user clock 2 frequency
+					.PCIE_DEBUG_MODE                ( 0 )
+			)
+			pipe_clock_i
+			(
+
+					//---------- Input -------------------------------------
+					.CLK_CLK                        ( sys_clk ),
+					.CLK_TXOUTCLK                   ( pipe_txoutclk_in ),     // Reference clock from lane 0
+					.CLK_RXOUTCLK_IN                ( pipe_rxoutclk_in ),
+					.CLK_RST_N                      ( pipe_mmcm_rst_n ),      // Allow system reset for error_recovery             
+					.CLK_PCLK_SEL                   ( pipe_pclk_sel_in ),
+					.CLK_PCLK_SEL_SLAVE             ( pipe_pclk_sel_slave),
+					.CLK_GEN3                       ( pipe_gen3_in ),
+
+					//---------- Output ------------------------------------
+					.CLK_PCLK                       ( pipe_pclk_out),
+					.CLK_PCLK_SLAVE                 ( pipe_pclk_out_slave),
+					.CLK_RXUSRCLK                   ( pipe_rxusrclk_out),
+					.CLK_RXOUTCLK_OUT               ( pipe_rxoutclk_out),
+					.CLK_DCLK                       ( pipe_dclk_out),
+					.CLK_OOBCLK                     ( pipe_oobclk_out),
+					.CLK_USERCLK1                   ( pipe_userclk1_out),
+					.CLK_USERCLK2                   ( pipe_userclk2_out),
+					.CLK_MMCM_LOCK                  ( pipe_mmcm_lock_out)
+
+					/*.ClkUser3_o (clkUser3)*/
+
+			);
+
+			ClkPllSysTo125 ClkPllSysTo125_inst
+			(
+				 .clk_out1	(ClkUser3_o),     // output clk_out1
+				 .clk_in1	(sysClkBufG)       // input clk_in1
+			);
+
+		//---------- GT COMMON Internal Mode---------------------------------------
+
+						wire [1:0]                          qpll_qplllock;
+						wire [1:0]                          qpll_qplloutclk;
+						wire [1:0]                          qpll_qplloutrefclk;
+						
+			assign qpll_drp_done                         =  2'd0;
+						assign qpll_drp_reset                        =  2'd0;
+						assign qpll_drp_crscode                      =  12'd0;
+						assign qpll_drp_fsm                          =  18'd0;
+						assign qpll_qplloutclk                       =  2'd0;
+						assign qpll_qplloutrefclk                    =  2'd0;
+						assign qpll_qplllock                         =  2'd0;
+
+
+
+pcie1234 pcie1234_i
+(
+		.pci_exp_txn(pci_exp_txn),
+		.pci_exp_txp(pci_exp_txp),
+		.pci_exp_rxn(pci_exp_rxn),
+		.pci_exp_rxp(pci_exp_rxp),
+		.pipe_pclk_in(pipe_pclk_out),
+		.pipe_rxusrclk_in(pipe_rxusrclk_out),
+		.pipe_rxoutclk_in(pipe_rxoutclk_out),
+		.pipe_mmcm_rst_n(pipe_mmcm_rst_n),
+		.pipe_dclk_in(pipe_dclk_out),
+		.pipe_userclk1_in(pipe_userclk1_out),
+		.pipe_userclk2_in(pipe_userclk2_out),
+	.pipe_oobclk_in( pipe_oobclk_out ),
+		.pipe_mmcm_lock_in(pipe_mmcm_lock_out),
+		.pipe_txoutclk_out(pipe_txoutclk_in),
+		.pipe_rxoutclk_out(pipe_rxoutclk_in),
+		.pipe_pclk_sel_out(pipe_pclk_sel_in),
+		.pipe_gen3_out(pipe_gen3_in),
+		.user_clk_out(user_clk_out),
+		.user_reset_out(user_reset_out),
+		.user_lnk_up(user_lnk_up),
+		.user_app_rdy(user_app_rdy),
+		.s_axis_tx_tdata(s_axis_tx_tdata),
+		.s_axis_tx_tvalid(s_axis_tx_tvalid),
+		.s_axis_tx_tready(s_axis_tx_tready),
+		.s_axis_tx_tkeep(s_axis_tx_tkeep),
+		.s_axis_tx_tlast(s_axis_tx_tlast),
+		.s_axis_tx_tuser(s_axis_tx_tuser),
+		.m_axis_rx_tdata(m_axis_rx_tdata),
+		.m_axis_rx_tvalid(m_axis_rx_tvalid),
+		.m_axis_rx_tready(m_axis_rx_tready),
+		.m_axis_rx_tkeep(m_axis_rx_tkeep),
+		.m_axis_rx_tlast(m_axis_rx_tlast),
+		.m_axis_rx_tuser(m_axis_rx_tuser),
+		.tx_cfg_gnt(tx_cfg_gnt),
+		.rx_np_ok(rx_np_ok),
+		.rx_np_req(rx_np_req),
+		.cfg_trn_pending(cfg_trn_pending),
+		.cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s),
+		.cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1),
+		.cfg_pm_force_state_en(cfg_pm_force_state_en),
+		.cfg_pm_force_state(cfg_pm_force_state),
+		.cfg_dsn(cfg_dsn),
+		.cfg_turnoff_ok(cfg_turnoff_ok),
+		.cfg_pm_wake(cfg_pm_wake),
+		.cfg_pm_send_pme_to(cfg_pm_send_pme_to),
+		.cfg_ds_bus_number(cfg_ds_bus_number),
+		.cfg_ds_device_number(cfg_ds_device_number),
+		.cfg_ds_function_number(cfg_ds_function_number),
+		.fc_cpld(fc_cpld),
+		.fc_cplh(fc_cplh),
+		.fc_npd(fc_npd),
+		.fc_nph(fc_nph),
+		.fc_pd(fc_pd),
+		.fc_ph(fc_ph),
+		.fc_sel(fc_sel),
+		.cfg_mgmt_do(cfg_mgmt_do),
+		.cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
+		.cfg_mgmt_di(cfg_mgmt_di),
+		.cfg_mgmt_byte_en(cfg_mgmt_byte_en),
+		.cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
+		.cfg_mgmt_wr_en(cfg_mgmt_wr_en),
+		.cfg_mgmt_rd_en(cfg_mgmt_rd_en),
+		.cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
+		.cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw),
+		.tx_buf_av(tx_buf_av),
+		.tx_err_drop(tx_err_drop),
+		.tx_cfg_req(tx_cfg_req),
+		.cfg_status(cfg_status),
+		.cfg_command(cfg_command),
+		.cfg_dstatus(cfg_dstatus),
+		.cfg_dcommand(cfg_dcommand),
+		.cfg_lstatus(cfg_lstatus),
+		.cfg_lcommand(cfg_lcommand),
+		.cfg_dcommand2(cfg_dcommand2),
+		.cfg_pcie_link_state(cfg_pcie_link_state),
+		.cfg_pmcsr_pme_en(cfg_pmcsr_pme_en),
+		.cfg_pmcsr_powerstate(cfg_pmcsr_powerstate),
+		.cfg_pmcsr_pme_status(cfg_pmcsr_pme_status),
+		.cfg_vc_tcvc_map(cfg_vc_tcvc_map),
+		.cfg_to_turnoff(cfg_to_turnoff),
+		.cfg_bus_number(cfg_bus_number),
+		.cfg_device_number(cfg_device_number),
+		.cfg_function_number(cfg_function_number),
+		.cfg_bridge_serr_en(cfg_bridge_serr_en),
+		.cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse),
+		.cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en),
+		.cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en),
+		.cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en),
+		.cfg_root_control_pme_int_en(cfg_root_control_pme_int_en),
+		.cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en),
+		.cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en),
+		.cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en),
+		.cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received),
+		.cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received),
+		.cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received),
+		.cfg_received_func_lvl_rst(cfg_received_func_lvl_rst),
+		.cfg_err_ecrc(cfg_err_ecrc),
+		.cfg_err_ur(cfg_err_ur),
+		.cfg_err_cpl_timeout(cfg_err_cpl_timeout),
+		.cfg_err_cpl_unexpect(cfg_err_cpl_unexpect),
+		.cfg_err_cpl_abort(cfg_err_cpl_abort),
+		.cfg_err_posted(cfg_err_posted),
+		.cfg_err_cor(cfg_err_cor),
+		.cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked),
+		.cfg_err_internal_cor(cfg_err_internal_cor),
+		.cfg_err_malformed(cfg_err_malformed),
+		.cfg_err_mc_blocked(cfg_err_mc_blocked),
+		.cfg_err_poisoned(cfg_err_poisoned),
+		.cfg_err_norecovery(cfg_err_norecovery),
+		.cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
+		.cfg_err_cpl_rdy(cfg_err_cpl_rdy),
+		.cfg_err_locked(cfg_err_locked),
+		.cfg_err_acs(cfg_err_acs),
+		.cfg_err_internal_uncor(cfg_err_internal_uncor),
+		.cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en),
+		.cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en),
+		.cfg_err_aer_headerlog(cfg_err_aer_headerlog),
+		.cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set),
+		.cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
+		.cfg_interrupt(cfg_interrupt),
+		.cfg_interrupt_rdy(cfg_interrupt_rdy),
+		.cfg_interrupt_assert(cfg_interrupt_assert),
+		.cfg_interrupt_di(cfg_interrupt_di),
+		.cfg_interrupt_do(cfg_interrupt_do),
+		.cfg_interrupt_mmenable(cfg_interrupt_mmenable),
+		.cfg_interrupt_msienable(cfg_interrupt_msienable),
+		.cfg_interrupt_msixenable(cfg_interrupt_msixenable),
+		.cfg_interrupt_msixfm(cfg_interrupt_msixfm),
+		.cfg_interrupt_stat(cfg_interrupt_stat),
+		.cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
+		.cfg_msg_received(cfg_msg_received),
+		.cfg_msg_data(cfg_msg_data),
+		.cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak),
+		.cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit),
+		.cfg_msg_received_err_cor(cfg_msg_received_err_cor),
+		.cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal),
+		.cfg_msg_received_err_fatal(cfg_msg_received_err_fatal),
+		.cfg_msg_received_pm_pme(cfg_msg_received_pm_pme),
+		.cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack),
+		.cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a),
+		.cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b),
+		.cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c),
+		.cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d),
+		.cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a),
+		.cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b),
+		.cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c),
+		.cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d),
+		.pl_directed_link_change(pl_directed_link_change),
+		.pl_directed_link_width(pl_directed_link_width),
+		.pl_directed_link_speed(pl_directed_link_speed),
+		.pl_directed_link_auton(pl_directed_link_auton),
+		.pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
+		.pl_sel_lnk_rate(pl_sel_lnk_rate),
+		.pl_sel_lnk_width(pl_sel_lnk_width),
+		.pl_ltssm_state(pl_ltssm_state),
+		.pl_lane_reversal_mode(pl_lane_reversal_mode),
+		.pl_phy_lnk_up(pl_phy_lnk_up),
+		.pl_tx_pm_state(pl_tx_pm_state),
+		.pl_rx_pm_state(pl_rx_pm_state),
+		.pl_link_upcfg_cap(pl_link_upcfg_cap),
+		.pl_link_gen2_cap(pl_link_gen2_cap),
+		.pl_link_partner_gen2_supported(pl_link_partner_gen2_supported),
+		.pl_initial_link_width(pl_initial_link_width),
+		.pl_directed_change_done(pl_directed_change_done),
+		.pl_received_hot_rst(pl_received_hot_rst),
+		.pl_transmit_hot_rst(pl_transmit_hot_rst),
+		.pl_downstream_deemph_source(pl_downstream_deemph_source),
+		.pcie_drp_clk(pcie_drp_clk),
+		.pcie_drp_en(pcie_drp_en),
+		.pcie_drp_we(pcie_drp_we),
+		.pcie_drp_addr(pcie_drp_addr),
+		.pcie_drp_di(pcie_drp_di),
+		.pcie_drp_rdy(pcie_drp_rdy),
+		.pcie_drp_do(pcie_drp_do),
+		.sys_clk(sys_clk),
+		.sys_rst_n(sys_rst_n)
+	);
+
+endmodule

src/src/PCIeImports/pcie_app_7x.v

@@ -0,0 +1,264 @@
+
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : pcie_app_7x.v
+// Version    : 3.3
+//--
+//-- Description:  PCI Express Endpoint sample application
+//--               design.
+//--
+//------------------------------------------------------------------------------
+
+`timescale 1ps / 1ps
+
+`define PCI_EXP_EP_OUI                           24'h000A35
+`define PCI_EXP_EP_DSN_1                         {{8'h1},`PCI_EXP_EP_OUI}
+`define PCI_EXP_EP_DSN_2                         32'h00000001
+
+module  pcie_app_7x#(
+  parameter C_DATA_WIDTH = 64,            // RX/TX interface data width
+
+  // Do not override parameters below this line
+  parameter KEEP_WIDTH = C_DATA_WIDTH / 8,              // TSTRB width
+  parameter TCQ        = 1
+)(
+
+  input                         user_clk,
+  input                         user_reset,
+  input                         user_lnk_up,
+
+  // Tx
+  input                         s_axis_tx_tready,
+  output  [C_DATA_WIDTH-1:0]    s_axis_tx_tdata,
+  output  [KEEP_WIDTH-1:0]      s_axis_tx_tkeep,
+  output  [3:0]                 s_axis_tx_tuser,
+  output                        s_axis_tx_tlast,
+  output                        s_axis_tx_tvalid,
+
+  // Rx
+  input  [C_DATA_WIDTH-1:0]     m_axis_rx_tdata,
+  input  [KEEP_WIDTH-1:0]       m_axis_rx_tkeep,
+  input                         m_axis_rx_tlast,
+  input                         m_axis_rx_tvalid,
+  output                        m_axis_rx_tready,
+  input    [21:0]               m_axis_rx_tuser,
+
+  input                         cfg_to_turnoff,
+  input   [7:0]                 cfg_bus_number,
+  input   [4:0]                 cfg_device_number,
+  input   [2:0]                 cfg_function_number,
+  output                        tx_cfg_gnt,
+  output                        cfg_pm_halt_aspm_l0s,
+  output                        cfg_pm_halt_aspm_l1,
+  output                        cfg_pm_force_state_en,
+  output [1:0]                  cfg_pm_force_state,
+  output                        rx_np_ok,
+  output                        rx_np_req,
+  output                        cfg_turnoff_ok,
+  output                        cfg_trn_pending,
+  output                        cfg_pm_wake,
+  output [63:0]                 cfg_dsn,
+  // Flow Control
+  output [2:0]                  fc_sel,
+  // CFG
+  output                        cfg_err_cor,
+  output                        cfg_err_ur,
+  output                        cfg_err_ecrc,
+  output                        cfg_err_cpl_timeout,
+  output                        cfg_err_cpl_unexpect,
+  output                        cfg_err_cpl_abort,
+  output                        cfg_err_atomic_egress_blocked,
+  output                        cfg_err_internal_cor,
+  output                        cfg_err_malformed,
+  output                        cfg_err_mc_blocked,
+  output                        cfg_err_poisoned,
+  output                        cfg_err_norecovery,
+  output                        cfg_err_acs,
+  output                        cfg_err_internal_uncor,
+  output                        cfg_err_posted,
+  output                        cfg_err_locked,
+  output [47:0]                 cfg_err_tlp_cpl_header,
+  output [127:0]                cfg_err_aer_headerlog,
+  output   [4:0]                cfg_aer_interrupt_msgnum,
+  output  [1:0]                 pl_directed_link_change,
+  output  [1:0]                 pl_directed_link_width,
+  output                        pl_directed_link_speed,
+  output                        pl_directed_link_auton,
+  output                        pl_upstream_prefer_deemph,
+  output [31:0]                 cfg_mgmt_di,
+  output  [3:0]                 cfg_mgmt_byte_en,
+  output  [9:0]                 cfg_mgmt_dwaddr,
+  output                        cfg_mgmt_wr_en,
+  output                        cfg_mgmt_rd_en,
+  output                        cfg_mgmt_wr_readonly, 
+  output                        cfg_interrupt,
+  output                        cfg_interrupt_assert,
+  output [7:0]                  cfg_interrupt_di,
+  output                        cfg_interrupt_stat,
+  output  [4:0]                 cfg_pciecap_interrupt_msgnum,
+
+  input   [63:0] MeasData_i,
+  input   MeasEnd_i,
+
+  output  StartMeasCmd_o
+);
+  //----------------------------------------------------------------------------------------------------------------//
+  // PCIe Block EP Tieoffs - Example PIO doesn't support the following inputs                                       //
+  //----------------------------------------------------------------------------------------------------------------//
+  assign fc_sel = 3'b0;
+
+  assign tx_cfg_gnt = 1'b1;                        // Always allow transmission of Config traffic within block
+  assign rx_np_ok = 1'b1;                          // Allow Reception of Non-posted Traffic
+  assign rx_np_req = 1'b1;                         // Always request Non-posted Traffic if available
+  assign cfg_pm_wake = 1'b0;                       // Never direct the core to send a PM_PME Message
+  assign cfg_trn_pending = 1'b0;                   // Never set the transaction pending bit in the Device Status Register
+  assign cfg_pm_halt_aspm_l0s = 1'b0;              // Allow entry into L0s
+  assign cfg_pm_halt_aspm_l1 = 1'b0;               // Allow entry into L1
+  assign cfg_pm_force_state_en  = 1'b0;            // Do not qualify cfg_pm_force_state
+  assign cfg_pm_force_state  = 2'b00;              // Do not move force core into specific PM state
+  assign cfg_dsn = {`PCI_EXP_EP_DSN_2, `PCI_EXP_EP_DSN_1};  // Assign the input DSN
+  assign s_axis_tx_tuser[0] = 1'b0;                // Unused for V6
+  assign s_axis_tx_tuser[1] = 1'b0;                // Error forward packet
+  assign s_axis_tx_tuser[2] = 1'b0;                // Stream packet
+
+  assign cfg_err_cor = 1'b0;                       // Never report Correctable Error
+  assign cfg_err_ur = 1'b0;                        // Never report UR
+  assign cfg_err_ecrc = 1'b0;                      // Never report ECRC Error
+  assign cfg_err_cpl_timeout = 1'b0;               // Never report Completion Timeout
+  assign cfg_err_cpl_abort = 1'b0;                 // Never report Completion Abort
+  assign cfg_err_cpl_unexpect = 1'b0;              // Never report unexpected completion
+  assign cfg_err_posted = 1'b0;                    // Never qualify cfg_err_* inputs
+  assign cfg_err_locked = 1'b0;                    // Never qualify cfg_err_ur or cfg_err_cpl_abort
+  assign cfg_err_atomic_egress_blocked = 1'b0;     // Never report Atomic TLP blocked
+  assign cfg_err_internal_cor = 1'b0;              // Never report internal error occurred
+  assign cfg_err_malformed = 1'b0;                 // Never report malformed error
+  assign cfg_err_mc_blocked = 1'b0;                // Never report multi-cast TLP blocked
+  assign cfg_err_poisoned = 1'b0;                  // Never report poisoned TLP received
+  assign cfg_err_norecovery = 1'b0;                // Never qualify cfg_err_poisoned or cfg_err_cpl_timeout
+  assign cfg_err_acs = 1'b0;                       // Never report an ACS violation
+  assign cfg_err_internal_uncor = 1'b0;            // Never report internal uncorrectable error
+  assign cfg_err_aer_headerlog = 128'h0;           // Zero out the AER Header Log
+  assign cfg_aer_interrupt_msgnum = 5'b00000;      // Zero out the AER Root Error Status Register
+  assign cfg_err_tlp_cpl_header = 48'h0;           // Zero out the header information
+
+  assign cfg_interrupt_stat = 1'b0;                // Never set the Interrupt Status bit
+  assign cfg_pciecap_interrupt_msgnum = 5'b00000;  // Zero out Interrupt Message Number
+  assign cfg_interrupt_assert = 1'b0;              // Always drive interrupt de-assert
+  assign cfg_interrupt = 1'b0;                     // Never drive interrupt by qualifying cfg_interrupt_assert
+  assign cfg_interrupt_di = 8'b0;                  // Do not set interrupt fields
+
+  assign pl_directed_link_change = 2'b00;          // Never initiate link change
+  assign pl_directed_link_width = 2'b00;          // Zero out directed link width
+  assign pl_directed_link_speed = 1'b0;            // Zero out directed link speed
+  assign pl_directed_link_auton = 1'b0;            // Zero out link autonomous input
+  assign pl_upstream_prefer_deemph = 1'b1;         // Zero out preferred de-emphasis of upstream port
+
+  assign cfg_mgmt_di = 32'h0;                      // Zero out CFG MGMT input data bus
+  assign cfg_mgmt_byte_en = 4'h0;                  // Zero out CFG MGMT byte enables
+  assign cfg_mgmt_dwaddr = 10'h0;                  // Zero out CFG MGMT 10-bit address port
+  assign cfg_mgmt_wr_en = 1'b0;                    // Do not write CFG space
+  assign cfg_mgmt_rd_en = 1'b0;                    // Do not read CFG space
+  assign cfg_mgmt_wr_readonly = 1'b0;              // Never treat RO bit as RW
+  //----------------------------------------------------------------------------------------------------------------//
+  // Programmable I/O Module                                                                                        //
+  //----------------------------------------------------------------------------------------------------------------//
+
+  wire [15:0] cfg_completer_id      = { cfg_bus_number, cfg_device_number, cfg_function_number };
+//  reg         s_axis_tx_tready_i ;
+//  always @(posedge user_clk)
+//  begin
+//   if (user_reset)
+//      s_axis_tx_tready_i <= #TCQ 1'b0;
+//   else
+//      s_axis_tx_tready_i <= #TCQ s_axis_tx_tready;
+//  end
+  wire  s_axis_tx_tready_i ;
+  assign s_axis_tx_tready_i = s_axis_tx_tready;
+
+  //----------------------------------------------------------------------------------------------------------------//
+
+  PIO  #(
+
+    .C_DATA_WIDTH( C_DATA_WIDTH ),
+    .KEEP_WIDTH( KEEP_WIDTH ),
+    .TCQ( TCQ )
+
+  ) PIO (
+
+    .user_clk ( user_clk ),                         // I
+    .user_reset ( user_reset ),                     // I
+    .user_lnk_up ( user_lnk_up ),                   // I
+
+    .cfg_to_turnoff ( cfg_to_turnoff ),             // I
+    .cfg_completer_id ( cfg_completer_id ),         // I [15:0]
+    .cfg_turnoff_ok ( cfg_turnoff_ok ),             // O
+
+    .s_axis_tx_tready ( s_axis_tx_tready_i ),       // I
+    .s_axis_tx_tdata  ( s_axis_tx_tdata ),          // O
+    .s_axis_tx_tkeep  ( s_axis_tx_tkeep ),          // O
+    .s_axis_tx_tlast  ( s_axis_tx_tlast ),          // O
+    .s_axis_tx_tvalid ( s_axis_tx_tvalid ),         // O
+    .tx_src_dsc       ( s_axis_tx_tuser[3] ),       // O
+
+    .m_axis_rx_tdata ( m_axis_rx_tdata ),           // I
+    .m_axis_rx_tkeep ( m_axis_rx_tkeep ),           // I
+    .m_axis_rx_tlast ( m_axis_rx_tlast ),           // I
+    .m_axis_rx_tvalid( m_axis_rx_tvalid ),          // I
+    .m_axis_rx_tready( m_axis_rx_tready ),          // O
+    .m_axis_rx_tuser ( m_axis_rx_tuser ),            // I
+
+    .MeasData_i(MeasData_i),
+    .MeasEnd_i(MeasEnd_i),
+
+    .StartMeasCmd_o(StartMeasCmd_o)
+  );
+
+endmodule // pcie_app

src/src/PCIeImports/pcie_axi_trn_bridge.v

@@ -0,0 +1,289 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : pcie_axi_trn_bridge.v
+// Version    : 3.3
+//
+//     Description : AXI - TRN Bridge for Root Port Model. 
+//                   Root Port Usrapp's require TRN interface.
+//-----------------------------------------------------------------------
+
+`timescale 1ns/1ns
+
+module pcie_axi_trn_bridge # (
+  parameter         C_DATA_WIDTH = 64,
+  parameter         RBAR_WIDTH = 7,
+  parameter         KEEP_WIDTH = C_DATA_WIDTH / 8,
+  parameter         REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1
+)
+(
+
+    // Common
+  input                       user_clk,
+  input                       user_reset,
+  input                       user_lnk_up,
+
+  // AXI TX
+  //-----------
+  output   [C_DATA_WIDTH-1:0] s_axis_tx_tdata,        // TX data from user
+  output                      s_axis_tx_tvalid,       // TX data is valid
+  input                       s_axis_tx_tready,       // TX ready for data
+  output     [KEEP_WIDTH-1:0] s_axis_tx_tkeep,        // TX strobe byte enables
+  output                      s_axis_tx_tlast,        // TX data is last
+  output                [3:0] s_axis_tx_tuser,        // TX user signals
+
+  // AXI RX
+  //-----------
+  input  [C_DATA_WIDTH-1:0]   m_axis_rx_tdata,        // RX data to user
+  input                       m_axis_rx_tvalid,       // RX data is valid
+  output                      m_axis_rx_tready,       // RX ready for data
+  input    [KEEP_WIDTH-1:0]   m_axis_rx_tkeep,        // RX strobe byte enables
+  input                       m_axis_rx_tlast,        // RX data is last
+  input              [21:0]   m_axis_rx_tuser,        // RX user signals
+
+  //---------------------------------------------//
+  // PCIe Usrapp I/O                             //
+  //---------------------------------------------//
+
+  // TRN TX
+  //-----------
+  input [C_DATA_WIDTH-1:0]    trn_td,                  // TX data from usrapp
+  input                       trn_tsof,                // TX start of packet
+  input                       trn_teof,                // TX end of packet
+  input                       trn_tsrc_rdy,            // TX source ready
+  output                      trn_tdst_rdy,            // TX destination ready
+  input                       trn_tsrc_dsc,            // TX source discontinue
+  input    [REM_WIDTH-1:0]    trn_trem,                // TX remainder
+  input                       trn_terrfwd,             // TX error forward
+  input                       trn_tstr,                // TX streaming enable
+  input                       trn_tecrc_gen,           // TX ECRC generate
+
+  // TRN RX
+  //-----------
+  output  [C_DATA_WIDTH-1:0]  trn_rd,                  // RX data to usrapp
+  output                      trn_rsof,                // RX start of packet
+  output                      trn_reof,                // RX end of packet
+  output                      trn_rsrc_rdy,            // RX source ready
+  input                       trn_rdst_rdy,            // RX destination ready
+  output reg                  trn_rsrc_dsc,            // RX source discontinue
+  output     [REM_WIDTH-1:0]  trn_rrem,                // RX remainder
+  output wire                 trn_rerrfwd,             // RX error forward
+  output    [RBAR_WIDTH-1:0]  trn_rbar_hit             // RX BAR hit
+
+ );
+
+//DWORD Reordering between AXI and TRN interface//
+
+generate begin:gen_axis_txdata
+  if (C_DATA_WIDTH == 64)
+  begin 
+    assign s_axis_tx_tdata = {trn_td[31:0],trn_td[63:32]};
+  end
+  else if (C_DATA_WIDTH == 128)
+  begin
+    assign s_axis_tx_tdata = {trn_td[31:0],trn_td[63:32],trn_td[95:64],trn_td[127:96]};
+  end
+end
+endgenerate
+
+//Coversion from trn_rem to s_axis_tkeep[7:0]//
+
+generate begin: gen_axis_tx_tkeep
+if (C_DATA_WIDTH == 64)
+begin
+   
+  assign s_axis_tx_tkeep = (trn_teof && ~trn_trem) ? 8'h0F : 8'hFF;
+//  always @*
+//  begin
+//    if (trn_teof && ~trn_trem)  begin
+//        s_axis_tx_tkeep <= 8'h0F;
+//    end else begin
+//        s_axis_tx_tkeep <= 8'hFF;
+//    end
+//  end
+end
+
+else if (C_DATA_WIDTH == 128)
+begin
+
+  assign s_axis_tx_tkeep = (trn_teof) ? ((trn_trem == 2'b11) ? 16'hFFFF :
+                                         ((trn_trem == 2'b10) ? 16'h0FFF :
+                                         ((trn_trem == 2'b01) ? 16'h00FF : 16'h000F ))) :
+                                        16'hFFFF;
+//  always @*
+//  begin
+//    if (trn_teof)
+//    begin
+//      case (trn_trem)
+//        2'b11: begin s_axis_tx_tkeep <= 16'hFFFF; end
+//        2'b10: begin s_axis_tx_tkeep <= 16'h0FFF; end
+//        2'b01: begin s_axis_tx_tkeep <= 16'h00FF; end
+//        2'b00: begin s_axis_tx_tkeep <= 16'h000F; end
+//      endcase
+//    end
+//    else
+//    begin
+//        s_axis_tx_tkeep <= 16'hFFFF;
+//    end
+//  end
+end
+end
+endgenerate
+
+//Connection of s_axis_tx_tuser with  trn_tsrc_dsc,trn_tstr,trn_terr_fwd and trn_terr_fwd
+assign s_axis_tx_tuser [3] = trn_tsrc_dsc; 
+assign s_axis_tx_tuser [2] = trn_tstr;
+assign s_axis_tx_tuser [1] = trn_terrfwd;
+assign s_axis_tx_tuser [0] = trn_tecrc_gen;
+
+//Constraint trn_tsrc_rdy. If constrained, testbench keep trn_tsrc_rdy constantly asserted. This makes axi bridge to generate trn_tsof immeditely after trn_teof of previous packet.//
+reg trn_tsrc_rdy_derived = 1'b0;
+always @*
+begin
+  if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof) 
+  begin
+    trn_tsrc_rdy_derived <= 1'b1;
+  end
+  else if(trn_tsrc_rdy_derived && trn_teof && trn_tsrc_rdy && trn_tdst_rdy) 
+  begin
+    trn_tsrc_rdy_derived <= 1'b0;
+  end
+end
+
+assign s_axis_tx_tvalid = trn_tsrc_rdy_derived || trn_tsof || trn_teof;
+
+assign trn_tdst_rdy = s_axis_tx_tready;
+
+assign s_axis_tx_tlast = trn_teof;
+
+assign m_axis_rx_tready = trn_rdst_rdy;
+
+generate begin:gen_trn_rd
+if (C_DATA_WIDTH == 64) begin 
+    assign trn_rd = {m_axis_rx_tdata[31:0],m_axis_rx_tdata[63:32]};
+end else if (C_DATA_WIDTH == 128) begin
+  assign trn_rd = {m_axis_rx_tdata[31:0],m_axis_rx_tdata [63:32],m_axis_rx_tdata [95:64],m_axis_rx_tdata [127:96]};
+end
+end
+endgenerate
+
+//Regenerate trn_rsof
+//Used clock. Latency may have been added
+
+reg in_packet_reg;
+generate begin:gen_trn_rsof 
+if (C_DATA_WIDTH == 64)
+begin
+  always @(posedge user_clk)
+  begin
+    if (user_reset)
+      in_packet_reg <= 1'b0;
+    else if (m_axis_rx_tvalid && m_axis_rx_tready)
+      in_packet_reg <= ~m_axis_rx_tlast;
+  end
+  assign trn_rsof = m_axis_rx_tvalid & ~in_packet_reg;
+end
+else if (C_DATA_WIDTH == 128)
+begin
+  assign trn_rsof = m_axis_rx_tuser [14];
+end
+end
+endgenerate
+
+generate begin: gen_trn_reof
+if (C_DATA_WIDTH == 64)
+begin
+  assign trn_reof = m_axis_rx_tlast;
+end
+else if (C_DATA_WIDTH == 128)
+begin
+  assign trn_reof = m_axis_rx_tuser[21]; //is_eof[4];
+end
+end
+endgenerate
+
+assign trn_rsrc_rdy = m_axis_rx_tvalid;
+
+//Regenerate trn_rsrc_dsc
+//Used clock. Latency may have been added
+always @(posedge user_clk)
+begin
+  if (user_reset)
+    trn_rsrc_dsc <= 1'b1;
+  else
+    trn_rsrc_dsc <= ~user_lnk_up;
+end
+
+wire [4:0] is_sof;
+wire [4:0] is_eof;
+
+assign is_sof = m_axis_rx_tuser[14:10];
+assign is_eof = m_axis_rx_tuser[21:17];
+
+generate begin:gen_trn_rrem
+if (C_DATA_WIDTH == 64)
+begin
+  assign trn_rrem = m_axis_rx_tlast ? (m_axis_rx_tkeep == 8'hFF) ? 1'b1 : 1'b0: 1'b1;
+end
+else if (C_DATA_WIDTH == 128)
+begin
+  assign trn_rrem[0] = is_eof[2];
+  assign trn_rrem[1] = (is_eof[4] || is_sof[4] )  ?  ( (is_sof[4] && is_eof[4] && is_eof[3]) || (!is_sof[4] && is_eof[4] && is_eof[3]) || (is_sof[4] && !is_eof[4] && !is_sof[3]) )  :   1'b1;
+end
+end
+endgenerate
+
+assign trn_rerrfwd = m_axis_rx_tuser[1];
+
+assign trn_rbar_hit = m_axis_rx_tuser[8:2];
+
+
+endmodule 
+

src/src/PCIeImports/pipe_interconnect.vh

@@ -0,0 +1,98 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : pipe_interconnect.vh
+// Version    : 3.3
+
+`define EP  board.EP.pcie1234_support.pcie1234_i.inst.inst.pcie_top_i
+`define RP board.RP.rport.pcie_top_i
+
+//----------------------------------------------------------  PIO RTL & RP simulation  -------------------------------------------------------------------//  
+generate
+ if (PIPE_SIM == "TRUE")
+  begin
+   assign `EP.pipe_rx0_char_is_k_gt = `RP.pipe_tx0_char_is_k_gt;   
+   assign `EP.pipe_rx1_char_is_k_gt = `RP.pipe_tx1_char_is_k_gt;   
+   assign `EP.pipe_rx2_char_is_k_gt = `RP.pipe_tx2_char_is_k_gt;   
+   assign `EP.pipe_rx3_char_is_k_gt = `RP.pipe_tx3_char_is_k_gt;   
+   assign `EP.pipe_rx4_char_is_k_gt = `RP.pipe_tx4_char_is_k_gt;   
+   assign `EP.pipe_rx5_char_is_k_gt = `RP.pipe_tx5_char_is_k_gt;   
+   assign `EP.pipe_rx6_char_is_k_gt = `RP.pipe_tx6_char_is_k_gt;   
+   assign `EP.pipe_rx7_char_is_k_gt = `RP.pipe_tx7_char_is_k_gt;   
+
+   assign `EP.pipe_rx0_data_gt      = `RP.pipe_tx0_data_gt;   
+   assign `EP.pipe_rx1_data_gt      = `RP.pipe_tx1_data_gt;   
+   assign `EP.pipe_rx2_data_gt      = `RP.pipe_tx2_data_gt;   
+   assign `EP.pipe_rx3_data_gt      = `RP.pipe_tx3_data_gt;   
+   assign `EP.pipe_rx4_data_gt      = `RP.pipe_tx4_data_gt;   
+   assign `EP.pipe_rx5_data_gt      = `RP.pipe_tx5_data_gt;   
+   assign `EP.pipe_rx6_data_gt      = `RP.pipe_tx6_data_gt;   
+   assign `EP.pipe_rx7_data_gt      = `RP.pipe_tx7_data_gt; 
+//-------------------------------------------------------------------------------------------------------------------------//  
+   assign `RP.pipe_rx0_char_is_k_gt = `EP.pipe_tx0_char_is_k_gt;   
+   assign `RP.pipe_rx1_char_is_k_gt = `EP.pipe_tx1_char_is_k_gt;   
+   assign `RP.pipe_rx2_char_is_k_gt = `EP.pipe_tx2_char_is_k_gt;   
+   assign `RP.pipe_rx3_char_is_k_gt = `EP.pipe_tx3_char_is_k_gt;   
+   assign `RP.pipe_rx4_char_is_k_gt = `EP.pipe_tx4_char_is_k_gt;   
+   assign `RP.pipe_rx5_char_is_k_gt = `EP.pipe_tx5_char_is_k_gt;   
+   assign `RP.pipe_rx6_char_is_k_gt = `EP.pipe_tx6_char_is_k_gt;   
+   assign `RP.pipe_rx7_char_is_k_gt = `EP.pipe_tx7_char_is_k_gt;   
+
+   assign `RP.pipe_rx0_data_gt      = `EP.pipe_tx0_data_gt;
+   assign `RP.pipe_rx1_data_gt      = `EP.pipe_tx1_data_gt;
+   assign `RP.pipe_rx2_data_gt      = `EP.pipe_tx2_data_gt;
+   assign `RP.pipe_rx3_data_gt      = `EP.pipe_tx3_data_gt;
+   assign `RP.pipe_rx4_data_gt      = `EP.pipe_tx4_data_gt;
+   assign `RP.pipe_rx5_data_gt      = `EP.pipe_tx5_data_gt;
+   assign `RP.pipe_rx6_data_gt      = `EP.pipe_tx6_data_gt;
+   assign `RP.pipe_rx7_data_gt      = `EP.pipe_tx7_data_gt;
+  end
+ endgenerate
+//----------------------------------------------------------------------------------------------------------------------------------------------------------//  

src/src/PCIeImports/sample_tests1.vh

@@ -0,0 +1,345 @@
+
+else if(testname == "sample_smoke_test0")
+begin
+
+
+    TSK_SIMULATION_TIMEOUT(5050);
+
+    //System Initialization
+    TSK_SYSTEM_INITIALIZATION;
+
+
+
+
+    
+    $display("[%t] : Expected Device/Vendor ID = %x", $realtime, DEV_VEN_ID); 
+    
+    //--------------------------------------------------------------------------
+    // Read core configuration space via PCIe fabric interface
+    //--------------------------------------------------------------------------
+
+    $display("[%t] : Reading from PCI/PCI-Express Configuration Register 0x00", $realtime);
+
+    TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h0, 4'hF);
+    TSK_WAIT_FOR_READ_DATA;
+    if  (P_READ_DATA != DEV_VEN_ID) begin
+        $display("[%t] : TEST FAILED --- Data Error Mismatch, Write Data %x != Read Data %x", $realtime, 
+                                    DEV_VEN_ID, P_READ_DATA);
+    end
+    else begin
+        $display("[%t] : TEST PASSED --- Device/Vendor ID %x successfully received", $realtime, P_READ_DATA);
+        $display("Test Completed Successfully");
+    end
+
+    //--------------------------------------------------------------------------
+    // Direct Root Port to allow upstream traffic by enabling Mem, I/O and
+    // BusMstr in the command register
+    //--------------------------------------------------------------------------
+
+    board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);
+    board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000001, 32'h00000007, 4'b1110);
+    board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);
+
+  $finish;
+end
+
+
+else if(testname == "sample_smoke_test1")
+begin
+
+    // This test use tlp expectation tasks.
+
+    TSK_SIMULATION_TIMEOUT(5050);
+
+    //System Initialization
+    TSK_SYSTEM_INITIALIZATION;
+
+fork
+  begin
+    //--------------------------------------------------------------------------
+    // Read core configuration space via PCIe fabric interface
+    //--------------------------------------------------------------------------
+
+    $display("[%t] : Reading from PCI/PCI-Express Configuration Register 0x00", $realtime);
+
+    TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h0, 4'hF);
+    DEFAULT_TAG = DEFAULT_TAG + 1;
+    TSK_TX_CLK_EAT(100);
+  end
+    //---------------------------------------------------------------------------
+    // List Rx TLP expections
+    //---------------------------------------------------------------------------
+  begin
+    test_vars[0] = 0;                                                                                                                         
+                                          
+    $display("[%t] : Expected Device/Vendor ID = %x", $realtime, DEV_VEN_ID);                                              
+
+    expect_cpld_payload[0] = DEV_VEN_ID[7:0]; 
+    expect_cpld_payload[1] = DEV_VEN_ID[15:8]; 
+    expect_cpld_payload[2] = DEV_VEN_ID[23:16]; 
+    expect_cpld_payload[3] = DEV_VEN_ID[31:24]; 
+    board.RP.com_usrapp.TSK_EXPECT_CPLD(
+      3'h0, //traffic_class;
+      1'b0, //td;
+      1'b0, //ep;
+      2'h0, //attr;
+      10'h1, //length;
+      16'h0000, //completer_id;
+      3'h0, //completion_status;
+      1'b0, //bcm;
+      12'h4, //byte_count;
+      16'h01a0, //requester_id;
+      8'h0, //tag;
+      7'b0, //address_low;
+      expect_status //expect_status;
+    );
+
+    if (expect_status) 
+      test_vars[0] = test_vars[0] + 1;      
+  end
+join
+  
+  expect_finish_check = 1;
+
+  if (test_vars[0] == 1) begin
+    $display("[%t] : TEST PASSED --- Finished transmission of PCI-Express TLPs", $realtime);
+    $display ("Test Completed Successfully");
+  end
+  else begin
+    $display("[%t] : TEST FAILED --- Haven't Received All Expected TLPs", $realtime);
+
+    //--------------------------------------------------------------------------
+    // Direct Root Port to allow upstream traffic by enabling Mem, I/O and
+    // BusMstr in the command register
+    //--------------------------------------------------------------------------
+
+    board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);
+    board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000001, 32'h00000007, 4'b1110);
+    board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);
+
+  end
+
+  $finish;
+end
+
+else if(testname == "pio_writeReadBack_test0")
+begin
+
+    // This test performs a 32 bit write to a 32 bit Memory space and performs a read back
+
+    board.RP.tx_usrapp.TSK_SIMULATION_TIMEOUT(10050);
+
+    board.RP.tx_usrapp.TSK_SYSTEM_INITIALIZATION;
+
+    board.RP.tx_usrapp.TSK_BAR_INIT;
+
+//--------------------------------------------------------------------------
+// Event : Testing BARs
+//--------------------------------------------------------------------------
+
+        for (board.RP.tx_usrapp.ii = 0; board.RP.tx_usrapp.ii <= 6; board.RP.tx_usrapp.ii =
+            board.RP.tx_usrapp.ii + 1) begin
+            if (board.RP.tx_usrapp.BAR_INIT_P_BAR_ENABLED[board.RP.tx_usrapp.ii] > 2'b00) // bar is enabled
+               case(board.RP.tx_usrapp.BAR_INIT_P_BAR_ENABLED[board.RP.tx_usrapp.ii])
+                   2'b01 : // IO SPACE
+                        begin
+
+                          $display("[%t] : Transmitting TLPs to IO Space BAR %x", $realtime, board.RP.tx_usrapp.ii);
+
+                          //--------------------------------------------------------------------------
+                          // Event : IO Write bit TLP
+                          //--------------------------------------------------------------------------
+
+
+
+                          board.RP.tx_usrapp.TSK_TX_IO_WRITE(board.RP.tx_usrapp.DEFAULT_TAG,
+                             board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0], 4'hF, 32'hdead_beef);
+
+                          board.RP.com_usrapp.TSK_EXPECT_CPL(3'h0, 1'b0, 1'b0, 2'b0,
+                             board.RP.tx_usrapp.COMPLETER_ID_CFG, 3'h0, 1'b0, 12'h4,
+                             board.RP.tx_usrapp.COMPLETER_ID_CFG, board.RP.tx_usrapp.DEFAULT_TAG,
+                             board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0], test_vars[0]);
+
+                          board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
+                          board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
+
+                          //--------------------------------------------------------------------------
+                          // Event : IO Read bit TLP
+                          //--------------------------------------------------------------------------
+
+
+                          // make sure P_READ_DATA has known initial value
+                          board.RP.tx_usrapp.P_READ_DATA = 32'hffff_ffff;
+                          fork
+                             board.RP.tx_usrapp.TSK_TX_IO_READ(board.RP.tx_usrapp.DEFAULT_TAG,
+                                board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0], 4'hF);
+                             board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA;
+                          join
+                          if  (board.RP.tx_usrapp.P_READ_DATA != 32'hdead_beef)
+                             begin
+                               $display("[%t] : Test FAILED --- Data Error Mismatch, Write Data %x != Read Data %x",
+                                   $realtime, 32'hdead_beef, board.RP.tx_usrapp.P_READ_DATA);
+                               test_failed_flag = 1;
+                             end
+                          else
+                             begin
+                               $display("[%t] : Test PASSED --- Write Data: %x successfully received",
+                                   $realtime, board.RP.tx_usrapp.P_READ_DATA);
+                             end
+
+
+                          board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
+                          board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
+
+
+                        end
+
+                   2'b10 : // MEM 32 SPACE
+                        begin
+
+
+                          $display("[%t] : Transmitting TLPs to Memory 32 Space BAR %x", $realtime,
+                              board.RP.tx_usrapp.ii);
+
+                          //--------------------------------------------------------------------------
+                          // Event : Memory Write 32 bit TLP
+                          //--------------------------------------------------------------------------
+
+                          board.RP.tx_usrapp.DATA_STORE[0] = 8'h04;
+                          board.RP.tx_usrapp.DATA_STORE[1] = 8'h03;
+                          board.RP.tx_usrapp.DATA_STORE[2] = 8'h02;
+                          board.RP.tx_usrapp.DATA_STORE[3] = 8'h01;
+
+                          board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_32(board.RP.tx_usrapp.DEFAULT_TAG,
+                              board.RP.tx_usrapp.DEFAULT_TC, 10'd1,
+                              board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h14, 4'h0, 4'hF, 1'b0);
+                          board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
+                          board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
+
+
+
+
+
+                          board.RP.tx_usrapp.DATA_STORE[0] = 8'h05;
+                          board.RP.tx_usrapp.DATA_STORE[1] = 8'h06;
+                          board.RP.tx_usrapp.DATA_STORE[2] = 8'h07;
+                          board.RP.tx_usrapp.DATA_STORE[3] = 8'h08;
+
+                          board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_32(board.RP.tx_usrapp.DEFAULT_TAG,
+                              board.RP.tx_usrapp.DEFAULT_TC, 10'd1,
+                              board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h14, 4'h0, 4'hF, 1'b0);
+                          board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
+                          board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
+
+
+
+                          
+
+                          //--------------------------------------------------------------------------
+                          // Event : Memory Read 32 bit TLP
+                          //--------------------------------------------------------------------------
+
+
+                         // make sure P_READ_DATA has known initial value
+                         board.RP.tx_usrapp.P_READ_DATA = 32'hffff_ffff;
+                          fork
+                             board.RP.tx_usrapp.TSK_TX_MEMORY_READ_32(board.RP.tx_usrapp.DEFAULT_TAG,
+                                 board.RP.tx_usrapp.DEFAULT_TC, 10'd1,
+                                 board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h14, 4'h0, 4'hF);
+                             board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA;
+                          join
+                          if  (board.RP.tx_usrapp.P_READ_DATA != {board.RP.tx_usrapp.DATA_STORE[3],
+                             board.RP.tx_usrapp.DATA_STORE[2], board.RP.tx_usrapp.DATA_STORE[1],
+                             board.RP.tx_usrapp.DATA_STORE[0] })
+                             begin
+                               $display("[%t] : Test FAILED --- Data Error Mismatch, Write Data %x != Read Data %x",
+                                    $realtime, {board.RP.tx_usrapp.DATA_STORE[3],board.RP.tx_usrapp.DATA_STORE[2],
+                                     board.RP.tx_usrapp.DATA_STORE[1],board.RP.tx_usrapp.DATA_STORE[0]},
+                                     board.RP.tx_usrapp.P_READ_DATA);
+                               test_failed_flag = 1;
+
+                             end
+                          else
+                             begin
+                               $display("[%t] : Test PASSED --- Write Data: %x successfully received",
+                                   $realtime, board.RP.tx_usrapp.P_READ_DATA);
+                             end
+
+
+                          board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
+                          board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
+
+                     end
+                2'b11 : // MEM 64 SPACE
+                     begin
+
+
+                          $display("[%t] : Transmitting TLPs to Memory 64 Space BAR %x", $realtime,
+                              board.RP.tx_usrapp.ii);
+
+
+                          //--------------------------------------------------------------------------
+                          // Event : Memory Write 64 bit TLP
+                          //--------------------------------------------------------------------------
+
+                          board.RP.tx_usrapp.DATA_STORE[0] = 8'h64;
+                          board.RP.tx_usrapp.DATA_STORE[1] = 8'h63;
+                          board.RP.tx_usrapp.DATA_STORE[2] = 8'h62;
+                          board.RP.tx_usrapp.DATA_STORE[3] = 8'h61;
+
+                          board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_64(board.RP.tx_usrapp.DEFAULT_TAG,
+                              board.RP.tx_usrapp.DEFAULT_TC, 10'd1,
+                              {board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii+1][31:0],
+                              board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h20}, 4'h0, 4'hF, 1'b0);
+                          board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
+                          board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
+
+                          //--------------------------------------------------------------------------
+                          // Event : Memory Read 64 bit TLP
+                          //--------------------------------------------------------------------------
+
+
+                          // make sure P_READ_DATA has known initial value
+                          board.RP.tx_usrapp.P_READ_DATA = 32'hffff_ffff;
+                          fork
+                             board.RP.tx_usrapp.TSK_TX_MEMORY_READ_64(board.RP.tx_usrapp.DEFAULT_TAG,
+                                 board.RP.tx_usrapp.DEFAULT_TC, 10'd1,
+                                 {board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii+1][31:0],
+                                 board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h20}, 4'h0, 4'hF);
+                             board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA;
+                          join
+                          if  (board.RP.tx_usrapp.P_READ_DATA != {board.RP.tx_usrapp.DATA_STORE[3],
+                             board.RP.tx_usrapp.DATA_STORE[2], board.RP.tx_usrapp.DATA_STORE[1],
+                             board.RP.tx_usrapp.DATA_STORE[0] })
+
+                             begin
+                               $display("[%t] : Test FAILED --- Data Error Mismatch, Write Data %x != Read Data %x",
+                                   $realtime, {board.RP.tx_usrapp.DATA_STORE[3],
+                                   board.RP.tx_usrapp.DATA_STORE[2], board.RP.tx_usrapp.DATA_STORE[1],
+                                   board.RP.tx_usrapp.DATA_STORE[0]}, board.RP.tx_usrapp.P_READ_DATA);
+                               test_failed_flag = 1;
+                             end
+                          else
+                             begin
+                               $display("[%t] : Test PASSED --- Write Data: %x successfully received",
+                                   $realtime, board.RP.tx_usrapp.P_READ_DATA);
+                             end
+
+
+                          board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
+                          board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
+
+
+                     end
+                default : $display("Error case in usrapp_tx\n");
+            endcase
+
+         end
+
+
+    $display("[%t] : Finished transmission of PCI-Express TLPs", $realtime);
+    if (!test_failed_flag) begin 
+       $display ("Test Completed Successfully");
+    end 
+    $finish;
+end

src/src/PCIeImports/sys_clk_gen.v

@@ -0,0 +1,75 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : sys_clk_gen.v
+// Version    : 3.3
+//--
+//--------------------------------------------------------------------------------
+`timescale 1ps/1ps
+
+module sys_clk_gen (sys_clk);
+
+output	sys_clk;
+
+reg		sys_clk;
+
+parameter        offset = 0;
+parameter        halfcycle = 500;
+
+initial begin
+
+	sys_clk = 0;
+	#(offset);
+
+	forever #(halfcycle) sys_clk = ~sys_clk;
+
+end
+
+endmodule // sys_clk_gen

src/src/PCIeImports/sys_clk_gen_ds.v

@@ -0,0 +1,81 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : sys_clk_gen_ds.v
+// Version    : 3.3
+//--
+//--------------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module sys_clk_gen_ds (sys_clk_p, sys_clk_n);
+
+output	         sys_clk_p;
+output	         sys_clk_n;
+
+parameter        offset = 0;
+parameter        halfcycle = 500;
+
+
+sys_clk_gen 	#(
+
+                 .offset( offset ),
+                 .halfcycle( halfcycle )
+
+)
+clk_gen (
+
+                 .sys_clk(sys_clk_p)
+
+);
+
+assign sys_clk_n = !sys_clk_p;
+
+endmodule // sys_clk_gen_ds

src/src/PCIeImports/tests.vh

@@ -0,0 +1 @@
+`include "sample_tests1.vh"

src/src/PCIeImports/xil_sig2pipe.v

@@ -0,0 +1,216 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xil_sig2pipe.v
+// Version    : 3.3
+//-----------------------------------------------------------------------------
+//-- Description:  Pipe Mode Interface
+  //-- 16bit data for Gen1 rate @ Pipe Clk 125 
+  //-- 16bit data for Gen2 rate @ Pipe Clk 250
+  //-- Pipe Clk is provided as output of this module - All pipe signals need to be aligned to provided Pipe Clk
+  //-- pipe_tx_rate (0 - Gen1, 1 -Gen2 )
+  //-- Rcvr Detect is handled internally by the core (Rcvr Detect Bypassed)
+  //-- RX Status and PHY Status are handled internally (speed change & rcvr detect )
+//-----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module xil_sig2pipe
+(
+ 
+  output [24:0]  xil_rx0_sigs,
+  output [24:0]  xil_rx1_sigs,
+  output [24:0]  xil_rx2_sigs,
+  output [24:0]  xil_rx3_sigs,
+  output [24:0]  xil_rx4_sigs,
+  output [24:0]  xil_rx5_sigs,
+  output [24:0]  xil_rx6_sigs,
+  output [24:0]  xil_rx7_sigs,
+
+  input  [11:0]  xil_common_commands,
+  input  [22:0]  xil_tx0_sigs,
+  input  [22:0]  xil_tx1_sigs,
+  input  [22:0]  xil_tx2_sigs,
+  input  [22:0]  xil_tx3_sigs,
+  input  [22:0]  xil_tx4_sigs,
+  input  [22:0]  xil_tx5_sigs,
+  input  [22:0]  xil_tx6_sigs,
+  input  [22:0]  xil_tx7_sigs,
+  
+  // Pipe Interface - Common
+  
+  output         pipe_clk,
+  output         pipe_tx_rate,
+  output         pipe_tx_detect_rx,
+  output [15:0]  pipe_tx_powerdown,
+  
+  // Pipe Interface - TX
+ 
+  output [15:0]  pipe_tx0_data,
+  output [15:0]  pipe_tx1_data,
+  output [15:0]  pipe_tx2_data,
+  output [15:0]  pipe_tx3_data,
+  output [15:0]  pipe_tx4_data,
+  output [15:0]  pipe_tx5_data,
+  output [15:0]  pipe_tx6_data,
+  output [15:0]  pipe_tx7_data,
+  
+  output  [1:0]  pipe_tx0_char_is_k,
+  output  [1:0]  pipe_tx1_char_is_k,
+  output  [1:0]  pipe_tx2_char_is_k,
+  output  [1:0]  pipe_tx3_char_is_k,
+  output  [1:0]  pipe_tx4_char_is_k,
+  output  [1:0]  pipe_tx5_char_is_k,
+  output  [1:0]  pipe_tx6_char_is_k,
+  output  [1:0]  pipe_tx7_char_is_k,
+  
+  output         pipe_tx0_elec_idle,
+  output         pipe_tx1_elec_idle,
+  output         pipe_tx2_elec_idle,
+  output         pipe_tx3_elec_idle,
+  output         pipe_tx4_elec_idle,
+  output         pipe_tx5_elec_idle,
+  output         pipe_tx6_elec_idle,
+  output         pipe_tx7_elec_idle,
+  
+  // Pipe Interface - RX
+  
+  input  [15:0]  pipe_rx0_data,
+  input  [15:0]  pipe_rx1_data,
+  input  [15:0]  pipe_rx2_data,
+  input  [15:0]  pipe_rx3_data,
+  input  [15:0]  pipe_rx4_data,
+  input  [15:0]  pipe_rx5_data,
+  input  [15:0]  pipe_rx6_data,
+  input  [15:0]  pipe_rx7_data,
+  
+  input   [1:0]  pipe_rx0_char_is_k,
+  input   [1:0]  pipe_rx1_char_is_k,
+  input   [1:0]  pipe_rx2_char_is_k,
+  input   [1:0]  pipe_rx3_char_is_k,
+  input   [1:0]  pipe_rx4_char_is_k,
+  input   [1:0]  pipe_rx5_char_is_k,
+  input   [1:0]  pipe_rx6_char_is_k,
+  input   [1:0]  pipe_rx7_char_is_k,
+
+  input          pipe_rx0_elec_idle,
+  input          pipe_rx1_elec_idle,
+  input          pipe_rx2_elec_idle,
+  input          pipe_rx3_elec_idle,
+  input          pipe_rx4_elec_idle,
+  input          pipe_rx5_elec_idle,
+  input          pipe_rx6_elec_idle,
+  input          pipe_rx7_elec_idle
+
+);
+
+   assign pipe_clk          = xil_common_commands[0];
+   assign pipe_tx_rate      = xil_common_commands[1];
+   assign pipe_tx_detect_rx = xil_common_commands[2];
+   assign pipe_tx_powerdown = {xil_tx7_sigs[22:21],xil_tx6_sigs[22:21],xil_tx5_sigs[22:21],xil_tx4_sigs[22:21],
+                               xil_tx3_sigs[22:21],xil_tx2_sigs[22:21],xil_tx1_sigs[22:21],xil_tx0_sigs[22:21]};
+   
+  //------------------------------------------------------------------------------//
+  // RX PIPE to RX INT BUS 
+  //------------------------------------------------------------------------------//
+
+   assign xil_rx0_sigs = {6'b0,pipe_rx0_elec_idle,pipe_rx0_char_is_k,pipe_rx0_data}; 
+                            
+   assign xil_rx1_sigs = {6'b0,pipe_rx1_elec_idle,pipe_rx1_char_is_k,pipe_rx1_data}; 
+                            
+   assign xil_rx2_sigs = {6'b0,pipe_rx2_elec_idle,pipe_rx2_char_is_k,pipe_rx2_data}; 
+                            
+   assign xil_rx3_sigs = {6'b0,pipe_rx3_elec_idle,pipe_rx3_char_is_k,pipe_rx3_data}; 
+                            
+   assign xil_rx4_sigs = {6'b0,pipe_rx4_elec_idle,pipe_rx4_char_is_k,pipe_rx4_data}; 
+                            
+   assign xil_rx5_sigs = {6'b0,pipe_rx5_elec_idle,pipe_rx5_char_is_k,pipe_rx5_data}; 
+                            
+   assign xil_rx6_sigs = {6'b0,pipe_rx6_elec_idle,pipe_rx6_char_is_k,pipe_rx6_data}; 
+                            
+   assign xil_rx7_sigs = {6'b0,pipe_rx7_elec_idle,pipe_rx7_char_is_k,pipe_rx7_data}; 
+  //------------------------------------------------------------------------------//
+  // TX INT BUS to TX PIPE 
+  //------------------------------------------------------------------------------//
+   assign pipe_tx0_data        = xil_tx0_sigs[15: 0] ; 
+   assign pipe_tx0_char_is_k   = xil_tx0_sigs[17:16] ;
+   assign pipe_tx0_elec_idle   = xil_tx0_sigs[18]    ; 
+   
+   assign pipe_tx1_data        = xil_tx1_sigs[15: 0] ; 
+   assign pipe_tx1_char_is_k   = xil_tx1_sigs[17:16] ;
+   assign pipe_tx1_elec_idle   = xil_tx1_sigs[18]    ; 
+
+   assign pipe_tx2_data        = xil_tx2_sigs[15: 0] ; 
+   assign pipe_tx2_char_is_k   = xil_tx2_sigs[17:16] ;
+   assign pipe_tx2_elec_idle   = xil_tx2_sigs[18]    ;   
+   
+   assign pipe_tx3_data        = xil_tx3_sigs[15: 0] ; 
+   assign pipe_tx3_char_is_k   = xil_tx3_sigs[17:16] ;
+   assign pipe_tx3_elec_idle   = xil_tx3_sigs[18]    ; 
+   
+   assign pipe_tx4_data        = xil_tx4_sigs[15: 0] ; 
+   assign pipe_tx4_char_is_k   = xil_tx4_sigs[17:16] ;
+   assign pipe_tx4_elec_idle   = xil_tx4_sigs[18]    ; 
+
+   assign pipe_tx5_data        = xil_tx5_sigs[15: 0] ; 
+   assign pipe_tx5_char_is_k   = xil_tx5_sigs[17:16] ;
+   assign pipe_tx5_elec_idle   = xil_tx5_sigs[18]    ; 
+
+   assign pipe_tx6_data        = xil_tx6_sigs[15: 0] ; 
+   assign pipe_tx6_char_is_k   = xil_tx6_sigs[17:16] ;
+   assign pipe_tx6_elec_idle   = xil_tx6_sigs[18]    ; 
+   
+   assign pipe_tx7_data        = xil_tx7_sigs[15: 0] ; 
+   assign pipe_tx7_char_is_k   = xil_tx7_sigs[17:16] ;
+   assign pipe_tx7_elec_idle   = xil_tx7_sigs[18]    ; 
+
+endmodule
+
+   

src/src/PCIeImports/xilinx_pcie_2_1_ep_7x.v

@@ -0,0 +1,592 @@
+
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xilinx_pcie_2_1_ep_7x.v
+// Version    : 3.3
+//--
+//-- Description:  PCI Express Endpoint example FPGA design
+//--
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module xilinx_pcie_2_1_ep_7x # (
+  parameter PL_FAST_TRAIN       = "FALSE", // Simulation Speedup
+  parameter EXT_PIPE_SIM        = "FALSE",  // This Parameter has effect on selecting Enable External PIPE Interface in GUI.	
+  parameter PCIE_EXT_CLK        = "TRUE",    // Use External Clocking Module
+  parameter PCIE_EXT_GT_COMMON  = "FALSE",
+  parameter REF_CLK_FREQ        = 0,     // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
+  parameter C_DATA_WIDTH        = 64, // RX/TX interface data width
+  parameter KEEP_WIDTH          = C_DATA_WIDTH / 8 // TSTRB width
+) (
+  output  [1:0]    pci_exp_txp,
+  output  [1:0]    pci_exp_txn,
+  input   [1:0]    pci_exp_rxp,
+  input   [1:0]    pci_exp_rxn,
+
+
+
+  input                                       sys_clk_p,
+  input                                       sys_clk_n,
+  input                                       sys_rst_n,
+
+  output Clk_o,
+
+  input   [63:0] MeasData_i,
+  input   MeasEnd_i,
+
+  output  StartMeasCmd_o,
+
+  output  ClkUser3_o
+);
+
+// Wire Declarations
+  wire                                        pipe_mmcm_rst_n;
+
+  wire                                        user_clk;
+  wire                                        user_reset;
+  wire                                        user_lnk_up;
+
+  // Tx
+  wire                                        s_axis_tx_tready;
+  wire [3:0]                                  s_axis_tx_tuser;
+  wire [C_DATA_WIDTH-1:0]                     s_axis_tx_tdata;
+  wire [KEEP_WIDTH-1:0]                       s_axis_tx_tkeep;
+  wire                                        s_axis_tx_tlast;
+  wire                                        s_axis_tx_tvalid;
+
+  // Rx
+  wire [C_DATA_WIDTH-1:0]                     m_axis_rx_tdata;
+  wire [KEEP_WIDTH-1:0]                       m_axis_rx_tkeep;
+  wire                                        m_axis_rx_tlast;
+  wire                                        m_axis_rx_tvalid;
+  wire                                        m_axis_rx_tready;
+  wire  [21:0]                                m_axis_rx_tuser;
+
+  wire                                        tx_cfg_gnt;
+  wire                                        rx_np_ok;
+  wire                                        rx_np_req;
+  wire                                        cfg_turnoff_ok;
+  wire                                        cfg_trn_pending;
+  wire                                        cfg_pm_halt_aspm_l0s;
+  wire                                        cfg_pm_halt_aspm_l1;
+  wire                                        cfg_pm_force_state_en;
+  wire   [1:0]                                cfg_pm_force_state;
+  wire                                        cfg_pm_wake;
+  wire  [63:0]                                cfg_dsn;
+
+  // Flow Control
+  wire [2:0]                                  fc_sel;
+
+  //-------------------------------------------------------
+  // Configuration (CFG) Interface
+  //-------------------------------------------------------
+  wire                                        cfg_err_ecrc;
+  wire                                        cfg_err_cor;
+  wire                                        cfg_err_atomic_egress_blocked;
+  wire                                        cfg_err_internal_cor;
+  wire                                        cfg_err_malformed;
+  wire                                        cfg_err_mc_blocked;
+  wire                                        cfg_err_poisoned;
+  wire                                        cfg_err_norecovery;
+  wire                                        cfg_err_acs;
+  wire                                        cfg_err_internal_uncor;
+  wire                                        cfg_err_ur;
+  wire                                        cfg_err_cpl_timeout;
+  wire                                        cfg_err_cpl_abort;
+  wire                                        cfg_err_cpl_unexpect;
+  wire                                        cfg_err_posted;
+  wire                                        cfg_err_locked;
+  wire  [47:0]                                cfg_err_tlp_cpl_header;
+  wire [127:0]                                cfg_err_aer_headerlog;
+  wire   [4:0]                                cfg_aer_interrupt_msgnum;
+
+  wire                                        cfg_interrupt;
+  wire                                        cfg_interrupt_assert;
+  wire   [7:0]                                cfg_interrupt_di;
+  wire                                        cfg_interrupt_stat;
+  wire   [4:0]                                cfg_pciecap_interrupt_msgnum;
+
+  wire                                        cfg_to_turnoff;
+  wire   [7:0]                                cfg_bus_number;
+  wire   [4:0]                                cfg_device_number;
+  wire   [2:0]                                cfg_function_number;
+
+  wire  [31:0]                                cfg_mgmt_di;
+  wire   [3:0]                                cfg_mgmt_byte_en;
+  wire   [9:0]                                cfg_mgmt_dwaddr;
+  wire                                        cfg_mgmt_wr_en;
+  wire                                        cfg_mgmt_rd_en;
+  wire                                        cfg_mgmt_wr_readonly;
+
+  //-------------------------------------------------------
+  // Physical Layer Control and Status (PL) Interface
+  //-------------------------------------------------------
+  wire                                        pl_directed_link_auton;
+  wire [1:0]                                  pl_directed_link_change;
+  wire                                        pl_directed_link_speed;
+  wire [1:0]                                  pl_directed_link_width;
+  wire                                        pl_upstream_prefer_deemph;
+
+  wire                                        sys_rst_n_c;
+  wire                                        sys_clk;
+
+
+// Register Declaration
+
+  reg                                         user_reset_q;
+  reg                                         user_lnk_up_q;
+
+  assign Clk_o = user_clk;
+// Local Parameters
+  localparam TCQ               = 1;
+  localparam USER_CLK_FREQ     = 2;
+  localparam USER_CLK2_DIV2    = "FALSE";
+  localparam USERCLK2_FREQ     = (USER_CLK2_DIV2 == "TRUE") ? (USER_CLK_FREQ == 4) ? 3 : (USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ: USER_CLK_FREQ;
+
+
+ //-----------------------------I/O BUFFERS------------------------//
+
+  IBUF   sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_rst_n));
+
+  IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n));
+
+
+  always @(posedge user_clk) begin
+    user_reset_q  <= user_reset;
+    user_lnk_up_q <= user_lnk_up;
+  end
+
+
+
+      assign pipe_mmcm_rst_n                        = 1'b1;
+
+
+
+pcie1234_support #
+   (	 
+    .LINK_CAP_MAX_LINK_WIDTH        ( 2 ),  // PCIe Lane Width
+    .C_DATA_WIDTH                   ( C_DATA_WIDTH ),                       // RX/TX interface data width
+    .KEEP_WIDTH                     ( KEEP_WIDTH ),                         // TSTRB width
+    .PCIE_REFCLK_FREQ               ( REF_CLK_FREQ ),                       // PCIe reference clock frequency
+    .PCIE_USERCLK1_FREQ             ( USER_CLK_FREQ +1 ),                   // PCIe user clock 1 frequency
+    .PCIE_USERCLK2_FREQ             ( USERCLK2_FREQ +1 ),                   // PCIe user clock 2 frequency             
+    .PCIE_USE_MODE                  ("1.0"),           // PCIe use mode
+    .PCIE_GT_DEVICE                 ("GTP")              // PCIe GT device
+   ) 
+pcie1234_support
+  (
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // PCI Express (pci_exp) Interface                                                                                //
+  //----------------------------------------------------------------------------------------------------------------//
+  // Tx
+  .pci_exp_txn                               ( pci_exp_txn ),
+  .pci_exp_txp                               ( pci_exp_txp ),
+
+  // Rx
+  .pci_exp_rxn                               ( pci_exp_rxn ),
+  .pci_exp_rxp                               ( pci_exp_rxp ),
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // Clocking Sharing Interface                                                                                     //
+  //----------------------------------------------------------------------------------------------------------------//
+  .pipe_pclk_out_slave                        ( ),
+  .pipe_rxusrclk_out                          ( ),
+  .pipe_rxoutclk_out                          ( ),
+  .pipe_dclk_out                              ( ),
+  .pipe_userclk1_out                          ( ),
+  .pipe_oobclk_out                            ( ),
+  .pipe_userclk2_out                          ( ),
+  .pipe_mmcm_lock_out                         ( ),
+  .pipe_pclk_sel_slave                        ( 2'b0),
+  .pipe_mmcm_rst_n                            ( pipe_mmcm_rst_n ),        // Async      | Async
+
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // AXI-S Interface                                                                                                //
+  //----------------------------------------------------------------------------------------------------------------//
+
+  // Common
+  .user_clk_out                              ( user_clk ),
+  .user_reset_out                            ( user_reset ),
+  .user_lnk_up                               ( user_lnk_up ),
+  .user_app_rdy                              ( ),
+
+  // TX
+  .s_axis_tx_tready                          ( s_axis_tx_tready ),
+  .s_axis_tx_tdata                           ( s_axis_tx_tdata ),
+  .s_axis_tx_tkeep                           ( s_axis_tx_tkeep ),
+  .s_axis_tx_tuser                           ( s_axis_tx_tuser ),
+  .s_axis_tx_tlast                           ( s_axis_tx_tlast ),
+  .s_axis_tx_tvalid                          ( s_axis_tx_tvalid ),
+
+  // Rx
+  .m_axis_rx_tdata                           ( m_axis_rx_tdata ),
+  .m_axis_rx_tkeep                           ( m_axis_rx_tkeep ),
+  .m_axis_rx_tlast                           ( m_axis_rx_tlast ),
+  .m_axis_rx_tvalid                          ( m_axis_rx_tvalid ),
+  .m_axis_rx_tready                          ( m_axis_rx_tready ),
+  .m_axis_rx_tuser                           ( m_axis_rx_tuser ),
+
+  // Flow Control
+  .fc_cpld                                   ( ),
+  .fc_cplh                                   ( ),
+  .fc_npd                                    ( ),
+  .fc_nph                                    ( ),
+  .fc_pd                                     ( ),
+  .fc_ph                                     ( ),
+  .fc_sel                                    ( fc_sel ),
+
+  // Management Interface
+  .cfg_mgmt_di                               ( cfg_mgmt_di ),
+  .cfg_mgmt_byte_en                          ( cfg_mgmt_byte_en ),
+  .cfg_mgmt_dwaddr                           ( cfg_mgmt_dwaddr ),
+  .cfg_mgmt_wr_en                            ( cfg_mgmt_wr_en ),
+  .cfg_mgmt_rd_en                            ( cfg_mgmt_rd_en ),
+  .cfg_mgmt_wr_readonly                      ( cfg_mgmt_wr_readonly ),
+
+  //------------------------------------------------//
+  // EP and RP                                      //
+  //------------------------------------------------//
+  .cfg_mgmt_do                               ( ),
+  .cfg_mgmt_rd_wr_done                       ( ),
+  .cfg_mgmt_wr_rw1c_as_rw                    ( 1'b0 ),
+
+  // Error Reporting Interface
+  .cfg_err_ecrc                              ( cfg_err_ecrc ),
+  .cfg_err_ur                                ( cfg_err_ur ),
+  .cfg_err_cpl_timeout                       ( cfg_err_cpl_timeout ),
+  .cfg_err_cpl_unexpect                      ( cfg_err_cpl_unexpect ),
+  .cfg_err_cpl_abort                         ( cfg_err_cpl_abort ),
+  .cfg_err_posted                            ( cfg_err_posted ),
+  .cfg_err_cor                               ( cfg_err_cor ),
+  .cfg_err_atomic_egress_blocked             ( cfg_err_atomic_egress_blocked ),
+  .cfg_err_internal_cor                      ( cfg_err_internal_cor ),
+  .cfg_err_malformed                         ( cfg_err_malformed ),
+  .cfg_err_mc_blocked                        ( cfg_err_mc_blocked ),
+  .cfg_err_poisoned                          ( cfg_err_poisoned ),
+  .cfg_err_norecovery                        ( cfg_err_norecovery ),
+  .cfg_err_tlp_cpl_header                    ( cfg_err_tlp_cpl_header ),
+  .cfg_err_cpl_rdy                           ( ),
+  .cfg_err_locked                            ( cfg_err_locked ),
+  .cfg_err_acs                               ( cfg_err_acs ),
+  .cfg_err_internal_uncor                    ( cfg_err_internal_uncor ),
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // AER Interface                                                                                                  //
+  //----------------------------------------------------------------------------------------------------------------//
+  .cfg_err_aer_headerlog                     ( cfg_err_aer_headerlog ),
+  .cfg_err_aer_headerlog_set                 ( ),
+  .cfg_aer_ecrc_check_en                     ( ),
+  .cfg_aer_ecrc_gen_en                       ( ),
+  .cfg_aer_interrupt_msgnum                  ( cfg_aer_interrupt_msgnum ),
+
+  .tx_cfg_gnt                                ( tx_cfg_gnt ),
+  .rx_np_ok                                  ( rx_np_ok ),
+  .rx_np_req                                 ( rx_np_req ),
+  .cfg_trn_pending                           ( cfg_trn_pending ),
+  .cfg_pm_halt_aspm_l0s                      ( cfg_pm_halt_aspm_l0s ),
+  .cfg_pm_halt_aspm_l1                       ( cfg_pm_halt_aspm_l1 ),
+  .cfg_pm_force_state_en                     ( cfg_pm_force_state_en ),
+  .cfg_pm_force_state                        ( cfg_pm_force_state ),
+  .cfg_dsn                                   ( cfg_dsn ),
+  .cfg_turnoff_ok                            ( cfg_turnoff_ok ),
+  .cfg_pm_wake                               ( cfg_pm_wake ),
+  //------------------------------------------------//
+  // RP Only                                        //
+  //------------------------------------------------//
+  .cfg_pm_send_pme_to                        ( 1'b0 ),
+  .cfg_ds_bus_number                         ( 8'b0 ),
+  .cfg_ds_device_number                      ( 5'b0 ),
+  .cfg_ds_function_number                    ( 3'b0 ),
+
+  //------------------------------------------------//
+  // EP Only                                        //
+  //------------------------------------------------//
+  .cfg_interrupt                             ( cfg_interrupt ),
+  .cfg_interrupt_rdy                         ( ),
+  .cfg_interrupt_assert                      ( cfg_interrupt_assert ),
+  .cfg_interrupt_di                          ( cfg_interrupt_di ),
+  .cfg_interrupt_do                          ( ),
+  .cfg_interrupt_mmenable                    ( ),
+  .cfg_interrupt_msienable                   ( ),
+  .cfg_interrupt_msixenable                  ( ),
+  .cfg_interrupt_msixfm                      ( ),
+  .cfg_interrupt_stat                        ( cfg_interrupt_stat ),
+  .cfg_pciecap_interrupt_msgnum              ( cfg_pciecap_interrupt_msgnum ),
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // Configuration (CFG) Interface                                                                                  //
+  //----------------------------------------------------------------------------------------------------------------//
+  .cfg_status                                ( ),
+  .cfg_command                               ( ),
+  .cfg_dstatus                               ( ),
+  .cfg_lstatus                               ( ),
+  .cfg_pcie_link_state                       ( ),
+  .cfg_dcommand                              ( ),
+  .cfg_lcommand                              ( ),
+  .cfg_dcommand2                             ( ),
+
+  .cfg_pmcsr_pme_en                          ( ),
+  .cfg_pmcsr_powerstate                      ( ),
+  .cfg_pmcsr_pme_status                      ( ),
+  .cfg_received_func_lvl_rst                 ( ),
+  .tx_buf_av                                 ( ),
+  .tx_err_drop                               ( ),
+  .tx_cfg_req                                ( ),
+  .cfg_to_turnoff                            ( cfg_to_turnoff ),
+  .cfg_bus_number                            ( cfg_bus_number ),
+  .cfg_device_number                         ( cfg_device_number ),
+  .cfg_function_number                       ( cfg_function_number ),
+  .cfg_bridge_serr_en                        ( ),
+  .cfg_slot_control_electromech_il_ctl_pulse ( ),
+  .cfg_root_control_syserr_corr_err_en       ( ),
+  .cfg_root_control_syserr_non_fatal_err_en  ( ),
+  .cfg_root_control_syserr_fatal_err_en      ( ),
+  .cfg_root_control_pme_int_en               ( ),
+  .cfg_aer_rooterr_corr_err_reporting_en     ( ),
+  .cfg_aer_rooterr_non_fatal_err_reporting_en( ),
+  .cfg_aer_rooterr_fatal_err_reporting_en    ( ),
+  .cfg_aer_rooterr_corr_err_received         ( ),
+  .cfg_aer_rooterr_non_fatal_err_received    ( ),
+  .cfg_aer_rooterr_fatal_err_received        ( ),
+  //----------------------------------------------------------------------------------------------------------------//
+  // VC interface                                                                                                  //
+  //---------------------------------------------------------------------------------------------------------------//
+  .cfg_vc_tcvc_map                           ( ),
+
+  .cfg_msg_received                          ( ),
+  .cfg_msg_data                              ( ),
+  .cfg_msg_received_err_cor                  ( ),
+  .cfg_msg_received_err_non_fatal            ( ),
+  .cfg_msg_received_err_fatal                ( ),
+  .cfg_msg_received_pm_as_nak                ( ),
+  .cfg_msg_received_pme_to_ack               ( ),
+  .cfg_msg_received_assert_int_a             ( ),
+  .cfg_msg_received_assert_int_b             ( ),
+  .cfg_msg_received_assert_int_c             ( ),
+  .cfg_msg_received_assert_int_d             ( ),
+  .cfg_msg_received_deassert_int_a           ( ),
+  .cfg_msg_received_deassert_int_b           ( ),
+  .cfg_msg_received_deassert_int_c           ( ),
+  .cfg_msg_received_deassert_int_d           ( ),
+  .cfg_msg_received_pm_pme                  ( ),
+  .cfg_msg_received_setslotpowerlimit       ( ),
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // Physical Layer Control and Status (PL) Interface                                                               //
+  //----------------------------------------------------------------------------------------------------------------//
+  .pl_directed_link_change                   ( pl_directed_link_change ),
+  .pl_directed_link_width                    ( pl_directed_link_width ),
+  .pl_directed_link_speed                    ( pl_directed_link_speed ),
+  .pl_directed_link_auton                    ( pl_directed_link_auton ),
+  .pl_upstream_prefer_deemph                 ( pl_upstream_prefer_deemph ),
+
+  .pl_sel_lnk_rate                           ( ),
+  .pl_sel_lnk_width                          ( ),
+  .pl_ltssm_state                            ( ),
+  .pl_lane_reversal_mode                     ( ),
+
+  .pl_phy_lnk_up                             ( ),
+  .pl_tx_pm_state                            ( ),
+  .pl_rx_pm_state                            ( ),
+
+  .pl_link_upcfg_cap                         ( ),
+  .pl_link_gen2_cap                          ( ),
+  .pl_link_partner_gen2_supported            ( ),
+  .pl_initial_link_width                     ( ),
+
+  .pl_directed_change_done                   ( ),
+
+  //------------------------------------------------//
+  // EP Only                                        //
+  //------------------------------------------------//
+  .pl_received_hot_rst                       ( ),
+
+  //------------------------------------------------//
+  // RP Only                                        //
+  //------------------------------------------------//
+  .pl_transmit_hot_rst                       ( 1'b0 ),
+  .pl_downstream_deemph_source               ( 1'b0 ),
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // PCIe DRP (PCIe DRP) Interface                                                                                  //
+  //----------------------------------------------------------------------------------------------------------------//
+  .pcie_drp_clk                               ( 1'b1 ),
+  .pcie_drp_en                                ( 1'b0 ),
+  .pcie_drp_we                                ( 1'b0 ),
+  .pcie_drp_addr                              ( 9'h0 ),
+  .pcie_drp_di                                ( 16'h0 ),
+  .pcie_drp_rdy                               ( ),
+  .pcie_drp_do                                ( ),
+
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // System  (SYS) Interface                                                                                        //
+  //----------------------------------------------------------------------------------------------------------------//
+  .sys_clk                                    ( sys_clk ),
+  .sys_rst_n                                  ( sys_rst_n_c ),
+
+  .ClkUser3_o (ClkUser3_o)
+
+);
+
+
+pcie_app_7x  #(
+  .C_DATA_WIDTH( C_DATA_WIDTH ),
+  .TCQ( TCQ )
+
+) app (
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // AXI-S Interface                                                                                                //
+  //----------------------------------------------------------------------------------------------------------------//
+
+  // Common
+  .user_clk                       ( user_clk ),
+  .user_reset                     ( user_reset_q ),
+  .user_lnk_up                    ( user_lnk_up_q ),
+
+  // Tx
+  .s_axis_tx_tready               ( s_axis_tx_tready ),
+  .s_axis_tx_tdata                ( s_axis_tx_tdata ),
+  .s_axis_tx_tkeep                ( s_axis_tx_tkeep ),
+  .s_axis_tx_tuser                ( s_axis_tx_tuser ),
+  .s_axis_tx_tlast                ( s_axis_tx_tlast ),
+  .s_axis_tx_tvalid               ( s_axis_tx_tvalid ),
+
+  // Rx
+  .m_axis_rx_tdata                ( m_axis_rx_tdata ),
+  .m_axis_rx_tkeep                ( m_axis_rx_tkeep ),
+  .m_axis_rx_tlast                ( m_axis_rx_tlast ),
+  .m_axis_rx_tvalid               ( m_axis_rx_tvalid ),
+  .m_axis_rx_tready               ( m_axis_rx_tready ),
+  .m_axis_rx_tuser                ( m_axis_rx_tuser ),
+
+  .tx_cfg_gnt                     ( tx_cfg_gnt ),
+  .rx_np_ok                       ( rx_np_ok ),
+  .rx_np_req                      ( rx_np_req ),
+  .cfg_turnoff_ok                 ( cfg_turnoff_ok ),
+  .cfg_trn_pending                ( cfg_trn_pending ),
+  .cfg_pm_halt_aspm_l0s           ( cfg_pm_halt_aspm_l0s ),
+  .cfg_pm_halt_aspm_l1            ( cfg_pm_halt_aspm_l1 ),
+  .cfg_pm_force_state_en          ( cfg_pm_force_state_en ),
+  .cfg_pm_force_state             ( cfg_pm_force_state ),
+  .cfg_pm_wake                    ( cfg_pm_wake ),
+  .cfg_dsn                        ( cfg_dsn ),
+
+  // Flow Control
+  .fc_sel                         ( fc_sel ),
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // Configuration (CFG) Interface                                                                                  //
+  //----------------------------------------------------------------------------------------------------------------//
+  .cfg_err_cor                    ( cfg_err_cor ),
+  .cfg_err_atomic_egress_blocked  ( cfg_err_atomic_egress_blocked ),
+  .cfg_err_internal_cor           ( cfg_err_internal_cor ),
+  .cfg_err_malformed              ( cfg_err_malformed ),
+  .cfg_err_mc_blocked             ( cfg_err_mc_blocked ),
+  .cfg_err_poisoned               ( cfg_err_poisoned ),
+  .cfg_err_norecovery             ( cfg_err_norecovery ),
+  .cfg_err_ur                     ( cfg_err_ur ),
+  .cfg_err_ecrc                   ( cfg_err_ecrc ),
+  .cfg_err_cpl_timeout            ( cfg_err_cpl_timeout ),
+  .cfg_err_cpl_abort              ( cfg_err_cpl_abort ),
+  .cfg_err_cpl_unexpect           ( cfg_err_cpl_unexpect ),
+  .cfg_err_posted                 ( cfg_err_posted ),
+  .cfg_err_locked                 ( cfg_err_locked ),
+  .cfg_err_acs                    ( cfg_err_acs ), //1'b0 ),
+  .cfg_err_internal_uncor         ( cfg_err_internal_uncor ), //1'b0 ),
+  .cfg_err_tlp_cpl_header         ( cfg_err_tlp_cpl_header ),
+  //----------------------------------------------------------------------------------------------------------------//
+  // Advanced Error Reporting (AER) Interface                                                                       //
+  //----------------------------------------------------------------------------------------------------------------//
+  .cfg_err_aer_headerlog          ( cfg_err_aer_headerlog ),
+  .cfg_aer_interrupt_msgnum       ( cfg_aer_interrupt_msgnum ),
+
+  .cfg_to_turnoff                 ( cfg_to_turnoff ),
+  .cfg_bus_number                 ( cfg_bus_number ),
+  .cfg_device_number              ( cfg_device_number ),
+  .cfg_function_number            ( cfg_function_number ),
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // Management (MGMT) Interface                                                                                    //
+  //----------------------------------------------------------------------------------------------------------------//
+  .cfg_mgmt_di                    ( cfg_mgmt_di ),
+  .cfg_mgmt_byte_en               ( cfg_mgmt_byte_en ),
+  .cfg_mgmt_dwaddr                ( cfg_mgmt_dwaddr ),
+  .cfg_mgmt_wr_en                 ( cfg_mgmt_wr_en ),
+  .cfg_mgmt_rd_en                 ( cfg_mgmt_rd_en ),
+  .cfg_mgmt_wr_readonly           ( cfg_mgmt_wr_readonly ),
+
+  //----------------------------------------------------------------------------------------------------------------//
+  // Physical Layer Control and Status (PL) Interface                                                               //
+  //----------------------------------------------------------------------------------------------------------------//
+  .pl_directed_link_auton         ( pl_directed_link_auton ),
+  .pl_directed_link_change        ( pl_directed_link_change ),
+  .pl_directed_link_speed         ( pl_directed_link_speed ),
+  .pl_directed_link_width         ( pl_directed_link_width ),
+  .pl_upstream_prefer_deemph      ( pl_upstream_prefer_deemph ),
+
+  .cfg_interrupt                  ( cfg_interrupt ),
+  .cfg_interrupt_assert           ( cfg_interrupt_assert ),
+  .cfg_interrupt_di               ( cfg_interrupt_di ),
+  .cfg_interrupt_stat             ( cfg_interrupt_stat ),
+  .cfg_pciecap_interrupt_msgnum   ( cfg_pciecap_interrupt_msgnum ),
+
+  .MeasData_i(MeasData_i),
+  .MeasEnd_i(MeasEnd_i),
+
+  .StartMeasCmd_o(StartMeasCmd_o)
+);
+
+endmodule

src/src/PCIeImports/xilinx_pcie_2_1_rport_7x.v

@@ -0,0 +1,665 @@
+//-----------------------------------------------------------------------------
+//
+// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//-----------------------------------------------------------------------------
+// Project    : Series-7 Integrated Block for PCI Express
+// File       : xilinx_pcie_2_1_rport_7x.v
+// Version    : 3.3
+//
+//--------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+
+`include "board_common.vh"
+
+module xilinx_pcie_2_1_rport_7x # (
+
+
+  parameter                       REF_CLK_FREQ = 0,                                   // 0 - 100 MHz, 1 - 125 MHz,  2 - 250 MHz
+  parameter                       PCIE_EXT_CLK = "FALSE", // Use External Clocking Module	//postsynthsim changes
+  parameter                       PL_FAST_TRAIN = "FALSE",
+  parameter                       ALLOW_X8_GEN2 = "FALSE",
+  parameter                       C_DATA_WIDTH = 64,
+  parameter                       REM_WIDTH  = (C_DATA_WIDTH == 128) ? 2 : 1,
+  parameter                       KEEP_WIDTH = C_DATA_WIDTH / 8,
+  parameter                       LINK_CAP_MAX_LINK_WIDTH = 6'h08,
+  parameter                       DEVICE_ID = 16'h506F,
+  parameter                       LINK_CAP_MAX_LINK_SPEED = 4'h1,
+  parameter                       LINK_CTRL2_TARGET_LINK_SPEED = 4'h1,
+  parameter                       DEV_CAP_MAX_PAYLOAD_SUPPORTED = 1,
+  parameter                       USER_CLK_FREQ = 3,
+  parameter                       USER_CLK2_DIV2 = "FALSE",
+  parameter                       TRN_DW = "FALSE",
+  parameter                       VC0_TX_LASTPACKET = 28,
+  parameter                       VC0_RX_RAM_LIMIT = 13'h03ff,
+  parameter                       VC0_CPL_INFINITE = "TRUE",
+  parameter                       VC0_TOTAL_CREDITS_PD = 154,
+  parameter                       VC0_TOTAL_CREDITS_CD = 154
+
+)
+(
+
+  input                           sys_clk,
+  input                           sys_rst_n,
+
+  input  [0:0]              pci_exp_rxn, pci_exp_rxp,
+  output [0:0]              pci_exp_txn, pci_exp_txp
+
+);
+
+  // Local Wires
+  // Common
+  wire                            trn_clk;
+  wire                            user_reset_out;
+  wire                            trn_reset_n;
+  wire                            trn_lnk_up;
+
+  // Tx
+  wire  [C_DATA_WIDTH-1:0]        trn_td;
+  wire  [REM_WIDTH-1:0]           trn_trem_n;
+  wire                            trn_tsof_n;
+  wire                            trn_teof_n;
+  wire                            trn_tsrc_rdy_n;
+  wire                            trn_tdst_rdy;
+  wire                            trn_tsrc_dsc_n;
+  wire                            trn_terrfwd_n;
+  wire                            trn_tdst_dsc;
+  wire  [5:0]                    	trn_tbuf_av;
+
+  // Rx
+  wire  [C_DATA_WIDTH-1:0]        trn_rd;
+  wire  [REM_WIDTH-1:0]           trn_rrem;
+  wire                            trn_rsof;
+  wire                            trn_reof;
+  wire                            trn_rsrc_rdy;
+  wire                            trn_rsrc_dsc;
+  wire                            trn_rdst_rdy_n;
+  wire                            trn_rerrfwd;
+  wire                            trn_rnp_ok_n;
+  wire [6:0]                	    trn_rbar_hit;
+  wire [7:0]                	    trn_rfc_nph_av;
+  wire [11:0]               	    trn_rfc_npd_av;
+  wire [7:0]                	    trn_rfc_ph_av;
+  wire [11:0]               	    trn_rfc_pd_av;
+  wire [7:0]                	    trn_rfc_cplh_av;
+  wire [11:0]               	    trn_rfc_cpld_av;
+
+  wire [31:0]               	    cfg_do;
+  wire [31:0]               	    cfg_di;
+  wire [3:0]             		      cfg_byte_en_n;
+  wire [9:0]               	      cfg_dwaddr;
+  wire [47:0]               	    cfg_err_tlp_cpl_header;
+  wire                            cfg_wr_en_n;
+  wire                            cfg_rd_wr_done;
+  wire                            cfg_rd_en_n;
+  wire                            cfg_err_cor_n;
+  wire                            cfg_err_ur_n;
+  wire                            cfg_err_ecrc_n;
+  wire                            cfg_err_cpl_timeout_n;
+  wire                            cfg_err_cpl_abort_n;
+  wire                            cfg_err_cpl_unexpect_n;
+  wire                            cfg_err_posted_n;
+  wire                            cfg_interrupt_n;
+  wire                            cfg_interrupt_rdy;
+  wire [15:0]               	    cfg_status;
+  wire [15:0]               	    cfg_command;
+  wire [15:0]               	    cfg_dstatus;
+  wire [15:0]               	    cfg_dcommand;
+  wire [15:0]               	    cfg_lstatus;
+  wire [15:0]               	    cfg_lcommand;
+  wire                            cfg_rdy_n;
+  wire [2:0]                	    cfg_pcie_link_state;
+  wire                            cfg_trn_pending_n;
+
+  wire [2:0]                      pl_initial_link_width;
+  wire [1:0]                      pl_lane_reversal_mode;
+  wire                            pl_link_gen2_capable;
+  wire                            pl_link_partner_gen2_supported;
+  wire                            pl_link_upcfg_capable;
+  wire [5:0]                      pl_ltssm_state;
+  wire                            pl_sel_link_rate;
+  wire [1:0]                      pl_sel_link_width;
+  wire                            pl_directed_link_auton;
+  wire [1:0]                      pl_directed_link_change;
+  wire                            pl_directed_link_speed;
+  wire [1:0]                      pl_directed_link_width;
+  wire                            pl_upstream_prefer_deemph;
+
+  wire                            speed_change_done_n;
+
+  wire                            trn_tstr;
+  wire                            trn_tecrc_gen;
+
+
+
+  wire [C_DATA_WIDTH-1:0]         s_axis_tx_tdata;
+  wire                            s_axis_tx_tvalid;
+  wire                            s_axis_tx_tready;
+  wire   [KEEP_WIDTH-1:0]         s_axis_tx_tkeep;
+  wire                            s_axis_tx_tlast;
+  wire              [3:0]         s_axis_tx_tuser;
+
+  wire [C_DATA_WIDTH-1:0]         m_axis_rx_tdata;
+  wire                            m_axis_rx_tvalid;
+  wire                            m_axis_rx_tready;
+  wire   [KEEP_WIDTH-1:0]         m_axis_rx_tkeep;
+  wire                            m_axis_rx_tlast;
+  wire             [21:0]         m_axis_rx_tuser;
+
+  // Wires used for external clocking connectivity
+  wire                                        pipe_pclk_in;
+  wire                                        pipe_rxusrclk_in;
+  wire  [0:0]    pipe_rxoutclk_in;
+  wire                                        pipe_dclk_in;
+  wire                                        pipe_userclk1_in;
+  wire                                        pipe_userclk2_in;
+  wire                                        pipe_mmcm_lock_in;
+
+  wire                                        pipe_txoutclk_out;
+  wire [0:0]     pipe_rxoutclk_out;
+  wire [0:0]     pipe_pclk_sel_out;
+  wire                                        pipe_gen3_out;
+  wire                                        pipe_oobclk_in;
+
+  assign trn_reset_n = !user_reset_out;
+
+  // PCI-Express FPGA Endpoint Instance
+
+  pcie_2_1_rport_7x # (
+
+    .REF_CLK_FREQ                              ( REF_CLK_FREQ ),
+    .PCIE_EXT_CLK                              ( PCIE_EXT_CLK ),
+    .PL_FAST_TRAIN                             ( PL_FAST_TRAIN ),
+    .ALLOW_X8_GEN2                             ( ALLOW_X8_GEN2 ),
+    .C_DATA_WIDTH                              ( C_DATA_WIDTH ),
+    .LINK_CAP_MAX_LINK_WIDTH                   ( LINK_CAP_MAX_LINK_WIDTH ),
+    .LINK_CAP_MAX_LINK_SPEED                   ( LINK_CAP_MAX_LINK_SPEED ),
+    .LINK_CTRL2_TARGET_LINK_SPEED              ( LINK_CTRL2_TARGET_LINK_SPEED ),
+    .DEV_CAP_MAX_PAYLOAD_SUPPORTED             ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
+    .USER_CLK_FREQ                             ( USER_CLK_FREQ ),
+    .USER_CLK2_DIV2                            ( USER_CLK2_DIV2 ),
+    .TRN_DW                                    ( TRN_DW ),
+    .VC0_TX_LASTPACKET                         ( VC0_TX_LASTPACKET ),
+    .VC0_RX_RAM_LIMIT                          ( VC0_RX_RAM_LIMIT ),
+    .VC0_CPL_INFINITE                          ( VC0_CPL_INFINITE ),
+    .VC0_TOTAL_CREDITS_PD                      ( VC0_TOTAL_CREDITS_PD ),
+    .VC0_TOTAL_CREDITS_CD                      ( VC0_TOTAL_CREDITS_CD )
+
+  ) rport (
+
+    //----------------------------------------------------------------------------------------------------------------//
+    // 1. PCI Express (pci_exp) Interface                                                                             //
+    //----------------------------------------------------------------------------------------------------------------//
+
+
+    .pci_exp_txp                               ( pci_exp_txp ),
+    .pci_exp_txn                               ( pci_exp_txn ),
+    .pci_exp_rxp                               ( pci_exp_rxp ),
+    .pci_exp_rxn                               ( pci_exp_rxn ),
+
+    //----------------------------------------------------------------------------------------------------------------//
+    // 2. Clocking Interface - For Partial Reconfig Support                                                           //
+    //----------------------------------------------------------------------------------------------------------------//
+    .pipe_pclk_in                              ( pipe_pclk_in ),
+    .pipe_rxusrclk_in                          ( pipe_rxusrclk_in ),
+    .pipe_rxoutclk_in                          ( pipe_rxoutclk_in ),
+    .pipe_dclk_in                              ( pipe_dclk_in ),
+    .pipe_userclk1_in                          ( pipe_userclk1_in ),
+    .pipe_userclk2_in                          ( pipe_userclk2_in ),
+    .pipe_oobclk_in                            ( pipe_oobclk_in ),
+    .pipe_mmcm_lock_in                         ( pipe_mmcm_lock_in ),
+
+    .pipe_txoutclk_out                         ( pipe_txoutclk_out ),
+    .pipe_rxoutclk_out                         ( pipe_rxoutclk_out ),
+    .pipe_pclk_sel_out                         ( pipe_pclk_sel_out ),
+    .pipe_gen3_out                             ( pipe_gen3_out ),
+
+    //----------------------------------------------------------------------------------------------------------------//
+    // 3. AXI-S Interface                                                                                             //
+    //----------------------------------------------------------------------------------------------------------------//
+
+
+    .user_clk_out                              ( trn_clk ),
+    .user_reset_out                            ( user_reset_out ),
+    .user_lnk_up                               ( trn_lnk_up ),
+
+    // Tx
+    .tx_buf_av                                 ( trn_tbuf_av ),
+    .tx_cfg_req                                ( ),
+    .tx_err_drop                               ( trn_tdst_dsc ),
+    .tx_cfg_gnt                                ( 1'b1 ),
+
+    .s_axis_tx_tdata                           ( s_axis_tx_tdata ),
+    .s_axis_tx_tvalid                          ( s_axis_tx_tvalid ),
+    .s_axis_tx_tready                          ( s_axis_tx_tready ),
+    .s_axis_tx_tkeep                           ( s_axis_tx_tkeep ),
+    .s_axis_tx_tlast                           ( s_axis_tx_tlast ),
+    .s_axis_tx_tuser                           ( s_axis_tx_tuser ),
+
+    // Rx
+    .m_axis_rx_tdata                           ( m_axis_rx_tdata ),
+    .m_axis_rx_tvalid                          ( m_axis_rx_tvalid ),
+    .m_axis_rx_tready                          ( m_axis_rx_tready ),
+    .m_axis_rx_tkeep                           ( m_axis_rx_tkeep ),
+    .m_axis_rx_tlast                           ( m_axis_rx_tlast ),
+    .m_axis_rx_tuser                           ( m_axis_rx_tuser ),
+    .rx_np_ok                                  ( 1'b1 ),
+    .rx_np_req                                 ( 1'b1 ),
+
+    .fc_cpld                                   ( ),
+    .fc_cplh                                   ( ),
+    .fc_npd                                    ( ),
+    .fc_nph                                    ( ),
+    .fc_pd                                     ( ),
+    .fc_ph                                     ( ),
+    .fc_sel                                    ( 3'b0 ),
+
+    //----------------------------------------------------------------------------------------------------------------//
+    // 4. Configuration (CFG) Interface                                                                               //
+    //----------------------------------------------------------------------------------------------------------------//
+
+
+    .cfg_status                                 ( cfg_status ),
+    .cfg_command                                ( cfg_command ),
+    .cfg_dstatus                                ( cfg_dstatus ),
+    .cfg_dcommand                               ( cfg_dcommand ),
+    .cfg_lstatus                                ( cfg_lstatus ),
+    .cfg_lcommand                               ( cfg_lcommand ),
+    .cfg_dcommand2                              ( ),
+    .cfg_pcie_link_state                        ( cfg_pcie_link_state ),
+
+    .cfg_pmcsr_pme_en                           ( ),
+    .cfg_pmcsr_pme_status                       ( ),
+    .cfg_pmcsr_powerstate                       ( ),
+    .cfg_received_func_lvl_rst                  ( ),
+
+    .cfg_mgmt_do                                ( cfg_do ),
+    .cfg_mgmt_rd_wr_done                        ( cfg_rd_wr_done ),
+    .cfg_mgmt_di                                ( cfg_di ),
+    .cfg_mgmt_byte_en                           ( ~cfg_byte_en_n ),
+    .cfg_mgmt_dwaddr                            ( cfg_dwaddr ),
+    .cfg_mgmt_wr_en                             ( ~cfg_wr_en_n ),
+    .cfg_mgmt_rd_en                             ( ~cfg_rd_en_n ),
+    .cfg_mgmt_wr_readonly                       ( 1'b0 ),
+
+    .cfg_err_ecrc                               ( ~cfg_err_ecrc_n ),
+    .cfg_err_ur                                 ( ~cfg_err_ur_n ),
+    .cfg_err_cpl_timeout                        ( ~cfg_err_cpl_timeout_n ),
+    .cfg_err_cpl_unexpect                       ( ~cfg_err_cpl_unexpect_n ),
+    .cfg_err_cpl_abort                          ( ~cfg_err_cpl_abort_n ),
+    .cfg_err_posted                             ( ~cfg_err_posted_n ),
+    .cfg_err_cor                                ( ~cfg_err_cor_n ),
+
+    .cfg_err_atomic_egress_blocked              ( 1'b0 ),
+    .cfg_err_internal_cor                       ( 1'b0 ),
+    .cfg_err_malformed                          ( 1'b0 ),
+    .cfg_err_mc_blocked                         ( 1'b0 ),
+    .cfg_err_poisoned                           ( 1'b0 ),
+    .cfg_err_norecovery                         ( 1'b0 ),
+    .cfg_err_tlp_cpl_header                     ( cfg_err_tlp_cpl_header ),
+    .cfg_err_cpl_rdy                            ( ),
+    .cfg_err_locked                             ( 1'b0 ),
+    .cfg_err_acs                                ( 1'b0 ),
+    .cfg_err_internal_uncor                     ( 1'b0 ),
+    .cfg_trn_pending                            ( ~cfg_trn_pending_n ),
+
+    .cfg_pm_halt_aspm_l0s                       ( 1'b0 ),
+    .cfg_pm_halt_aspm_l1                        ( 1'b0 ),
+
+    .cfg_pm_force_state_en                      ( 1'b0 ),
+    .cfg_pm_force_state                         ( 2'b00 ),
+
+    .cfg_dsn                                    ( 64'h0 ),
+    .cfg_msg_received                           ( ),
+    .cfg_msg_data                               ( ),
+
+    .cfg_interrupt                              ( 1'b0 ),
+    .cfg_interrupt_rdy                          ( ),
+    .cfg_interrupt_assert                       ( 1'b0 ),
+    .cfg_interrupt_di                           ( 8'h0 ),
+
+    .cfg_interrupt_do                           ( ),
+    .cfg_interrupt_mmenable                     ( ),
+    .cfg_interrupt_msienable                    ( ),
+    .cfg_interrupt_msixenable                   ( ),
+    .cfg_interrupt_msixfm                       ( ),
+    .cfg_interrupt_stat                         ( 1'b0 ),
+    .cfg_pciecap_interrupt_msgnum               ( 5'h00 ),
+
+    .cfg_to_turnoff                             ( ),
+    .cfg_turnoff_ok                             ( 1'b0 ),
+    .cfg_bus_number                             ( ),
+    .cfg_device_number                          ( ),
+    .cfg_function_number                        ( ),
+    .cfg_pm_wake                                ( 1'b0 ),
+    .cfg_msg_received_pm_as_nak                 ( ),
+    .cfg_msg_received_setslotpowerlimit         ( ),
+
+    .cfg_pm_send_pme_to                         ( 1'b0 ),
+    .cfg_ds_bus_number                          ( 8'h0 ),
+    .cfg_ds_device_number                       ( 5'h0 ),
+    .cfg_ds_function_number                     ( 3'b000 ),
+
+    .cfg_mgmt_wr_rw1c_as_rw                     ( 1'b0 ),
+
+    .cfg_bridge_serr_en                         ( ),
+    .cfg_slot_control_electromech_il_ctl_pulse  ( ),
+    .cfg_root_control_syserr_corr_err_en        ( ),
+    .cfg_root_control_syserr_non_fatal_err_en   ( ),
+    .cfg_root_control_syserr_fatal_err_en       ( ),
+    .cfg_root_control_pme_int_en                ( ),
+    .cfg_aer_rooterr_corr_err_reporting_en      ( ),
+    .cfg_aer_rooterr_non_fatal_err_reporting_en ( ),
+    .cfg_aer_rooterr_fatal_err_reporting_en     ( ),
+    .cfg_aer_rooterr_corr_err_received          ( ),
+    .cfg_aer_rooterr_non_fatal_err_received     ( ),
+    .cfg_aer_rooterr_fatal_err_received         ( ),
+
+    .cfg_msg_received_err_cor                   ( ),
+    .cfg_msg_received_err_non_fatal             ( ),
+    .cfg_msg_received_err_fatal                 ( ),
+    .cfg_msg_received_pm_pme                    ( ),
+    .cfg_msg_received_pme_to_ack                ( ),
+    .cfg_msg_received_assert_int_a              ( ),
+    .cfg_msg_received_assert_int_b              ( ),
+    .cfg_msg_received_assert_int_c              ( ),
+    .cfg_msg_received_assert_int_d              ( ),
+    .cfg_msg_received_deassert_int_a            ( ),
+    .cfg_msg_received_deassert_int_b            ( ),
+    .cfg_msg_received_deassert_int_c            ( ),
+    .cfg_msg_received_deassert_int_d            ( ),
+
+    //----------------------------------------------------------------------------------------------------------------//
+    // 5. Physical Layer Control and Status (PL) Interface                                                            //
+    //----------------------------------------------------------------------------------------------------------------//
+
+    .pl_directed_link_change                    ( pl_directed_link_change ),
+    .pl_directed_link_speed                     ( pl_directed_link_speed ),
+    .pl_directed_link_width                     ( pl_directed_link_width ),
+    .pl_directed_link_auton                     ( pl_directed_link_auton ),
+    .pl_upstream_prefer_deemph                  ( pl_upstream_prefer_deemph ),
+
+    .pl_sel_lnk_rate                            ( pl_sel_link_rate ),
+    .pl_sel_lnk_width                           ( pl_sel_link_width ),
+    .pl_ltssm_state                             ( pl_ltssm_state ),
+    .pl_lane_reversal_mode                      ( pl_lane_reversal_mode ),
+
+    .pl_phy_lnk_up                              ( ),
+    .pl_tx_pm_state                             ( ),
+    .pl_rx_pm_state                             ( ),
+
+    .pl_link_upcfg_cap                         ( pl_link_upcfg_capable ),
+    .pl_link_gen2_cap                          ( pl_link_gen2_capable ),
+    .pl_link_partner_gen2_supported            ( pl_link_partner_gen2_supported ),
+    .pl_initial_link_width                     ( pl_initial_link_width ),
+
+    .pl_directed_change_done                   ( ),
+
+    .pl_received_hot_rst                       ( ),
+
+    .pl_downstream_deemph_source               ( 1'b0 ),
+    .pl_transmit_hot_rst                       ( 1'b0 ),
+
+    //----------------------------------------------------------------------------------------------------------------//
+    // 6. AER Interface                                                                                               //
+    //----------------------------------------------------------------------------------------------------------------//
+
+    .cfg_err_aer_headerlog                     ( 128'b0 ),
+    .cfg_aer_interrupt_msgnum                  ( 5'b0 ),
+    .cfg_err_aer_headerlog_set                 ( ),
+    .cfg_aer_ecrc_check_en                     ( ),
+    .cfg_aer_ecrc_gen_en                       ( ),
+
+    //----------------------------------------------------------------------------------------------------------------//
+    // 7. VC interface                                                                                                //
+    //----------------------------------------------------------------------------------------------------------------//
+
+    .cfg_vc_tcvc_map                           ( ),
+
+    //----------------------------------------------------------------------------------------------------------------//
+    // 8. System  (SYS) Interface                                                                                     //
+    //----------------------------------------------------------------------------------------------------------------//
+    .common_commands_in           ( 12'b0 ), 
+    .pipe_rx_0_sigs               ( 25'b0 ), 
+    .pipe_rx_1_sigs               ( 25'b0 ), 
+    .pipe_rx_2_sigs               ( 25'b0 ), 
+    .pipe_rx_3_sigs               ( 25'b0 ), 
+    .pipe_rx_4_sigs               ( 25'b0 ), 
+    .pipe_rx_5_sigs               ( 25'b0 ), 
+    .pipe_rx_6_sigs               ( 25'b0 ), 
+    .pipe_rx_7_sigs               ( 25'b0 ), 
+                                                       
+    .common_commands_out          (  ), 
+    .pipe_tx_0_sigs               (  ), 
+    .pipe_tx_1_sigs               (  ), 
+    .pipe_tx_2_sigs               (  ), 
+    .pipe_tx_3_sigs               (  ), 
+    .pipe_tx_4_sigs               (  ), 
+    .pipe_tx_5_sigs               (  ), 
+    .pipe_tx_6_sigs               (  ), 
+    .pipe_tx_7_sigs               (  ), 
+
+    .pipe_mmcm_rst_n                           ( 1'b1 ),        // Async      | Async
+    .sys_clk                                   ( sys_clk ),
+    .sys_rst_n                                 ( sys_rst_n )
+
+  );
+
+// User Application Instances
+
+// Rx User Application Interface
+
+  pci_exp_usrapp_rx # (
+     .C_DATA_WIDTH(                      C_DATA_WIDTH)
+  ) rx_usrapp (
+
+    .trn_clk                             (trn_clk),
+    .trn_reset_n                         (trn_reset_n),
+    .trn_lnk_up_n                        (~trn_lnk_up),
+
+    .trn_rd(trn_rd),
+    .trn_rrem_n                          ( ~trn_rrem ),
+    .trn_rsof_n                          ( ~trn_rsof ),
+    .trn_reof_n                          ( ~trn_reof ),
+    .trn_rsrc_rdy_n                      ( ~trn_rsrc_rdy ),
+    .trn_rsrc_dsc_n                      ( ~trn_rsrc_dsc ),
+    .trn_rdst_rdy_n                      ( trn_rdst_rdy_n ),
+    .trn_rerrfwd_n                       ( ~trn_rerrfwd ),
+    .trn_rnp_ok_n                        ( trn_rnp_ok_n ),
+    .trn_rbar_hit_n                      ( ~trn_rbar_hit )
+  );
+
+  // Tx User Application Interface
+  pci_exp_usrapp_tx # (
+
+    .LINK_CAP_MAX_LINK_SPEED         ( LINK_CAP_MAX_LINK_SPEED )
+
+  ) tx_usrapp (
+
+    .trn_clk                         ( trn_clk ),
+    .trn_reset_n                     ( trn_reset_n ),
+    .trn_lnk_up_n                    ( ~trn_lnk_up ),
+
+    .trn_td                          ( trn_td ),
+    .trn_trem_n                      ( trn_trem_n ),
+    .trn_tsof_n                      ( trn_tsof_n ),
+    .trn_teof_n                      ( trn_teof_n ),
+    .trn_terrfwd_n                   ( trn_terrfwd_n ),
+    .trn_tsrc_rdy_n                  ( trn_tsrc_rdy_n ),
+    .trn_tdst_rdy_n                  ( ~trn_tdst_rdy ),
+    .trn_tsrc_dsc_n                  ( trn_tsrc_dsc_n ),
+    .trn_tdst_dsc_n                  ( ~trn_tdst_dsc ),
+    .trn_tbuf_av                     ( trn_tbuf_av ),
+    .speed_change_done_n             ( speed_change_done_n )
+
+  );
+
+  // Cfg UsrApp
+
+  pci_exp_usrapp_cfg cfg_usrapp (
+
+
+    .trn_clk                         ( trn_clk ),
+    .trn_reset_n                     ( trn_reset_n ),
+
+    .cfg_do                          ( cfg_do ),
+    .cfg_di                          ( cfg_di ),
+    .cfg_byte_en_n                   ( cfg_byte_en_n ),
+    .cfg_dwaddr                      ( cfg_dwaddr ),
+    .cfg_wr_en_n                     ( cfg_wr_en_n ),
+    .cfg_rd_en_n                     ( cfg_rd_en_n ),
+    .cfg_rd_wr_done_n                ( ~cfg_rd_wr_done ),
+
+    .cfg_err_cor_n                   ( cfg_err_cor_n ),
+    .cfg_err_ur_n                    ( cfg_err_ur_n ),
+    .cfg_err_ecrc_n                  ( cfg_err_ecrc_n ),
+    .cfg_err_cpl_timeout_n           ( cfg_err_cpl_timeout_n ),
+    .cfg_err_cpl_abort_n             ( cfg_err_cpl_abort_n ),
+    .cfg_err_cpl_unexpect_n          ( cfg_err_cpl_unexpect_n ),
+    .cfg_err_posted_n                ( cfg_err_posted_n ),
+    .cfg_err_tlp_cpl_header          ( cfg_err_tlp_cpl_header ),
+    .cfg_interrupt_n                 ( cfg_interrupt_n ),
+    .cfg_interrupt_rdy_n             ( ~cfg_interrupt_rdy ),
+    .cfg_turnoff_ok_n                ( ),
+    .cfg_pm_wake_n                   ( ),
+    .cfg_to_turnoff_n                ( 1'b1 ),
+    .cfg_bus_number                  ( 8'h0 ),
+    .cfg_device_number               ( 5'h0 ),
+    .cfg_function_number             ( 3'h0 ),
+    .cfg_status                      ( cfg_status ),
+    .cfg_command                     ( cfg_command ),
+    .cfg_dstatus                     ( cfg_dstatus ),
+    .cfg_dcommand                    ( cfg_dcommand ),
+    .cfg_lstatus                     ( cfg_lstatus ),
+    .cfg_lcommand                    ( cfg_lcommand ),
+    .cfg_pcie_link_state_n           ( ~cfg_pcie_link_state ),
+    .cfg_trn_pending_n               ( cfg_trn_pending_n )
+
+  );
+
+  // Common UsrApp
+
+  pci_exp_usrapp_com com_usrapp   ();
+
+  // PL UsrApp
+
+  pci_exp_usrapp_pl # (
+    .LINK_CAP_MAX_LINK_SPEED         (LINK_CAP_MAX_LINK_SPEED)
+  ) pl_usrapp (
+
+    .pl_initial_link_width           ( pl_initial_link_width ),
+    .pl_lane_reversal_mode           ( pl_lane_reversal_mode ),
+    .pl_link_gen2_capable            ( pl_link_gen2_capable ),
+    .pl_link_partner_gen2_supported  ( pl_link_partner_gen2_supported ),
+    .pl_link_upcfg_capable           ( pl_link_upcfg_capable ),
+    .pl_ltssm_state                  ( pl_ltssm_state ),
+    .pl_received_hot_rst             ( 1'b0 ),
+    .pl_sel_link_rate                ( pl_sel_link_rate ),
+    .pl_sel_link_width               ( pl_sel_link_width ),
+    .pl_directed_link_auton          ( pl_directed_link_auton ),
+    .pl_directed_link_change         ( pl_directed_link_change ),
+    .pl_directed_link_speed          ( pl_directed_link_speed ),
+    .pl_directed_link_width          ( pl_directed_link_width ),
+    .pl_upstream_prefer_deemph       ( pl_upstream_prefer_deemph ),
+    .speed_change_done_n             ( speed_change_done_n),
+
+    .trn_lnk_up_n                    ( ~trn_lnk_up ),
+    .trn_clk                         ( trn_clk ),
+    .trn_reset_n                     ( trn_reset_n )
+
+  );
+
+  //-------------------------------------------------------------------------------------------------//
+  //     PCIe AXI TRN Bridge                                                                         //
+  //-------------------------------------------------------------------------------------------------//
+
+  pcie_axi_trn_bridge #(
+    .C_DATA_WIDTH                    ( C_DATA_WIDTH )
+  ) pcie_axi_trn_bridge_i (
+    .user_clk                        ( trn_clk ),
+    .user_reset                      ( ~trn_reset_n ),
+    .user_lnk_up                     ( trn_lnk_up ),
+
+    .s_axis_tx_tdata                 ( s_axis_tx_tdata ),
+    .s_axis_tx_tvalid                ( s_axis_tx_tvalid ),
+    .s_axis_tx_tready                ( s_axis_tx_tready ),
+    .s_axis_tx_tkeep                 ( s_axis_tx_tkeep ),
+    .s_axis_tx_tlast                 ( s_axis_tx_tlast ),
+    .s_axis_tx_tuser                 ( s_axis_tx_tuser ),
+
+    .m_axis_rx_tdata                 ( m_axis_rx_tdata ),
+    .m_axis_rx_tvalid                ( m_axis_rx_tvalid ),
+    .m_axis_rx_tready                ( m_axis_rx_tready ),
+    .m_axis_rx_tkeep                 ( m_axis_rx_tkeep ),
+    .m_axis_rx_tlast                 ( m_axis_rx_tlast ),
+    .m_axis_rx_tuser                 ( m_axis_rx_tuser ),
+
+    .trn_td                          ( trn_td ),
+    .trn_tsof                        ( ~trn_tsof_n ),
+    .trn_teof                        ( ~trn_teof_n ),
+    .trn_tsrc_rdy                    ( ~trn_tsrc_rdy_n ),
+    .trn_tdst_rdy                    ( trn_tdst_rdy ),
+    .trn_tsrc_dsc                    ( ~trn_tsrc_dsc_n ),
+    .trn_trem                        ( ~trn_trem_n ),
+    .trn_terrfwd                     ( ~trn_terrfwd_n ),
+    .trn_tstr                        ( 1'b0 ),
+    .trn_tecrc_gen                   ( 1'b0 ),
+
+    .trn_rd                          ( trn_rd ),
+    .trn_rsof                        ( trn_rsof ),
+    .trn_reof                        ( trn_reof ),
+    .trn_rsrc_rdy                    ( trn_rsrc_rdy ),
+    .trn_rdst_rdy                    ( ~trn_rdst_rdy_n ),
+    .trn_rsrc_dsc                    ( trn_rsrc_dsc ),
+    .trn_rrem                        ( trn_rrem ),
+    .trn_rerrfwd                     ( trn_rerrfwd ),
+    .trn_rbar_hit                    ( trn_rbar_hit )
+  );
+
+
+endmodule

src/src/PulseMeas/ActivePortSelector.v

@@ -0,0 +1,152 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	ActivePortSelector	
+#(	
+	parameter	PortsNum	=	4
+)
+(
+	input	Rst_i,
+	
+	input	Mod_i,
+	input	[PortsNum-1:0]	Ctrl_i,
+	
+	output	reg	[PortsNum-1:0]	Ctrl_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+//================================================================================
+	localparam	LutNum		=	2**PortsNum;
+	localparam	PortsNone	=	4'b0000;
+	localparam	Ports_1		=	4'b0001;
+	localparam	Ports_2		=	4'b0010;
+	localparam	Ports_21	=	4'b0011;
+	localparam	Ports_3		=	4'b0100;
+	localparam	Ports_31	=	4'b0101;
+	localparam	Ports_32	=	4'b0110;
+	localparam	Ports_321	=	4'b0111;
+	localparam	Ports_4		=	4'b1000;
+	localparam	Ports_41	=	4'b1001;
+	localparam	Ports_42	=	4'b1010;
+	localparam	Ports_421	=	4'b1011;
+	localparam	Ports_43	=	4'b1100;
+	localparam	Ports_431	=	4'b1101;
+	localparam	Ports_432	=	4'b1110;
+	localparam	Ports_4321	=	4'b1111;
+	
+//================================================================================
+//	REG/WIRE
+//================================================================================
+	wire		[PortsNum-1:0]	Lut	[LutNum-1:0];
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+	assign	Lut	[0]		=	~(4'b0000);
+	assign	Lut	[1]		=	~({3'b000,Mod_i});
+	assign	Lut	[2]		=	~({2'b00,Mod_i,1'b0});
+	assign	Lut	[3]		=	~({2'b00,Mod_i,Mod_i});
+	assign	Lut	[4]		=	~({1'b0,Mod_i,2'b0});
+	assign	Lut	[5]		=	~({1'b0,Mod_i,1'b0,Mod_i});
+	assign	Lut	[6]		=	~({1'b0,Mod_i,Mod_i,1'b0});
+	assign	Lut	[7]		=	~({1'b0,Mod_i,Mod_i,Mod_i});
+	assign	Lut	[8]		=	~({Mod_i,3'b000});
+	assign	Lut	[9]		=	~({Mod_i,2'b00,Mod_i});
+	assign	Lut	[10]	=	~({Mod_i,1'b0,Mod_i,1'd0});
+	assign	Lut	[11]	=	~({Mod_i,1'b0,Mod_i,Mod_i});
+	assign	Lut	[12]	=	~({Mod_i,Mod_i,2'b00});
+	assign	Lut	[13]	=	~({Mod_i,Mod_i,1'b0,Mod_i});
+	assign	Lut	[14]	=	~({Mod_i,Mod_i,Mod_i,1'b0});
+	assign	Lut	[15]	=	~({Mod_i,Mod_i,Mod_i,Mod_i});
+
+//================================================================================
+//  CODING
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		case	(Ctrl_i)
+			PortsNone:	begin
+							Ctrl_o	=	Lut[0];
+						end
+			Ports_1:	begin
+							Ctrl_o	=	Lut[1];
+						end	
+			Ports_2:	begin
+							Ctrl_o	=	Lut[2];
+						end
+			Ports_21:	begin
+							Ctrl_o	=	Lut[3];
+						end	
+			Ports_3:	begin
+							Ctrl_o	=	Lut[4];
+						end		
+			Ports_31:	begin
+							Ctrl_o	=	Lut[5];
+						end	
+			Ports_32:	begin
+							Ctrl_o	=	Lut[6];
+						end	
+			Ports_321:	begin
+							Ctrl_o	=	Lut[7];
+						end
+			Ports_4:	begin
+							Ctrl_o	=	Lut[8];
+						end		
+			Ports_41:	begin
+							Ctrl_o	=	Lut[9];
+						end	
+			Ports_42:	begin
+							Ctrl_o	=	Lut[10];
+						end	
+			Ports_421:	begin
+							Ctrl_o	=	Lut[11];
+						end
+			Ports_43:	begin
+							Ctrl_o	=	Lut[12];
+						end	
+			Ports_431:	begin
+							Ctrl_o	=	Lut[13];
+						end
+			Ports_432:	begin
+							Ctrl_o	=	Lut[14];
+						end
+			Ports_4321:	begin
+							Ctrl_o	=	Lut[15];
+						end
+		endcase
+	end	else	begin
+		Ctrl_o	=	4'd0;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/MeasStartEventGen.v

@@ -0,0 +1,126 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)	
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//commands:
+//	ExtTrigUsage: 0 - no, 1 - yes.
+//
+//
+//
+//
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	MeasStartEventGen	
+#(	
+	parameter	CmdRegWidth	=	32
+)
+(
+	input	Clk_i,
+	input	Rst_i,
+
+	input	MeasTrig_i,
+	input	StartMeasDsp_i,
+	
+	output	StartMeasEvent_o,
+	output	InitTrig_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+	reg		startMeasEventVal;
+	reg		startMeasEvent;
+	reg		initTrig;
+	
+	reg		measTrigReg;
+	wire	measTrigPos;
+//================================================================================
+//  ASSIGNMENTS
+	assign	measTrigPos			=	(!measTrigReg&MeasTrig_i);
+	assign	StartMeasEvent_o	=	startMeasEvent;
+	assign	InitTrig_o			=	initTrig;
+//================================================================================
+//  CODING
+
+	always	@(posedge	Clk_i)	begin
+		if	(!Rst_i)	begin
+			measTrigReg	 <=	MeasTrig_i;
+		end	else	begin
+			measTrigReg	 <=	0;
+		end
+	end
+	
+	always	@(posedge Clk_i)	begin
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(measTrigPos)	begin
+					startMeasEventVal	<=	1'b1;
+				end 
+			end	else	begin
+				startMeasEventVal	<=	0;
+			end
+		end	else	begin
+			startMeasEventVal	<=	0;
+		end
+	end
+	
+	always	@(*)	begin
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(startMeasEventVal)	begin
+					startMeasEvent	=	measTrigReg;
+				end else begin
+					startMeasEvent	=	0;
+				end
+			end	else	begin
+				startMeasEvent	=	0;
+			end
+		end	else	begin
+			startMeasEvent	=	0;
+		end
+	end
+	
+	always	@(*)	begin
+		if	(!Rst_i)	begin
+			if	(StartMeasDsp_i)	begin
+				if	(MeasTrig_i)	begin
+					initTrig	=	1'b1;
+				end	else	begin
+					initTrig	=	1'b0;
+				end	
+			end	else	begin
+				initTrig	=	0;
+			end
+		end	else	begin
+			initTrig	=	0;
+		end
+	end
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/Mux.v

@@ -0,0 +1,75 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	Mux	
+#(	
+	parameter	CmdRegWidth		=	24,
+	parameter	PGenNum			=	7,
+	parameter	TrigPortsNum	=	6
+)
+(
+	input	Rst_i,
+	
+	input	[CmdRegWidth-28:0]	MuxCtrl_i,
+	
+	input	DspTrigOut_i,
+	input	DspStartCmd_i,
+	input	IntTrig_i,
+	input	IntTrig2_i,
+	input	[PGenNum-1:0]		PulseBus_i,
+	input	[TrigPortsNum-1:0]	ExtPortsBus_i,
+	
+	output	MuxOut_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+//	REG/WIRE
+	reg		muxOut;
+	wire	[PGenNum+TrigPortsNum+5:0]	inputBus	=	{IntTrig2_i,1'b1,1'b0,DspStartCmd_i,DspTrigOut_i,IntTrig_i,ExtPortsBus_i,PulseBus_i};
+//================================================================================
+//  ASSIGNMENTS
+	assign	MuxOut_o	=	muxOut;
+
+//================================================================================
+//  CODING
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		muxOut	=	inputBus[MuxCtrl_i];
+	end	else	begin
+		muxOut	=	1'b0;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/PGenRstGenerator.v

@@ -0,0 +1,117 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    PulseGen 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	PGenRstGenerator	
+#(	
+	parameter	PgenNum	=	7
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	
+	input	[PgenNum-1:0]	PGenRst_i,
+	
+	output	reg	[PgenNum-1:0]	PGenRst_o,
+	output	reg	RstDone_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+//================================================================================
+	localparam	IDLE	=	2'h0;
+	localparam	RST		=	2'h1;
+	localparam	DEL		=	2'h2;
+	
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg	[1:0]	currState;
+	
+	reg	[PgenNum-1:0]	pGenRstReg;
+	
+	wire	orPGenRstReg	=	|pGenRstReg;
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+
+//================================================================================
+//  CODING
+//================================================================================
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		pGenRstReg		<=	PGenRst_i;
+	end	else	begin
+		pGenRstReg		<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		case(currState)
+		IDLE	:	begin
+						if (orPGenRstReg)	begin
+							currState 	<= RST;
+							PGenRst_o	<=	pGenRstReg;
+							RstDone_o	<=	1'b1;
+						end	else begin
+							currState <= IDLE;
+							PGenRst_o	<=	0;
+							RstDone_o	<=	0;
+						end
+					end
+					
+		RST	:		begin
+						if	(RstDone_o)	begin
+							PGenRst_o	<=	0;
+							RstDone_o	<=	0;
+							currState 	<= DEL;
+						end	else begin
+							currState 	<= RST;
+							PGenRst_o	<=	0;
+							RstDone_o	<=	0;
+						end
+					end
+					
+		DEL	:		begin
+						PGenRst_o	<=	0;
+						RstDone_o	<=	0;
+						currState 	<= IDLE;
+					end
+		endcase
+	end	else	begin
+		currState	<=	IDLE;
+		PGenRst_o	<=	0;
+		RstDone_o	<=	0;
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/PulseGen.v

@@ -0,0 +1,314 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    PulseGen 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	PulseGen	
+#(	
+	parameter	CmdRegWidth	=	32
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	EnPulse_i,
+	
+	input	PulsePol_i,
+	input	EnEdge_i,
+	input	[CmdRegWidth-29:0]	Mode_i,
+	input	[CmdRegWidth-1:0]	P1Del_i,
+	input	[CmdRegWidth-1:0]	P2Del_i,
+	input	[CmdRegWidth-1:0]	P3Del_i,
+	input	[CmdRegWidth-1:0]	P1Width_i,
+	input	[CmdRegWidth-1:0]	P2Width_i,
+	input	[CmdRegWidth-1:0]	P3Width_i,
+	
+	output	Pulse_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+	localparam	IDLE	=	2'h0;
+	localparam	DELAY	=	2'h1;
+	localparam	PULSE	=	2'h2;
+	
+	localparam	DISABLED	=	8'd0;
+	localparam	SINGLE		=	8'd1;
+	localparam	DOUBLE		=	8'd2;
+	localparam	TRIPPLE		=	8'd3;
+	localparam	BURST		=	8'd4;
+	localparam	CONTINIOUS	=	8'd5;
+	
+//================================================================================
+	reg		pulse;
+	wire	[31:0]	delArray	[2:0];
+	wire	[31:0]	widthArray	[2:0];
+	
+	reg	[31:0]	pulseCnt;
+	reg	[31:0]	delayCnt;
+	reg	[31:0]	widthCnt;
+	
+	reg	[31:0]	currWidthValue;
+	reg	[31:0]	currDelValue;
+
+	reg	[1:0]	currState;
+	reg	[1:0]	nextState;
+	
+	reg		pulseDone;	
+	wire	delayDone	=	(currState	==	DELAY)?	delayCnt==currDelValue-1:1'b0;	
+	
+	wire	zeroDelay	=	(P1Del_i==0||P1Del_i==1);
+	
+	reg	patternDone;
+
+	reg	enPulseR;
+	
+	wire	enPulsePos	=	(!enPulseR&EnPulse_i);
+	wire	enPulseNeg	=	(enPulseR&!EnPulse_i);
+	
+	wire	enPulse		=	(EnEdge_i)?	enPulseNeg:enPulsePos;
+	wire	enPulseEn	=	(Mode_i	!=	0)?	enPulse:1'b0;
+//================================================================================
+//  ASSIGNMENTS
+	assign	delArray	[0]	=	P1Del_i;
+	assign	delArray	[1]	=	P2Del_i;
+	assign	delArray	[2]	=	P3Del_i;
+	
+	assign	widthArray	[0]	=	P1Width_i;
+	assign	widthArray	[1]	=	P2Width_i;
+	assign	widthArray	[2]	=	P3Width_i;
+	
+	assign	Pulse_o	=	(PulsePol_i)?	~pulse:pulse;
+
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		enPulseR	<=	EnPulse_i;
+	end	else	begin
+		enPulseR	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	>=1 & Mode_i<=3)	begin	
+			if	(currState	!=	IDLE)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end	else	begin
+			if	(currState	==	DELAY)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end
+	end	else	begin
+		delayCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PULSE)	begin
+			widthCnt	<=	widthCnt+1;
+		end	else	begin
+			widthCnt	<=	0;
+		end
+	end	else	begin
+		widthCnt	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PULSE)	begin
+			if	(widthCnt==currWidthValue-1)	begin
+				pulseDone	=	1'b1;
+			end	else	begin
+				pulseDone	=	1'b0;
+			end
+		end	else	begin
+			pulseDone	=	1'b0;
+		end
+	end	else	begin
+		pulseDone	=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(pulseDone)	begin
+			if	(!patternDone)	begin
+				pulseCnt	<=	pulseCnt+1;
+			end	else	begin
+				pulseCnt	<=	0;
+			end
+		end
+	end	else	begin
+		pulseCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	==	0)	begin
+				currDelValue	<=	0;
+				currWidthValue	<=	0;
+		end	else	begin
+			if	(Mode_i	>=1 & Mode_i<=3)	begin
+				currDelValue	<=	delArray[pulseCnt];
+				currWidthValue	<=	widthArray[pulseCnt];
+			end	else	begin
+				if	(Mode_i	==	4|Mode_i	==	5)	begin
+					if	(currState	==	IDLE)	begin
+						currDelValue	<=	delArray[0];
+						currWidthValue	<=	widthArray[0];
+					end	else	if	(currState	==	PULSE	&	pulseDone)	begin
+						currDelValue	<=	delArray[1];
+						currWidthValue	<=	widthArray[0];
+					end	
+				end
+			end
+		end
+	end	else	begin
+		currDelValue	<=	0;
+		currWidthValue	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(currState	!=	IDLE)	begin
+			case(Mode_i)
+				8'd0:	begin
+							patternDone	=	0;
+						end
+				8'd1:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd2:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd3:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd4:	begin
+							patternDone	=	((pulseCnt==P2Width_i-1)&pulseDone);
+						end
+				8'd5:	begin
+							patternDone	=	0;
+						end
+				default	:begin
+							patternDone	=	0;
+						end
+			endcase
+		end	else	begin
+			patternDone	=	0;
+		end
+	end	else	begin
+		patternDone	=	0;
+	end
+end
+
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		currState	<=	nextState;
+	end	else	begin
+		currState	<=	IDLE;
+	end
+end
+
+always	@(*)	begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (enPulseEn)	begin
+						if	(zeroDelay)	begin
+							nextState = PULSE;
+						end	else begin
+							nextState = DELAY;
+						end
+					end	else	begin
+						nextState = IDLE;
+					end
+				end
+				
+	DELAY	:	begin
+					if	(delayDone)	begin
+						nextState = PULSE;
+					end	else begin
+						nextState = DELAY;
+					end
+				end
+
+	PULSE	:	begin
+					if	(pulseDone)	begin
+						if	(!patternDone)	begin
+							nextState  = DELAY;
+						end	else begin
+							nextState  = IDLE;
+						end
+					end	else	begin
+						nextState  = PULSE;
+					end
+				end
+	endcase
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	!=	0)	begin
+			case(currState)
+				IDLE:	begin
+							pulse	=	1'b0;
+						end
+				DELAY:	begin
+							pulse	=	1'b0;
+						end
+				PULSE:	begin
+							pulse	=	1'b1;
+						end
+				default:begin
+							pulse	=	1'b0;
+						end
+			endcase
+		end	else	begin
+			pulse	=	1'b0;
+		end	
+	end	else	begin
+		pulse	=	1'b0;
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/PulseGenNew.v

@@ -0,0 +1,340 @@
+//`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    PulseGen 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	PulseGenNew	
+#(	
+	parameter	CmdRegWidth	=	32
+)
+(
+	input	Rst_i,
+	input	Clk_i,
+	input	EnPulse_i,
+	
+	input	PulsePol_i,
+	input	EnEdge_i,
+	input	[CmdRegWidth-29:0]	Mode_i,
+	input	[CmdRegWidth-1:0]	P1Del_i,
+	input	[CmdRegWidth-1:0]	P2Del_i,
+	input	[CmdRegWidth-1:0]	P3Del_i,
+	input	[CmdRegWidth-1:0]	P1Width_i,
+	input	[CmdRegWidth-1:0]	P2Width_i,
+	input	[CmdRegWidth-1:0]	P3Width_i,
+	
+	output	Pulse_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+	localparam	IDLE	=	2'h0;
+	localparam	DELAY	=	2'h1;
+	localparam	PULSE	=	2'h2;
+	
+	localparam	DISABLED	=	8'd0;
+	localparam	SINGLE		=	8'd1;
+	localparam	DOUBLE		=	8'd2;
+	localparam	TRIPPLE		=	8'd3;
+	localparam	BURST		=	8'd4;
+	localparam	CONTINIOUS	=	8'd5;
+	
+//================================================================================
+	reg		pulse;
+	wire	[31:0]	delArray	[2:0];
+	wire	[31:0]	widthArray	[2:0];
+	
+	reg	[31:0]	pulseCnt;
+	reg	[31:0]	delayCnt;
+	reg	[31:0]	widthCnt;
+	
+	reg	[31:0]	currWidthValue;
+	reg	[31:0]	currDelValue;
+
+	reg	[1:0]	currState;
+	reg	[1:0]	nextState;
+	
+	reg		pulseDone;	
+	reg		delayDone;	
+	// wire	delayDone	=	(currState	==	DELAY)?	delayCnt==currDelValue-1:1'b0;	
+	
+	// wire	zeroDelay	=	(P1Del_i==0||P1Del_i==1);
+	wire	zeroDelay	=	(P1Del_i==0);
+	wire	singleDelay	=	(P1Del_i==1);
+	
+	reg	patternDone;
+
+	reg	enPulseR;
+	
+	wire	enPulsePos	=	(!enPulseR&EnPulse_i);
+	wire	enPulseNeg	=	(enPulseR&!EnPulse_i);
+	
+	wire	enPulse		=	(EnEdge_i)?	enPulseNeg:enPulsePos;
+	wire	enPulseEn	=	(Mode_i	!=	0)?	enPulse:1'b0;
+//================================================================================
+//  ASSIGNMENTS
+	assign	delArray	[0]	=	P1Del_i;
+	assign	delArray	[1]	=	P2Del_i;
+	assign	delArray	[2]	=	P3Del_i;
+	
+	assign	widthArray	[0]	=	P1Width_i;
+	assign	widthArray	[1]	=	P2Width_i;
+	assign	widthArray	[2]	=	P3Width_i;
+	
+	assign	Pulse_o	=	(PulsePol_i)?	~pulse:pulse;
+
+//================================================================================
+//  CODING
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i==0)	begin
+			delayDone=1'b0;
+		end	else	if	(Mode_i	>=1 & Mode_i<=3)	begin
+			delayDone=(delayCnt==currDelValue-2);
+		end	else	begin
+			delayDone=(delayCnt==currDelValue-1);
+		end
+	end	else	begin
+		delayDone=1'b0;
+	end
+end
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		enPulseR	<=	EnPulse_i;
+	end	else	begin
+		enPulseR	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	>=1 & Mode_i<=3)	begin	
+			if	(currState	!=	IDLE)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end	else	begin
+			if	(currState	==	DELAY)	begin
+				delayCnt	<=	delayCnt+1;
+			end	else	begin
+				delayCnt	<=	0;
+			end
+		end
+	end	else	begin
+		delayCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(pulse)	begin
+			widthCnt	<=	widthCnt+1;
+		end	else	begin
+			widthCnt	<=	0;
+		end
+	end	else	begin
+		widthCnt	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(pulse)	begin
+			if	(widthCnt==currWidthValue-1)	begin
+				pulseDone	=	1'b1;
+			end	else	begin
+				pulseDone	=	1'b0;
+			end
+		end	else	begin
+			pulseDone	=	1'b0;
+		end
+	end	else	begin
+		pulseDone	=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(pulseDone)	begin
+			if	(!patternDone)	begin
+				pulseCnt	<=	pulseCnt+1;
+			end	else	begin
+				pulseCnt	<=	0;
+			end
+		end
+	end	else	begin
+		pulseCnt	<=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	==	0)	begin
+				currDelValue	=	0;
+				currWidthValue	=	0;
+		end	else	begin
+			if	(Mode_i	>=1 & Mode_i<=3)	begin
+				currDelValue	=	delArray[pulseCnt];
+				currWidthValue	=	widthArray[pulseCnt];
+			end	else	begin
+				if	(Mode_i	==	4|Mode_i	==	5)	begin
+					if	(pulseCnt==0)	begin
+						currDelValue	=	delArray[0];
+						currWidthValue	=	widthArray[0];
+					end	else	begin
+						currDelValue	=	delArray[1];
+						currWidthValue	=	widthArray[0];
+					end	
+				end
+			end
+		end
+	end	else	begin
+		currDelValue	=	0;
+		currWidthValue	=	0;
+	end
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		// if	(currState	!=	IDLE)	begin
+			case(Mode_i)
+				8'd0:	begin
+							patternDone	=	0;
+						end
+				8'd1:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd2:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd3:	begin
+							patternDone	=	((pulseCnt==Mode_i-1)&pulseDone);
+						end
+				8'd4:	begin
+							patternDone	=	((pulseCnt==P2Width_i-1)&pulseDone);
+						end
+				8'd5:	begin
+							patternDone	=	0;
+						end
+				default	:begin
+							patternDone	=	0;
+						end
+			endcase
+		// end	else	begin
+			// patternDone	=	0;
+		// end
+	end	else	begin
+		patternDone	=	0;
+	end
+end
+
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		currState	<=	nextState;
+	end	else	begin
+		currState	<=	IDLE;
+	end
+end
+
+always	@(*)	begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (enPulseEn)	begin
+						if	(zeroDelay)	begin
+							if	(currWidthValue==1)	begin
+								nextState = DELAY;
+							end	else begin
+								nextState = PULSE;
+							end
+						end	else	if	(singleDelay)	begin
+							nextState	=	PULSE;
+						end	else	begin
+							nextState	=	DELAY;
+						end
+					end	else	begin
+						nextState = IDLE;
+					end
+				end
+				
+	DELAY	:	begin
+					if	(delayDone)	begin
+						nextState = PULSE;
+					end	else begin
+						nextState = DELAY;
+					end
+				end
+
+	PULSE	:	begin
+					if	(pulseDone)	begin
+						if	(!patternDone)	begin
+							nextState  = DELAY;
+						end	else begin
+							nextState  = IDLE;
+						end
+					end	else	begin
+						nextState  = PULSE;
+					end
+				end
+	endcase
+end
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		if	(Mode_i	!=	0)	begin
+			case(currState)
+				IDLE:	begin
+							if	(zeroDelay&enPulseEn)	begin
+								pulse	=	1'b1;
+							end	else	begin
+								pulse	=	1'b0;
+							end
+						end
+				DELAY:	begin
+							pulse	=	1'b0;
+						end
+				PULSE:	begin
+							pulse	=	1'b1;
+						end
+				default:begin
+							pulse	=	1'b0;
+						end
+			endcase
+		end	else	begin
+			pulse	=	1'b0;
+		end	
+	end	else	begin
+		pulse	=	1'b0;
+	end
+end
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/SampleStrobeGenRstDemux.v

@@ -0,0 +1,91 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	SampleStrobeGenRstDemux	
+#(	
+	parameter	CmdRegWidth		=	24,
+	parameter	PGenNum			=	7,
+	parameter	TrigPortsNum	=	6
+)
+(
+	input	Rst_i,
+	input	[CmdRegWidth-28:0]	MuxCtrl_i,
+	input	GenRst_i,
+	
+	output	[PGenNum-1:0]	RstDemuxOut_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+//	REG/WIRE
+	reg	[PGenNum-1:0]	demuxOut;
+//================================================================================
+//  ASSIGNMENTS
+	assign	RstDemuxOut_o	=	demuxOut;
+
+//================================================================================
+//  CODING
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		case(MuxCtrl_i)
+			5'd0:	begin
+						demuxOut	=	{6'b000000,GenRst_i};
+					end
+			5'd1:	begin
+						demuxOut	=	{5'b00000,GenRst_i,1'b0};
+					end
+			5'd2:	begin
+						demuxOut	=	{5'b0000,GenRst_i,2'b00};
+					end
+			5'd3:	begin
+						demuxOut	=	{3'b000,GenRst_i,3'b000};
+					end
+			5'd4:	begin
+						demuxOut	=	{2'b00,GenRst_i,5'b0000};
+					end
+			5'd5:	begin
+						demuxOut	=	{1'b0,GenRst_i,5'b00000};
+					end
+			5'd6:	begin
+						demuxOut	=	{GenRst_i,6'b000000};
+					end
+			default	:begin
+						demuxOut	=	7'b0000000;
+					end
+		endcase
+	end	else	begin
+		demuxOut	=	0;
+	end
+end
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/PulseMeas/StartAfterGainSel.v

@@ -0,0 +1,103 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 		Churbanov S.
+// 
+// Create Date:    15:24:31 08/20/2019 
+// Design Name: 
+// Module Name:  
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.02 - File Modified
+// Additional Comments: 16.09.2019 file modified in assotiate with task.
+//
+//////////////////////////////////////////////////////////////////////////////////
+module StartAfterGainSel
+#(	
+	parameter	ChNum	=	4
+)	
+(
+	input	Rst_i,	
+	input	[ChNum-1:0]	MeasStart_i,
+	input	[ChNum-1:0]	GainCtrl_i,
+	
+	output	MeasStart_o
+);
+
+//================================================================================
+//  LOCALPARAMS
+
+//================================================================================
+//  REG/WIRE
+	reg	measStart;
+//================================================================================
+//  ASSIGNMENTS
+	assign	MeasStart_o	=	measStart;
+//================================================================================
+//  CODING
+
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		case(GainCtrl_i)
+			4'd0:	begin
+						measStart	=	&MeasStart_i;
+					end
+			4'd1:	begin
+						measStart	=	MeasStart_i[0];
+					end
+			4'd2:	begin
+						measStart	=	MeasStart_i[1];
+					end
+			4'd3:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1];
+					end
+			4'd4:	begin
+						measStart	=	&MeasStart_i[2];
+					end
+			4'd5:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[2];
+					end
+			4'd6:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[2];
+					end
+			4'd7:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[2];
+					end
+			4'd8:	begin
+						measStart	=	MeasStart_i[3];
+					end
+			4'd9:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[3];
+					end
+			4'd10:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[3];
+					end
+			4'd11:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[1]&MeasStart_i[3];
+					end
+			4'd12:	begin
+						measStart	=	MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd13:	begin
+						measStart	=	MeasStart_i[0]&MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd14:	begin
+						measStart	=	MeasStart_i[1]&MeasStart_i[2]&MeasStart_i[3];
+					end
+			4'd15:	begin
+						measStart	=	&MeasStart_i;
+					end		
+			default:	begin
+							measStart	=	&MeasStart_i;
+						end
+		endcase
+	end
+end
+
+endmodule

src/src/PulseMeas/TrigInt2Mux.v

@@ -0,0 +1,67 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:02:35 04/20/2020 
+// Design Name: 
+// Module Name:    mult_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module	TrigInt2Mux	
+#(	
+	parameter	PGenNum			=	7
+)
+(
+	input	Rst_i,
+	
+	input	[3:0]	MuxCtrl_i,
+	input	[PGenNum-1:0]	PulseBus_i,
+	
+	output	MuxOut_o
+);	
+
+//================================================================================
+//  LOCALPARAM
+
+//================================================================================
+//	REG/WIRE
+	reg		muxOut;
+	
+//================================================================================
+//  ASSIGNMENTS
+	assign	MuxOut_o	=	muxOut;
+
+//================================================================================
+//  CODING
+always	@(*)	begin
+	if	(!Rst_i)	begin
+		muxOut	=	PulseBus_i[MuxCtrl_i];
+	end	else	begin
+		muxOut	=	1'b0;
+	end
+end
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+

src/src/Sim/S5443TopPulseProfileTb.v

@@ -0,0 +1,680 @@
+`timescale 1ns / 1ps
+
+//=============================================================================================================
+
+//	Тестовая конфигурация:
+//
+//	Режим измерения "Точка в импульсе".
+//	Количество измерений = 1.
+//	Выбраный фильтр = 2МГц.
+//
+//	PG1	->	Reference Sequense Generator.	|	Шаблон 1 имп.
+//	PG2	->	модулятор.						|	Шаблон 1 имп.
+//	PG3	->	Sample Strobe Generator.		|	Шаблон 1 имп.
+//	PG4	->	Gating Generator.				|	Шаблон 1 имп.
+//	
+//	Настройки мультиплексоров генераторов:
+//	PG1MUX_OUT	->	INT_TRIG.
+//	PG2MUX_OUT	->	PG1. Для всех генераторов кроме PG1 сигналом начала работы является выход PG1.
+//	PG3MUX_OUT	->	PG1.
+//	PG4MUX_OUT	->	PG1.
+//	PG5MUX_OUT	->	PG1.
+//	PG6MUX_OUT	->	PG1.
+//	PG7MUX_OUT	->	PG1.
+//	
+//	Настройки остальных мультиплексоров:
+//	MODMUX_OUT			->	PG2.
+//	GATINGMUX_OUT		->	PG4.
+//	SAMPLSTROBEMUX_OUT	->	PG3.
+//	EXTSTARTMUX			->	DSPSTART.
+
+//=============================================================================================================
+module S5443TopPulseProfileTb;
+	
+	localparam	[4:0]	EP1MUXCMD	=	5'd14;
+	localparam	[4:0]	EP2MUXCMD	=	5'd1;
+	localparam	[4:0]	EP3MUXCMD	=	5'd1;
+	localparam	[4:0]	EP4MUXCMD	=	5'd1;
+	localparam	[4:0]	EP5MUXCMD	=	5'd1;
+	localparam	[4:0]	EP6MUXCMD	=	5'd1;
+	
+	localparam	[4:0]	PG1MUXCMD	=	5'd13;
+	localparam	[4:0]	PG2MUXCMD	=	5'd0;
+	localparam	[4:0]	PG3MUXCMD	=	5'd18;
+	localparam	[4:0]	PG4MUXCMD	=	5'd18;
+	localparam	[4:0]	PG5MUXCMD	=	5'd0;
+	localparam	[4:0]	PG6MUXCMD	=	5'd0;
+	localparam	[4:0]	PG7MUXCMD	=	5'd0;
+	
+	localparam	[2:0]	PG1MODE	=	3'd5;
+	localparam	[2:0]	PG2MODE	=	3'd1;
+	localparam	[2:0]	PG3MODE	=	3'd3;
+	localparam	[2:0]	PG4MODE	=	3'd4;
+	localparam	[2:0]	PG5MODE	=	3'd0;
+	localparam	[2:0]	PG6MODE	=	3'd0;
+	localparam	[2:0]	PG7MODE	=	3'd3;
+	
+	localparam	PG1POL	=	1'b0;
+	localparam	PG2POL	=	1'b0;
+	localparam	PG3POL	=	1'b0;
+	localparam	PG4POL	=	1'b0;
+	localparam	PG5POL	=	1'b0;
+	localparam	PG6POL	=	1'b0;
+	localparam	PG7POL	=	1'b0;
+	
+	localparam	[4:0]	EXTTRIGMUXCMD	=	5'd7;
+	// localparam	[4:0]	EXTTRIGMUXCMD	=	5'd15;
+	localparam	[4:0]	DSPTRIGINCMD	=	5'h8;
+	localparam	[4:0]	MUXSLOWMODCMD	=	5'd1;
+	localparam	[4:0]	MUXFASTMODCMD	=	5'd1;
+	localparam	[4:0]	GATINGMUXCMD	=	5'd2;
+	localparam	[4:0]	SMPLSTRBMUXCMD	=	5'd3;
+	
+	//COMMANDS	FOR REG_MAP
+	parameter	[31:0]	MeasCmdBypass	=	{8'h11,8'h0,8'h63,8'h1};
+	parameter	[31:0]	MeasCmdFft 		=	{8'h11,8'h0,8'h63,7'h5,1'b1};
+	// parameter	[31:0]	MeasCmd 		=	{8'h11,8'h0,8'h53,8'h0};
+	parameter	[31:0]	MeasCmd =	{8'h11,8'h3f,8'h72,8'h0};
+	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};
+	parameter	[31:0]	SensCtrlCmd =	{1'b0,27'h0,4'b1};
+	// parameter	[31:0]	DitherCmd 	= {8'h0E,24'h100192};
+	parameter	[31:0]	DitherCmd 	= {8'h0E,8'd9,4'h0,4'h1,4'd11,4'h3};
+	parameter	[31:0]	IfFtwH 	=	{8'h15,16'h0,8'h40};
+	parameter	[31:0]	IfFtwL 	=	{8'h16,24'h000000};
+	parameter	[31:0]	FilterCorrCmdH 		=	{8'h17,24'hD70A3D};
+	parameter	[31:0]	FilterCorrCmdL 		=	{8'h18,24'hD70A3D};
+	
+	//PG7 Cmd
+	parameter	[31:0]	PG7P1DelayRegCmd	=	{8'h20,24'd0};
+	parameter	[31:0]	PG7P2DelayRegCmd	=	{8'h21,24'd1};
+	parameter	[31:0]	PG7P3DelayRegCmd	=	{8'h22,24'd5};
+	parameter	[31:0]	PG7P123DelayRegCmd	=	{8'h23,24'd15};
+	parameter	[31:0]	PG7P1WidthRegCmd	=	{8'h24,24'd1};
+	parameter	[31:0]	PG7P2WidthRegCmd	=	{8'h25,24'd3};
+	parameter	[31:0]	PG7P3WidthRegCmd	=	{8'h26,24'd5};
+	parameter	[31:0]	PG7P123WidthRegCmd	=	{8'h27,24'd0};
+
+	//PG1 Cmd
+	parameter	[31:0]	PG1P1DelayRegCmd	=	{8'h28,24'd0};
+	parameter	[31:0]	PG1P2DelayRegCmd	=	{8'h29,24'd400};
+	parameter	[31:0]	PG1P3DelayRegCmd	=	{8'h2a,24'd0};
+	parameter	[31:0]	PG1P123DelayRegCmd	=	{8'h2b,24'd0};
+	parameter	[31:0]	PG1P1WidthRegCmd	=	{8'h2c,24'd1};
+	parameter	[31:0]	PG1P2WidthRegCmd	=	{8'h2d,24'd0};
+	parameter	[31:0]	PG1P3WidthRegCmd	=	{8'h2e,24'd0};
+	parameter	[31:0]	PG1P123WidthRegCmd	=	{8'h2f,24'd0};
+	
+	//PG2 Cmd
+	parameter	[31:0]	PG2P1DelayRegCmd	=	{8'h20,24'd0};
+	parameter	[31:0]	PG2P2DelayRegCmd	=	{8'h21,24'd1};
+	parameter	[31:0]	PG2P3DelayRegCmd	=	{8'h22,24'd5};
+	parameter	[31:0]	PG2P123DelayRegCmd	=	{8'h23,24'd15};
+	parameter	[31:0]	PG2P1WidthRegCmd	=	{8'h24,24'd1};
+	parameter	[31:0]	PG2P2WidthRegCmd	=	{8'h25,24'd3};
+	parameter	[31:0]	PG2P3WidthRegCmd	=	{8'h26,24'd5};
+	parameter	[31:0]	PG2P123WidthRegCmd	=	{8'h27,24'd0};
+	
+	//PG3 Cmd
+	parameter	[31:0]	PG3P1DelayRegCmd	=	{8'h20,24'd0};
+	parameter	[31:0]	PG3P2DelayRegCmd	=	{8'h21,24'd1};
+	parameter	[31:0]	PG3P3DelayRegCmd	=	{8'h22,24'd5};
+	parameter	[31:0]	PG3P123DelayRegCmd	=	{8'h23,24'd15};
+	parameter	[31:0]	PG3P1WidthRegCmd	=	{8'h24,24'd1};
+	parameter	[31:0]	PG3P2WidthRegCmd	=	{8'h25,24'd3};
+	parameter	[31:0]	PG3P3WidthRegCmd	=	{8'h26,24'd5};
+	parameter	[31:0]	PG3P123WidthRegCmd	=	{8'h27,24'd0};
+	
+	//PG4 Cmd
+	parameter	[31:0]	PG4P1DelayRegCmd	=	{8'h40,24'd0};
+	parameter	[31:0]	PG4P2DelayRegCmd	=	{8'h41,24'd3};
+	parameter	[31:0]	PG4P3DelayRegCmd	=	{8'h42,24'd0};
+	parameter	[31:0]	PG4P123DelayRegCmd	=	{8'h43,24'd0};
+	parameter	[31:0]	PG4P1WidthRegCmd	=	{8'h44,24'd1};
+	parameter	[31:0]	PG4P2WidthRegCmd	=	{8'h45,24'd10};
+	parameter	[31:0]	PG4P3WidthRegCmd	=	{8'h46,24'd7};
+	parameter	[31:0]	PG4P123WidthRegCmd	=	{8'h47,24'd0};
+	
+	//PG5 Cmd
+	parameter	[31:0]	PG5P1DelayRegCmd	=	{8'h48,24'd0};
+	parameter	[31:0]	PG5P2DelayRegCmd	=	{8'h49,24'd0};
+	parameter	[31:0]	PG5P3DelayRegCmd	=	{8'h4a,24'd0};
+	parameter	[31:0]	PG5P123DelayRegCmd	=	{8'h4b,24'd0};
+	parameter	[31:0]	PG5P1WidthRegCmd	=	{8'h4c,24'd0};
+	parameter	[31:0]	PG5P2WidthRegCmd	=	{8'h4d,24'd0};
+	parameter	[31:0]	PG5P3WidthRegCmd	=	{8'h4e,24'd0};
+	parameter	[31:0]	PG5P123WidthRegCmd	=	{8'h4f,24'd0};
+	
+	//PG6 Cmd
+	parameter	[31:0]	PG6P1DelayRegCmd	=	{8'h50,24'd0};
+	parameter	[31:0]	PG6P2DelayRegCmd	=	{8'h51,24'd5};
+	parameter	[31:0]	PG6P3DelayRegCmd	=	{8'h52,24'd15};
+	parameter	[31:0]	PG6P123DelayRegCmd	=	{8'h53,24'd0};
+	parameter	[31:0]	PG6P1WidthRegCmd	=	{8'h54,24'd1};
+	parameter	[31:0]	PG6P2WidthRegCmd	=	{8'h55,24'd3};
+	parameter	[31:0]	PG6P3WidthRegCmd	=	{8'h56,24'd5};
+	parameter	[31:0]	PG6P123WidthRegCmd	=	{8'h57,24'd0};
+	
+	parameter	[31:0]	MeasNum0RegCmd		=	{8'h58,24'd10};
+	parameter	[31:0]	MeasNum1RegCmd		=	{8'h59,MUXSLOWMODCMD,MUXFASTMODCMD,DSPTRIGINCMD,25'd0};
+	parameter	[31:0]	PGMode0RegCmd		=	{8'h0b,3'b0,PG7MODE,PG6MODE,PG5MODE,PG4MODE,PG3MODE,PG2MODE,PG1MODE};
+	parameter	[31:0]	PGMode1RegCmd		=	{8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'h0};
+	
+	parameter	[31:0]	MuxCtrl1RegCmd	=	{8'h1c,4'h0,PG7MUXCMD,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD};
+	parameter	[31:0]	MuxCtrl2RegCmd	=	{8'h1d,4'h0,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD,SMPLSTRBMUXCMD};
+	parameter	[31:0]	MuxCtrl3RegCmd	=	{8'h1e,4'h0,GATINGMUXCMD,EXTTRIGMUXCMD,EP2MUXCMD,EP1MUXCMD};
+	parameter	[31:0]	MuxCtrl4RegCmd	=	{8'h1f,4'h0,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD};
+	
+	//=================================================================================================================================================================================================================
+	
+	reg		Clk41;
+	reg		Clk50;
+	reg		Clk70;
+	
+	reg	[31:0]	tb_cnt=4'd0;
+	reg	rst;
+	reg	mosi_i	=	1'b0;
+	reg	Miso_i	=	1'b0;
+	reg	ss_i;
+	reg	clk_i	=	1'b0;
+	
+	
+	reg	[31:0]	DspSpiData;
+	reg		startCalcCmdReg;
+						
+	wire	[17:0]	cos_value;	
+	wire	[17:0]	sin_value;				
+
+	wire	ExtDspTrigPos0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b1:1'b0;
+	wire	ExtDspTrigNeg0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b0:1'b1;
+	
+	wire	ExtTrigger0		=	ExtDspTrigNeg0;
+	
+	wire	TrigFromDsp		=	(tb_cnt	>=	1100	&&	tb_cnt	<=	1101)?	1'b1:1'b0;
+	wire	endMeas;
+	reg	[31:0]	cmdCnt;
+	
+	reg	trig0;
+	reg	trig1;
+	
+	wire	trig0R;
+    wire	trig1R;
+	
+	assign	trig0R	=	trig0;
+    assign	trig1R	=	trig1;
+	
+	
+	wire [5:0] trig6to1Dir;
+	wire [5:0] trig6to1Test = (tb_cnt >= 3555 & tb_cnt <= 3557) ? 6'h3f:6'b0;
+	wire [5:0] trig6to1 = (!trig6to1Dir) ? trig6to1Test:6'bz;
+//==========================================================================================
+//clocks gen
+	always	#10 Clk50	=	~Clk50;
+	always	#(14.285714285714/2) Clk70	=	~Clk70;
+	always	#10 clk_i	=	~clk_i;
+	always	#(24.390243902439/2)	Clk41	=	~Clk41;
+	
+	wire	sck_i;	
+//==========================================================================================
+initial begin
+	Clk50	=	1'b1;
+	Clk70	=	1'b1;
+	rst		=	1'b1;
+	Clk41	=	1'b0;
+	trig0	=	1'b0;
+	trig1	=	1'b0;
+#100;
+	rst		=	1'b0;
+#400;
+	Clk41	=	1'b0;
+end		
+	
+reg	endMeasReg;
+always	@(posedge	Clk41)	begin
+	endMeasReg	<=	endMeas;
+end
+
+wire	endMeasNeg	=	!endMeas&endMeasReg;
+
+always	@(posedge	Clk70)	begin
+	if	(!rst)	begin
+		if	(!endMeas)	begin
+			if	(tb_cnt	==	3550	|	tb_cnt	==	3950	|tb_cnt	==	4505)	begin
+				startCalcCmdReg	<=	1'b1;
+			end	
+		end	else	begin
+			startCalcCmdReg	<=	1'b0;
+		end
+	end	else	begin
+		startCalcCmdReg	<=	1'b0;
+	end
+end
+
+always	@(negedge	Clk41)	begin
+	if	(!rst)		begin
+		tb_cnt	<=	tb_cnt+1;
+	end	else	begin
+		tb_cnt	<=	0;
+	end
+end
+
+wire	Adc1DataDa0P;
+wire	Adc1DataDa1P;
+
+wire	[31:0]	test	=	32'h2351eb85;
+// wire	[31:0]	test	=	32'h40000000;
+CordicNco		
+#(	.ODatWidth	(18),
+	.PhIncWidth	(32),
+	.IterNum	(10),
+	.EnSinN		(0))
+ncoInst
+(
+	.Clk_i				(Clk50),
+	.Rst_i				(rst),
+	.Val_i				(1'b1),
+	.PhaseInc_i			(test),
+	.WindVal_i			(1'b1),
+	.WinType_i			(),
+	.Wind_o				(),
+	.Sin_o				(sin_value),
+	.Cos_o				(cos_value),
+	.Val_o				()
+);
+
+
+S5443Top MasterFpga 
+(
+	.Clk_i				(Clk50),
+	.Led_o				(),
+//------------------------------------------	
+    .Adc1FclkP_i		(),		
+    .Adc1FclkN_i		(),		
+
+    .Adc1DataDa0P_i		(Adc1DataDa0P),
+	.Adc1DataDa0N_i		(~Adc1DataDa0P),		
+    .Adc1DataDa1P_i		(Adc1DataDa1P),
+    .Adc1DataDa1N_i		(~Adc1DataDa1P),
+
+	.Adc1DataDb0P_i		(Adc1DataDa0P),
+    .Adc1DataDb0N_i		(~Adc1DataDa0P),		
+    .Adc1DataDb1P_i		(Adc1DataDa1P),
+    .Adc1DataDb1N_i		(~Adc1DataDa1P),
+//------------------------------------------	
+    .Adc2FclkP_i		(),		
+    .Adc2FclkN_i		(),		
+
+    .Adc2DataDa0P_i		(1'b1),
+    .Adc2DataDa0N_i		(1'b0),		
+    .Adc2DataDa1P_i		(1'b1),
+    .Adc2DataDa1N_i		(1'b0),
+  
+	.Adc2DataDb0P_i		(1'b1),
+    .Adc2DataDb0N_i		(1'b0),		
+    .Adc2DataDb1P_i		(1'b1),
+    .Adc2DataDb1N_i		(1'b0),
+//------------------------------------------
+	.AdcInitMosi_o		(),
+	.AdcInitClk_o		(),			
+	.Adc1InitCs_o		(),
+	.Adc2InitCs_o		(),
+	.AdcInitRst_o		(),
+//------------------------------------------	
+	
+	.Mosi_i				(mosi_i),
+	.Sck_i				(~sck_i),
+	.Ss_i				(ss_i),
+
+	.LpOutClk_o			(),
+	.LpOutFs_o			(),			
+	.LpOutData_o		(),
+	
+	//fpga-dsp signals
+	.StartMeas_i		(startCalcCmdReg),
+	.StartMeasEvent_o	(startMeasS),
+	.EndMeas_o			(endMeas),
+	.TimersClk_o		(),
+	
+	.Trig6to1_io		(trig6to1),	
+	.Trig6to1Dir_o		(trig6to1Dir),	
+	
+	.DspTrigOut_i		(Clk41),				//Trig from DSP
+	.DspTrigIn_o		(),				//Trig To DSP
+	
+	.OverloadS_i		(1'b0),
+	.Overload_o			(),
+	
+	.PortSel_o			(),
+	.PortSelDir_o		(),
+	
+	//mod out line
+	
+	.Mod_o				(),	
+	
+	//gain lines
+	.DspReadyForRx_i		(1'b0),
+	.DspReadyForRxToFpgaS_o	(),
+	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
+	.AdcData_i				(sin_value[17-:14])
+	// .AdcData_i			(Data_i)
+);
+
+parameter	IDLE	=	2'h0;
+parameter	CMD		=	2'h1;
+parameter	TX		=	2'h2;
+parameter	PAUSE	=	2'h3;
+
+reg	[1:0]	txCurrState;
+reg	[1:0]	txNextState;
+
+wire	txWork	=	tb_cnt	>=	23;
+// wire	txStop	=	(cmdCnt	>=	90)	&	(cmdCnt	>=	70)	&	(cmdCnt	>=	71);
+wire	txStop	=	(cmdCnt	>=	251);
+
+
+reg	[6:0]	txCnt;
+reg	[3:0]	pauseCnt;
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	TX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			DspSpiData		<=	MeasCmd;
+		end	else	if	(cmdCnt	==	1)	begin
+			DspSpiData		<=	IfFtwH;
+		end	else	if	(cmdCnt	==	2)	begin
+			DspSpiData		<=	IfFtwL;
+		end	else	if	(cmdCnt	==	3)	begin
+			DspSpiData		<=	FilterCorrCmdH;
+		end	else	if	(cmdCnt	==	4)	begin
+			DspSpiData		<=	FilterCorrCmdL;
+		end	else	if	(cmdCnt	==	5)	begin
+			DspSpiData		<=	PG1P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	6)	begin
+			DspSpiData		<=	PG1P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	7)	begin
+			DspSpiData		<=	PG1P3DelayRegCmd;
+		end	else	if	(cmdCnt	==	8)	begin
+			DspSpiData		<=	PG1P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	9)	begin
+			DspSpiData		<=	PG1P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	10)	begin
+			DspSpiData		<=	PG1P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	11)	begin
+			DspSpiData		<=	PG1P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	12)	begin
+			DspSpiData		<=	PG1P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	13)	begin
+			DspSpiData		<=	PG2P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	14)	begin
+			DspSpiData		<=	PG2P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	15)	begin
+			DspSpiData		<=	PG2P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	16)	begin
+			DspSpiData		<=	PG2P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	17)	begin
+			DspSpiData		<=	PG2P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	18)	begin
+			DspSpiData		<=	PG2P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	19)	begin
+			DspSpiData		<=	PG2P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	20)	begin
+			DspSpiData		<=	PG2P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	21)	begin
+			DspSpiData		<=	PG3P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	22)	begin
+			DspSpiData		<=	PG3P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	23)	begin
+			DspSpiData		<=	PG3P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	24)	begin
+			DspSpiData		<=	PG3P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	25)	begin
+			DspSpiData		<=	PG3P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	26)	begin
+			DspSpiData		<=	PG3P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	27)	begin
+			DspSpiData		<=	PG3P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	28)	begin
+			DspSpiData		<=	PG3P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	29)	begin
+			DspSpiData		<=	PG4P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	30)	begin
+			DspSpiData		<=	PG4P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	31)	begin
+			DspSpiData		<=	PG4P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	32)	begin
+			DspSpiData		<=	PG4P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	33)	begin
+			DspSpiData		<=	PG4P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	34)	begin
+			DspSpiData		<=	PG4P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	35)	begin
+			DspSpiData		<=	PG4P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	36)	begin
+			DspSpiData		<=	PG4P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	37)	begin
+			DspSpiData		<=	PG5P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	38)	begin
+			DspSpiData		<=	PG5P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	39)	begin
+			DspSpiData		<=	PG5P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	40)	begin
+			DspSpiData		<=	PG5P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	41)	begin
+			DspSpiData		<=	PG5P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	42)	begin
+			DspSpiData		<=	PG5P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	43)	begin
+			DspSpiData		<=	PG5P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	44)	begin
+			DspSpiData		<=	PG5P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	45)	begin
+			DspSpiData		<=	PG6P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	46)	begin
+			DspSpiData		<=	PG6P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	47)	begin
+			DspSpiData		<=	PG6P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	48)	begin
+			DspSpiData		<=	PG6P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	49)	begin
+			DspSpiData		<=	PG6P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	50)	begin
+			DspSpiData		<=	PG6P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	51)	begin
+			DspSpiData		<=	PG6P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	52)	begin
+			DspSpiData		<=	PG6P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	53)	begin
+			DspSpiData		<=	PG7P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	54)	begin
+			DspSpiData		<=	PG7P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	55)	begin
+			DspSpiData		<=	PG7P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	56)	begin
+			DspSpiData		<=	PG7P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	57)	begin
+			DspSpiData		<=	PG7P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	58)	begin
+			DspSpiData		<=	PG7P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	59)	begin
+			DspSpiData		<=	PG7P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	60)	begin
+			DspSpiData		<=	DitherCmd;
+		end	else	if	(cmdCnt	==	61)	begin
+			DspSpiData		<=	MeasNum0RegCmd;
+		end else	if	(cmdCnt	==	62)	begin
+			DspSpiData		<=	MeasNum1RegCmd;
+		end else	if	(cmdCnt	==	63)	begin
+			DspSpiData		<=	PGMode0RegCmd;
+		end	else	if	(cmdCnt	==	64)	begin
+			DspSpiData		<=	PGMode1RegCmd;
+		end	else	if	(cmdCnt	==	65)	begin
+			DspSpiData		<=	MuxCtrl1RegCmd;
+		end	else	if	(cmdCnt	==	66)	begin
+			DspSpiData		<=	MuxCtrl2RegCmd;
+		end	else	if	(cmdCnt	==	67)	begin
+			DspSpiData		<=	MuxCtrl3RegCmd;
+		end	else	if	(cmdCnt	==	68)	begin
+			DspSpiData		<=	AdcCtrl;
+		end	else	if	(cmdCnt	==	99)	begin
+			DspSpiData		<=	{8'h58,24'd100};
+		end	else begin
+			DspSpiData	<=	32'hfffffff;
+		end
+	end	else	if	(txCurrState	==	TX)	begin
+		DspSpiData	<=	DspSpiData<<1;
+	end
+end
+
+always	@(posedge Clk41)	begin
+	if	(txCurrState	==	TX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			mosi_i	<=	DspSpiData[31];
+		end	else	begin
+			mosi_i	<=	1'b1;
+		end
+	end	else	begin
+		mosi_i	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	TX)	begin
+		ss_i	<=	1'b0;
+	end	else	begin
+		ss_i	<=	1'b1;
+	end
+end
+
+assign	sck_i	=	Clk41;
+
+always	@(posedge	Clk41)	begin
+	if	(rst)	begin
+		txCurrState	<=	IDLE;
+	end	else	begin
+		txCurrState	<=	txNextState;
+	end
+end
+
+
+always @(*) begin
+	txNextState	=	IDLE;
+	case(txCurrState)
+	IDLE	:	begin
+					if (txWork)	begin
+						txNextState = CMD;
+					end	else begin
+						txNextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						txNextState = TX;
+					end	else begin
+						txNextState = IDLE;
+					end
+				end
+
+	TX		:	begin
+					if (txCnt==6'd31) begin
+						txNextState  = PAUSE;
+					end	else begin
+						txNextState  = TX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd10) begin
+						txNextState  = CMD;
+					end	else begin
+						txNextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+	reg [13:0] Data_i;
+	real pi = 3.14159265358;
+	real phase = 0;
+	real phaseInc = 0.001;
+	real signal;
+	always @ (posedge Clk50)
+		begin
+			if (tb_cnt >= 4505)
+				begin
+					phase = phase + phaseInc;
+					phaseInc <= phaseInc + 0.0005;
+					signal = $sin(2*pi*phase);
+					Data_i = 2**12 * signal;
+				end
+			else
+				Data_i = 0;
+		end
+		
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/Sim/S5443TopSimpleMeasTb.v

@@ -0,0 +1,731 @@
+`timescale 1ns / 1ps
+
+//=============================================================================================================
+
+//	Тестовая конфигурация:
+//
+//	Режим измерения "Точка в импульсе".
+//	Количество измерений = 1.
+//	Выбраный фильтр = 2МГц.
+//
+//	PG1	->	Reference Sequense Generator.	|	Шаблон 1 имп.
+//	PG2	->	модулятор.						|	Шаблон 1 имп.
+//	PG3	->	Sample Strobe Generator.		|	Шаблон 1 имп.
+//	PG4	->	Gating Generator.				|	Шаблон 1 имп.
+//	
+//	Настройки мультиплексоров генераторов:
+//	PG1MUX_OUT	->	INT_TRIG.
+//	PG2MUX_OUT	->	PG1. Для всех генераторов кроме PG1 сигналом начала работы является выход PG1.
+//	PG3MUX_OUT	->	PG1.
+//	PG4MUX_OUT	->	PG1.
+//	PG5MUX_OUT	->	PG1.
+//	PG6MUX_OUT	->	PG1.
+//	PG7MUX_OUT	->	PG1.
+//	
+//	Настройки остальных мультиплексоров:
+//	MODMUX_OUT			->	PG2.
+//	GATINGMUX_OUT		->	PG4.
+//	SAMPLSTROBEMUX_OUT	->	PG3.
+//	EXTSTARTMUX			->	DSPSTART.
+
+//=============================================================================================================
+module S5443TopSimpleMeasTb;
+	
+	localparam	[31:0]	FIRST	=	{4'b0,14'h2000,14'h2000};
+	localparam	[31:0]	SECOND	=	{4'b0,14'h1fff,14'h2000};
+	localparam	[31:0]	THIRD	=	{4'b0,14'h1fff,14'h1fff};
+	localparam	[31:0]	FOURTH	=	{4'b0,14'h2000,14'h1fff};
+	
+	localparam	[3:0]	EP1MUXCMD	=	4'd1;
+	localparam	[3:0]	EP2MUXCMD	=	4'd1;
+	localparam	[3:0]	EP3MUXCMD	=	4'd1;
+	localparam	[3:0]	EP4MUXCMD	=	4'd1;
+	localparam	[3:0]	EP5MUXCMD	=	4'd1;
+	localparam	[3:0]	EP6MUXCMD	=	4'd1;
+	
+	localparam	[3:0]	PG1MUXCMD	=	4'd13;
+	localparam	[3:0]	PG2MUXCMD	=	4'd0;
+	localparam	[3:0]	PG3MUXCMD	=	4'd0;
+	localparam	[3:0]	PG4MUXCMD	=	4'd0;
+	localparam	[3:0]	PG5MUXCMD	=	4'd0;
+	localparam	[3:0]	PG6MUXCMD	=	4'd0;
+	localparam	[3:0]	PG7MUXCMD	=	4'd0;
+	
+	localparam	[2:0]	PG1MODE	=	3'd1;
+	localparam	[2:0]	PG2MODE	=	3'd1;
+	localparam	[2:0]	PG3MODE	=	3'd1;
+	localparam	[2:0]	PG4MODE	=	3'd1;
+	localparam	[2:0]	PG5MODE	=	3'd0;
+	localparam	[2:0]	PG6MODE	=	3'd0;
+	localparam	[2:0]	PG7MODE	=	3'd0;
+	
+	localparam	PG1POL	=	1'b0;
+	localparam	PG2POL	=	1'b1;
+	localparam	PG3POL	=	1'b1;
+	localparam	PG4POL	=	1'b0;
+	localparam	PG5POL	=	1'b0;
+	localparam	PG6POL	=	1'b0;
+	localparam	PG7POL	=	1'b0;
+	
+	localparam	[3:0]	EXTTRIGMUXCMD	=	4'd15;
+	localparam	[3:0]	MODMUXCMD		=	4'd1;
+	localparam	[3:0]	GATINGMUXCMD	=	4'd2;
+	localparam	[3:0]	SMPLSTRBMUXCMD	=	4'd3;
+	localparam	[3:0]	DTIMUXCMD		=	4'd7;
+	
+	//COMMANDS	FOR REG_MAP
+	parameter	[31:0]	MeasCmd =	{8'h11,8'h1,8'h71,8'h0};
+	parameter	[31:0]	SensCtrlCmd =	{31'h0,1'b0};
+	// parameter	[31:0]	MeasCmd =	{8'h11,8'h0,8'h64,8'h0};
+	parameter	[31:0]	AdcCtrl =	{8'h12,24'h2};
+	parameter	[31:0]	IfFtwH 	=	{8'h15,16'h0,8'h38};
+	parameter	[31:0]	IfFtwL 	=	{8'h16,24'h51eb85};
+	parameter	[31:0]	FilterCorrCmdH 		=	{8'h17,24'hD70A3D};
+	parameter	[31:0]	FilterCorrCmdL 		=	{8'h18,24'hD70A3D};
+	
+	
+
+	//PG1 Cmd
+	parameter	[31:0]	PG1P1DelayRegCmd	=	{8'h28,24'd0};
+	parameter	[31:0]	PG1P2DelayRegCmd	=	{8'h29,24'd0};
+	parameter	[31:0]	PG1P3DelayRegCmd	=	{8'h2a,24'd0};
+	parameter	[31:0]	PG1P123DelayRegCmd	=	{8'h2b,24'd0};
+	parameter	[31:0]	PG1P1WidthRegCmd	=	{8'h2c,24'd1};
+	parameter	[31:0]	PG1P2WidthRegCmd	=	{8'h2d,24'd0};
+	parameter	[31:0]	PG1P3WidthRegCmd	=	{8'h2e,24'd0};
+	parameter	[31:0]	PG1P123WidthRegCmd	=	{8'h2f,24'd0};
+	
+	//PG2 Cmd
+	parameter	[31:0]	PG2P1DelayRegCmd	=	{8'h30,24'd0};
+	parameter	[31:0]	PG2P2DelayRegCmd	=	{8'h31,24'd0};
+	parameter	[31:0]	PG2P3DelayRegCmd	=	{8'h32,24'd0};
+	parameter	[31:0]	PG2P123DelayRegCmd	=	{8'h33,24'd0};
+	parameter	[31:0]	PG2P1WidthRegCmd	=	{8'h34,24'd1};
+	parameter	[31:0]	PG2P2WidthRegCmd	=	{8'h35,24'd0};
+	parameter	[31:0]	PG2P3WidthRegCmd	=	{8'h36,24'd0};
+	parameter	[31:0]	PG2P123WidthRegCmd	=	{8'h37,24'd0};
+	
+	//PG3 Cmd
+	parameter	[31:0]	PG3P1DelayRegCmd	=	{8'h38,24'd0};
+	parameter	[31:0]	PG3P2DelayRegCmd	=	{8'h39,24'd0};
+	parameter	[31:0]	PG3P3DelayRegCmd	=	{8'h3a,24'd0};
+	parameter	[31:0]	PG3P123DelayRegCmd	=	{8'h3b,24'd0};
+	parameter	[31:0]	PG3P1WidthRegCmd	=	{8'h3c,24'd1};
+	parameter	[31:0]	PG3P2WidthRegCmd	=	{8'h3d,24'd0};
+	parameter	[31:0]	PG3P3WidthRegCmd	=	{8'h3e,24'd0};
+	parameter	[31:0]	PG3P123WidthRegCmd	=	{8'h3f,24'd0};
+	
+	//PG4 Cmd
+	parameter	[31:0]	PG4P1DelayRegCmd	=	{8'h40,24'd0};
+	parameter	[31:0]	PG4P2DelayRegCmd	=	{8'h41,24'd0};
+	parameter	[31:0]	PG4P3DelayRegCmd	=	{8'h42,24'd0};
+	parameter	[31:0]	PG4P123DelayRegCmd	=	{8'h43,24'd0};
+	parameter	[31:0]	PG4P1WidthRegCmd	=	{8'h44,24'd1};
+	parameter	[31:0]	PG4P2WidthRegCmd	=	{8'h45,24'd0};
+	parameter	[31:0]	PG4P3WidthRegCmd	=	{8'h46,24'd0};
+	parameter	[31:0]	PG4P123WidthRegCmd	=	{8'h47,24'd0};
+	
+	//PG5 Cmd
+	parameter	[31:0]	PG5P1DelayRegCmd	=	{8'h48,24'd0};
+	parameter	[31:0]	PG5P2DelayRegCmd	=	{8'h49,24'd0};
+	parameter	[31:0]	PG5P3DelayRegCmd	=	{8'h4a,24'd0};
+	parameter	[31:0]	PG5P123DelayRegCmd	=	{8'h4b,24'd0};
+	parameter	[31:0]	PG5P1WidthRegCmd	=	{8'h4c,24'd1};
+	parameter	[31:0]	PG5P2WidthRegCmd	=	{8'h4d,24'd0};
+	parameter	[31:0]	PG5P3WidthRegCmd	=	{8'h4e,24'd0};
+	parameter	[31:0]	PG5P123WidthRegCmd	=	{8'h4f,24'd0};
+	
+	//PG6 Cmd
+	parameter	[31:0]	PG6P1DelayRegCmd	=	{8'h50,24'd5};
+	parameter	[31:0]	PG6P2DelayRegCmd	=	{8'h51,24'd15};
+	parameter	[31:0]	PG6P3DelayRegCmd	=	{8'h52,24'd30};
+	parameter	[31:0]	PG6P123DelayRegCmd	=	{8'h53,24'd0};
+	parameter	[31:0]	PG6P1WidthRegCmd	=	{8'h54,24'd5};
+	parameter	[31:0]	PG6P2WidthRegCmd	=	{8'h55,24'd6};
+	parameter	[31:0]	PG6P3WidthRegCmd	=	{8'h56,24'd7};
+	parameter	[31:0]	PG6P123WidthRegCmd	=	{8'h57,24'd0};
+	
+	//PG7 Cmd
+	parameter	[31:0]	PG7P1DelayRegCmd	=	{8'h20,24'd0};
+	parameter	[31:0]	PG7P2DelayRegCmd	=	{8'h21,24'd0};
+	parameter	[31:0]	PG7P3DelayRegCmd	=	{8'h22,24'd0};
+	parameter	[31:0]	PG7P123DelayRegCmd	=	{8'h23,24'd0};
+	parameter	[31:0]	PG7P1WidthRegCmd	=	{8'h24,24'd1};
+	parameter	[31:0]	PG7P2WidthRegCmd	=	{8'h25,24'd0};
+	parameter	[31:0]	PG7P3WidthRegCmd	=	{8'h26,24'd0};
+	parameter	[31:0]	PG7P123WidthRegCmd	=	{8'h27,24'd0};
+	
+	parameter	[31:0]	MeasNum0RegCmd		=	{8'h58,24'd1};
+	parameter	[31:0]	MeasNum1RegCmd		=	{8'h59,24'd0};
+	parameter	[31:0]	PGMode0RegCmd		=	{8'h0b,3'b0,PG7MODE,PG6MODE,PG5MODE,PG4MODE,PG3MODE,PG2MODE,PG1MODE};
+	parameter	[31:0]	PGMode1RegCmd		=	{8'h1b,7'b0000000,PG7POL,PG6POL,PG5POL,PG4POL,PG3POL,PG2POL,PG1POL,10'b0};
+	
+	parameter	[31:0]	MuxCtrl1RegCmd	=	{8'h1c,4'h0,PG7MUXCMD,PG6MUXCMD,PG5MUXCMD,PG4MUXCMD};
+	parameter	[31:0]	MuxCtrl2RegCmd	=	{8'h1d,4'h0,PG3MUXCMD,PG2MUXCMD,PG1MUXCMD,SMPLSTRBMUXCMD};
+	parameter	[31:0]	MuxCtrl3RegCmd	=	{8'h1e,4'h0,GATINGMUXCMD,EXTTRIGMUXCMD,EP2MUXCMD,EP1MUXCMD};
+	parameter	[31:0]	MuxCtrl4RegCmd	=	{8'h1f,4'h0,EP6MUXCMD,EP5MUXCMD,EP4MUXCMD,EP3MUXCMD};
+	
+	//=================================================================================================================================================================================================================
+	
+	reg		Clk41;
+	reg		Clk50;
+	reg		Clk70;
+	
+	reg	[31:0]	tb_cnt=4'd0;
+	reg	[31:0]	tb_cnt1=4'd0;
+	reg	rst;
+	reg	mosi_i	=	1'b0;
+	reg	Miso_i	=	1'b0;
+	reg	ss_i;
+	reg	clk_i	=	1'b0;
+	
+	
+	reg	[31:0]	DspSpiData;
+	reg		startCalcCmdReg;
+	wire	startMeasS;
+	wire	[5:0]	trig6to1_io;
+	reg		[5:0]	trig6to1;
+	wire	[5:0]	trigDir;
+
+	wire	[17:0]	cos_value;	
+	wire	[17:0]	sin_value;				
+
+	wire	ExtDspTrigPos0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b1:1'b0;
+	wire	ExtDspTrigNeg0	=	(tb_cnt	>=	180	&&	tb_cnt	<=	181)?	1'b0:1'b1;
+	
+	wire	ExtTrigger0		=	ExtDspTrigNeg0;
+	
+	wire	TrigFromDsp		=	(tb_cnt	>=	1100	&&	tb_cnt	<=	1101)?	1'b1:1'b0;
+	wire	endMeas;
+	reg	[31:0]	cmdCnt;
+	
+	reg	trig0;
+	reg	trig1;
+	reg	dspTrigOut;
+	
+	reg		sensEnReg;
+	reg		sensEnNewR;
+	wire	sensEnS;
+	wire	sensEnM;
+	// trior	sensEn;
+	wire	sensEn;
+	pullup 	(sensEn);
+	wand	sensEnNew	=	sensEn;
+	
+	// wire	sensEnPos	=	(sensEn&!sensEnReg);
+	reg	sensEnPos;
+	//(tb_cnt1==32'd4283)?
+	wire	trig0R;
+    wire	trig1R;
+	
+//==========================================================================================
+//clocks gen
+	always	#10 Clk50	=	~Clk50;
+	always	#(14.285714285714/2) Clk70	=	~Clk70;
+	always	#10 clk_i	=	~clk_i;
+	always	#(24.390243902439/2)	Clk41	=	~Clk41;
+	
+	wire	sck_i;	
+//==========================================================================================
+initial begin
+	Clk50	=	1'b1;
+	Clk70	=	1'b1;
+	rst		=	1'b1;
+	Clk41	=	1'b0;
+	trig0	=	1'b0;
+	trig1	=	1'b0;
+	trig6to1	= 6'b000000;
+#100;
+	rst		=	1'b0;
+#400;
+	Clk41	=	1'b0;
+end		
+	
+// always	@(*)	begin
+	// if	(tb_cnt	==	3501)	begin
+		// trig6to1	<=	6'b000001;
+	// end	else	begin
+		// trig6to1	<=	1'b000000;
+	// end
+// end
+
+always	@(*)	begin
+	if	(tb_cnt	==	3501)	begin
+		dspTrigOut	<=	1'b1;
+	end	else	begin
+		dspTrigOut	<=	1'b0;
+	end
+end
+
+reg	endMeasReg;
+always	@(posedge	Clk41)	begin
+	endMeasReg	<=	endMeas;
+end
+
+
+always	@(posedge	Clk50)	begin
+	if	(!rst)	begin
+		sensEnReg	<=	sensEn;
+		sensEnNewR	<=	sensEnNew;
+	end	else	begin
+		sensEnReg	<=	0;
+		sensEnNewR	<=	0;
+	end
+end
+
+always	@(posedge	Clk50)	begin
+	sensEnPos	<=	(sensEn&!sensEnReg);
+end
+
+wire	endMeasNeg	=	!endMeas&endMeasReg;
+
+always	@(posedge	Clk70)	begin
+	if	(!rst)	begin
+		if	(!endMeas)	begin
+			if	(tb_cnt	==	3501)	begin
+				startCalcCmdReg	<=	1'b1;
+			end	
+		end	else	begin
+			startCalcCmdReg	<=	1'b0;
+		end
+	end	else	begin
+		startCalcCmdReg	<=	1'b0;
+	end
+end
+
+always	@(negedge	Clk41)	begin
+	if	(!rst)		begin
+		tb_cnt	<=	tb_cnt+1;
+	end	else	begin
+		tb_cnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk50)	begin
+	if	(!rst)		begin
+		tb_cnt1	<=	tb_cnt1+1;
+	end	else	begin
+		tb_cnt1	<=	0;
+	end
+end
+
+wire	Adc1DataDa0P;
+wire	Adc1DataDa1P;
+
+// wire	[31:0]	test	=	32'h2351eb85;
+wire	[31:0]	test	=	32'h3851eb85;
+CordicNco		
+#(	.ODatWidth	(18),
+	.PhIncWidth	(32),
+	.IterNum	(10),
+	.EnSinN		(0))
+ncoInst
+(
+	.Clk_i				(Clk50),
+	.Rst_i				(rst),
+	.Val_i				(1'b1),
+	.PhaseInc_i			(test),
+	.WindVal_i			(1'b1),
+	.WinType_i			(),
+	.Wind_o				(),
+	.Sin_o				(sin_value),
+	.Cos_o				(cos_value),
+	.Val_o				()
+);
+
+
+S5443Top MasterFpga 
+(
+	.Clk_i				(Clk50),
+	.Led_o				(),
+//------------------------------------------	
+    .Adc1FclkP_i		(),		
+    .Adc1FclkN_i		(),		
+
+    .Adc1DataDa0P_i		(),
+	.Adc1DataDa0N_i		(),		
+    .Adc1DataDa1P_i		(),
+    .Adc1DataDa1N_i		(),
+
+	.Adc1DataDb0P_i		(),
+    .Adc1DataDb0N_i		(),		
+    .Adc1DataDb1P_i		(),
+    .Adc1DataDb1N_i		(),
+//------------------------------------------	
+    .Adc2FclkP_i		(),		
+    .Adc2FclkN_i		(),		
+
+    .Adc2DataDa0P_i		(1'b1),
+    .Adc2DataDa0N_i		(1'b0),		
+    .Adc2DataDa1P_i		(1'b1),
+    .Adc2DataDa1N_i		(1'b0),
+  
+	.Adc2DataDb0P_i		(1'b1),
+    .Adc2DataDb0N_i		(1'b0),		
+    .Adc2DataDb1P_i		(1'b1),
+    .Adc2DataDb1N_i		(1'b0),
+//------------------------------------------
+	.AdcInitMosi_o		(),
+	.AdcInitClk_o		(),			
+	.Adc1InitCs_o		(),
+	.Adc2InitCs_o		(),
+	.AdcInitRst_o		(),
+//------------------------------------------	
+	
+	.Mosi_i				(mosi_i),
+	.Sck_i				(~sck_i),
+	.Ss_i				(ss_i),
+
+	.LpOutClk_o			(),
+	.LpOutFs_o			(),			
+	.LpOutData_o		(),
+	
+	//fpga-dsp signals
+	.StartMeas_i		(startCalcCmdReg),
+	.StartMeasEvent_o	(startMeasS),
+	.EndMeas_o			(endMeas),
+	.TimersClk_o		(),
+	
+	.Trig6to1_io		(),	
+	.Trig6to1Dir_o		(),	
+	
+	.DspTrigOut_i		(Clk41),				//Trig from DSP
+	.DspTrigIn_o		(),				//Trig To DSP
+	
+	.OverloadS_i		(1'b0),
+	.Overload_o			(),
+	
+	.PortSel_o			(),
+	.PortSelDir_o		(),
+	
+	//mod out line
+	
+	.Mod_o				(),	
+	
+	//gain lines
+	.DspReadyForRx_i		(1'b0),
+	.DspReadyForRxToFpgaS_o	(),
+	.AmpEn_o				(),	//	0-adc1ChA 1-adc1ChB 2-adc2ChA 3-adc2ChB
+	.AdcData_i				(sin_value[17-:14])
+	// .AdcData_i			(Data_i)
+);
+
+parameter	IDLE	=	2'h0;
+parameter	CMD		=	2'h1;
+parameter	TX		=	2'h2;
+parameter	PAUSE	=	2'h3;
+
+reg	[1:0]	txCurrState;
+reg	[1:0]	txNextState;
+
+wire	txWork	=	tb_cnt	>=	23;
+wire	txStop	=	cmdCnt	>=	69;
+
+
+reg	[6:0]	txCnt;
+reg	[3:0]	pauseCnt;
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	TX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(!rst)	begin
+		if	(txCurrState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			DspSpiData		<=	MeasCmd;
+		end	else	if	(cmdCnt	==	1)	begin
+			DspSpiData		<=	IfFtwH;
+		end	else	if	(cmdCnt	==	2)	begin
+			DspSpiData		<=	IfFtwL;
+		end	else	if	(cmdCnt	==	3)	begin
+			DspSpiData		<=	FilterCorrCmdH;
+		end	else	if	(cmdCnt	==	4)	begin
+			DspSpiData		<=	FilterCorrCmdL;
+		end	else	if	(cmdCnt	==	5)	begin
+			DspSpiData		<=	PG1P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	6)	begin
+			DspSpiData		<=	PG1P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	7)	begin
+			DspSpiData		<=	PG1P3DelayRegCmd;
+		end	else	if	(cmdCnt	==	8)	begin
+			DspSpiData		<=	PG1P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	9)	begin
+			DspSpiData		<=	PG1P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	10)	begin
+			DspSpiData		<=	PG1P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	11)	begin
+			DspSpiData		<=	PG1P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	12)	begin
+			DspSpiData		<=	PG1P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	13)	begin
+			DspSpiData		<=	PG2P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	14)	begin
+			DspSpiData		<=	PG2P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	15)	begin
+			DspSpiData		<=	PG2P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	16)	begin
+			DspSpiData		<=	PG2P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	17)	begin
+			DspSpiData		<=	PG2P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	18)	begin
+			DspSpiData		<=	PG2P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	19)	begin
+			DspSpiData		<=	PG2P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	20)	begin
+			DspSpiData		<=	PG2P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	21)	begin
+			DspSpiData		<=	PG3P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	22)	begin
+			DspSpiData		<=	PG3P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	23)	begin
+			DspSpiData		<=	PG3P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	24)	begin
+			DspSpiData		<=	PG3P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	25)	begin
+			DspSpiData		<=	PG3P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	26)	begin
+			DspSpiData		<=	PG3P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	27)	begin
+			DspSpiData		<=	PG3P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	28)	begin
+			DspSpiData		<=	PG3P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	29)	begin
+			DspSpiData		<=	PG4P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	30)	begin
+			DspSpiData		<=	PG4P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	31)	begin
+			DspSpiData		<=	PG4P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	32)	begin
+			DspSpiData		<=	PG4P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	33)	begin
+			DspSpiData		<=	PG4P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	34)	begin
+			DspSpiData		<=	PG4P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	35)	begin
+			DspSpiData		<=	PG4P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	36)	begin
+			DspSpiData		<=	PG4P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	37)	begin
+			DspSpiData		<=	PG5P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	38)	begin
+			DspSpiData		<=	PG5P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	39)	begin
+			DspSpiData		<=	PG5P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	40)	begin
+			DspSpiData		<=	PG5P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	41)	begin
+			DspSpiData		<=	PG5P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	42)	begin
+			DspSpiData		<=	PG5P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	43)	begin
+			DspSpiData		<=	PG5P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	44)	begin
+			DspSpiData		<=	PG5P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	45)	begin
+			DspSpiData		<=	PG6P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	46)	begin
+			DspSpiData		<=	PG6P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	47)	begin
+			DspSpiData		<=	PG6P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	48)	begin
+			DspSpiData		<=	PG6P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	49)	begin
+			DspSpiData		<=	PG6P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	50)	begin
+			DspSpiData		<=	PG6P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	51)	begin
+			DspSpiData		<=	PG6P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	52)	begin
+			DspSpiData		<=	PG6P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	53)	begin
+			DspSpiData		<=	PG7P1DelayRegCmd;
+		end	else	if	(cmdCnt	==	54)	begin
+			DspSpiData		<=	PG7P2DelayRegCmd;
+		end	else	if	(cmdCnt	==	55)	begin
+			DspSpiData		<=	PG7P3DelayRegCmd;	
+		end	else	if	(cmdCnt	==	56)	begin
+			DspSpiData		<=	PG7P123DelayRegCmd;
+		end	else	if	(cmdCnt	==	57)	begin
+			DspSpiData		<=	PG7P1WidthRegCmd;
+		end	else	if	(cmdCnt	==	58)	begin
+			DspSpiData		<=	PG7P2WidthRegCmd;
+		end	else	if	(cmdCnt	==	59)	begin
+			DspSpiData		<=	PG7P3WidthRegCmd;
+		end	else	if	(cmdCnt	==	60)	begin
+			DspSpiData		<=	PG7P123WidthRegCmd;
+		end	else	if	(cmdCnt	==	61)	begin
+			DspSpiData		<=	MeasNum0RegCmd;
+		end else	if	(cmdCnt	==	62)	begin
+			DspSpiData		<=	MeasNum1RegCmd;
+		end else	if	(cmdCnt	==	63)	begin
+			DspSpiData		<=	PGMode0RegCmd;
+		end	else	if	(cmdCnt	==	64)	begin
+			DspSpiData		<=	PGMode1RegCmd;
+		end	else	if	(cmdCnt	==	65)	begin
+			DspSpiData		<=	MuxCtrl1RegCmd;
+		end	else	if	(cmdCnt	==	66)	begin
+			DspSpiData		<=	MuxCtrl2RegCmd;
+		end	else	if	(cmdCnt	==	67)	begin
+			DspSpiData		<=	MuxCtrl3RegCmd;
+		end	else	if	(cmdCnt	==	68)	begin
+			DspSpiData		<=	SensCtrlCmd;
+		end	
+	end	else	if	(txCurrState	==	TX)	begin
+		DspSpiData	<=	DspSpiData<<1;
+	end
+end
+
+always	@(posedge Clk41)	begin
+	if	(txCurrState	==	TX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			mosi_i	<=	DspSpiData[31];
+		end	else	begin
+			mosi_i	<=	1'b1;
+		end
+	end	else	begin
+		mosi_i	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk41)	begin
+	if	(txCurrState	==	TX)	begin
+		ss_i	<=	1'b0;
+	end	else	begin
+		ss_i	<=	1'b1;
+	end
+end
+
+assign	sck_i	=	Clk41;
+
+always	@(posedge	Clk41)	begin
+	if	(rst)	begin
+		txCurrState	<=	IDLE;
+	end	else	begin
+		txCurrState	<=	txNextState;
+	end
+end
+
+
+always @(*) begin
+	txNextState	=	IDLE;
+	case(txCurrState)
+	IDLE	:	begin
+					if (txWork)	begin
+						txNextState = CMD;
+					end	else begin
+						txNextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						txNextState = TX;
+					end	else begin
+						txNextState = IDLE;
+					end
+				end
+
+	TX		:	begin
+					if (txCnt==6'd31) begin
+						txNextState  = PAUSE;
+					end	else begin
+						txNextState  = TX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd10) begin
+						txNextState  = CMD;
+					end	else begin
+						txNextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/Top/IntermediateLogic.v

@@ -0,0 +1,137 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    
+// design name: 
+// module name:   
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module IntermediateLogic 
+(
+input Clk_i,
+input Rst_i,
+
+input MeasEnd_i,
+
+input ReadReq_i,
+
+input ValToCfgReg_i,
+input [31:0] CfgData_i,
+
+input ValToMeasData_i,
+input [32*2-1:0] MeasData_i,
+
+output reg StartMeasCmd_o,
+
+output [31:0] Data_o
+);
+
+reg [31:0] cfgReg;
+reg [63:0] measDataR;
+reg [31:0] dataOut;
+reg [1:0] measDwCnt;
+
+reg measEndR;
+reg measEndRR;
+
+reg valToCfgRegR;
+wire valToCfgPos;
+
+reg valToMeasDataR;
+wire valToMeasDataPos;
+
+
+assign Data_o = dataOut;
+
+assign valToCfgPos = (ValToCfgReg_i&!valToCfgRegR);
+assign valToMeasDataPos = (ValToMeasData_i&!valToMeasDataR);
+
+always @(posedge Clk_i or posedge Rst_i) begin
+	if (Rst_i) begin
+		StartMeasCmd_o <= 0;
+		valToCfgRegR <= 0;
+		valToMeasDataR <= 0;
+	end else begin
+		StartMeasCmd_o <= cfgReg[0];
+		valToCfgRegR <= ValToCfgReg_i;
+		valToMeasDataR <= ValToMeasData_i;
+	end
+end
+
+always @(posedge Clk_i or posedge Rst_i) begin
+	if (Rst_i) begin
+		measEndR <= 0;
+		measEndRR <= 0;
+	end else begin
+		measEndR <= MeasEnd_i;
+		measEndRR <= measEndR;
+	end
+end
+
+always @(posedge Clk_i or posedge Rst_i) begin
+	if (Rst_i) begin
+		cfgReg <= 0;
+	end else begin
+		if (!ReadReq_i) begin
+			if (valToCfgPos) begin
+				cfgReg <= CfgData_i;
+			end else if (measEndRR) begin
+				cfgReg[1:0] <= {measEndRR,1'b0};
+			end
+		end
+	end
+end
+
+always @(posedge Clk_i or posedge Rst_i) begin
+	if (Rst_i) begin
+		measDwCnt <= 1;
+	end else begin
+		if (ReadReq_i) begin
+			if (measDwCnt!=2'd2) begin
+				measDwCnt <= 	measDwCnt+1;
+			end else begin
+				measDwCnt <= 1;
+			end
+		end
+	end
+end
+
+always @(posedge Clk_i or posedge Rst_i) begin
+	if (Rst_i) begin
+		measDataR <= 0;
+	end else begin
+		if (measEndRR) begin
+			measDataR <= MeasData_i;
+		end 
+	end
+end
+
+always @(posedge Clk_i or posedge Rst_i) begin
+	if (Rst_i) begin
+		dataOut <= 0;
+	end else begin
+		if (ReadReq_i) begin
+			if (ValToMeasData_i) begin
+				dataOut <= measDataR[measDwCnt*32-1-:32];
+			end else if (ValToCfgReg_i) begin
+				dataOut <= cfgReg;
+			end 
+		end
+	end
+end
+
+endmodule

src/src/Top/IntermediateLogicTb.v

@@ -0,0 +1,57 @@
+`timescale 1ns / 1ns
+
+module IntermediateLogicTb();
+
+
+reg [31:0] cfgReg = 32'h1;
+reg [63:0] measData = 64'hCDCD0000_AABB0000;
+
+reg [31:0] tbCnt;
+
+wire measEnd = (tbCnt==20);
+wire measDataReq = (tbCnt==50)||(tbCnt==60)||(tbCnt==100);
+wire cfgVal = (tbCnt==10)||(tbCnt==100);
+wire dataVal = (tbCnt==50)||(tbCnt==60);
+reg clk;
+reg rst;
+
+
+
+always #25 clk = ~clk;
+
+initial begin
+	rst = 1;
+	clk = 0;
+	#100;
+	rst = 0;
+end
+
+
+always @(posedge clk) begin
+	if (rst) begin
+		tbCnt <= 0;
+	end else begin
+		tbCnt <= tbCnt+1;
+	end
+end
+
+IntermediateLogic Test
+(
+  .Clk_i(clk),
+  .Rst_i(rst),
+
+  .MeasEnd_i(measEnd),
+
+  .ReadReq_i(measDataReq),
+
+  .ValToCfgReg_i(cfgVal),
+  .CfgData_i(cfgReg),
+ 
+  .ValToMeasData_i(dataVal),
+  .MeasData_i(measData),
+  
+  .StartMeasCmd_o(),
+  .Data_o()
+);
+
+endmodule

src/src/Top/PciVnaEmulTop.v

@@ -0,0 +1,175 @@
+`timescale 1ns / 1ps
+(* keep_hierarchy = "yes" *)
+//////////////////////////////////////////////////////////////////////////////////
+// company: 
+// engineer: 
+// 
+// create date:    
+// design name: 
+// module name:   
+// project name: 
+// target devices: 
+// tool versions: 
+// description: 
+//
+// dependencies: 
+//
+// revision: 
+// revision 0.01 - file created
+// additional comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module PciVnaEmulTop 
+(
+  output  [1:0]    pci_exp_txp,
+  output  [1:0]    pci_exp_txn,
+  input   [1:0]    pci_exp_rxp,
+  input   [1:0]    pci_exp_rxn,
+
+  input sys_clk_p,
+  input sys_clk_n,
+  input sys_rst_n
+);
+
+
+wire [63:0] measData;
+wire clk;
+wire endMeas;
+wire endMeasSync;
+wire measEnd;
+reg measEndR;
+reg measEndRR;
+reg measEndRRR;
+reg measEndRRRR;
+wire measEndSync;
+wire startMeasCmd;
+
+wire clkUser3;
+
+xilinx_pcie_2_1_ep_7x EP 
+(
+  // SYS Inteface
+  .sys_clk_n(sys_clk_n),
+  .sys_clk_p(sys_clk_p),
+  .sys_rst_n(sys_rst_n),
+
+  // PCI-Express Interface
+  .pci_exp_txn(pci_exp_txn),
+  .pci_exp_txp(pci_exp_txp),
+  .pci_exp_rxn(pci_exp_rxn),
+  .pci_exp_rxp(pci_exp_rxp),
+
+  .Clk_o(clk),
+
+  .MeasData_i(measData),
+  .MeasEnd_i(endMeasSync),
+
+  .StartMeasCmd_o(startMeasCmd),
+
+  .ClkUser3_o	(clkUser3)
+);
+
+xpm_cdc_single #(
+   .DEST_SYNC_FF(10),   // DECIMAL; range: 2-10
+   .INIT_SYNC_FF(0),   // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+   .SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+   .SRC_INPUT_REG(1)   // DECIMAL; 0=do not register input, 1=register input
+)
+xpm_cdc_single_inst (
+   .dest_out(endMeasSync), // 1-bit output: src_in synchronized to the destination clock domain. This output is // registered.
+   .dest_clk(clk), // 1-bit input: Clock signal for the destination clock domain.
+   .src_clk(clkUser3),   // 1-bit input: optional; required when SRC_INPUT_REG = 1
+   .src_in(measEndRRRR)      // 1-bit input: Input signal to be synchronized to dest_clk domain.
+);
+
+always @(posedge clkUser3 ) begin
+    measEndR <= endMeas;
+end
+
+always @(posedge clkUser3) begin 
+    measEndRR <= measEndR;
+end
+
+always @(posedge clkUser3) begin 
+    measEndRRR <= measEndRR;
+end
+
+
+always @(posedge clkUser3) begin 
+  measEndRRRR <= measEndRRR;
+end
+   
+S5443Top FPGA_M 
+(
+	.Clk_i				(clkUser3), 
+	.Led_o				(),
+	
+    .Adc1FclkP_i		(),		
+    .Adc1FclkN_i		(),		
+
+    .Adc1DataDa0P_i		(),
+	.Adc1DataDa0N_i		(),		
+    .Adc1DataDa1P_i		(),
+    .Adc1DataDa1N_i		(),
+
+	.Adc1DataDb0P_i		(),
+    .Adc1DataDb0N_i		(),		
+    .Adc1DataDb1P_i		(),
+    .Adc1DataDb1N_i		(),
+	
+    .Adc2FclkP_i		(),		
+    .Adc2FclkN_i		(),		
+
+    .Adc2DataDa0P_i		(),
+    .Adc2DataDa0N_i		(),		
+    .Adc2DataDa1P_i		(),
+    .Adc2DataDa1N_i		(),
+  
+	.Adc2DataDb0P_i		(),
+    .Adc2DataDb0N_i		(),		
+    .Adc2DataDb1P_i		(),
+    .Adc2DataDb1N_i		(),
+
+	.AdcInitMosi_o		(),
+	.AdcInitClk_o		(),			
+	.Adc1InitCs_o		(),
+	.Adc2InitCs_o		(),
+	.AdcInitRst_o		(),
+	
+	.Mosi_i				(),
+	.Sck_i				(),
+	.Ss_i				(),
+
+	.LpOutClk_o			(),
+	.LpOutFs_o			(),			
+	.LpOutData_o		(),
+
+	.StartMeas_i		(startMeasCmd),
+	.StartMeasEvent_o	(),
+	.EndMeas_o			(endMeas),
+  .MeasEnd_o      (measEnd),
+	.TimersClk_o		(),
+	
+	.Trig6to1_io		(),	
+	.Trig6to1Dir_o		(),	
+	
+	.DspTrigOut_i		(),				
+	.DspTrigIn_o		(),				
+	
+	.OverloadS_i		(),
+	.Overload_o			(),
+	
+	.PortSel_o			(),
+	.PortSelDir_o		(),
+	
+	.Mod_o				(),	
+	
+	.DspReadyForRx_i		(),
+	.DspReadyForRxToFpgaS_o	(),
+	.AmpEn_o				(),
+
+	.MeasData_o		(measData)
+);
+
+endmodule