Merge branch 'Anatoliy/feature_FifoCtrl' of zaytsev.mikhail/SB_TMSG44V1_FPGA into dev

src/src/FifoCtrl/FifoCtrl.v

@@ -0,0 +1,164 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     FifoCtrl
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:     This module is a controller for the FIFOs. It controls the read and write pointers of the FIFOs.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module FifoCtrl #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 24
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+    input BusySpiM_i,
+    input FifoFull_i,
+    input FifoEmpty_i,
+
+    output [OUT_WIDTH-1:0] Data_o,
+    output reg ReadEn_o,
+    output reg  WriteEn_o,
+    output reg ValRdData_o
+
+);
+//================================================================================
+//	LOCAL PARAMETERS
+//================================================================================
+localparam DATA_WIDTH = WR_NUM*IN_WIDTH;
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg [DATA_WIDTH-1:0] dataReg;
+reg [1:0]  wrCnt;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign Data_o = dataReg[OUT_WIDTH-1:0];
+
+//================================================================================
+//	CODING
+//================================================================================
+always @(posedge WrClk_i) begin 
+    if (Rst_i) begin 
+        wrCnt <= 0;
+    end
+    else begin 
+        if (Val_i) begin 
+            wrCnt <= wrCnt + 1;
+        end
+        else if (wrCnt == WR_NUM) begin 
+            wrCnt <= 0;
+        end
+    end
+end
+
+always @(posedge WrClk_i) begin 
+    if (Rst_i) begin 
+        dataReg <= 0;
+    end
+    else begin
+        if (WR_NUM>1) begin
+            case (WR_NUM)  
+            3: begin
+                case (wrCnt)
+                0 : begin 
+                    if (Val_i) begin 
+                        dataReg[(3*IN_WIDTH)-1:(2*IN_WIDTH)] <= Data_i;
+                    end
+                end
+                1 : begin 
+                    if (Val_i) begin 
+                        dataReg[(2*IN_WIDTH)-1:IN_WIDTH] <= Data_i;
+                    end
+                end
+                2 : begin 
+                    if (Val_i) begin 
+                        dataReg[IN_WIDTH-1:0] <= Data_i;
+                    end
+                end
+                endcase
+            end
+            2 : begin 
+                case (wrCnt)
+                0: begin 
+                    if (Val_i) begin 
+                        dataReg[(2*IN_WIDTH)-1:IN_WIDTH] <= Data_i;
+                    end
+                end
+                1: begin 
+                    if (Val_i) begin 
+                        dataReg[IN_WIDTH-1:0] <= Data_i;
+                    end
+                end
+                endcase
+            end
+            endcase
+        end
+        else begin
+            if (Val_i) begin 
+                dataReg[IN_WIDTH-1:0] <= Data_i;
+            end
+        end
+    end
+end
+
+always @(posedge WrClk_i) begin
+    if (Rst_i) begin 
+        WriteEn_o <= 1'b0;
+    end
+    else begin  
+        if (Val_i && wrCnt == WR_NUM-1 && !FifoFull_i) begin
+            WriteEn_o <= 1'b1;
+        end
+        else begin 
+            WriteEn_o <= 1'b0;
+        end
+    end
+end
+
+always @(posedge RdClk_i) begin
+    if (Rst_i) begin 
+        ReadEn_o <= 1'b0;
+    end
+    else begin  
+        if (!FifoEmpty_i && !BusySpiM_i) begin 
+            ReadEn_o <= 1'b1;
+        end
+        else begin 
+            ReadEn_o <= 1'b0;
+        end
+    end
+end
+
+always @(posedge RdClk_i) begin 
+    if (Rst_i) begin 
+        ValRdData_o <= 1'b0;
+    end
+    else begin
+        if (!FifoEmpty_i && !BusySpiM_i) begin 
+            ValRdData_o <= 1'b1;
+        end
+        else begin 
+            ValRdData_o <= 1'b0;
+        end
+    end
+end
+
+endmodule

src/src/FifoCtrl/FifoCtrl_tb.do

@@ -0,0 +1,39 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider FifoCtrlDDS
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/IN_WIDTH
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/WR_NUM
+add wave -noupdate -radix unsigned /FifoCtrl_tb/FifoCtrlDDS_inst/OUT_WIDTH
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/DATA_WIDTH
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/WrClk_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/RdClk_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/Rst_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/Data_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/Val_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/BusySpiM_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/FifoFull_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/FifoEmpty_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/Data_o
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/ReadEn_o
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/ValRdData_o
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/WriteEn_o
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/dataReg
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/wrCnt
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {11121814 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {15750 ns}

src/src/FifoCtrl/FifoCtrl_tb.sv

@@ -0,0 +1,282 @@
+`timescale 1ns/1ps
+module FifoCtrl_tb;
+logic WrClk_i;
+logic RdClkDDS_i;
+logic RdClkLMX_i;
+logic RdClkMax_i;
+logic Rst_i;
+logic [23:0] dataForDDS;
+logic [23:0] dataForLMX;
+logic [23:0] dataForMAX;
+logic BusySpiLMX;
+logic BusySpiDDS;
+logic BusySpiMax;
+logic valFromSPI64;
+logic valFromSPI32;
+logic valFromSPI24;
+
+logic wrEnDDS;
+logic wrEnLMX;
+
+logic rdEnDDS;
+logic rdEnLMX;
+
+logic fullFlagLMX;
+logic emptyFlagLMX;
+
+logic fullFlagDDS;
+logic emptyFlagDDS;
+
+logic [23:0] dataToFifo24;
+logic [31:0] dataToFifo32;
+logic [63:0] dataToFifo64;
+logic [23:0] dataFromFifo24;
+logic [31:0] dataFromFifo32;
+logic [63:0] dataFromFifo64;
+
+logic [6:0] OUT_WIDTH;
+logic [1:0] WR_NUM;
+
+//***********************************************
+//	           LOCALPARAMS
+//***********************************************
+localparam FIFTY_MHZ = 20;
+localparam SIXTY_MHZ = 16;
+localparam TWENTY_MHZ = 50;
+
+//***********************************************
+//	           CLOCK GENERATION
+//***********************************************
+always begin
+    #50 WrClk_i = ~WrClk_i;
+    #(FIFTY_MHZ/2) RdClkDDS_i = ~RdClkDDS_i;
+    #(SIXTY_MHZ/2) RdClkLMX_i = ~RdClkLMX_i;
+    #(TWENTY_MHZ/2) RdClkMax_i = ~RdClkMax_i;
+end
+//***********************************************
+//	           DUT INSTANTIATION
+//***********************************************
+FifoCtrl#(
+    .IN_WIDTH(24),
+    .WR_NUM(3),
+    .OUT_WIDTH(64)
+) FifoCtrlDDS_inst (
+    .WrClk_i(WrClk_i),
+    .RdClk_i(RdClkDDS_i),
+    .Rst_i(Rst_i),
+    .Data_i(dataForDDS),
+    .Val_i(valFromSPI64),
+    .FifoFull_i(fullFlagDDS),
+    .FifoEmpty_i(emptyFlagDDS),
+    .BusySpiM_i(BusySpiDDS),
+    .Data_o(dataToFifo64),
+    .ReadEn_o(rdEnDDS),
+    .ValRdData_o(valRdDDS),
+    .WriteEn_o(wrEnDDS)
+);
+
+FifoCtrl #(
+    .IN_WIDTH(24),
+    .WR_NUM(1),
+    .OUT_WIDTH(24)
+) FifoCtrlLMX_inst (
+    .WrClk_i(WrClk_i),
+    .RdClk_i(RdClkLMX_i),
+    .Rst_i(Rst_i),
+    .Data_i(dataForLMX),
+    .Val_i(valFromSPI24),
+    .FifoFull_i(fullFlagLMX),
+    .FifoEmpty_i(emptyFlagLMX),
+    .BusySpiM_i(BusySpiLMX),
+    .Data_o(dataToFifo24),
+    .ReadEn_o(rdEnLMX),
+    .ValRdData_o(valRdLMX),
+    .WriteEn_o(wrEnLMX)
+);
+
+FifoCtrl #(
+    .IN_WIDTH(24),
+    .WR_NUM(2),
+    .OUT_WIDTH(32)
+) FifoCtrlMax_inst (
+    .WrClk_i(WrClk_i),
+    .RdClk_i(RdClkMax_i),
+    .Rst_i(Rst_i),
+    .Data_i(dataForMAX),
+    .Val_i(valFromSPI32),
+    .FifoFull_i(fullFlagMax),
+    .FifoEmpty_i(emptyFlagMax),
+    .BusySpiM_i(BusySpiMax),
+    .Data_o(dataToFifo32),
+    .ReadEn_o(rdEnMax),
+    .ValRdData_o(valRdMax),
+    .WriteEn_o(wrEnMax)
+);
+// Depth 16
+FifoLMX FifoLMX_inst (
+    .Data(dataToFifo24),
+    .WrClk(WrClk_i),
+    .Reset(Rst_i),
+    .RdClk(RdClkLMX_i),
+    .WrEn(wrEnLMX),
+    .RdEn(rdEnLMX),
+    .Q(dataFromFifo24),
+    .Empty(emptyFlagLMX),
+    .Full(fullFlagLMX)
+);
+// Depth 2
+FifoDDS FifoDDS_inst (
+    .Data(dataToFifo64),
+    .WrClk(WrClk_i),
+    .Reset(Rst_i),
+    .RdClk(RdClkDDS_i),
+    .WrEn(wrEnDDS),
+    .RdEn(rdEnDDS),
+    .Q(dataFromFifo64),
+    .Empty(emptyFlagDDS),
+    .Full(fullFlagDDS)
+);
+//Depth 4
+FifoMax2870 FifoMax_inst (
+    .Data(dataToFifo32),
+    .WrClk(WrClk_i),
+    .Reset(Rst_i),
+    .RdClk(RdClkMax_i),
+    .WrEn(wrEnMax),
+    .RdEn(rdEnMax),
+    .Q(dataFromFifo32),
+    .Empty(emptyFlagMax),
+    .Full(fullFlagMax)
+);
+
+SpiM #(
+    .DATA_WIDTH(24)
+)SpiMLMX_inst(
+    .Clk_i(RdClkLMX_i),
+    .Rst_i(Rst_i),
+    .Val_i(valRdLMX),
+    .SpiData_i(dataFromFifo24),
+    .Busy_o(BusySpiLMX)
+);
+
+SpiM #(
+    .DATA_WIDTH(64)
+)SpiMDDS_inst(
+    .Clk_i(RdClkDDS_i),
+    .Rst_i(Rst_i),
+    .Val_i(valRdDDS),
+    .SpiData_i(dataFromFifo64),
+    .Busy_o(BusySpiDDS)
+);
+
+SpiM #(
+    .DATA_WIDTH(32)
+)SpiMMax_inst(
+    .Clk_i(RdClkMax_i),
+    .Rst_i(Rst_i),
+    .Val_i(valRdMax),
+    .SpiData_i(dataFromFifo32),
+    .Busy_o(BusySpiMax)
+);
+//***********************************************
+//	           TASKS
+//***********************************************
+task drive_fifo64();
+    valFromSPI64 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI64 = 1'b1;
+    dataForDDS = {8'h0, 16'hFFFF};
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI64 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI64 = 1'b1;
+    dataForDDS = 24'habcdef;
+    #10;
+    @ (posedge WrClk_i)
+    valFromSPI64 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI64 = 1'b1;
+    dataForDDS = 24'h123456;
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI64 = 1'b0;
+endtask
+
+task drive_fifo32();
+    valFromSPI32 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI32 = 1'b1;
+    dataForMAX = {16'h0, 8'h12};
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI32 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI32 = 1'b1;
+    dataForMAX = 24'habcdef;
+    #10;
+    @ (posedge WrClk_i)
+    valFromSPI32 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI32 = 1'b1;
+    dataForMAX = {16'h0, 8'h12};
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI32 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI32 = 1'b1;
+    dataForMAX = $urandom();
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI32 = 1'b0;
+endtask
+
+task drive_fifo24();
+    Rst_i = 1'b1;
+    valFromSPI24 = 1'b0;
+    dataForLMX = 24'h0;
+    #200;
+    Rst_i = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI24 = 1'b1;
+    dataForLMX = 24'h123456;
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI24 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI24 = 1'b1;
+    dataForLMX = 24'habcdef;
+    #10;
+    @ (posedge WrClk_i)
+    valFromSPI24 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI24 = 1'b1;
+    dataForLMX = 24'h123456;
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI24 = 1'b0;
+endtask
+//***********************************************
+//	           INITIALIZATION
+//***********************************************
+initial begin 
+    WrClk_i = 1'b1;
+    RdClkDDS_i = 1'b1;
+    RdClkLMX_i = 1'b1;
+    RdClkMax_i = 1'b1;
+    drive_fifo24();
+    drive_fifo32();
+    drive_fifo64();
+end
+
+endmodule

src/src/SPIm/SpiM.v

@@ -70,19 +70,11 @@ always @(negedge Clk_i) begin
         ssCnt <= 7'h0;
     end
     else begin
-        if (ssCnt == 0) begin 
-            if (Val_i) begin 
-                ssCnt <= ssCnt + 1;
-            end
-        end
-        else begin 
-            if (ssCnt < DATA_WIDTH) begin 
-                ssCnt <= ssCnt + 1;
-            end
-            else begin 
-                ssCnt <= 7'h0;
-            end
-        end
+        if (!ssReg) begin
+			ssCnt <= ssCnt+1;
+		end else begin
+			ssCnt <= 0;
+		end
     end
 end
 
@@ -107,12 +99,12 @@ always @(negedge Clk_i) begin
         ssReg <= 1'b1;
     end
     else begin 
-        if (ssCnt < DATA_WIDTH) begin 
-            ssReg <= 1'b0;
-        end
-        else begin 
-            ssReg <= 1'b1;
-        end
+        if (Val_i) begin
+			ssReg <= 0;
+		end
+		if (ssCnt == DATA_WIDTH-1) begin
+			ssReg <= 1;
+		end
     end
 end
 

src/src/Top/ExtSpiMEmul.v

@@ -1,205 +1,536 @@
-`timescale 1ns / 1ps
-
-module ExtSpiMEmul 
-(
-	input Rst_i,
-	input Clk_i,
-	
-	input Start_i,
-	output TxDone_o,
-	
-	output Sck_o,
-	output reg Ss_o,
-	output reg Mosi_o
-	
+module ExtSpiMEmul (
+    input Clk_i,
+    input Rst_i,
+    input Start_i,
+    input EmptyFlag_i,
+    input ClockPhase_i,
+    input [31:0] SpiData_i,
+    input SelSt_i,
+    input [1:0] WidthSel_i,
+    input  Lag_i,
+    input  Lead_i,
+    input EndianSel_i,
+    input [5:0] Stop_i,
+    input PulsePol_i,
+
+
+    output reg Mosi0_o,
+    output reg Sck_o,
+    output  Ss_o,
+    output reg  Val_o
 );
 
-//================================================================================
-//  PARAMETERS
-	localparam [1:0] IDLE = 0;
-	localparam [1:0] CMD = 1;
-	localparam [1:0] TX = 2;
-	localparam [1:0] PAUSE = 3;
 
-	parameter MODE = 1'h0;
-	parameter [4:0] DEVID = 5'h1;
-	parameter [16:0] WORDSNUM = 17'd24;
-	parameter EOPBIT = 1'b1;
-	
 //================================================================================
-//  REG/WIRE
-	reg [1:0] currState;
-	reg [1:0] nextState;
-	
-	reg	[6:0]	txCnt;
-	reg	[6:0]	cmdCnt;
-	reg	[3:0]	pauseCnt;
-
-	wire	txStop	=	(cmdCnt	>=	WORDSNUM+1);
-	
-	reg [23:0] headerCmd = {MODE,DEVID,WORDSNUM,EOPBIT};
-	reg [23:0] spiData;
-	
-	reg	[23:0]	dspSpiData;
-	
-	reg sckFlag;
+//	REG/WIRE
 //================================================================================
-//  ASSIGNMENTS
-
-assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b0;
-assign	TxDone_o	=	(txStop & (currState== CMD));
-
-//================================================================================
-//  CODING
-
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(currState	==	CMD)	begin
-			if	(!txStop)	begin
-				cmdCnt	<=	cmdCnt+1;
-			end else begin
-				cmdCnt <= 0;
-			end
-		end
-	end	else	begin
-		cmdCnt	<=	0;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(currState	==	TX)	begin
-			txCnt	<=	txCnt+1;
-		end	else	begin
-			txCnt	<=	0;
-		end
-	end	else	begin
-		txCnt	<=	0;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(currState	==	PAUSE)	begin
-			pauseCnt	<=	pauseCnt+1;
-		end	else	begin
-			pauseCnt	<=	0;
-		end
-	end	else	begin
-		pauseCnt	<=	0;
-	end
-end
-	
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(currState	==	CMD)	begin
-			spiData	<=	spiData+cmdCnt;
-		end
-	end	else	begin
-		spiData	<=	24'hab;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(currState	==	CMD)	begin
-		if	(cmdCnt	==	0)	begin
-			dspSpiData		<=	headerCmd;
-		end	else	begin
-			dspSpiData		<=	spiData;
-		end	
-	end	else	if	(currState	==	TX)	begin
-		dspSpiData	<=	dspSpiData<<1;
-	end if	(currState	==	IDLE)	begin
-		dspSpiData	<=	0;
-	end
-end
-
-always	@(posedge Clk_i)	begin
-	if	(currState	==	TX)	begin
-		if	(txCnt	>=	7'd0)	begin
-			Mosi_o	<=	dspSpiData[23];
-		end	else	begin
-			Mosi_o	<=	1'b0;
-		end
-	end	else	begin
-		Mosi_o	<=	1'b0;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(currState	==	TX)	begin
-		Ss_o	<=	1'b0;
-		sckFlag	<=	1'b1;
-	end	else	begin
-		Ss_o	<=	1'b1;
-		sckFlag	<=	1'b0;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(Rst_i)	begin
-		currState	<=	IDLE;
-	end	else	begin
-		currState	<=	nextState;
-	end
-end
-
-always @(*) begin
-	nextState	=	IDLE;
-	case(currState)
-	IDLE	:	begin
-					if (Start_i)	begin
-						nextState = CMD;
-					end	else begin
-						nextState = IDLE;
-					end
-				end
-				
-	CMD	:		begin
-					if (!txStop)	begin
-						nextState = TX;
-					end	else begin
-						nextState = IDLE;
-					end
-				end
-
-	TX		:	begin
-					if (txCnt==6'd23) begin
-						nextState  = PAUSE;
-					end	else begin
-						nextState  = TX;
-					end
-				end
-        
-	PAUSE	:	begin
-					if (pauseCnt==4'd2) begin
-						nextState  = CMD;
-					end	else begin
-						nextState  = PAUSE;
-					end
-				end
-	endcase
-end
-
-
-
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
 
+    reg startFlag;
+    reg startR;
+    reg [31:0] trCnt;
+    reg valReg;
+    reg valToRxFifo1;
+    reg lineBusy;
+    reg [5:0] ssCnt;
+    reg Ss;
+    reg [31:0]spiDataR;
+    reg oldDataFlag;
+    
+    reg ssR;
+    reg SSR;
+    reg [31:0] mosiReg0;
+    reg [5:0] ssNum;
+    reg [2:0] delayCnt;
+    reg stopFlag;
+    
+    wire ssPol = SelSt_i ? Ss : ~Ss;
+    
+    
+    //================================================================================
+    //  ASSIGNMENTS
+    //================================================================================
+    
+    
+    assign Ss_o = ssPol; 
+    
+    //================================================================================
+    //	CODING
+    //================================================================================
+    
+    always @(*) begin 
+        if (Start_i) begin  
+            Val_o = valReg;
+        end
+        else begin 
+            Val_o = 1'b0;
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (SelSt_i) begin 
+            if (!Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+        else begin 
+            if (Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge Clk_i) begin
+        if (valReg) begin  
+            spiDataR <= SpiData_i;
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            oldDataFlag = 1'b0;
+        end
+        else begin 
+            if (spiDataR == SpiData_i && (SpiData_i != 0) || EmptyFlag_i) begin 
+                oldDataFlag = 1'b1;
+            end
+            else begin 
+                oldDataFlag = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(posedge Clk_i) begin 
+        startR <= Start_i;
+    end
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            valToRxFifo1 = 1'b0;
+        end
+        else begin 
+            if (Start_i && !startR) begin 
+                valToRxFifo1 = 1'b1;
+            end
+            else begin 
+                valToRxFifo1 = 1'b0;
+            end
+        end
+    end
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            delayCnt <= 1'b0;
+        end
+        else begin 
+            if (stopFlag &&delayCnt < Stop_i) begin 
+                delayCnt <= delayCnt + 1'b1;
+            end
+            else begin 
+                delayCnt <= 1'b0;
+            end
+        end
+    end
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            stopFlag <= 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (ssPol && !ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if ( delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+            else begin 
+                if (!ssPol && ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if (delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(*) begin
+        if (SelSt_i) begin 
+            if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+        else begin 
+              if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+            
+    end
+    
+    
+    always @(*) begin
+        if (Rst_i) begin 
+            Mosi0_o = 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
+                end
+                else begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
+                end
+            end
+            else begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
+                end
+                else begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
+                end
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge Clk_i) begin
+        ssR <= ssPol;
+        SSR <= Ss;
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            startFlag = 1'b0;
+        end
+        else begin 
+            if (Start_i && !stopFlag && !EmptyFlag_i) begin 
+                startFlag = 1'b1;
+            end
+            else begin 
+                startFlag = 1'b0;
+            end
+        end
+    end
+    
+    always @(*) begin
+        if (SelSt_i) begin 
+            if (Ss_o && !ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+        else begin 
+            if (!Ss_o&& ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            ssNum = 1'b0;
+        end
+        else begin 
+            case (WidthSel_i) 
+                0 : begin 
+                    ssNum = 8;
+                end
+                1 : begin 
+                    ssNum = 16;
+                end
+                2 : begin 
+                    ssNum = 24;
+                end
+                3 : begin 
+                    ssNum = 32;
+                end
+            endcase
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            ssCnt <= 1'b0;
+        end
+        else if (ssCnt <= (ssNum+Lag_i+Lead_i)  && startFlag  ) begin 
+            ssCnt <= ssCnt + 1'b1;
+        end
+        else begin
+            if (ssCnt == ssNum-1 || !startFlag) begin 
+                ssCnt <= 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            Ss <= 1'b1;
+        end
+        else begin 
+            if (ssCnt <= (ssNum+Lag_i+Lead_i)  && startFlag ) begin 
+                Ss <= 1'b0;
+            end
+            else begin 
+                Ss <= 1'b1;
+            end
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg0 <= SpiData_i[31:0];
+        end
+        else begin
+            if (!EndianSel_i) begin 
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 << 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
+            end
+            else begin 
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 >> 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
+            end
+        end
+    end
+    
+    
+    
+    
+    
+    
+    
+    endmodule

src/src/Top/TopSbTmsg.v

@@ -39,18 +39,42 @@ module TopSbTmsg
 	input Mosi2_i,
 	input Mosi3_i,
 	
-	input Miso1_i,
-	input Miso2_i,
-	input MisoMax2870_i,
+	input MisoLdLmx_i,
+	input MisoDds_i,
+	input MisoLdMax2870_i,
 	
-	output I2CSck_o,
-	inout I2CSda_io,
+	output I2cScl_o,
+	inout I2cSda_io,
 	
 	output [DEVNUM-1:0] Ss_o,
 	output [DEVNUM-1:0] Sck_o,
 	output [DEVNUM-1:0] Mosi_o,
 	
-	output [21:0] Gpio_o
+	output RfLd_o,
+
+	//GPIO
+	output RfSw1_o,
+	output RfSw2_o,
+	output CtrlAmSw3_o,
+	output DdsSyncCtrlFpga_o,
+	output DdsResetFpga_o,
+	output DdsSyncFpga_o,
+	output SwCap4_o,
+	output AmAlcSw_o,
+	output SwCap3_o,
+	output SwCap2_o,
+	output SwCap1_o,
+	output AmAlc1Fix_o,
+	output PllVtuneCtrl_o,
+	output PllSyncCtrl_o,
+	output PllSync_o,
+	output PllLoopCtrl_o,
+	output DdsX2Fpga_o,
+	output DdsSaw2Fpga_o,
+	output RefOffsetCtrlFpga_o,
+	output GpioAdRfV1_o,
+	output GpioAdRfV2_o,
+	output DdsSaw1Fpga_o
 );
 
 //================================================================================
@@ -70,6 +94,7 @@ module TopSbTmsg
 
 	wire spiDataVal;
 	wire [WORDWIDTH-1:0] spiData;
+	wire [21:0] gpio1CtrlData;
 	
 	wire busyMosi1;
 	wire busyMosi4;
@@ -90,18 +115,74 @@ module TopSbTmsg
 	wire flagDirectAtt;	
 	wire flagDirectShReg;	
 	wire flagDirectMax;	
-	wire flagDirectGpio;	
-	wire flagDirectTemp;	
-	
-//================================================================================
-//  ASSIGNMENTS
+	wire flagDirectGpio1;
+	wire flagDirectGpio2;	
+	wire flagDirectTemp;
 
+	wire misoTemp;
+	wire misoGpio2;
+	wire anyFlag;
 
+	reg misoReg;	
 
+ //================================================================================
+    //  ASSIGNMENTS
+//================================================================================
+assign DdsSaw1Fpga_o 		= gpio1CtrlData[21];
+assign GpioAdRfV2_o 		= gpio1CtrlData[20];
+assign GpioAdRfV1_o 		= gpio1CtrlData[19];
+assign RefOffsetCtrlFpga_o	= gpio1CtrlData[18];
+assign DdsSaw2Fpga_o 		= gpio1CtrlData[17];
+assign DdsX2Fpga_o 			= gpio1CtrlData[16];
+assign PllLoopCtrl_o 		= gpio1CtrlData[15];
+assign PllSync_o 			= gpio1CtrlData[14];
+assign PllSyncCtrl_o 		= gpio1CtrlData[13];
+assign PllVtuneCtrl_o 		= gpio1CtrlData[12];
+assign AmAlc1Fix_o 			= gpio1CtrlData[11];
+assign SwCap1_o 			= gpio1CtrlData[10];
+assign SwCap2_o 			= gpio1CtrlData[9];
+assign SwCap3_o 			= gpio1CtrlData[8];
+assign AmAlcSw_o 			= gpio1CtrlData[7];
+assign SwCap4_o 			= gpio1CtrlData[6];
+assign DdsSyncFpga_o 		= gpio1CtrlData[5];
+assign DdsResetFpga_o 		= gpio1CtrlData[4];
+assign DdsSyncCtrlFpga_o 	= gpio1CtrlData[3];
+assign CtrlAmSw3_o 			= gpio1CtrlData[2];
+assign RfSw2_o 				= gpio1CtrlData[1];
+assign RfSw1_o 				= gpio1CtrlData[0];
 
+assign anyFlag = flagDirectTemp | flagDirectMax | flagDirectDds | flagDirectLmx | flagDirectGpio2;
+
+assign RfLd_o = MisoLdLmx_i && MisoLdMax2870_i;
+assign Miso1_io = misoReg;
 
 //================================================================================
 //  CODING
+always @(*) begin 
+	if (Rst_i) begin 
+		misoReg = 1'b0;
+	end
+	else begin 
+		if (flagDirectLmx) begin 
+			misoReg = MisoLdLmx_i;
+		end
+		else if (flagDirectDds) begin 
+			misoReg = MisoDds_i;
+		end
+		else if (flagDirectMax) begin 
+			misoReg = MisoLdMax2870_i;
+		end
+		else if (flagDirectTemp) begin 
+			misoReg = misoTemp;
+		end
+		else if (flagDirectGpio2) begin 
+			misoReg = misoGpio2;
+		end
+		else begin 
+			misoReg = 1'bz;
+		end
+	end
+end
 
 ClkGen ClkGen
 (
@@ -178,22 +259,154 @@ PacketAnalyzer1Mosi	PacketAnalyzer1Mosi
 	.FlagDirectAtt_o		(flagDirectAtt),
 	.FlagDirectShReg_o		(flagDirectShReg),
 	.FlagDirectMax_o		(flagDirectMax),
-	.FlagDirectGpio_o		(flagDirectGpio),
+	.FlagDirectGpio1_o		(flagDirectGpio1),
 	.FlagDirectTemp_o		(flagDirectTemp),
+	.FlagDirectGpio2_o		(flagDirectGpio2),
 	
 	.Busy_o					(busyMosi1)
 );
 
-GpioCtrl GpioCtrl
+LmxWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(24),
+	.DATA_WIDTH		(24)
+) LmxWrapper(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk60),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valLmxDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+DDSWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(3),
+	.OUT_WIDTH		(64),
+	.DATA_WIDTH		(64)
+) DDSWrapper(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk50),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valDdsDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+PotWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16),
+	.DATA_WIDTH		(16)
+) PotWrapper(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk5),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valPotDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+DacWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16),
+	.DATA_WIDTH		(16)
+) DacWrapper(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk50),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valDacDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+AttenuatorWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16),
+	.DATA_WIDTH		(16)
+) AttenuatorWrapper(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk50),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valAttDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+ShiftRegWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(8),
+	.DATA_WIDTH		(8)
+) ShiftRegWrapper(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk26dot25),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valShRegDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+Max2870Wrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(2),
+	.OUT_WIDTH		(32),
+	.DATA_WIDTH		(32)
+) Max2870Wrapper(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk20),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valMaxDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+TempRead TempRead (
+	.Clk24Mhz_i				(clk24),
+	.Rst_i					(Rst_i),
+	.ClkSpi_i				(Sck_i),
+	.FlagDirectTempRead_i	(flagDirectTemp),
+	.I2cScl_o				(I2cScl_o),
+	.I2cSda_io				(I2cSda_io),
+	.MisoTemp_o				(misoTemp)
+);
+
+Gpio1Ctrl Gpio1Ctrl
 (
 	.Clk_i					(gclk100),
 	.Rst_i					(Rst_i),
-	
 	.ValGpioDataToFifo_i	(valGpioDataToFifo),
+	.ValDataFromSpi_i		(spiDataVal),
+	.FlagDirectGpio1_i		(flagDirectGpio1),
 	.Data_i					(spiData),
-
-	.GpioReg_o				(Gpio_o)
+	.GpioReg_o				(gpio1CtrlData)
 );
 
+Gpio2Read Gpio2Read (
+	.Clk_i				(gclk100),
+	.Rst_i				(Rst_i),
+	.ClkSpi_i			(Sck_i),
+	.LdMax_i			(MisoLdMax2870_i),
+	.LdLmx_i			(MisoLdLmx_i),
+	.FlagDirectGpio2_i	(flagDirectGpio2),
+	.MisoGpio2_o		(misoGpio2)
+);
 
 endmodule

src/src/Top/TopSbTmsgTb.sv

@@ -0,0 +1,351 @@
+`timescale 1ns/1ps
+
+module TopSbTmsgTb;
+   parameter CLK_PERIOD = 8.13; // Clock period in ns
+
+    // Inputs
+    logic Clk_i;
+    logic Clk100;
+    logic Clk20;
+    logic Clk80;
+    logic Clk50;
+    logic Clk24;
+    logic Clk10; 
+    logic Rst_i;
+    logic Start_i;
+    logic CPHA_i;
+    logic [31:0] SPIdata;
+	logic SpiDataVal_i;
+    logic SELST_i;
+    logic [1:0] WidthSel_i;
+    logic LAG_i;
+    logic LEAD_i;
+    logic EndianSel_i;
+    logic [5:0] Stop_i;
+    logic PulsePol_i;
+    logic MisoLdLmx_i;
+
+    // Outputs
+    wire Mosi0_o;
+    wire Mosi1_o;
+    wire Mosi1_io;
+    wire Mosi2_o;
+    wire Mosi3_o;
+    wire Sck_o;
+    wire Ss_o;
+    wire Val_o;
+
+    wire valR;
+    wire valQ;
+    wire SckR;
+    wire SckQ;
+    wire SsR;
+    wire SsQ;
+    wire mosi0R;
+    wire mosi0Q;
+
+    wire locked;
+    wire rstInit;
+
+    logic [16:0] trCnt;
+    logic [4:0] trCntSync;
+
+
+    logic modeSel; 
+    logic [23:0] randData;
+    logic [31:0] randData32;
+    logic [5:0] QSPITotalWordNum;
+    logic Stop;
+    logic [31:0] stopCnt;
+    logic rstForFPGA;
+
+//***********************************************
+//	            Lines From RF Top
+//***********************************************
+
+    logic [7:0] sckFromRFTop;
+    logic [7:0] mosiFromRFTop;
+    logic [7:0] ssFromRFTop;
+
+
+    logic [23:0] dataFromSPItb;
+    logic        valFromSPItb; 
+
+//***********************************************
+//	            CLASSES
+//***********************************************
+
+class Packet;
+    rand bit [23:0] data;
+    rand bit [31:0] data32;
+endclass
+
+Packet pkt;
+
+//***********************************************
+//	      HEADERS FOR DEVICES
+//***********************************************
+localparam [4:0]  DeviceIdLmx2594 = 5'h0;
+localparam [4:0]  DeviceIdDDS = 5'h1;
+localparam [4:0]  DeviceIdPot = 5'h2;
+localparam [4:0]  DeviceIdDac = 5'h3;
+localparam [4:0]  DeviceIdAtt = 5'h4;
+localparam [4:0]  DeviceIdShReg = 5'h5;
+localparam [4:0]  DeviceIdMax2870 = 5'h6;
+localparam [4:0]  DeviceIdGpio1 = 5'h7;
+localparam [4:0]  DeviceIdTemp = 5'h8;
+localparam [4:0]  DeviceIdGpio2 = 5'h9;
+
+localparam [16:0] Gpio1InitWordNum = 17'd1;
+localparam [16:0] Gpio2InitWordNum = 17'd1;
+localparam [16:0] Lmx2594InitWordNum = 17'd113;
+localparam [16:0] DDSInitWordNum = 17'd37;
+localparam [16:0] MaxInitWordNum = 17'd6;
+
+localparam [23:0] InitGpio1Header        = {1'h0, DeviceIdGpio1, Gpio1InitWordNum, 1'h1};
+localparam [23:0] InitGpio2Header        = {1'b0, DeviceIdGpio2,Gpio2InitWordNum,1'h1 };
+localparam [23:0] InitLMX2594Header     = {1'h0, DeviceIdLmx2594, Lmx2594InitWordNum, 1'h1};
+localparam [23:0] InitDDSHeader         = {1'h0, DeviceIdDDS, DDSInitWordNum, 1'h1};
+localparam [23:0] InitMAX2870Header     = {1'h0, DeviceIdMax2870, MaxInitWordNum, 1'h1};
+localparam [3:0]  LMXWordNum = 4'd14;
+localparam [1:0]  DDSWordNum = 2'd3;
+localparam        POTWordNum = 1'd1;
+localparam        DACWordNum = 1'd1;
+localparam        ATTWordNum = 1'd1;
+localparam [1:0]  ShRegWordNum = 1'd1;
+localparam [2:0]  MaxWordNum =   3'd2;
+localparam [1:0]  GPIOWordNum =  2'd1;
+
+localparam [23:0] AllDevQSPIHeader = {1'h1, LMXWordNum, DDSWordNum, POTWordNum, DACWordNum,ATTWordNum, ShRegWordNum,MaxWordNum, GPIOWordNum, 7'h1};
+
+//***********************************************
+//	           ASSIGNS
+//***********************************************
+assign Val_o = (modeSel) ? valQ : valR;
+assign Sck_o = (modeSel) ? SckQ : SckR;
+assign Ss_o = (modeSel) ? SsQ : SsR;
+assign Mosi0_o = (modeSel) ? mosi0Q : mosi0R;
+assign MisoLdLmx_i = 1'b1;
+
+assign emptyFlagTx = (trCnt > 187) ? 1'b1 : 1'b0;
+assign QSPITotalWordNum = LMXWordNum + DDSWordNum + POTWordNum + DACWordNum + ATTWordNum + ShRegWordNum + MaxWordNum + GPIOWordNum; 
+
+//***********************************************
+//	           CLOCK GENERATION
+//***********************************************
+always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
+always #(10/2) Clk100 = ~Clk100;
+always #(20/2) Clk50 = ~Clk50;
+always #(12.5/2) Clk80 = ~Clk80;
+always #(41.67/2) Clk24 = ~Clk24;
+always #(50/2) Clk20 = ~Clk20;
+always #(50)   Clk10 = ~Clk10; 
+
+//***********************************************
+//	           INITIALIZATION
+//***********************************************
+
+initial begin
+      // Initialize Inputs
+      Clk_i = 1;
+      Clk100= 1;
+      Clk20 = 1;
+      Clk50 = 1;
+      Clk80 = 1;
+      Clk24 = 1;
+      rstForFPGA = 0;
+      Clk10 = 1;
+      pkt = new();
+      Rst_i = 1;
+      Start_i = 0;
+      CPHA_i = 0;		SpiDataVal_i = 0;
+      SELST_i = 1;//0:High, 1:Low
+    //   WidthSel_i = 2; // 3-32bit, 2-24bit, 1-16bit, 0-8bit
+      LAG_i = 0;
+      LEAD_i = 0;
+      EndianSel_i = 0; // 0:MSB first, 1:lsb first
+      PulsePol_i = 0;
+      // Reset the system
+      #(CLK_PERIOD*10) Rst_i = 0;
+      #(300000-60) rstForFPGA = 1;
+      #(CLK_PERIOD*74) rstForFPGA = 0;
+      #(20) Start_i = 1; // Start SPI transaction
+    
+  end
+//***********************************************
+
+always_ff @(posedge Clk10) begin
+    if (Rst_i) begin 
+        trCnt <= 0;
+    end
+    else begin 
+        if (Val_o) begin 
+            trCnt <= trCnt + 1;
+        end
+    end
+end
+
+genvar i;
+always_comb begin 
+    if (Rst_i) begin 
+        WidthSel_i = 2'd0;
+    end
+    else begin 
+        if (trCnt > 152 && trCnt < 159) begin 
+            WidthSel_i = 2'd3;
+        end
+        else begin 
+            WidthSel_i = 2'd2;
+        end
+    end
+end
+
+always_comb begin 
+    if (Rst_i) begin 
+        modeSel = 0;
+    end
+    else begin 
+        if (trCnt == 159) begin 
+            modeSel = 1;
+        end
+    end
+end
+
+always_comb begin 
+    if (Rst_i) begin 
+        Stop_i = 6'd0;
+    end
+    else begin 
+        if (trCnt == 158) begin 
+            Stop_i = 6'h0;
+        end
+        else begin
+            Stop_i = 6'd0;
+        end
+    end
+end
+
+always_ff @(posedge Clk10) begin 
+    if (Rst_i) begin 
+        randData<=0;
+        randData32 <= 0;
+    end
+    else begin 
+        randData <= pkt.randomize(data);
+        randData32 <= pkt.randomize(data32);
+    end
+end
+
+always_comb begin 
+    if (Rst_i) begin 
+        SPIdata = 0;
+    end
+    else begin 
+        // if (!rstInit && locked) begin
+            if (trCnt == 0) begin 
+                SPIdata = InitGpio2Header;
+            end
+            else if (trCnt == 2) begin 
+                SPIdata = InitGpio2Header;
+            end
+            else if (trCnt == 4) begin
+                SPIdata = InitLMX2594Header;
+            end
+            // else if (trCnt > 0 && trCnt < 114) begin 
+            //     SPIdata = pkt.data;
+            // end
+            else if (trCnt == 118) begin 
+                SPIdata = InitDDSHeader;
+            end
+            else if (trCnt == 156) begin 
+                SPIdata = InitMAX2870Header;
+            end
+            else if (trCnt > 156 && trCnt < 163) begin 
+                // if (trCnt % 2 == 0) begin 
+                //     SPIdata = 32'haaaaaaaa;
+                // end
+                // else begin 
+                //     SPIdata = 32'h55555555;
+                // end
+                SPIdata = 32'haaaaaaaa;
+                // SPIdata = pkt.data32;
+            end
+            else if (trCnt == 163) begin 
+                SPIdata = AllDevQSPIHeader;
+            end
+            else begin
+                // if (trCnt % 2 == 0) begin 
+                //     SPIdata = 24'haaaaaa;
+                // end
+                // else begin 
+                //     SPIdata = 24'h555555;
+                // end
+                SPIdata = 24'haaaaaa;
+                // SPIdata = pkt.data;
+            end
+        end
+    end
+// end
+
+//***********************************************
+//	           DUT INSTANTIATION
+//***********************************************
+    GSR GSR(.GSRI(1'b1));
+
+   ExtSpiMEmul ExtSpiMEmul_inst (
+        .Clk_i(Clk10), 
+        .Rst_i(Rst_i || modeSel), 
+        .Start_i(Start_i), 
+        .ClockPhase_i(CPHA_i),
+        .EmptyFlag_i(emptyFlagTx), 
+        .SpiData_i(SPIdata),
+        .SelSt_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .Lag_i(LAG_i),
+        .Lead_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(Stop_i),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_o(mosi0R),
+        .Sck_o(SckR),
+        .Ss_o(SsR),
+        .Val_o(valR)
+    );
+
+    ExtQspiMEmul ExtQspiMEmul_inst (
+        .Clk_i(Clk10),
+        .Rst_i(Rst_i || !modeSel),
+        .Start_i(Start_i),
+        .ClockPhase_i(CPHA_i),
+        .EmptyFlag_i(emptyFlagTx),
+        .SpiData_i(SPIdata),
+        .SelSt_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .Lag_i(LAG_i),
+        .Lead_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(Stop_i),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_o(mosi0Q),
+        .Mosi1_o(Mosi1_o),
+        .Mosi2_o(Mosi2_o),
+        .Mosi3_o(Mosi3_o),
+        .Sck_o(SckQ),
+        .Ss_o(SsQ),
+        .Val_o(valQ)
+    );
+
+    TopSbTmsg TopSbTmsg_inst (
+        .Clk_i(Clk24),
+        .Rst_i(rstForFPGA),
+        .Sck_i(Sck_o),
+        .Ss_i(Ss_o),
+        .MisoLdLmx_i(1'b1),
+        .MisoLdMax2870_i(1'b1),
+        .Mosi0_i(Mosi0_o),
+        .Mosi1_io(Mosi1_o),
+        .Mosi2_i(Mosi2_o),
+        .Mosi3_i(Mosi3_o)
+    );
+
+    endmodule

src/src/Top/TopSbTmsgTb.v

@@ -1,275 +0,0 @@
-`timescale 1ns / 1ps
-
-//////////////////////////////////////////////////////////////////////////////////
-// Company: Tair
-// Engineer: Churbanov S.
-// 
-// Create Date:     
-// Design Name: 
-// Module Name:    InterfaceArbiter
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-
-module TopSbTmsgTb();
-
-//================================================================================
-//  REG/WIRE
-	
-	parameter OUTWORDWIDTH = 24;
-	parameter SSPIWORDWIDTH = 24;
-	parameter QSPIWORDWIDTH = 6;
-	
-	localparam [1:0] IDLE = 0;
-	localparam [1:0] SINGLE = 1;
-	localparam [1:0] DELAY = 2;
-	localparam [1:0] QUAD = 3;
-	
-	reg spiMode = 1'b0; //0 - single 1- quad
-	
-	reg [31:0] tbCnt;
-	reg [31:0] delCnt;
-	reg stateCnt;
-	
-	reg Clk100;
-	reg Clk10;
-	
-	reg [1:0] currState;
-	reg [1:0] nextState;
-	
-	reg rst;
-	
-	wire txStart = (tbCnt == 100 | tbCnt == 3000);
-	wire txDoneS;
-	wire txDoneQ;
-	
-	
-	wire sckS;
-	wire sckQ;
-	wire ssS;
-	wire ssQ;
-	
-	wire ss;
-	wire sck;
-	
-	wire mosi0S;
-	wire mosi0Q;
-	wire mosi1Q;
-	wire mosi2Q;
-	wire mosi3Q;
-	
-	wire delDone = (delCnt == 500);
-//================================================================================
-//  ASSIGNMENTS
-	
-	assign sck = (currState==SINGLE) ? sckS:sckQ;
-	assign ss = (currState==SINGLE) ? ssS:ssQ;
-	assign mosi0 = (currState==SINGLE) ? mosi0S:mosi0Q;
-	assign mosi1 = (currState==SINGLE) ? 1'b1:mosi1Q;
-	assign mosi2 = (currState==SINGLE) ? 1'b1:mosi2Q;
-	assign mosi3 = (currState==SINGLE) ? 1'b1:mosi3Q;
-//================================================================================
-//clocks gen
-	always	#5 Clk100	=	~Clk100;	
-	always	#50 Clk10	=	~Clk10;	
-	
-	
-//================================================================================
-//  CODING
-
-initial begin
-	Clk100	=	1'b1;
-	Clk10	=	1'b1;
-	rst		=	1'b1;
-#100;
-	rst		=	1'b0;
-end	
-	
-always	@(negedge	Clk100)	begin
-	if	(!rst)		begin
-		tbCnt	<=	tbCnt+1;
-	end	else	begin
-		tbCnt	<=	0;
-	end
-end
-
-always	@(posedge	Clk100)	begin
-	if	(!rst)		begin
-		if (currState == DELAY) begin
-			delCnt	<=	delCnt+1;
-		end	else	begin
-			delCnt	<=	0;
-		end
-	end else	begin
-		delCnt	<=	0;
-	end
-end
-
-always	@(negedge	Clk10)	begin
-	if	(!rst)		begin
-		if (txDoneS|txDoneQ) begin
-			stateCnt	<=	stateCnt+1;
-		end	
-	end else begin
-		stateCnt <= 0;
-	end
-end
-
-always	@(posedge	Clk100)	begin
-	if	(!rst)		begin
-		case (stateCnt)
-			0:	begin
-					spiMode <= 1'b0;
-				end
-			1:	begin
-					spiMode <= 1'b1;
-				end
-			default:begin
-						spiMode <= 1'b0;
-					end
-		endcase
-	end else begin
-		spiMode <= 1'b0;
-	end
-end
-
-always	@(posedge	Clk100)	begin
-	if	(rst)	begin
-		currState	<=	IDLE;
-	end	else	begin
-		currState	<=	nextState;
-	end
-end
-
-
-always @(*) begin
-	nextState	=	IDLE;
-	case(currState)
-	IDLE	:	begin
-					if (txStart)	begin
-						case (spiMode)
-							1'b0:	begin
-											nextState = SINGLE;
-										end
-							1'b1:		begin
-											nextState = QUAD;
-										end
-						endcase
-					end	else begin
-						nextState = IDLE;
-					end
-				end
-				
-	SINGLE	:	begin
-					if (txDoneS)	begin
-						nextState = DELAY;
-					end	else begin
-						nextState = SINGLE;
-					end
-				end
-				
-	DELAY	:	begin
-					if (delDone)	begin
-						nextState = QUAD;
-					end	else begin
-						nextState = DELAY;
-					end
-				end
-				
-	QUAD		:	begin
-					if (txDoneQ) begin
-						nextState  = IDLE;
-					end	else begin
-						nextState  = QUAD;
-					end
-				end
-	endcase
-end
-
-ExtSpiMEmul SingleSpiSm
-(
-	.Rst_i		(rst),
-	.Clk_i		(Clk10),
-	
-	.Start_i	((currState==SINGLE)),
-	.TxDone_o	(txDoneS),
-	
-	.Sck_o		(sckS),
-	.Ss_o		(ssS),
-	.Mosi_o		(mosi0S)
-	
-);
-
-ExtQSpiMEmul QuadSpiSm
-(
-	.Rst_i		(rst),
-	.Clk_i		(Clk10),
-	
-	.Start_i	((currState==QUAD)),
-	.TxDone_o	(txDoneQ),
-	
-	.Sck_o		(sckQ),
-	.Ss_o		(ssQ),
-	.Mosi0_o	(mosi0Q),
-	.Mosi1_o	(mosi1Q),
-	.Mosi2_o	(mosi2Q),
-	.Mosi3_o	(mosi3Q)
-	
-);
-
-TopSbTmsg DUT
-(
-	.Clk_i	(Clk100),
-	.Rst_i	(rst),
-	
-	.Sck_i	(sck),
-	.Ss_i	(ss),
-	
-	.Mosi0_i	(mosi0),
-	.Mosi1_io	(mosi1),
-	.Mosi2_i	(mosi2),
-	.Mosi3_i	(mosi3),
-	
-	.Miso1_i		(),
-	.Miso2_i		(),
-	.MisoMax2870_i	(),
-	
-	.I2CSck_o	(),
-	.I2CSda_io	(),
-	
-	.Ss_o		(),
-	.Sck_o		(),
-	.Mosi_o		(),
-	
-	.Gpio_o		()
-);
-
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

src/src/Top/TopSbTmsg_Fifos.do

@@ -0,0 +1,167 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider Lmx_Wrapper
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/IN_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/WR_NUM
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/OUT_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/DATA_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/WrClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/RdClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/Rst_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/Data_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/Val_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/Ss_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/Sck_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/Mosi_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/dataFromLmxFifoCtrl
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/dataFromLmxFifo
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/readEnLmx
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/writeEnLmx
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/valRdDataLMX
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/busySpiMLmx
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/lmxFifoFull
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/LmxWrapper/lmxFifoEmpty
+add wave -noupdate -divider DDS_Wrapper
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/IN_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/WR_NUM
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/OUT_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/DATA_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/WrClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/RdClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/Rst_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/Data_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/Val_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/Ss_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/Sck_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/Mosi_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/dataFromDdsFifoCtrl
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/dataFromDdsFifo
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/readEnDds
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/writeEnDds
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/valRdDataDDS
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/busySpiMDds
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/ddsFifoFull
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DDSWrapper/ddsFifoEmpty
+add wave -noupdate -divider Pot_Wrapper
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/IN_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/WR_NUM
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/OUT_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/DATA_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/WrClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/RdClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/Rst_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/Data_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/Val_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/Ss_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/Sck_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/Mosi_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/dataFromPotFifoCtrl
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/dataFromPotFifo
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/readEnPot
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/writeEnPot
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/valRdDataPOT
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/busySpiMPot
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/potFifoFull
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/PotWrapper/potFifoEmpty
+add wave -noupdate -divider Dac_Wrapper
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/IN_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/WR_NUM
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/OUT_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/DATA_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/WrClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/RdClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/Rst_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/Data_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/Val_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/Ss_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/Sck_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/Mosi_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/dataFromDacFifoCtrl
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/dataFromDacFifo
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/readEnDac
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/writeEnDac
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/valRdDataDAC
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/busySpiMDac
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/dacFifoFull
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/DacWrapper/dacFifoEmpty
+add wave -noupdate -divider AttenuatorWrapper
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/IN_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/WR_NUM
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/OUT_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/DATA_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/WrClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/RdClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/Rst_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/Data_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/Val_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/Ss_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/Sck_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/Mosi_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/dataFromAttFifoCtrl
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/dataFromAttFifo
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/readEnAtt
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/writeEnAtt
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/valRdDataATT
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/busySpiMAtt
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/attFifoFull
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/AttenuatorWrapper/attFifoEmpty
+add wave -noupdate -divider ShiftRegWrapper
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/IN_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/WR_NUM
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/OUT_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/DATA_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/WrClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/RdClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/Rst_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/Data_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/Val_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/Ss_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/Sck_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/Mosi_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/dataFromShRegFifoCtrl
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/dataFromShRegFifo
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/readEnShReg
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/writeEnShReg
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/valRdDataShReg
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/busySpiMShReg
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/shRegFifoFull
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/ShiftRegWrapper/shRegFifoEmpty
+add wave -noupdate -divider Max2870Wrapper
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/IN_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/WR_NUM
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/OUT_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/DATA_WIDTH
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/WrClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/RdClk_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/Rst_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/Data_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/Val_i
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/Ss_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/Sck_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/Mosi_o
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/dataFromMaxFifoCtrl
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/dataFromMaxFifo
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/readEnMax
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/writeEnMax
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/valRdDataMAX
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/busySpiMMax
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/maxFifoFull
+add wave -noupdate /TopSbTmsgTb/TopSbTmsg_inst/Max2870Wrapper/maxFifoEmpty
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {840629685 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {753643129 ps} {755703694 ps}

src/src/WrapFifoChain/AttenuatorWrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     AttenuatorWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module AttenuatorWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 16,
+    parameter DATA_WIDTH = 16
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromAttFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromAttFifo;
+wire readEnAtt;
+wire writeEnAtt;
+wire valRdDataATT;
+wire busySpiMAtt;
+wire attFifoFull;
+wire attFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(IN_WIDTH),
+	.WR_NUM			(WR_NUM),
+	.OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrlAtt
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMAtt),
+	.FifoFull_i		(attFifoFull),
+	.FifoEmpty_i	(attFifoEmpty),
+	.Data_o			(dataFromAttFifoCtrl),
+	.ReadEn_o		(readEnAtt),
+	.WriteEn_o		(writeEnAtt),
+	.ValRdData_o	(valRdDataATT)
+);
+
+Fifo16x3 FifoAtt_inst (
+	.Data	(dataFromAttFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnAtt),
+	.RdEn	(readEnAtt),
+	.Full	(attFifoFull),
+	.Empty	(attFifoEmpty),
+	.Q		(dataFromAttFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(DATA_WIDTH)
+)SpiMAtt(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataATT),
+	.SpiData_i	(dataFromAttFifo),
+	.Busy_o	    (busySpiMAtt),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/WrapFifoChain/DDSWrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     DDSWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module DDSWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 3,
+    parameter OUT_WIDTH = 64,
+    parameter DATA_WIDTH = 64
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromDdsFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromDdsFifo;
+wire readEnDds;
+wire writeEnDds;
+wire valRdDataDDS;
+wire busySpiMDds;
+wire ddsFifoFull;
+wire ddsFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(IN_WIDTH),
+	.WR_NUM			(WR_NUM),
+	.OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrlDDS
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMDds),
+	.FifoFull_i		(ddsFifoFull),
+	.FifoEmpty_i	(ddsFifoEmpty),
+	.Data_o			(dataFromDdsFifoCtrl),
+	.ReadEn_o		(readEnDds),
+	.WriteEn_o		(writeEnDds),
+	.ValRdData_o	(valRdDataDDS)
+);
+
+FifoDDS FifoDDS_inst (
+	.Data	(dataFromDdsFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnDds),
+	.RdEn	(readEnDds),
+	.Full	(ddsFifoFull),
+	.Empty	(ddsFifoEmpty),
+	.Q		(dataFromDdsFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(DATA_WIDTH)
+)SpiMDDS(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataDDS),
+	.SpiData_i	(dataFromDdsFifo),
+	.Busy_o	    (busySpiMDds),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/WrapFifoChain/DacWrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     DDSWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module DacWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 16,
+    parameter DATA_WIDTH = 16
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromDacFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromDacFifo;
+wire readEnDac;
+wire writeEnDac;
+wire valRdDataDAC;
+wire busySpiMDac;
+wire dacFifoFull;
+wire dacFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(IN_WIDTH),
+	.WR_NUM			(WR_NUM),
+	.OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrlDac
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMDac),
+	.FifoFull_i		(dacFifoFull),
+	.FifoEmpty_i	(dacFifoEmpty),
+	.Data_o			(dataFromDacFifoCtrl),
+	.ReadEn_o		(readEnDac),
+	.WriteEn_o		(writeEnDac),
+	.ValRdData_o	(valRdDataDAC)
+);
+
+Fifo16x3 FifoDAC_inst (
+	.Data	(dataFromDacFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnDac),
+	.RdEn	(readEnDac),
+	.Full	(dacFifoFull),
+	.Empty	(dacFifoEmpty),
+	.Q		(dataFromDacFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(DATA_WIDTH)
+)SpiMDac(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataDAC),
+	.SpiData_i	(dataFromDacFifo),
+	.Busy_o	    (busySpiMDac),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/WrapFifoChain/Fifo16x3/Fifo16x3.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=Fifo16x3
+module=Fifo16x3
+target_device=gw1n9-014
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=true
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=16
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=false
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=16
+WriteDepth=2

src/src/WrapFifoChain/Fifo16x3/Fifo16x3.v

@@ -0,0 +1,187 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Thu Apr 25 16:04:59 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+IsmCBviST/NaLrbecssUM4rq97mLxpIwmAMLvgPpLBryi3SVk7UkqtY=
+`pragma protect end_protected
+module Fifo16x3 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [15:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [15:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.Fifo16x3  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[15:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[15:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* Fifo16x3 */

src/src/WrapFifoChain/Fifo16x3/Fifo16x3.vo

@@ -0,0 +1,353 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.02
+//Created Time: Thu Apr 25 16:04:59 2024
+
+`timescale 100 ps/100 ps
+module Fifo16x3(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [15:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [15:0] Q;
+output Empty;
+output Full;
+wire [15:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [15:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n217_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+wire [31:16] \fifo_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n217_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n217_4 )
+);
+defparam \fifo_inst/n217_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
+);
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/reset_r [1]),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n217_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n217_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[15:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:16], Q[15:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=16;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=16;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/WrapFifoChain/Fifo16x3/Fifo16x3_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Thu Apr 25 16:04:59 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	Fifo16x3 your_instance_name(
+		.Data(Data_i), //input [15:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [15:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/Fifo16x3/temp/FIFOHS"/>
+        <Option type="output_file" value="Fifo16x3.vg"/>
+        <Option type="output_template" value="Fifo16x3_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'Fifo16x3'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "Fifo16x3"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3.vg

@@ -0,0 +1,187 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Thu Apr 25 16:04:59 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+t/bYNDjO0d+SB5/il7zBD/3fBQDGuJm2Z5KM7Q==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+IsmCBviST/NaLrbecssUM4rq97mLxpIwmAMLvgPpLBryi3SVk7UkqtY=
+`pragma protect end_protected
+module Fifo16x3 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [15:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [15:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.Fifo16x3  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[15:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[15:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* Fifo16x3 */

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">Fifo16x3 (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">19</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="Fifo16x3" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Thu Apr 25 16:04:59 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	Fifo16x3 your_instance_name(
+		.Data(Data_i), //input [15:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [15:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,5 @@
+`define module_name Fifo16x3
+`define EBR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 16;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 16;

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/WrapFifoChain/FifoDDS/FifoDDS.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoDDS
+module=FifoDDS
+target_device=gw1n9-014
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=true
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=64
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=false
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=64
+WriteDepth=2

src/src/WrapFifoChain/FifoDDS/FifoDDS.v

@@ -0,0 +1,199 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Thu Apr 25 16:06:49 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7024)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+yLUXcvMsVv4bPZxPFw==
+`pragma protect end_protected
+module FifoDDS (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [63:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [63:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoDDS  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[63:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[63:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoDDS */

src/src/WrapFifoChain/FifoDDS/FifoDDS.vo

@@ -0,0 +1,373 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.02
+//Created Time: Thu Apr 25 16:06:49 2024
+
+`timescale 100 ps/100 ps
+module FifoDDS(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [63:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [63:0] Q;
+output Empty;
+output Full;
+wire [63:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [63:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n457_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n457_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n457_4 )
+);
+defparam \fifo_inst/n457_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
+);
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/reset_r [1]),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n457_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n457_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({Data[31:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.DO({Q[31:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_1_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({Data[63:32]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.DO({Q[63:32]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/WrapFifoChain/FifoDDS/FifoDDS_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Thu Apr 25 16:06:49 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoDDS your_instance_name(
+		.Data(Data_i), //input [63:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [63:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoDDS/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoDDS.vg"/>
+        <Option type="output_template" value="FifoDDS_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoDDS'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoDDS"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoDDS\temp\FIFOHS\FifoDDS.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoDDS\temp\FIFOHS\FifoDDS_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoDDS\temp\FIFOHS\FifoDDS_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS.vg

@@ -0,0 +1,199 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Thu Apr 25 16:06:49 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+Xs0Rq7KS+nMjcFcl7E3CRA+0+XO4iCSxRkS+iA==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7024)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+`pragma protect end_protected
+module FifoDDS (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [63:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [63:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoDDS  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[63:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[63:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoDDS */

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoDDS (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">19</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">2</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoDDS" Register="19" Lut="18" Bsram="2" T_Register="19(19)" T_Lut="18(18)" T_Bsram="2(2)"/>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Thu Apr 25 16:06:49 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoDDS your_instance_name(
+		.Data(Data_i), //input [63:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [63:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,5 @@
+`define module_name FifoDDS
+`define EBR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 64;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 64;

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/WrapFifoChain/FifoLMX/FifoLMX.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoLMX
+module=FifoLMX
+target_device=gw1n9-014
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=true
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=24
+ReadDepth=16
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=false
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=24
+WriteDepth=16

src/src/WrapFifoChain/FifoLMX/FifoLMX.v

@@ -0,0 +1,304 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Thu Apr 25 16:07:21 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=13040)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+iquJKrJAOuQAmJm6Dbw/7b7Bf5o03PviM2gY4OBRgfCcMxEADJT1Tcslq6E=
+`pragma protect end_protected
+module FifoLMX (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [23:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [23:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoLMX  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[23:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[23:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoLMX */

src/src/WrapFifoChain/FifoLMX/FifoLMX.vo

@@ -0,0 +1,681 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.02
+//Created Time: Thu Apr 25 16:07:21 2024
+
+`timescale 100 ps/100 ps
+module FifoLMX(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [23:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [23:0] Q;
+output Empty;
+output Full;
+wire [23:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [23:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n23_5 ;
+wire \fifo_inst/n29_4 ;
+wire \fifo_inst/wfull_val ;
+wire \fifo_inst/n371_4 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/Equal.rgraynext_1_4 ;
+wire \fifo_inst/Equal.wgraynext_1_4 ;
+wire \fifo_inst/Equal.wgraynext_2_4 ;
+wire \fifo_inst/Equal.wgraynext_3_4 ;
+wire \fifo_inst/wfull_val_4 ;
+wire \fifo_inst/wfull_val_5 ;
+wire \fifo_inst/n371_5 ;
+wire \fifo_inst/wfull_val1_16 ;
+wire \fifo_inst/Full_11 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n130_1_SUM ;
+wire \fifo_inst/n130_3 ;
+wire \fifo_inst/n131_1_SUM ;
+wire \fifo_inst/n131_3 ;
+wire \fifo_inst/n132_1_SUM ;
+wire \fifo_inst/n132_3 ;
+wire \fifo_inst/n133_1_SUM ;
+wire \fifo_inst/n133_3 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [3:0] \fifo_inst/Equal.rgraynext ;
+wire [3:0] \fifo_inst/Equal.wgraynext ;
+wire [4:0] \fifo_inst/rbin_num_next ;
+wire [4:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [4:0] \fifo_inst/rbin_num ;
+wire [4:0] \fifo_inst/Equal.rq1_wptr ;
+wire [4:0] \fifo_inst/Equal.rq2_wptr ;
+wire [3:0] \fifo_inst/rptr ;
+wire [4:0] \fifo_inst/wptr ;
+wire [3:0] \fifo_inst/Equal.wbin ;
+wire [31:24] \fifo_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n23_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n23_5 )
+);
+defparam \fifo_inst/n23_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n29_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n29_4 )
+);
+defparam \fifo_inst/n29_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_1_s0  (
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I1(\fifo_inst/rbin_num_next [1]),
+	.I2(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/Equal.rgraynext [1])
+);
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=8'h1E;
+LUT3 \fifo_inst/Equal.rgraynext_2_s0  (
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/rbin_num [3]),
+	.F(\fifo_inst/Equal.rgraynext [2])
+);
+defparam \fifo_inst/Equal.rgraynext_2_s0 .INIT=8'h1E;
+LUT4 \fifo_inst/Equal.rgraynext_3_s0  (
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/rbin_num [3]),
+	.I3(\fifo_inst/rbin_num [4]),
+	.F(\fifo_inst/Equal.rgraynext [3])
+);
+defparam \fifo_inst/Equal.rgraynext_3_s0 .INIT=16'h07F8;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/n23_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT4 \fifo_inst/Equal.wgraynext_1_s0  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_1_4 ),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/Equal.wbin [2]),
+	.F(\fifo_inst/Equal.wgraynext [1])
+);
+defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h0BF4;
+LUT4 \fifo_inst/Equal.wgraynext_2_s0  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_2_4 ),
+	.I2(\fifo_inst/Equal.wbin [2]),
+	.I3(\fifo_inst/Equal.wbin [3]),
+	.F(\fifo_inst/Equal.wgraynext [2])
+);
+defparam \fifo_inst/Equal.wgraynext_2_s0 .INIT=16'h0BF4;
+LUT4 \fifo_inst/Equal.wgraynext_3_s0  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_3_4 ),
+	.I2(\fifo_inst/Equal.wbin [3]),
+	.I3(\fifo_inst/wptr [4]),
+	.F(\fifo_inst/Equal.wgraynext [3])
+);
+defparam \fifo_inst/Equal.wgraynext_3_s0 .INIT=16'h0BF4;
+LUT4 \fifo_inst/wfull_val_s0  (
+	.I0(\fifo_inst/wptr [4]),
+	.I1(\fifo_inst/rbin_num [4]),
+	.I2(\fifo_inst/wfull_val_4 ),
+	.I3(\fifo_inst/wfull_val_5 ),
+	.F(\fifo_inst/wfull_val )
+);
+defparam \fifo_inst/wfull_val_s0 .INIT=16'h6000;
+LUT3 \fifo_inst/n371_s1  (
+	.I0(\fifo_inst/wfull_val_4 ),
+	.I1(\fifo_inst/wfull_val_5 ),
+	.I2(\fifo_inst/n371_5 ),
+	.F(\fifo_inst/n371_4 )
+);
+defparam \fifo_inst/n371_s1 .INIT=8'h80;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT4 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_5 ),
+	.I1(\fifo_inst/n371_5 ),
+	.I2(\fifo_inst/wfull_val_4 ),
+	.I3(\fifo_inst/wfull_val1_16 ),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=16'hFF80;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT4 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_5 ),
+	.I1(\fifo_inst/n371_5 ),
+	.I2(\fifo_inst/wfull_val_4 ),
+	.I3(\fifo_inst/Full_11 ),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=16'hFF80;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT4 \fifo_inst/rbin_num_next_1_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s5 .INIT=16'hBF40;
+LUT2 \fifo_inst/rbin_num_next_2_s5  (
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/rbin_num_next [2])
+);
+defparam \fifo_inst/rbin_num_next_2_s5 .INIT=4'h6;
+LUT3 \fifo_inst/rbin_num_next_3_s5  (
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/rbin_num [3]),
+	.F(\fifo_inst/rbin_num_next [3])
+);
+defparam \fifo_inst/rbin_num_next_3_s5 .INIT=8'h78;
+LUT4 \fifo_inst/rbin_num_next_4_s2  (
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/rbin_num [3]),
+	.I3(\fifo_inst/rbin_num [4]),
+	.F(\fifo_inst/rbin_num_next [4])
+);
+defparam \fifo_inst/rbin_num_next_4_s2 .INIT=16'h7F80;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/n23_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_2_s3  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_2_4 ),
+	.I2(\fifo_inst/Equal.wbin [2]),
+	.F(\fifo_inst/Equal.wbinnext [2])
+);
+defparam \fifo_inst/Equal.wbinnext_2_s3 .INIT=8'hB4;
+LUT3 \fifo_inst/Equal.wbinnext_3_s3  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_3_4 ),
+	.I2(\fifo_inst/Equal.wbin [3]),
+	.F(\fifo_inst/Equal.wbinnext [3])
+);
+defparam \fifo_inst/Equal.wbinnext_3_s3 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.wbinnext_4_s2  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_3_4 ),
+	.I2(\fifo_inst/Equal.wbin [3]),
+	.I3(\fifo_inst/wptr [4]),
+	.F(\fifo_inst/Equal.wbinnext [4])
+);
+defparam \fifo_inst/Equal.wbinnext_4_s2 .INIT=16'hBF40;
+LUT4 \fifo_inst/Equal.rgraynext_1_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext_1_4 )
+);
+defparam \fifo_inst/Equal.rgraynext_1_s1 .INIT=16'h4000;
+LUT2 \fifo_inst/Equal.wgraynext_1_s1  (
+	.I0(WrEn),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wgraynext_1_4 )
+);
+defparam \fifo_inst/Equal.wgraynext_1_s1 .INIT=4'h8;
+LUT3 \fifo_inst/Equal.wgraynext_2_s1  (
+	.I0(WrEn),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wgraynext_2_4 )
+);
+defparam \fifo_inst/Equal.wgraynext_2_s1 .INIT=8'h80;
+LUT4 \fifo_inst/Equal.wgraynext_3_s1  (
+	.I0(WrEn),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/Equal.wbin [2]),
+	.F(\fifo_inst/Equal.wgraynext_3_4 )
+);
+defparam \fifo_inst/Equal.wgraynext_3_s1 .INIT=16'h8000;
+LUT4 \fifo_inst/wfull_val_s1  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rptr [1]),
+	.F(\fifo_inst/wfull_val_4 )
+);
+defparam \fifo_inst/wfull_val_s1 .INIT=16'h9009;
+LUT4 \fifo_inst/wfull_val_s2  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rptr [2]),
+	.I2(\fifo_inst/wptr [3]),
+	.I3(\fifo_inst/rptr [3]),
+	.F(\fifo_inst/wfull_val_5 )
+);
+defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
+LUT3 \fifo_inst/n371_s2  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wptr [4]),
+	.I2(\fifo_inst/rbin_num [4]),
+	.F(\fifo_inst/n371_5 )
+);
+defparam \fifo_inst/n371_s2 .INIT=8'h14;
+LUT2 \fifo_inst/wfull_val1_s11  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1_16 )
+);
+defparam \fifo_inst/wfull_val1_s11 .INIT=4'h4;
+LUT2 \fifo_inst/Full_s9  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/Full_1 ),
+	.F(\fifo_inst/Full_11 )
+);
+defparam \fifo_inst/Full_s9 .INIT=4'h4;
+LUT4 \fifo_inst/Equal.wbinnext_1_s4  (
+	.I0(Full),
+	.I1(WrEn),
+	.I2(\fifo_inst/Equal.wbin [0]),
+	.I3(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s4 .INIT=16'hBF40;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num_next [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h4BB4;
+LUT3 \fifo_inst/rempty_val_s2  (
+	.I0(\fifo_inst/rbin_num_next [4]),
+	.I1(\fifo_inst/Equal.rq2_wptr [4]),
+	.I2(\fifo_inst/n133_3 ),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_4_s0  (
+	.D(\fifo_inst/rbin_num_next [4]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [4])
+);
+defparam \fifo_inst/rbin_num_4_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_3_s0  (
+	.D(\fifo_inst/rbin_num_next [3]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [3])
+);
+defparam \fifo_inst/rbin_num_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_2_s0  (
+	.D(\fifo_inst/rbin_num_next [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [2])
+);
+defparam \fifo_inst/rbin_num_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_4_s0  (
+	.D(\fifo_inst/wptr [4]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [4])
+);
+defparam \fifo_inst/Equal.rq1_wptr_4_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_3_s0  (
+	.D(\fifo_inst/wptr [3]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [3])
+);
+defparam \fifo_inst/Equal.rq1_wptr_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_2_s0  (
+	.D(\fifo_inst/wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [2])
+);
+defparam \fifo_inst/Equal.rq1_wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_4_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [4]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [4])
+);
+defparam \fifo_inst/Equal.rq2_wptr_4_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_3_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [3]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [3])
+);
+defparam \fifo_inst/Equal.rq2_wptr_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_2_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [2])
+);
+defparam \fifo_inst/Equal.rq2_wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_3_s0  (
+	.D(\fifo_inst/Equal.rgraynext [3]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [3])
+);
+defparam \fifo_inst/rptr_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_2_s0  (
+	.D(\fifo_inst/Equal.rgraynext [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [2])
+);
+defparam \fifo_inst/rptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_1_s0  (
+	.D(\fifo_inst/Equal.rgraynext [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [1])
+);
+defparam \fifo_inst/rptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_4_s0  (
+	.D(\fifo_inst/Equal.wbinnext [4]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [4])
+);
+defparam \fifo_inst/wptr_4_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_3_s0  (
+	.D(\fifo_inst/Equal.wgraynext [3]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [3])
+);
+defparam \fifo_inst/wptr_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_2_s0  (
+	.D(\fifo_inst/Equal.wgraynext [2]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [2])
+);
+defparam \fifo_inst/wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wgraynext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_3_s0  (
+	.D(\fifo_inst/Equal.wbinnext [3]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [3])
+);
+defparam \fifo_inst/Equal.wbin_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_2_s0  (
+	.D(\fifo_inst/Equal.wbinnext [2]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [2])
+);
+defparam \fifo_inst/Equal.wbin_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [1])
+);
+defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/reset_r [1]),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n371_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n371_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n23_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n29_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, Data[23:0]}),
+	.ADA({GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [3:0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [3:0], GND, GND, GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:24], Q[23:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+ALU \fifo_inst/n130_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(GND),
+	.CIN(GND),
+	.COUT(\fifo_inst/n130_3 ),
+	.SUM(\fifo_inst/n130_1_SUM )
+);
+defparam \fifo_inst/n130_s0 .ALU_MODE=3;
+ALU \fifo_inst/n131_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [1]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I3(GND),
+	.CIN(\fifo_inst/n130_3 ),
+	.COUT(\fifo_inst/n131_3 ),
+	.SUM(\fifo_inst/n131_1_SUM )
+);
+defparam \fifo_inst/n131_s0 .ALU_MODE=3;
+ALU \fifo_inst/n132_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [2]),
+	.I1(\fifo_inst/Equal.rq2_wptr [2]),
+	.I3(GND),
+	.CIN(\fifo_inst/n131_3 ),
+	.COUT(\fifo_inst/n132_3 ),
+	.SUM(\fifo_inst/n132_1_SUM )
+);
+defparam \fifo_inst/n132_s0 .ALU_MODE=3;
+ALU \fifo_inst/n133_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [3]),
+	.I1(\fifo_inst/Equal.rq2_wptr [3]),
+	.I3(GND),
+	.CIN(\fifo_inst/n132_3 ),
+	.COUT(\fifo_inst/n133_3 ),
+	.SUM(\fifo_inst/n133_1_SUM )
+);
+defparam \fifo_inst/n133_s0 .ALU_MODE=3;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/WrapFifoChain/FifoLMX/FifoLMX_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Thu Apr 25 16:07:21 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoLMX your_instance_name(
+		.Data(Data_i), //input [23:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [23:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoLMX/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoLMX.vg"/>
+        <Option type="output_template" value="FifoLMX_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoLMX'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoLMX"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX.vg

@@ -0,0 +1,304 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Thu Apr 25 16:07:21 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
+CQcsRTWNeKG9A5gO3GdSoNvW9zYr3PmooBz3vJJYrHFkazaqmvxtJGKC4UGygBk8vXE1NIKCzrix
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+Eeo9r6zKZBCzzoX/vEjCCVRH/vbTUoQQ9buY6g==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=13040)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+iquJKrJAOuQAmJm6Dbw/7b7Bf5o03PviM2gY4OBRgfCcMxEADJT1Tcslq6E=
+`pragma protect end_protected
+module FifoLMX (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [23:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [23:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoLMX  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[23:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[23:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoLMX */

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoLMX (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">37</td>
+<td align = "center">4</td>
+<td align = "center">38</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoLMX" Register="37" Alu="4" Lut="38" Bsram="1" T_Register="37(37)" T_Alu="4(4)" T_Lut="38(38)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Thu Apr 25 16:07:21 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoLMX your_instance_name(
+		.Data(Data_i), //input [23:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [23:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,5 @@
+`define module_name FifoLMX
+`define EBR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 16;
+parameter ASIZE = 4;
+parameter WDSIZE = 24;
+parameter RDEPTH = 16;
+parameter RASIZE = 4;
+parameter RDSIZE = 24;

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/WrapFifoChain/FifoMax2870/FifoMax2870.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoMax2870
+module=FifoMax2870
+target_device=gw1n9-014
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=true
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=32
+ReadDepth=4
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=false
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=32
+WriteDepth=4

src/src/WrapFifoChain/FifoMax2870/FifoMax2870.v

@@ -0,0 +1,222 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Thu Apr 25 16:07:36 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=8352)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+bPVpgkyuhCzoUp+3N37RJ/RWjqbeq6RDzOkIPZox
+`pragma protect end_protected
+module FifoMax2870 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [31:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [31:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoMax2870  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[31:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[31:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoMax2870 */

src/src/WrapFifoChain/FifoMax2870/FifoMax2870.vo

@@ -0,0 +1,457 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.02
+//Created Time: Thu Apr 25 16:07:36 2024
+
+`timescale 100 ps/100 ps
+module FifoMax2870(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [31:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [31:0] Q;
+output Empty;
+output Full;
+wire [31:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [31:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n21_5 ;
+wire \fifo_inst/n27_4 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/wfull_val_4 ;
+wire \fifo_inst/wfull_val_5 ;
+wire \fifo_inst/n335_6 ;
+wire \fifo_inst/wfull_val ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n158_1_SUM ;
+wire \fifo_inst/n158_3 ;
+wire \fifo_inst/n159_1_SUM ;
+wire \fifo_inst/n159_3 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [1:0] \fifo_inst/Equal.rgraynext ;
+wire [1:0] \fifo_inst/Equal.wgraynext ;
+wire [2:0] \fifo_inst/rbin_num_next ;
+wire [2:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [2:0] \fifo_inst/rbin_num ;
+wire [2:0] \fifo_inst/Equal.rq1_wptr ;
+wire [2:0] \fifo_inst/Equal.rq2_wptr ;
+wire [1:0] \fifo_inst/rptr ;
+wire [2:0] \fifo_inst/wptr ;
+wire [1:0] \fifo_inst/Equal.wbin ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n21_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n21_5 )
+);
+defparam \fifo_inst/n21_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n27_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n27_4 )
+);
+defparam \fifo_inst/n27_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT4 \fifo_inst/Equal.rgraynext_1_s0  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/Equal.rgraynext [1])
+);
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h0BF4;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT4 \fifo_inst/Equal.wgraynext_1_s0  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/wptr [2]),
+	.F(\fifo_inst/Equal.wgraynext [1])
+);
+defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h07F8;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT4 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_4 ),
+	.I1(\fifo_inst/wfull_val_5 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.I3(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=16'h00F8;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT4 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_4 ),
+	.I1(\fifo_inst/wfull_val_5 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=16'h00F8;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s5  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s5 .INIT=8'hB4;
+LUT4 \fifo_inst/rbin_num_next_2_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/rbin_num_next [2])
+);
+defparam \fifo_inst/rbin_num_next_2_s2 .INIT=16'hBF40;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s3  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s3 .INIT=8'h78;
+LUT4 \fifo_inst/Equal.wbinnext_2_s2  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/wptr [2]),
+	.F(\fifo_inst/Equal.wbinnext [2])
+);
+defparam \fifo_inst/Equal.wbinnext_2_s2 .INIT=16'h7F80;
+LUT2 \fifo_inst/wfull_val_s1  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/wfull_val_4 )
+);
+defparam \fifo_inst/wfull_val_s1 .INIT=4'h6;
+LUT4 \fifo_inst/wfull_val_s2  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rptr [1]),
+	.F(\fifo_inst/wfull_val_5 )
+);
+defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
+LUT4 \fifo_inst/n335_s2  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/reset_w [1]),
+	.I3(\fifo_inst/wfull_val_5 ),
+	.F(\fifo_inst/n335_6 )
+);
+defparam \fifo_inst/n335_s2 .INIT=16'h0600;
+LUT3 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/wfull_val_5 ),
+	.F(\fifo_inst/wfull_val )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=8'h60;
+LUT3 \fifo_inst/rempty_val_s2  (
+	.I0(\fifo_inst/rbin_num_next [2]),
+	.I1(\fifo_inst/Equal.rq2_wptr [2]),
+	.I2(\fifo_inst/n159_3 ),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_2_s0  (
+	.D(\fifo_inst/rbin_num_next [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [2])
+);
+defparam \fifo_inst/rbin_num_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_2_s0  (
+	.D(\fifo_inst/wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [2])
+);
+defparam \fifo_inst/Equal.rq1_wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_2_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [2])
+);
+defparam \fifo_inst/Equal.rq2_wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_1_s0  (
+	.D(\fifo_inst/Equal.rgraynext [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [1])
+);
+defparam \fifo_inst/rptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_2_s0  (
+	.D(\fifo_inst/Equal.wbinnext [2]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [2])
+);
+defparam \fifo_inst/wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wgraynext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [1])
+);
+defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/reset_r [1]),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n335_6 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n335_6 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n21_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n27_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({Data[31:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [1:0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [1:0], GND, GND, GND, GND, GND}),
+	.DO({Q[31:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+ALU \fifo_inst/n158_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(GND),
+	.CIN(GND),
+	.COUT(\fifo_inst/n158_3 ),
+	.SUM(\fifo_inst/n158_1_SUM )
+);
+defparam \fifo_inst/n158_s0 .ALU_MODE=3;
+ALU \fifo_inst/n159_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [1]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I3(GND),
+	.CIN(\fifo_inst/n158_3 ),
+	.COUT(\fifo_inst/n159_3 ),
+	.SUM(\fifo_inst/n159_1_SUM )
+);
+defparam \fifo_inst/n159_s0 .ALU_MODE=3;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/WrapFifoChain/FifoMax2870/FifoMax2870_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Thu Apr 25 16:07:36 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoMax2870 your_instance_name(
+		.Data(Data_i), //input [31:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [31:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoMax2870/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoMax2870.vg"/>
+        <Option type="output_template" value="FifoMax2870_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoMax2870'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoMax2870"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870.vg

@@ -0,0 +1,222 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Thu Apr 25 16:07:36 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
+Da6ePPXJ0x1Zkr3+qduAM8J+kvtpawq4mD4KNKBETeC4EH7Szs6BzQt56oavp90RuKDAboLkt4Jg
++G92rwctBdMEwq+eB6c7QPHl/H1uRLQVqlR4yx0r3BOVYQPjoymqLzmZv8veGRBC1kdMpZB80yUK
+zmz+xkaf5+Uj2LoGUbWb2pOECph91GIFDeF+RqGJtZTKyt08qFT8oijjiMTL0Xb+qn22EE7E1RFY
+OllWGiYHO4QEEG6qgweiS5shJRiL6+3Pxmw7CJNrKZ/zyFyC0a6pFdp6mTM2DN5SkKBIq/YzyLXr
+XKL3+73PMXlMajN6EcsM4S1BTp7fXxaHLIWB1w==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=8352)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+qVmXdmdwKDtJmtYhyMOxNRK8erlu4r6zEeDvEpx2IBIOGnT0ApDjYviZlP99fgMh3yJfI/had4rT
+mC1Z685Ml2+hMNFdxFjxEm8BVqAUNgfuaDj7Li5jZnGpqdGjUKfMwV4do/jufEf8Veu3WdAF65og
+swhI56mnllNG9wN34pjZ4RslCEtlkr4Gxz+LdX+cV/WpGQJnFBIabFIQZOawAZLpev8obH3dGkEh
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+bPVpgkyuhCzoUp+3N37RJ/RWjqbeq6RDzOkIPZox
+`pragma protect end_protected
+module FifoMax2870 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [31:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [31:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoMax2870  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[31:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[31:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoMax2870 */

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoMax2870 (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">25</td>
+<td align = "center">2</td>
+<td align = "center">23</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoMax2870" Register="25" Alu="2" Lut="23" Bsram="1" T_Register="25(25)" T_Alu="2(2)" T_Lut="23(23)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Thu Apr 25 16:07:36 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoMax2870 your_instance_name(
+		.Data(Data_i), //input [31:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [31:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,5 @@
+`define module_name FifoMax2870
+`define EBR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 4;
+parameter ASIZE = 2;
+parameter WDSIZE = 32;
+parameter RDEPTH = 4;
+parameter RASIZE = 2;
+parameter RDSIZE = 32;

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoShiftReg
+module=FifoShiftReg
+target_device=gw1n9-014
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=true
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=8
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=false
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=8
+WriteDepth=2

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg.v

@@ -0,0 +1,188 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Thu Apr 25 16:08:18 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+BrWHDjSsnheYikR4eooDlA==
+`pragma protect end_protected
+module FifoShiftReg (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [7:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [7:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoShiftReg  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[7:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[7:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoShiftReg */

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg.vo

@@ -0,0 +1,353 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.02
+//Created Time: Thu Apr 25 16:08:18 2024
+
+`timescale 100 ps/100 ps
+module FifoShiftReg(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [7:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [7:0] Q;
+output Empty;
+output Full;
+wire [7:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [7:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n177_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+wire [31:8] \fifo_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n177_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n177_4 )
+);
+defparam \fifo_inst/n177_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
+);
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/reset_r [1]),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n177_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n177_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[7:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:8], Q[7:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=8;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=8;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Thu Apr 25 16:08:18 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoShiftReg your_instance_name(
+		.Data(Data_i), //input [7:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [7:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoShiftReg/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoShiftReg.vg"/>
+        <Option type="output_template" value="FifoShiftReg_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoShiftReg'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoShiftReg"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg_syn.rpt.html" completed
+GowinSynthesis finish

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg.vg

@@ -0,0 +1,188 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Thu Apr 25 16:08:18 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+8DM4h8FNMqFHubE/tetwFYOqKFxGclYw1Xqrhw==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+BrWHDjSsnheYikR4eooDlA==
+`pragma protect end_protected
+module FifoShiftReg (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [7:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [7:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoShiftReg  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[7:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[7:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoShiftReg */

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoShiftReg (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">19</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoShiftReg" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Thu Apr 25 16:08:18 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoShiftReg your_instance_name(
+		.Data(Data_i), //input [7:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [7:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,5 @@
+`define module_name FifoShiftReg
+`define EBR_BASED
+`define FWFT
+`define En_Reset
+`define Reset_Synchronization

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 8;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 8;

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/WrapFifoChain/LmxWrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     LmxWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the LMX Fifo, LMX Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module LmxWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 24,
+    parameter DATA_WIDTH = 24
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromLmxFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromLmxFifo;
+wire readEnLmx;
+wire writeEnLmx;
+wire valRdDataLMX;
+wire busySpiMLmx;
+wire lmxFifoFull;
+wire lmxFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(IN_WIDTH),
+	.WR_NUM			(WR_NUM),
+	.OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrlLmx
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMLmx),
+	.FifoFull_i		(lmxFifoFull),
+	.FifoEmpty_i	(lmxFifoEmpty),
+	.Data_o			(dataFromLmxFifoCtrl),
+	.ReadEn_o		(readEnLmx),
+	.WriteEn_o		(writeEnLmx),
+	.ValRdData_o	(valRdDataLMX)
+);
+
+FifoLMX FifoLMX_inst (
+	.Data	(dataFromLmxFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnLmx),
+	.RdEn	(readEnLmx),
+	.Full	(lmxFifoFull),
+	.Empty	(lmxFifoEmpty),
+	.Q		(dataFromLmxFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(DATA_WIDTH)
+)SpiMLmx(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataLMX),
+	.SpiData_i	(dataFromLmxFifo),
+	.Busy_o	    (busySpiMLmx),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/WrapFifoChain/Max2870Wrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     Max2870Wrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module Max2870Wrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 2,
+    parameter OUT_WIDTH = 32,
+    parameter DATA_WIDTH = 32
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromMaxFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromMaxFifo;
+wire readEnMax;
+wire writeEnMax;
+wire valRdDataMAX;
+wire busySpiMMax;
+wire maxFifoFull;
+wire maxFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(IN_WIDTH),
+	.WR_NUM			(WR_NUM),
+	.OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrlMax
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMMax),
+	.FifoFull_i		(maxFifoFull),
+	.FifoEmpty_i	(maxFifoEmpty),
+	.Data_o			(dataFromMaxFifoCtrl),
+	.ReadEn_o		(readEnMax),
+	.WriteEn_o		(writeEnMax),
+	.ValRdData_o	(valRdDataMAX)
+);
+
+FifoMax2870 FifoMax2870_inst (
+	.Data	(dataFromMaxFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnMax),
+	.RdEn	(readEnMax),
+	.Full	(maxFifoFull),
+	.Empty	(maxFifoEmpty),
+	.Q		(dataFromMaxFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(DATA_WIDTH)
+)SpiMMax(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataMAX),
+	.SpiData_i	(dataFromMaxFifo),
+	.Busy_o	    (busySpiMMax),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/WrapFifoChain/PotWrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     DDSWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module PotWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 16,
+    parameter DATA_WIDTH = 16
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromPotFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromPotFifo;
+wire readEnPot;
+wire writeEnPot;
+wire valRdDataPOT;
+wire busySpiMPot;
+wire potFifoFull;
+wire potFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(IN_WIDTH),
+	.WR_NUM			(WR_NUM),
+	.OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrlPot
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMPot),
+	.FifoFull_i		(potFifoFull),
+	.FifoEmpty_i	(potFifoEmpty),
+	.Data_o			(dataFromPotFifoCtrl),
+	.ReadEn_o		(readEnPot),
+	.WriteEn_o		(writeEnPot),
+	.ValRdData_o	(valRdDataPOT)
+);
+
+Fifo16x3 FifoPot_inst (
+	.Data	(dataFromPotFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnPot),
+	.RdEn	(readEnPot),
+	.Full	(potFifoFull),
+	.Empty	(potFifoEmpty),
+	.Q		(dataFromPotFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(DATA_WIDTH)
+)SpiMPot(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataPOT),
+	.SpiData_i	(dataFromPotFifo),
+	.Busy_o	    (busySpiMPot),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/WrapFifoChain/ShifRegWrapper.v

@@ -0,0 +1,94 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     ShiftRegWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module ShiftRegWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 8,
+    parameter DATA_WIDTH = 8
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromShRegFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromShRegFifo;
+wire readEnShReg;
+wire writeEnShReg;
+wire valRdDataShReg;
+wire busySpiMShReg;
+wire shRegFifoFull;
+wire shRegFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(IN_WIDTH),
+	.WR_NUM			(WR_NUM),
+	.OUT_WIDTH		(OUT_WIDTH)
+) FifoCtrlShReg
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMShReg),
+	.FifoFull_i		(shRegFifoFull),
+	.FifoEmpty_i	(shRegFifoEmpty),
+	.Data_o			(dataFromShRegFifoCtrl),
+	.ReadEn_o		(readEnShReg),
+	.WriteEn_o		(writeEnShReg),
+	.ValRdData_o	(valRdDataShReg)
+);
+
+FifoShiftReg FifoShReg_inst (
+	.Data	(dataFromShRegFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnShReg),
+	.RdEn	(readEnShReg),
+	.Full	(shRegFifoFull),
+	.Empty	(shRegFifoEmpty),
+	.Q		(dataFromShRegFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(DATA_WIDTH)
+)SpiMShReg(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataShReg),
+	.SpiData_i	(dataFromShRegFifo),
+	.Busy_o	    (busySpiMShReg),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule