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@@ -59,7 +59,19 @@ module InterfaceArbiter
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reg [QSPIWORDWIDTH-1:0] captReg1;
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reg [QSPIWORDWIDTH-1:0] captReg2;
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reg [QSPIWORDWIDTH-1:0] captReg3;
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-
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+
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+ reg [OUTWORDWIDTH-1:0] captRegSspiR;
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+ reg [OUTWORDWIDTH-1:0] captRegSspiRR;
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+
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+ reg [QSPIWORDWIDTH-1:0] captReg0R;
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+ reg [QSPIWORDWIDTH-1:0] captReg0RR;
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+ reg [QSPIWORDWIDTH-1:0] captReg1R;
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+ reg [QSPIWORDWIDTH-1:0] captReg1RR;
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+ reg [QSPIWORDWIDTH-1:0] captReg2R;
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+ reg [QSPIWORDWIDTH-1:0] captReg2RR;
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+ reg [QSPIWORDWIDTH-1:0] captReg3R;
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+ reg [QSPIWORDWIDTH-1:0] captReg3RR;
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+
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reg ssReg;
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reg ssRegR;
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reg ssRegRR;
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@@ -167,7 +179,41 @@ module InterfaceArbiter
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end
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end
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end
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-
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+
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+ always @(posedge Clk_i) begin
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+ if (Rst_i) begin
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+ captRegSspiR <= 0;
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+ captRegSspiRR <= 0;
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+ end
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+ else begin
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+ captRegSspiR <= captRegSspi;
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+ captRegSspiRR <= captRegSspiR;
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+ end
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+ end
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+
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+ always @(posedge Clk_i) begin
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+ if (Rst_i) begin
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+ captReg0R <= 0;
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+ captReg0RR <= 0;
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+ captReg1R <= 0;
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+ captReg1RR <= 0;
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+ captReg2R <= 0;
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+ captReg2RR <= 0;
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+ captReg3R <= 0;
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+ captReg3RR <= 0;
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+ end
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+ else begin
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+ captReg0R <= captReg0;
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+ captReg0RR <= captReg0R;
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+ captReg1R <= captReg1;
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+ captReg1RR <= captReg1R;
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+ captReg2R <= captReg2;
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+ captReg2RR <= captReg2R;
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+ captReg3R <= captReg3;
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+ captReg3RR <= captReg3R;
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+ end
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+ end
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+
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always @(*) begin
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if (currState == IDLE && (Data_o[11]& Data_o[8])) begin
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TestTrig_o = 1'b1;
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@@ -263,8 +309,8 @@ module InterfaceArbiter
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always @(posedge Clk_i) begin
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if (!Rst_i) begin
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if (plsToggleSyncSignal) begin
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- dataRegSSpi <= captRegSspi;
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- dataRegQSpi <= {captReg0,captReg1,captReg2,captReg3};
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+ dataRegSSpi <= captRegSspiRR;
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+ dataRegQSpi <= {captReg0R,captReg1R,captReg2R,captReg3R};
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dataValReg <= 1'b1;
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end else begin
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dataValReg <= 1'b0;
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