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@@ -61,7 +61,6 @@ reg [22:0] dataSpiReg;
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//==========================================
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//==========================================
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wire lmxOr;
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wire lmxOr;
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wire ddsOr;
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wire ddsOr;
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-wire loadOrderOr;
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wire potOr;
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wire potOr;
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wire dacOr;
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wire dacOr;
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wire attOr;
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wire attOr;
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@@ -102,7 +101,6 @@ assign attOr = dataSpiReg[1];
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assign shRegOr = |dataSpiReg[7:6];
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assign shRegOr = |dataSpiReg[7:6];
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assign maxOr = |dataSpiReg[10:9];
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assign maxOr = |dataSpiReg[10:9];
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assign gpioOr = |dataSpiReg[17:16];
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assign gpioOr = |dataSpiReg[17:16];
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-assign loadOrderOr = dataSpiReg[22];
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assign selector = {lmxOr, gpioOr, ddsOr, maxOr, shRegOr, potOr, dacOr, attOr};
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assign selector = {lmxOr, gpioOr, ddsOr, maxOr, shRegOr, potOr, dacOr, attOr};
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@@ -143,6 +141,7 @@ always @(posedge Clk_i) begin
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LmxWordNum_o <= DataFromSpi_i[21:18];
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LmxWordNum_o <= DataFromSpi_i[21:18];
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DdsWordNum_o <= DataFromSpi_i[14:12];
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DdsWordNum_o <= DataFromSpi_i[14:12];
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ValWordNum_o <= 1'b1;
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ValWordNum_o <= 1'b1;
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+ ValLoadOrder_o <= 1'b1;
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end
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end
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else begin
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else begin
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casez(selector)
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casez(selector)
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@@ -150,7 +149,7 @@ always @(posedge Clk_i) begin
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dataSpiReg <= dataSpiReg - DECREMENT_LMX;
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dataSpiReg <= dataSpiReg - DECREMENT_LMX;
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ValLmxDataToFifo_o <= 1'b1;
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ValLmxDataToFifo_o <= 1'b1;
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end
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end
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- 9'b001??????: begin //GPIO
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+ 8'b01??????: begin //GPIO
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dataSpiReg <= dataSpiReg - DECREMENT_GPIO;
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dataSpiReg <= dataSpiReg - DECREMENT_GPIO;
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ValGpioDataToFifo_o <= 1'b1;
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ValGpioDataToFifo_o <= 1'b1;
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end
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end
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@@ -158,23 +157,23 @@ always @(posedge Clk_i) begin
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dataSpiReg <= dataSpiReg - DECREMENT_DDS;
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dataSpiReg <= dataSpiReg - DECREMENT_DDS;
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ValDdsDataToFifo_o <= 1'b1;
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ValDdsDataToFifo_o <= 1'b1;
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end
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end
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- 9'b00001????: begin //MAX
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+ 8'b0001????: begin //MAX
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dataSpiReg <= dataSpiReg - DECREMENT_MAX;
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dataSpiReg <= dataSpiReg - DECREMENT_MAX;
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ValMaxDataToFifo_o <= 1'b1;
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ValMaxDataToFifo_o <= 1'b1;
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end
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end
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- 9'b000001???: begin //ShReg
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+ 8'b00001???: begin //ShReg
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dataSpiReg <= dataSpiReg - DECREMENT_SH_REG;
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dataSpiReg <= dataSpiReg - DECREMENT_SH_REG;
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ValShRegDataToFifo_o <= 1'b1;
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ValShRegDataToFifo_o <= 1'b1;
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end
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end
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- 9'b0000001??: begin //Pot
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+ 8'b000001??: begin //Pot
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dataSpiReg <= dataSpiReg - DECREMENT_POT;
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dataSpiReg <= dataSpiReg - DECREMENT_POT;
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ValPotDataToFifo_o <= 1'b1;
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ValPotDataToFifo_o <= 1'b1;
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end
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end
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- 9'b00000001?: begin //DAC
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+ 8'b0000001?: begin //DAC
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dataSpiReg <= dataSpiReg - DECREMENT_DAC;
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dataSpiReg <= dataSpiReg - DECREMENT_DAC;
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ValDacDataToFifo_o <= 1'b1;
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ValDacDataToFifo_o <= 1'b1;
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end
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end
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- 9'b000000001: begin //ATT
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+ 8'b00000001: begin //ATT
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dataSpiReg <= dataSpiReg - DECREMENT_ATT;
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dataSpiReg <= dataSpiReg - DECREMENT_ATT;
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ValAttDataToFifo_o <= 1'b1;
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ValAttDataToFifo_o <= 1'b1;
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end
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end
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@@ -187,7 +186,6 @@ always @(posedge Clk_i) begin
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ValShRegDataToFifo_o <= 1'b0;
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ValShRegDataToFifo_o <= 1'b0;
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ValMaxDataToFifo_o <= 1'b0;
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ValMaxDataToFifo_o <= 1'b0;
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ValGpioDataToFifo_o <= 1'b0;
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ValGpioDataToFifo_o <= 1'b0;
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- ValLoadOrder_o <= 1'b0;
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end
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end
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endcase
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endcase
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//=========================DELETE AFTER HARDWARE TEST===========================
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//=========================DELETE AFTER HARDWARE TEST===========================
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@@ -247,6 +245,7 @@ always @(posedge Clk_i) begin
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ValGpioDataToFifo_o <= 1'b0;
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ValGpioDataToFifo_o <= 1'b0;
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ValLoadOrder_o <= 1'b0;
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ValLoadOrder_o <= 1'b0;
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ValWordNum_o <= 1'b0;
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ValWordNum_o <= 1'b0;
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+ ValLoadOrder_o <= 1'b0;
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end
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end
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end
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end
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