Переключил режим работы FIFO из "First word fallthrough" в "Standard".

src/constr/SbTmsg.cst

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
-//Created Time: Wed 06 25 12:33:50 2025
+//Created Time: Wed 06 25 16:51:40 2025
 
 IO_LOC "FpgaLed_o" L16;
 IO_PORT "FpgaLed_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;

src/constr/SbTmsg.sdc

@@ -2,7 +2,7 @@
 //All rights reserved.
 //File Title: Timing Constraints file
 //Tool Version: V1.9.11.02 (64-bit) 
-//Created Time: 2025-06-25 11:36:44
+//Created Time: 2025-06-26 10:43:21
 create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
 create_clock -name Sck_i -period 16.667 -waveform {0 8.334} [get_ports {Sck_i}]
 create_generated_clock -name clk50 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 12 -multiply_by 25 [get_nets {clk50}]
@@ -12,8 +12,10 @@ create_generated_clock -name clk26dot25 -source [get_ports {Clk_i}] -master_cloc
 create_generated_clock -name clk20 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 30 -multiply_by 25 [get_nets {clk20}]
 create_generated_clock -name clk100 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 6 -multiply_by 25 [get_nets {ClkGen/clk100Mhz}]
 create_generated_clock -name clk60 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 14 -multiply_by 35 [get_nets {clk60}]
+create_generated_clock -name spiClkDds -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 12 -multiply_by 25 [get_nets {ClkAd9912Fpga_o_d}]
+set_clock_groups -asynchronous -group [get_clocks {Clk_i Sck_i}]
 set_false_path -from [get_regs {InitRst/signal_o_s1}] 
 report_timing -setup -max_paths 300 -max_common_paths 1
-report_timing -setup -from_clock [get_clocks {clk60}] -to_clock [get_clocks {clk60}] -max_paths 50
-report_timing -setup -from_clock [get_clocks {clk50}] -to_clock [get_clocks {clk50}] -max_paths 50
-report_timing -setup -from_clock [get_clocks {clk100}] -to_clock [get_clocks {clk100}] -max_paths 50
+report_timing -setup -from_clock [get_clocks {clk60}] -to_clock [get_clocks {clk60}] -max_paths 50 -max_common_paths 1
+report_timing -setup -from_clock [get_clocks {clk50}] -to_clock [get_clocks {clk50}] -max_paths 50 -max_common_paths 1
+report_timing -setup -from_clock [get_clocks {clk100}] -to_clock [get_clocks {clk100}] -max_paths 50 -max_common_paths 1

src/src/FifoCtrl/FifoCtrl.v

@@ -48,6 +48,7 @@ localparam DATA_WIDTH = WR_NUM*IN_WIDTH;
 //================================================================================
 reg [DATA_WIDTH-1:0] dataReg;
 reg [1:0]  wrCnt;
+reg valRdData;
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
@@ -182,7 +183,7 @@ always @(posedge RdClk_i) begin
         if (!FifoEmpty_i && !BusySpiM_i) begin 
             ReadEn_o <= 1'b1;
         end
-        else begin 
+        if (ReadEn_o) begin
             ReadEn_o <= 1'b0;
         end
     end
@@ -190,16 +191,20 @@ end
 
 always @(posedge RdClk_i) begin 
     if (Rst_i) begin 
-        ValRdData_o <= 1'b0;
+        valRdData <= 1'b0;
     end
     else begin
         if (!FifoEmpty_i && !BusySpiM_i) begin 
-            ValRdData_o <= 1'b1;
+            valRdData <= 1'b1;
         end
-        else begin 
-            ValRdData_o <= 1'b0;
+        if (valRdData) begin 
+            valRdData <= 1'b0;
         end
     end
 end
 
+always @(posedge RdClk_i) begin 
+    ValRdData_o <= valRdData;
+end
+
 endmodule

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -103,6 +103,9 @@ module InterfaceArbiter
 	reg plsToggleSyncC;
 	reg plsToggleSyncSignalR;
 
+	reg ss_sync1, ss_sync2, ss_sync3;
+	reg ss_posedge_detect;
+
 //================================================================================
 //  ASSIGNMENTS
 	assign ssPos = ssRegR & !ssRegRR;

src/src/Top/ExtSpiMEmul.v

@@ -166,9 +166,6 @@ module ExtSpiMEmul (
         end
     end
     
-    
-    
-    
     always @(*) begin
         if (SelSt_i) begin 
             if (PulsePol_i) begin 

src/src/Top/TopSbTmsg.v

@@ -211,7 +211,12 @@ localparam LED_TICK_RATE = 48000000;//0.5Hz 24MHz
 	/* LedReg */
 	reg ledReg;
 	/* Result of test */
-	wire resultOfTest;
+	reg resultOfTest;
+
+	/* Spi Slave */
+	wire valFromSpiSlave;
+	wire [79:0] dataFromSpiSlave;
+	reg currentSample;
 
 //================================================================================
 //  ASSIGNMENTS
@@ -247,7 +252,8 @@ assign AnyFlag_o = anyFlag;//Debug-only
 
 assign servInfo	= {BOARD_VER, FIRMWARE_VER};
 
-assign FpgaLed_o = resultOfTest;
+// assign FpgaLed_o = resultOfTest;
+assign FpgaLed_o = ledReg; //Blink Led
 // assign FpgaLed_o = 1'b1; //Golden-Image
 
 //================================================================================
@@ -374,6 +380,41 @@ always @(*) begin
 	end
 end
 
+SpiSlave #(
+	.WIDTH		(80)
+) SpiS_inst (
+	.Clk_i		(clk50),
+	.Rst_i		(initRst),
+	.Ss_i		(CsAd9912Fpga_o),
+	.Mosi_i		(MosiAd9912Fpga_o),
+	.Sck_i		(ClkAd9912Fpga_o),
+	.Val_o		(valFromSpiSlave),
+	.Data_o		(dataFromSpiSlave)
+);
+
+/* Spi Master Check */
+always @(posedge clk50) begin 
+	if (Rst_i) begin
+		resultOfTest <= 1'b0;
+		currentSample <= 1'b0;
+	end
+	else begin
+		if (valFromSpiSlave) begin 
+			if ((currentSample == 0) && dataFromSpiSlave == 80'hAAAAAAAAAAAAAAAAAAAA ) begin 
+				currentSample <= 1'b1;
+				resultOfTest <= 1'b0;
+			end
+			else if ((currentSample == 1) && dataFromSpiSlave == 80'h55555555555555555555 ) begin 
+				currentSample <= 1'b0;
+				resultOfTest <= 1'b0;
+			end
+			else begin 
+				resultOfTest <= 1'b1; // Ошибка, данные не совпадают
+			end  
+		end
+	end
+end
+
 ClkGen ClkGen
 (
 	.Clk24Mhz_i			(Clk_i),
@@ -514,7 +555,6 @@ DDSWrapper #(
 	.Val_i				(valDdsDataToFifo),
 	.DdsWordNumReg_o	(ddsWordNumReg),
 	.DdsSyncFpga_o		(DdsSyncFpga_o),
-	.ResultOfTest_o		(resultOfTest),
 	.Ss_o				(ddsCsSpiM),
 	.Sck_o				(ddsClkSpiM),
 	.Mosi_o				(ddsMosiSpiM)

src/src/Top/TopSbTmsgTb.sv

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns
+`timescale 1ns/1ps
 
 module TopSbTmsgTb(inout Mosi1_io);
    parameter CLK_PERIOD = 8.13; // Clock period in ns
@@ -131,7 +131,7 @@ localparam        POTWordNum = 2'd2;
 localparam        DACWordNum = 1'd1;
 localparam        ATTWordNum = 1'd1;
 localparam [1:0]  ShRegWordNum = 2'd1;
-localparam [2:0]  MaxWordNum =   3'd4;
+localparam [2:0]  MaxWordNum =   3'd2;
 localparam [1:0]  GPIOWordNum =  2'd1;
 
 localparam [23:0] Max2870Header         = {1'h1, 1'h0, 3'h0, 1'h0, 2'h0, 4'h0, 1'h0, MaxWordNum, 1'h0, 2'h0, 1'h0, 2'h0, 1'h0, 1'h0, 1'h1};
@@ -179,7 +179,7 @@ assign Mosi0_o = (modeSel) ? mosi0Q : mosi0R;
 assign Mosi1_io = (anyFlag) ? 1'bz : Mosi1_o;
 assign MisoLdLmx_i = 1'b1;
 
-assign emptyFlagTx = (trCnt > 74) ? 1'b1 : 1'b0;
+assign emptyFlagTx = (trCnt > 71) ? 1'b1 : 1'b0;
 assign QSPITotalWordNum = LMXWordNum + DDSWordNum + POTWordNum + DACWordNum + ATTWordNum + ShRegWordNum + MaxWordNum + GPIOWordNum; 
 
 assign currClk = (modeSel) ? Clk60 : Clk10;
@@ -397,7 +397,7 @@ always_comb begin
         .Lag_i(LAG_i),
         .Lead_i(LEAD_i),
         .EndianSel_i(EndianSel_i),
-        .Stop_i(6'h0),
+        .Stop_i(6'h3),
         .PulsePol_i(PulsePol_i),
         .Mosi0_o(mosi0R),
         .Sck_o(SckR),

src/src/WrapFifoChain/DDSWrapper.v

@@ -92,12 +92,6 @@ wire [9:0] storedParityBits; // Сохранённые биты чётности
 reg ssNegEdge;
 reg isLastWord;
 reg directFlagRisingEdge;
-
-reg currentSample;
-
-/* Spi Slave */
-wire valFromSpiSlave;
-wire [79:0] dataFromSpiSlave;
 //================================================================================
 //	                                ASSIGNMENTS
 //================================================================================ 
@@ -282,30 +276,6 @@ always @(posedge RdClk_i) begin
 	end
 end
 
-/* Spi Master Check */
-always @(posedge RdClk_i) begin 
-	if (RstExt_i) begin
-		ResultOfTest_o <= 1'b0;
-		currentSample <= 1'b0;
-	end
-	else begin
-		if (valFromSpiSlave) begin 
-			if ((currentSample == 0) && dataFromSpiSlave == 80'hAAAAAAAAAAAAAAAAAAAA ) begin 
-				currentSample <= 1'b1;
-				ResultOfTest_o <= 1'b0;
-			end
-			else if ((currentSample == 1) && dataFromSpiSlave == 80'h55555555555555555555 ) begin 
-				currentSample <= 1'b0;
-				ResultOfTest_o <= 1'b0;
-			end
-			else begin 
-				ResultOfTest_o <= 1'b1; // Ошибка, данные не совпадают
-			end  
-		end
-	end
-end
-
-
 FifoCtrl #(
 	.PARITY_CHECK	(1),
 	.IN_WIDTH		(IN_WIDTH),
@@ -353,16 +323,4 @@ SpiM #(
 	.Sck_o		(Sck_o)
 );
 
-SpiSlave #(
-	.WIDTH		(OUT_WIDTH)
-) SpiS_inst (
-	.Clk_i		(RdClk_i),
-	.Rst_i		(Rst_i),
-	.Ss_i		(Ss_o),
-	.Mosi_i		(Mosi_o),
-	.Sck_i		(Sck_o),
-	.Val_o		(valFromSpiSlave),
-	.Data_o		(dataFromSpiSlave)
-);
-
 endmodule

src/src/WrapFifoChain/Fifo16x3/Fifo16x3.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=true
+FirstWordFallThrough=false
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=16
 ReadDepth=2
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=false
+StandardFIFO=true
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=16

src/src/WrapFifoChain/Fifo16x3/Fifo16x3.v

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:04:59 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:09:42 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,129 +17,119 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5808)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module Fifo16x3 (
   Data,

src/src/WrapFifoChain/Fifo16x3/Fifo16x3.vo

@@ -1,8 +1,8 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
-//File Title: Post-PnR Simulation Model file
-//Tool Version: V1.9.9.02
-//Created Time: Thu Apr 25 16:04:59 2024
+//File Title: Post-PnR Verilog Simulation Model file
+//Tool Version: V1.9.11.02 (64-bit)
+//Created Time: Thu Jun 26 11:09:43 2025
 
 `timescale 100 ps/100 ps
 module Fifo16x3(
@@ -37,30 +37,30 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n20_5 ;
-wire \fifo_inst/n26_4 ;
-wire \fifo_inst/n217_4 ;
+wire \fifo_inst/n24_3 ;
+wire \fifo_inst/n167_3 ;
+wire \fifo_inst/n218_4 ;
 wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val_7 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
-wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/Equal.wbinnext_0_8 ;
+wire \fifo_inst/rbin_num_next_0_10 ;
+wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
-wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [0:0] \fifo_inst/Equal.wgraynext ;
-wire [1:0] \fifo_inst/rbin_num_next ;
 wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:1] \fifo_inst/rbin_num_next ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [1:0] \fifo_inst/rbin_num ;
-wire [1:0] \fifo_inst/Equal.rq1_wptr ;
-wire [1:0] \fifo_inst/Equal.rq2_wptr ;
 wire [0:0] \fifo_inst/rptr ;
 wire [1:0] \fifo_inst/wptr ;
 wire [0:0] \fifo_inst/Equal.wbin ;
@@ -82,41 +82,39 @@ LUT4 \fifo_inst/n20_s1  (
 	.F(\fifo_inst/n20_5 )
 );
 defparam \fifo_inst/n20_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n26_s1  (
-	.I0(RdEn),
-	.I1(Empty),
-	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n26_4 )
-);
-defparam \fifo_inst/n26_s1 .INIT=8'h0E;
-LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
-	.I0(\fifo_inst/rbin_num [0]),
-	.I1(\fifo_inst/rbin_num_next [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
+LUT2 \fifo_inst/n24_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n24_3 )
 );
-defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+defparam \fifo_inst/n24_s0 .INIT=4'h4;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n217_s1  (
+LUT2 \fifo_inst/n167_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n167_3 )
+);
+defparam \fifo_inst/n167_s0 .INIT=4'hE;
+LUT2 \fifo_inst/n218_s1  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n217_4 )
+	.F(\fifo_inst/n218_4 )
 );
-defparam \fifo_inst/n217_s1 .INIT=4'h4;
+defparam \fifo_inst/n218_s1 .INIT=4'h4;
 LUT4 \fifo_inst/rempty_val_s3  (
-	.I0(\fifo_inst/Equal.rq2_wptr [1]),
-	.I1(\fifo_inst/rempty_val_8 ),
-	.I2(\fifo_inst/Equal.rq2_wptr [0]),
-	.I3(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
 LUT4 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [0]),
 	.I1(\fifo_inst/wptr [1]),
@@ -133,8 +131,8 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 );
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT3 \fifo_inst/wfull_val1_s10  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/wfull_val1_0 ),
+	.I0(\fifo_inst/wfull_val1_0 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/wfull_val1_0 )
 );
@@ -147,47 +145,48 @@ LUT3 \fifo_inst/Full_d_s  (
 );
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT3 \fifo_inst/Full_s8  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/Full_1 ),
+	.I0(\fifo_inst/Full_1 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=8'h0E;
-LUT3 \fifo_inst/rbin_num_next_0_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next [0])
-);
-defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT3 \fifo_inst/rbin_num_next_1_s2  (
-	.I0(\fifo_inst/rbin_num_next [0]),
-	.I1(\fifo_inst/rbin_num [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
-	.F(\fifo_inst/Equal.wbinnext_0_7 )
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_8 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
 LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
-LUT4 \fifo_inst/rempty_val_s4  (
-	.I0(\fifo_inst/Equal.rq2_wptr [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.I3(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rempty_val_8 )
+LUT4 \fifo_inst/rbin_num_next_1_s3  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_10 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -217,40 +216,12 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next [0]),
+	.D(\fifo_inst/rbin_num_next_0_10 ),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
-	.D(\fifo_inst/wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [1])
-);
-defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
-	.D(\fifo_inst/wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [0])
-);
-defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [1])
-);
-defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [0])
-);
-defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_0_s0  (
 	.D(\fifo_inst/Equal.rgraynext [0]),
 	.CLK(RdClk),
@@ -273,16 +244,23 @@ DFFC \fifo_inst/wptr_0_s0  (
 );
 defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
-	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.D(\fifo_inst/Equal.wbinnext_0_8 ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/Empty_s0  (
+DFFP \fifo_inst/rempty_val1_s0  (
 	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/reset_r [1]),
+	.PRESET(\fifo_inst/n167_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n167_3 ),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -303,7 +281,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val_7 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n217_4 ),
+	.PRESET(\fifo_inst/n218_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -317,7 +295,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n217_4 ),
+	.PRESET(\fifo_inst/n218_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -326,14 +304,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n24_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[15:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:16], Q[15:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;

src/src/WrapFifoChain/Fifo16x3/Fifo16x3_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:04:59 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 11:09:42 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	Fifo16x3 your_instance_name(
-		.Data(Data_i), //input [15:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [15:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [15:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [15:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/FIFOHS.prj

@@ -4,17 +4,19 @@
     <Version>beta</Version>
     <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
     <FileList>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
-        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/Fifo16x3/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS"/>
         <Option type="output_file" value="Fifo16x3.vg"/>
         <Option type="output_template" value="Fifo16x3_tmp.v"/>
         <Option type="ram_balance" value="1"/>
         <Option type="ram_rw_check" value="1"/>
+        <Option type="vcc" value="1.2"/>
+        <Option type="vccx" value="3.3"/>
         <Option type="verilog_language" value="sysv-2017"/>
     </OptionList>
 </Project>

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3.log

@@ -1,19 +1,28 @@
 GowinSynthesis start
 Running parser ...
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
-Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
-Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'Fifo16x3'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
-Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'Reset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'RPReset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'Fifo16x3'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 NOTE  (EX0101) : Current top module is "Fifo16x3"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
@@ -29,17 +38,17 @@ Running technical mapping ...
 [60%] Tech-Mapping Phase 0 completed
 [65%] Tech-Mapping Phase 1 completed
 [75%] Tech-Mapping Phase 2 completed
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\Fifo16x3\temp\FIFOHS\Fifo16x3.vg" completed
+Generate template file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\Fifo16x3\temp\FIFOHS\Fifo16x3_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\Fifo16x3\temp\FIFOHS\Fifo16x3_syn.rpt.html" completed
 GowinSynthesis finish

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3.vg

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:04:59 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:09:42 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,129 +17,119 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+nrwY8z/Nec9IUKlRrVQ6JMH6jCXJWlZETP2N5w==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5808)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module Fifo16x3 (
   Data,

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3_syn_resource.html

@@ -30,8 +30,8 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">Fifo16x3 (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">19</td>
+<td class="label">Fifo16x3 (C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">16</td>
 <td align = "center">-</td>
 <td align = "center">18</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="Fifo16x3" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>
+<Module name="Fifo16x3" Register="16" Lut="18" Bsram="1" T_Register="16(16)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:04:59 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 11:09:42 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	Fifo16x3 your_instance_name(
-		.Data(Data_i), //input [15:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [15:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [15:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [15:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/fifo_define.v

@@ -1,5 +1,4 @@
 `define module_name Fifo16x3
 `define EBR_BASED
-`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/WrapFifoChain/FifoDDS/FifoDDS.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=true
+FirstWordFallThrough=false
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=80
 ReadDepth=2
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=false
+StandardFIFO=true
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=80

src/src/WrapFifoChain/FifoDDS/FifoDDS.v

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.03 (64-bit)"
-//Tue May 28 15:49:41 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:09:20 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,156 +17,146 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+sPn/fYjDgkHcdGVe++mN41kzGiD37X68lMYU8Q==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=7872)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7312)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoDDS (
   Data,

src/src/WrapFifoChain/FifoDDS/FifoDDS.vo

@@ -1,8 +1,8 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
-//File Title: Post-PnR Simulation Model file
-//Tool Version: V1.9.9.03 (64-bit)
-//Created Time: Tue May 28 15:49:41 2024
+//File Title: Post-PnR Verilog Simulation Model file
+//Tool Version: V1.9.11.02 (64-bit)
+//Created Time: Thu Jun 26 11:09:20 2025
 
 `timescale 100 ps/100 ps
 module FifoDDS(
@@ -37,30 +37,30 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n20_5 ;
-wire \fifo_inst/n26_4 ;
-wire \fifo_inst/n537_4 ;
+wire \fifo_inst/n24_3 ;
+wire \fifo_inst/n423_3 ;
+wire \fifo_inst/n538_4 ;
 wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val_7 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
-wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/Equal.wbinnext_0_8 ;
+wire \fifo_inst/rbin_num_next_0_10 ;
+wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
-wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [0:0] \fifo_inst/Equal.wgraynext ;
-wire [1:0] \fifo_inst/rbin_num_next ;
 wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:1] \fifo_inst/rbin_num_next ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [1:0] \fifo_inst/rbin_num ;
-wire [1:0] \fifo_inst/Equal.rq1_wptr ;
-wire [1:0] \fifo_inst/Equal.rq2_wptr ;
 wire [0:0] \fifo_inst/rptr ;
 wire [1:0] \fifo_inst/wptr ;
 wire [0:0] \fifo_inst/Equal.wbin ;
@@ -82,41 +82,39 @@ LUT4 \fifo_inst/n20_s1  (
 	.F(\fifo_inst/n20_5 )
 );
 defparam \fifo_inst/n20_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n26_s1  (
-	.I0(RdEn),
-	.I1(Empty),
-	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n26_4 )
-);
-defparam \fifo_inst/n26_s1 .INIT=8'h0E;
-LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
-	.I0(\fifo_inst/rbin_num [0]),
-	.I1(\fifo_inst/rbin_num_next [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
+LUT2 \fifo_inst/n24_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n24_3 )
 );
-defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+defparam \fifo_inst/n24_s0 .INIT=4'h4;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n537_s1  (
+LUT2 \fifo_inst/n423_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n423_3 )
+);
+defparam \fifo_inst/n423_s0 .INIT=4'hE;
+LUT2 \fifo_inst/n538_s1  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n537_4 )
+	.F(\fifo_inst/n538_4 )
 );
-defparam \fifo_inst/n537_s1 .INIT=4'h4;
+defparam \fifo_inst/n538_s1 .INIT=4'h4;
 LUT4 \fifo_inst/rempty_val_s3  (
-	.I0(\fifo_inst/Equal.rq2_wptr [1]),
-	.I1(\fifo_inst/rempty_val_8 ),
-	.I2(\fifo_inst/Equal.rq2_wptr [0]),
-	.I3(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
 LUT4 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [0]),
 	.I1(\fifo_inst/wptr [1]),
@@ -133,8 +131,8 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 );
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT3 \fifo_inst/wfull_val1_s10  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/wfull_val1_0 ),
+	.I0(\fifo_inst/wfull_val1_0 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/wfull_val1_0 )
 );
@@ -147,47 +145,48 @@ LUT3 \fifo_inst/Full_d_s  (
 );
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT3 \fifo_inst/Full_s8  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/Full_1 ),
+	.I0(\fifo_inst/Full_1 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=8'h0E;
-LUT3 \fifo_inst/rbin_num_next_0_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next [0])
-);
-defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT3 \fifo_inst/rbin_num_next_1_s2  (
-	.I0(\fifo_inst/rbin_num_next [0]),
-	.I1(\fifo_inst/rbin_num [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
-	.F(\fifo_inst/Equal.wbinnext_0_7 )
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_8 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
 LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
-LUT4 \fifo_inst/rempty_val_s4  (
-	.I0(\fifo_inst/Equal.rq2_wptr [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.I3(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rempty_val_8 )
+LUT4 \fifo_inst/rbin_num_next_1_s3  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_10 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -217,40 +216,12 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next [0]),
+	.D(\fifo_inst/rbin_num_next_0_10 ),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
-	.D(\fifo_inst/wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [1])
-);
-defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
-	.D(\fifo_inst/wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [0])
-);
-defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [1])
-);
-defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [0])
-);
-defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_0_s0  (
 	.D(\fifo_inst/Equal.rgraynext [0]),
 	.CLK(RdClk),
@@ -273,16 +244,23 @@ DFFC \fifo_inst/wptr_0_s0  (
 );
 defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
-	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.D(\fifo_inst/Equal.wbinnext_0_8 ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/Empty_s0  (
+DFFP \fifo_inst/rempty_val1_s0  (
 	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/reset_r [1]),
+	.PRESET(\fifo_inst/n423_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n423_3 ),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -303,7 +281,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val_7 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n537_4 ),
+	.PRESET(\fifo_inst/n538_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -317,7 +295,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n537_4 ),
+	.PRESET(\fifo_inst/n538_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -326,14 +304,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n24_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({Data[31:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
 	.DO({Q[31:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
@@ -347,14 +325,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_1_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n24_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({Data[63:32]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
 	.DO({Q[63:32]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .READ_MODE=1'b0;
@@ -368,14 +346,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_2_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n24_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[79:64]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:16], Q[79:64]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .READ_MODE=1'b0;

src/src/WrapFifoChain/FifoDDS/FifoDDS_tmp.v

@@ -1,10 +1,10 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.03 (64-bit)
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
-//Created Time: Tue May 28 15:49:41 2024
+//Created Time: Thu Jun 26 11:09:20 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FIFOHS.prj

@@ -4,17 +4,19 @@
     <Version>beta</Version>
     <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
     <FileList>
-        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
-        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
-        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data"/>
         <Option type="include_path" value="C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoDDS/temp/FIFOHS"/>
         <Option type="output_file" value="FifoDDS.vg"/>
         <Option type="output_template" value="FifoDDS_tmp.v"/>
         <Option type="ram_balance" value="1"/>
         <Option type="ram_rw_check" value="1"/>
+        <Option type="vcc" value="1.2"/>
+        <Option type="vccx" value="3.3"/>
         <Option type="verilog_language" value="sysv-2017"/>
     </OptionList>
 </Project>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS.log

@@ -1,19 +1,28 @@
 GowinSynthesis start
 Running parser ...
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
-Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Back to file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
-Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Analyzing included file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'FifoDDS'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
-Compiling module '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'Reset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'RPReset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoDDS'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 NOTE  (EX0101) : Current top module is "FifoDDS"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
@@ -29,13 +38,13 @@ Running technical mapping ...
 [60%] Tech-Mapping Phase 0 completed
 [65%] Tech-Mapping Phase 1 completed
 [75%] Tech-Mapping Phase 2 completed
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS.vg

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.03 (64-bit)"
-//Tue May 28 15:49:41 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:09:20 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,156 +17,146 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+sPn/fYjDgkHcdGVe++mN41kzGiD37X68lMYU8Q==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=7872)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7312)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+RduhTOFPizU7Tojp/yuOeA==
 `pragma protect end_protected
 module FifoDDS (
   Data,

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_syn_resource.html

@@ -30,8 +30,8 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">FifoDDS (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">19</td>
+<td class="label">FifoDDS (C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">16</td>
 <td align = "center">-</td>
 <td align = "center">18</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoDDS" Register="19" Lut="18" Bsram="3" T_Register="19(19)" T_Lut="18(18)" T_Bsram="3(3)"/>
+<Module name="FifoDDS" Register="16" Lut="18" Bsram="3" T_Register="16(16)" T_Lut="18(18)" T_Bsram="3(3)"/>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_tmp.v

@@ -1,10 +1,10 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.03 (64-bit)
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
-//Created Time: Tue May 28 15:49:41 2024
+//Created Time: Thu Jun 26 11:09:20 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/fifo_define.v

@@ -1,5 +1,4 @@
 `define module_name FifoDDS
 `define EBR_BASED
-`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/WrapFifoChain/FifoLMX/FifoLMX.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=true
+FirstWordFallThrough=false
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=24
 ReadDepth=16
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=false
+StandardFIFO=true
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=24

src/src/WrapFifoChain/FifoLMX/FifoLMX.v

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:07:21 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 10:59:11 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,246 +17,225 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+vflXgIPlnA4Fz6U/GJBjaBy+jPW4yirAZG0Xmw==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=13040)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=11840)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoLMX (
   Data,

src/src/WrapFifoChain/FifoLMX/FifoLMX.vo

@@ -1,8 +1,8 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
-//File Title: Post-PnR Simulation Model file
-//Tool Version: V1.9.9.02
-//Created Time: Thu Apr 25 16:07:21 2024
+//File Title: Post-PnR Verilog Simulation Model file
+//Tool Version: V1.9.11.02 (64-bit)
+//Created Time: Thu Jun 26 10:59:11 2025
 
 `timescale 100 ps/100 ps
 module FifoLMX(
@@ -37,46 +37,47 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n23_5 ;
-wire \fifo_inst/n29_4 ;
+wire \fifo_inst/n27_3 ;
 wire \fifo_inst/wfull_val ;
-wire \fifo_inst/n371_4 ;
+wire \fifo_inst/n277_3 ;
+wire \fifo_inst/n372_4 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
-wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/Equal.rgraynext_1_4 ;
+wire \fifo_inst/Equal.wbinnext_0_8 ;
+wire \fifo_inst/Equal.rgraynext_2_4 ;
 wire \fifo_inst/Equal.wgraynext_1_4 ;
 wire \fifo_inst/Equal.wgraynext_2_4 ;
 wire \fifo_inst/Equal.wgraynext_3_4 ;
 wire \fifo_inst/wfull_val_4 ;
 wire \fifo_inst/wfull_val_5 ;
-wire \fifo_inst/n371_5 ;
+wire \fifo_inst/n372_5 ;
 wire \fifo_inst/wfull_val1_16 ;
 wire \fifo_inst/Full_11 ;
+wire \fifo_inst/rbin_num_next_0_10 ;
 wire \fifo_inst/rempty_val ;
+wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n128_1_SUM ;
+wire \fifo_inst/n128_3 ;
+wire \fifo_inst/n129_1_SUM ;
+wire \fifo_inst/n129_3 ;
 wire \fifo_inst/n130_1_SUM ;
 wire \fifo_inst/n130_3 ;
 wire \fifo_inst/n131_1_SUM ;
 wire \fifo_inst/n131_3 ;
-wire \fifo_inst/n132_1_SUM ;
-wire \fifo_inst/n132_3 ;
-wire \fifo_inst/n133_1_SUM ;
-wire \fifo_inst/n133_3 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
 wire [3:0] \fifo_inst/Equal.rgraynext ;
 wire [3:0] \fifo_inst/Equal.wgraynext ;
-wire [4:0] \fifo_inst/rbin_num_next ;
+wire [4:1] \fifo_inst/rbin_num_next ;
 wire [4:1] \fifo_inst/Equal.wbinnext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [4:0] \fifo_inst/rbin_num ;
-wire [4:0] \fifo_inst/Equal.rq1_wptr ;
-wire [4:0] \fifo_inst/Equal.rq2_wptr ;
 wire [3:0] \fifo_inst/rptr ;
 wire [4:0] \fifo_inst/wptr ;
 wire [3:0] \fifo_inst/Equal.wbin ;
@@ -98,29 +99,29 @@ LUT4 \fifo_inst/n23_s1  (
 	.F(\fifo_inst/n23_5 )
 );
 defparam \fifo_inst/n23_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n29_s1  (
-	.I0(RdEn),
-	.I1(Empty),
-	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n29_4 )
-);
-defparam \fifo_inst/n29_s1 .INIT=8'h0E;
-LUT3 \fifo_inst/Equal.rgraynext_1_s0  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
-	.I1(\fifo_inst/rbin_num_next [1]),
-	.I2(\fifo_inst/rbin_num [2]),
+LUT2 \fifo_inst/n27_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n27_3 )
+);
+defparam \fifo_inst/n27_s0 .INIT=4'h4;
+LUT4 \fifo_inst/Equal.rgraynext_1_s0  (
+	.I0(\fifo_inst/n27_3 ),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/Equal.rgraynext [1])
 );
-defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=8'h1E;
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h07F8;
 LUT3 \fifo_inst/Equal.rgraynext_2_s0  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.F(\fifo_inst/Equal.rgraynext [2])
 );
 defparam \fifo_inst/Equal.rgraynext_2_s0 .INIT=8'h1E;
 LUT4 \fifo_inst/Equal.rgraynext_3_s0  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.I3(\fifo_inst/rbin_num [4]),
@@ -166,13 +167,19 @@ LUT4 \fifo_inst/wfull_val_s0  (
 	.F(\fifo_inst/wfull_val )
 );
 defparam \fifo_inst/wfull_val_s0 .INIT=16'h6000;
-LUT3 \fifo_inst/n371_s1  (
+LUT2 \fifo_inst/n277_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n277_3 )
+);
+defparam \fifo_inst/n277_s0 .INIT=4'hE;
+LUT3 \fifo_inst/n372_s1  (
 	.I0(\fifo_inst/wfull_val_4 ),
 	.I1(\fifo_inst/wfull_val_5 ),
-	.I2(\fifo_inst/n371_5 ),
-	.F(\fifo_inst/n371_4 )
+	.I2(\fifo_inst/n372_5 ),
+	.F(\fifo_inst/n372_4 )
 );
-defparam \fifo_inst/n371_s1 .INIT=8'h80;
+defparam \fifo_inst/n372_s1 .INIT=8'h80;
 LUT3 \fifo_inst/wfull_val1_s9  (
 	.I0(\fifo_inst/wfull_val1_3 ),
 	.I1(\fifo_inst/wfull_val1_2 ),
@@ -182,7 +189,7 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT4 \fifo_inst/wfull_val1_s10  (
 	.I0(\fifo_inst/wfull_val_5 ),
-	.I1(\fifo_inst/n371_5 ),
+	.I1(\fifo_inst/n372_5 ),
 	.I2(\fifo_inst/wfull_val_4 ),
 	.I3(\fifo_inst/wfull_val1_16 ),
 	.F(\fifo_inst/wfull_val1_0 )
@@ -197,42 +204,27 @@ LUT3 \fifo_inst/Full_d_s  (
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT4 \fifo_inst/Full_s8  (
 	.I0(\fifo_inst/wfull_val_5 ),
-	.I1(\fifo_inst/n371_5 ),
+	.I1(\fifo_inst/n372_5 ),
 	.I2(\fifo_inst/wfull_val_4 ),
 	.I3(\fifo_inst/Full_11 ),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=16'hFF80;
-LUT3 \fifo_inst/rbin_num_next_0_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next [0])
-);
-defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT4 \fifo_inst/rbin_num_next_1_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s5 .INIT=16'hBF40;
-LUT2 \fifo_inst/rbin_num_next_2_s5  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+LUT2 \fifo_inst/rbin_num_next_2_s3  (
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/rbin_num_next [2])
 );
-defparam \fifo_inst/rbin_num_next_2_s5 .INIT=4'h6;
-LUT3 \fifo_inst/rbin_num_next_3_s5  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+defparam \fifo_inst/rbin_num_next_2_s3 .INIT=4'h6;
+LUT3 \fifo_inst/rbin_num_next_3_s3  (
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.F(\fifo_inst/rbin_num_next [3])
 );
-defparam \fifo_inst/rbin_num_next_3_s5 .INIT=8'h78;
+defparam \fifo_inst/rbin_num_next_3_s3 .INIT=8'h78;
 LUT4 \fifo_inst/rbin_num_next_4_s2  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.I3(\fifo_inst/rbin_num [4]),
@@ -242,7 +234,7 @@ defparam \fifo_inst/rbin_num_next_4_s2 .INIT=16'h7F80;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
 	.I0(\fifo_inst/n23_5 ),
 	.I1(\fifo_inst/Equal.wbin [0]),
-	.F(\fifo_inst/Equal.wbinnext_0_7 )
+	.F(\fifo_inst/Equal.wbinnext_0_8 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
 LUT3 \fifo_inst/Equal.wbinnext_2_s3  (
@@ -267,14 +259,14 @@ LUT4 \fifo_inst/Equal.wbinnext_4_s2  (
 	.F(\fifo_inst/Equal.wbinnext [4])
 );
 defparam \fifo_inst/Equal.wbinnext_4_s2 .INIT=16'hBF40;
-LUT4 \fifo_inst/Equal.rgraynext_1_s1  (
+LUT4 \fifo_inst/Equal.rgraynext_2_s1  (
 	.I0(Empty),
 	.I1(RdEn),
 	.I2(\fifo_inst/rbin_num [0]),
 	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext_1_4 )
+	.F(\fifo_inst/Equal.rgraynext_2_4 )
 );
-defparam \fifo_inst/Equal.rgraynext_1_s1 .INIT=16'h4000;
+defparam \fifo_inst/Equal.rgraynext_2_s1 .INIT=16'h4000;
 LUT2 \fifo_inst/Equal.wgraynext_1_s1  (
 	.I0(WrEn),
 	.I1(\fifo_inst/Equal.wbin [0]),
@@ -312,13 +304,13 @@ LUT4 \fifo_inst/wfull_val_s2  (
 	.F(\fifo_inst/wfull_val_5 )
 );
 defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
-LUT3 \fifo_inst/n371_s2  (
+LUT3 \fifo_inst/n372_s2  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wptr [4]),
 	.I2(\fifo_inst/rbin_num [4]),
-	.F(\fifo_inst/n371_5 )
+	.F(\fifo_inst/n372_5 )
 );
-defparam \fifo_inst/n371_s2 .INIT=8'h14;
+defparam \fifo_inst/n372_s2 .INIT=8'h14;
 LUT2 \fifo_inst/wfull_val1_s11  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val1_0 ),
@@ -339,21 +331,36 @@ LUT4 \fifo_inst/Equal.wbinnext_1_s4  (
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s4 .INIT=16'hBF40;
+LUT4 \fifo_inst/rbin_num_next_1_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s4 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_10 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
 LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
 	.I0(Empty),
 	.I1(RdEn),
 	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num_next [1]),
+	.I3(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h4BB4;
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
 LUT3 \fifo_inst/rempty_val_s2  (
-	.I0(\fifo_inst/rbin_num_next [4]),
-	.I1(\fifo_inst/Equal.rq2_wptr [4]),
-	.I2(\fifo_inst/n133_3 ),
+	.I0(\fifo_inst/n131_3 ),
+	.I1(\fifo_inst/rbin_num [4]),
+	.I2(\fifo_inst/wptr [4]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
+defparam \fifo_inst/rempty_val_s2 .INIT=8'h41;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -404,82 +411,12 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next [0]),
+	.D(\fifo_inst/rbin_num_next_0_10 ),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_4_s0  (
-	.D(\fifo_inst/wptr [4]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [4])
-);
-defparam \fifo_inst/Equal.rq1_wptr_4_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_3_s0  (
-	.D(\fifo_inst/wptr [3]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [3])
-);
-defparam \fifo_inst/Equal.rq1_wptr_3_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_2_s0  (
-	.D(\fifo_inst/wptr [2]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [2])
-);
-defparam \fifo_inst/Equal.rq1_wptr_2_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
-	.D(\fifo_inst/wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [1])
-);
-defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
-	.D(\fifo_inst/wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [0])
-);
-defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_4_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [4]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [4])
-);
-defparam \fifo_inst/Equal.rq2_wptr_4_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_3_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [3]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [3])
-);
-defparam \fifo_inst/Equal.rq2_wptr_3_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_2_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [2]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [2])
-);
-defparam \fifo_inst/Equal.rq2_wptr_2_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [1])
-);
-defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [0])
-);
-defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_3_s0  (
 	.D(\fifo_inst/Equal.rgraynext [3]),
 	.CLK(RdClk),
@@ -565,16 +502,23 @@ DFFC \fifo_inst/Equal.wbin_1_s0  (
 );
 defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
-	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.D(\fifo_inst/Equal.wbinnext_0_8 ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/Empty_s0  (
+DFFP \fifo_inst/rempty_val1_s0  (
 	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/reset_r [1]),
+	.PRESET(\fifo_inst/n277_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n277_3 ),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -595,7 +539,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n371_4 ),
+	.PRESET(\fifo_inst/n372_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -609,7 +553,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n371_4 ),
+	.PRESET(\fifo_inst/n372_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -618,14 +562,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n23_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n29_4 ),
+	.CEB(\fifo_inst/n27_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, Data[23:0]}),
 	.ADA({GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [3:0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [3:0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, \fifo_inst/rbin_num [3:0], GND, GND, GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:24], Q[23:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
@@ -634,42 +578,42 @@ defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
-ALU \fifo_inst/n130_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [0]),
+ALU \fifo_inst/n128_s0  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
 	.I3(GND),
 	.CIN(GND),
+	.COUT(\fifo_inst/n128_3 ),
+	.SUM(\fifo_inst/n128_1_SUM )
+);
+defparam \fifo_inst/n128_s0 .ALU_MODE=3;
+ALU \fifo_inst/n129_s0  (
+	.I0(\fifo_inst/wptr [1]),
+	.I1(\fifo_inst/rptr [1]),
+	.I3(GND),
+	.CIN(\fifo_inst/n128_3 ),
+	.COUT(\fifo_inst/n129_3 ),
+	.SUM(\fifo_inst/n129_1_SUM )
+);
+defparam \fifo_inst/n129_s0 .ALU_MODE=3;
+ALU \fifo_inst/n130_s0  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rptr [2]),
+	.I3(GND),
+	.CIN(\fifo_inst/n129_3 ),
 	.COUT(\fifo_inst/n130_3 ),
 	.SUM(\fifo_inst/n130_1_SUM )
 );
 defparam \fifo_inst/n130_s0 .ALU_MODE=3;
 ALU \fifo_inst/n131_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [1]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I0(\fifo_inst/wptr [3]),
+	.I1(\fifo_inst/rptr [3]),
 	.I3(GND),
 	.CIN(\fifo_inst/n130_3 ),
 	.COUT(\fifo_inst/n131_3 ),
 	.SUM(\fifo_inst/n131_1_SUM )
 );
 defparam \fifo_inst/n131_s0 .ALU_MODE=3;
-ALU \fifo_inst/n132_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [2]),
-	.I1(\fifo_inst/Equal.rq2_wptr [2]),
-	.I3(GND),
-	.CIN(\fifo_inst/n131_3 ),
-	.COUT(\fifo_inst/n132_3 ),
-	.SUM(\fifo_inst/n132_1_SUM )
-);
-defparam \fifo_inst/n132_s0 .ALU_MODE=3;
-ALU \fifo_inst/n133_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [3]),
-	.I1(\fifo_inst/Equal.rq2_wptr [3]),
-	.I3(GND),
-	.CIN(\fifo_inst/n132_3 ),
-	.COUT(\fifo_inst/n133_3 ),
-	.SUM(\fifo_inst/n133_1_SUM )
-);
-defparam \fifo_inst/n133_s0 .ALU_MODE=3;
 INV \fifo_inst/n4_s2  (
 	.I(RdClk),
 	.O(\fifo_inst/n4_6 )

src/src/WrapFifoChain/FifoLMX/FifoLMX_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:07:21 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 10:59:11 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoLMX your_instance_name(
-		.Data(Data_i), //input [23:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [23:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [23:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [23:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FIFOHS.prj

@@ -4,17 +4,19 @@
     <Version>beta</Version>
     <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
     <FileList>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
-        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoLMX/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoLMX/temp/FIFOHS"/>
         <Option type="output_file" value="FifoLMX.vg"/>
         <Option type="output_template" value="FifoLMX_tmp.v"/>
         <Option type="ram_balance" value="1"/>
         <Option type="ram_rw_check" value="1"/>
+        <Option type="vcc" value="1.2"/>
+        <Option type="vccx" value="3.3"/>
         <Option type="verilog_language" value="sysv-2017"/>
     </OptionList>
 </Project>

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX.log

@@ -1,19 +1,28 @@
 GowinSynthesis start
 Running parser ...
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
-Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
-Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'FifoLMX'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
-Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'Reset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'RPReset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoLMX'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 NOTE  (EX0101) : Current top module is "FifoLMX"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
@@ -29,17 +38,17 @@ Running technical mapping ...
 [60%] Tech-Mapping Phase 0 completed
 [65%] Tech-Mapping Phase 1 completed
 [75%] Tech-Mapping Phase 2 completed
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoLMX\temp\FIFOHS\FifoLMX.vg" completed
+Generate template file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoLMX\temp\FIFOHS\FifoLMX_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoLMX\temp\FIFOHS\FifoLMX_syn.rpt.html" completed
 GowinSynthesis finish

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX.vg

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:07:21 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 10:59:11 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,246 +17,225 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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-Eeo9r6zKZBCzzoX/vEjCCVRH/vbTUoQQ9buY6g==
+jb/odx/M3J8e8kRiR7CVV91CJX8BTh8PdYQ4M38+OHGehJgH1KMDpY+cpGdnH57nam7FSuZ/jq0v
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+l6ZFwRGuAf1H3J0OgGic/RaTw/yCT49qxlvSJMr60oxwfMIGYDUnRPSjBxgMhgnhkKt/lTHcxx57
+vflXgIPlnA4Fz6U/GJBjaBy+jPW4yirAZG0Xmw==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=13040)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=11840)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoLMX (
   Data,

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX_syn_resource.html

@@ -30,10 +30,10 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">FifoLMX (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">37</td>
+<td class="label">FifoLMX (C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">28</td>
 <td align = "center">4</td>
-<td align = "center">38</td>
+<td align = "center">39</td>
 <td align = "center">-</td>
 <td align = "center">1</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoLMX" Register="37" Alu="4" Lut="38" Bsram="1" T_Register="37(37)" T_Alu="4(4)" T_Lut="38(38)" T_Bsram="1(1)"/>
+<Module name="FifoLMX" Register="28" Alu="4" Lut="39" Bsram="1" T_Register="28(28)" T_Alu="4(4)" T_Lut="39(39)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:07:21 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 10:59:11 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoLMX your_instance_name(
-		.Data(Data_i), //input [23:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [23:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [23:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [23:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/fifo_define.v

@@ -1,5 +1,4 @@
 `define module_name FifoLMX
 `define EBR_BASED
-`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/WrapFifoChain/FifoMax2870/FifoMax2870.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=true
+FirstWordFallThrough=false
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=32
 ReadDepth=4
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=false
+StandardFIFO=true
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=32

src/src/WrapFifoChain/FifoMax2870/FifoMax2870.v

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:07:36 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:10:16 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,164 +17,156 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
-Da6ePPXJ0x1Zkr3+qduAM8J+kvtpawq4mD4KNKBETeC4EH7Szs6BzQt56oavp90RuKDAboLkt4Jg
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-XKL3+73PMXlMajN6EcsM4S1BTp7fXxaHLIWB1w==
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+8ygXDzlmPp+ZRlqJdLYAUkCus73410L9DCj0mg==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=8352)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7904)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoMax2870 (
   Data,

src/src/WrapFifoChain/FifoMax2870/FifoMax2870.vo

@@ -1,8 +1,8 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
-//File Title: Post-PnR Simulation Model file
-//Tool Version: V1.9.9.02
-//Created Time: Thu Apr 25 16:07:36 2024
+//File Title: Post-PnR Verilog Simulation Model file
+//Tool Version: V1.9.11.02 (64-bit)
+//Created Time: Thu Jun 26 11:10:16 2025
 
 `timescale 100 ps/100 ps
 module FifoMax2870(
@@ -37,35 +37,37 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n21_5 ;
-wire \fifo_inst/n27_4 ;
+wire \fifo_inst/n25_3 ;
+wire \fifo_inst/n257_3 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
-wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/Equal.wbinnext_0_8 ;
+wire \fifo_inst/Equal.wgraynext_1_4 ;
 wire \fifo_inst/wfull_val_4 ;
 wire \fifo_inst/wfull_val_5 ;
-wire \fifo_inst/n335_6 ;
+wire \fifo_inst/n336_6 ;
 wire \fifo_inst/wfull_val ;
+wire \fifo_inst/rbin_num_next_0_10 ;
 wire \fifo_inst/rempty_val ;
+wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
-wire \fifo_inst/n158_1_SUM ;
-wire \fifo_inst/n158_3 ;
-wire \fifo_inst/n159_1_SUM ;
-wire \fifo_inst/n159_3 ;
+wire \fifo_inst/n156_1_SUM ;
+wire \fifo_inst/n156_3 ;
+wire \fifo_inst/n157_1_SUM ;
+wire \fifo_inst/n157_3 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
 wire [1:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/Equal.wgraynext ;
-wire [2:0] \fifo_inst/rbin_num_next ;
+wire [2:1] \fifo_inst/rbin_num_next ;
 wire [2:1] \fifo_inst/Equal.wbinnext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [2:0] \fifo_inst/rbin_num ;
-wire [2:0] \fifo_inst/Equal.rq1_wptr ;
-wire [2:0] \fifo_inst/Equal.rq2_wptr ;
 wire [1:0] \fifo_inst/rptr ;
 wire [2:0] \fifo_inst/wptr ;
 wire [1:0] \fifo_inst/Equal.wbin ;
@@ -86,28 +88,20 @@ LUT4 \fifo_inst/n21_s1  (
 	.F(\fifo_inst/n21_5 )
 );
 defparam \fifo_inst/n21_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n27_s1  (
-	.I0(RdEn),
-	.I1(Empty),
-	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n27_4 )
-);
-defparam \fifo_inst/n27_s1 .INIT=8'h0E;
-LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
-	.I0(\fifo_inst/rbin_num_next [0]),
-	.I1(\fifo_inst/rbin_num [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
+LUT2 \fifo_inst/n25_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n25_3 )
 );
-defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+defparam \fifo_inst/n25_s0 .INIT=4'h4;
 LUT4 \fifo_inst/Equal.rgraynext_1_s0  (
-	.I0(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/n25_3 ),
 	.I1(\fifo_inst/rbin_num [0]),
 	.I2(\fifo_inst/rbin_num [1]),
 	.I3(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/Equal.rgraynext [1])
 );
-defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h0BF4;
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h07F8;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
 	.I0(\fifo_inst/n21_5 ),
 	.I1(\fifo_inst/Equal.wbin [0]),
@@ -116,13 +110,19 @@ LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
 LUT4 \fifo_inst/Equal.wgraynext_1_s0  (
-	.I0(\fifo_inst/n21_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_1_4 ),
 	.I2(\fifo_inst/Equal.wbin [1]),
 	.I3(\fifo_inst/wptr [2]),
 	.F(\fifo_inst/Equal.wgraynext [1])
 );
-defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h07F8;
+defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h0BF4;
+LUT2 \fifo_inst/n257_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n257_3 )
+);
+defparam \fifo_inst/n257_s0 .INIT=4'hE;
 LUT3 \fifo_inst/wfull_val1_s9  (
 	.I0(\fifo_inst/wfull_val1_3 ),
 	.I1(\fifo_inst/wfull_val1_2 ),
@@ -153,49 +153,34 @@ LUT4 \fifo_inst/Full_s8  (
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=16'h00F8;
-LUT3 \fifo_inst/rbin_num_next_0_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next [0])
-);
-defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT3 \fifo_inst/rbin_num_next_1_s5  (
-	.I0(\fifo_inst/rbin_num_next [0]),
-	.I1(\fifo_inst/rbin_num [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s5 .INIT=8'hB4;
 LUT4 \fifo_inst/rbin_num_next_2_s2  (
-	.I0(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/n25_3 ),
 	.I1(\fifo_inst/rbin_num [0]),
 	.I2(\fifo_inst/rbin_num [1]),
 	.I3(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/rbin_num_next [2])
 );
-defparam \fifo_inst/rbin_num_next_2_s2 .INIT=16'hBF40;
+defparam \fifo_inst/rbin_num_next_2_s2 .INIT=16'h7F80;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
 	.I0(\fifo_inst/n21_5 ),
 	.I1(\fifo_inst/Equal.wbin [0]),
-	.F(\fifo_inst/Equal.wbinnext_0_7 )
+	.F(\fifo_inst/Equal.wbinnext_0_8 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
-LUT3 \fifo_inst/Equal.wbinnext_1_s3  (
-	.I0(\fifo_inst/n21_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
-	.I2(\fifo_inst/Equal.wbin [1]),
-	.F(\fifo_inst/Equal.wbinnext [1])
-);
-defparam \fifo_inst/Equal.wbinnext_1_s3 .INIT=8'h78;
 LUT4 \fifo_inst/Equal.wbinnext_2_s2  (
-	.I0(\fifo_inst/n21_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_1_4 ),
 	.I2(\fifo_inst/Equal.wbin [1]),
 	.I3(\fifo_inst/wptr [2]),
 	.F(\fifo_inst/Equal.wbinnext [2])
 );
-defparam \fifo_inst/Equal.wbinnext_2_s2 .INIT=16'h7F80;
+defparam \fifo_inst/Equal.wbinnext_2_s2 .INIT=16'hBF40;
+LUT2 \fifo_inst/Equal.wgraynext_1_s1  (
+	.I0(WrEn),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wgraynext_1_4 )
+);
+defparam \fifo_inst/Equal.wgraynext_1_s1 .INIT=4'h8;
 LUT2 \fifo_inst/wfull_val_s1  (
 	.I0(\fifo_inst/wptr [2]),
 	.I1(\fifo_inst/rbin_num [2]),
@@ -210,14 +195,22 @@ LUT4 \fifo_inst/wfull_val_s2  (
 	.F(\fifo_inst/wfull_val_5 )
 );
 defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
-LUT4 \fifo_inst/n335_s2  (
+LUT4 \fifo_inst/Equal.wbinnext_1_s4  (
+	.I0(Full),
+	.I1(WrEn),
+	.I2(\fifo_inst/Equal.wbin [0]),
+	.I3(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s4 .INIT=16'hBF40;
+LUT4 \fifo_inst/n336_s2  (
 	.I0(\fifo_inst/wptr [2]),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/reset_w [1]),
 	.I3(\fifo_inst/wfull_val_5 ),
-	.F(\fifo_inst/n335_6 )
+	.F(\fifo_inst/n336_6 )
 );
-defparam \fifo_inst/n335_s2 .INIT=16'h0600;
+defparam \fifo_inst/n336_s2 .INIT=16'h0600;
 LUT3 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [2]),
 	.I1(\fifo_inst/rbin_num [2]),
@@ -225,13 +218,36 @@ LUT3 \fifo_inst/wfull_val_s3  (
 	.F(\fifo_inst/wfull_val )
 );
 defparam \fifo_inst/wfull_val_s3 .INIT=8'h60;
+LUT4 \fifo_inst/rbin_num_next_1_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s4 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_10 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
 LUT3 \fifo_inst/rempty_val_s2  (
-	.I0(\fifo_inst/rbin_num_next [2]),
-	.I1(\fifo_inst/Equal.rq2_wptr [2]),
-	.I2(\fifo_inst/n159_3 ),
+	.I0(\fifo_inst/n157_3 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/wptr [2]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
+defparam \fifo_inst/rempty_val_s2 .INIT=8'h41;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -268,54 +284,12 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next [0]),
+	.D(\fifo_inst/rbin_num_next_0_10 ),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_2_s0  (
-	.D(\fifo_inst/wptr [2]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [2])
-);
-defparam \fifo_inst/Equal.rq1_wptr_2_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
-	.D(\fifo_inst/wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [1])
-);
-defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
-	.D(\fifo_inst/wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [0])
-);
-defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_2_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [2]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [2])
-);
-defparam \fifo_inst/Equal.rq2_wptr_2_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [1])
-);
-defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [0])
-);
-defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_1_s0  (
 	.D(\fifo_inst/Equal.rgraynext [1]),
 	.CLK(RdClk),
@@ -359,16 +333,23 @@ DFFC \fifo_inst/Equal.wbin_1_s0  (
 );
 defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
-	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.D(\fifo_inst/Equal.wbinnext_0_8 ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/Empty_s0  (
+DFFP \fifo_inst/rempty_val1_s0  (
 	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/reset_r [1]),
+	.PRESET(\fifo_inst/n257_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n257_3 ),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -389,7 +370,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n335_6 ),
+	.PRESET(\fifo_inst/n336_6 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -403,7 +384,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n335_6 ),
+	.PRESET(\fifo_inst/n336_6 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -412,14 +393,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n21_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n27_4 ),
+	.CEB(\fifo_inst/n25_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({Data[31:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [1:0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [1:0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [1:0], GND, GND, GND, GND, GND}),
 	.DO({Q[31:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
@@ -428,24 +409,24 @@ defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
-ALU \fifo_inst/n158_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [0]),
+ALU \fifo_inst/n156_s0  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
 	.I3(GND),
 	.CIN(GND),
-	.COUT(\fifo_inst/n158_3 ),
-	.SUM(\fifo_inst/n158_1_SUM )
+	.COUT(\fifo_inst/n156_3 ),
+	.SUM(\fifo_inst/n156_1_SUM )
 );
-defparam \fifo_inst/n158_s0 .ALU_MODE=3;
-ALU \fifo_inst/n159_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [1]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+defparam \fifo_inst/n156_s0 .ALU_MODE=3;
+ALU \fifo_inst/n157_s0  (
+	.I0(\fifo_inst/wptr [1]),
+	.I1(\fifo_inst/rptr [1]),
 	.I3(GND),
-	.CIN(\fifo_inst/n158_3 ),
-	.COUT(\fifo_inst/n159_3 ),
-	.SUM(\fifo_inst/n159_1_SUM )
+	.CIN(\fifo_inst/n156_3 ),
+	.COUT(\fifo_inst/n157_3 ),
+	.SUM(\fifo_inst/n157_1_SUM )
 );
-defparam \fifo_inst/n159_s0 .ALU_MODE=3;
+defparam \fifo_inst/n157_s0 .ALU_MODE=3;
 INV \fifo_inst/n4_s2  (
 	.I(RdClk),
 	.O(\fifo_inst/n4_6 )

src/src/WrapFifoChain/FifoMax2870/FifoMax2870_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:07:36 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 11:10:16 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoMax2870 your_instance_name(
-		.Data(Data_i), //input [31:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [31:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [31:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [31:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FIFOHS.prj

@@ -4,17 +4,19 @@
     <Version>beta</Version>
     <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
     <FileList>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
-        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoMax2870/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS"/>
         <Option type="output_file" value="FifoMax2870.vg"/>
         <Option type="output_template" value="FifoMax2870_tmp.v"/>
         <Option type="ram_balance" value="1"/>
         <Option type="ram_rw_check" value="1"/>
+        <Option type="vcc" value="1.2"/>
+        <Option type="vccx" value="3.3"/>
         <Option type="verilog_language" value="sysv-2017"/>
     </OptionList>
 </Project>

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870.log

@@ -1,19 +1,28 @@
 GowinSynthesis start
 Running parser ...
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
-Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
-Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'FifoMax2870'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
-Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'Reset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'RPReset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoMax2870'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 NOTE  (EX0101) : Current top module is "FifoMax2870"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
@@ -29,17 +38,17 @@ Running technical mapping ...
 [60%] Tech-Mapping Phase 0 completed
 [65%] Tech-Mapping Phase 1 completed
 [75%] Tech-Mapping Phase 2 completed
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoMax2870\temp\FIFOHS\FifoMax2870.vg" completed
+Generate template file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoMax2870\temp\FIFOHS\FifoMax2870_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoMax2870\temp\FIFOHS\FifoMax2870_syn.rpt.html" completed
 GowinSynthesis finish

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870.vg

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:07:36 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:10:16 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,164 +17,156 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
-Da6ePPXJ0x1Zkr3+qduAM8J+kvtpawq4mD4KNKBETeC4EH7Szs6BzQt56oavp90RuKDAboLkt4Jg
-+G92rwctBdMEwq+eB6c7QPHl/H1uRLQVqlR4yx0r3BOVYQPjoymqLzmZv8veGRBC1kdMpZB80yUK
-zmz+xkaf5+Uj2LoGUbWb2pOECph91GIFDeF+RqGJtZTKyt08qFT8oijjiMTL0Xb+qn22EE7E1RFY
-OllWGiYHO4QEEG6qgweiS5shJRiL6+3Pxmw7CJNrKZ/zyFyC0a6pFdp6mTM2DN5SkKBIq/YzyLXr
-XKL3+73PMXlMajN6EcsM4S1BTp7fXxaHLIWB1w==
+Z83UCZIyQLA5aZMBgRXKgKdFNZPpNcLIhN5ISEHIvdrYM8ZW+qkSUJuWKX54KlBm+8ZifH61UNQE
+RnYpGjhDRAcTJZ74gsP712dIgnpfywKWv4ZK+NEMenvCbcbjjSiXlH/CMlJO8pS4We5BK2jeExNN
+jvygdNr7IiAQc8H8ivK2qFpWjMu2r69ikmGmhsMV314okW5DdzS+IUlvNzB7oijB3r9n9PnflE90
+OUWcEehX0jCn4jb34XiJxgNam7WoJF5fx4wIx0ldjFDEBcgHbrDCTqr8ET4KrNzGyHGH9GCmUW+v
+8ygXDzlmPp+ZRlqJdLYAUkCus73410L9DCj0mg==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=8352)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7904)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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-eTtS/CeV+tVF1zogFIOqy9LvzYZkIDPujTi55rc8uEJeaMNOKXwgIROcKdoiJee263hDjUVNI0nq
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-OzM/12LglFlwYP+7wkdU+yudf4mjjeR1D3AMisuGdGQh0eMm036PQzMobcL1E0ILSkJYj8h9oN8J
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-vYxxZIG3T50vgimW43jJntlQNuKhGrc/+Xu37eiTc0FP/nMBOpNB9UmK865glyYCXf8xnuhFGF30
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+zG7Z44wP2cunpJrUuU2Dg8wdKK77t8k7ph7kQovaXhsaz6S6uSGLD2gF1YygCuy5vs8p+eFgn6Lr
+llhZqyOZ/VFPO1hR3VyLHTKdCSpealYt36LeyslIUreVduWuUQl4+3QplmgZTS18/Nztb3n/OYF0
+Vc/J+q+badQoqq6ZWk5+cEVjCBcM/FvVq9Wyt+g8/pG7Chnt+Zs=
 `pragma protect end_protected
 module FifoMax2870 (
   Data,

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870_syn_resource.html

@@ -30,10 +30,10 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">FifoMax2870 (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">25</td>
+<td class="label">FifoMax2870 (C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">20</td>
 <td align = "center">2</td>
-<td align = "center">23</td>
+<td align = "center">25</td>
 <td align = "center">-</td>
 <td align = "center">1</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoMax2870" Register="25" Alu="2" Lut="23" Bsram="1" T_Register="25(25)" T_Alu="2(2)" T_Lut="23(23)" T_Bsram="1(1)"/>
+<Module name="FifoMax2870" Register="20" Alu="2" Lut="25" Bsram="1" T_Register="20(20)" T_Alu="2(2)" T_Lut="25(25)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:07:36 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 11:10:16 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoMax2870 your_instance_name(
-		.Data(Data_i), //input [31:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [31:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [31:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [31:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/fifo_define.v

@@ -1,5 +1,4 @@
 `define module_name FifoMax2870
 `define EBR_BASED
-`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=true
+FirstWordFallThrough=false
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=8
 ReadDepth=2
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=false
+StandardFIFO=true
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=8

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg.v

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:08:18 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 12:23:20 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,130 +17,120 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+HIh3VFyc2t5fnAnrVhmzNZEMicj1U34soUinRQ==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5840)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoShiftReg (
   Data,

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg.vo

@@ -1,8 +1,8 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
-//File Title: Post-PnR Simulation Model file
-//Tool Version: V1.9.9.02
-//Created Time: Thu Apr 25 16:08:18 2024
+//File Title: Post-PnR Verilog Simulation Model file
+//Tool Version: V1.9.11.02 (64-bit)
+//Created Time: Thu Jun 26 12:23:20 2025
 
 `timescale 100 ps/100 ps
 module FifoShiftReg(
@@ -37,30 +37,30 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n20_5 ;
-wire \fifo_inst/n26_4 ;
-wire \fifo_inst/n177_4 ;
+wire \fifo_inst/n24_3 ;
+wire \fifo_inst/n135_3 ;
+wire \fifo_inst/n178_4 ;
 wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val_7 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
-wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/Equal.wbinnext_0_8 ;
+wire \fifo_inst/rbin_num_next_0_10 ;
+wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
-wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [0:0] \fifo_inst/Equal.wgraynext ;
-wire [1:0] \fifo_inst/rbin_num_next ;
 wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:1] \fifo_inst/rbin_num_next ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [1:0] \fifo_inst/rbin_num ;
-wire [1:0] \fifo_inst/Equal.rq1_wptr ;
-wire [1:0] \fifo_inst/Equal.rq2_wptr ;
 wire [0:0] \fifo_inst/rptr ;
 wire [1:0] \fifo_inst/wptr ;
 wire [0:0] \fifo_inst/Equal.wbin ;
@@ -82,41 +82,39 @@ LUT4 \fifo_inst/n20_s1  (
 	.F(\fifo_inst/n20_5 )
 );
 defparam \fifo_inst/n20_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n26_s1  (
-	.I0(RdEn),
-	.I1(Empty),
-	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n26_4 )
-);
-defparam \fifo_inst/n26_s1 .INIT=8'h0E;
-LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
-	.I0(\fifo_inst/rbin_num [0]),
-	.I1(\fifo_inst/rbin_num_next [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
+LUT2 \fifo_inst/n24_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n24_3 )
 );
-defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+defparam \fifo_inst/n24_s0 .INIT=4'h4;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n177_s1  (
+LUT2 \fifo_inst/n135_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n135_3 )
+);
+defparam \fifo_inst/n135_s0 .INIT=4'hE;
+LUT2 \fifo_inst/n178_s1  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n177_4 )
+	.F(\fifo_inst/n178_4 )
 );
-defparam \fifo_inst/n177_s1 .INIT=4'h4;
+defparam \fifo_inst/n178_s1 .INIT=4'h4;
 LUT4 \fifo_inst/rempty_val_s3  (
-	.I0(\fifo_inst/Equal.rq2_wptr [1]),
-	.I1(\fifo_inst/rempty_val_8 ),
-	.I2(\fifo_inst/Equal.rq2_wptr [0]),
-	.I3(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
 LUT4 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [0]),
 	.I1(\fifo_inst/wptr [1]),
@@ -133,8 +131,8 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 );
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT3 \fifo_inst/wfull_val1_s10  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/wfull_val1_0 ),
+	.I0(\fifo_inst/wfull_val1_0 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/wfull_val1_0 )
 );
@@ -147,47 +145,48 @@ LUT3 \fifo_inst/Full_d_s  (
 );
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT3 \fifo_inst/Full_s8  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/Full_1 ),
+	.I0(\fifo_inst/Full_1 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=8'h0E;
-LUT3 \fifo_inst/rbin_num_next_0_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next [0])
-);
-defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT3 \fifo_inst/rbin_num_next_1_s2  (
-	.I0(\fifo_inst/rbin_num_next [0]),
-	.I1(\fifo_inst/rbin_num [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
-	.F(\fifo_inst/Equal.wbinnext_0_7 )
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_8 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
 LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
-LUT4 \fifo_inst/rempty_val_s4  (
-	.I0(\fifo_inst/Equal.rq2_wptr [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.I3(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rempty_val_8 )
+LUT4 \fifo_inst/rbin_num_next_1_s3  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_10 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -217,40 +216,12 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next [0]),
+	.D(\fifo_inst/rbin_num_next_0_10 ),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
-	.D(\fifo_inst/wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [1])
-);
-defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
-	.D(\fifo_inst/wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [0])
-);
-defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [1])
-);
-defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [0])
-);
-defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_0_s0  (
 	.D(\fifo_inst/Equal.rgraynext [0]),
 	.CLK(RdClk),
@@ -273,16 +244,23 @@ DFFC \fifo_inst/wptr_0_s0  (
 );
 defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
-	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.D(\fifo_inst/Equal.wbinnext_0_8 ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/Empty_s0  (
+DFFP \fifo_inst/rempty_val1_s0  (
 	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/reset_r [1]),
+	.PRESET(\fifo_inst/n135_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n135_3 ),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -303,7 +281,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val_7 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n177_4 ),
+	.PRESET(\fifo_inst/n178_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -317,7 +295,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n177_4 ),
+	.PRESET(\fifo_inst/n178_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -326,14 +304,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n24_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[7:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, GND}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:8], Q[7:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:08:18 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 12:23:20 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoShiftReg your_instance_name(
-		.Data(Data_i), //input [7:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [7:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [7:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [7:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FIFOHS.prj

@@ -4,17 +4,19 @@
     <Version>beta</Version>
     <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
     <FileList>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
-        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoShiftReg/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS"/>
         <Option type="output_file" value="FifoShiftReg.vg"/>
         <Option type="output_template" value="FifoShiftReg_tmp.v"/>
         <Option type="ram_balance" value="1"/>
         <Option type="ram_rw_check" value="1"/>
+        <Option type="vcc" value="1.2"/>
+        <Option type="vccx" value="3.3"/>
         <Option type="verilog_language" value="sysv-2017"/>
     </OptionList>
 </Project>

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg.log

@@ -1,19 +1,28 @@
 GowinSynthesis start
 Running parser ...
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
-Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
-Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'FifoShiftReg'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
-Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'Reset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'RPReset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoShiftReg'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 NOTE  (EX0101) : Current top module is "FifoShiftReg"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
@@ -29,17 +38,17 @@ Running technical mapping ...
 [60%] Tech-Mapping Phase 0 completed
 [65%] Tech-Mapping Phase 1 completed
 [75%] Tech-Mapping Phase 2 completed
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoShiftReg\temp\FIFOHS\FifoShiftReg.vg" completed
+Generate template file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoShiftReg\temp\FIFOHS\FifoShiftReg_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoShiftReg\temp\FIFOHS\FifoShiftReg_syn.rpt.html" completed
 GowinSynthesis finish

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg.vg

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:08:18 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 12:23:20 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,130 +17,120 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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-ArJzg7FAyvR/3aNkWyNra/6lK47Ld15z5DXOp6Qw4yowJyzNpUIg7BGTwuT5hvVdE8HU5+LAGBLC
-8DM4h8FNMqFHubE/tetwFYOqKFxGclYw1Xqrhw==
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+HIh3VFyc2t5fnAnrVhmzNZEMicj1U34soUinRQ==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5840)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+16S6C+eWEfTdQpO0UeIHmgnX+duLBsIec7qPGa9BPY6v6fYSe59XWd8XlVH2tp9ippAAiY2RQbi+
+PYX1eGjo+6KkQ97vqbbzSlVz+WgY9jo4x0l+8cxDN14WFCT2d4woDTR3WexQ1q2Ii3JN7ppsrtCS
+CCYhBmaqujB/CF1bsuyF76xP/uilGHAS4cWY+dZda+elkUw/PBw+7aE2fLNQ4vJmS2XkhPd4j60W
++D73S5LMKPe2GiUhM2siU7Y3s+f9o2Ahm3lacvVRmeHIvZK+aQ40T+OFWlIb6VYltYtDvlxmFRBQ
+cjf5yRYhtPv8G5NHBw4akvv7y/jtL7JxgWTkmux7fWgul8hTqC5cY835wFTvuf7NcsfyXAHDvyfK
+8FJA/ZQb1gEi2/6sTyfPJUjkMvJ1HhPmKw7BvqQT5EiLL6qze+Dr3wrErJo1qTeJ7UPJ1iVO/tfg
+BfEUBlASDwCIOUXz90zB1rtT+awvNQfLQ0k=
 `pragma protect end_protected
 module FifoShiftReg (
   Data,

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg_syn_resource.html

@@ -30,8 +30,8 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">FifoShiftReg (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">19</td>
+<td class="label">FifoShiftReg (C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">16</td>
 <td align = "center">-</td>
 <td align = "center">18</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoShiftReg" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>
+<Module name="FifoShiftReg" Register="16" Lut="18" Bsram="1" T_Register="16(16)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:08:18 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 12:23:20 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoShiftReg your_instance_name(
-		.Data(Data_i), //input [7:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [7:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [7:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [7:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/fifo_define.v

@@ -1,5 +1,4 @@
 `define module_name FifoShiftReg
 `define EBR_BASED
-`define FWFT
 `define En_Reset
 `define Reset_Synchronization