Merge branch 'dev' into Anatoliy/feature_FifoCtrl

src/src/GpioCtrl/GpioCtrl.v

@@ -0,0 +1,38 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		24/04/2024 
+// Design Name: 
+// Module Name:		GpioCtrl 
+// Project Name:	SB_TMSG44V1_FPGA
+// Target Devices:	Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:		The module saves data to the register by validity signal for GPIO devices.
+//
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module GpioCtrl (
+	input Clk_i,
+	input Rst_i,
+	
+	input ValGpioDataToFifo_i,
+	input [23:0] Data_i,
+
+	output reg [21:0] GpioReg_o
+);
+
+always @(posedge Clk_i) begin
+	if(Rst_i) begin
+		GpioReg_o <= 0;
+	end 
+	else if (ValGpioDataToFifo_i) begin
+		GpioReg_o <= Data_i[21:0];
+	end
+end
+
+endmodule

src/src/GpioCtrl/GpioCtrlTb.v

@@ -0,0 +1,90 @@
+`timescale 1ns / 1ns
+
+module GpioCtrlTb();
+
+reg Clk;
+reg Rst;
+reg [4:0] cnt;
+reg [4:0] state;
+
+reg [23:0] DataGpio;
+reg ValData;
+
+always #5 Clk = ~Clk;
+
+initial begin
+	Clk	=	1'b1;
+	Rst = 	1'b1;
+	#100
+	Rst = 	1'b0;
+end
+
+always @(posedge Clk) begin
+	if(Rst) begin
+		DataGpio <= 0;
+		cnt <= 0;
+		state <= 0;
+		ValData <= 0;
+	end 
+	else begin
+		case (state)
+			0: begin
+				DataGpio <= 23'h3FFFFF;
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValData <= 1;
+					state <= state + 1;
+				end
+				else begin
+					ValData = 0;
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			1: begin
+				DataGpio <= 23'h311111;
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValData <= 1;
+					state <= state + 1;
+				end
+				else begin
+					ValData = 0;
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			2: begin
+				DataGpio <= 23'h3AAAAA;
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValData <= 1;
+					state <= state + 1;
+				end
+				else begin
+					ValData = 0;
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			3: begin
+				ValData = 0;
+			end
+		endcase
+	end
+end
+
+GpioCtrl DUT(
+	.Clk_i					(Clk),
+	.Rst_i					(Rst),
+
+	.ValGpioDataToFifo_i	(ValData),
+	.Data_i					(DataGpio),
+
+	.GpioReg_o				()
+);
+
+endmodule

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -71,7 +71,7 @@ module InterfaceArbiter
 	reg dataValReg;
 	
 	reg [OUTWORDWIDTH/4-1:0] ssCnt;
-	reg [OUTWORDWIDTH/4-1:0] wordsCnt;
+	reg [16:0] wordsCnt;
 	wire [OUTWORDWIDTH/4-1:0] ssCntRstThresh = (spiMode) ? QSPIWORDWIDTH-1:SSPIWORDWIDTH-1;
 	
 	reg [16:0] wordsNum;
@@ -90,7 +90,7 @@ module InterfaceArbiter
 	
 //================================================================================
 //  CODING
-	always @(posedge Sck_i) begin
+	always @(posedge Sck_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (!Ss_i) begin
 				captRegSspi <= {captRegSspi[OUTWORDWIDTH-2:0], Mosi0_i};
@@ -110,7 +110,7 @@ module InterfaceArbiter
 		end
 	end
 	
-	always @(posedge Sck_i) begin
+	always @(posedge Sck_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (!Ss_i) begin
 				if (ssCnt == ssCntRstThresh) begin
@@ -124,7 +124,7 @@ module InterfaceArbiter
 		end
 	end
 	
-	always @(posedge Clk_i) begin
+	always @(posedge Clk_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (currState == DATARX) begin
 				if (ssPos) begin
@@ -146,7 +146,7 @@ module InterfaceArbiter
 		end
 	end
 	
-	always @(posedge Clk_i) begin
+	always @(posedge Sck_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (currState == IDLE) begin
 				if (ssCnt == 1) begin
@@ -162,7 +162,7 @@ module InterfaceArbiter
 		end
 	end 
 	
-	always @(posedge Clk_i) begin
+	always @(posedge Clk_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (currState == IDLE) begin
 				if (!spiMode) begin
@@ -176,7 +176,7 @@ module InterfaceArbiter
 		end
 	end 
 	
-	always @(posedge Clk_i) begin
+	always @(posedge Clk_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			ssReg <= Ss_i;
 			ssRegR <= ssReg;
@@ -190,7 +190,7 @@ module InterfaceArbiter
 		end
 	end 
 	
-	always @(posedge Clk_i) begin
+	always @(posedge Clk_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (ssPos) begin
 				dataRegSSpi <= captRegSspi;
@@ -206,16 +206,16 @@ module InterfaceArbiter
 		end
 	end
 
-	always	@(posedge	Clk_i)	begin
-		if	(Rst_i)	begin
-			currState	<=	IDLE;
-		end	else	begin
-			currState	<=	nextState;
+	always @(posedge Clk_i or posedge Rst_i) begin
+		if (Rst_i) begin
+			currState <= IDLE;
+		end else begin
+			currState <= nextState;
 		end
 	end
 
 	always @(*) begin
-		nextState	=	IDLE;
+		nextState = IDLE;
 		case(currState)
 		IDLE		:begin
 						if (ssPosR)	begin

src/src/Top/ExtQspiMEmul.v

@@ -24,13 +24,13 @@ module ExtQSpiMEmul
 	localparam [1:0] PAUSE = 3;
 
 	parameter MODE = 1'h1;
-	parameter [3:0] LMX = 4'h1;
-	parameter [1:0] DDS = 2'h1;
+	parameter [3:0] LMX = 4'h3;
+	parameter [1:0] DDS = 2'h2;
 	parameter POT = 1'h1;
 	parameter DAC = 1'h1;
 	parameter ATT = 1'h1;
-	parameter [1:0] SHREG = 2'h1;
-	parameter [2:0] MAX2870 = 3'h1;
+	parameter [1:0] SHREG = 2'h3;
+	parameter [2:0] MAX2870 = 3'h3;
 	parameter [1:0] GPIO = 2'h1;
 	parameter [5:0] RESERVED = 6'h0;
 	parameter EOPBIT = 1'b0;
@@ -60,7 +60,7 @@ module ExtQSpiMEmul
 //================================================================================
 //  ASSIGNMENTS
 
-assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b1;
+assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b0;
 assign	TxDone_o	=	(txStop & (currState== CMD));
 
 //================================================================================
@@ -136,16 +136,16 @@ always	@(posedge Clk_i)	begin
 			Mosi2_o	<=	dspSpiData[11];
 			Mosi3_o	<=	dspSpiData[5];
 		end	else	begin
-			Mosi0_o	<=	1'b1;
-			Mosi1_o	<=	1'b1;
-			Mosi2_o	<=	1'b1;
-			Mosi3_o	<=	1'b1;
+			Mosi0_o	<=	1'b0;
+			Mosi1_o	<=	1'b0;
+			Mosi2_o	<=	1'b0;
+			Mosi3_o	<=	1'b0;
 		end
 	end	else	begin
-		Mosi0_o	<=	1'b1;
-		Mosi1_o	<=	1'b1;
-		Mosi2_o	<=	1'b1;
-		Mosi3_o	<=	1'b1;
+		Mosi0_o	<=	1'b0;
+		Mosi1_o	<=	1'b0;
+		Mosi2_o	<=	1'b0;
+		Mosi3_o	<=	1'b0;
 	end
 end
 

src/src/Top/ExtSpiMEmul.v

@@ -23,7 +23,7 @@ module ExtSpiMEmul
 
 	parameter MODE = 1'h0;
 	parameter [4:0] DEVID = 5'h1;
-	parameter [16:0] WORDSNUM = 17'h3;
+	parameter [16:0] WORDSNUM = 17'd24;
 	parameter EOPBIT = 1'b1;
 	
 //================================================================================
@@ -46,7 +46,7 @@ module ExtSpiMEmul
 //================================================================================
 //  ASSIGNMENTS
 
-assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b1;
+assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b0;
 assign	TxDone_o	=	(txStop & (currState== CMD));
 
 //================================================================================
@@ -119,10 +119,10 @@ always	@(posedge Clk_i)	begin
 		if	(txCnt	>=	7'd0)	begin
 			Mosi_o	<=	dspSpiData[23];
 		end	else	begin
-			Mosi_o	<=	1'b1;
+			Mosi_o	<=	1'b0;
 		end
 	end	else	begin
-		Mosi_o	<=	1'b1;
+		Mosi_o	<=	1'b0;
 	end
 end