Добавлена синхронизация команд из RegMap

sources_1/new/CDC/Cdc.v

@@ -1,77 +1,331 @@
-module  Cdc#(
-    parameter CmdRegWidth = 32,
-    parameter AddrRegWidth = 12
-)(
-    input Clk_i,
-    input [CmdRegWidth-1:0] Spi0CtrlReg_i,
-    input [CmdRegWidth-1:0] Spi0ClkReg_i,
-    input [CmdRegWidth-1:0] Spi0CsDelayReg_i,
-    input [CmdRegWidth-1:0] Spi0CsCtrlReg_i,
-    input [CmdRegWidth-1:0] Spi0TxFifoCtrlReg_i,
-    input [CmdRegWidth-1:0] Spi0RxFifoCtrlReg_i,
-    input [CmdRegWidth-1:0] AnsData_i,
-
-
-    output reg [CmdRegWidth-1:0] Spi0CtrlRR_o,
-    output reg [CmdRegWidth-1:0] Spi0ClkRR_o,
-    output reg [CmdRegWidth-1:0] Spi0CsDelayRR_o,
-    output reg [CmdRegWidth-1:0] Spi0CsCtrlRR_o,
-    output reg [CmdRegWidth-1:0] Spi0TxFifoCtrlRR_o,
-    output reg [CmdRegWidth-1:0] Spi0RxFifoCtrlRR_o,
-    output reg [CmdRegWidth-1:0] AnsDataRR_o
+module CDC #(
+    parameter WIDTH = 32,
+    parameter STAGES = 3,
+    parameter SpiNum = 7
 
+
+
+)
+(
+    input ClkFast_i,
+    input [SpiNum-1:0] ClkSlow_i,
+
+    input [WIDTH-1:0] Spi0Ctrl_i,
+    input [WIDTH-1:0] Spi0CsCtrl_i,
+    input [WIDTH-1:0] Spi0CsDelay_i,
+    input [WIDTH-1:0] Spi0TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi0RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi1Ctrl_i,
+    input [WIDTH-1:0] Spi1CsCtrl_i,
+    input [WIDTH-1:0] Spi1CsDelay_i,
+    input [WIDTH-1:0] Spi1TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi1RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi2Ctrl_i,
+    input [WIDTH-1:0] Spi2CsCtrl_i,
+    input [WIDTH-1:0] Spi2CsDelay_i,
+    input [WIDTH-1:0] Spi2TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi2RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi3Ctrl_i,
+    input [WIDTH-1:0] Spi3CsCtrl_i,
+    input [WIDTH-1:0] Spi3CsDelay_i,
+    input [WIDTH-1:0] Spi3TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi3RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi4Ctrl_i,
+    input [WIDTH-1:0] Spi4CsCtrl_i,
+    input [WIDTH-1:0] Spi4CsDelay_i,
+    input [WIDTH-1:0] Spi4TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi4RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi5Ctrl_i,
+    input [WIDTH-1:0] Spi5CsCtrl_i,
+    input [WIDTH-1:0] Spi5CsDelay_i,
+    input [WIDTH-1:0] Spi5TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi5RxFifoCtrl_i,
+
+    input [WIDTH-1:0] Spi6Ctrl_i,
+    input [WIDTH-1:0] Spi6CsCtrl_i,
+    input [WIDTH-1:0] Spi6CsDelay_i,
+    input [WIDTH-1:0] Spi6TxFifoCtrl_i,
+    input [WIDTH-1:0] Spi6RxFifoCtrl_i,
+
+    output [WIDTH-1:0] Spi0Ctrl_o,
+    output [WIDTH-1:0] Spi0CsCtrl_o,
+    output [WIDTH-1:0] Spi0CsDelay_o,
+    output [WIDTH-1:0] Spi0TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi0RxFifoCtrl_o,
+
+    output [WIDTH-1:0] Spi1Ctrl_o,
+    output [WIDTH-1:0] Spi1CsCtrl_o,
+    output [WIDTH-1:0] Spi1CsDelay_o,
+    output [WIDTH-1:0] Spi1TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi1RxFifoCtrl_o,
+
+    output [WIDTH-1:0] Spi2Ctrl_o,
+    output [WIDTH-1:0] Spi2CsCtrl_o,
+    output [WIDTH-1:0] Spi2CsDelay_o,
+    output [WIDTH-1:0] Spi2TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi2RxFifoCtrl_o,
+
+    output [WIDTH-1:0] Spi3Ctrl_o,
+    output [WIDTH-1:0] Spi3CsCtrl_o,
+    output [WIDTH-1:0] Spi3CsDelay_o,
+    output [WIDTH-1:0] Spi3TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi3RxFifoCtrl_o,
+
+    output [WIDTH-1:0] Spi4Ctrl_o,
+    output [WIDTH-1:0] Spi4CsCtrl_o,
+    output [WIDTH-1:0] Spi4CsDelay_o,
+    output [WIDTH-1:0] Spi4TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi4RxFifoCtrl_o,
+
+    output [WIDTH-1:0] Spi5Ctrl_o,
+    output [WIDTH-1:0] Spi5CsCtrl_o,
+    output [WIDTH-1:0] Spi5CsDelay_o,
+    output [WIDTH-1:0] Spi5TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi5RxFifoCtrl_o,
+    
+    output [WIDTH-1:0] Spi6Ctrl_o,
+    output [WIDTH-1:0] Spi6CsCtrl_o,
+    output [WIDTH-1:0] Spi6CsDelay_o,
+    output [WIDTH-1:0] Spi6TxFifoCtrl_o,
+    output [WIDTH-1:0] Spi6RxFifoCtrl_o
+    
 );
 
+//lauch registers 
+reg [WIDTH-1:0] spi0Ctrl;
+reg [WIDTH-1:0] spi0CsCtrl;
+reg [WIDTH-1:0] spi0CsDelay;
+reg [WIDTH-1:0] spi0TxFifoCtrl;
+reg [WIDTH-1:0] spi0RxFifoCtrl;
+
+reg [WIDTH-1:0] spi1Ctrl;
+reg [WIDTH-1:0] spi1CsCtrl;
+reg [WIDTH-1:0] spi1CsDelay;
+reg [WIDTH-1:0] spi1TxFifoCtrl;
+reg [WIDTH-1:0] spi1RxFifoCtrl;
 
-reg [CmdRegWidth-1:0] Spi0CtrlR;
-reg [CmdRegWidth-1:0] Spi0ClkRegR;
-reg [CmdRegWidth-1:0] Spi0CsDelayR;
-reg [CmdRegWidth-1:0] Spi0CsCtrlR;
-reg [CmdRegWidth-1:0] Spi0TxFifoCtrlR;
-reg [CmdRegWidth-1:0] Spi0RxFifoCtrlR;
-reg [CmdRegWidth-1:0] ansDataR;
+reg [WIDTH-1:0] spi2Ctrl;
+reg [WIDTH-1:0] spi2CsCtrl;
+reg [WIDTH-1:0] spi2CsDelay;
+reg [WIDTH-1:0] spi2TxFifoCtrl;
+reg [WIDTH-1:0] spi2RxFifoCtrl;
 
-reg [CmdRegWidth-1:0] Spi0CtrlRR;
-reg [CmdRegWidth-1:0] Spi0ClkRegRR;
-reg [CmdRegWidth-1:0] Spi0CsDelayRR;
-reg [CmdRegWidth-1:0] Spi0CsCtrlRR;
-reg [CmdRegWidth-1:0] Spi0TxFifoCtrlRR;
-reg [CmdRegWidth-1:0] Spi0RxFifoCtrlRR;
-reg [CmdRegWidth-1:0] ansDataRR;
+reg [WIDTH-1:0] spi3Ctrl;
+reg [WIDTH-1:0] spi3CsCtrl;
+reg [WIDTH-1:0] spi3CsDelay;
+reg [WIDTH-1:0] spi3TxFifoCtrl;
+reg [WIDTH-1:0] spi3RxFifoCtrl;
 
+reg [WIDTH-1:0] spi4Ctrl;
+reg [WIDTH-1:0] spi4CsCtrl;
+reg [WIDTH-1:0] spi4CsDelay;
+reg [WIDTH-1:0] spi4TxFifoCtrl;
+reg [WIDTH-1:0] spi4RxFifoCtrl;
 
+reg [WIDTH-1:0] spi5Ctrl;
+reg [WIDTH-1:0] spi5CsCtrl;
+reg [WIDTH-1:0] spi5CsDelay;
+reg [WIDTH-1:0] spi5TxFifoCtrl;
+reg [WIDTH-1:0] spi5RxFifoCtrl;
 
+reg [WIDTH-1:0] spi6Ctrl;
+reg [WIDTH-1:0] spi6CsCtrl;
+reg [WIDTH-1:0] spi6CsDelay;
+reg [WIDTH-1:0] spi6TxFifoCtrl;
+reg [WIDTH-1:0] spi6RxFifoCtrl;
 
+// capture registers
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0Ctrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0CsCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0CsDelay_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0TxFifoCtrl_c;
+(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0RxFifoCtrl_c;
 
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1RxFifoCtrl_c;
 
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2RxFifoCtrl_c;
 
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3RxFifoCtrl_c;
 
-always @(posedge Clk_i) begin
-    Spi0CtrlR <= Spi0CtrlReg_i;
-    Spi0ClkRegR <= Spi0ClkReg_i;
-    Spi0CsDelayR <= Spi0CsDelayReg_i;
-    Spi0CsCtrlR  <= Spi0CsCtrlReg_i;
-    Spi0TxFifoCtrlR <= Spi0TxFifoCtrlReg_i;
-    Spi0RxFifoCtrlR <= Spi0RxFifoCtrlReg_i;
-    ansDataR <= AnsData_i;
-    Spi0CtrlRR_o <= Spi0CtrlR;
-    Spi0ClkRR_o <= Spi0ClkRegR;
-    Spi0CsDelayRR_o <= Spi0CsDelayR;
-    Spi0CsCtrlRR_o <= Spi0CsCtrlR;
-    Spi0TxFifoCtrlRR_o <= Spi0TxFifoCtrlR;
-    Spi0RxFifoCtrlRR_o <= Spi0RxFifoCtrlR;
-    AnsDataRR_o <= ansDataR;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4RxFifoCtrl_c;
+
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5RxFifoCtrl_c;
+
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6Ctrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6CsCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6CsDelay_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6TxFifoCtrl_c;
+(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6RxFifoCtrl_c;
+
+//SPI0
+assign Spi0Ctrl_o = spi0Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi0CsDelay_o = spi0CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi0CsCtrl_o = spi0CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi0TxFifoCtrl_o = spi0TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi0RxFifoCtrl_o = spi0RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI1
+assign Spi1Ctrl_o = spi1Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi1CsDelay_o = spi1CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi1CsCtrl_o = spi1CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi1TxFifoCtrl_o = spi1TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi1RxFifoCtrl_o = spi1RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI2
+assign Spi2Ctrl_o = spi2Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi2CsDelay_o = spi2CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi2CsCtrl_o = spi2CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi2TxFifoCtrl_o = spi2TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi2RxFifoCtrl_o = spi2RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI3
+assign Spi3Ctrl_o = spi3Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi3CsDelay_o = spi3CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi3CsCtrl_o = spi3CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi3TxFifoCtrl_o = spi3TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi3RxFifoCtrl_o = spi3RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI4
+assign Spi4Ctrl_o = spi4Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi4CsDelay_o = spi4CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi4CsCtrl_o = spi4CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi4TxFifoCtrl_o = spi4TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi4RxFifoCtrl_o = spi4RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI5
+assign Spi5Ctrl_o = spi5Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi5CsDelay_o = spi5CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi5CsCtrl_o = spi5CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi5TxFifoCtrl_o = spi5TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi5RxFifoCtrl_o = spi5RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+//SPI6
+assign Spi6Ctrl_o = spi6Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi6CsDelay_o = spi6CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi6CsCtrl_o = spi6CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi6TxFifoCtrl_o = spi6TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign Spi6RxFifoCtrl_o = spi6RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+always @(posedge ClkFast_i) begin
+    spi0Ctrl <= Spi0Ctrl_i;
+    spi0CsDelay <= Spi0CsDelay_i;
+    spi0CsCtrl <= Spi0CsCtrl_i;
+    spi0TxFifoCtrl <= Spi0TxFifoCtrl_i;
+    spi0RxFifoCtrl <= Spi0RxFifoCtrl_i;
+    spi1Ctrl <= Spi1Ctrl_i;
+    spi1CsDelay <= Spi1CsDelay_i;
+    spi1CsCtrl <= Spi1CsCtrl_i;
+    spi1TxFifoCtrl <= Spi1TxFifoCtrl_i;
+    spi1RxFifoCtrl <= Spi1RxFifoCtrl_i;
+    spi2Ctrl <= Spi2Ctrl_i;
+    spi2CsDelay <= Spi2CsDelay_i;
+    spi2CsCtrl <= Spi2CsCtrl_i;
+    spi2TxFifoCtrl <= Spi2TxFifoCtrl_i;
+    spi2RxFifoCtrl <= Spi2RxFifoCtrl_i;
+    spi3Ctrl <= Spi3Ctrl_i;
+    spi3CsDelay <= Spi3CsDelay_i;
+    spi3CsCtrl <= Spi3CsCtrl_i;
+    spi3TxFifoCtrl <= Spi3TxFifoCtrl_i;
+    spi3RxFifoCtrl <= Spi3RxFifoCtrl_i;
+    spi4Ctrl <= Spi4Ctrl_i;
+    spi4CsDelay <= Spi4CsDelay_i;
+    spi4CsCtrl <= Spi4CsCtrl_i;
+    spi4TxFifoCtrl <= Spi4TxFifoCtrl_i;
+    spi4RxFifoCtrl <= Spi4RxFifoCtrl_i;
+    spi5Ctrl <= Spi5Ctrl_i;
+    spi5CsDelay <= Spi5CsDelay_i;
+    spi5CsCtrl <= Spi5CsCtrl_i;
+    spi5TxFifoCtrl <= Spi5TxFifoCtrl_i;
+    spi5RxFifoCtrl <= Spi5RxFifoCtrl_i;
+    spi6Ctrl <= Spi6Ctrl_i;
+    spi6CsDelay <= Spi6CsDelay_i;
+    spi6CsCtrl <= Spi6CsCtrl_i;
+    spi6TxFifoCtrl <= Spi6TxFifoCtrl_i;
+    spi6RxFifoCtrl <= Spi6RxFifoCtrl_i;
 end
 
 
 
 
 
+always @(posedge ClkSlow_i[0]) begin 
+    spi0Ctrl_c <= {spi0Ctrl_c[(STAGES-1)*WIDTH-1:0],spi0Ctrl};
+    spi0CsDelay_c <= {spi0CsDelay_c[(STAGES-1)*WIDTH-1:0],spi0CsDelay};
+    spi0CsCtrl_c <= {spi0CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi0CsCtrl};
+    spi0TxFifoCtrl_c <= {spi0TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi0TxFifoCtrl};
+    spi0RxFifoCtrl_c <= {spi0RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi0RxFifoCtrl};
+end
+
+always@(posedge ClkSlow_i[1]) begin 
+    spi1Ctrl_c <= {spi1Ctrl_c[(STAGES-1)*WIDTH-1:0],spi1Ctrl};
+    spi1CsDelay_c <= {spi1CsDelay_c[(STAGES-1)*WIDTH-1:0],spi1CsDelay};
+    spi1CsCtrl_c <= {spi1CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi1CsCtrl};
+    spi1TxFifoCtrl_c <= {spi1TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi1TxFifoCtrl};
+    spi1RxFifoCtrl_c <= {spi1RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi1RxFifoCtrl};
+end
+
+always@(posedge ClkSlow_i[2]) begin 
+    spi2Ctrl_c <= {spi2Ctrl_c[(STAGES-1)*WIDTH-1:0],spi2Ctrl};
+    spi2CsDelay_c <= {spi2CsDelay_c[(STAGES-1)*WIDTH-1:0],spi2CsDelay};
+    spi2CsCtrl_c <= {spi2CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi2CsCtrl};
+    spi2TxFifoCtrl_c <= {spi2TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi2TxFifoCtrl};
+    spi2RxFifoCtrl_c <= {spi2RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi2RxFifoCtrl};
+end
+
+always@(posedge ClkSlow_i[3]) begin 
+    spi3Ctrl_c <= {spi3Ctrl_c[(STAGES-1)*WIDTH-1:0],spi3Ctrl};
+    spi3CsDelay_c <= {spi3CsDelay_c[(STAGES-1)*WIDTH-1:0],spi3CsDelay};
+    spi3CsCtrl_c <= {spi3CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi3CsCtrl};
+    spi3TxFifoCtrl_c <= {spi3TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi3TxFifoCtrl};
+    spi3RxFifoCtrl_c <= {spi3RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi3RxFifoCtrl};
+end
+
+always@(posedge ClkSlow_i[4]) begin 
+    spi4Ctrl_c <= {spi4Ctrl_c[(STAGES-1)*WIDTH-1:0],spi4Ctrl};
+    spi4CsDelay_c <= {spi4CsDelay_c[(STAGES-1)*WIDTH-1:0],spi4CsDelay};
+    spi4CsCtrl_c <= {spi4CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi4CsCtrl};
+    spi4TxFifoCtrl_c <= {spi4TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi4TxFifoCtrl};
+    spi4RxFifoCtrl_c <= {spi4RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi4RxFifoCtrl};
+end
 
+always@(posedge ClkSlow_i[5]) begin 
+    spi5Ctrl_c <= {spi5Ctrl_c[(STAGES-1)*WIDTH-1:0],spi5Ctrl};
+    spi5CsDelay_c <= {spi5CsDelay_c[(STAGES-1)*WIDTH-1:0],spi5CsDelay};
+    spi5CsCtrl_c <= {spi5CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi5CsCtrl};
+    spi5TxFifoCtrl_c <= {spi5TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi5TxFifoCtrl};
+    spi5RxFifoCtrl_c <= {spi5RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi5RxFifoCtrl};
+end
 
+always@(posedge ClkSlow_i[6]) begin 
+    spi6Ctrl_c <= {spi6Ctrl_c[(STAGES-1)*WIDTH-1:0],spi6Ctrl};
+    spi6CsDelay_c <= {spi6CsDelay_c[(STAGES-1)*WIDTH-1:0],spi6CsDelay};
+    spi6CsCtrl_c <= {spi6CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi6CsCtrl};
+    spi6TxFifoCtrl_c <= {spi6TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi6TxFifoCtrl};
+    spi6RxFifoCtrl_c <= {spi6RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi6RxFifoCtrl};
+end
 
 
 
 
-endmodule
 
+endmodule

sources_1/new/CDC/Sync1bit.v

@@ -0,0 +1,47 @@
+module Sync1bit #(
+    parameter WIDTH = 1,
+    parameter STAGES = 3
+
+
+
+)
+(
+    input ClkFast_i,
+    input ClkSlow_i,
+    input TxEn_i,
+    input RstReg_i,
+
+    output [WIDTH-1:0] TxEn_o,
+    output [WIDTH-1:0] RstReg_o
+
+);
+//lauch registers 
+reg spiTxEnReg;
+reg rstReg;
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] spiTxEnReg_c;
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rstReg_c;
+
+assign TxEn_o = spiTxEnReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+assign RstReg_o = rstReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+always @(posedge ClkFast_i) begin
+    spiTxEnReg <= TxEn_i;
+    rstReg <= RstReg_i;
+end
+
+
+
+
+
+always @(posedge ClkSlow_i) begin 
+    spiTxEnReg_c <= {spiTxEnReg_c[(STAGES-1)*WIDTH-1:0], spiTxEnReg};
+    rstReg_c <= {rstReg_c[(STAGES-1)*WIDTH-1:0], rstReg};
+end
+
+
+
+
+
+endmodule

sources_1/new/DataFifo/DataFifoWrapper.v

@@ -3,6 +3,7 @@ module DataFifoWrapper
 #(
     parameter	CmdRegWidth	=	32,
     parameter	AddrRegWidth=	12,
+	parameter	STAGES		=	3,
 	
 	parameter	FifoNum	=	7
 )
@@ -11,6 +12,8 @@ module DataFifoWrapper
 	input	RdClk_i,
     input	FifoRxRst_i,
 	input	FifoTxRst_i,
+	input	FifoTxRstWrPtr_i,
+	input	FifoRxRstRdPtr_i,
 	input   SmcAre_i,
 	input	SmcAwe_i,
 	input	[AddrRegWidth-1:0]	SmcAddr_i,
@@ -63,64 +66,66 @@ module DataFifoWrapper
 //	CODING
 //================================================================================
 
-FifoCtrl FifoCtrl_inst (
-	.ToFifoTxWriteVal_i	(ToFifoVal_i),
-	.ToFifoTxReadVal_i (ToFifoTxReadVal_i),
-	.ToFifoRxWriteVal_i	(ToFifoRxWriteVal_i),
-	.ToFifoRxReadVal_i	(!SmcAre_i),
-	.SmcAddr_i			(SmcAddr_i),
-	.TxFifoWrdCnt_i		(TxFifoWrdCnt_i),
-	.RxFifoWrdCnt_i		(RxFifoWrdCnt_i),
-	.FifoTxFull_i		(fullFlagTx),
-	.FifoTxRst_i		(FifoTxRst_i),
-	.FifoRxRst_i		(FifoRxRst_i),
-	.FifoTxEmpty_i		(emptyFlagTx),
-	.FifoRxFull_i		(fullFlagRx),
-	.FifoRxEmpty_i		(emptyFlagRx),
-	.FifoTxWrClock_i	(WrClk_i),
-	.FifoTxRdClock_i	(RdClk_i),
-	.FifoRxWrClock_i	(RdClk_i),
-	.FifoRxRdClock_i	(WrClk_i),
-	.RxFifoUpDnCnt_o	(rxFifoUpDnCnt),
-	.TxFifoUpDnCnt_o	(txFifoUpDnCnt),
-	.FifoTxWriteEn_o	(txFifoWrEn),
-	.FifoTxReadEn_o		(txFifoRdEn),
-	.FifoRxWriteEn_o	(rxFifoWrEn),
-	.FifoRxReadEn_o		(rxFifoRdEn)
-
-
-
-
-
-);
-
-
-
-DataFifoTx	DataFifoTx
-( 
-	.wr_clk		(WrClk_i), 
-	.rd_clk		(RdClk_i), 
-	.rst		(FifoTxRst_i),
-	.din		(ToFifoData_i), 
-	.wr_en		(txFifoWrEn), 
-	.rd_en		(txFifoRdEn), 
-	.dout		(ToSpiData_o),
-	.full		(fullFlagTx), 
-	.empty		(emptyFlagTx)
-
-);
-
-DataFifoRx	DataFifoRx
-( 
-	.wr_clk		(RdClk_i), 
-	.rd_clk		(WrClk_i),
-	.rst		(FifoRxRst_i), 
-	.din		(ToFifoRxData_i), 
-	.wr_en		(rxFifoWrEn), 
-	.rd_en		(rxFifoRdEn), 
-	.dout		(dataFromRxFifo), 
-	.full		(fullFlagRx), 
-	.empty		(emptyFlagRx)
-);
-
-endmodule
+	FifoCtrl FifoCtrl_inst (
+		.ToFifoTxWriteVal_i	(ToFifoVal_i),
+		.ToFifoTxReadVal_i (ToFifoTxReadVal_i),
+		.ToFifoRxWriteVal_i	(ToFifoRxWriteVal_i),
+		.ToFifoRxReadVal_i	(!SmcAre_i),
+		.SmcAddr_i			(SmcAddr_i),
+		.TxFifoWrdCnt_i		(TxFifoWrdCnt_i),
+		.RxFifoWrdCnt_i		(RxFifoWrdCnt_i),
+		.FifoTxFull_i		(fullFlagTx),
+		.FifoTxRst_i		(FifoTxRst_i),
+		.FifoRxRst_i		(FifoRxRst_i),
+		.FifoTxRstWrPtr_i	(FifoTxRstWrPtr_i),
+		.FifoRxRstRdPtr_i	(FifoRxRstRdPtr_i),
+		.FifoTxEmpty_i		(emptyFlagTx),
+		.FifoRxFull_i		(fullFlagRx),
+		.FifoRxEmpty_i		(emptyFlagRx),
+		.FifoTxWrClock_i	(WrClk_i),
+		.FifoTxRdClock_i	(RdClk_i),
+		.FifoRxWrClock_i	(RdClk_i),
+		.FifoRxRdClock_i	(WrClk_i),
+		.RxFifoUpDnCnt_o	(rxFifoUpDnCnt),
+		.TxFifoUpDnCnt_o	(txFifoUpDnCnt),
+		.FifoTxWriteEn_o	(txFifoWrEn),
+		.FifoTxReadEn_o		(txFifoRdEn),
+		.FifoRxWriteEn_o	(rxFifoWrEn),
+		.FifoRxReadEn_o		(rxFifoRdEn)
+	
+	
+	
+	
+	
+	);
+	
+	
+	
+	DataFifoTx	DataFifoTx
+	( 
+		.wr_clk		(WrClk_i), 
+		.rd_clk		(RdClk_i), 
+		.rst		(FifoTxRst_i),
+		.din		(ToFifoData_i), 
+		.wr_en		(txFifoWrEn), 
+		.rd_en		(txFifoRdEn), 
+		.dout		(ToSpiData_o),
+		.full		(fullFlagTx), 
+		.empty		(emptyFlagTx)
+	
+	);
+	
+	DataFifoRx	DataFifoRx
+	( 
+		.wr_clk		(RdClk_i), 
+		.rd_clk		(WrClk_i),
+		.rst		(FifoRxRst_i), 
+		.din		(ToFifoRxData_i), 
+		.wr_en		(rxFifoWrEn), 
+		.rd_en		(rxFifoRdEn), 
+		.dout		(dataFromRxFifo), 
+		.full		(fullFlagRx), 
+		.empty		(emptyFlagRx)
+	);
+	
+	endmodule

sources_1/new/DataFifo/DataOutMux.v

@@ -26,142 +26,142 @@ module DataOutMux#(
 );
 
 
-wire [0:31] dataFromRxFifo [6:0];
-wire [15:0] dataFromRegMap;
-
-reg [15:0] dataFromRxFifoR;
-reg [1:0] readEnCnt;
-
-(* dont_touch = "true" *)reg [CmdRegWidth/2-1:0] dataFromRxFifoR1;
-reg [CmdRegWidth-1:0] dataFromRxFifoR2;
-reg [CmdRegWidth-1:0] dataFromRxFifoR3;
-reg [CmdRegWidth-1:0] dataFromRxFifoR4;
-reg [CmdRegWidth-1:0] dataFromRxFifoR5;
-reg [CmdRegWidth-1:0] dataFromRxFifoR6;
-reg [CmdRegWidth-1:0] dataFromRxFifoR7;
-
-
-
-assign dataFromRxFifo[0] = DataFromRxFifo1_i;
-assign dataFromRxFifo[1] = DataFromRxFifo2_i;
-assign dataFromRxFifo[2] = DataFromRxFifo3_i;
-assign dataFromRxFifo[3] = DataFromRxFifo4_i;
-assign dataFromRxFifo[4] = DataFromRxFifo5_i;
-assign dataFromRxFifo[5] = DataFromRxFifo6_i;
-assign dataFromRxFifo[6] = DataFromRxFifo7_i;
-
-assign dataFromRegMap = DataFromRegMap_i;
-assign AnsData_o = (ToRegMapAddr_i)?dataFromRegMap:dataFromRxFifoR;
-
-
-always @(posedge Clk_i) begin 
-    if (FifoRxRst_i) begin 
-        readEnCnt <= 1'b0;
-    end
-    else begin 
-        if (!SmcAre_i) begin 
-            readEnCnt <= readEnCnt + 1'b1;
+    wire [0:31] dataFromRxFifo [6:0];
+    wire [15:0] dataFromRegMap;
+    
+    reg [15:0] dataFromRxFifoR;
+    reg [1:0] readEnCnt;
+    
+    (* dont_touch = "true" *)reg [CmdRegWidth/2-1:0] dataFromRxFifoR1;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR2;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR3;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR4;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR5;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR6;
+    reg [CmdRegWidth-1:0] dataFromRxFifoR7;
+    
+    
+    
+    assign dataFromRxFifo[0] = DataFromRxFifo1_i;
+    assign dataFromRxFifo[1] = DataFromRxFifo2_i;
+    assign dataFromRxFifo[2] = DataFromRxFifo3_i;
+    assign dataFromRxFifo[3] = DataFromRxFifo4_i;
+    assign dataFromRxFifo[4] = DataFromRxFifo5_i;
+    assign dataFromRxFifo[5] = DataFromRxFifo6_i;
+    assign dataFromRxFifo[6] = DataFromRxFifo7_i;
+    
+    assign dataFromRegMap = DataFromRegMap_i;
+    assign AnsData_o = (ToRegMapAddr_i)?dataFromRegMap:dataFromRxFifoR;
+    
+    
+    always @(posedge Clk_i) begin 
+        if (FifoRxRst_i) begin 
+            readEnCnt <= 1'b0;
         end
         else begin 
-            readEnCnt <= 1'b0;
+            if (!SmcAre_i) begin 
+                readEnCnt <= readEnCnt + 1'b1;
+            end
+            else begin 
+                readEnCnt <= 1'b0;
+            end
         end
     end
-end
-
-
-
-always @(*) begin
-    if (Rst_i) begin
-        dataFromRxFifoR1 = 0;
-        dataFromRxFifoR2 = 0;
-        dataFromRxFifoR3 = 0;
-        dataFromRxFifoR4 = 0;
-        dataFromRxFifoR5 = 0;
-        dataFromRxFifoR6 = 0;
-        dataFromRxFifoR7 = 0;
+    
+    
+    
+    always @(*) begin
+        if (Rst_i) begin
+            dataFromRxFifoR1 = 0;
+            dataFromRxFifoR2 = 0;
+            dataFromRxFifoR3 = 0;
+            dataFromRxFifoR4 = 0;
+            dataFromRxFifoR5 = 0;
+            dataFromRxFifoR6 = 0;
+            dataFromRxFifoR7 = 0;
+        end
+        else begin
+            if (!SmcAre_i && readEnCnt < 1 ) begin  
+                case(Addr_i) 
+                    12'h1c : begin
+                        dataFromRxFifoR1 = DataFromRxFifo1_i[31:16];
+                    end
+                    12'h6c : begin
+                        dataFromRxFifoR2 = DataFromRxFifo2_i;
+                    end
+                    12'h10c : begin
+                        dataFromRxFifoR3 = DataFromRxFifo3_i;
+                    end
+                    12'h15c : begin
+                        dataFromRxFifoR4 = DataFromRxFifo4_i;
+                    end
+                    12'h1ac : begin
+                        dataFromRxFifoR5 = DataFromRxFifo5_i;
+                    end
+                    12'h1fc : begin
+                        dataFromRxFifoR6 = DataFromRxFifo6_i;
+                    end
+                    12'h24c : begin
+                        dataFromRxFifoR7 = DataFromRxFifo7_i;
+                    end
+                endcase
+            end
+        end
     end
-    else begin
-        if (!SmcAre_i && readEnCnt < 1 ) begin  
-            case(Addr_i) 
-                12'h1c : begin
-                    dataFromRxFifoR1 = DataFromRxFifo1_i[31:16];
+    
+    
+    
+    always @(*) begin 
+            case (Addr_i)  
+                12'h1c: begin 
+                    dataFromRxFifoR = DataFromRxFifo1_i[15:0];
+                end
+                12'h1e: begin
+                    dataFromRxFifoR = dataFromRxFifoR1;
+                end 
+                12'h6c: begin 
+                    dataFromRxFifoR =  DataFromRxFifo2_i[15:0];
+                end
+                12'h6e: begin 
+                    dataFromRxFifoR = dataFromRxFifoR2[31:16];
+                end
+                12'h10c: begin 
+                    dataFromRxFifoR =  DataFromRxFifo3_i[15:0];
+                end
+                12'h10e: begin 
+                    dataFromRxFifoR = dataFromRxFifoR3[31:16];
+                end
+                12'h15c: begin 
+                    dataFromRxFifoR =  DataFromRxFifo4_i[15:0];
+                end
+                12'h15e: begin 
+                    dataFromRxFifoR = dataFromRxFifoR4[31:16];
                 end
-                12'h6c : begin
-                    dataFromRxFifoR2 = DataFromRxFifo2_i;
+                12'h1ac: begin 
+                    dataFromRxFifoR =  DataFromRxFifo5_i[15:0];
                 end
-                12'h10c : begin
-                    dataFromRxFifoR3 = DataFromRxFifo3_i;
+                12'h1ae: begin 
+                    dataFromRxFifoR = dataFromRxFifoR5[31:16];
                 end
-                12'h15c : begin
-                    dataFromRxFifoR4 = DataFromRxFifo4_i;
+                12'h1fc: begin 
+                    dataFromRxFifoR =  DataFromRxFifo6_i[15:0];
                 end
-                12'h1ac : begin
-                    dataFromRxFifoR5 = DataFromRxFifo5_i;
+                12'h1fe: begin 
+                    dataFromRxFifoR = dataFromRxFifoR6[31:16];
                 end
-                12'h1fc : begin
-                    dataFromRxFifoR6 = DataFromRxFifo6_i;
+                12'h24c: begin 
+                    dataFromRxFifoR =  DataFromRxFifo7_i[15:0];
                 end
-                12'h24c : begin
-                    dataFromRxFifoR7 = DataFromRxFifo7_i;
+                12'h24e: begin 
+                    dataFromRxFifoR = dataFromRxFifoR7[31:16];
+                end
+                default: begin
+                    dataFromRxFifoR = 16'h0;
                 end
             endcase
         end
-    end
-end
-
-
-
-always @(*) begin 
-        case (Addr_i)  
-            12'h1c: begin 
-                dataFromRxFifoR = DataFromRxFifo1_i[15:0];
-            end
-            12'h1e: begin
-                dataFromRxFifoR = dataFromRxFifoR1;
-            end 
-            12'h6c: begin 
-                dataFromRxFifoR =  DataFromRxFifo2_i[15:0];
-            end
-            12'h6e: begin 
-                dataFromRxFifoR = dataFromRxFifoR2[31:16];
-            end
-            12'h10c: begin 
-                dataFromRxFifoR =  DataFromRxFifo3_i[15:0];
-            end
-            12'h10e: begin 
-                dataFromRxFifoR = dataFromRxFifoR3[31:16];
-            end
-            12'h15c: begin 
-                dataFromRxFifoR =  DataFromRxFifo4_i[15:0];
-            end
-            12'h15e: begin 
-                dataFromRxFifoR = dataFromRxFifoR4[31:16];
-            end
-            12'h1ac: begin 
-                dataFromRxFifoR =  DataFromRxFifo5_i[15:0];
-            end
-            12'h1ae: begin 
-                dataFromRxFifoR = dataFromRxFifoR5[31:16];
-            end
-            12'h1fc: begin 
-                dataFromRxFifoR =  DataFromRxFifo6_i[15:0];
-            end
-            12'h1fe: begin 
-                dataFromRxFifoR = dataFromRxFifoR6[31:16];
-            end
-            12'h24c: begin 
-                dataFromRxFifoR =  DataFromRxFifo7_i[15:0];
-            end
-            12'h24e: begin 
-                dataFromRxFifoR = dataFromRxFifoR7[31:16];
-            end
-            default: begin
-                dataFromRxFifoR = 16'h0;
-            end
-        endcase
-    end
-
-
-
-
-endmodule
+    
+    
+    
+    
+    endmodule

sources_1/new/DataFifo/FifoCtrl.v

@@ -5,214 +5,261 @@ module FifoCtrl #(
 	parameter Fifo3ReadMsbAddr		= 12'h140+12'd28,
 	parameter Fifo4ReadMsbAddr		= 12'h190+12'd28,
 	parameter Fifo5ReadMsbAddr		= 12'h1e0+12'd28,
-	parameter Fifo6ReadMsbAddr		= 12'h230+12'd28
+	parameter Fifo6ReadMsbAddr		= 12'h230+12'd28,
+    parameter STAGES = 3
 
 
 
 
 )(
-  input ToFifoTxWriteVal_i,
-  input ToFifoTxReadVal_i,
-  input ToFifoRxWriteVal_i,
-  input ToFifoRxReadVal_i,
+    input ToFifoTxWriteVal_i,
+    input ToFifoTxReadVal_i,
+    input ToFifoRxWriteVal_i,
+    input ToFifoRxReadVal_i,
 
-  input FifoTxFull_i,
-  input FifoTxEmpty_i,
-  input FifoRxFull_i,
-  input FifoRxEmpty_i,
-  input [11:0] SmcAddr_i,
+    input FifoTxFull_i,
+    input FifoTxEmpty_i,
+    input FifoRxFull_i,
+    input FifoRxEmpty_i,
+    input [11:0] SmcAddr_i,
 
-  input   [7:0] TxFifoWrdCnt_i,
-  input   [7:0] RxFifoWrdCnt_i,
+    input   [7:0] TxFifoWrdCnt_i,
+    input   [7:0] RxFifoWrdCnt_i,
 
-  input FifoTxWrClock_i,
-  input FifoTxRdClock_i,
-  input FifoRxWrClock_i,
-  input FifoRxRdClock_i,
+    input FifoTxWrClock_i,
+    input FifoTxRdClock_i,
+    input FifoRxWrClock_i,
+    input FifoRxRdClock_i,
 
-  input FifoTxRst_i,
-  input FifoRxRst_i,
+    input FifoTxRst_i,
+    input FifoRxRst_i,
 
+    input FifoTxRstWrPtr_i,
+    input FifoRxRstRdPtr_i,
 
-  output  [7:0] RxFifoUpDnCnt_o,
-  output  [7:0] TxFifoUpDnCnt_o,
 
-  output FifoTxWriteEn_o,
-  output FifoTxReadEn_o,
-  output FifoRxWriteEn_o,
-  output FifoRxReadEn_o
-
-);
-
-
-reg fifoTxWriteEn;
-reg fifoTxReadEn;
-reg fifoRxWriteEn;
-reg fifoRxReadEn;
-
-(* dont_touch = "true" *)reg [7:0] txFifoWrPtr;
-(* dont_touch = "true" *)reg [7:0] txFifoRdPtr;
-(* dont_touch = "true" *)reg [7:0] rxFifoWrPtr;
-(* dont_touch = "true" *)reg [7:0] rxFifoRdPtr;
-
-(* dont_touch = "true" *) reg [7:0] rxFifoUpDnCnt;
-(* dont_touch = "true" *) reg [7:0] txFifoUpDnCnt;
-
-reg [1:0] readEnCnt;    
-
-
-
-wire	requestToFifo0	=(SmcAddr_i == Fifo0ReadMsbAddr)?1'b1:1'b0;
-wire	requestToFifo1	=(SmcAddr_i == Fifo1ReadMsbAddr)?1'b1:1'b0;
-wire	requestToFifo2	=(SmcAddr_i == Fifo2ReadMsbAddr)?1'b1:1'b0;
-wire	requestToFifo3	=(SmcAddr_i == Fifo3ReadMsbAddr)?1'b1:1'b0;
-wire	requestToFifo4	=(SmcAddr_i == Fifo4ReadMsbAddr)?1'b1:1'b0;
-wire	requestToFifo5	=(SmcAddr_i == Fifo5ReadMsbAddr)?1'b1:1'b0;
-wire	requestToFifo6	=(SmcAddr_i == Fifo6ReadMsbAddr)?1'b1:1'b0;
-wire	requestToFifo   =(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6)?1'b1:1'b0;
+    output  [7:0] RxFifoUpDnCnt_o,
+    output  [7:0] TxFifoUpDnCnt_o,
 
+    output FifoTxWriteEn_o,
+    output FifoTxReadEn_o,
+    output FifoRxWriteEn_o,
+    output FifoRxReadEn_o
 
-
-// //================================================================================
-// //	ASSIGNMENTS
-
-assign FifoTxWriteEn_o = fifoTxWriteEn;
-assign FifoTxReadEn_o = fifoTxReadEn;
-assign FifoRxWriteEn_o = fifoRxWriteEn;
-assign FifoRxReadEn_o = fifoRxReadEn;
-
-
-assign RxFifoUpDnCnt_o = rxFifoUpDnCnt;
-assign TxFifoUpDnCnt_o = txFifoUpDnCnt;
-
-
-// //================================================================================
+);
 
 
-always @(posedge FifoRxRdClock_i) begin 
-    if (FifoRxRst_i) begin 
-        readEnCnt <= 1'b0;
-    end
-    else begin 
-        if (ToFifoRxReadVal_i) begin 
-            readEnCnt <= readEnCnt + 1'b1;
+    reg fifoTxWriteEn;
+    reg fifoTxReadEn;
+    reg fifoRxWriteEn;
+    reg fifoRxReadEn;
+    
+    (* dont_touch = "true" *)reg [7:0] txFifoWrPtr;
+    (* dont_touch = "true" *)reg [7:0] txFifoRdPtr;
+    (* dont_touch = "true" *)reg [7:0] rxFifoWrPtr;
+    (* dont_touch = "true" *)reg [7:0] rxFifoRdPtr;
+    
+    (* dont_touch = "true" *) reg [7:0] rxFifoUpDnCnt;
+    (* dont_touch = "true" *) reg [7:0] txFifoUpDnCnt;
+    
+    reg [1:0] readEnCnt;    
+    
+    
+    
+    wire	requestToFifo0	=(SmcAddr_i == Fifo0ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo1	=(SmcAddr_i == Fifo1ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo2	=(SmcAddr_i == Fifo2ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo3	=(SmcAddr_i == Fifo3ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo4	=(SmcAddr_i == Fifo4ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo5	=(SmcAddr_i == Fifo5ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo6	=(SmcAddr_i == Fifo6ReadMsbAddr)?1'b1:1'b0;
+    wire	requestToFifo   =(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6)?1'b1:1'b0;
+
+    wire [7:0] rxFifoWrPtrSync;
+    wire [7:0] txFifoWrPtrSync;
+
+    wire rxFifoRstSync;
+
+    
+    
+    
+    // //================================================================================
+    // //	ASSIGNMENTS
+    
+    assign FifoTxWriteEn_o = fifoTxWriteEn;
+    assign FifoTxReadEn_o = fifoTxReadEn;
+    assign FifoRxWriteEn_o = fifoRxWriteEn;
+    assign FifoRxReadEn_o = fifoRxReadEn;
+    
+    
+    assign RxFifoUpDnCnt_o = rxFifoUpDnCnt;
+    assign TxFifoUpDnCnt_o = txFifoUpDnCnt;
+    
+    
+    // //================================================================================
+    
+
+    RxFifoPtrSync #(
+        .WIDTH(8),
+        .STAGES(3)
+    )
+    rxFifoPtrSync (
+        .ClkFast_i(FifoRxWrClock_i),
+        .ClkSlow_i(FifoRxRdClock_i),
+        .RxFifoWrPtr_i(rxFifoWrPtr),
+        .RxFifoWrPtr_o(rxFifoWrPtrSync)
+    );
+
+    TxFifoPtrSync #(
+        .WIDTH(8),
+        .STAGES(3)
+    )
+    txFifoPtrSync (
+        .ClkFast_i(FifoTxWrClock_i),
+        .ClkSlow_i(FifoTxRdClock_i),
+        .TxFifoWrPtr_i(txFifoWrPtr),
+        .TxFifoWrPtr_o(txFifoWrPtrSync)
+    );
+
+    // RxFifoRstSync #(
+    //     .WIDTH(1),
+    //     .STAGES(3)
+    // )
+    // rxFifoRstSync (
+    //     .ClkFast_i(FifoRxWrClock_i),
+    //     .ClkSlow_i(FifoRxRdClock_i),
+    //     .RxFifoRst_i(FifoRxRst_i),
+    //     .RxFifoRst_o(rxFifoRstSync)
+    // );
+
+
+
+
+    
+    always @(posedge FifoRxRdClock_i) begin 
+        if (FifoRxRstRdPtr_i) begin 
+            readEnCnt <= 1'b0;
         end
         else begin 
-            readEnCnt <= 1'b0;
+            if (ToFifoRxReadVal_i) begin 
+                readEnCnt <= readEnCnt + 1'b1;
+            end
+            else begin 
+                readEnCnt <= 1'b0;
+            end
         end
     end
-end
-
-
-
-always @(posedge FifoTxWrClock_i) begin 
-    if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
-        fifoTxWriteEn <= 1'b1;
-    end
-    else begin 
-        fifoTxWriteEn <= 1'b0;
-    end
-end
-
-
-always @(posedge FifoTxRdClock_i ) begin 
-    if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
-        fifoTxReadEn <= 1'b1;
-    end
-    else begin 
-        fifoTxReadEn <= 1'b0;
-    end
-end
-
-
-always @(posedge FifoRxWrClock_i) begin 
-    if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
-        fifoRxWriteEn <= 1'b1;
-    end
-    else begin 
-        fifoRxWriteEn <= 1'b0;
-    end
-end
-
-
-always @(posedge FifoRxRdClock_i) begin 
-    if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo && readEnCnt < 1 ) begin 
-        fifoRxReadEn <= 1'b1;
-    end
-    else begin 
-        fifoRxReadEn <= 1'b0;
-    end
-end
-
-
-always @(posedge FifoTxWrClock_i ) begin 
-    if (FifoTxRst_i) begin 
-        txFifoWrPtr <= 8'h0;
-    end
-    else begin 
-        if (fifoTxWriteEn  ) begin 
-            txFifoWrPtr <= txFifoWrPtr + 1'b1;
+    
+    
+    
+    always @(posedge FifoTxWrClock_i) begin 
+        if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
+            fifoTxWriteEn <= 1'b1;
+        end
+        else begin 
+            fifoTxWriteEn <= 1'b0;
         end
     end
-end
-
-always @(posedge FifoTxRdClock_i ) begin 
-    if (FifoTxRst_i) begin 
-        txFifoRdPtr <= 8'h0;
-    end
-    else begin 
-        if (fifoTxReadEn ) begin 
-            txFifoRdPtr <= txFifoRdPtr + 1'b1;
+    
+    
+    always @(posedge FifoTxRdClock_i ) begin 
+        if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
+            fifoTxReadEn <= 1'b1;
+        end
+        else begin 
+            fifoTxReadEn <= 1'b0;
         end
     end
-end
-
-
-always @(posedge FifoRxWrClock_i) begin 
-    if (FifoRxRst_i) begin 
-        rxFifoWrPtr <= 8'h0;
+    
+    
+    always @(posedge FifoRxWrClock_i) begin 
+        if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
+            fifoRxWriteEn <= 1'b1;
+        end
+        else begin 
+            fifoRxWriteEn <= 1'b0;
+        end
     end
-    else begin
-        if (fifoRxWriteEn ) begin 
-            rxFifoWrPtr <= rxFifoWrPtr + 1'b1;
+    
+    
+    always @(posedge FifoRxRdClock_i) begin 
+        if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo && readEnCnt < 1 ) begin 
+            fifoRxReadEn <= 1'b1;
+        end
+        else begin 
+            fifoRxReadEn <= 1'b0;
         end
     end
-end
-
-always @(posedge FifoRxRdClock_i) begin 
-    if (FifoRxRst_i) begin 
-        rxFifoRdPtr <= 8'h0;
+    
+    
+    always @(posedge FifoTxWrClock_i ) begin 
+        if (FifoTxRstWrPtr_i) begin 
+            txFifoWrPtr <= 8'h0;
+        end
+        else begin 
+            if (fifoTxWriteEn  ) begin 
+                txFifoWrPtr <= txFifoWrPtr + 1'b1;
+            end
+        end
     end
-    else begin 
-        if (fifoRxReadEn ) begin 
-            rxFifoRdPtr <= rxFifoRdPtr + 1'b1;
+    
+    always @(posedge FifoTxRdClock_i ) begin 
+        if (FifoTxRst_i) begin 
+            txFifoRdPtr <= 8'h0;
+        end
+        else begin 
+            if (fifoTxReadEn ) begin 
+                txFifoRdPtr <= txFifoRdPtr + 1'b1;
+            end
         end
     end
-end
-
-
-always @(posedge FifoRxRdClock_i) begin 
-    if (FifoRxRst_i) begin 
-        rxFifoUpDnCnt <= 8'h0;
+    
+    
+    always @(posedge FifoRxWrClock_i) begin 
+        if (FifoRxRst_i) begin 
+            rxFifoWrPtr <= 8'h0;
+        end
+        else begin
+            if (fifoRxWriteEn ) begin 
+                rxFifoWrPtr <= rxFifoWrPtr + 1'b1;
+            end
+        end
     end
-    else begin 
-        rxFifoUpDnCnt <= rxFifoWrPtr - rxFifoRdPtr;
+    
+    always @(posedge FifoRxRdClock_i) begin 
+        if (FifoRxRstRdPtr_i) begin 
+            rxFifoRdPtr <= 8'h0;
+        end
+        else begin 
+            if (fifoRxReadEn ) begin 
+                rxFifoRdPtr <= rxFifoRdPtr + 1'b1;
+            end
+        end
     end
-end
-
-always @(posedge FifoTxRdClock_i) begin 
-    if (FifoTxRst_i) begin 
-        txFifoUpDnCnt <= 8'h0;
+    
+    
+    always @(posedge FifoRxRdClock_i) begin 
+        if (FifoRxRstRdPtr_i) begin 
+            rxFifoUpDnCnt <= 8'h0;
+        end
+        else begin 
+            rxFifoUpDnCnt <= rxFifoWrPtrSync - rxFifoRdPtr;
+        end
     end
-    else begin 
-        txFifoUpDnCnt <= txFifoWrPtr - txFifoRdPtr;
+    
+    always @(posedge FifoTxRdClock_i) begin 
+        if (FifoTxRst_i) begin 
+            txFifoUpDnCnt <= 8'h0;
+        end
+        else begin 
+            txFifoUpDnCnt <= txFifoWrPtrSync - txFifoRdPtr;
+        end
     end
-end
-
-
-
-
-
-// //================================================================================
-
-endmodule
+    
+    
+    
+    
+    
+    // //================================================================================
+    
+    endmodule

sources_1/new/DataFifo/RxFifoPtrSync.v

@@ -0,0 +1,47 @@
+module RxFifoPtrSync #(
+    parameter WIDTH = 8,
+    parameter STAGES = 3
+
+
+
+)
+(
+    input ClkFast_i,
+    input ClkSlow_i,
+    input [WIDTH-1:0] RxFifoWrPtr_i,
+
+    output [WIDTH-1:0] RxFifoWrPtr_o
+);
+
+
+
+
+//lauch registers 
+reg [WIDTH-1:0] rxFifoWrPtrReg;
+
+
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rxFifoWrPtrReg_c;
+
+
+
+assign RxFifoWrPtr_o = rxFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+always @(posedge ClkFast_i) begin
+    rxFifoWrPtrReg <= RxFifoWrPtr_i;
+end
+
+
+
+
+
+always @(posedge ClkSlow_i) begin
+    rxFifoWrPtrReg_c <= {rxFifoWrPtrReg_c[(STAGES-1)*WIDTH-1:0], rxFifoWrPtrReg};
+end
+
+
+
+
+
+endmodule

sources_1/new/DataFifo/RxFifoRstSync.v

@@ -0,0 +1,45 @@
+module RxFifoRstSync #(
+    parameter WIDTH = 1,
+    parameter STAGES = 3
+
+
+
+)
+(
+    input ClkFast_i,
+    input ClkSlow_i,
+    input [WIDTH-1:0] RxFifoRst_i,
+
+    output [WIDTH-1:0] RxFifoRst_o
+);
+
+
+
+
+
+//lauch registers 
+reg [WIDTH-1:0] rxFifoRstReg;
+
+
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rxFifoRstReg_c;
+
+
+assign RxFifoWrPtr_o = rxFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+
+always @(posedge ClkFast_i) begin
+    rxFifoRstReg <= RxFifoRst_i;
+end
+
+
+always @(posedge ClkSlow_i) begin
+    rxFifoRstReg_c <= {rxFifoRstReg_c[(STAGES-1)*WIDTH-1:0], rxFifoRstReg};
+end
+
+
+
+
+
+endmodule

sources_1/new/DataFifo/TxFifoPtrsync.v

@@ -0,0 +1,44 @@
+module TxFifoPtrSync #(
+    parameter WIDTH = 8,
+    parameter STAGES = 3
+
+
+
+)
+(
+    input ClkFast_i,
+    input ClkSlow_i,
+    input [WIDTH-1:0] TxFifoWrPtr_i,
+
+    output [WIDTH-1:0] TxFifoWrPtr_o
+);
+
+//lauch registers 
+reg [WIDTH-1:0] txFifoWrPtrReg;
+
+
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] txFifoWrPtrReg_c;
+
+
+
+assign TxFifoWrPtr_o = txFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+always @(posedge ClkFast_i) begin
+    txFifoWrPtrReg <= TxFifoWrPtr_i;
+end
+
+
+
+
+
+always @(posedge ClkSlow_i) begin
+    txFifoWrPtrReg_c <= {txFifoWrPtrReg_c[(STAGES-1)*WIDTH-1:0], txFifoWrPtrReg};
+end
+
+
+
+
+
+endmodule

sources_1/new/DspSmc/DspSmcModel.v

@@ -1,237 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date: 01.09.2022 15:03:04
-// Design Name: 
-// Module Name: DspModel
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-// 
-//
-//	2BYTES ADDRESING
-//	0->2->4->6
-//	
-//////////////////////////////////////////////////////////////////////////////////
-
-
-module	DspSmcModel
-#(
-	parameter	DwordsNum	=	5,
-	parameter	DataToClkRate	=	4,		//data changes every 4th clk negedge
-	parameter	SmcWrBaseAddr	=	4,		//data changes every 4th clk negedge
-	parameter	SmcRdBaseAddr	=	1,		//data changes every 4th clk negedge
-	parameter	[15:0]	SmcBaseData	=	16'h5,		//data changes every 4th clk negedge
-	parameter	Offset		=	2,		//data changes every 4th clk negedge
-	parameter	WordsNum	=	10		//data changes every 4th clk negedge
-)
-(
-	input	Clk120MHz_i,
-	input	RstN_i,
-	inout	[15:0]	SmcD_o,
-	output	[10:0]	SmcA_o,
-	output	SmcAwe_o,
-	output	SmcAmsN_o,
-	output	SmcAoe_o,
-	output	SmcAre_o,
-	output	[1:0]	SmcBe_o,
-	
-	input	Start_i
-);
-
-//================================================================================
-//  REG/WIRE
-	reg		smcAmsN;
-	reg		smcAoe;
-	reg		smcAwe;
-	reg		smcAre;
-	reg		[1:0]	smcBe;
-
-	reg	[1:0]	writeSetupDelay;
-	reg	[1:0]	writeAccessDelay;
-	reg	[1:0]	writeHoldDelay;
-	reg	[1:0]	transTurnDelay;
-	reg	[1:0]	readSetupDelay;
-	reg	[1:0]	readAccessDelay;
-	
-	reg	[24:0]	smcAddr;
-	reg	[15:0]	smcData;
-	
-	reg	[3:0]	currState;
-	
-	reg	[3:0]	wordsCnt;
-	
-	wire	txDone;
-//================================================================================
-//  LOCALPARAM
-
-	localparam	IDLE			=	3'h0;
-	localparam	WriteSetup		=	3'h1;
-	localparam	WriteAccess		=	3'h2;
-	localparam	WriteHold		=	3'h3;
-	localparam	TramsTurn		=	3'h4;
-	localparam	ReadSetup		=	3'h5;
-	localparam	ReadAccess		=	3'h6;
-	localparam	ReadHold		=	3'h7;
-	
-	
-//================================================================================
-//  ASSIGNMENTS	
-	assign	SmcA_o		=	smcAddr;
-	assign	SmcD_o		=	(!SmcAre_o)?	15'bz:smcData;
-	assign	SmcAwe_o	=	smcAwe;
-	assign	SmcAmsN_o	=	smcAmsN;
-	assign	SmcAoe_o	=	smcAoe;
-	assign	SmcAre_o	=	smcAre;
-	assign	SmcBe_o		=	smcBe;
-	
-	assign	txDone	=	wordsCnt==WordsNum-1;
-//================================================================================
-//  CODING
-
-always	@(posedge	Clk120MHz_i	or	negedge	RstN_i)	begin
-	if	(!RstN_i)	begin
-		wordsCnt	<=	0;
-	end	else	begin
-		if	(currState	==	TramsTurn)	begin
-			if	(smcAmsN)	begin
-				if	(wordsCnt!=WordsNum-1)	begin
-					wordsCnt	<=	wordsCnt+4'd1;
-				end	else	begin
-					wordsCnt	<=	0;
-				end
-			end
-		end	
-	end
-end
-
-always	@(negedge	Clk120MHz_i	or	negedge	RstN_i)	begin
-	if	(!RstN_i)	begin
-		currState	<=	0;
-		smcAddr	<=	0;
-		smcData	<=	0;
-		smcAmsN	<=	1'b1;
-		smcAoe	<=	1'b1;
-		smcAwe	<=	1'b1;
-		smcAre	<=	1'b1;
-		smcBe	<=	2'b00;
-		writeSetupDelay	<=	2'b01;
-		writeAccessDelay<=	4'b01;
-		writeHoldDelay	<=	2'b01;
-		transTurnDelay	<=	2'b01;
-		readSetupDelay	<=	3'b01;
-		readAccessDelay	<=	5'b01;
-	end	else	begin
-		case(currState)
-		IDLE:		begin
-						if	(Start_i)	begin
-							currState	<=	WriteSetup;
-							smcAmsN	<=	1'b0;
-							smcAddr	<=	wordsCnt;
-							smcData	<=	wordsCnt;
-							smcAmsN	<=	1'b0;
-							smcAoe	<=	1'b1;
-							smcAre	<=	1'b1;
-							smcAwe	<=	1'b1;
-							smcBe	<=	2'b00;
-						end	else	begin
-							currState	<=	IDLE;
-						end
-					end
-					
-		WriteSetup:	begin
-						if	(writeSetupDelay[0])	begin
-							currState	<=	WriteAccess;
-							smcAwe	<=	1'b0;
-							writeSetupDelay	<=	2'b01;
-						end	else	begin
-							currState	<=	WriteSetup;
-							writeSetupDelay	<=	writeSetupDelay<<1;
-						end	
-					end
-					
-		WriteAccess:begin
-						if	(writeAccessDelay[0])	begin
-							currState	<=	WriteHold;
-							writeAccessDelay<=	4'b0001;
-							smcAwe	<=	1'b1;
-						end	else	begin
-							currState	<=	WriteAccess;	
-							writeAccessDelay<=	writeAccessDelay<<1;
-						end
-					end
-					
-		WriteHold	:begin
-						if	(writeHoldDelay[0])	begin
-							currState	<=	TramsTurn;
-							writeHoldDelay<=	2'b01;
-							smcAmsN	<=	1'b1;
-						end	else	begin
-							currState	<=	WriteHold;	
-							writeHoldDelay<=	writeHoldDelay<<1;
-						end
-					end
-					
-		TramsTurn	:begin
-							if	(transTurnDelay[0])	begin
-								if	(!txDone)	begin
-									currState	<=	WriteSetup;
-									smcAmsN	<=	1'b0;
-									smcAddr	<=	wordsCnt;
-									smcData	<=	wordsCnt;
-									smcAmsN	<=	1'b0;
-									smcAoe	<=	1'b1;
-									smcAre	<=	1'b1;
-									smcAwe	<=	1'b1;
-									smcBe	<=	2'b00;
-								end	else	begin
-									currState	<=	ReadSetup;
-									transTurnDelay<=	2'b01;
-									smcAmsN	<=	1'b0;
-									smcAoe	<=	1'b0;
-									smcAddr	<=	SmcRdBaseAddr;
-								end
-							end	else	begin
-									currState	<=	TramsTurn;	
-									transTurnDelay<=	transTurnDelay<<1;
-							end
-					end
-		ReadSetup	:begin
-						if	(readSetupDelay[0])	begin
-							currState	<=	ReadAccess;
-							readSetupDelay<=	3'b001;
-							smcAre	<=	1'b0;
-						end	else	begin
-							currState		<=	ReadSetup;	
-							readSetupDelay	<=	readSetupDelay<<1;
-						end
-					end
-		ReadAccess	:begin
-						if	(readAccessDelay[0])	begin
-							currState	<=	ReadHold;
-							readAccessDelay<=	5'b00001;
-							smcAre	<=	1'b1;
-						end	else	begin
-							currState		<=	ReadAccess;	
-							readAccessDelay	<=	readAccessDelay<<1;
-						end
-					end
-		ReadHold	:begin
-						currState	<=	IDLE;
-						smcAmsN	<=1'b1;
-						smcAoe	<=	1'b1;
-					end
-					
-		endcase
-	end
-end
-endmodule

sources_1/new/DspSmc/MasterFpgaTop.v

@@ -1,78 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date: 10.10.2018 01:07:38
-// Design Name: 
-// Module Name: sram_ctrl2
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-// 
-//////////////////////////////////////////////////////////////////////////////////
-
-
-module	MasterFpgaTop
-(
-	input	Clk_i,                       
-	input	RstN_i,                     
-	input	ForceRstN_i,                     
-
-	input	[15:0]	SmcD_i,
-	input	[24:0]	SmcA_i,
-	input	SmcAwe_i,
-	input	SmcAmsN_i,
-	input	SmcAoe_i,	
-	input	SmcAre_i,	
-	input	[1:0]	SmcBe_i,
-	
-	output	[15:0]	Data_o,
-	output	[24:0]	Addr_o,
-	output	Val_o
-);
-
-//================================================================================
-//  REG/WIRE
-	
-	wire	[24:0]	sramSmcAddr;
-	wire	[31:0]	sramSmcData;
-	wire	sramVal;
-
-//================================================================================
-//  LOCALPARAM
-	
-//================================================================================
-//  ASSIGNMENTS	
-
-//================================================================================
-//  CODING
-	
-
-SramRx	SramRx
-(
-	.Clk_i		(Clk_i	),
-	.RstN_i		(RstN_i),
-	.ForceRstN_i(ForceRstN_i),
-
-	.SmcD_i		(SmcD_i),
-	.SmcA_i		(SmcA_i),
-	.SmcAwe_i	(SmcAwe_i),
-	.SmcAmsN_i	(SmcAmsN_i),
-	.SmcAoe_i	(SmcAoe_i),
-	.SmcAre_i	(SmcAre_i),
-	.SmcBe_i	(SmcBe_i),
-	
-	.Data_o		(sramSmcData),
-	.Addr_o		(sramSmcAddr),
-	.Val_o		(sramVal)
-);
-
-endmodule

sources_1/new/DspSmc/MasterFpgaTopTb.v

@@ -1,102 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date: 10.10.2018 01:07:38
-// Design Name: 
-// Module Name: sram_ctrl2
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-// 
-//////////////////////////////////////////////////////////////////////////////////
-
-
-module	MasterFpgaTopTb
-(
-	input	Clk_i
-);
-
-//================================================================================
-//  REG/WIRE
-	reg	clk120Dsp;
-	reg	clk120Fpga;
-	reg	start;
-	reg	rstN;
-	reg	ForceRstN;
-	
-	wire	[15:0]	data;
-	wire	[24:0]	addr;
-	wire	awe;
-	wire	amsn;
-	wire	aoe;
-	wire	are;
-	wire	[1:0]	be;
-//================================================================================
-//  LOCALPARAM
-	
-//================================================================================
-//  ASSIGNMENTS	
-	always	#4.2	clk120Dsp	=	~clk120Dsp;
-	always	#4.2	clk120Fpga	=	~clk120Fpga;
-//================================================================================
-//  CODING
-
-initial	begin
-	rstN		=	0;
-	ForceRstN	=	0;
-	clk120Dsp	=	1;
-	start		=	0;
-	clk120Fpga	=	0;
-	#20
-	rstN		=	1;
-	ForceRstN	=	1;
-	#100
-	start	=	1;
-	#4.2
-	start	=	0;
-	
-end
-
-DspSramModel	DspSramInterface
-(
-	.Clk120MHz_i	(clk120Dsp),
-	.RstN_i			(rstN),
-	.SmcD_o			(data),
-	.SmcA_o			(addr),
-	.SmcAwe_o		(awe),
-	.SmcAmsN_o		(amsn),
-	.SmcAoe_o		(aoe),
-	.SmcAre_o		(are),
-	.SmcBe_o		(be),
-	
-	.Start_i		(start)
-);
-
-MasterFpgaTop	MasterFpgaTop
-(
-	.Clk_i		(clk120Fpga),
-	.RstN_i		(rstN),
-	.ForceRstN_i(ForceRstN),
-
-	.SmcD_i		(data),
-	.SmcA_i		(addr),
-	.SmcAwe_i	(awe),
-	.SmcAmsN_i	(amsn),
-	.SmcAoe_i	(aoe),
-	.SmcAre_i	(are),
-	.SmcBe_i	(be),
-	
-	.Data_o		(),
-	.Addr_o		(),
-	.Val_o		()
-);
-endmodule

sources_1/new/DspSmc/S5443_3TopTb.v

@@ -1,113 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date: 10.10.2018 01:07:38
-// Design Name: 
-// Module Name: sram_ctrl2
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-// 
-//////////////////////////////////////////////////////////////////////////////////
-
-
-module	S5443_3TopTb
-(
-	input	Clk_i
-);
-
-//================================================================================
-//  REG/WIRE
-	reg	clk123Dsp;
-	wire	start;
-	reg	rstN;
-	reg	ForceRstN;
-	
-	wire	[15:0]	data;
-	wire	[10:0]	addr;
-	wire	awe;
-	wire	amsn;
-	wire	aoe;
-	wire	are;
-	wire	[1:0]	be;
-	
-	reg	[31:0]	tbCnt;
-//================================================================================
-//  LOCALPARAM
-	
-//================================================================================
-//  ASSIGNMENTS	
-	always	#8.13	clk123Dsp	=	~clk123Dsp;
-	assign	start	=	(tbCnt==50||tbCnt==51);
-//================================================================================
-//  CODING
-
-initial	begin
-	rstN		=	0;
-	ForceRstN	=	0;
-	clk123Dsp	=	1;
-	#20
-	rstN		=	1;
-	ForceRstN	=	1;
-	
-end
-
-always	@(posedge	clk123Dsp)	begin
-	if	(rstN)	begin
-		tbCnt	<=	tbCnt+32'd1;
-	end	else	begin
-		tbCnt	<=	0;
-	end
-end
-
-DspSmcModel	DspSmcModel
-(
-	.Clk120MHz_i	(clk123Dsp),
-	.RstN_i			(rstN),
-	.SmcD_o			(data),
-	.SmcA_o			(addr),
-	.SmcAwe_o		(awe),
-	.SmcAmsN_o		(amsn),
-	.SmcAoe_o		(aoe),
-	.SmcAre_o		(are),
-	.SmcBe_o		(be),
-	
-	.Start_i		(start)
-);
-
-S5443_3Top S5443_3Top
-(
-	.Clk123_i	(clk123Dsp),
-	.SmcAddr_i	(addr),
-	.SmcData_i	(data),
-    
-	.SmcAwe_i	(awe),
-	.SmcAmsN_i	(amsn),
-	
-	.SmcAre_i	(are),
-	.SmcBe_i	(be),
-	.SmcAoe_i	(aoe),
-	.LD_i		(),
-	
-	.Led_o		(),
-	
-	.Mosi0_o	(),
-	.Mosi1_o	(),
-	.Mosi2_o	(),
-	.Mosi3_o	(),
-	.Ss_o		(),
-	.SsFlash_o	(),
-	.Sck_o		(),
-	.SpiRst_o	(),
-	.LD_o		()
-);
-endmodule

sources_1/new/DspSmc/SmcRx.v

@@ -1,101 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date: 10.10.2018 01:07:38
-// Design Name: 
-// Module Name: sram_ctrl2
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-// 
-//////////////////////////////////////////////////////////////////////////////////
-
-
-module	SmcRx
-#(
-	parameter	DataInOutWidth	=	16,
-	parameter	AddrWidth		=	12
-)
-(
-	input	Clk_i,                       
-	input	Rst_i,                         
-
-	inout	[DataInOutWidth-1:0]	SmcD_i,
-	input	[AddrWidth-2:0]	SmcA_i,
-	input	SmcAwe_i,
-	input	SmcAmsN_i,
-	input	SmcAoe_i,
-	input	SmcAre_i,	
-	input	[1:0]	SmcBe_i,	
-	
-	input	[DataInOutWidth-1:0]	AnsData_i,
-	
-	output	[1:0]	Be_o,
-	output	[DataInOutWidth-1:0]	Data_o,
-	output	[AddrWidth-1:0]	Addr_o,
-	output	Val_o
-);
-
-//================================================================================
-//  REG/WIRE
-	
-	
-	reg	[DataInOutWidth-1:0]	inDataReg;
-	reg	[AddrWidth-1:0]			addrReg;
-	reg	valReg;
-	
-	reg	[DataInOutWidth-1:0]	outDataReg;
-	reg	[1:0]	beReg;
-//================================================================================
-//  LOCALPARAM
-
-//================================================================================
-//  ASSIGNMENTS	
-	assign	Data_o	=	inDataReg;
-	assign	Addr_o	=	addrReg;
-	assign	Val_o	=	valReg;
-	assign	Be_o	=	beReg;
-	
-	// assign	SmcD_i	=	(!SmcAre_i && !SmcAoe_i)?AnsData_i:16'bz;
-//================================================================================
-//  CODING
-	
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(!SmcAmsN_i)	begin
-			if	(!SmcAwe_i)	begin
-				addrReg	<=	{SmcA_i,1'b0};
-				inDataReg	<=	SmcD_i;
-				valReg	<=	1'b1;
-				beReg	<=	SmcBe_i;
-			end	else	begin
-				valReg	<=	0;
-			end
-			
-			if	(!SmcAre_i && !SmcAoe_i)	begin
-				addrReg		<=	{SmcA_i,1'b0};
-				outDataReg	<=	AnsData_i;
-			end	
-		end
-		else	begin
-			valReg	<=	0;
-		end
-	end	else	begin
-		inDataReg	<=	0;
-		outDataReg	<=	0;
-		addrReg	<=	0;
-		valReg		<=	0;
-		beReg	<=	2'b0;
-	end
-end
-
-endmodule

sources_1/new/MMCM/ClkDivSync.v

@@ -0,0 +1,44 @@
+module ClkDivSync #(
+    parameter WIDTH = 4,
+    parameter STAGES = 3
+
+
+
+)
+(
+    input ClkFast_i,
+    input ClkSlow_i,
+    input [WIDTH-1:0] ClkDiv_i,
+
+    output [WIDTH-1:0] ClkDiv_o
+);
+
+
+//lauch registers 
+reg [WIDTH-1:0] clkDivReg;
+
+// capture registers
+(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] clkDivReg_c;
+
+
+assign ClkDiv_o = clkDivReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+
+
+always @(posedge ClkFast_i) begin
+    clkDivReg <= ClkDiv_i;
+end
+
+
+
+
+
+always @(posedge ClkSlow_i) begin
+    clkDivReg_c <= {clkDivReg_c[(STAGES-1)*WIDTH-1:0], clkDivReg};
+end
+
+
+
+
+
+endmodule

sources_1/new/MMCM/MmcmWrapper.v

@@ -6,6 +6,7 @@ module MmcmWrapper
 (
    input	Clk_i,
    input	Rst_i,
+   input Rst80_i,
    input [7:0] BaudRate0_i,
    input [7:0] BaudRate1_i,
    input [7:0] BaudRate2_i,
@@ -15,7 +16,7 @@ module MmcmWrapper
    input [7:0] BaudRate6_i,
 
 
-
+   output   Clk80_o,
 	output 	[SpiNum-1:0]	SpiClk_o
    
 );
@@ -39,6 +40,7 @@ wire [SpiNum-1:0] clkMan;
 
 wire [0:2] clkNum [SpiNum-1:0];
 wire [0:3] clkDiv [SpiNum-1:0];
+wire [0:3] clkDivSync [SpiNum-1:0];
 wire [SpiNum-1:0] clkCh; 
 wire [SpiNum-1:0] spiClk;
 
@@ -88,81 +90,93 @@ wire [SpiNum-1:0] spiClk;
    assign SpiClk_o[6] = spiClk[6];
 
    assign Clk100_o = clk0out;
+   assign Clk80_o = clk1out;
 
 
 
-//================================================================================
-//	LOCALPARAMS
-//================================================================================
-
-
-//================================================================================
-//	CODING
-//================================================================================
-
-
-
+   //================================================================================
+   //	LOCALPARAMS
+   //================================================================================
    
-
-genvar i;
-
-generate
-   for (i=0; i < SpiNum; i = i +1) begin : ClkGen
-      ClkGen ClkGen_inst (
-         .Clk_i(clk1out),
-         .ClkDiv_i(clkDiv[i]),
-         .Rst_i(Rst_i),
-         .Clk_o(clkMan[i])
-      );
-
-      clkOutMMCM clkOutMMCM_inst (
-         .Rst_i(Rst_i),
-         .clkNum(clkNum[i]),
-         .clk0out(clk0out),
-         .clk1out(clk1out),
-         .clk2out(clk2out),
-         .clk3out(clk3out),
-         .clk4out(clk4out),
-         .clk5out(clk5out),
-         .clk6out(clk6out),
-         .ClkOutMMCM_o(clkOutMMCM[i])
-      );
-
-      ClkCh ClkCh_inst (
-         .Rst_i(Rst_i),
-         .clkCh(clkCh[i]),
-         .clkOutMMCM(clkOutMMCM[i]),
-         .clkMan(clkMan[i]),
-         .SpiClk_o(spiClk[i])
-      );
-   end
-
-
-endgenerate
-
-
-
-
-
-  ClkDiv ClkDiv_inst
-   (
-    // Clock out ports
-    .clk_out1(clk0out),     //100 MHz
-    .clk_out2(clk1out),     // 80 MHz
-    .clk_out3(clk2out),     // 70 MHz
-    .clk_out4(clk3out),     // 60MHz
-    .clk_out5(clk4out),     // 50MHz
-    .clk_out6(clk5out),     // 40MHz
-    .clk_out7(clk6out),     // 30MHz 
-    // Status and control signals
-    .reset(Rst_i), // input reset
-    .locked(locked),       // output locked
-   // Clock in ports
-    .clk_in1(Clk_i));      // input clk_in1
-
-
-
-
-
-
-endmodule
+   
+   //================================================================================
+   //	CODING
+   //================================================================================
+   
+   
+   
+      
+   genvar i;
+   
+   generate
+      for (i=0; i < SpiNum; i = i +1) begin : ClkGen
+         ClkGen ClkGen_inst (
+            .Clk_i(clk1out),
+            .ClkDiv_i(clkDivSync[i]),
+            .Rst_i(Rst80_i),
+            .Clk_o(clkMan[i])
+         );
+
+         ClkDivSync #(
+            .WIDTH(4),
+            .STAGES(3)
+         )(
+            .ClkFast_i(Clk_i),
+            .ClkSlow_i(clk1out),
+            .ClkDiv_i(clkDiv[i]),
+            .ClkDiv_o(clkDivSync[i])
+
+         );
+         
+
+         clkOutMMCM clkOutMMCM_inst (
+            .Rst_i(Rst_i),
+            .clkNum(clkNum[i]),
+            .clk0out(clk0out),
+            .clk1out(clk1out),
+            .clk2out(clk2out),
+            .clk3out(clk3out),
+            .clk4out(clk4out),
+            .clk5out(clk5out),
+            .clk6out(clk6out),
+            .ClkOutMMCM_o(clkOutMMCM[i])
+         );
+   
+         ClkCh ClkCh_inst (
+            .Rst_i(Rst_i),
+            .clkCh(clkCh[i]),
+            .clkOutMMCM(clkOutMMCM[i]),
+            .clkMan(clkMan[i]),
+            .SpiClk_o(spiClk[i])
+         );
+      end
+   
+   
+   endgenerate
+   
+   
+   
+   
+   
+   ClkDiv ClkDiv_inst
+    (
+     // Clock out ports
+     .clk_out1(clk0out),     //100 MHz
+     .clk_out2(clk1out),     // 80 MHz
+     .clk_out3(clk2out),     // 70 MHz
+     .clk_out4(clk3out),     // 60MHz
+     .clk_out5(clk4out),     // 50MHz
+   //   .clk_out6(clk5out),     // 40MHz
+     .clk_out7(clk6out),     // 30MHz 
+     // Status and control signals
+     .reset(Rst_i), // input reset
+     .locked(locked),       // output locked
+    // Clock in ports
+     .clk_in1(Clk_i));      // input clk_in1
+   
+   
+      
+   
+   
+   
+   endmodule

sources_1/new/Mux/DataMuxer.v

@@ -66,13 +66,13 @@ module DataMuxer
 //================================================================================
 //	REG/WIRE
 //================================================================================
-	wire	requestToFifo0	=	((SmcAddr_i==Fifo0WriteLsbAddr||SmcAddr_i==Fifo0WriteMsbAddr)|| (SmcAddr_i==Fifo0ReadLsbAddr||SmcAddr_i==Fifo0ReadMsbAddr));
-	wire	requestToFifo1	=	((SmcAddr_i==Fifo1WriteLsbAddr||SmcAddr_i==Fifo1WriteMsbAddr)|| (SmcAddr_i==Fifo1ReadLsbAddr||SmcAddr_i==Fifo1ReadMsbAddr));
-	wire	requestToFifo2	=	((SmcAddr_i==Fifo2WriteLsbAddr||SmcAddr_i==Fifo2WriteMsbAddr)|| (SmcAddr_i==Fifo2ReadLsbAddr||SmcAddr_i==Fifo2ReadMsbAddr));
-	wire	requestToFifo3	=	((SmcAddr_i==Fifo3WriteLsbAddr||SmcAddr_i==Fifo3WriteMsbAddr)|| (SmcAddr_i==Fifo3ReadLsbAddr||SmcAddr_i==Fifo3ReadMsbAddr));
-	wire	requestToFifo4	=	((SmcAddr_i==Fifo4WriteLsbAddr||SmcAddr_i==Fifo4WriteMsbAddr)|| (SmcAddr_i==Fifo4ReadLsbAddr||SmcAddr_i==Fifo4ReadMsbAddr));
-	wire	requestToFifo5	=	((SmcAddr_i==Fifo5WriteLsbAddr||SmcAddr_i==Fifo5WriteMsbAddr)|| (SmcAddr_i==Fifo5ReadLsbAddr||SmcAddr_i==Fifo5ReadMsbAddr));
-	wire	requestToFifo6	=	((SmcAddr_i==Fifo6WriteLsbAddr||SmcAddr_i==Fifo6WriteMsbAddr)|| (SmcAddr_i==Fifo6ReadLsbAddr||SmcAddr_i==Fifo6ReadMsbAddr));
+	wire	requestToFifo0	=((SmcAddr_i==Fifo0WriteLsbAddr||SmcAddr_i==Fifo0WriteMsbAddr)|| (SmcAddr_i==Fifo0ReadLsbAddr||SmcAddr_i==Fifo0ReadMsbAddr));
+	wire	requestToFifo1	=((SmcAddr_i==Fifo1WriteLsbAddr||SmcAddr_i==Fifo1WriteMsbAddr)|| (SmcAddr_i==Fifo1ReadLsbAddr||SmcAddr_i==Fifo1ReadMsbAddr));
+	wire	requestToFifo2	=((SmcAddr_i==Fifo2WriteLsbAddr||SmcAddr_i==Fifo2WriteMsbAddr)|| (SmcAddr_i==Fifo2ReadLsbAddr||SmcAddr_i==Fifo2ReadMsbAddr));
+	wire	requestToFifo3	=((SmcAddr_i==Fifo3WriteLsbAddr||SmcAddr_i==Fifo3WriteMsbAddr)|| (SmcAddr_i==Fifo3ReadLsbAddr||SmcAddr_i==Fifo3ReadMsbAddr));
+	wire	requestToFifo4	=((SmcAddr_i==Fifo4WriteLsbAddr||SmcAddr_i==Fifo4WriteMsbAddr)|| (SmcAddr_i==Fifo4ReadLsbAddr||SmcAddr_i==Fifo4ReadMsbAddr));
+	wire	requestToFifo5	=((SmcAddr_i==Fifo5WriteLsbAddr||SmcAddr_i==Fifo5WriteMsbAddr)|| (SmcAddr_i==Fifo5ReadLsbAddr||SmcAddr_i==Fifo5ReadMsbAddr));
+	wire	requestToFifo6	=((SmcAddr_i==Fifo6WriteLsbAddr||SmcAddr_i==Fifo6WriteMsbAddr)|| (SmcAddr_i==Fifo6ReadLsbAddr||SmcAddr_i==Fifo6ReadMsbAddr));
 	
 	wire	requestToFifo	=	(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6);
 //================================================================================
@@ -87,88 +87,88 @@ module DataMuxer
 //	CODING
 //================================================================================
 
-always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
-	if	(Rst_i)	begin
-		ToRegMapVal_o	<=	1'b0;
-		ToRegMapData_o	<=	16'h0;
-		ToRegMapAddr_o	<=	12'h0;
-		
-		ToFifoVal_o		<=	7'h0;
-		ToFifoData_o	<=	0;
-	end	else	begin
-		if	(requestToFifo)	begin	
-			case(SmcAddr_i)	
-				Fifo0WriteLsbAddr:	begin
-									ToFifoVal_o[0]	<=	1'b0;
-									ToFifoData_o[CmdRegWidth*0+:CmdRegWidth]	<=	SmcData_i;
-								end
-				Fifo0WriteMsbAddr:	begin
-									ToFifoVal_o[0]	<=	SmcVal_i;
-									ToFifoData_o[CmdRegWidth*1+:CmdRegWidth]	<=	SmcData_i;
-								end
-								
-				Fifo1WriteLsbAddr:	begin
-									ToFifoVal_o[1]	<=	1'b0;
-									ToFifoData_o[CmdRegWidth*2+:CmdRegWidth]	<=	SmcData_i;
-								end
-				Fifo1WriteMsbAddr:	begin
-									ToFifoVal_o[1]	<=	SmcVal_i;
-									ToFifoData_o[CmdRegWidth*3+:CmdRegWidth]	<=	SmcData_i;
-								end
-								
-				Fifo2WriteLsbAddr:	begin
-									ToFifoVal_o[2]	<=	1'b0;
-									ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
-								end
-				Fifo2WriteMsbAddr:	begin
-									ToFifoVal_o[2]	<=	SmcVal_i;
-									ToFifoData_o[CmdRegWidth*5+:CmdRegWidth]	<=	SmcData_i;
-								end
-								
-				Fifo3WriteLsbAddr:	begin
-									ToFifoVal_o[3]	<=	1'b0;
-									ToFifoData_o[CmdRegWidth*6+:CmdRegWidth]	<=	SmcData_i;
-								end
-				Fifo3WriteMsbAddr:	begin
-									ToFifoVal_o[3]	<=	SmcVal_i;
-									ToFifoData_o[CmdRegWidth*7+:CmdRegWidth]	<=	SmcData_i;
-								end
-								
-				Fifo4WriteLsbAddr:	begin
-									ToFifoVal_o[4]	<=	1'b0;
-									ToFifoData_o[CmdRegWidth*8+:CmdRegWidth]	<=	SmcData_i;
-								end
-				Fifo4WriteMsbAddr:	begin
-									ToFifoVal_o[4]	<=	SmcVal_i;
-									ToFifoData_o[CmdRegWidth*9+:CmdRegWidth]	<=	SmcData_i;
-								end
-								
-				Fifo5WriteLsbAddr:	begin
-									ToFifoVal_o[5]	<=	1'b0;
-									ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
-								end
-				Fifo5WriteMsbAddr:	begin
-									ToFifoVal_o[5]	<=	SmcVal_i;
-									ToFifoData_o[CmdRegWidth*11+:CmdRegWidth]	<=	SmcData_i;
-								end
-								
-				Fifo6WriteLsbAddr:	begin
-									ToFifoVal_o[6]	<=	1'b0;
-									ToFifoData_o[CmdRegWidth*12+:CmdRegWidth]	<=	SmcData_i;
-								end
-				Fifo6WriteMsbAddr:	begin
-									ToFifoVal_o[6]	<=	SmcVal_i;
-									ToFifoData_o[CmdRegWidth*13+:CmdRegWidth]	<=	SmcData_i;
-								end
-			endcase
-			ToRegMapAddr_o	<=	0;
-		end	else	begin
-			ToRegMapVal_o	<=	SmcVal_i;
+	always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
+		if	(Rst_i)	begin
+			ToRegMapVal_o	<=	1'b0;
+			ToRegMapData_o	<=	16'h0;
+			ToRegMapAddr_o	<=	12'h0;
+			
 			ToFifoVal_o		<=	7'h0;
-			ToRegMapData_o	<=	SmcData_i;
-			ToRegMapAddr_o	<=	SmcAddr_i;
 			ToFifoData_o	<=	0;
+		end	else	begin
+			if	(requestToFifo)	begin	
+				case(SmcAddr_i)	
+					Fifo0WriteLsbAddr:	begin
+										ToFifoVal_o[0]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*0+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo0WriteMsbAddr:	begin
+										ToFifoVal_o[0]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*1+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo1WriteLsbAddr:	begin
+										ToFifoVal_o[1]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*2+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo1WriteMsbAddr:	begin
+										ToFifoVal_o[1]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*3+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo2WriteLsbAddr:	begin
+										ToFifoVal_o[2]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo2WriteMsbAddr:	begin
+										ToFifoVal_o[2]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*5+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo3WriteLsbAddr:	begin
+										ToFifoVal_o[3]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*6+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo3WriteMsbAddr:	begin
+										ToFifoVal_o[3]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*7+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo4WriteLsbAddr:	begin
+										ToFifoVal_o[4]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*8+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo4WriteMsbAddr:	begin
+										ToFifoVal_o[4]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*9+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo5WriteLsbAddr:	begin
+										ToFifoVal_o[5]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo5WriteMsbAddr:	begin
+										ToFifoVal_o[5]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*11+:CmdRegWidth]	<=	SmcData_i;
+									end
+									
+					Fifo6WriteLsbAddr:	begin
+										ToFifoVal_o[6]	<=	1'b0;
+										ToFifoData_o[CmdRegWidth*12+:CmdRegWidth]	<=	SmcData_i;
+									end
+					Fifo6WriteMsbAddr:	begin
+										ToFifoVal_o[6]	<=	SmcVal_i;
+										ToFifoData_o[CmdRegWidth*13+:CmdRegWidth]	<=	SmcData_i;
+									end
+				endcase
+				ToRegMapAddr_o	<=	0;
+			end	else	begin
+				ToRegMapVal_o	<=	SmcVal_i;
+				ToFifoVal_o		<=	7'h0;
+				ToRegMapData_o	<=	SmcData_i;
+				ToRegMapAddr_o	<=	SmcAddr_i;
+				ToFifoData_o	<=	0;
+			end
 		end
 	end
-end
-endmodule
+	endmodule

sources_1/new/RstSync/RstSync.v

@@ -1,30 +0,0 @@
-
-module RstSync 
-(
-    input	Clk_i,
-    input	Rst_i,
-
-	output	Rst_o
-);
-//================================================================================
-//	REG/WIRE
-//================================================================================
-	reg	rstReg0;
-	reg	rstReg1;
-//================================================================================
-//	ASSIGNMENTS
-//================================================================================
-	assign	Rst_o	=	rstReg1;
-//================================================================================
-//	LOCALPARAMS
-//================================================================================
-
-//================================================================================
-//	CODING
-//================================================================================
-
-always	@(posedge	Clk_i)	begin
-	rstReg0	<=	Rst_i;
-	rstReg1	<=	rstReg0;
-end
-endmodule

sources_1/new/S5443_3_tb.v

@@ -30,13 +30,12 @@ always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
     S5443_3Top uut (
         .Clk123_i(Clk_i), 
         .SmcAddr_i(SmcAddr_i), 
-        .SmcData_i(smcData), 
+        .SmcData_io(smcData), 
         .SmcAwe_i(SmcAwe_i), 
         .SmcAmsN_i(SmcAmsN_i), 
         .SmcAre_i(SmcAre_i), 
         .SmcBe_i(SmcBe_i), 
         .SmcAoe_i(SmcAoe_i), 
-        .Ld_i(Ld_i), 
         .Led_o(), 
         .Mosi0_o(), 
         .Mosi1_io(), 

sources_1/new/SpiR/SPIm.v

@@ -2,12 +2,12 @@ module SPIm (
     input Clk_i,
     input Rst_i,
     input Start_i,
-    input CPHA_i,
-    input [31:0] SPIdata,
-    input SELST_i,
+    input ClockPhase_i,
+    input [31:0] SpiData_i,
+    input SelSt_i,
     input [1:0] WidthSel_i,
-    input  LAG_i,
-    input  LEAD_i,
+    input  Lag_i,
+    input  Lead_i,
     input EndianSel_i,
     input [5:0] Stop_i,
     input PulsePol_i,
@@ -24,512 +24,512 @@ module SPIm (
 //	REG/WIRE
 //================================================================================
 
-reg startFlag;
-reg startR;
-reg [31:0] trCnt;
-reg valReg;
-reg valToRxFifo1;
-reg lineBusy;
-reg [5:0] ssCnt;
-reg Ss;
-reg [31:0]spiDataR;
-reg oldDataFlag;
-
-reg ssR;
-reg SSR;
-reg [31:0] mosiReg0;
-reg [5:0] ssNum;
-reg [2:0] delayCnt;
-reg stopFlag;
-
-wire ssPol = SELST_i ? Ss : ~Ss;
-
-
-//================================================================================
-//  ASSIGNMENTS
-//================================================================================
-
-
-assign Ss_o = ssPol; 
-
-//================================================================================
-//	CODING
-//================================================================================
-
-always @(*) begin 
-    if (Start_i) begin  
-        Val_o = valReg;
-    end
-    else begin 
-        Val_o = 1'b0;
-    end
-end
-
-
-always @(*) begin 
-    if (SELST_i) begin 
-        if (!Ss_o) begin 
-            lineBusy = 1'b1;
+    reg startFlag;
+    reg startR;
+    reg [31:0] trCnt;
+    reg valReg;
+    reg valToRxFifo1;
+    reg lineBusy;
+    reg [5:0] ssCnt;
+    reg Ss;
+    reg [31:0]spiDataR;
+    reg oldDataFlag;
+    
+    reg ssR;
+    reg SSR;
+    reg [31:0] mosiReg0;
+    reg [5:0] ssNum;
+    reg [2:0] delayCnt;
+    reg stopFlag;
+    
+    wire ssPol = SelSt_i ? Ss : ~Ss;
+    
+    
+    //================================================================================
+    //  ASSIGNMENTS
+    //================================================================================
+    
+    
+    assign Ss_o = ssPol; 
+    
+    //================================================================================
+    //	CODING
+    //================================================================================
+    
+    always @(*) begin 
+        if (Start_i) begin  
+            Val_o = valReg;
         end
         else begin 
-            lineBusy = 1'b0;
+            Val_o = 1'b0;
         end
     end
-    else begin 
-        if (Ss_o) begin 
-            lineBusy = 1'b1;
+    
+    
+    always @(*) begin 
+        if (SelSt_i) begin 
+            if (!Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
         end
         else begin 
-            lineBusy = 1'b0;
+            if (Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
         end
     end
-end
-
-
-
-always @(posedge Clk_i) begin
-    if (valReg) begin  
-        spiDataR <= SPIdata;
-    end
-end
-
-
-always @(*) begin 
-    if (Rst_i) begin 
-        oldDataFlag = 1'b0;
-    end
-    else begin 
-        if (spiDataR == SPIdata) begin 
-            oldDataFlag = 1'b1;
-        end
-        else begin 
-            oldDataFlag = 1'b0;
+    
+    
+    
+    always @(posedge Clk_i) begin
+        if (valReg) begin  
+            spiDataR <= SpiData_i;
         end
     end
-end
-
-
-always @(posedge Clk_i) begin 
-    startR <= Start_i;
-end
-
-always @(*) begin 
-    if (Rst_i) begin 
-        valToRxFifo1 = 1'b0;
-    end
-    else begin 
-        if (Start_i && !startR) begin 
-            valToRxFifo1 = 1'b1;
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            oldDataFlag = 1'b0;
         end
         else begin 
-            valToRxFifo1 = 1'b0;
+            if (spiDataR == SpiData_i) begin 
+                oldDataFlag = 1'b1;
+            end
+            else begin 
+                oldDataFlag = 1'b0;
+            end
         end
     end
-end
-
-always @(negedge Clk_i) begin 
-    if (Rst_i) begin 
-        delayCnt <= 1'b0;
+    
+    
+    always @(posedge Clk_i) begin 
+        startR <= Start_i;
     end
-    else begin 
-        if (stopFlag &&delayCnt < Stop_i) begin 
-            delayCnt <= delayCnt + 1'b1;
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            valToRxFifo1 = 1'b0;
         end
         else begin 
-            delayCnt <= 1'b0;
-        end
-    end
-end
-
-always @(posedge Clk_i) begin 
-    if (Rst_i) begin 
-        stopFlag <= 1'b0;
-    end
-    else begin
-        if (SELST_i) begin 
-            if (ssPol && !ssR) begin 
-                stopFlag <= 1'b1;
+            if (Start_i && !startR) begin 
+                valToRxFifo1 = 1'b1;
             end
-            else if ( delayCnt == Stop_i) begin 
-                stopFlag <= 1'b0;
+            else begin 
+                valToRxFifo1 = 1'b0;
             end
         end
+    end
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            delayCnt <= 1'b0;
+        end
         else begin 
-            if (!ssPol && ssR) begin 
-                stopFlag <= 1'b1;
+            if (stopFlag &&delayCnt < Stop_i) begin 
+                delayCnt <= delayCnt + 1'b1;
             end
-            else if (delayCnt == Stop_i) begin 
-                stopFlag <= 1'b0;
+            else begin 
+                delayCnt <= 1'b0;
             end
         end
     end
-end
-
-
-
-
-always @(*) begin
-    if (SELST_i) begin 
-        if (PulsePol_i) begin 
-            if (CPHA_i) begin
-                if (LEAD_i == 0) begin 
-                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                        Sck_o = ~(~Clk_i);
-                    end
-                    else begin 
-                        Sck_o = 1'b0;
-                    end
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            stopFlag <= 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (ssPol && !ssR) begin 
+                    stopFlag <= 1'b1;
                 end
-                else begin 
-                    if (!Ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
-                        Sck_o = ~(~Clk_i);
-                    end
-                    else begin 
-                        Sck_o = 1'b0;
-                    end
+                else if ( delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
                 end
             end
-            else begin
-                if (LEAD_i == 0) begin 
-                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                        Sck_o = ~(Clk_i);
-                    end
-                    else begin 
-                        Sck_o = 1'b0;
-                    end
+            else begin 
+                if (!ssPol && ssR) begin 
+                    stopFlag <= 1'b1;
                 end
-                else begin 
-                    if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
-                        Sck_o = ~(Clk_i);
-                    end
-                    else begin 
-                        Sck_o = 1'b0;
-                    end
+                else if (delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
                 end
             end
         end
-        else begin 
-            if (CPHA_i) begin
-                if (LEAD_i == 0) begin  
-                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                        Sck_o = ~(Clk_i);
+    end
+    
+    
+    
+    
+    always @(*) begin
+        if (SelSt_i) begin 
+            if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                     else begin 
-                        Sck_o = 1'b0;
+                        if (!Ss && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                 end
-                else begin 
-                    if (!Ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
-                        Sck_o = ~(Clk_i);
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                     else begin 
-                        Sck_o = 1'b0;
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                 end
-            end 
-            else begin
-                if (LEAD_i == 0) begin 
-                    if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                        Sck_o = ~(~Clk_i);
+            end
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                     else begin 
-                        Sck_o = 1'b0;
-                    end
-                end
-                else begin 
-                    if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
-                        Sck_o = ~(~Clk_i);
+                        if (!Ss && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                     else begin 
-                        Sck_o = 1'b0;
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                 end
             end
         end
-    end
-    else begin 
-          if (PulsePol_i) begin 
-            if (CPHA_i) begin
-                if (LEAD_i == 0) begin 
-                    if (ssPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                        Sck_o = ~(~Clk_i);
+        else begin 
+              if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                     else begin 
-                        Sck_o = 1'b0;
+                        if (ssPol && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                 end
-                else begin 
-                    if (ssPol && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
-                        Sck_o = ~(~Clk_i);
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                     else begin 
-                        Sck_o = 1'b0;
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                 end
             end
-            else begin
-                if (LEAD_i == 0) begin 
-                    if (ssPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                        Sck_o = ~(Clk_i);
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                     else begin 
-                        Sck_o = 1'b0;
-                    end
-                end
-                else begin 
-                    if (ssPol && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
-                        Sck_o = ~(Clk_i);
+                        if (ssPol && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                     else begin 
-                        Sck_o = 1'b0;
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
                     end
                 end
             end
         end
-        else begin 
-            if (CPHA_i) begin
-                if (LEAD_i == 0) begin  
-                    if (ssPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                        Sck_o = ~(Clk_i);
-                    end
-                    else begin 
-                        Sck_o = 1'b0;
-                    end
+            
+    end
+    
+    
+    always @(*) begin
+        if (Rst_i) begin 
+            Mosi0_o = 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
                 end
                 else begin 
-                    if (ssPol && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
-                        Sck_o = ~(Clk_i);
-                    end
-                    else begin 
-                        Sck_o = 1'b0;
-                    end
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
                 end
-            end 
-            else begin
-                if (LEAD_i == 0) begin 
-                    if (ssPol && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
-                        Sck_o = ~(~Clk_i);
-                    end
-                    else begin 
-                        Sck_o = 1'b0;
-                    end
+            end
+            else begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
                 end
                 else begin 
-                    if (ssPol && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
-                        Sck_o = ~(~Clk_i);
-                    end
-                    else begin 
-                        Sck_o = 1'b0;
-                    end
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
                 end
             end
         end
     end
-        
-end
-
-
-always @(*) begin
-    if (Rst_i) begin 
-        Mosi0_o = 1'b0;
+    
+    
+    
+    always @(posedge Clk_i) begin
+        ssR <= ssPol;
+        SSR <= Ss;
     end
-    else begin
-        if (SELST_i) begin 
-            if (!EndianSel_i) begin 
-                case (WidthSel_i)  
-                    0 : begin
-                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
-                    end
-                    1 : begin
-                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
-                    end
-                    2 : begin
-                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
-                    end
-                    3 : begin
-                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
-                    end
-                endcase
-            end
-            else begin 
-                case (WidthSel_i)  
-                    0 : begin
-                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                    end
-                    1 : begin
-                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                    end
-                    2 : begin
-                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                    end
-                    3 : begin
-                        Mosi0_o = (!Ss&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                    end
-                endcase
-            end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            startFlag = 1'b0;
         end
         else begin 
-            if (!EndianSel_i) begin 
-                case (WidthSel_i)  
-                    0 : begin
-                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
-                    end
-                    1 : begin
-                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
-                    end
-                    2 : begin
-                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
-                    end
-                    3 : begin
-                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
-                    end
-                endcase
+            if (Start_i&& !stopFlag && SpiData_i != 0 && !oldDataFlag ) begin 
+                startFlag = 1'b1;
             end
             else begin 
-                case (WidthSel_i)  
-                    0 : begin
-                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                    end
-                    1 : begin
-                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                    end
-                    2 : begin
-                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                    end
-                    3 : begin
-                        Mosi0_o = (ssPol&& (ssCnt <= ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
-                    end
-                endcase
+                startFlag = 1'b0;
             end
         end
     end
-end
-
-
-
-always @(posedge Clk_i) begin
-    ssR <= ssPol;
-    SSR <= Ss;
-end
-
-
-always @(*) begin 
-    if (Rst_i) begin 
-        startFlag = 1'b0;
-    end
-    else begin 
-        if (Start_i&& !stopFlag && SPIdata != 0 && !oldDataFlag ) begin 
-            startFlag = 1'b1;
+    
+    always @(*) begin
+        if (SelSt_i) begin 
+            if (Ss_o && !ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
         end
         else begin 
-            startFlag = 1'b0;
+            if (!Ss_o&& ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
         end
     end
-end
-
-always @(*) begin
-    if (SELST_i) begin 
-        if (Ss_o && !ssR) begin 
-            valReg = 1'b1;
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            ssNum = 1'b0;
         end
         else begin 
-            valReg = 1'b0;
+            case (WidthSel_i) 
+                0 : begin 
+                    ssNum = 8;
+                end
+                1 : begin 
+                    ssNum = 16;
+                end
+                2 : begin 
+                    ssNum = 24;
+                end
+                3 : begin 
+                    ssNum = 32;
+                end
+            endcase
         end
     end
-    else begin 
-        if (!Ss_o&& ssR) begin 
-            valReg = 1'b1;
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            ssCnt <= 1'b0;
         end
-        else begin 
-            valReg = 1'b0;
+        else if (ssCnt < (ssNum+Lag_i+Lead_i)  && startFlag  ) begin 
+            ssCnt <= ssCnt + 1'b1;
         end
-    end
-end
-
-
-always @(*) begin 
-    if (Rst_i) begin 
-        ssNum = 1'b0;
-    end
-    else begin 
-        case (WidthSel_i) 
-            0 : begin 
-                ssNum = 8;
-            end
-            1 : begin 
-                ssNum = 16;
-            end
-            2 : begin 
-                ssNum = 24;
-            end
-            3 : begin 
-                ssNum = 32;
+        else begin
+            if (ssCnt == ssNum-1 || !startFlag) begin 
+                ssCnt <= 1'b0;
             end
-        endcase
-    end
-end
-
-
-always @(negedge Clk_i) begin 
-    if (Rst_i) begin 
-        ssCnt <= 1'b0;
-    end
-    else if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag  ) begin 
-        ssCnt <= ssCnt + 1'b1;
-    end
-    else begin
-        if (ssCnt == ssNum-1 || !startFlag) begin 
-            ssCnt <= 1'b0;
         end
     end
-end
-
-
-
-
-always @(negedge Clk_i) begin 
-    if (Rst_i) begin 
-        Ss <= 1'b1;
-    end
-    else begin 
-        if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag ) begin 
-            Ss <= 1'b0;
-        end
-        else begin 
+    
+    
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
             Ss <= 1'b1;
         end
-    end
-end
-
-
-always @(negedge Clk_i) begin 
-    if (Rst_i) begin 
-        mosiReg0 <= SPIdata[31:0];
-    end
-    else begin
-        if (!EndianSel_i) begin 
-            if (!SSR && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
-                mosiReg0 <= mosiReg0 << 1;
+        else begin 
+            if (ssCnt < (ssNum+Lag_i+Lead_i)  && startFlag ) begin 
+                Ss <= 1'b0;
             end
             else begin 
-                mosiReg0 <= SPIdata[31:0];
+                Ss <= 1'b1;
             end
         end
-        else begin 
-            if (!SSR && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
-                mosiReg0 <= mosiReg0 >> 1;
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg0 <= SpiData_i[31:0];
+        end
+        else begin
+            if (!EndianSel_i) begin 
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 << 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
             end
             else begin 
-                mosiReg0 <= SPIdata[31:0];
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 >> 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
             end
         end
     end
-end
-
-
-
-
-
-
-
-endmodule
+    
+    
+    
+    
+    
+    
+    
+    endmodule

sources_1/new/SpiR/SPIs.v

@@ -7,7 +7,7 @@ module SPIs (
     input Mosi0_i,
     input [1:0] WidthSel_i,
     input EndianSel_i,
-    input SELST_i,
+    input SelSt_i,
    
 
     output reg [23:0] Data_o,
@@ -20,159 +20,159 @@ module SPIs (
 //	REG/WIRE
 //================================================================================
 
-reg ssReg;
-reg ssRegR;  
-reg [31:0] shiftReg;
-
-reg [31:0] shiftRegM; 
+    reg ssReg;
+    reg ssRegR;  
+    reg [31:0] shiftReg;
+    
+    reg [31:0] shiftRegM; 
  
 
 //===============================================================================
 //  ASSIGNMENTS
 
 
-assign DataToRxFifo_o = {Addr_o, Data_o};
+    assign DataToRxFifo_o = {Addr_o, Data_o};
 
 //================================================================================
 //	CODING
 //================================================================================
 
-always	@(posedge	Clk_i)	begin
-	ssReg	<=	Ss_i;
-	ssRegR	<=	ssReg;
-end
+    always	@(posedge	Clk_i)	begin
+    	ssReg	<=	Ss_i;
+    	ssRegR	<=	ssReg;
+    end
 
 
-always @(*) begin 
-    if (Rst_i) begin
-      shiftRegM = 32'h0;
-    end
-    else begin 
-        case(WidthSel_i)  
-             0: begin 
-                shiftRegM = shiftReg[7:0];
-            end
-            1: begin 
-                shiftRegM = shiftReg[15:0];
-            end
-            2: begin 
-                shiftRegM = shiftReg[23:0];
-            end
-            3: begin 
-                shiftRegM = shiftReg[31:0];
-            end
-        endcase
+    always @(*) begin 
+        if (Rst_i) begin
+          shiftRegM = 32'h0;
+        end
+        else begin 
+            case(WidthSel_i)  
+                 0: begin 
+                    shiftRegM = shiftReg[7:0];
+                end
+                1: begin 
+                    shiftRegM = shiftReg[15:0];
+                end
+                2: begin 
+                    shiftRegM = shiftReg[23:0];
+                end
+                3: begin 
+                    shiftRegM = shiftReg[31:0];
+                end
+            endcase
+        end
     end
-end
 
 
 
-always @(posedge Clk_i) begin 
-    if (Rst_i) begin 
-        Data_o <= 24'h0;
-    end
-    else begin
-        if (SELST_i) begin  
-            if (ssReg && !ssRegR) begin 
-                Data_o <= shiftRegM;
-            end
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            Data_o <= 24'h0;
         end
-        else begin 
-            if (!ssReg && ssRegR) begin 
-                Data_o <= shiftRegM[23:0];
+        else begin
+            if (SelSt_i) begin  
+                if (ssReg && !ssRegR) begin 
+                    Data_o <= shiftRegM;
+                end
+            end
+            else begin 
+                if (!ssReg && ssRegR) begin 
+                    Data_o <= shiftRegM[23:0];
+                end
             end
         end
     end
-end
 
-always @(posedge Clk_i) begin 
-    if (Rst_i) begin 
-        Addr_o <= 8'h0;
-    end
-    else begin
-        if (SELST_i) begin 
-            if (ssReg && !ssRegR) begin 
-                Addr_o <= shiftRegM[31:24];
-            end
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            Addr_o <= 8'h0;
         end
-        else begin 
-            if (!ssReg && ssRegR) begin 
-                Addr_o <= shiftRegM[31:24];
+        else begin
+            if (SelSt_i) begin 
+                if (ssReg && !ssRegR) begin 
+                    Addr_o <= shiftRegM[31:24];
+                end
+            end
+            else begin 
+                if (!ssReg && ssRegR) begin 
+                    Addr_o <= shiftRegM[31:24];
+                end
             end
         end
     end
-end
 
 
 
 
-always @(posedge Sck_i or posedge Rst_i) begin 
-    if (Rst_i) begin 
-        shiftReg<= 32'h0;
-    end
-    else begin
-        if (!EndianSel_i) begin 
-            if (SELST_i) begin   
-                if (!Ss_i) begin 
-                    shiftReg<= {shiftReg[30:0], Mosi0_i};
-                end
-                else begin 
-                    shiftReg<= 32'h0;
-                end
-            end
-            else begin 
-                if (Ss_i) begin 
-                    shiftReg<= {shiftReg[30:0], Mosi0_i};
-                end
-                else begin 
-                    shiftReg<= 32'h0;
-                end
-            end
+    always @(posedge Sck_i or posedge Rst_i) begin 
+        if (Rst_i) begin 
+            shiftReg<= 32'h0;
         end
-        else begin 
-            if (SELST_i) begin   
-                if (!Ss_i) begin 
-                    shiftReg<= {Mosi0_i, shiftReg[31:1]};
+        else begin
+            if (!EndianSel_i) begin 
+                if (SelSt_i) begin   
+                    if (!Ss_i) begin 
+                        shiftReg<= {shiftReg[30:0], Mosi0_i};
+                    end
+                    else begin 
+                        shiftReg<= 32'h0;
+                    end
                 end
                 else begin 
-                    shiftReg<= 32'h0;
+                    if (Ss_i) begin 
+                        shiftReg<= {shiftReg[30:0], Mosi0_i};
+                    end
+                    else begin 
+                        shiftReg<= 32'h0;
+                    end
                 end
             end
             else begin 
-                if (Ss_i) begin 
-                    shiftReg<= {Mosi0_i, shiftReg[31:1]};
+                if (SelSt_i) begin   
+                    if (!Ss_i) begin 
+                        shiftReg<= {Mosi0_i, shiftReg[31:1]};
+                    end
+                    else begin 
+                        shiftReg<= 32'h0;
+                    end
                 end
                 else begin 
-                    shiftReg<= 32'h0;
+                    if (Ss_i) begin 
+                        shiftReg<= {Mosi0_i, shiftReg[31:1]};
+                    end
+                    else begin 
+                        shiftReg<= 32'h0;
+                    end
                 end
             end
         end
     end
-end
 
 
 
 
-always @(posedge Clk_i) begin
-    if (SELST_i) begin 
-        if (ssReg && !ssRegR) begin 
-            Val_o <= 1'b1;
-        end
-        else begin 
-            Val_o <= 1'b0;
-        end
-    end
-    else begin 
-        if (!ssReg&& ssRegR) begin 
-            Val_o <= 1'b1;
+    always @(posedge Clk_i) begin
+        if (SelSt_i) begin 
+            if (ssReg && !ssRegR) begin 
+                Val_o <= 1'b1;
+            end
+            else begin 
+                Val_o <= 1'b0;
+            end
         end
         else begin 
-            Val_o <= 1'b0;
+            if (!ssReg&& ssRegR) begin 
+                Val_o <= 1'b1;
+            end
+            else begin 
+                Val_o <= 1'b0;
+            end
         end
     end
-end
 
 
 
 
-endmodule
+    endmodule